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| * net: phy: xgene: disable clk on error pathsAlexey Khoroshilov2017-12-181-6/+15
| | | | | | | | | | | | | | | | | | | | There are several error paths in xgene_mdio_probe(), where clk is left undisabled. The patch fixes them. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: phy: marvell: avoid pause mode on SGMII-to-Copper for 88e151xRussell King2017-12-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Observed on the 88e1512 in SGMII-to-Copper mode, negotiating pause is unreliable. While the pause bits can be set in the advertisment register, they clear shortly after negotiation with a link partner commences irrespective of the cause of the negotiation. While these bits may be correctly conveyed to the link partner on the first negotiation, a subsequent negotiation (eg, due to negotiation restart by the link partner, or reconnection of the cable) will result in the link partner seeing these bits as zero, while the kernel believes that it has advertised pause modes. This leads to the local kernel evaluating (eg) symmetric pause mode, while the remote end evaluates that we have no pause mode capability. Since we can't guarantee the advertisment, disable pause mode support with this PHY when used in SGMII-to-Copper mode. The 88e1510 in RGMII-to-Copper mode appears to behave correctly. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: phy: marvell: Limit 88m1101 autoneg errata to 88E1145 as well.Zhao Qiang2017-12-181-1/+1
| | | | | | | | | | | | | | | | 88E1145 also need this autoneg errata. Fixes: f2899788353c ("net: phy: marvell: Limit errata to 88m1101") Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: avoid attaching more than one PHYRussell King2017-12-211-0/+3
| | | | | | | | | | | | | | | | | | | | Attaching more than one PHY to phylink is bad news, as we store a pointer to the PHY in a single location. Error out if more than one PHY is attempted to be attached. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: fix locking assertsRussell King2017-12-181-17/+17
| | | | | | | | | | | | | | | | | | Use ASSERT_RTNL() rather than WARN_ON(!lockdep_rtnl_is_held()) which stops working when lockdep fires, and we end up with lots of warnings. Fixes: 9525ae83959b ("phylink: add phylink infrastructure") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
* | sfp: fix EEPROM reading in the case of non-SFF8472 SFPsRussell King2017-12-181-4/+3
| | | | | | | | | | | | | | | | | | | | | | The EEPROM reading was trying to read from the second EEPROM address if we requested the last byte from the SFF8079 EEPROM, which caused a failure when the second EEPROM is not present. Discovered with a S-RJ01 SFP module. Fix this. Fixes: 73970055450e ("sfp: add SFP module support") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
* | sfp: fix non-detection of PHYRussell King2017-12-181-4/+4
| | | | | | | | | | | | | | | | | | | | The detection of a PHY changed in commit e98a3aabf85f ("mdio_bus: don't return NULL from mdiobus_scan()") which now causes sfp to print an error message. Update for this change. Fixes: 73970055450e ("sfp: add SFP module support") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: meson-gxl: join the authorsJerome Brunet2017-12-181-0/+1
| | | | | | | | | | | | | | | | | | Following previous changes, join the other authors of this driver and take the blame with them Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: meson-gxl: add interrupt supportJerome Brunet2017-12-181-1/+36
| | | | | | | | | | | | | | Enable interrupt support in meson-gxl PHY driver Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: meson-gxl: leave CONFIG_A6 untouchedJerome Brunet2017-12-181-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PHY performs just as well when left in its default configuration and it makes senses because this poke gets reset just after init. According to the documentation, all registers in the Analog/DSP bank are reset when there is a mode switch from 10BT to 100BT. The bank is also reset on power down and soft reset, so we will never see the value which may have been set by the bootloader. In the end, we have used the default configuration so far and there is no reason to change now. Remove CONFIG_A6 poke to make this clear. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: meson-gxl: use genphy_config_initJerome Brunet2017-12-181-1/+1
| | | | | | | | | | | | | | | | | | Use the generic init function to populate some of the phydev structure fields Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: meson-gxl: add read and write helpers for banked registersJerome Brunet2017-12-181-61/+69
| | | | | | | | | | | | | | | | | | | | Add read and write helpers to manipulate banked registers on this PHY This helps clarify the settings applied to these registers and what the driver actually does Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: meson-gxl: define control registersJerome Brunet2017-12-181-20/+66
| | | | | | | | | | | | | | | | | | Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: meson-gxl: check phy_write return valueJerome Brunet2017-12-181-12/+38
| | | | | | | | | | | | | | | | Always check phy_write return values. Better to be safe than sorry Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2017-12-166-14/+87
|\| | | | | | | | | | | | | Three sets of overlapping changes, two in the packet scheduler and one in the meson-gxl PHY driver. Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: phy: marvell: avoid configuring fiber page for SGMII-to-CopperRussell King2017-12-131-0/+4
| | | | | | | | | | | | | | | | | | | | When in SGMII-to-Copper mode, the fiber page is used for the MAC facing link, and does not require configuration of the fiber auto-negotiation settings. Avoid trying. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: phy: meson-gxl: make function meson_gxl_read_status staticColin Ian King2017-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The function meson_gxl_read_status is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'meson_gxl_read_status' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * of_mdio / mdiobus: ensure mdio devices have fwnode correctly populatedRussell King2017-12-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | Ensure that all mdio devices populate the struct device fwnode pointer as well as the of_node pointer to allow drivers that wish to use fwnode APIs to work. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: phy: fix resume handlingRussell King2017-12-133-14/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a PHY has the BMCR_PDOWN bit set, it may decide to ignore writes to other registers, or reset the registers to power-on defaults. Micrel PHYs do this for their interrupt registers. The current structure of phylib tries to enable interrupts before resuming (and releasing) the BMCR_PDOWN bit. This fails, causing Micrel PHYs to stop working after a suspend/resume sequence if they are using interrupts. Fix this by ensuring that the PHY driver resume methods do not take the phydev->lock mutex themselves, but the callers of phy_resume() take that lock. This then allows us to move the call to phy_resume() before we enable interrupts in phy_start(). Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: phy: meson-gxl: detect LPA corruptionJerome Brunet2017-12-111-1/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The purpose of this change is to fix the incorrect detection of the link partner (LP) advertised capabilities which sometimes happens with this PHY (roughly 1 time in a dozen) This issue may cause the link to be negotiated at 10Mbps/Full or 10Mbps/Half when 100MBps/Full is actually possible. In some case, the link is even completely broken and no communication is possible. To detect the corruption, we must look for a magic undocumented bit in the WOL bank (hint given by the SoC vendor kernel) but this is not enough to cover all cases. We also have to look at the LPA ack. If the LP supports Aneg but did not ack our base code when aneg is completed, we assume something went wrong. The detection of a corrupted LPA triggers a restart of the aneg process. This solves the problem but may take up to 6 retries to complete. Fixes: 7334b3e47aee ("net: phy: Add Meson GXL Internal PHY driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: broadcom: Add entry for 5395 switch PHYsFlorian Fainelli2017-12-151-0/+42
| | | | | | | | | | | | | | | | | | Add an entry for the builtin PHYs present in the Broadcom BCM5395 switch. This allows us to retrieve the PHY statistics among other things. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Chris Healy <cphealy@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: phylink: Handle NULL fwnode_handleFlorian Fainelli2017-12-151-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the various of_* routines to fetch properties, fwnode_* routines can have an early check against a NULL fwnode_handle reference which makes them return -EINVAL (see fwnode_call_int_op), thus making it virtually impossible to differentiate what type of error is going on. Have an early check in phylink_register_sfp() so we can keep proceeding with the initialization, there is not much we can do without a valid fwnode_handle except return early and treat this similarly to -ENOENT. Fixes: 8fa7b9b6af25 ("phylink: convert to fwnode") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
* | sfp: add sff module supportRussell King2017-12-151-14/+64
| | | | | | | | | | | | | | | | | | | | Add support for SFF modules, which are soldered down SFP modules. These have a different phys_id value, and also have the present and rate select signals omitted compared with their socketed counter-parts. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: phylink: Report MoCA as PORT_BNCFlorian Fainelli2017-12-131-1/+4
| | | | | | | | | | | | | | | | | | Similarly to what PHYLIB already does, make sure that PHY_INTERFACE_MODE_MOCA is reported as PORT_BNC. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: phylink: Allow setting a custom link state callbackFlorian Fainelli2017-12-131-2/+32
| | | | | | | | | | | | | | | | | | | | | | phylink_get_fixed_state() currently consults an optional "link_gpio" GPIO descriptor, expand this mechanism to allow specifying a custom callback. This is necessary to support out of band link notifcation (e.g: from an interrupt within a MMIO register). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: phylink: Remove error messageFlorian Fainelli2017-12-131-3/+1
| | | | | | | | | | | | | | | | | | | | Some subsystems like DSA may be trying to connect to a PHY through OF first, and then attempt a connect using a local MDIO bus, remove the error message: "unable to find PHY node" so we can let MAC drivers whether to print it or not. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: phylink: Use PHY device interface if N/AFlorian Fainelli2017-12-131-0/+6
| | | | | | | | | | | | | | | | | | We may not always be able to resolve a correct phy_interface_t value before actually connecting to the PHY device, when that happens, just have phylink_connect_phy() utilize what the PHY device/driver provided. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: phylink: Allow specifying PHY device flagsFlorian Fainelli2017-12-131-2/+5
| | | | | | | | | | | | | | | | | | | | In order to let subsystems like DSA fully utilize PHYLINK, we need to be able to communicate phy_device::flags from of_phy_{connect,attach} even when using PHYLINK APIs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: marvell10g: remove XGMII as an option for 88x3310Russell King2017-12-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | Remove XGMII as an option for the 88x3310 PHY driver, as the PHY doesn't support XGMII's 32-bit data lanes. It supports USXGMII, which is not XGMII, but a single-lane serdes interface - see https://developer.cisco.com/site/usgmii-usxgmii/ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: phy: smsc: LAN8710/20: add PHY_RST_AFTER_CLK_EN flagRichard Leitner2017-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The Microchip/SMSC LAN8710/LAN8720 PHYs need (according to their datasheet [1]) a continuous REF_CLK when configured to "REF_CLK In Mode". Therefore set the PHY_RST_AFTER_CLK_EN flag for those PHYs to let the ETH driver reset them after the REF_CLK is enabled. [1] http://ww1.microchip.com/downloads/en/DeviceDoc/00002165B.pdf Signed-off-by: Richard Leitner <richard.leitner@skidata.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylib: add reset after clk enable supportRichard Leitner2017-12-131-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PHYs need the refclk to be a continuous clock. Therefore they don't allow turning it off and on again during operation. Nonetheless such a clock switching is performed by some ETH drivers (namely FEC [1]) for power saving reasons. An example for an affected PHY is the SMSC/Microchip LAN8720 in "REF_CLK In Mode". In order to provide a uniform method to overcome this problem this patch adds a new phy_driver flag (PHY_RST_AFTER_CLK_EN) and corresponding function phy_reset_after_clk_enable() to the phylib. These should be used to trigger reset of the PHY after the refclk is switched on again. [1] commit e8fcfcd5684a ("net: fec: optimize the clock management to save power") Signed-off-by: Richard Leitner <richard.leitner@skidata.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylib: Add device reset delay supportRichard Leitner2017-12-131-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | Some PHYs need a minimum time after the reset gpio was asserted and/or deasserted. To ensure we meet these timing requirements add two new optional devicetree parameters for the phy: reset-delay-us and reset-post-delay-us. Signed-off-by: Richard Leitner <richard.leitner@skidata.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylib: Add device reset GPIO supportSergei Shtylyov2017-12-054-19/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PHY devices sometimes do have their reset signal (maybe even power supply?) tied to some GPIO and sometimes it also does happen that a boot loader does not leave it deasserted. So far this issue has been attacked from (as I believe) a wrong angle: by teaching the MAC driver to manipulate the GPIO in question; that solution, when applied to the device trees, led to adding the PHY reset GPIO properties to the MAC device node, with one exception: Cadence MACB driver which could handle the "reset-gpios" prop in a PHY device subnode. I believe that the correct approach is to teach the 'phylib' to get the MDIO device reset GPIO from the device tree node corresponding to this device -- which this patch is doing... Note that I had to modify the AT803x PHY driver as it would stop working otherwise -- it made use of the reset GPIO for its own purposes... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> [geert: Propagate actual errors from fwnode_get_named_gpiod()] [geert: Avoid destroying initial setup] [geert: Consolidate GPIO descriptor acquiring code] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Richard Leitner <richard.leitner@skidata.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: convert to fwnodeRussell King2017-12-051-38/+53
| | | | | | | | | | | | | | | | | | | | Convert phylink to fwnode, switching phylink_create() from taking a device_node to taking a fwnode_handle. This will allow other firmware systems to take advantage of sfp/phylink support. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | sfp: convert to fwnodeRussell King2017-12-052-8/+9
| | | | | | | | | | | | | | | | | | Convert sfp-bus to use fwnode rather than device_node internally, so we can support more than just device tree firmware. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | sfp: fix sparse warningRussell King2017-12-051-1/+1
| | | | | | | | | | | | | | | | drivers/net/phy/sfp-bus.c:298:13: warning: context imbalance in 'sfp_bus_release' - wrong count at exit Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | sfp: add documentation for kernel APIsRussell King2017-12-051-0/+104
| | | | | | | | | | | | | | | | | | Add kernel-doc documentation for sfp kernel APIs, and link it into the networking kapi documentation under "Network device support". Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: add documentation for kernel APIsRussell King2017-12-051-0/+182
| | | | | | | | | | | | | | | | | | Add kernel-doc documentation for phylink kernel APIs, and link it into the networking kapi documentation under "Network device support". Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: restart 802.3z negotiation when starting net deviceRussell King2017-12-051-0/+6
| | | | | | | | | | | | | | | | | | Restart 802.3z negotiation when the net device is brought up to ensure that the link partner has our current link modes. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: remove phylink_init_eee()Russell King2017-12-051-13/+0
| | | | | | | | | | | | | | | | phylink_init_eee() serves no purpose, remove it. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: add support for 2500baseX and 10GbaseKRRussell King2017-12-051-0/+2
| | | | | | | | | | | | | | | | | | Add support for handling the faster 2.5G and 10G link modes when used with SFP modules. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: get rid of separate Cisco SGMII and 802.3z modesRussell King2017-12-051-25/+14
| | | | | | | | | | | | | | | | | | | | Since the handling of SGMII and 802.3z is now the same, combine the MLO_AN_xxx constants into a single MLO_AN_INBAND, and use the PHY interface mode to distinguish between Cisco SGMII and 802.3z. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phylink: merge SGMII and 802.3z handlingRussell King2017-12-051-7/+9
| | | | | | | | | | | | | | | | | | | | | | The code handling SGMII and 802.3z is essentially the same, except that we assume 802.3z has no PHY. Re-organise the code such that these cases are merged, and exclude 802.3z mode from having a PHY attached. This results in the same link handling behaviour as before. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | phy: add phy_interface_mode_is_8023z() helperRussell King2017-12-051-2/+1
| | | | | | | | | | | | | | | | | | | | Add and use phy_interface_mode_is_8023z() helper to identify the interface modes that use 802.3z negotiation. Use it in phylink's phylink_mac_an_restart(). Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2017-12-053-13/+35
|\| | | | | | | | | | | | | Small overlapping change conflict ('net' changed a line, 'net-next' added a line right afterwards) in flexcan.c Signed-off-by: David S. Miller <davem@davemloft.net>
| * phylink: ensure we take the link down when phylink_stop() is calledRussell King2017-12-011-0/+1
| | | | | | | | | | | | | | | | | | | | Ensure that we tell the MAC to take the link down when phylink_stop() is called, and that this completes prior to phylink_stop() returns. Reported-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
| * sfp: warn about modules requiring address change sequenceRussell King2017-12-011-1/+7
| | | | | | | | | | | | | | | | | | We do not support SFP modules which require the address change sequence as detailed by SFF 8472 revision 1.22 section 8.9. Warn when these modules are inserted, and treat them as SFF8079 modules for ethtool. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
| * sfp: improve RX_LOS handlingRussell King2017-12-011-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two bits in the option word for the RX_LOS signal. One reports that the RX_LOS signal is active high, the other reports that it is active low. When both or neither are set, the result is not well defined in the specification. Rather than assuming that neither set means normal RX_LOS, take this as meaning no RX_LOS signal available, thereby ignoring the signal. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
| * sfp: fix RX_LOS signal handlingRussell King2017-12-011-3/+5
| | | | | | | | | | | | | | | | | | | | | | The options word is a be16 quantity, so we need to test the flags having converted the endian-ness. Convert the flag bits to be16, which can be optimised by the compiler, rather than converting a variable at runtime. Reported-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
| * net: phy-micrel: check return code in flp center functionMax Uvarov2017-12-011-2/+4
| | | | | | | | | | | | | | Fix obvious typo that first return value is set but not checked. Signed-off-by: Max Uvarov <muvarov@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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