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path: root/drivers/net/wireless/ath/ath10k/hw.h
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* ath10k: add new hw_ops for sdio chipWen Gong2019-06-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It report error message while suspend/resume test. dmesg log: [ 150.749962] ath10k_sdio mmc1:0001:1: hif read32 not supported [ 150.755728] ath10k_sdio mmc1:0001:1: failed to set coverage class: expected integer microsecond value in register Reason is sdio chip does not support set_coverage_class as well as pcie chip, remove the set_coverage_class handler will avoid it. callstack of the error message: OUTLINED_FUNCTION_6+0xc/0x14 [ath10k_core] ath10k_mac_op_set_coverage_class+0x2c/0x40 [ath10k_core] ieee80211_reconfig+0x5d0/0x108c [mac80211] ieee80211_resume+0x34/0x6c [mac80211] wiphy_resume+0xbc/0x13c [cfg80211] dpm_run_callback+0xa4/0x168 device_resume+0x1d4/0x200 async_resume+0x1c/0x34 async_run_entry_fn+0x48/0xf8 process_one_work+0x178/0x2f8 worker_thread+0x1d8/0x2cc kthread+0x11c/0x12c ret_from_fork+0x10/0x18 the error log will not happen after this patch applied. Tested with QCA6174 SDIO with firmware WLAN.RMH.4.4.1-00007-QCARMSWP-1. Signed-off-by: Wen Gong <wgong@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: enabling tx stats support over pktlogBalaji Pothunoori2019-06-251-0/+3
| | | | | | | | | | | | | | | | | | | For QCA988X target, pktlog gives details of the tx bitrate which is used in the driver for station info. Enabling pktlog by default will cause more interrupts in target to host CE pipe, which can impact more CPU usage for targets ex:WCN3990 and also not required for all other platforms (eg: WCN3990), for getting tx bitrate. Enable pktlog only for QCA988X based on hardware params. Tested HW : WCN3990 Tested FW : WLAN.HL.3.1-00784-QCAHLSWMTPLZ-1 Fixes: e8123bb74c4e ("ath10k: add per peer tx stats support for 10.2.4") Signed-off-by: Balaji Pothunoori <bpothuno@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: change firmware file name for UTF mode of SDIO/USBWen Gong2019-06-251-0/+2
| | | | | | | | | | | | | | | Firmware name for UTF mode of SDIO has changed from utf-2.bin to utf-sdio-2.bin, so it need to change in ath10k, otherwise it will fail for UTF mode. After change the name in ath10k, it will success for UTF mode of SDIO/USB. Tested with QCA6174 SDIO with firmware WLAN.RMH.4.4.1-00007-QCARMSWP-1. Signed-off-by: Wen Gong <wgong@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: add support for firmware crash recovery on SDIO chipWen Gong2019-06-251-0/+1
| | | | | | | | | | | | | | | | | | | The command to simulate firmware crash: echo soft > /sys/kernel/debug/ieee80211/phy0/ath10k/simulate_fw_crash It will send WMI_FORCE_FW_HANG_ASSERT to firmware, then it will trigger CPU interrupt status register for SDIO chip, ath10k driver need to configure it while enable SDIO interrupt, otherwise ath10k driver will not get the assert error info. After this change, it will success for simulate firmware crash. Tested with QCA6174 SDIO with firmware WLAN.RMH.4.4.1-00007-QCARMSWP-1. Signed-off-by: Wen Gong <wgong@codeaurora.org> Tested-by: Claire Chang <tientzu@chromium.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: enable QCA6174 hw3.2 SDIO hardwareWen Gong2019-04-291-0/+1
| | | | | | | | | | | | | | After implementing PN replay check we can enable SDIO support on QCA6174. Tested with client mode on all security modes, and fragmentation as well. AP mode does not work yet. Also tone down the warning about SDIO being not ready yet. Tested on QCA6174 SDIO with firmware WLAN.RMH.4.4.1-00007-QCARMSWP-1. AP mode is not working yet. Signed-off-by: Wen Gong <wgong@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: sdio: workaround firmware UART pin configuration bugWen Gong2019-04-231-0/+5
| | | | | | | | | | | | | | On QCA6174 SDIO devices the SDIO interrupt will fail if UART is disabled from ath10k. SDIO firmware enables UART printouts by default. If ath10k will try to enable UART again the firmware will configure it's GPIO line incorrectly and SDIO interrupts won't work anymore. The workaround is to set UART pin again (19 for QCA6174 SDIO) if uart_print is 0. Tested with QCA6174 SDIO with firmware WLAN.RMH.4.4.1-00007-QCARMSWP-1. Signed-off-by: Wen Gong <wgong@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: update the max num of peers supported for WCN3990Abhishek Ambure2019-02-261-3/+3
| | | | | | | | | | | | WCN3990 firmware versions WLAN.HL.2.0-01617-QCAHLSWMTPLZ-1 & onwards supports maximum 33 peers including self peer. To support maximum peers, send updated peer param to firmware during initialization. Tested HW: WCN3990 Tested FW: WLAN.HL.3.1-00784-QCAHLSWMTPLZ-1 Signed-off-by: Abhishek Ambure <aambure@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: add support for ack rssi value of data tx packetsAbhishek Ambure2019-02-261-0/+22
| | | | | | | | | | | | | | | | In WCN3990, WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI service Indicates that the firmware has the capability to send the RSSI value of the ACK for all data and management packets transmitted. If WMI_RSRC_CFG_FLAG_TX_ACK_RSSI is set in host capability then firmware sends RSSI value in "data" tx completion event. Host extracts ack rssi values of data packets from their tx completion event. Tested HW: WCN3990 Tested FW: WLAN.HL.2.0-01617-QCAHLSWMTPLZ-1 Signed-off-by: Abhishek Ambure <aambure@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: switch to use SPDX license identifiersKalle Valo2019-02-201-12/+1
| | | | | | | | | Use SPDX identifiers everywhere in ath10k. Makefile was incorrectly marked in commit b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license"), fix that as well. Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: reduce transmit msdu countAlagu Sankar2019-02-071-0/+1
| | | | | | | | | | | | | | | | | Reduce the transmit MSDU count for SDIO, to match with the descriptors as used by the firmware. This also acts as a high watermark level for transmit. Too many packets to the firmware results in transmit overflow interrupt. It only affect SDIO chip, it will not cause functionaly changes to other hardware. Tested with QCA6174 SDIO with firmware WLAN.RMH.4.4.1-00005-QCARMSWP-1. Signed-off-by: Alagu Sankar <alagusankar@silex-india.com> Signed-off-by: Wen Gong <wgong@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: Set DMA address mask to 35 bit for WCN3990Rakesh Pillai2019-02-041-2/+4
| | | | | | | | | | | | | | | | | | | | | WCN3990 is a 37-bit target but can address memory range only upto 35 bits. The 36th bit is used to control the smmu/iommu translation and the 37th bit is used by the internal bus masters to access the wifi subsystem internal SRAM. With the DMA mask set to 37i-bit, the host driver can get 37-bit dma address, which leads to incorrect address access in the target. Hence the host driver can used addresses upto 35-bit for WCN3990. Fix the dma mask for wcn3990 to 35-bit, instead of 37-bit. Tested HW: WCN3990 Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1 Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: fix warning due to msdu limit errorBhagavathi Perumal S2018-12-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some hardwares variants (QCA99x0) are limiting msdu deaggregation with some threshold value(default limit in QCA99x0 is 64 msdus), it was introduced to avoid excessive MSDU-deaggregation in error cases. When number of sub frames exceeds the limit, target hardware will send all msdus starting from present msdu in RAW format as a single msdu packet and it will be indicated with error status bit "RX_MSDU_END_INFO0_MSDU_LIMIT_ERR" set in rx descriptor. This msdu frame is a partial raw MSDU and does't have first msdu and ieee80211 header. It caused below warning message. [ 320.151332] ------------[ cut here ]------------ [ 320.155006] WARNING: CPU: 0 PID: 3 at drivers/net/wireless/ath/ath10k/htt_rx.c:1188 In our issue case, MSDU limit error happened due to FCS error and generated this warning message. This fixes the warning by handling the MSDU limit error. If msdu limit error happens, driver adds first MSDU's ieee80211 header and sets A-MSDU present bit in QOS header so that upper layer processes this frame if it is valid or drop it if FCS error set. And removed the warning message, hence partial msdus without first msdu is expected in msdu limit error cases. Tested on QCA9984, Firmware 10.4-3.6-00104 Signed-off-by: Bhagavathi Perumal S <bperumal@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: add bus type check in ath10k_init_hw_paramsErik Stromdahl2018-09-061-0/+9
| | | | | | | | | | | | The bus type is used together with the other hw parameters to find a matching entry in ath10k_hw_params_list for the device. This is necessary since HL devices can have the same dev_id and target_version as a corresponding LL device (same chipset) and yet use a totally different configuration. Signed-off-by: Erik Stromdahl <erik.stromdahl@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: download firmware via diag Copy Engine for QCA6174 and QCA9377.Carl Huang2018-09-061-0/+19
| | | | | | | | | | | | | | | | | | Downloading firmware via BMI protocol takes too long time. For example, a ~700K bytes firmware takes about 500ms to download via BMI protocol. This is too long especially in suspend and resume scenario where firmware is re-downloaded unless WoWLAN is enabled. Downloading firmware via diag CE can reduce the time to ~40ms for a ~700K bytes firmware binary. Ath10k driver parses the firmware to segments and downloads the segments to the specified address directly. If the firmware is compressed or has unsupported segments, ath10k driver will try BMI download again. It's tested with QCA6174 hw3.2 and firmware-6.bin_WLAN.RM.4.4.1-00111-QCARMSWP-1. QCA9377 is also affected. Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: support extended board data download for dual-band QCA9984Sathishkumar Muruganandam2018-09-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support dual-band variant of QCA9984, new extended board data (eBDF) is introduced since existing board data ran out of space. Below is the brief implementation & design detail, ---------------------------------------------------- 1. New OTP changes to inform eBDF support in existing OTP download to fetch board ID and chip ID. This is backward compatible and older card sends 0 by default for eBDF support bit (bit 18 of OTP response) we check in ath10k driver. 2. If eBDF is supported, then we need to fetch eBDF ID which is bundled in downloaded board data. So again OTP is executed for knowing the eBDF ID. This is done once we set 'board_data_initialized' bit. If eBDF ID returned is zero, we continue booting with previous board data downloaded. 3. Based on the eBDF ID fetched, ath10k driver tries to download the extended board data to a new offset ahead of already downloaded board data address. 4. A new BD IE type, ATH10K_BD_IE_BOARD_EXT is added to differentiate in bundling eBDF separately in board-2.bin and also to parse through board bundle for eBDF download in ath10k boot. 5. If eBDF is not present in the board-2.bin bundle or when board ID is zero, we do a fallback boot to "eboard.bin" in the same QCA9984/hw1.0 dir. This is same as done to existing "board.bin" if board ID is not present in board-2.bin bundle. Current design is that eBDF size will be 2KB and eBDF ID will be byte value. Tested the above changes with dual-band variant of QCA9984 card. OTP update needed for the test will be part of next FW release 10.4-3.6-xxxx. Below are the logs with ath10k BOOT debugs enabled. First OTP response : --------------------- .. boot upload otp to 0x1234 len 9478 for board id boot get otp board id result 0x00040400 board_id 1 chip_id 0 ext_bid_support 1 .. Second OTP response : --------------------- .. boot upload otp to 0x1234 len 9478 for ext board id boot get otp ext board id result 0x00000005 ext_board_id 5 boot using eboard name 'bus=pci,bmi-chip-id=0,bmi-eboard-id=5' .. Extended board data download: ------------------------------ .. board name 00000000: 62 75 73 3d 70 63 69 2c 62 6d 69 2d 63 68 69 70 bus=pci,bmi-chip 00000010: 2d 69 64 3d 30 2c 62 6d 69 2d 65 62 6f 61 72 64 -id=0,bmi-eboard 00000020: 2d 69 64 3d 35 -id=5 boot found match for name 'bus=pci,bmi-chip-id=0,bmi-eboard-id=5' boot found eboard data for 'bus=pci,bmi-chip-id=0,bmi-eboard-id=5' using board api 2 boot writing ext board data to addr 0xc3000 .. Fallback Extended board data download from "eboard.bin": --------------------------------------------------------- .. board name 00000000: 62 75 73 3d 70 63 69 2c 62 6d 69 2d 63 68 69 70 bus=pci,bmi-chip 00000010: 2d 69 64 3d 30 2c 62 6d 69 2d 62 6f 61 72 64 2d -id=0,bmi-board- 00000020: 69 64 3d 31 30 id=10 failed to fetch board data for bus=pci,bmi-chip-id=0,bmi-eboard-id=5 from ath10k/QCA9984/hw1.0/board-2.bin boot fw request 'ath10k/QCA9984/hw1.0/eboard.bin': 0 using board api 1 boot writing ext board data to addr 0xc3000 .. Signed-off-by: Sathishkumar Muruganandam <murugana@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: skip resetting rx filter for WCN3990Rakesh Pillai2018-08-281-0/+5
| | | | | | | | | | | | | | | | | WCN3990 has the MAC_PCU_ADDR1 configured properly and hence it will not send spurious ack frames during boot up. Hence the reset_rx_filter workaround is not needed for WCN3990. Add a hw_param to indicate if hardware rx filter reset is needed and skip the reset_rx_filter for WCN3990. Tested HW: WCN3990 Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1 Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: handle mgmt tx completion eventRakesh Pillai2018-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | WCN3990 transmits management frames via WMI with reference. Currently, with the management tx completion not being handled, these frames are not getting freed even after the transmission status is returned by the firmware. The transmitted management frames should be freed when the firmware sends the over-the-air tx status of the corresponding management frames. Handle the wmi mgmt tx completion event and free the corresponding management frame. Tested HW: WCN3990 Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1 Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: fix spectral scan for QCA9984 and QCA9888 chipsetsKarthikeyan Periyasamy2018-06-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The spectral scan has been always broken on QCA9984 and QCA9888. Introduce a hardware parameter 'spectral_bin_offset' to resolve this issue for QCA9984 and QCA9888 chipsets. For other chipsets, the hardware parameter 'spectral_bin_offset' is zero so that existing behaviour is retained as it is. In QCA9984 and QCA9888 chipsets, hardware param value 'spectral_bin_discard' is 12 bytes. This 12 bytes is derived as the sum of segment index (4 bytes), extra bins before the actual data (4 bytes) and extra bins after the actual data (4 bytes). Always discarding (12 bytes) happens at end of the samples and incorrect samples got dumped, so that user can find incorrect arrangement samples in spectral scan dump. To fix this issue, we have to discard first 8 bytes and last 4 bytes in every samples, so totally 12 bytes are discarded. In every sample we need to consider the offset while taking the actual spectral data. For QCA9984, QCA9888 the offset is 8 bytes (segment index + extra bins before actual data). Hardware tested: QCA9984 and QCA9888 Firmware tested: 10.4-3.5.3-00053 Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: hw: make consistent usage of ATH10K_FW_DIR in pathsMarcus Folkesson2018-05-121-2/+2
| | | | | | | | For some reason not all entries used ATH10K_FW_DIR so fix that. No functional changes. Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: enable SRRI/DRRI support on ddr for WCN3990Govind Singh2018-04-241-1/+12
| | | | | | | | | | | | | | | | | | | | | SRRI/DRRI are not mapped in the HW Shadow block and can lead to un-clocked access if common subsystem in the target is powered down due to idle mode. To mitigate this problem SRRI/DRRI can be read from DDR instead of doing an actual hardware read. Host allocates non cached memory on ddr and configures the physical address of this memory to the CE hardware. The hardware updates the RRI on this particular location. Read SRRI/DRRI from DDR location instead of direct target read. Enable retention restore on ddr using hw params to enable in specific targets. Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: add hw params for shadow register supportRakesh Pillai2018-04-241-0/+4
| | | | | | | | | wcn3990 supports shadow register for ce write. Add a hw param for shadow register support. Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: fix fw path name for WCN3990 targetGovind Singh2018-04-191-1/+1
| | | | | | | | FW path is mapped incorrectly for the WCN3990 hw version. Fix fw path with correct hw1.0 name. Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: check all CE for data if irq summary is not retainedRakesh Pillai2018-04-191-0/+3
| | | | | | | | | | | | | | | WCN3990 has interrupts per CE and the interrupt summary is not retained after the interrupt handler has finished execution. We need to check if we received any ce in rx and tx completion path. Generate a interrupt summary with all CE interrupts if the target does not retain interrupt summary after the execution of interrupt handler. Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: add support for Ubiquiti rebranded QCA988X v2Tobias Schramm2018-02-071-0/+1
| | | | | | | | | | Some modern Ubiquiti devices contain a rebranded QCA988X rev2 with a custom Ubiquiti vendor and device id. This patch adds support for those devices, treating them as a QCA988X v2. Signed-off-by: Tobias Schramm <tobleminer@gmail.com> [kvalo@codeaurora.org: rebase, add missing fields in hw_params, fix a long line in pci.c:61] Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath10k: update copyright yearKalle Valo2017-12-271-1/+1
| | | | | | Update year for Qualcomm Atheros, Inc. copyrights. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add memory dump support for QCA6174/QCA9377Alan Liu2017-12-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add memory dump to the firmware crash data file which is provided to user space via devcoredump interface. This makes it easier for firmware engineers to debug firmware crashes. Due to increased memory consumption the memory dump is disabled by default. To enable it make sure that bit 3 is set in coredump_mask module parameter: modprobe ath10k_core coredump_mask=0xffffffff When RAMDUMP is enabled a buffer for the dump is allocated with vmalloc during device probe. The actual memory layout is different in hardware versions and the layouts are defined in coredump.c. The memory is split to regions and, to get even finegrained control of what to copy, the region can split to smaller sections as not all registers are readable (which could cause the whole system to stall). Signed-off-by: Alan Liu <alanliu@qca.qualcomm.com> [kvalo@qca.qualcomm.com: refactoring and cleanup] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: Add hw param for rx ring size supportGovind Singh2017-12-271-0/+3
| | | | | | | | | | WCN3990 uses larger ring size in comparison to existing ring size value. Add rx ring size hw param for supporting different rx ring size across multiple target. Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: Add hw param for 64-bit address supportRakesh Pillai2017-12-271-0/+3
| | | | | | | | | | WCN3990 target supports 37-bit addressing mode. In order to accommodate extended address support, add hw param to indicate if the target supports addressing above 32-bits. Signed-off-by: Rakesh Pillai <pillair@qti.qualcomm.com> Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: wmi: add hw params entry for wcn3990Rakesh Pillai2017-12-141-0/+10
| | | | | | | | | Add hw params entry for wcn3990 and populate various target specific values for wcn3990. Signed-off-by: Rakesh Pillai <pillair@qti.qualcomm.com> Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: wmi: get wmi init parameter values from hw paramsRakesh Pillai2017-12-141-0/+4
| | | | | | | | | | | | | | The parameter values for skid limit, number of peers and wds entries values which are sent in wmi init cmd are hardware specific. Add support to obtain skid limit, number of peers and wds entries values from hw params which will have the hw specific values for these parameters. Signed-off-by: Rakesh Pillai <pillair@qti.qualcomm.com> Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add new cipher suite supportRajkumar Manoharan2017-10-131-0/+3
| | | | | | | | | | | | QCA99x0 and QCA4019 family chips support CCMP-256, GCMP-128, and GCMP-256 ciphers in hardware, so advertise support for these. As firmware does not support group management frame ciphers (BIP), handle them in software (mac80211). Reviewed-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Cc: Jouni Malinen <jouni@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: make ath10k_hw_ce_regs constBhumika Goyal2017-09-251-2/+2
| | | | | | | | | Make them const as they are not modified in the file referencing them. They are only stored in the const field 'hw_ce_reg' of an ath10k structure. Also, make the declarations in the header const. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add tdls support for 10.4 firmwaresManikanta Pubbisetty2017-08-031-0/+5
| | | | | | | | | | | This patch adds the support of TDLS feature for 10.4 firmware versions. A new WMI service is added to advertise the support of TDLS for 10.4 firmwares. Signed-off-by: Manikanta Pubbisetty <mpubbise@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add copy engine register MAP for wcn3990 targetGovind Singh2017-07-061-0/+9
| | | | | | | | | | | Copy engine is a host to target communication interface between wlan firmware and wlan wcn3990 platform driver. Add copy engine register map for wcn3990 wlan module. This add support for the copy engine source/destination ring configuration for wcn3990 chipset. Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: configure rxnss_override for QCA9984Ben Greear2017-06-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | QCA9984 hardware can do 4x4 at 80Mhz, but only 2x2 at 160Mhz. First, report this to user-space by setting the max-tx-speed and max-rx-speed vht capabilities. Second, if the peer rx-speed is configured, and if we are in 160 or 80+80 mode, and the peer rx-speed matches the max speed for 2x2 or 1x1 at 160Mhz (long guard interval), then use that info to set the peer_bw_rxnss_override appropriately. Without this, a 9984 firmware will not use 2x2 ratesets when transmitting to peer (it will be stuck at 1x1), because the firmware would not have configured the rxnss_override. Signed-off-by: Ben Greear <greearb@candelatech.com> [sven.eckelmann@openmesh.com: rebase, cleanup, drop 160Mhz workaround cleanup] Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [kvalo@qca.qualcomm.com: use hw_params, rename the title] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: define structures for CE ctrl/misc registerSarada Prasanna Garnayak2017-06-161-0/+81
| | | | | | | | | | | | | Define structures for the copy engine ctrl/misc registers, that includes CE CMD halt, watermark source, watermark destination, host IE ring, source, destination and dmax ring. This adds support to avoid the conditional compilation, code optimization and dynamic configuration of the copy engine register map for respective hardware bus interface. Signed-off-by: Sarada Prasanna Garnayak <c_sgarna@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: various sdio related definitionsErik Stromdahl2017-05-041-0/+53
| | | | | | | | | Debug masks for SDIO HIF layer. Address definitions for SDIO/mbox based chipsets. Augmented struct host_interest with more members. Signed-off-by: Erik Stromdahl <erik.stromdahl@gmail.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: bump up FW API to 6Ryan Hsu2017-04-191-1/+4
| | | | | | | | | | | | | For QCA6174 hw3.0, since WLAN.RM.4.4-00022-QCARMSWPZ-2, it starts to support the board ID information from otp, with some devices released on the market that didn't calibrated with OTP, will have 0 for board ID information, which cause the backward compatibility issue and was fixed in commit 'd2e202c06ca4 ("ath10k: ignore configuring the incorrect board_id")' So bump the fw api version to differentiate the latest firmware support. Signed-off-by: Ryan Hsu <ryanhsu@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix spectral scan for QCA99X0 family of chipsetsMohammed Shafi Shajakhan2017-04-191-0/+3
| | | | | | | | | | | | | | | | | spectral_bin length (number of bins per fft sample) is usually a value where (2^n = value), n is an integer. All of the QCA99X0 family of chipsets seems to report a spectral_bin length of 2^n + 'm' bytes, where m = 4, 12 based on the chipset. This 'm' bytes seems to carry some radar related info which is currently discarded only for 'bin_len = 68' bytes. Extend this discarding of irrelevant 'bin_len' for QCA9984, QCA9888, IPQ4019 as well by introducing a hardware parameter 'spectral_bin_discard'. Also for QCA988X based family of chipsets which doesn't seem to have this issue and also for some of the hardware which I have not tested like QCA6174/QCA9377 the existing behaviour is retained as it is. Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: clean header files from bad block commentsMarcin Rokicki2017-04-051-1/+2
| | | | | | | | | Fix output from checkpatch.pl like: Block comments use a trailing */ on a separate line Signed-off-by: Marcin Rokicki <marcin.rokicki@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: improve the firmware download time for QCA6174Ryan Hsu2017-03-091-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Len Brown reported the system resume time is taking more than 2 seconds in bug - https://bugzilla.kernel.org/show_bug.cgi?id=185621. The reason of the 2 seconds is due to the firmware download time. The chip is booted up in the default reference clock speed to handle the firmware download to chip memory and advanced to the support higher speed clock to run the firmware after all. The default reference clock in the hardware is slow so that the firmware download time is taking up to 2 seconds for a 600KB firmware file. [76796.349701] ath10k_pci : boot uploading firmware image len 688691 [76798.334612] ath10k_pci : htt tx max num pending tx 1056 The resolution here is to enable the higher speed clock if the hardware supported before the firmware download at BMI stage, so that the hardware can handle the firmare download in a more efficient way. This can help to improve the firmware download time from 2 seconds to around 500ms for the same 600KB firmware file. [322858.577919] ath10k_pci boot uploading firmware image len 688691 [322859.093094] ath10k_pci htt tx max num pending tx 1056 The steps to advance to the higher speed clock is very hardware specific, so adding the hardware ops for the hardware that can support this. Reported-by: Len Brown <lenb@kernel.org> Tested-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Ryan Hsu <ryanhsu@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fetch firmware images in a loopErik Stromdahl2017-02-141-0/+4
| | | | | | | | | | | | | | | To make it easier to handle minimum and maximum firmware API numbers convert the firmware fetch functionality to a loop. If no firmware image is found print an error with minimum and maximum API numbers and the name of firmware directory. This is needed when we switch to using request_firmware_direct() which doesn't print any errors anymore. Also add a new function for creating the fw file name dynamically which makes it easier to add new bus support, for example SDIO and USB, later. Signed-off-by: Erik Stromdahl <erik.stromdahl@gmail.com> [kvalo@qca.qualcomm.com: remove sdio/usb part, new error message, clarify commit log] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: dump Copy Engine registers during firmware crashMohammed Shafi Shajakhan2017-01-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dump Copy Engine source and destination ring addresses. This is useful information to debug firmware crashes, assertes or hangs over long run assessing the Copy Engine Register status. This also enables dumping CE register status in debugfs Crash Dump file. Screenshot: ath10k_pci 0000:02:00.0: simulating hard firmware crash ath10k_pci 0000:02:00.0: firmware crashed! (uuid 84901ff5-d33c-456e-93ee-0165dea643cf) ath10k_pci 0000:02:00.0: qca988x hw2.0 target 0x4100016c chip_id 0x043202ff sub 0000:0000 ath10k_pci 0000:02:00.0: kconfig debug 1 debugfs 1 tracing 1 dfs 1 testmode 1 ath10k_pci 0000:02:00.0: firmware ver 10.2.4.70.59-2 api 5 features no-p2p,raw-mode,mfp,allows-mesh-bcast crc32 4159f498 ath10k_pci 0000:02:00.0: board_file api 1 bmi_id N/A crc32 bebc7c08 ath10k_pci 0000:02:00.0: htt-ver 2.1 wmi-op 5 htt-op 2 cal otp max-sta 128 raw 0 hwcrypto 1 ath10k_pci 0000:02:00.0: firmware register dump: ath10k_pci 0000:02:00.0: [00]: 0x4100016C 0x00000000 0x009A0F2A 0x00000000 ath10k_pci 0000:02:00.0: [04]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [08]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [12]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [16]: 0x00000000 0x00000000 0x00000000 0x009A0F2A ath10k_pci 0000:02:00.0: [20]: 0x00000000 0x00401930 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [24]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [28]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [32]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [36]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [40]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [44]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [48]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [52]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [56]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: Copy Engine register dump: ath10k_pci 0000:02:00.0: [00]: 0x00057400 7 7 3 3 ath10k_pci 0000:02:00.0: [01]: 0x00057800 18 18 85 86 ath10k_pci 0000:02:00.0: [02]: 0x00057c00 49 49 48 49 ath10k_pci 0000:02:00.0: [03]: 0x00058000 16 16 17 16 ath10k_pci 0000:02:00.0: [04]: 0x00058400 4 4 44 4 ath10k_pci 0000:02:00.0: [05]: 0x00058800 12 12 11 12 ath10k_pci 0000:02:00.0: [06]: 0x00058c00 3 3 3 3 ath10k_pci 0000:02:00.0: [07]: 0x00059000 0 0 0 0 ieee80211 phy0: Hardware restart was requested ath10k_pci 0000:02:00.0: device successfully recovered Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com> [kvalo@qca.qualcomm.com: simplify the implementation] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: decrease num of peers supportBartosz Markowski2016-12-291-1/+1
| | | | | | | | The correct number for QCA9377 chip is 33 VDEVs. This impacts also QCA6174 chip and it's max VDEV number. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: allow setting coverage classBenjamin Berg2016-10-041-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately ath10k does not generally allow modifying the coverage class with the stock firmware and Qualcomm has so far refused to implement this feature so that it can be properly supported in ath10k. If we however know the registers that need to be modified for proper operation with a higher coverage class, then we can do these modifications from the driver. This is a hack and might cause subtle problems but as it's not enabled by default (only when user space changes the coverage class explicitly) it should not cause new problems for existing setups. But still this should be considered as an experimental feature and used with caution. This patch implements the support for first generation cards (QCA9880, QCA9887 and so on) which are based on a core that is similar to ath9k. The registers are modified in place and need to be re-written every time the firmware sets them. To achieve this the register status is verified after certain WMI events from the firmware. The coverage class may not be modified temporarily right after the card re-initializes the registers. This is for example the case during scanning. Thanks to Sebastian Gottschall <s.gottschall@dd-wrt.com> for initially working on a userspace support for this. This patch wouldn't have been possible without this documentation. Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net> Signed-off-by: Simon Wunderlich <sw@simonwunderlich.de> Signed-off-by: Mathias Kretschmer <mathias.kretschmer@fit.fraunhofer.de> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix rfc1042 header retrieval in QCA4019 with eth decap modeVasanthakumar Thiagarajan2016-09-271-0/+3
| | | | | | | | | | | | | Chipset from QCA99X0 onwards (QCA99X0, QCA9984, QCA4019 & future) rx_hdr_status is not padded to align in 4-byte boundary. Define a new hw_params field to handle different alignment behaviour between different hw. This patch fixes improper retrieval of rfc1042 header with QCA4019. This patch along with "ath10k: Properly remove padding from the start of rx payload" will fix traffic failure in ethernet decap mode for QCA4019. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: spelling and miscellaneous neateningJoe Perches2016-09-271-1/+1
| | | | | | | | | Correct some trivial comment typos. Remove unnecessary parentheses in a long line. Signed-off-by: Joe Perches <joe@perches.com> [kvalo@qca.qualcomm.com: drop the change for return] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove 4-addr padding related hw_param configurationVasanthakumar Thiagarajan2016-09-131-8/+0
| | | | | | | | | | | | hw_4addr_pad was added to handle different types of padding in 4-address rx frame. But this padding is not very specific to 4-address, it can happen even with three address + ethernet decap mode. Since the padding information can be obtained through Rx desc for QCA99X0 and newer chips, this hw_param is not needed any more. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: properly remove padding from the start of rx payloadVasanthakumar Thiagarajan2016-09-131-0/+9
| | | | | | | | | | | | | | | | In QCA99X0 (QCA99X0, QCA9984, QCA9888 and QCA4019) family chips, hw adds padding at the begining of the rx payload to make L3 header 4-byte aligned. In the chips doing this type of padding, the number of bytes padded will be indicated through msdu_end:info1. Define a hw_rx_desc_ops wrapper to retrieve the number of padded bytes and use this while doing undecap. This should fix padding related issues with ethernt decap format with QCA99X0, QCA9984, QCA9888 and QCA4019 hw. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> [Rename operations to hw_ops for other purposes] Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add provision for Rx descriptor abstractionVasanthakumar Thiagarajan2016-09-131-0/+12
| | | | | | | | | | | | | | | | | | There are slight differences in Rx hw descriptor information among different chips. So far driver does not use those new information for any functionalities, but there is one important information which is available from QCA99X0 onwards to indicate the number of bytes that hw padded at the begining of the rx payload and this information is needed to undecap the rx packet. Add an abstraction for Rx desc to make use of the new desc information available. The callback that this patch defines to retrieve the padding bytes will be used in follow-up patch. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> [Rename operations to hw_ops for other purposes] Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 01:14:28 +0000