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| | * | PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0Manivannan Sadhasivam2023-06-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SoCs making use of Qcom PCIe controller IPs v2.3.3 and v2.9.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's not set the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Link: https://lore.kernel.org/r/20230619150408.8468-6-manivannan.sadhasivam@linaro.org Tested-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
| | * | PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and v1.9.0Manivannan Sadhasivam2023-06-201-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SoCs making use of Qcom PCIe controller IPs v2.7.0 and v1.9.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Link: https://lore.kernel.org/r/20230619150408.8468-5-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
| | * | PCI: qcom: Disable write access to read only registers for IP v2.9.0Manivannan Sadhasivam2023-06-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. While at it, let's also add a newline after existing dw_pcie_dbi_ro_wr_en() guard function to align with rest of the driver. Link: https://lore.kernel.org/r/20230619150408.8468-4-manivannan.sadhasivam@linaro.org Fixes: 0cf7c2efe8ac ("PCI: qcom: Add IPQ60xx support") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
| | * | PCI: qcom: Use DWC helpers for modifying the read-only DBI registersManivannan Sadhasivam2023-06-201-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DWC core already exposes dw_pcie_dbi_ro_wr_{en/dis} helper APIs for enabling and disabling the write access to read only DBI registers. So let's use them instead of doing it manually. Also, the existing code doesn't disable the write access when it's done. This is also fixed now. Link: https://lore.kernel.org/r/20230619150408.8468-3-manivannan.sadhasivam@linaro.org Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
| | * | PCI: qcom: Disable write access to read only registers for IP v2.3.3Manivannan Sadhasivam2023-06-201-0/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. Link: https://lore.kernel.org/r/20230619150408.8468-2-manivannan.sadhasivam@linaro.org Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: <stable@vger.kernel.org>
| * | PCI: imx6: Save and restore root port MSI control in suspend and resumeRichard Zhu2023-06-191-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The imx6 PCI host controller suffers from a HW integration bug whereby the MSI enable bit in the root port MSI capability enables/disables MSIs interrupts for all downstream components in the PCI tree. This requires, as implemented in 75cb8d20c112 ("PCI: imx: Enable MSI from downstream components") that the root port MSI enable bit should be set in order for downstream PCI devices MSIs to function. The MSI enable bit programming might be lost during the suspend and should be re-stored during resume. Save the MSI control during suspend and restore it in resume. Link: https://lore.kernel.org/r/1670479534-22154-1-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> [lpieralisi@kernel.org: commit log] Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| * | PCI: dwc: Wait for link up only if link is startedAjay Agarwal2023-05-263-11/+23
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In dw_pcie_host_init() regardless of whether the link has been started or not, the code waits for the link to come up. Even in cases where start_link() is not defined the code ends up spinning in a loop for 1 second. Since in some systems dw_pcie_host_init() gets called during probe, this one second loop for each pcie interface instance ends up extending the boot time. Wait for the link up in only if the start_link() is defined. Link: https://lore.kernel.org/r/20230412093425.3659088-1-ajayagarwal@google.com Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Sajid Dalvi <sdalvi@google.com> Signed-off-by: Ajay Agarwal <ajayagarwal@google.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
* | PCI: tegra194: Add interconnect support in Tegra234Sumit Gupta2023-05-161-16/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to request DRAM bandwidth (BW) with Memory Interconnect in Tegra234 SoC. The DRAM BW required for different modes depends on the link speed (Gen-1/2/3/4) and width/lanes (x1/x2/x4/x8). Currently, the DRAM frequency is always set to the maximum available but that results in the highest power consumption. The Memory Interconnect is a software feature which uses Interconnect framework (ICC). It adds the capability for Memory Controller (MC) clients to request bandwidth and therefore scale DRAM frequency dynamically depending on the required link speed so that the DRAM energy consumption can be optimized. Suggested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | PCI: tegra194: Fix possible array out of bounds accessSumit Gupta2023-05-161-2/+11
|/ | | | | | | | | | | | | | Add check to fix the possible array out of bounds violation by making speed equal to GEN1_CORE_CLK_FREQ when its value is more than the size of "pcie_gen_freq" array. This array has size of four but possible speed (CLS) values are from "0 to 0xF". So, "speed - 1" values are "-1 to 0xE". Suggested-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Link: https://lore.kernel.org/lkml/72b9168b-d4d6-4312-32ea-69358df2f2d0@nvidia.com/ Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'pci-v6.4-changes' of ↵Linus Torvalds2023-04-274-945/+740
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull pci updates from Bjorn Helgaas: "Resource management: - Add pci_dev_for_each_resource() and pci_bus_for_each_resource() iterators PCIe native device hotplug: - Fix AB-BA deadlock between reset_lock and device_lock Power management: - Wait longer for devices to become ready after resume (as we do for reset) to accommodate Intel Titan Ridge xHCI devices - Extend D3hot delay for NVIDIA HDA controllers to avoid unrecoverable devices after a bus reset Error handling: - Clear PCIe Device Status after EDR since generic error recovery now only clears it when AER is native ASPM: - Work around Chromebook firmware defect that clobbers Capability list (including ASPM L1 PM Substates Cap) when returning from D3cold to D0 Freescale i.MX6 PCIe controller driver: - Install imprecise external abort handler only when DT indicates PCIe support Freescale Layerscape PCIe controller driver: - Add ls1028a endpoint mode support Qualcomm PCIe controller driver: - Add SM8550 DT binding and driver support - Add SDX55 DT binding and driver support - Use bulk APIs for clocks of IP 1.0.0, 2.3.2, 2.3.3 - Use bulk APIs for reset of IP 2.1.0, 2.3.3, 2.4.0 - Add DT "mhi" register region for supported SoCs - Expose link transition counts via debugfs to help debug low power issues - Support system suspend and resume; reduce interconnect bandwidth and turn off clock and PHY if there are no active devices - Enable async probe by default to reduce boot time Miscellaneous: - Sort controller Kconfig entries by vendor" * tag 'pci-v6.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (56 commits) PCI: xilinx: Drop obsolete dependency on COMPILE_TEST PCI: mobiveil: Sort Kconfig entries by vendor PCI: dwc: Sort Kconfig entries by vendor PCI: Sort controller Kconfig entries by vendor PCI: Use consistent controller Kconfig menu entry language PCI: xilinx-nwl: Add 'Xilinx' to Kconfig prompt PCI: hv: Add 'Microsoft' to Kconfig prompt PCI: meson: Add 'Amlogic' to Kconfig prompt PCI: Use of_property_present() for testing DT property presence PCI/PM: Extend D3hot delay for NVIDIA HDA controllers dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties PCI: qcom: Add SM8550 PCIe support dt-bindings: PCI: qcom: Add SM8550 compatible PCI: qcom: Add support for SDX55 SoC dt-bindings: PCI: qcom-ep: Fix the unit address used in example dt-bindings: PCI: qcom: Add SDX55 SoC dt-bindings: PCI: qcom: Update maintainers entry PCI: qcom: Enable async probe by default PCI: qcom: Add support for system suspend and resume PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter ...
| * PCI: dwc: Sort Kconfig entries by vendorBjorn Helgaas2023-04-201-203/+203
| | | | | | | | | | | | | | | | Sort Kconfig entries by vendor so they appear in alphabetical order in menuconfig. Link: https://lore.kernel.org/r/20230418174336.145585-7-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: Use consistent controller Kconfig menu entry languageBjorn Helgaas2023-04-201-27/+27
| | | | | | | | | | | | | | | | Use "PCIe controller" consistently instead of "host bridge", "bus driver", etc. Annotate with "(host mode)" or "(endpoint mode)" as needed. Link: https://lore.kernel.org/r/20230418174336.145585-5-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: meson: Add 'Amlogic' to Kconfig promptBjorn Helgaas2023-04-201-1/+1
| | | | | | | | | | | | | | | | | | | | Add the "Amlogic" vendor name to the CONFIG_PCI_MESON Kconfig prompt to match other PCIe drivers. Capitalize "Meson" to match other Meson Kconfig prompts. Link: https://lore.kernel.org/r/20230418174336.145585-2-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Yue Wang <yue.wang@Amlogic.com>
| * Merge branch 'pci/controller/qcom'Bjorn Helgaas2023-04-201-730/+516
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use correct PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register for v2.7.0 (Manivannan Sadhasivam) - Remove "PCIE20_" prefix from register definitions (Manivannan Sadhasivam) - Sort registers and bitfield declarations (Manivannan Sadhasivam) - Convert to GENMASK and FIELD_PREP (Manivannan Sadhasivam) - Use bulk APIs for clocks of IP 1.0.0, 2.3.2, 2.3.3 (Manivannan Sadhasivam) - Use bulk APIs for reset of IP 2.1.0, 2.3.3, 2.4.0 (Manivannan Sadhasivam) - Rename qcom_pcie_config_sid_sm8250() to be non SM8250-specific (Manivannan Sadhasivam) - Add DT "mhi" register region for supported SoCs (Manivannan Sadhasivam) - Expose link transition counts via debugfs to help debug low power issues (Manivannan Sadhasivam) - Support system suspend and resume; reduce interconnect bandwidth and turn off clock and PHY if there are no active devices (Manivannan Sadhasivam) - Enable async probe by default to reduce boot time (Manivannan Sadhasivam) - Add Manivannan Sadhasivam as qcom DT binding maintainer, replacing Stanimir Varbanov (Manivannan Sadhasivam) - Add DT binding and driver support for Qcom SDX55 SoC (Manivannan Sadhasivam) - Add DT binding and driver support for SM8550 SoC (Abel Vesa) - Document msi-map and msi-map-mask DT properties (Manivannan Sadhasivam) * pci/controller/qcom: dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties PCI: qcom: Add SM8550 PCIe support dt-bindings: PCI: qcom: Add SM8550 compatible PCI: qcom: Add support for SDX55 SoC dt-bindings: PCI: qcom-ep: Fix the unit address used in example dt-bindings: PCI: qcom: Add SDX55 SoC dt-bindings: PCI: qcom: Update maintainers entry PCI: qcom: Enable async probe by default PCI: qcom: Add support for system suspend and resume PCI: qcom: Expose link transition counts via debugfs dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version PCI: qcom: Use macros for defining total no. of clocks & supplies PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3 PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 PCI: qcom: Use lower case for hex PCI: qcom: Add missing macros for register fields PCI: qcom: Use bitfield definitions for register fields PCI: qcom: Sort and group registers and bitfield definitions PCI: qcom: Remove PCIE20_ prefix from register definitions PCI: qcom: Fix the incorrect register usage in v2.7.0 config
| | * PCI: qcom: Add SM8550 PCIe supportAbel Vesa2023-04-121-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SM8550 requires two additional clocks for proper working. Add these two clocks as optional clocks (as only required by this platform) and compatible for this platform. While at it, let's also rename the reset variable to "rst" from "pci_reset" to match the existing naming preference. Link: https://lore.kernel.org/r/20230320144658.1794991-2-abel.vesa@linaro.org Signed-off-by: Abel Vesa <abel.vesa@linaro.org> [lpieralisi@kernel.org: commit log rewording] Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
| | * PCI: qcom: Add support for SDX55 SoCManivannan Sadhasivam2023-04-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SDX55 SoC reusing the 1.9.0 config. The PCIe controller is of version 1.10.0 but it is compatible with the 1.9.0 config. This SoC also requires "sleep" clock which is added as an optional clock in the driver, since it is not required on other SoCs. Link: https://lore.kernel.org/r/20230308082424.140224-14-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Enable async probe by defaultManivannan Sadhasivam2023-04-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qcom PCIe RC driver waits for the PHY link to be up during the probe; this consumes several milliseconds during boot. Enable async probe by default so that other drivers can load in parallel while this driver waits for the link to be up. Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230320064644.5217-1-manivannan.sadhasivam@linaro.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
| | * PCI: qcom: Add support for system suspend and resumeManivannan Sadhasivam2023-04-121-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the system suspend, vote for minimal interconnect bandwidth (1KiB) to keep the interconnect path active for config access and also turn OFF the resources like clock and PHY if there are no active devices connected to the controller. For the controllers with active devices, the resources are kept ON as removing the resources will trigger access violation during the late end of suspend cycle as kernel tries to access the config space of PCIe devices to mask the MSIs. Also, it is not desirable to put the link into L2/L3 state as that implies VDD supply will be removed and the devices may go into powerdown state. This will affect the lifetime of storage devices like NVMe. And finally, during resume, turn ON the resources if the controller was truly suspended (resources OFF) and update the interconnect bandwidth based on PCIe Gen speed. Suggested-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Link: https://lore.kernel.org/r/20230403154922.20704-2-manivannan.sadhasivam@linaro.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Dhruva Gole <d-gole@ti.com>
| | * PCI: qcom: Expose link transition counts via debugfsManivannan Sadhasivam2023-04-111-2/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qualcomm PCIe controllers have debug registers in the MHI region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Note that even though the registers are prefixed as PARF_, they don't live under the "parf" register region. The register naming is following the Qualcomm's internal documentation as like other registers. While at it, let's arrange the local variables in probe function to follow reverse XMAS tree order. Link: https://lore.kernel.org/r/20230316081117.14288-20-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP versionManivannan Sadhasivam2023-04-111-72/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qcom_pcie_config_sid_sm8250() function no longer applies only to SM8250. So let's rename it to reflect the actual IP version and also move its definition to keep it sorted as per IP revisions. Link: https://lore.kernel.org/r/20230316081117.14288-15-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use macros for defining total no. of clocks & suppliesManivannan Sadhasivam2023-04-111-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | To keep uniformity, let's use macros to define the total number of clocks and supplies in qcom_pcie_resources_{2_7_0/2_9_0} structs. Link: https://lore.kernel.org/r/20230316081117.14288-14-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0Manivannan Sadhasivam2023-04-111-208/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. It should be noted that there were delays in-between the reset asserts and deasserts. But going by the config used by other revisions, those delays are not really necessary. So a single delay after all asserts and one after deasserts is used. The total number of resets supported is 12 but only ipq4019 is using all of them. Link: https://lore.kernel.org/r/20230316081117.14288-13-manivannan.sadhasivam@linaro.org Tested-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3Manivannan Sadhasivam2023-04-111-26/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. Link: https://lore.kernel.org/r/20230316081117.14288-12-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3Manivannan Sadhasivam2023-04-111-68/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Link: https://lore.kernel.org/r/20230316081117.14288-11-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2Manivannan Sadhasivam2023-04-111-57/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Link: https://lore.kernel.org/r/20230316081117.14288-10-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0Manivannan Sadhasivam2023-04-111-53/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Link: https://lore.kernel.org/r/20230316081117.14288-9-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0Manivannan Sadhasivam2023-04-111-95/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. While at it, let's also move the qcom_pcie_resources_2_1_0 struct below qcom_pcie_resources_1_0_0 to keep it sorted. Link: https://lore.kernel.org/r/20230316081117.14288-8-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use lower case for hexManivannan Sadhasivam2023-04-111-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | To maintain uniformity, let's use lower case for representing hexadecimal numbers. Link: https://lore.kernel.org/r/20230316081117.14288-7-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Add missing macros for register fieldsManivannan Sadhasivam2023-04-111-17/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the registers are changed using hardcoded bitfields without macros. This provides no information on what the register setting is about. So add the macros to those fields for making the code more understandable. Link: https://lore.kernel.org/r/20230316081117.14288-6-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Use bitfield definitions for register fieldsManivannan Sadhasivam2023-04-111-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | To maintain uniformity throughout the driver and also to make the code easier to read, let's make use of bitfield definitions for register fields. Link: https://lore.kernel.org/r/20230316081117.14288-5-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Sort and group registers and bitfield definitionsManivannan Sadhasivam2023-04-111-45/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sorting the registers and their bit definitions will make it easier to add more definitions in the future and it also helps in maintenance. While at it, let's also group the registers and bit definitions separately as done in the pcie-qcom-ep driver. Link: https://lore.kernel.org/r/20230316081117.14288-4-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Remove PCIE20_ prefix from register definitionsManivannan Sadhasivam2023-04-111-93/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIE part is redundant and 20 doesn't represent anything across the SoCs supported now. So let's get rid of the prefix. This involves adding the IP version suffix to one definition of PARF_SLV_ADDR_SPACE_SIZE that defines offset specific to that version. The other definition is generic for the rest of the versions. Also, the register PCIE20_LNK_CONTROL2_LINK_STATUS2 is not used anywhere, hence removed. Link: https://lore.kernel.org/r/20230316081117.14288-3-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * PCI: qcom: Fix the incorrect register usage in v2.7.0 configManivannan Sadhasivam2023-04-111-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qcom PCIe IP version v2.7.0 and its derivatives don't contain the PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT register. Instead, they have the new PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register. So fix the incorrect register usage which is modifying a different register. Also in this IP version, this register change doesn't depend on MSI being enabled. So remove that check also. Link: https://lore.kernel.org/r/20230316081117.14288-2-manivannan.sadhasivam@linaro.org Fixes: ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: <stable@vger.kernel.org> # 5.6+
| * | Merge branch 'pci/controller/layerscape'Bjorn Helgaas2023-04-201-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Add ls1028a endpoint mode support (Xiaowei Bao) * pci/controller/layerscape: PCI: layerscape: Add EP mode support for ls1028a
| | * | PCI: layerscape: Add EP mode support for ls1028aXiaowei Bao2023-03-171-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe EP mode support for ls1028a. Link: https://lore.kernel.org/r/20230209151050.233973-1-Frank.Li@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Alok Tiwari <alok.a.tiwari@oracle.com> Acked-by: Roy Zang <Roy.Zang@nxp.com>
| * | Merge branch 'pci/controller/kirin'Bjorn Helgaas2023-04-201-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Select CONFIG_REGMAP_MMIO so kirin driver links correctly (Josh Triplett) * pci/controller/kirin: PCI: kirin: Select REGMAP_MMIO
| | * | PCI: kirin: Select REGMAP_MMIOJosh Triplett2023-03-101-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pcie-kirin uses regmaps, and needs to pull them in; otherwise, with CONFIG_PCIE_KIRIN=y and without CONFIG_REGMAP_MMIO pcie-kirin produces a linker failure looking for __devm_regmap_init_mmio_clk(). Fixes: d19afe7be126 ("PCI: kirin: Use regmap for APB registers") Link: https://lore.kernel.org/r/04636141da1d6d592174eefb56760511468d035d.1668410580.git.josh@joshtriplett.org Signed-off-by: Josh Triplett <josh@joshtriplett.org> [lpieralisi@kernel.org: commit log and removed REGMAP select] Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: stable@vger.kernel.org # 5.16+
| * / PCI: imx6: Install the fault handler only on compatible matchH. Nikolaus Schaller2023-03-241-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit bb38919ec56e ("PCI: imx6: Add support for i.MX6 PCIe controller") added a fault hook to this driver in the probe function. So it was only installed if needed. commit bde4a5a00e76 ("PCI: imx6: Allow probe deferral by reset GPIO") moved it from probe to driver init which installs the hook unconditionally as soon as the driver is compiled into a kernel. When this driver is compiled as a module, the hook is not registered until after the driver has been matched with a .compatible and loaded. commit 415b6185c541 ("PCI: imx6: Fix config read timeout handling") extended the fault handling code. commit 2d8ed461dbc9 ("PCI: imx6: Add support for i.MX8MQ") added some protection for non-ARM architectures, but this does not protect non-i.MX ARM architectures. Since fault handlers can be triggered on any architecture for different reasons, there is no guarantee that they will be triggered only for the assumed situation, leading to improper error handling (i.MX6-specific imx6q_pcie_abort_handler) on foreign systems. I had seen strange L3 imprecise external abort messages several times on OMAP4 and OMAP5 devices and couldn't make sense of them until I realized they were related to this unused imx6q driver because I had CONFIG_PCI_IMX6=y. Note that CONFIG_PCI_IMX6=y is useful for kernel binaries that are designed to run on different ARM SoC and be differentiated only by device tree binaries. So turning off CONFIG_PCI_IMX6 is not a solution. Therefore we check the compatible in the init function before registering the fault handler. Link: https://lore.kernel.org/r/e1bcfc3078c82b53aa9b78077a89955abe4ea009.1678380991.git.hns@goldelico.com Fixes: bde4a5a00e76 ("PCI: imx6: Allow probe deferral by reset GPIO") Fixes: 415b6185c541 ("PCI: imx6: Fix config read timeout handling") Fixes: 2d8ed461dbc9 ("PCI: imx6: Add support for i.MX8MQ") Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
* / PCI: dwc: Fix PORT_LINK_CONTROL update when CDM check enabledYoshihiro Shimoda2023-03-211-5/+5
|/ | | | | | | | | | | | | | | | | | If CDM_CHECK is enabled (by the DT "snps,enable-cdm-check" property), 'val' is overwritten by PCIE_PL_CHK_REG_CONTROL_STATUS initialization. Commit ec7b952f453c ("PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" exists") did not account for further usage of 'val', so we wrote improper values to PCIE_PORT_LINK_CONTROL when the CDM check is enabled. Move the PCIE_PORT_LINK_CONTROL update to be completely after the PCIE_PL_CHK_REG_CONTROL_STATUS register initialization. [bhelgaas: commit log adapted from Serge's version] Fixes: ec7b952f453c ("PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" exists") Link: https://lore.kernel.org/r/20230310123510.675685-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
* Merge tag 'pci-v6.3-changes' of ↵Linus Torvalds2023-02-2411-28/+479
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Rework portdrv shutdown so it disables interrupts but doesn't disable bus mastering, which leads to hangs on Loongson LS7A - Add mechanism to prevent Max_Read_Request_Size (MRRS) increases, again to avoid hardware issues on Loongson LS7A (and likely other devices based on DesignWare IP) - Ignore devices with a firmware (DT or ACPI) node that says the device is disabled Resource management: - Distribute spare resources to unconfigured hotplug bridges at boot-time (not just when hot-adding such a bridge), which makes hot-adding devices to docks work better. Tried this in v6.1 but had to revert for regressions, so try again - Fix root bus issue that dropped resources that happened to end at 0, e.g., [bus 00] PCI device hotplug: - Remove device locking when marking device as disconnected so this doesn't have to wait for concurrent driver bind/unbind to complete - Quirk more Qualcomm bridges that don't fully implement the PCIe Slot Status 'Command Completed' bit Power management: - Account for _S0W of the target bridge in acpi_pci_bridge_d3() so we don't miss hot-add notifications for USB4 docks, Thunderbolt, etc Reset: - Observe delay after reset, e.g., resuming from system sleep, regardless of whether a bridge can suspend to D3cold at runtime - Wait for secondary bus to become ready after a bridge reset Virtualization: - Avoid FLR on some AMD FCH AHCI adapters where it doesn't work - Allow independent IOMMU groups for some Wangxun NICs that prevent peer-to-peer transactions but don't advertise an ACS Capability Error handling: - Configure End-to-End-CRC (ECRC) only if Linux owns the AER Capability - Remove redundant Device Control Error Reporting Enable in the AER service driver since this is already done for all devices during enumeration ASPM: - Add pci_enable_link_state() interface to allow drivers to enable ASPM link state Endpoint framework: - Move dra7xx and tegra194 linkup processing from hard IRQ to threaded IRQ handler - Add a separate lock for endpoint controller list of endpoint function drivers to prevent deadlock in callbacks - Pass events from endpoint controller to endpoint function drivers via callbacks instead of notifiers Synopsys DesignWare eDMA controller driver (acked by Vinod): - Fix CPU vs PCI address issues - Fix source vs destination address issues - Fix issues with interleaved transfer semantics - Fix channel count initialization issue (issue still exists in several other drivers) - Clean up and improve debugfs usage so it will work on platforms with several eDMA devices Baikal T-1 PCIe controller driver: - Set a 64-bit DMA mask Freescale i.MX6 PCIe controller driver: - Add i.MX8MM, i.MX8MQ, i.MX8MP endpoint mode DT binding and driver support Intel VMD host bridge driver: - Add quirk to configure PCIe ASPM and LTR. This is normally done by BIOS, and will be for future products Marvell MVEBU PCIe controller driver: - Mark this driver as broken in Kconfig since bugs prevent its daily usage MediaTek MT7621 PCIe controller driver: - Delay PHY port initialization to improve boot reliability for ZBT WE1326, ZBT WF3526-P, and some Netgear models Qualcomm PCIe controller driver: - Add MSM8998 DT compatible string - Unify MSM8996 and MSM8998 clock orderings - Add SM8350 DT binding and driver support - Add IPQ8074 Gen3 DT binding and driver support - Correct qcom,perst-regs in DT binding - Add qcom_pcie_host_deinit() so the PHY is powered off and regulators and clocks are disabled on late host-init errors Socionext UniPhier Pro5 controller driver: - Clean up uniphier-ep reg, clocks, resets, and their names in DT binding Synopsys DesignWare PCIe controller driver: - Restrict coherent DMA mask to 32 bits for MSI, but allow controller drivers to set 64-bit streaming DMA mask - Add eDMA engine support in both Root Port and Endpoint controllers Miscellaneous: - Remove MODULE_LICENSE from boolean drivers so they don't look like modules so modprobe can complain about them" * tag 'pci-v6.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (86 commits) PCI: dwc: Add Root Port and Endpoint controller eDMA engine support PCI: bt1: Set 64-bit DMA mask PCI: dwc: Restrict only coherent DMA mask for MSI address allocation dmaengine: dw-edma: Prepare dw_edma_probe() for builtin callers dmaengine: dw-edma: Depend on DW_EDMA instead of selecting it dmaengine: dw-edma: Add mem-mapped LL-entries support PCI: Remove MODULE_LICENSE so boolean drivers don't look like modules PCI: hv: Drop duplicate PCI_MSI dependency PCI/P2PDMA: Annotate RCU dereference PCI/sysfs: Constify struct kobj_type pci_slot_ktype PCI: hotplug: Allow marking devices as disconnected during bind/unbind PCI: pciehp: Add Qualcomm quirk for Command Completed erratum PCI: qcom: Add IPQ8074 Gen3 port support dt-bindings: PCI: qcom: Add IPQ8074 Gen3 port dt-bindings: PCI: qcom: Sort compatibles alphabetically PCI: qcom: Fix host-init error handling PCI: qcom: Add SM8350 support dt-bindings: PCI: qcom: Add SM8350 dt-bindings: PCI: qcom-ep: Correct qcom,perst-regs dt-bindings: PCI: qcom: Unify MSM8996 and MSM8998 clock order ...
| * Merge branch 'pci/controller/qcom'Bjorn Helgaas2023-02-221-1/+14
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add DT compatible for qcom MSM8998 (Krzysztof Kozlowski) - Unify qcom MSM8996 and MSM8998 clock orderings (Krzysztof Kozlowski) - Correct qcom,perst-regs (Krzysztof Kozlowski) - Add qcom SM8350 DT binding and driver support (Dmitry Baryshkov) - Add qcom_pcie_host_deinit() so the PHY is powered off and regulators and clocks are disabled on late host-init errors (Johan Hovold) - Add IPQ8074 Gen3 port DT binding and driver support (the Gen2 port was already supported) (Robert Marko) * pci/controller/qcom: PCI: qcom: Add IPQ8074 Gen3 port support dt-bindings: PCI: qcom: Add IPQ8074 Gen3 port dt-bindings: PCI: qcom: Sort compatibles alphabetically PCI: qcom: Fix host-init error handling PCI: qcom: Add SM8350 support dt-bindings: PCI: qcom: Add SM8350 dt-bindings: PCI: qcom-ep: Correct qcom,perst-regs dt-bindings: PCI: qcom: Unify MSM8996 and MSM8998 clock order dt-bindings: PCI: qcom: Add MSM8998 specific compatible dt-bindings: PCI: qcom: Add oneOf to compatible match
| | * PCI: qcom: Add IPQ8074 Gen3 port supportRobert Marko2023-02-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported. Add compatible for Gen3 port which uses the same controller as IPQ6018. Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * PCI: qcom: Fix host-init error handlingJohan Hovold2023-02-141-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the new host_deinit() callback so that the PHY is powered off and regulators and clocks are disabled also on late host-init errors. Link: https://lore.kernel.org/r/20221017114705.8277-2-johan+linaro@kernel.org Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
| | * PCI: qcom: Add SM8350 supportDmitry Baryshkov2023-02-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the PCIe host on Qualcomm SM8350 platform. Link: https://lore.kernel.org/r/20221118233242.2904088-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org>
| * | Merge branch 'pci/controller/imx6'Bjorn Helgaas2023-02-222-19/+204
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add i.MX8MM, i.MX8MQ, i.MX8MP endpoint mode DT binding and driver support (Richard Zhu) * pci/controller/imx6: PCI: imx6: Add i.MX8MP PCIe EP support PCI: imx6: Add i.MX8MM PCIe EP support PCI: imx6: Add i.MX8MQ PCIe EP support PCI: imx6: Add i.MX PCIe EP mode support misc: pci_endpoint_test: Add i.MX8 PCIe EP device support dt-bindings: imx6q-pcie: Add i.MX8MP PCIe EP mode compatible string dt-bindings: imx6q-pcie: Add i.MX8MQ PCIe EP mode compatible string dt-bindings: imx6q-pcie: Add i.MX8MM PCIe EP mode compatible string
| | * | PCI: imx6: Add i.MX8MP PCIe EP supportRichard Zhu2023-01-161-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the i.MX8MP PCIe EP support. Link: https://lore.kernel.org/r/1673847684-31893-15-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * | PCI: imx6: Add i.MX8MM PCIe EP supportRichard Zhu2023-01-161-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8MM PCIe EP support. Link: https://lore.kernel.org/r/1673847684-31893-14-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * | PCI: imx6: Add i.MX8MQ PCIe EP supportRichard Zhu2023-01-161-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8MQ PCIe EP support. Link: https://lore.kernel.org/r/1673847684-31893-13-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| | * | PCI: imx6: Add i.MX PCIe EP mode supportRichard Zhu2023-01-162-14/+137
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX PCIe is one dual mode PCIe controller. Add i.MX PCIe EP mode support here, and split the PCIe modes to the Root Complex mode and Endpoint mode. Link: https://lore.kernel.org/r/1673847684-31893-12-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
| * | Merge branch 'pci/controller/dwc'Bjorn Helgaas2023-02-225-4/+253
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Release previously-requested DW eDMA IRQs if request_irq() fails (Serge Semin) - Convert DW eDMA linked-list (ll) and data target (dt) from CPU-relative addresses to PCI bus addresses (Serge Semin) - Fix missing src/dst address for interleaved transfers (Serge Semin) - Enforce the DW eDMA restriction that interleaved transfers must increment src and dst addresses (Serge Semin) - Fix some invalid interleaved transfer semantics (Serge Semin) - Convert CPU-relative addresses to PCI bus addresses for eDMA engine (Serge Semin) - Drop chancnt initialization from dw-edma-core, since it is managed by the dmaengine core, e.g., in dma_async_device_channel_register() (Serge Semin) - Clean up bogus casting of debugfs_entries.reg addresses (Serge Semin) - Ignore debugfs file/directory creation errors (Serge Semin) - Allocate debugfs entries from the heap to prepare for multi-eDMA platforms (Serge Semin) - Simplify and rework register accessors to remove another obstacle to multi-eDMA platforms (Serge Semin) - Consolidate eDMA read/write channels in a single dma_device to simplify, better reflect the hardware design, and avoid a debugfs complaint (Serge Semin) - Move eDMA-specific debugfs nodes into existing dmaengine subdirectory (Serge Semin) - Fix a readq_ch() truncation from 64 to 32 bits (Serge Semin) - Use existing readq()/writeq rather than hand-coding new ones (Serge Semin) - Drop unnecessary data target region allocation in favor of existing dw_edma_chip members (Serge Semin) - Use parent device in eDMA controller name to prepare for multi-eDMA platforms (Serge Semin) - In addition to the existing MMIO accessors for linked list entries, add support for ioremapped entries for use by eDMA in Root Ports or local Endpoints (Serge Semin) - Convert DW_EDMA_PCIE so it depends on DW_EDMA instead of selecting it (Serge Semin) - Allow DWC drivers to set streaming DMA masks larger than 32 bits; previously both streaming and coherent DMA were limited to 32 bits because some PCI devices only support coherent 32-bit DMA for MSI (Serge Semin) - Set 64-bit streaming and coherent DMA mask for the bt1 driver (Serge Semin) - Add DW Root Port and Endpoint controller support for eDMA (Serge Semin) * pci/controller/dwc: PCI: dwc: Add Root Port and Endpoint controller eDMA engine support PCI: bt1: Set 64-bit DMA mask PCI: dwc: Restrict only coherent DMA mask for MSI address allocation dmaengine: dw-edma: Prepare dw_edma_probe() for builtin callers dmaengine: dw-edma: Depend on DW_EDMA instead of selecting it dmaengine: dw-edma: Add mem-mapped LL-entries support dmaengine: dw-edma: Skip cleanup procedure if no private data found dmaengine: dw-edma: Replace chip ID number with device name dmaengine: dw-edma: Drop DT-region allocation dmaengine: dw-edma: Use non-atomic io-64 methods dmaengine: dw-edma: Fix readq_ch() return value truncation dmaengine: dw-edma: Use DMA engine device debugfs subdirectory dmaengine: dw-edma: Join read/write channels into a single device dmaengine: dw-edma: Move eDMA data pointer to debugfs node descriptor dmaengine: dw-edma: Simplify debugfs context CSRs init procedure dmaengine: dw-edma: Rename debugfs dentry variables to 'dent' dmaengine: dw-edma: Convert debugfs descs to being heap-allocated dmaengine: dw-edma: Add dw_edma prefix to debugfs nodes descriptor dmaengine: dw-edma: Stop checking debugfs_create_*() return value dmaengine: dw-edma: Drop unnecessary debugfs reg casts dmaengine: dw-edma: Drop chancnt initialization dmaengine: dw-edma: Add PCI bus address getter to the remote EP glue driver dmaengine: dw-edma: Add CPU to PCI bus address translation dmaengine: dw-edma: Fix invalid interleaved xfers semantics dmaengine: dw-edma: Don't permit non-inc interleaved xfers dmaengine: dw-edma: Fix missing src/dst address of interleaved xfers dmaengine: dw-edma: Convert ll/dt phys address to PCI bus/DMA address dmaengine: dw-edma: Release requested IRQs on failure dmaengine: Fix dma_slave_config.dst_addr description
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