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path: root/drivers/pci/pcie
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* Revert "PCI/ASPM: Refactor L1 PM Substates Control Register programming"Bjorn Helgaas2023-02-101-40/+34
* Revert "PCI/ASPM: Save L1 PM Substates Capability for suspend/resume"Bjorn Helgaas2023-02-101-37/+0
* Merge tag 'pci-v6.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2022-12-145-286/+264
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| * Merge branch 'pci/portdrv'Bjorn Helgaas2022-12-104-284/+256
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| | * PCI/portdrv: Allow AER service only for Root Ports & RCECsBjorn Helgaas2022-12-101-1/+3
| | * PCI/portdrv: Unexport pcie_port_service_register(), pcie_port_service_unregis...Bjorn Helgaas2022-10-241-2/+0
| | * PCI/portdrv: Move private things to portdrv.cBjorn Helgaas2022-10-242-9/+9
| | * PCI/portdrv: Squash into portdrv.cBjorn Helgaas2022-10-244-272/+244
| * | PCI/portdrv: Set PCIE_PORT_SERVICE_HP for Root and Downstream Ports onlyRafael J. Wysocki2022-11-221-0/+2
| * | PCI: pciehp: Enable by default if USB4 enabledAlbert Zhou2022-11-151-2/+6
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* / PCI/AER: Add optional logging callback for correctable errorDave Jiang2022-12-031-1/+7
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* Merge branch 'pci/pm'Bjorn Helgaas2022-10-051-130/+170
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| * PCI/PTM: Reorder functions in logical orderBjorn Helgaas2022-09-121-62/+62
| * PCI/PTM: Preserve RsvdP bits in PTM Control registerBjorn Helgaas2022-09-121-11/+14
| * PCI/PTM: Move pci_ptm_info() body into its only callerBjorn Helgaas2022-09-121-21/+17
| * PCI/PTM: Add pci_suspend_ptm() and pci_resume_ptm()Bjorn Helgaas2022-09-121-14/+57
| * PCI/PTM: Separate configuration and enableBjorn Helgaas2022-09-121-55/+49
| * PCI/PTM: Add pci_upstream_ptm() helperBjorn Helgaas2022-09-121-14/+25
| * PCI/PTM: Cache PTM Capability offsetBjorn Helgaas2022-09-121-24/+17
* | Merge branch 'pci/dpc'Bjorn Helgaas2022-10-051-5/+10
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| * | PCI/DPC: Quirk PIO log size for certain Intel Root PortsMika Westerberg2022-09-271-5/+10
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* | PCI/ASPM: Correct LTR_L1.2_THRESHOLD computationBjorn Helgaas2022-10-051-17/+32
* | PCI/ASPM: Ignore L1 PM Substates if device lacks capabilityBjorn Helgaas2022-10-051-0/+3
* | PCI/ASPM: Factor out L1 PM Substates configurationBjorn Helgaas2022-10-051-48/+55
* | PCI/ASPM: Save L1 PM Substates Capability for suspend/resumeVidya Sagar2022-10-041-0/+37
* | PCI/ASPM: Refactor L1 PM Substates Control Register programmingVidya Sagar2022-10-041-34/+40
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* Merge branch 'pci/err'Bjorn Helgaas2022-08-043-16/+20
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| * PCI/AER: Iterate over error counters instead of error stringsMohamed Khalfella2022-07-131-1/+6
| * PCI/AER: Enable error reporting when AER is nativeStefan Roese2022-07-131-0/+3
| * PCI/portdrv: Don't disable AER reporting in get_port_device_capability()Stefan Roese2022-07-131-8/+1
| * PCI/AER: Configure ECRC for every deviceStefan Roese2022-07-111-3/+2
| * PCI/ERR: Recognize disconnected devices in report_error_detected()Christoph Hellwig2022-06-081-4/+8
* | PCI/ASPM: Unexport pcie_aspm_support_enabled()Bjorn Helgaas2022-07-121-1/+0
* | PCI/ASPM: Remove pcie_aspm_pm_state_change()Kai-Heng Feng2022-07-121-19/+0
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* Merge tag 'iommu-updates-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2022-05-311-0/+2
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| * PCI: portdrv: Set driver_managed_dmaLu Baolu2022-04-281-0/+2
* | PCI/AER: Clear MULTI_ERR_COR/UNCOR_RCV bitsKuppuswamy Sathyanarayanan2022-05-171-1/+6
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* Merge tag 'pci-v5.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds2022-03-253-4/+4
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| * Merge branch 'pci/misc'Bjorn Helgaas2022-03-222-2/+2
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| | * PCI/AER: Update aer-inject URLYicong Yang2022-03-022-2/+2
| * | PCI: Add defines for normal and subtractive PCI bridgesPali Rohár2022-02-171-2/+2
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* / Revert "PCI/portdrv: Do not setup up IRQs if there are no users"Bjorn Helgaas2022-02-111-30/+17
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* Merge branch 'pci/errors'Bjorn Helgaas2022-01-132-4/+4
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| * PCI/PME: Use PCI_POSSIBLE_ERROR() to check config readsNaveen Naidu2021-11-181-2/+2
| * PCI/DPC: Use PCI_POSSIBLE_ERROR() to check config readsNaveen Naidu2021-11-181-2/+2
* | Merge branch 'pci/enumeration'Bjorn Helgaas2022-01-131-0/+1
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| * | PCI: Use DWORD accesses for LTR, L1 SS to avoid erratumRajat Jain2022-01-111-0/+1
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* | PCI/ASPM: Remove struct aspm_latencySaheed O. Bolarinwa2021-11-191-19/+13
* | PCI/ASPM: Stop caching device L0s, L1 acceptable exit latenciesSaheed O. Bolarinwa2021-11-191-19/+10
* | PCI/ASPM: Stop caching link L0s, L1 exit latenciesSaheed O. Bolarinwa2021-11-191-11/+17
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