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| * | Merge branch 'remotes/lorenzo/pci/keystone'Bjorn Helgaas2019-05-1314-379/+870
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move IRQ register address computation inside macros (Kishon Vijay Abraham I) - Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I) - Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham I) - Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon Vijay Abraham I) - Add dwc support for platforms with custom MSI controllers (Kishon Vijay Abraham I) - Add keystone-specific MSI controller (Kishon Vijay Abraham I) - Remove dwc host_ops previously used for keystone-specific MSI (Kishon Vijay Abraham I) - Skip dwc default MSI init if platform has custom MSI controller (Kishon Vijay Abraham I) - Implement .start_link() and .stop_link() for keystone endpoint support (Kishon Vijay Abraham I) - Add keystone "reg-names" DT binding (Kishon Vijay Abraham I) - Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon Vijay Abraham I) - Get keystone register resources from DT by name, not index (Kishon Vijay Abraham I) - Get DT resources in .probe() to prepare for endpoint support (Kishon Vijay Abraham I) - Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration (Kishon Vijay Abraham I) - Explicitly set keystone to host mode (Kishon Vijay Abraham I) - Document DT "atu" reg-names requirement for DesignWare core >= 4.80 (Kishon Vijay Abraham I) - Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon Vijay Abraham I) - Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon Vijay Abraham I) - Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham I) - Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham I) - Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I) - Reset keystone PHYs before enabling them (Kishon Vijay Abraham I) - Make of_pci_get_max_link_speed() available to endpoint drivers as well as host drivers (Kishon Vijay Abraham I) - Add keystone support for DT "max-link-speed" property (Kishon Vijay Abraham I) - Add endpoint library support for BAR buffer alignment (Kishon Vijay Abraham I) - Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I) - Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay Abraham I) - Add dwc hooks for dbi/dbi2 that share the same address space (Kishon Vijay Abraham I) - Add keystone support for TI AM654x in endpoint mode (Kishon Vijay Abraham I) - Configure designware endpoints to advertise smallest resizable BAR (1MB) (Kishon Vijay Abraham I) - Align designware endpoint ATU windows for raising MSIs (Kishon Vijay Abraham I) - Add endpoint test support for TI AM654x (Kishon Vijay Abraham I) - Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test misc: pci_endpoint_test: Add support to test PCI EP in AM654x PCI: designware-ep: Use aligned ATU window for raising MSI interrupts PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size PCI: keystone: Add support for PCIe EP in AM654x Platforms dt-bindings: PCI: Add PCI EP DT binding documentation for AM654 PCI: dwc: Add callbacks for accessing dbi2 address space PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops PCI: endpoint: Add support to specify alignment for buffers allocated to BARs PCI: keystone: Add support to set the max link speed from DT PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers PCI: keystone: Invoke phy_reset() API before enabling PHY PCI: keystone: Add support for PCIe RC in AM654x Platforms dt-bindings: PCI: Add PCI RC DT binding documentation for AM654 PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 PCI: dwc: Fix ATU identification for designware version >= 4.80 PCI: dwc: Enable iATU unroll for endpoint too dt-bindings: PCI: Document "atu" reg-names PCI: keystone: Explicitly set the PCIe mode dt-bindings: PCI: Add dt-binding to configure PCIe mode PCI: keystone: Move resources initialization to prepare for EP support PCI: keystone: Use platform_get_resource_byname() to get memory resources PCI: keystone: Perform host initialization in a single function dt-bindings: PCI: keystone: Add "reg-names" binding information PCI: keystone: Cleanup error_irq configuration PCI: keystone: Add start_link()/stop_link() dw_pcie_ops PCI: dwc: Remove default MSI initialization for platform specific MSI chips PCI: dwc: Remove Keystone specific dw_pcie_host_ops PCI: keystone: Use Keystone specific msi_irq_chip PCI: dwc: Add support to use non default msi_irq_chip PCI: keystone: Cleanup ks_pcie_msi_irq_handler() PCI: keystone: Use hwirq to get the MSI IRQ number offset PCI: keystone: Add separate functions for configuring MSI and legacy interrupt PCI: keystone: Cleanup interrupt related macros # Conflicts: # drivers/pci/controller/dwc/pcie-designware.h
| | * | PCI: designware-ep: Use aligned ATU window for raising MSI interruptsKishon Vijay Abraham I2019-05-011-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configure an aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest sizeKishon Vijay Abraham I2019-05-011-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the Resizable BAR capability to advertise the smallest size (1MB) for a couple of reasons: - Host side resource allocation of BAR fails for larger sizes - Endpoint function driver does not allocate memory for all supported sizes in the Resizable BAR capability. If and when there is a usecase required to add more flexibility using the Resizable BAR capability, this can be revisited. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Add support for PCIe EP in AM654x PlatformsKishon Vijay Abraham I2019-05-012-37/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe EP support for AM654x Platforms in pci-keystone.c Link: https://lore.kernel.org/linux-pci/20190325093947.32633-15-kishon@ti.com/ Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: made dev_vdbg() call a comment] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: dwc: Add callbacks for accessing dbi2 address spaceKishon Vijay Abraham I2019-04-162-2/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain platforms like TI's AM654 do not have aseparate address space for dbi2 instead they are accessed using the same address space as dbi with some configuration bit set. In order to support such platforms, add callbacks for accessing dbi2 address space. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offsetKishon Vijay Abraham I2019-04-161-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability() and __dw_pcie_ep_find_next_cap() for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present because of incorrect ordering of the "next_cap_ptr" check. Fix it. Fixes: beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: dwc: Add const qualifier to struct dw_pcie_ep_opsKishon Vijay Abraham I2019-04-155-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add const qualifier to struct dw_pcie_ep_ops member of struct dw_pcie_ep. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: endpoint: Add support to specify alignment for buffers allocated to BARsKishon Vijay Abraham I2019-04-152-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The address that is allocated using pci_epf_alloc_space() is directly written to the target address of the Inbound Address Translation unit (ie the HW component implementing inbound address decoding) on endpoint controllers. Designware IP [1] has a configuration parameter (CX_ATU_MIN_REGION_SIZE [2]) which has 64KB as default value and the lower 16 bits of the Base, Limit and Target registers of the Inbound ATU are fixed to zero. If the programmed memory address is not aligned to 64 KB boundary this causes memory corruption. Modify pci_epf_alloc_space() API to take alignment size as argument in order to allocate buffers to be mapped to BARs with an alignment that suits the platform where they are used. Add an 'align' parameter to epc_features which can be used by platform drivers to specify the BAR allocation alignment requirements and use this while invoking pci_epf_alloc_space(). [1] "I/O and MEM Match Modes" section in DesignWare Cores PCI Express Controller Databook version 4.90a [2] http://www.ti.com/lit/ug/spruid7c/spruid7c.pdf Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Add support to set the max link speed from DTKishon Vijay Abraham I2019-04-151-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe in TI's AM654 devices is by default configured to work in GEN3 mode. However PCIe does not work reliably in GEN3 mode because of SERDES configuration. Add support to set the link speed to GEN1, GEN2 or GEN3 based on "max-link-speed" DT property with GEN2 as the default speed if "max-link-speed" is absent. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint driversKishon Vijay Abraham I2019-04-152-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled. Make of_pci_get_max_link_speed() to be also used by PCI Endpoint controllers with just CONFIG_PCI_ENDPOINT enabled. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: keystone: Invoke phy_reset() API before enabling PHYKishon Vijay Abraham I2019-04-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SERDES connected to the PCIe controller in AM654 requires power on reset enable (POR_EN) to be set in the SERDES. The SERDES driver sets POR_EN in the reset ops and it has to be invoked before init or enable ops. In order for SERDES driver to set POR_EN, invoke the phy_reset() API in pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Add support for PCIe RC in AM654x PlatformsKishon Vijay Abraham I2019-04-152-15/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe RC support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64Kishon Vijay Abraham I2019-04-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hook_fault_code() is an ARM32 specific API for hooking into data abort. AM65X platforms (that integrate ARM v8 cores and select CONFIG_ARM64 as arch) rely on pci-keystone.c but on them the enumeration of a non-present BDF does not trigger a bus error, so the fixup exception provided by calling hook_fault_code() is not needed and can be guarded with CONFIG_ARM. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: dwc: Fix ATU identification for designware version >= 4.80Kishon Vijay Abraham I2019-04-152-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which have not populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: dwc: Enable iATU unroll for endpoint tooKishon Vijay Abraham I2019-04-153-23/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iatu_unroll_enabled flag is set only for Designware in host mode. However iATU unroll can be applicable for endpoint mode too. Set iatu_unroll_enabled flag in dw_pcie_setup() which is common for both host mode and endpoint mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Explicitly set the PCIe modeKishon Vijay Abraham I2019-04-151-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always relying on the default values. This is required when EP mode has to be explicitly written to BOOTCFG_DEVCFG register. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Move resources initialization to prepare for EP supportKishon Vijay Abraham I2019-04-151-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform_get_resource() calls for resources that are applicable to both host and endpoint mode (ie "dbics" and "app") from ks_add_pcie_port() to the probe() callback, in preparation for adding endpoint support to pci-keystone driver. No functional change intended. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Use platform_get_resource_byname() to get memory resourcesKishon Vijay Abraham I2019-04-111-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use platform_get_resource_byname() instead of platform_get_resource() which uses an index to get memory resources. While at that get the memory resource defined specifically for configuration space instead of deriving the configuration space address from dbics address space. Since the pci-keystone driver has never worked in the mainline kernel, DT backward compatibility is not an issue. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Perform host initialization in a single functionKishon Vijay Abraham I2019-04-111-40/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change. Instead of having two functions ks_pcie_add_pcie_port() and ks_pcie_dw_host_init() for initializing host, have a single function to perform all the host initialization. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Cleanup error_irq configurationKishon Vijay Abraham I2019-04-111-26/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci-keystone driver uses irq_of_parse_and_map() to get irq number of error_irq. Use platform_get_irq() instead and move platform_get_irq() and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe since error_irq is common to both RC mode and EP mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Add start_link()/stop_link() dw_pcie_opsKishon Vijay Abraham I2019-04-111-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add start_link()/stop_link() dw_pcie_ops and invoke ks_pcie_start_link() directly from host_init. start_link()/stop_link() ops are required for adding EP mode support. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: dwc: Remove default MSI initialization for platform specific MSI chipsKishon Vijay Abraham I2019-04-041-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platforms which populate msi_host_init() have their own MSI controller logic. Writing to MSI control registers on platforms which do not use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses its own MSI controller logic instead of Designware's MSI one. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: dwc: Remove Keystone specific dw_pcie_host_opsKishon Vijay Abraham I2019-04-042-41/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that Keystone started using its own msi_irq_chip, remove Keystone specific callback functions defined in dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Use Keystone specific msi_irq_chipKishon Vijay Abraham I2019-04-042-27/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use Keystone specific msi_irq_chip to configure the MSI controller logic in the PCIe keystone wrapper instead of using the default Designware msi_irq chip (dw_pci_msi_bottom_irq_chip) with callback functions for configuring the Keystone MSI controller. This will help to remove Keystone specific callback functions added in dw_pcie_host_ops. Move the default msi_irq_chip assignment to dw_pcie_host_init since platforms that doesn't use the default msi_irq_chip will assign msi_irq_chip in the msi_host_init() callback. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: dwc: Add support to use non default msi_irq_chipKishon Vijay Abraham I2019-04-042-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platforms using DesignWare IP use dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the DesignWare IP. However certain platforms like Keystone (K2G) which uses DesignWare IP have their own MSI controller logic. For handling such platforms, the irqchip ops use msi_irq_ack(), msi_set_irq(), msi_clear_irq() callback functions. Add support to use different msi_irq_chip with default set to dw_pci_msi_bottom_irq_chip. This is in preparation to get rid of msi_irq_ack(), msi_set_irq(), msi_clear_irq() and other Keystone specific dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Cleanup ks_pcie_msi_irq_handler()Kishon Vijay Abraham I2019-04-041-36/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ks_pcie_msi_irq_handler() invokes ks_pcie_handle_msi_irq() for handling the interrupts. Having two functions for handling the interrupt was used when keystone PCIe driver was implemented using two files but with commit b492aca35c98 ("PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c"), which merged the keystone PCIe driver to use a single file, two functions for handling the interrupt handler are not required. Handle MSI interrupt in a single interrupt handler here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Use hwirq to get the MSI IRQ number offsetKishon Vijay Abraham I2019-04-041-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ks_pcie_msi_irq_handler() uses 'virq' to get the IRQ number offset. This offset is used to get the correct MSI_IRQ_STATUS register corresponding to the IRQ line that raised the interrupt. There is no guarantee that 'virq' assigned for consecutive hardware IRQ will be contiguous and this might get us an incorrect IRQ number offset. Fix it here by using 'hwirq' to get the IRQ number offset. Since we don't store the 'virq' numbers of all the IRQ numbers, stop checking if irq count is greater than MAX_MSI_HOST_IRQS and remove MAX_MSI_HOST_IRQS. Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d838c@arm.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Add separate functions for configuring MSI and legacy interruptKishon Vijay Abraham I2019-04-041-92/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ks_pcie_get_irq_controller_info() is used to configure both MSI and legacy interrupt. This will prevent MSI or legacy interrupt specific intializations. Add separate functions to configure MSI and legacy interrupts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: keystone: Cleanup interrupt related macrosKishon Vijay Abraham I2019-04-041-13/+13
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | No functional change. Change both MSI interrupt and legacy interrupt related macros to take an additional argument in order to return the correct register offset. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | Merge branch 'remotes/lorenzo/pci/iproc'Bjorn Helgaas2019-05-131-5/+41
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Work around iproc CRS completion issues (Srinath Mannam) - Allow smaller iproc outbound windows so driver can work on 32-bit systems (Srinath Mannam) - Use iproc-specific config read for PAXBv2 (not PAXB) (Srinath Mannam) * remotes/lorenzo/pci/iproc: PCI: iproc: Enable iProc config read for PAXBv2 PCI: iproc: Allow outbound configuration for 32-bit I/O region PCI: iproc: Add CRS check in config read
| | * | PCI: iproc: Enable iProc config read for PAXBv2Srinath Mannam2019-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iProc config read flag has to be enabled for PAXBv2 instead of PAXB. Fixes: f78e60a29d4f ("PCI: iproc: Reject unconfigured physical functions from PAXC") Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
| | * | PCI: iproc: Allow outbound configuration for 32-bit I/O regionSrinath Mannam2019-04-031-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IProc host controller has I/O memory windows allocated in the AXI memory map that can be used to address PCI I/O memory space. Mapping from AXI memory windows to PCI outbound memory windows is carried out in the host controller through OARR/OMAP registers pairs that permit to define power of two region size AXI<->PCI mappings, the smallest of which is 128MB. Current code enables AXI memory window to PCI outbound memory window mapping only for AXI windows matching one of the OARR/OMAP window sizes, that are SoC dependent and the smallest of which is 128MB. Some SoCs implementing the IProc host controller have a 32-bit AXI memory window into PCI I/O memory space, eg: Base address | Size ----------------------------- (1) 0x42000000 | 0x2000000 (2) 0x400000000 | 0x80000000 but its size (32MB - (1) above) is smaller than the smallest AXI<->PCI region size provided by OARR (128MB), so the current driver rejects mappings for the 32-bit region making the IProc host controller driver unusable on 32-bit systems. However, there is no reason why the 32-bit I/O memory window cannot be enabled by mapping it through an OARR/OMAP region bigger in size (ie 32-bit AXI window size is 32MB but can be mapped using a 128MB OARR/OMAP region). Allow outbound window configuration of I/O memory windows that are smaller in size than the host controller OARR/OMAP region, so that the 32-bit AXI memory window can actually be enabled, making the IProc host controller operational on 32-bit systems. Link: https://lore.kernel.org/linux-pci/1551415936-30174-3-git-send-email-srinath.mannam@broadcom.com/ Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> [lorenzo.pieralisi@arm.com: rewrote the commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Scott Branden <scott.branden@broadcom.com>
| | * | PCI: iproc: Add CRS check in config readSrinath Mannam2019-04-031-2/+21
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IPROC PCIe host controller implementation returns CFG_RETRY_STATUS (0xffff0001) data when it receives a CRS completion, regardless of the address of the read or the CRS Software Visibility Enable bit. As a workaround the driver retries in software any read that returns CFG_RETRY_STATUS even though, for reads of registers that are not Vendor ID, the register value can correspond to CFG_RETRY_STATUS; this situation would cause a timeout and failure of reading a valid register value. IPROC PCIe host controller PAXB v2 has a register to show config read status flags like SC, UR, CRS and CA. Using this status flag, an extra check is added to confirm the CRS using status flags before reissuing a config read, fixing the issue. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> [lorenzo.pieralisi@arm.com: rewrote commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Scott Branden <scott.branden@broadcom.com>
| * | Merge branch 'remotes/lorenzo/pci/imx'Bjorn Helgaas2019-05-133-96/+62
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Simplify imx7d_pcie_wait_for_phy_pll_lock() by using regmap_read_poll_timeout() (Andrey Smirnov) - Drop imx6_pcie_wait_for_link() in favor of the more generic dw_pcie_wait_for_link() (Andrey Smirnov) - Return -ETIMEDOUT instead of -EINVAL from imx6_pcie_wait_for_speed_change() (Andrey Smirnov) - Remove unused PCIE_PL_PFLR_* constants from imx6 (Andrey Smirnov) - Use shared PHY debug register definitions in imx6 (Andrey Smirnov) - Use BIT() in imx6 (Andrey Smirnov) - Simplify imx6 PHY bit operations (Andrey Smirnov) - Simplify imx6 pcie_phy_poll_ack() (Andrey Smirnov) - Use data types that match actual imx6 PHY register width (Andrey Smirnov) - Mark imx6 suspend support with drvdata flags instead of checking variants (Andrey Smirnov) - Sleep instead of delay in imx6_pcie_enable_ref_clk() (Andrey Smirnov) * remotes/lorenzo/pci/imx: PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk() PCI: imx6: Use flags to indicate support for suspend PCI: imx6: Restrict PHY register data to 16-bit PCI: imx6: Simplify pcie_phy_poll_ack() PCI: imx6: Simplify bit operations in PHY functions PCI: imx6: Make use of BIT() in constant definitions PCI: dwc: imx6: Share PHY debug register definitions PCI: imx6: Remove PCIE_PL_PFLR_* constants PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change() PCI: imx6: Drop imx6_pcie_wait_for_link() PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()
| | * | PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk()Andrey Smirnov2019-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | imx6_pcie_enable_ref_clk() is never called in atomic context, so there's no need to use udelay(). Replace it with usleep_range(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Use flags to indicate support for suspendAndrey Smirnov2019-05-011-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that driver data has flags variable that can be used to indicate quirks/features supported we can switch the code to use it instead of having a special function that does so based on variant alone. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Restrict PHY register data to 16-bitAndrey Smirnov2019-05-011-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PHY registers on i.MX6 are 16-bit wide, so we can get rid of explicit masking if we restrict pcie_phy_read()/pcie_phy_write() to use 'u16' instead of 'int'. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Simplify pcie_phy_poll_ack()Andrey Smirnov2019-05-011-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify pcie_phy_poll_ack() by incorporating shifting into constant definition and convert the code to use 'bool'. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Simplify bit operations in PHY functionsAndrey Smirnov2019-05-011-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the code by incorporating left shifts into constant definitions as well as using FIELD_PREP/GENMASK. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Make use of BIT() in constant definitionsAndrey Smirnov2019-05-011-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid using explicit left shifts and convert various definitions to use BIT() instead. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: dwc: imx6: Share PHY debug register definitionsAndrey Smirnov2019-05-013-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both pcie-designware.c and pci-imx6.c contain custom definitions for PHY debug registers R0/R1 and on top of that there's already a definition for R0 in pcie-designware.h. Move all of the definitions to pcie-designware.h. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Remove PCIE_PL_PFLR_* constantsAndrey Smirnov2019-05-011-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code using these constants was removed in commit a71280722eeb ("PCI: imx6: Remove LTSSM disable workaround"). No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change()Andrey Smirnov2019-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change error code from -EINVAL to -ETIMEDOUT in imx6_pcie_wait_for_speed_change() since that error code seems more appropriate. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Drop imx6_pcie_wait_for_link()Andrey Smirnov2019-05-011-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All calls to imx6_pcie_wait_for_link() share the same error path and the state of PHY debug registers will already be printed there, so there's no real reason we can't just use dw_pcie_wait_for_link(). Drop imx6_pcie_wait_for_link() and replace it with dw_pcie_wait_for_link(). Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| | * | PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()Andrey Smirnov2019-05-011-14/+7
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make use of regmap_read_poll_timeout() to simplify imx7d_pcie_wait_for_phy_pll_lock(). No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| * | Merge branch 'pci/dwc'Bjorn Helgaas2019-05-134-45/+41
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use generic config space reader in qcom (Marc Gonzalez) - Stop calling IRQ handler cleanup in dwc driver for invalid MSI IRQs (Jisheng Zhang) - Free dwc MSI target page when freeing MSI (Jisheng Zhang) - Fix dwc MSI leak in host init error path (Jisheng Zhang) - Use managed host bridge alloc to simplify dwc (Jisheng Zhang) - Save dwc root pci_bus pointer for use by .remove() methods (Jisheng Zhang) - Allow imx6 asynchronous probing (Lucas Stach) * pci/dwc: PCI: imx6: Allow asynchronous probing PCI: dwc: Save root bus for driver remove hooks PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code PCI: dwc: Free MSI in dw_pcie_host_init() error path PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi() PCI: dwc: Fix dw_pcie_free_msi() if msi_irq is invalid PCI: qcom: Use default config space read function
| | * | PCI: imx6: Allow asynchronous probingLucas Stach2019-05-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Establishing a PCIe link can take a while; allow asynchronous probing so that link establishment can happen in the background while other devices are being probed. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| | * | PCI: dwc: Save root bus for driver remove hooksJisheng Zhang2019-05-072-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently DWC host does not support the remove callback, but nothing prevents us from supporting it. Save the root bus for clean up work in driver remove code paths to allow DWC host drivers to implement their remove hook as, eg: static int foo_pcie_remove(struct platform_device *pdev) { ... pci_stop_root_bus(pp->root_bus); pci_remove_root_bus(pp->root_bus); dw_pcie_free_msi(pp); ... } Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
| | * | PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify codeJisheng Zhang2019-05-071-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use devm_pci_alloc_host_bridge() to simplify the error code path. This also fixes a leak in the dw_pcie_host_init() error path. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> CC: stable@vger.kernel.org # v4.13+
| | * | PCI: dwc: Free MSI in dw_pcie_host_init() error pathJisheng Zhang2019-05-071-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we ever did MSI-related initializations, we need to call dw_pcie_free_msi() in the error code path. Remove the IS_ENABLED(CONFIG_PCI_MSI) check for MSI init because pci_msi_enabled() already has a stub for !CONFIG_PCI_MSI. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-19 21:35:33 +0000