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* phy: cadence: Sierra: add phy_reset hookRoger Quadros2020-01-141-0/+10
| | | | | | | | | | | | Some platforms e.g. J721e need lane swap register to be programmed before reset is deasserted. This patch ensures that we propagate the phy_reset back to the reset controller driver. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: remove redundant initialization of pointer regmapColin Ian King2020-01-141-1/+1
| | | | | | | | | | | The pointer regmap is being initialized with a value that is never read and it is being updated later with a new value from phy->regmap_common_cdb. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Kishon Vijay Abraham I2020-01-081-1/+1
| | | | | | | commit 44d30d622821d3b ("phy: cadence: Add driver for Sierra PHY"), incorrectly used parent device pointer to get driver data. Fix it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency ↵Kishon Vijay Abraham I2020-01-081-0/+21
| | | | | | | | | | | | | | to 25MHz Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz as specified in "Common Module Clock Configurations" of the Cadence Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz since the only user of Cadence Sierra SERDES, TI J721E SoC provides input clock frequency of 100MHz. For other frequencies, cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured based on the "Common Module Clock Configurations". Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Kishon Vijay Abraham I2020-01-081-1/+21
| | | | | | | | Sierra SERDES IP supports upto 16 lanes (though not all of it will be enabled in a platform). Allow Sierra driver to support a maximum of upto 16 lanes. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Check for PLL lock during PHY power onKishon Vijay Abraham I2020-01-081-1/+32
| | | | | | Check for PLL lock during PHY power on. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Get reset control "array" for each linkKishon Vijay Abraham I2020-01-081-1/+1
| | | | | | | | A link may have multiple lanes each with a separate reset. Get reset control "array" in order to reset all the lanes associated with the link. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ↵Anil Varughese2020-01-081-96/+254
| | | | | | | | | | | | external SSC The existing configuration done in Cadence Sierra driver is only for reference and is not used in any platforms. Remove them and configure both lane cdb and common cdb registers to be used with external SSC configuration. This is validated in TI J721E platform. Signed-off-by: Anil Varughese <aniljoy@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Modify register macro names to be in sync with Sierra ↵Kishon Vijay Abraham I2020-01-081-83/+84
| | | | | | | | | user guide No functional change. Modify register offset macro names to be in sync with Sierra user guide. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_opsKishon Vijay Abraham I2020-01-081-6/+9
| | | | | | | | Instead of invoking cdns_sierra_phy_init() from probe, add it in phy_ops so that it's initialized when the PHY consumer invokes phy_init() Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoCKishon Vijay Abraham I2020-01-081-0/+14
| | | | | | | SERDES_16G in TI's J721E SoC uses Cadence Sierra PHY. Add support to use Cadence Sierra driver in J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Use "regmap" for read and write to Sierra registersKishon Vijay Abraham I2020-01-081-54/+237
| | | | | | | | Use "regmap" for read and write to Sierra registers. This is in perparation for adding SERDES_16G support present in TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resourcesKishon Vijay Abraham I2020-01-081-2/+2
| | | | | | | | Certain platforms like TI J721E using Cadence Sierra Serdes doesn't provide explicit phy_clk and reset (APB reset) control. Make them optional here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence: Add driver for Sierra PHYAlan Douglas2018-12-121-0/+395
Add a Sierra PHY driver with PCIe and USB support. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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