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* phy: phy-mtk-tphy: add a new reference clockChunfeng Yun2020-03-201-1/+18
| | | | | | | | | | | Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: remove unused u3phya_ref clockChunfeng Yun2020-03-201-18/+0
| | | | | | | | | The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it, this can avoid confusion when support new platforms Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: make the ref clock optionalChunfeng Yun2020-03-201-1/+1
| | | | | | | | | Sometimes the reference clock of USB3 PHY comes from oscillator directly, and no need refer to a fixed-clock in DTS anymore if make it optional. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: add a property for internal resistanceChunfeng Yun2020-03-201-2/+14
| | | | | | | | | This is used to tune J-K voltage by internal R (resistance), the range is [0, 31], the resistance value is about 6.9K ohm for 0, 3.8K ohm for 31, and the step is 1K ohm Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: add a property for disconnect thresholdChunfeng Yun2020-03-201-2/+15
| | | | | | | | | This is used to tune the threshold of disconnect, the index range is [0, 15], the threshold voltage is about 400mV for 0, 700mV for 15, and the step is 20mV. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: Enable compile testing for some of driversKrzysztof Kozlowski2020-01-141-3/+6
| | | | | | | | | Some of the phy drivers can be compile tested to increase build coverage. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: mediatek: Fix Kconfig indentationKrzysztof Kozlowski2020-01-141-10/+10
| | | | | | | | | | Adjust indentation from spaces to tab (+optional two spaces) as in coding style. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
| | | | | | | | | | | | | | Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* scsi: phy: mediatek: fix typo in author's email addressColin Ian King2019-04-181-1/+1
| | | | | | | | | | There is a typo in the module author's email address. Fix this. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: get optional clock by devm_clk_get_optional()Chunfeng Yun2019-04-171-7/+3
| | | | | | | Use devm_clk_get_optional() to get optional clock Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: mediatek: Add UFS M-PHY driverStanley Chu2019-04-173-0/+256
| | | | | | | | Add UFS M-PHY driver on MediaTek chipsets. Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: core: rework phy_set_mode to accept phy mode and submodeGrygorii Strashko2018-12-122-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the attempt to add support for Ethernet interface mode PHY (MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and duplicate there values from phy_interface_t enum (or introduce more PHY callbacks) [1]. Both approaches are ineffective and would lead to fast bloating of enum phy_mode or struct phy_ops in the process of adding more PHYs for different subsystems which will make them unmaintainable. As discussed in [1] the solution could be to introduce dual level PHYs mode configuration - PHY mode and PHY submode. The PHY mode will define generic PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem specific interface mode. The last is usually already defined in corresponding subsystem headers (phy_interface_t for Ethernet, enum usb_device_speed for USB). This patch is cumulative change which refactors PHY framework code to support dual level PHYs mode configuration - PHY mode and PHY submode. It extends .set_mode() callback to support additional parameter "int submode" and converts all corresponding PHY drivers to support new .set_mode() callback declaration. The new extended PHY API int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) is introduced to support dual level PHYs mode configuration and existing phy_set_mode() API is converted to macros, so PHY framework consumers do not need to be changed (~21 matches). [1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: add property for BC12Chunfeng Yun2018-07-101-0/+13
| | | | | | | | Some platforms support BC12 which is disabled by default, here add a property to enable it if need Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: add properties for eye diagram testChunfeng Yun2018-07-101-0/+62
| | | | | | | | Add properties for Eye diagram test of HQA which sometimes need adjust some parameters of u2phy Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: use SPDX license tagChunfeng Yun2018-07-102-9/+2
| | | | | | | Use SPDX-License-Identifier tag instead of the GPL license text Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: mediatek: add XS-PHY driverChunfeng Yun2018-05-203-0/+610
| | | | | | | Support XS-PHY for MediaTek SoCs with USB3.1 GEN2 controller Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: add configurable parameters for slew rate calibrateChunfeng Yun2018-03-161-5/+15
| | | | | | | | | | There are two parameters, ref_clk and coefficient, for U2 slew rate calibrate which may vary on different SoCs, here allow them to be configurable Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: keep default value of mcu_bus_ck_gate_enChunfeng Yun2018-03-161-2/+1
| | | | | | | | | The default value of mcu_bus_ck_gate_en is 1, if clear it, will prevent system to enter deep idle mode, so keep its default value and without affecting PCIe function. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: use of_device_get_match_data()Chunfeng Yun2017-12-291-6/+5
| | | | | | | reduce the boilerplate code to get the specific data Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: make shared banks optional for V1 TPHYChunfeng Yun2017-12-291-2/+3
| | | | | | | | V1 TPHY for SATA doesn't have shared banks if it isn't shared with PCIe or USB, so make it optional. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: use auto instead of force to bypass utmi signalsChunfeng Yun2017-12-291-12/+7
| | | | | | | | | | | When system is running, if usb2 phy is forced to bypass utmi signals, all PLL will be turned off, and it can't detect device connection anymore, so replace force mode with auto mode which can bypass utmi signals automatically if no device attached for normal flow. But keep the force mode to fix RX sensitivity degradation issue. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: add set_mode callbackChunfeng Yun2017-10-231-0/+39
| | | | | | | | This is used to force PHY with USB OTG function to enter a specific mode, and override OTG IDPIN(or IDDIG) signal. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mtk-tphy: fix NULL point of chip bankChunfeng Yun2017-09-261-1/+2
| | | | | | | | | Chip bank of version-1 is initialized as NULL, but it's used by pcie_phy_instance_power_on/off(), so assign it a right address. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-mt65xx-usb3: add mediatek directory and rename fileChunfeng Yun2017-08-203-0/+1100
The driver is actually for T-PHY which supports USB3.0, PCIe and SATA, and supports more SoCs now, but not just only for series of mt65xx SoCs, so the name of file, data struct, functions etc with 'mt65xx' may cause misunderstanding when new SoCs are supported. Here rename them to reflect the real functions and also enhance readability. And also update MAINTAINERS file to reflect the correct driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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