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| * phy: zynqmp: Only wait for PLL lock "primary" instancesSean Anderson2024-07-021-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: zynqmp: Store instance instead of typeSean Anderson2024-07-021-84/+31
| | | | | | | | | | | | | | | | | | | | The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-3-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: zynqmp: Enable reference clock correctlySean Anderson2024-07-021-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lanes can use other lanes' reference clocks, as determined by refclk. Use refclk to determine the clock to enable/disable instead of always using the lane's own reference clock. This ensures the clock selected in xpsgtr_configure_pll is the one enabled. For the other half of the equation, always program REF_CLK_SEL even when we are selecting the lane's own clock. This ensures that Linux's idea of the reference clock matches the hardware. We use the "local" clock mux for this instead of going through the ref clock network. Fixes: 25d700833513 ("phy: xilinx: phy-zynqmp: dynamic clock support for power-save") Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence-torrent: Check return value on register readMa Ke2024-07-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | cdns_torrent_dp_set_power_state() does not consider that ret might be overwritten. Add return value check of regmap_read_poll_timeout() after register read in cdns_torrent_dp_set_power_state(). Fixes: 5b16a790f18d ("phy: cadence-torrent: Reorder few functions to remove function declarations") Signed-off-by: Ma Ke <make24@iscas.ac.cn> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240702032042.3993031-1-make24@iscas.ac.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: Fix the cacography in phy-exynos5250-usb2.cLiu Jing2024-07-021-1/+1
| | | | | | | | | | | | | | | | The word 'swtich' is wrong, so fix it. Signed-off-by: Liu Jing <liujing@cmss.chinamobile.com> Link: https://lore.kernel.org/r/20240701112517.6597-1-liujing@cmss.chinamobile.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCONCristian Ciocaltea2024-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compile testing configurations without REGMAP support enabled results in a bunch of errors being reported: ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:569:21: error: variable ‘rk_hdptx_phy_regmap_config’ has initializer but incomplete type 569 | static const struct regmap_config rk_hdptx_phy_regmap_config = { | ^~~~~~~~~~~~~ ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:570:10: error: ‘const struct regmap_config’ has no member named ‘reg_bits’ 570 | .reg_bits = 32, | ^~~~~~~~ Note that selecting REGMAP alone is not enough, because of the following liker error: phy-rockchip-samsung-hdptx.c:(.text+0x10c): undefined reference to `__devm_regmap_init_mmio_clk' Instead of the obvious fix to enable REGMAP_MMIO, select MFD_SYSCON, which implicitly enables REGMAP_MMIO as well. The rationale is that the driver has been already relying on the syscon functionality. Moreover, without MFD_SYSCON enabled, the test coverage is reduced, since the linker might not detect any potential undefined references following syscon_regmap_lookup_by_phandle() invocation in rk_hdptx_phy_probe() body. That is because the function would unconditionally return -ENOTSUP, hence the compiler is free to optimize out any unreachable code. Finally ensure PHY_ROCKCHIP_SAMSUNG_HDPTX depends on HAS_IOMEM, as required by MFD_SYSCON. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240629-rk-hdptx-compile-test-fix-v1-1-c86675ba8070@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: airoha: Add PCIe PHY driver for EN7581 SoC.Lorenzo Bianconi2024-06-204-0/+1736
| | | | | | | | | | | | | | | | | | | | | | Introduce support for Airoha PCIe PHY controller available in EN7581 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20ac99aa8628d97778594f606681db7f868f24fe.1718485860.git.lorenzo@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: freescale: imx8qm-hsio: Include bitfield.h for FIELD_PREPNathan Chancellor2024-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In various configurations/architectures, bitfield.h may not be transitively included, which results in a compiler error because FIELD_PREP is an unexpanded macro: drivers/phy/freescale/phy-fsl-imx8qm-hsio.c:459:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 459 | val = FIELD_PREP(HSIO_MODE_MASK, val); | ^ 1 error generated. Include bitfield.h explicitly to fix the build. Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406170340.7mk3WU3Q-lkp@intel.com/ Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240620-phy-fsl-imx8qm-hsio-add-bitfield-include-v1-1-5c7c09ed87e6@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver supportRichard Zhu2024-06-153-1/+619
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8QM HSIO PHY driver support. i.MX8QM HSIO has three lane PHY instances, and can be bound to the following controllers in the different use cases listed in below table. - two lanes capable PCIEA controller. - one lane PCIEB controller. - AHCI SATA controller. i.MX8QM HSIO PHYs support the following use cases. +----------------------------------------------------+ | | Lane0| Lane1| Lane2| |-------------------------------|------|------|------| | use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA | |-------------------------------|------|------|------| | use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB| |-------------------------------|------|------|------| | use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA | +----------------------------------------------------+ Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/1716962565-2084-3-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: starfive: Add mipi dphy tx supportShengyang Chen2024-06-153-0/+470
| | | | | | | | | | | | | | | | | | | | | | Add mipi dphy tx support for the StarFive JH7110 SoC. It is a module which is used to receive data from DSI driver and transfer data to DSI interface like mipi screen. Signed-off-by: Shengyang Chen <shengyang.chen@starfivetech.com> Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20240418035020.47876-3-shengyang.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom: qmp-pcie: restore compatibility with existing DTsDmitry Baryshkov2024-06-151-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing device trees specify only a single clock-output-name for the PCIe PHYs. The function phy_aux_clk_register() expects a second entry in that property. When it doesn't find it, it returns an error, thus failing the probe of the PHY and thus breaking support for the corresponding PCIe host. Follow the approach of the combo USB+DT PHY and generate the name for the AUX clocks instead of requiring it in DT. Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: broadcom: add missing MODULE_DESCRIPTION() macrosJeff Johnson2024-06-122-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/phy/broadcom/phy-bcm-ns-usb2.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/phy/broadcom/phy-bcm-ns-usb3.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Link: https://lore.kernel.org/r/20240608-md-drivers-phy-broadcom-v1-1-f070f84cc3f0@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: ti: am654-serdes: Remove duplicate defineJan Kiszka2024-06-121-1/+0
| | | | | | | | | | | | Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/60089a71-dad2-4a87-a304-a738e3334d4a@siemens.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()André Draszik2024-06-121-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with the frequency of the reference clock for the USB2.0 phy instead. I stumbled across this while adding support for the Google Tensor gs101, but this should apply to E850 just the same. Do so. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-5-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: exynos5-usbdrd: fix definition of EXYNOS5_FSEL_26MHZAndré Draszik2024-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using 0x82 seems odd, where everything else is just a sequence. On E850, this macro isn't used (as a register value), only to assign its value to the 'extrefclk' variable, which is otherwise unused on that platform. Older platforms don't appear to support 26MHz in the first place (since this macro was added for E850). Furthermore, the downstream driver uses 0x82 to denote USBPHY_REFCLK_DIFF_26MHZ (whatever that means exactly), but for all the other values we match downstream's non-DIFF macros. Update to avoid confusion. No functional change intended. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-4-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: exynos5-usbdrd: make phy_isol() take a bool for clarityAndré Draszik2024-06-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on / not on is just a boolean flag and is a bit misleading as currently on==1 means to turn off the power, and on==0 to turn power on. Rename the flag and make it a bool to avoid confusion of future readers of this code. No functional change. While at it, fix a whitespace issue in nearby comment. No functional change. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-3-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: exynos5-usbdrd: convert udelay() to fsleep()André Draszik2024-06-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timers-howto recommends using usleep_range() and friends anytime waiting for >= ~10us is required. Doing so can help the timer subsystem a lot to coalesce wakeups. Additionally, fsleep() exists as a convenient wrapper so we do not have to think about which exact sleeping function is required in which case. Convert all udelay() calls in this driver to use fsleep() to follow the recommendataion. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-2-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: exynos5-usbdrd: uniform order of register bit macrosAndré Draszik2024-06-121-29/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the macros are ordered high -> low, but there are some outliers. Order them all uniformly from high to low. This will allow adding additional register (field) definitions in a consistent way. While at it, also remove some extra empty lines to group register bit field definitions together with the relevant register. This makes the registers easier to distinguish visually. No functional change. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-1-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEsdevi priya2024-06-031-0/+309
| | | | | | | | | | | | | | | | | | | | | | | | Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp: Add missing register definitions for PCS V5devi priya2024-06-031-0/+14
| | | | | | | | | | | | | | | | | | Add missing register offsets for PCS V5 registers. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-4-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp: Add missing offsets for Qserdes PLL registers.devi priya2024-06-031-0/+3
| | | | | | | | | | | | | | | | | | Add missing register offsets for Qserdes PLL. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-3-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: miphy28lp: remove unused struct 'miphy_initval'Dr. David Alan Gilbert2024-06-031-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | 'miphy_initval' is unused since the original commit 2c14e9be0c60 ("phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY"). Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Link: https://lore.kernel.org/r/20240527205844.165279-1-linux@treblig.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: starfive: remove unused struct 'regval'Dr. David Alan Gilbert2024-06-031-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | 'regval' is unused since the original commit f8aa660841bc ("phy: starfive: Add mipi dphy rx support"). Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20240527205937.165325-1-linux@treblig.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-usb: Add sc8180x USB UNIPHYBjorn Andersson2024-06-031-0/+3
| | | | | | | | | | | | | | | | | | | | The SC8180X platform has two UNIPHY blocks, add support for these in the QMP driver. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240525-sc8180x-usb-mp-v1-2-60a904392438@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence-torrent: add suspend and resume supportThomas Richard2024-06-031-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | Add suspend and resume support. The already_configured flag is cleared during the suspend stage to force the PHY initialization during the resume stage. Co-developed-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-8-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence-torrent: remove noop_ops phy operationsThomas Richard2024-06-031-17/+13
| | | | | | | | | | | | | | | | | | | | | | | | Even if a PHY is already configured, the PHY operations are needed during resume stage, as the PHY is in reset state. The noop_ops PHY operations is removed to always have PHY operations. The already_configured flag is checked at the begening of init, configure and poweron operations to keep the already_configured behaviour. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-7-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence-torrent: add already_configured to struct cdns_torrent_phyThomas Richard2024-06-031-5/+5
| | | | | | | | | | | | | | | | | | Add already_configured to struct cdns_torrent_phy, so it can be used at differents stages. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-6-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence-torrent: register resets even if the phy is already configuredThomas Richard2024-06-031-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Resets are needed during suspend and resume stages. So they shall be registered during the probe even the phy is already initialized. The function cdns_torrent_reset is renamed cdns_torrent_of_get_reset() to make it clear. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-5-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence-torrent: extract calls to clk_get from cdns_torrent_clkThomas Richard2024-06-031-16/+21
| | | | | | | | | | | | | | | | | | | | | | Extract calls to clk_get from cdns_torrent_clk into a separate function. It needs to call cdns_torrent_clk at resume without looking up the clock. Co-developed-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-4-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: ti: phy-j721e-wiz: add resume supportThomas Richard2024-06-031-0/+29
| | | | | | | | | | | | | | | | | | | | | | Add resume support. It has been tested on J7200 SR1.0 and SR2.0. Co-developed-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-3-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: ti: phy-j721e-wiz: split wiz_clock_init() functionThomas Richard2024-06-031-29/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | The wiz_clock_init() function mixes probe and hardware configuration. Rename the wiz_clock_init() to wiz_clock_probe() and move the hardware configuration part in a new function named wiz_clock_init(). This hardware configuration sequence must be called during the resume stage of the driver. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-2-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: ti: phy-j721e-wiz: use dev_err_probe() instead of dev_err()Thomas Richard2024-06-031-25/+21
| | | | | | | | | | | | | | | | | | Use dev_err_probe() instead of dev_err() in wiz_clock_init() to simplify the code and standardize the error output. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-1-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: cadence-torrent: Add SGMII + QSGMII multilink configuration for 100MHz ↵Swapnil Jakhade2024-06-031-4/+60
| | | | | | | | | | | | | | | | | | | | | | | | refclk Add register sequences for SGMII + QSGMII multilink configuration for 100MHz refclk. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20240602021629.3027660-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | Merge tag 'usb-6.11-rc1' of ↵Linus Torvalds2024-07-191-0/+49
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB / Thunderbolt updates from Greg KH: "Here is the big set of USB and Thunderbolt changes for 6.11-rc1. Nothing earth-shattering in here, just constant forward progress in adding support for new hardware and better debugging functionalities for thunderbolt devices and the subsystem. Included in here are: - thunderbolt debugging update and driver additions - xhci driver updates - typec driver updates - kselftest device driver changes (acked by the relevant maintainers, depended on other changes in this tree.) - cdns3 driver updates - gadget driver updates - MODULE_DESCRIPTION() additions - dwc3 driver updates and fixes All of these have been in linux-next for a while with no reported issues" * tag 'usb-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (112 commits) kselftest: devices: Add test to detect device error logs kselftest: Move ksft helper module to common directory kselftest: devices: Move discoverable devices test to subdirectory usb: gadget: f_uac2: fix non-newline-terminated function name USB: uas: Implement the new shutdown callback USB: core: add 'shutdown' callback to usb_driver usb: typec: Drop explicit initialization of struct i2c_device_id::driver_data to 0 usb: dwc3: enable CCI support for AMD-xilinx DWC3 controller usb: dwc2: add support for other Lantiq SoCs usb: gadget: Use u16 types for 16-bit fields usb: gadget: midi2: Fix incorrect default MIDI2 protocol setup usb: dwc3: core: Check all ports when set phy suspend usb: typec: tcpci: add support to set connector orientation dt-bindings: usb: Convert fsl-usb to yaml usb: typec: ucsi: reorder operations in ucsi_run_command() usb: typec: ucsi: extract common code for command handling usb: typec: ucsi: inline ucsi_read_message_in usb: typec: ucsi: rework command execution functions usb: typec: ucsi: split read operation usb: typec: ucsi: simplify command sending API ...
| * \ Merge 6.10-rc6 into usb-nextGreg Kroah-Hartman2024-07-014-29/+207
| |\ \ | | | | | | | | | | | | | | | | | | | | We need the USB fixes in here as well for some follow-on patches. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | | phy: ti: phy-da8xx-usb: Add runtime PM supportBastien Curutchet2024-06-041-0/+49
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Runtime PM is not supported while USB PHY can be turned off from register accesses. Add runtime PM for the USB2.0 PHY. The PHY is entirely shut down to save as much power as possible. This means that gadgets will not be discovered once suspend state is entered, and suspend state can not be left without an explicit user intervention (through sysfs). That's why runtime PM is disabled by default. Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com> Link: https://lore.kernel.org/r/20240528102026.40136-2-bastien.curutchet@bootlin.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | | phy: renesas: phy-rcar-gen3-usb2: Control VBUS for RZ/G2L SoCsBiju Das2024-07-031-1/+7
| |/ |/| | | | | | | | | | | | | | | | | Use regulator_hardware_enable() for controlling VBUS enable for RZ/G2L alike SoCs in interrupt context. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20240702180032.207275-4-biju.das.jz@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* | phy: qcom: qmp-combo: Switch from V6 to V6 N4 register offsetsAbel Vesa2024-06-032-29/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, none of the X1E80100 supported boards upstream have enabled DP. As for USB, the reason it is not broken when it's obvious that the offsets are wrong is because the only difference with respect to USB is the difference in register name. The V6 uses QPHY_V6_PCS_CDR_RESET_TIME while V6 N4 uses QPHY_V6_N4_PCS_RX_CONFIG. Now, in order for the DP to work, the DP serdes tables need to be added as they have different values for V6 N4 when compared to V6 ones, even though they use the same V6 offsets. While at it, switch swing and pre-emphasis tables to V6 as well. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-3-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: pcs: Add missing v6 N4 register offsetsAbel Vesa2024-06-031-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for combo USB and DP PHY. Currently, the X1E80100 uses the pure V6 PCS register offsets, which are different. Add the offsets so the mentioned platform can be fixed later on. Add the new PCS offsets in a dedicated header file. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-qmp: qserdes-txrx: Add missing registers offsetsAbel Vesa2024-06-031-0/+13
|/ | | | | | | | | | | | | | | Currently, the x1e80100 uses pure V6 register offsets for DP part of the combo PHY. This hasn't been an issue because external DP is not yet enabled on any of the boards yet. But in order to enabled it, all these new V6 N4 register offsets are needed. So add them. Fixes: 762c3565f3c8 ("phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'phy-for-6.10' of ↵Linus Torvalds2024-05-2128-97/+3719
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull generic phy updates from Vinod Koul: "New HW Support: - Support for Embedded DisplayPort and DisplayPort submodes and driver support on Qualcomm X1E80100 edp driver - Qualcomm QMP UFS PHY for SM8475, QMP USB phy for QDU1000/QRU1000 and eusb2-repeater for SMB2360 - Samsung HDMI PHY for i.MX8MP, gs101 UFS phy - Mediatek XFI T-PHY support for mt7988 - Rockchip usbdp combo phy driver Updates: - Qualcomm x4 lane EP support for sa8775p, v4 ad v6 support for X1E80100, SM8650 tables for UFS Gear 4 & 5 and correct voltage swing tables - Freescale imx8m-pci pcie link-up updates - Rockchip rx-common-refclk-mode support - More platform remove callback returning void conversions" * tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000 dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000 phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p phy: samsung-ufs: ufs: exit on first reported error phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h header phy: rockchip: fix CONFIG_TYPEC dependency phy: rockchip: usbdp: fix uninitialized variable phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode phy: rockchip: add usbdp combo phy driver dt-bindings: phy: add rockchip usbdp combo phy document phy: add driver for MediaTek XFI T-PHY dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindings phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5 MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101. ...
| * phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000Komal Bajaj2024-05-041-0/+47
| | | | | | | | | | | | | | | | | | | | | | Add QDU1000/QRU1000 specific register layout and table configs. Co-developed-by: Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by: Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240502082017.13777-5-quic_kbajaj@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: qcom-qmp-pcie: add x4 lane EP support for sa8775pMrinmay Sarkar2024-05-041-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add support for x4 lane end point mode PHY found on sa8755p platform. Reusing existing serdes and pcs_misc table for EP and moved BIAS_EN_CLKBUFLR_EN register from RC serdes table to common serdes table as this register is part of both RC and EP. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1714494089-7917-2-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: samsung-ufs: ufs: exit on first reported errorPeter Griffin2024-05-041-2/+8
| | | | | | | | | | | | | | | | | | | | To preserve the err value, exit the loop immediately if an error is returned. Fixes: f2c6d0fa197a ("phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap") Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426104129.2211949-3-peter.griffin@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h headerPeter Griffin2024-05-041-1/+0
| | | | | | | | | | | | | | | | | | | | mfd/syscon.h header is no longer required since the update to exynos_get_pmu_regmap_by_phandle() api. Fixes: f2c6d0fa197a ("phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap") Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426104129.2211949-2-peter.griffin@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: fix CONFIG_TYPEC dependencyArnd Bergmann2024-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly added driver causes a warning about missing dependencies by selecting CONFIG_TYPEC unconditionally: WARNING: unmet direct dependencies detected for TYPEC Depends on [n]: USB_SUPPORT [=n] Selected by [y]: - PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y] WARNING: unmet direct dependencies detected for USB_COMMON Depends on [n]: USB_SUPPORT [=n] Selected by [y]: - EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y] Since that is a user-visible option, it should not really be selected in the first place. Replace the 'select' with a 'depends on' as we have for similar drivers. Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: usbdp: fix uninitialized variableSebastian Reichel2024-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if the PHY is not using USB3 mode. Since the DisplayPort part is handled separately and the PHY does not support USB2 (which is routed to another PHY on Rockchip RK3588), the right exit code for this case is 0. Thus let's initialize the variable accordingly. Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-modeNiklas Cassel2024-04-131-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add support for the device tree property rockchip,rx-common-refclk-mode, such that the PCIe PHY can be used in configurations where the Root Complex and Endpoint are not using a common reference clock. Signed-off-by: Niklas Cassel <cassel@kernel.org> Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: add usbdp combo phy driverSebastian Reichel2024-04-123-0/+1621
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new USBDP combo PHY with Samsung IP block driver. The driver get lane mux and mapping info in 2 ways, supporting DisplayPort alternate mode or parsing from DT. When parsing from DT, the property "rockchip,dp-lane-mux" provide the DP mux and mapping info. This is needed when the PHY is not used with TypeC Alt-Mode. For example if the USB3 interface of the PHY is connected to a USB Type A connector and the DP interface is connected to a DisplayPort connector. When do DP link training, need to set lane number, link rate, swing, and pre-emphasis via PHY configure interface. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Co-developed-by: Zhang Yubing <yubing.zhang@rock-chips.com> Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com> Co-developed-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240408225109.128953-3-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: add driver for MediaTek XFI T-PHYDaniel Golle2024-04-123-0/+463
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for MediaTek's XFI T-PHY which can be found in the MT7988 SoC. The XFI T-PHY is a 10 Gigabit/s Ethernet SerDes PHY with muxes on the internal side to be used with either USXGMII PCS or LynxI PCS, depending on the selected PHY interface mode. The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of PHY_INTERFACE_MODE_* corresponding to the supported modes: * USXGMII \ * 10GBase-R }- USXGMII PCS - XGDM \ * 5GBase-R / \ }- Ethernet MAC * 2500Base-X \ / * 1000Base-X }- LynxI PCS - GDM / * Cisco SGMII (MAC side) / I chose the name XFI T-PHY because names of functions dealing with the phy in the vendor driver are prefixed "xfi_pextp_". The register space used by the phy is called "pextp" in the vendor sources, which could be read as "_P_CI _ex_press _T_-_P_hy", and that is quite misleading as this phy isn't used for anything related to PCIe, so I wanted to find a better name. XFI is still somehow related (as in: you would find the relevant places using grep in the vendor driver when looking for that) and the term seemed to at least somehow be aligned with the function of that phy: Dealing with (up to) 10 Gbit/s Ethernet serialized differential signals. In order to work-around a performance issue present on the first of two XFI T-PHYs found in MT7988, special tuning is applied which can be selected by adding the 'mediatek,usxgmii-performance-errata' property to the device tree node, similar to how the vendor driver is doing that too. There is no documentation for most registers used for the analog/tuning part, however, most of the registers have been partially reverse-engineered from MediaTek's SDK implementation (see links, an opaque sequence of 32-bit register writes) and descriptions for all relevant digital registers and bits such as resets and muxes have been supplied by MediaTek. Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/b72d6cba92bf9e29fb035c03052fa1e86664a25b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/dec96a1d9b82cdcda4a56453fd0b453d4cab4b85/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/8719c82634df7e8e984f1a608be3ba2f2d494fb4.1712625857.git.daniel@makrotopia.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-27 05:18:06 +0000