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* phy: cadence-torrent: Add PCIe + USB multilink configurationSwapnil Jakhade2020-09-181-0/+216
| | | | | | | | Add PCIe + USB Unique SSC multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-13-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add single link USB register sequencesSwapnil Jakhade2020-09-181-1/+259
| | | | | | | | Add support for single link USB configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-12-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add single link SGMII/QSGMII register sequencesSwapnil Jakhade2020-09-181-0/+89
| | | | | | | | Add support for single link SGMII/QSGMII configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-11-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_valsSwapnil Jakhade2020-09-181-4/+18
| | | | | | | | | Include PHY_PLL_CFG as a first register value to configure in link_cmn_vals array values. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-10-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add PHY link configuration sequences for single linkSwapnil Jakhade2020-09-181-0/+44
| | | | | | | | | Add support to configure link_cmn_vals and xcvr_diag_vals in case of single link PHY configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-9-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add clk changes for multilink configurationSwapnil Jakhade2020-09-181-24/+17
| | | | | | | | | Prepare and enable clock in probe instead of phy_init. Also, remove phy_exit callback. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-8-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Update PHY reset for multilink configurationSwapnil Jakhade2020-09-181-7/+21
| | | | | | | | | | For multilink configuration, deassert PHY and link reset after PHY registers are configured in probe and only check link status in power_on callback. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-7-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add support for PHY multilink configurationSwapnil Jakhade2020-09-181-26/+757
| | | | | | | | | | | | | Added support for multilink configuration of Torrent PHY. Currently, maximum two links are supported. In case of multilink configuration, PHY needs to be configured for both the protocols simultaneously at the beginning as per the requirement of Torrent PHY. Also, register sequences for PCIe + SGMII/QSGMII Unique SSC PHY multilink configurations are added. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-6-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add PHY APB reset supportSwapnil Jakhade2020-09-181-0/+13
| | | | | | | | Add support for PHY APB reset and make it optional. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Check cmn_ready assertion during PHY power onSwapnil Jakhade2020-09-181-1/+30
| | | | | | | | Check if cmn_ready is set after both PLL0 and PLL1 are locked. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add single link PCIe supportSwapnil Jakhade2020-09-181-30/+266
| | | | | | | | | Add single link PCIe register sequences in Torrent PHY driver. Also, add support for getting SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600327846-9733-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Check total lane count for all subnodes is within limitSwapnil Jakhade2020-09-181-4/+15
| | | | | | | | | Add checking if total number of lanes for all subnodes is not greater than number of lanes supported by PHY. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-6-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add separate regmap functions for torrent and DPSwapnil Jakhade2020-09-181-33/+66
| | | | | | | | | Added separate functions for regmap initialization of torrent PHY generic registers and DP specific registers. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Enable support for multiple subnodesSwapnil Jakhade2020-09-181-15/+0
| | | | | | | | | Enable support for multiple subnodes in torrent PHY to include multi-link combinations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Use devm_platform_ioremap_resource() to get reg addressesSwapnil Jakhade2020-09-181-6/+2
| | | | | | | | | Use devm_platform_ioremap_resource() to get register addresses instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Use of_device_get_match_data() to get driver dataSwapnil Jakhade2020-09-181-8/+5
| | | | | | | | | Use of_device_get_match_data() to get driver data instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1600280911-9214-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: intel: Add Keem Bay eMMC PHY supportWan Ahmad Zainie2020-09-163-0/+320
| | | | | | | | | Add support for eMMC PHY on Intel Keem Bay SoC. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200913235522.4316-4-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: intel: Rename phy-intel to phy-intel-lgmWan Ahmad Zainie2020-09-164-7/+7
| | | | | | | | | | Rename phy-intel-{combo,emmc}.c to phy-intel-lgm-{combo,emmc}.c to make drivers/phy/intel directory more generic for future use. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20200913235522.4316-2-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: torrent: Constify regmap_config structsRikard Falkeborn2020-09-161-6/+6
| | | | | | | | | The regmap_config structs are never modified and can be made const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200912204639.501669-4-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: salvo: Constify cdns_nxp_sequence_pairRikard Falkeborn2020-09-161-3/+3
| | | | | | | | | | cdns_nxp_sequence_pair[] are never modified and can be made const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200912204639.501669-3-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence: Sierra: Constify static structsRikard Falkeborn2020-09-161-12/+12
| | | | | | | | | | The static cdns_reg_pairs and regmap_config structs are not modified and can be made const. This allows the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200912204639.501669-2-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge branch 'topic/phy_attrs' into nextVinod Koul2020-09-161-0/+4
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| * phy: cadence-torrent: Set Torrent PHY attributesSwapnil Jakhade2020-09-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | Set Torrent PHY attributes bus_width, max_link_rate and mode for DisplayPort. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1599805114-22063-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: Add USB3 PHY support for Intel LGM SoCRamuthevar Vadivel Murugan2020-09-113-0/+295
| | | | | | | | | | | | | | | | | | Add support for USB PHY on Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20200828022312.52724-3-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: ti: gmii-sel: retrieve ports number and base offset from dtGrygorii Strashko2020-09-081-11/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On K3 AM654x/J721E platforms the Port MII mode selection register(s) have similar format and placed in the System Control Module (SCM) module sequentially as one register per port, but, depending SOC and CPSW instance, the base offset and number of ports can be different. Hence, add possibility to retrieve number of ports and base registers offset from DT and support for max possible number of ports supported by K3 SoCs like J721E. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20200828201943.29155-4-grygorii.strashko@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: ti: gmii-sel: use features mask during initGrygorii Strashko2020-09-081-8/+2
| | | | | | | | | | | | | | | | Use features mask during PHYs initialization to simplify code. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20200828201943.29155-3-grygorii.strashko@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: ti: gmii-sel: move phy init in separate functionGrygorii Strashko2020-09-081-47/+64
| | | | | | | | | | | | | | | | | | Move phy initialization in separate function to improve code readability and simplify future changes. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20200828201943.29155-2-grygorii.strashko@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: phy-pxa-28nm-usb2: convert to readl_poll_timeout()Chunfeng Yun2020-09-081-18/+15
| | | | | | | | | | | | | | | | Use readl_poll_timeout() to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1598320987-25518-6-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: phy-pxa-28nm-hsic: convert to readl_poll_timeout()Chunfeng Yun2020-09-081-20/+20
| | | | | | | | | | | | | | | | Use readl_poll_timeout() to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1598320987-25518-5-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: phy-qcom-apq8064-sata: convert to readl_relaxed_poll_timeout()Chunfeng Yun2020-09-081-13/+8
| | | | | | | | | | | | | | | | | | Use readl_relaxed_poll_timeout() to simplify code, rename local function read_poll_timeout() as poll_timeout() to avoid repeated definition Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1598320987-25518-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: phy-bcm-sr-usb: convert to readl_poll_timeout_atomic()Chunfeng Yun2020-09-081-11/+8
| | | | | | | | | | | | | | | | Use readl_poll_timeout_atomic() to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1598320987-25518-3-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: phy-bcm-ns2-usbdrd: convert to readl_poll_timeout_atomic()Chunfeng Yun2020-09-081-9/+4
| | | | | | | | | | | | | | | | Use readl_poll_timeout_atomic() to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1598320987-25518-2-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: phy-bcm-ns-usb3: convert to readl_poll_timeout_atomic()Chunfeng Yun2020-09-081-13/+9
| | | | | | | | | | | | | | | | Use readl_poll_timeout_atomic() to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: Move phy-rockchip-dphy-rx0 out of stagingEzequiel Garcia2020-08-313-0/+401
| | | | | | | | | | | | | | | | | | There is no need for this driver to be in staging. Let's promote it! Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Link: https://lore.kernel.org/r/20200825220710.634106-1-ezequiel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: socionext: Add UniPhier AHCI PHY driver supportKunihiko Hayashi2020-08-313-0/+332
| | | | | | | | | | | | | | | | | | Add a driver for PHY interface built into ahci controller implemented in UniPhier SoCs. This supports PXs2 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1598352071-26675-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-ipq4019-usb: Constify static phy_ops structsRikard Falkeborn2020-08-311-2/+2
| | | | | | | | | | | | | | | | | | | | Their only usages is to assign the address to the data field in the of_device_id struct, which is a const void pointer. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-9-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: samsung-ufs: Constify samsung_ufs_phy_opsRikard Falkeborn2020-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-8-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: ralink-usb: Constify ralink_usb_phy_opsRikard Falkeborn2020-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-7-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: lantiq: vrx200-pcie: Constify ltq_vrx200_pcie_phy_opsRikard Falkeborn2020-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200823220025.17588-6-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: lantiq: rcu-usb2: Constify ltq_rcu_usb2_phy_opsRikard Falkeborn2020-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-5-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: hisilicon; Constify hi3660_phy_opsRikard Falkeborn2020-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-4-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: fsl-imx8mq-usb: Constify imx8mq_usb_phy_opsRikard Falkeborn2020-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-3-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: cadence: salvo: Constify cdns_salvo_phy_opsRikard Falkeborn2020-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | The only usage is to pass its address to devm_phy_create() which takes a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-2-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: freescale: imx8mq-usb: add support for imx8mp usb phyLi Jun2020-08-311-7/+70
| | | | | | | | | | | | | | | | | | | | Add initial support for imx8mp usb phy support, imx8mp usb has a silimar phy as imx8mq, which has some different customizations on clock and low power design when SoC integration. Signed-off-by: Li Jun <jun.li@nxp.com> Link: https://lore.kernel.org/r/1598276014-2377-2-git-send-email-jun.li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: omap-usb2-phy: fix coding style issuesRoger Quadros2020-08-311-19/+17
| | | | | | | | | | | | | | | | Fix checkpatch warnings and sort the include files alphabetically. Signed-off-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200824075127.14902-3-rogerq@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | Merge branch 'fixes' into nextVinod Koul2020-08-314-17/+53
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| * | phy: omap-usb2-phy: disable PHY charger detectRoger Quadros2020-08-311-7/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM654x PG1.0 has a silicon bug that D+ is pulled high after POR, which could cause enumeration failure with some USB hubs. Disabling the USB2_PHY Charger Detect function will put D+ into the normal state. This addresses Silicon Errata: i2075 - "USB2PHY: USB2PHY Charger Detect is Enabled by Default Without VBUS Presence" Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20200824075127.14902-2-rogerq@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY initSivaprakash Murugesan2020-08-232-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were some problem in ipq8074 Gen2 PCIe phy init sequence. 1. Few register values were wrongly updated in the phy init sequence. 2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter register which is added in serdes table causing the wrong register was getting updated. 3. Clocks and resets were not added in the phy init. Fix these to make Gen2 PCIe port on ipq8074 devices to work. Fixes: eef243d04b2b6 ("phy: qcom-qmp: Add support for IPQ8074") Cc: stable@vger.kernel.org Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1596036607-11877-4-git-send-email-sivaprak@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: qualcomm: fix return value check in qcom_ipq806x_usb_phy_probe()Wei Yongjun2020-08-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200723113622.136752-1-weiyongjun1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * | phy: qualcomm: fix platform_no_drv_owner.cocci warningsYueHaibing2020-08-171-1/+0
| |/ | | | | | | | | | | | | | | | | Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200725031624.31432-1-yuehaibing@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-31 18:02:15 +0000