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* phy: qcom: qmp: Use power_on/off ops for PCIeBjorn Andersson2020-03-201-3/+3
| | | | | | | | | | | The PCIe PHY initialization requires the attached device to be present, which is primarily achieved by the PCI controller driver. So move the logic from init/exit to power_on/power_off. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: uniphier-pcie: Add SoC-dependent phy-mode function supportKunihiko Hayashi2020-03-201-7/+10
| | | | | | | | | | | | | | | Since this phy is shared by multiple devices including USB and PCIe, it is necessary to determine which device use this phy. This patch adds SoC-dependent functions to determine a device using this phy. When there is 'socionext,syscon' property in the pcie-phy node, the driver calls SoC-dependt function instead of checking .has_syscon in SoC-dependent data. The function configures the system controller to use phy for PCIe. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: uniphier-pcie: Add legacy SoC support for Pro5Kunihiko Hayashi2020-03-201-11/+72
| | | | | | | | | | | Add legacy SoC support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. This supports Pro5. This specifies only 1 port use because Pro5 doesn't set it in the power-on sequence. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failureKunihiko Hayashi2020-03-201-4/+16
| | | | | | | | In case of using default parameters, communication failure might occur in rare cases. This sets Rx sync mode parameter to avoid the issue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: uniphier-usb3hs: Add legacy SoC support for Pro5Kunihiko Hayashi2020-03-201-15/+53
| | | | | | | | Add legacy SoC support that needs to manage gio clock and reset. This supports Pro5. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: uniphier-usb3ss: Add Pro5 supportKunihiko Hayashi2020-03-201-0/+4
| | | | | | | | Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is equivalent to Pro4. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: socionext: Use devm_platform_ioremap_resource()Kunihiko Hayashi2020-03-203-9/+3
| | | | | | | Use devm_platform_ioremap_resource() to simplify the code. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom-qmp: Add MSM8996 UFS QMP supportBjorn Andersson2020-03-201-0/+106
| | | | | | | | | | | | | | The support for the 14nm MSM8996 UFS PHY is currently handled by the UFS-specific 14nm QMP driver, due to the earlier need for additional operations beyond the standard PHY API. Add support for this PHY to the common QMP driver, to allow us to remove the old driver. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Add support for subnode bindingsSwapnil Jakhade2020-03-201-75/+217
| | | | | | | | | Implement single link subnode support to the phy driver. Add reset support including PHY reset and individual lane reset. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Add platform dependent initialization structureSwapnil Jakhade2020-03-201-0/+9
| | | | | | | | | Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Use regmap to read and write DPTX PHY registersSwapnil Jakhade2020-03-201-69/+100
| | | | | | | | Use regmap to read and write DPTX specific PHY registers. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Use regmap to read and write Torrent PHY registersSwapnil Jakhade2020-03-201-369/+650
| | | | | | | | | | Use regmap for accessing Torrent PHY registers. Modify register offsets as defined in Torrent PHY user guide. Abstract address calculation using regmap APIs. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Implement PHY configure APIsSwapnil Jakhade2020-03-201-5/+431
| | | | | | | | | Add support for PHY configuration APIs. These will mainly reconfigure link rate, number of lanes, voltage swing and pre-emphasis values. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Add 19.2 MHz reference clock supportSwapnil Jakhade2020-03-201-17/+441
| | | | | | | | | Add configuration functions for 19.2 MHz refclock support. Add register configurations for SSC support. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Refactor code for reusabilitySwapnil Jakhade2020-03-201-93/+137
| | | | | | | | | | Add a separate function to set different power state values. Use uniform polling timeout value. Also check return values of functions for proper error handling. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Add wrapper for DPTX register accessSwapnil Jakhade2020-03-201-21/+50
| | | | | | | | | Add wrapper functions to read, write DisplayPort specific PHY registers to improve code readability. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Add wrapper for PHY register accessSwapnil Jakhade2020-03-201-65/+77
| | | | | | | | | Add a wrapper function to write Torrent PHY registers to improve code readability. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-torrent: Adopt Torrent nomenclatureSwapnil Jakhade2020-03-201-53/+58
| | | | | | | | | | | | - Change private data struct cdns_dp_phy to cdns_torrent_phy - Change module description and registration accordingly - Generic torrent functions have prefix cdns_torrent_phy_* - Functions specific to Torrent phy for DisplayPort are prefixed as cdns_torrent_dp_* Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: cadence-dp: Rename to phy-cadence-torrentYuti Amonkar2020-03-203-5/+5
| | | | | | | | | | | Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent to make it more generic for future use. Modifiy Makefile and Kconfig accordingly. Also, change driver compatible from "cdns,dp-phy" to "cdns,torrent-phy".This will not affect ABI as the driver has never been functional, and therefore do not exist in any active use case. Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom: qmp: Add SDM845 QHP PCIe PHYBjorn Andersson2020-02-212-0/+271
| | | | | | | | | | Add the GEN3 QHP PCIe PHY found in SDM845. Tested-by: Julien Massot <jmassot@softbankrobotics.com> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: qcom: qmp: Add SDM845 PCIe QMP PHY supportBjorn Andersson2020-02-211-0/+156
| | | | | | | | | | | qcom_qmp_phy_init() is extended to support the additional register writes needed in PCS MISC and the appropriate sequences and resources are defined for the GEN2 PCIe QMP PHY found in SDM845. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* treewide: remove redundant IS_ERR() before error code checkMasahiro Yamada2020-02-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 'PTR_ERR(p) == -E*' is a stronger condition than IS_ERR(p). Hence, IS_ERR(p) is unneeded. The semantic patch that generates this commit is as follows: // <smpl> @@ expression ptr; constant error_code; @@ -IS_ERR(ptr) && (PTR_ERR(ptr) == - error_code) +PTR_ERR(ptr) == - error_code // </smpl> Link: http://lkml.kernel.org/r/20200106045833.1725-1-masahiroy@kernel.org Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Cc: Julia Lawall <julia.lawall@lip6.fr> Acked-by: Stephen Boyd <sboyd@kernel.org> [drivers/clk/clk.c] Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [GPIO] Acked-by: Wolfram Sang <wsa@the-dreams.de> [drivers/i2c] Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [acpi/scan.c] Acked-by: Rob Herring <robh@kernel.org> Cc: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'usb-5.6-rc1' of ↵Linus Torvalds2020-01-2929-579/+3048
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/Thunderbolt/PHY driver updates from Greg KH: "Here is the big USB and Thunderbolt and PHY driver updates for 5.6-rc1. With the advent of USB4, "Thunderbolt" has really become USB4, so the renaming of the Kconfig option and starting to share subsystem code has begun, hence both subsystems coming in through the same tree here. PHY driver updates also touched USB drivers, so that is coming in through here as well. Major stuff included in here are: - USB 4 initial support added (i.e. Thunderbolt) - musb driver updates - USB gadget driver updates - PHY driver updates - USB PHY driver updates - lots of USB serial stuff fixed up - USB typec updates - USB-IP fixes - lots of other smaller USB driver updates All of these have been in linux-next for a while now (the usb-serial tree is already tested in linux-next on its own before merged into here), with no reported issues" [ Removed an incorrect compile test enablement for PHY_EXYNOS5250_SATA that causes configuration warnings - Linus ] * tag 'usb-5.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (207 commits) Doc: ABI: add usb charger uevent usb: phy: show USB charger type for user usb: cdns3: fix spelling mistake and rework grammar in text usb: phy: phy-gpio-vbus-usb: Convert to GPIO descriptors USB: serial: cyberjack: fix spelling mistake "To" -> "Too" USB: serial: ir-usb: simplify endpoint check USB: serial: ir-usb: make set_termios synchronous USB: serial: ir-usb: fix IrLAP framing USB: serial: ir-usb: fix link-speed handling USB: serial: ir-usb: add missing endpoint sanity check usb: typec: fusb302: fix "op-sink-microwatt" default that was in mW usb: typec: wcove: fix "op-sink-microwatt" default that was in mW usb: dwc3: pci: add ID for the Intel Comet Lake -V variant usb: typec: tcpci: mask event interrupts when remove driver usb: host: xhci-tegra: set MODULE_FIRMWARE for tegra186 usb: chipidea: add inline for ci_hdrc_host_driver_init if host is not defined usb: chipidea: handle single role for usb role class usb: musb: fix spelling mistake: "periperal" -> "peripheral" phy: ti: j721e-wiz: Fix build error without CONFIG_OF_ADDRESS USB: usbfs: Always unlink URBs in reverse order ...
| * phy: ti: j721e-wiz: Fix build error without CONFIG_OF_ADDRESSHongbo Yao2020-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_ADDRESS is not set and COMPILE_TEST=y, the following error is seen while building phy-j721e-wiz.c drivers/phy/ti/phy-j721e-wiz.o: In function `wiz_remove': phy-j721e-wiz.c:(.text+0x1a): undefined reference to `of_platform_device_destroy' Fix the config dependency for PHY_J721E_WIZ here. Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Hongbo Yao <yaohongbo@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20200117212310.2864-1-kishon@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * Merge tag 'phy-for-5.6_v2' of ↵Greg Kroah-Hartman2020-01-1725-566/+3027
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 5.6 *) Add support in PHY core to create link between PHY consumer and PHY provider *) Add DisplayPort PHY configuration set to be used for negotiating the configurations to be used between DisplayPort controller and DisplayPort PHY *) Add PHY wrapper driver (configure inputs to Cadence Sierra PHY) for TI's J721E SoC and adapt Cadence Sierra PHY driver to be used for J721E SoC (Supports USB and PCIe) *) Add PHY driver for eMMC PHY in Intel LGM SoC *) Add PHY support for 7216 and 7211 Broadcom SoCs which uses the new Synopsys USB Controller *) Add support for 16nm SATA PHY present in Broadcom 7216 SoC *) Fix lost packet issue, fix MDIO from getting inaccessible, fix occasional transaction failures, fix USB driver from crashing in Broadcom USB PHY driver *) Fix missing PCS SW reset in UFS PHY of Qualcomm SM8150 *) Use "struct phy_configure_opts_mipi_dphy" to pass parameters from display controller to rockchip-inno-dsidphy *) Other cleanups including compile testing for some of the PHY drivers, fixing Kconfig indentation, duplicate writes in drivers etc., Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (54 commits) dt-bindings: phy: Add PHY_TYPE_DP definition phy: ti: j721e-wiz: Fix return value check in wiz_probe() dt-bindings: usb: Convert Allwinner A80 USB PHY controller to a schema phy: intel-lgm-emmc: Fix warning by adding missing MODULE_LICENSE phy: ti: j721e-wiz: Manage typec-gpio-dir dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO phy: cadence: Sierra: add phy_reset hook phy: cadence: Sierra: remove redundant initialization of pointer regmap phy: Add DisplayPort configuration options phy: Enable compile testing for some of drivers phy: mediatek: Fix Kconfig indentation phy: intel-lgm-emmc: Add support for eMMC PHY dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC dt-bindings: phy: Document WIZ (SERDES wrapper) bindings phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 phy: cadence: Sierra: Check for PLL lock during PHY power on phy: cadence: Sierra: Get reset control "array" for each link ...
| | * phy: ti: j721e-wiz: Fix return value check in wiz_probe()Wei Yongjun2020-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: intel-lgm-emmc: Fix warning by adding missing MODULE_LICENSERamuthevar Vadivel Murugan2020-01-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 95f1061f715e ("phy: intel-lgm-emmc: Add support for eMMC PHY") introduces the below warning WARNING: modpost: missing MODULE_LICENSE() in drivers/phy/intel/phy-intel-emmc.o Fix it by adding missing MODULE_LICENSE. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: ti: j721e-wiz: Manage typec-gpio-dirRoger Quadros2020-01-141-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on this GPIO state we need to configure LN10 bit to swap lane0 and lane1 if required (flipped connector). Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Use the DT property to figure out if we need to add delay or not before sampling the Type-C DIR line. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: add phy_reset hookRoger Quadros2020-01-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms e.g. J721e need lane swap register to be programmed before reset is deasserted. This patch ensures that we propagate the phy_reset back to the reset controller driver. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: remove redundant initialization of pointer regmapColin Ian King2020-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pointer regmap is being initialized with a value that is never read and it is being updated later with a new value from phy->regmap_common_cdb. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: Enable compile testing for some of driversKrzysztof Kozlowski2020-01-146-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the phy drivers can be compile tested to increase build coverage. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: mediatek: Fix Kconfig indentationKrzysztof Kozlowski2020-01-141-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust indentation from spaces to tab (+optional two spaces) as in coding style. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: intel-lgm-emmc: Add support for eMMC PHYRamuthevar Vadivel Murugan2020-01-145-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | Add support for eMMC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCKishon Vijay Abraham I2020-01-143-0/+914
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig), two divider clocks and supports resets for each of the lanes. [jsarha@ti.com: Add support for Torrent(10G) SERDES wrapper] Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Kishon Vijay Abraham I2020-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | commit 44d30d622821d3b ("phy: cadence: Add driver for Sierra PHY"), incorrectly used parent device pointer to get driver data. Fix it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency ↵Kishon Vijay Abraham I2020-01-081-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to 25MHz Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz as specified in "Common Module Clock Configurations" of the Cadence Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz since the only user of Cadence Sierra SERDES, TI J721E SoC provides input clock frequency of 100MHz. For other frequencies, cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured based on the "Common Module Clock Configurations". Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Kishon Vijay Abraham I2020-01-081-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | Sierra SERDES IP supports upto 16 lanes (though not all of it will be enabled in a platform). Allow Sierra driver to support a maximum of upto 16 lanes. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Check for PLL lock during PHY power onKishon Vijay Abraham I2020-01-081-1/+32
| | | | | | | | | | | | | | | | | | Check for PLL lock during PHY power on. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Get reset control "array" for each linkKishon Vijay Abraham I2020-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | A link may have multiple lanes each with a separate reset. Get reset control "array" in order to reset all the lanes associated with the link. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ↵Anil Varughese2020-01-081-96/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | external SSC The existing configuration done in Cadence Sierra driver is only for reference and is not used in any platforms. Remove them and configure both lane cdb and common cdb registers to be used with external SSC configuration. This is validated in TI J721E platform. Signed-off-by: Anil Varughese <aniljoy@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Modify register macro names to be in sync with Sierra ↵Kishon Vijay Abraham I2020-01-081-83/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | user guide No functional change. Modify register offset macro names to be in sync with Sierra user guide. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_opsKishon Vijay Abraham I2020-01-081-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | Instead of invoking cdns_sierra_phy_init() from probe, add it in phy_ops so that it's initialized when the PHY consumer invokes phy_init() Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoCKishon Vijay Abraham I2020-01-081-0/+14
| | | | | | | | | | | | | | | | | | | | | SERDES_16G in TI's J721E SoC uses Cadence Sierra PHY. Add support to use Cadence Sierra driver in J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Use "regmap" for read and write to Sierra registersKishon Vijay Abraham I2020-01-081-54/+237
| | | | | | | | | | | | | | | | | | | | | | | | Use "regmap" for read and write to Sierra registers. This is in perparation for adding SERDES_16G support present in TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resourcesKishon Vijay Abraham I2020-01-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Certain platforms like TI J721E using Cadence Sierra Serdes doesn't provide explicit phy_clk and reset (APB reset) control. Make them optional here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: usb: Add support for wake and USB low power mode for 7211 S2/S5Al Cooper2020-01-084-34/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for 7211 USB wake. Disable all possible 7211 USB logic for S2/S5 if USB wake is not enabled. On the 7211, the XHCI wake signal was not connected properly and only goes to the USB1_USB1_CTRL_TP_DIAG1 diagonstic register. The workaround is to have VPU code running that polls for the proper bit in the DIAG register and to wake the system when the bit is asserted. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: usb: USB driver is crashing during S3 resume on 7216Al Cooper2020-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a result of the USB 2.0 clocks not being disabled/enabled during suspend/resume on XHCI only systems. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: usb: bdc: Fix occasional failure with BDC on 7211Al Cooper2020-01-083-4/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | The BDC "Read Transaction Size" needs to be changed from 1024 bytes to 256 bytes to prevent occasional transaction failures. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: usb: PHY's MDIO registers not accessible without device installedAl Cooper2020-01-081-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When there is no device connected and FSM is enabled, the XHCI puts the PHY into suspend mode. When the PHY is put into suspend mode the USB LDO powers down the PHY. This causes the MDIO to be inaccessible and its registers reset to default. The fix is to disable FSM. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * phy: usb: fix driver to defer on clk_get deferAl Cooper2020-01-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Handle defer on clk_get because the new SCMI clock driver comes up after this driver. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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