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* pinctrl: sh-pfc: r8a7795: Add SATA pins, groups, and functionsWolfram Sang2017-12-211-0/+24
| | | | | | | Tested with a Salvator-XS and H3 ES2.0. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7791: Add tpu groups and functionFabrizio Castro2017-12-191-2/+40
| | | | | | | | This patch adds tpu groups and function to r8a7743/r8a7791/r8a7793. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add i2c5 pin groups and functionBiju Das2017-12-191-0/+41
| | | | | | | | Add i2c5 pin groups and function to r8a7745 PFC driver. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add tpu groups and functionFabrizio Castro2017-12-191-0/+101
| | | | | | | | This patch adds tpu groups and function to r8a7745/r8a7794. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add PWM[0123456] supportFabrizio Castro2017-12-191-0/+165
| | | | | | | | | This patch adds PFC PWM[0123456] pin groups and functions, enabling PWM on the r8a7794 and r8a7745. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a77995: Add CAN FD supportUlrich Hecht2017-12-051-0/+27
| | | | | | | This patch adds CAN FD[0-1] pinmux support to the r8a77995 SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a77995: Add CAN supportUlrich Hecht2017-12-051-0/+59
| | | | | | | This patch adds CAN[0-1] pinmux support to the r8a77995 SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Rename RTS{0,1,3,4}# pin function definitionsTakeshi Kihara2017-12-051-24/+24
| | | | | | | | | | | | This patch renames the pin function macro definitions of the GPSR5 and IPSR{0,3,5,6,12} registers value for the RTS{0,1,3,4}# pin. This is a correction because GPSR and IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Rename RTS{0,1,3,4}# pin function definitionsTakeshi Kihara2017-12-051-24/+24
| | | | | | | | | | | | | | This patch renames the pin function macro definitions of the GPSR and IPSR registers value for the RTS{0,1,3,4}# pin. This is a correction because GPSR and IPSR register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Drop remaining "_TANS" from comments] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7796: Fix to delete A20..A25 pins function definitionsTakeshi Kihara2017-12-051-12/+6
| | | | | | | | | | | | This patch fixes the macro definitions of A20..A25 pins function deleted. This is a correction because IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Fix to delete A20..A25 pins function definitionsTakeshi Kihara2017-12-051-12/+6
| | | | | | | | | | | | This patch fixes the macro definitions of A20..A25 pins function deleted. This is a correction because IPSR register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795-es1: Fix MOD_SEL1 bit[25:24] to 0x3 when using ↵Takeshi Kihara2017-12-051-1/+1
| | | | | | | | | | | | | | | | STP_ISEN_1_D This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] value when STP_ISEN_1_D pin function is selected for IPSR16 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E. Fixes: 0b0ffc96dbe30fa9 ("pinctrl: sh-pfc: Initial R8A7795 PFC support) Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Add GP-1-28 port pin supportTakeshi Kihara2017-12-051-6/+8
| | | | | | | | | | This patch supports GP-1-28 port pin of R8A7795 ES2.0 SoC added in Rev.0.54E of the R-Car Gen3 Hardware User's Manual or later version. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Update forgotten PUEN2 entry] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a77995: Add missing pins SCL0 and SDA0 to pinmux dataUlrich Hecht2017-12-051-0/+2
| | | | | | | Required for I2C0 operation. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7791: Add can_clk functionFabrizio Castro2017-12-051-1/+21
| | | | | | | | | | | This patch adds can_clk function to r8a7743/r8a7791 which is cleaner, and allows for independent configuration. We keep the can_clk* pins definitions from within can0_groups and can1_groups for uniformity and backwards compatibility. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add can_clk functionFabrizio Castro2017-12-051-0/+20
| | | | | | | | | | | This patch adds can_clk function to r8a7745/r8a7794 which is cleaner, and allows for independent configuration. We keep the can_clk* pins definitions from within can0_groups and can1_groups for uniformity and backwards compatibility. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Add R8A77970 PFC supportSergei Shtylyov2017-12-055-0/+2342
| | | | | | | | | | | | | | | Add the PFC support for the R8A77970 SoC including pin groups for some on-chip devices such as CAN-FD, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM, VIN... Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> [geert: Drop EtherAVB for now] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Add PORT_GP_CFG_{6|22}() helper macrosSergei Shtylyov2017-11-281-4/+12
| | | | | | | | | | | | They follow the style of the existing PORT_GP_CFG_<n>() macros and will be used by a follow-up patch for the R8A77970 SoC. Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Add CAN FD supportRamesh Shanmugasundaram2017-11-281-0/+37
| | | | | | | | | This patch adds CAN FD[0-1] pinmux support for R-Car H3 ES2.0. The pin config is identical to H3 ES1.*. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7795: Add CAN supportRamesh Shanmugasundaram2017-11-281-0/+52
| | | | | | | | | This patch adds CAN[0-1] pinmux support for R-Car H3 ES2.0. The pin config is identical to H3 ES1.*. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7745: Add CAN[01] supportFabrizio Castro2017-11-281-0/+146
| | | | | | | | | This patch adds PFC CAN0 and CAN1 pin groups and functions, enabling CAN bus on the RZ/G1E. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Merge tag 'pinctrl-v4.15-1' of ↵Linus Torvalds2017-11-1611-951/+3048
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.15 kernel cycle: Core: - The pin control Kconfig entry PINCTRL is now turned into a menuconfig option. This obviously has the implication of making the subsystem menu visible in menuconfig. This is happening because of two things: (a) Intel have started to deploy and depend on pin controllers in a way that is affecting users directly. This happens on the highly integrated laptop chipsets named after geographical places: baytrail, broxton, cannonlake, cedarfork, cherryview, denverton, geminilake, lewisburg, merrifield, sunrisepoint... It started a while back and now it is ever more evident that this is crucial infrastructure for x86 laptops and not an embedded obscurity anymore. Users need to be aware. (b) Pin control expanders on I2C and SPI that are arch-agnostic. Currently Semtech SX150X and Microchip MCP28x08 but more are expected. Users will have to be able to configure these in directly for their set-up. - Just go and select GPIOLIB now that we made sure that GPIOLIB is a very vanilla subsystem. Do not depend on it, if we need it, select it. - Exposing the pin control subsystem in menuconfig uncovered a bunch of obscure bugs that are now hopefully fixed, all more or less pertaining to Blackfin. - Unified namespace for cross-calls between pin control and GPIO. - New support for clock skew/delay generic DT bindings and generic pin config options for this. - Minor documentation improvements. Various: - The Renesas SH-PFC pin controller has evolved a lot. It seems Renesas are churning out new SoCs by the minute. - A bunch of non-critical fixes for the Rockchip driver. - Improve the use of library functions instead of open coding. - Support the MCP28018 variant in the MCP28x08 driver. - Static constifying" * tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (91 commits) pinctrl: gemini: Fix missing pad descriptions pinctrl: Add some depends on HAS_IOMEM pinctrl: samsung/s3c24xx: add CONFIG_OF dependency pinctrl: gemini: Fix GMAC groups pinctrl: qcom: spmi-gpio: Add pmi8994 gpio support pinctrl: ti-iodelay: remove redundant unused variable dev pinctrl: max77620: Use common error handling code in max77620_pinconf_set() pinctrl: gemini: Implement clock skew/delay config pinctrl: gemini: Use generic DT parser pinctrl: Add skew-delay pin config and bindings pinctrl: armada-37xx: Add edge both type gpio irq support pinctrl: uniphier: remove eMMC hardware reset pin-mux pinctrl: rockchip: Add iomux-route switching support for rk3288 pinctrl: intel: Add Intel Cedar Fork PCH pin controller support pinctrl: intel: Make offset to interrupt status register configurable pinctrl: sunxi: Enforce the strict mode by default pinctrl: sunxi: Disable strict mode for old pinctrl drivers pinctrl: sunxi: Introduce the strict flag pinctrl: sh-pfc: Save/restore registers for PSCI system suspend pinctrl: sh-pfc: r8a7796: Use generic IOCTRL register description ...
| * Merge tag 'sh-pfc-for-v4.15-tag2' of ↵Linus Walleij2017-10-2010-977/+2330
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.15 (take two) - Add Audio, HSCIF, I2C, and INTC-EX pin groups on R-Car H3 ES2.0, - Add Audio and PWM pin groups on R-Car D3, - Add support for RZ/A1M and RZ/A1L, - Add INTC-EX pin groups on R-Car M3-W, - Add SDHI voltage switching on RZ/G1E, - Make bias control and IOCTRL support more generic, - Add suspend/resume support for R-Car Gen3, - Small fixes and cleanups.
| | * pinctrl: sh-pfc: Save/restore registers for PSCI system suspendGeert Uytterhoeven2017-10-202-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their pinctrl register state is lost. Note that as the boot loader skips most initialization after system resume, pinctrl register state differs from the state encountered during normal system boot, too. To fix this, save all GPIO and peripheral function select, module select, drive strength control, bias, and other I/O control registers during system suspend, and restore them during system resume. Note that to avoid overhead on platforms not needing it, the suspend/resume code has a build time dependency on sleep and PSCI support, and a runtime dependency on PSCI. Inspired by a patch in the BSP by Hien Dang. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7796: Use generic IOCTRL register descriptionGeert Uytterhoeven2017-10-201-1/+11
| | | | | | | | | | | | | | | | | | | | | Move R-Car M3-W I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Use generic IOCTRL register descriptionGeert Uytterhoeven2017-10-201-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | Move R-Car H3 ES2.0 I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795-es1: Use generic IOCTRL register descriptionGeert Uytterhoeven2017-10-201-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | Move R-Car H3 ES1.x I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: Add generic IOCTRL register descriptionGeert Uytterhoeven2017-10-201-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a generic way to describe IOCTRL registers (for e.g. SD I/O voltage and time delay control), like is already done for config, drive, and bias registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: Remove obsolete sh_pfc_pin_to_bias_info()Geert Uytterhoeven2017-10-203-24/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | All users of sh_pfc_pin_to_bias_info() and the related data structures have been converted to sh_pfc_pin_to_bias_reg(), so those can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| | * pinctrl: sh-pfc: r8a7778: Use generic bias register descriptionGeert Uytterhoeven2017-10-201-181/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move R-Car M1A bias support over to the generic way to describe bias registers. As the new description is more compact, this decreases kernel size by ca. 148 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7796: Use generic bias register descriptionGeert Uytterhoeven2017-10-201-241/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move R-Car M3-W bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Use generic bias register descriptionGeert Uytterhoeven2017-10-201-241/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move R-Car H3 ES2.0 bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 308 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795-es1: Use generic bias register descriptionGeert Uytterhoeven2017-10-201-241/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move R-Car H3 ES1.x bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| | * pinctrl: sh-pfc: Add sh_pfc_pin_to_bias_reg() helperGeert Uytterhoeven2017-10-202-0/+23
| | | | | | | | | | | | | | | | | | | | | Add a helper to look up bias registers and bit number for a specific pin, using the generic bias register description. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: Add generic bias register descriptionGeert Uytterhoeven2017-10-201-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a generic way to describe bias registers (for pull-up/down control), like is already done for config and drive registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| | * pinctrl: sh-pfc: Drop width parameter of sh_pfc_{read,write}_reg()Geert Uytterhoeven2017-10-206-31/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of sh_pfc_{read,write}_reg() already operate on 32-bit registers only. Hence make the 32-bit width implicit, and rename the functions to sh_pfc_{read,write}() to shorten lines. All accesses to 8-bit or 16-bit registers are still done using sh_pfc_{read,write}_raw_reg(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| | * pinctrl: sh-pfc: Remove matching on plain sh-pfc platform deviceGeert Uytterhoeven2017-10-201-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit 8682b3c522c639f3 ("sh-pfc: Remove platform device registration"), plain "sh-pfc" platform devices are no longer created. Hence remove their match entry, and the now obsolete checks for missing device IDs and driver data. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| | * pinctrl: sh-pfc: r8a7745: Implement voltage switching for SDHIBiju Das2017-10-161-0/+1
| | | | | | | | | | | | | | | | | | | | | Voltage switching is the same as on the r8a7794. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a77995: Remove USB0_IDIN and USB0_IDPU pinsGeert Uytterhoeven2017-10-161-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017 removed the USB0_IDIN and USB0_IDPU pins on R-Car D3. This change has no functional impact, as these definitions were unused. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a77995: Add Audio SSI pin supportKuninori Morimoto2017-10-111-0/+60
| | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a77995: Add Audio clock pin supportKuninori Morimoto2017-10-111-0/+42
| | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7796: Fix trivial typo in commentWolfram Sang2017-10-111-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795-es1: Fix trivial typo in commentWolfram Sang2017-10-111-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Fix trivial typo in commentWolfram Sang2017-10-111-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functionsWolfram Sang2017-10-111-0/+283
| | | | | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7796: Add support for INTC-EX IRQ pinsTakeshi Kihara2017-10-111-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most pins on the r8a7796 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". [takeshi.kihara.df: Ported from commit bb46f6f3f3bf ("pinctrl: sh-pfc: r8a7795: Add support for INTC-EX IRQ pins") to drivers/pinctrl/sh-pfc/pfc-r8a7796.c] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Add INTC-EX pins, groups and functionGeert Uytterhoeven2017-10-111-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and a function for the INTC-EX interrupt controller on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Restore sort orderGeert Uytterhoeven2017-10-051-16/+16
| | | | | | | | | | | | | | | | | | Move the SCIF_CLK pins where they belong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795-es1: Restore sort orderGeert Uytterhoeven2017-10-051-17/+17
| | | | | | | | | | | | | | | | | | Move the USB30 pins where they belong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Add I2C pin supportWolfram Sang2017-10-041-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since pinmuxing for I2C is equal on H3 ES1.0 and later versions, copy the I2C settings from ES1.0. Fixes this error in upstream for Salvator-XS: sh-pfc e6060000.pin-controller: function 'i2c2' not supported sh-pfc e6060000.pin-controller: invalid function i2c2 in map table i2c-rcar: probe of e6510000.i2c failed with error -22 Now, the bus works the same as with other Salvator boards. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-18 05:09:11 +0000