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* pinctrl: sunrisepoint: Align GPIO number space with WindowsMika Westerberg2018-05-021-3/+42
| | | | | | | | | | | | | | | | | | | | It turns out that the Windows GPIO driver for Sunrisepoint PCH-H uses similar bank structure than it does for Cannon Lake with the exception that here the bank size is always 24 pins. Starting from pad group E the BIOS/Windows GPIO numbering does not match the hardware anymore but instead there are gaps to make each pad group ("bank") consume exactly 24 pins. Because of this Linux does not use correct pins for GpioIo/GpioIo resources exposed by the BIOS. This patch aligns the GPIO number space with BIOS/Windows to make sure the same numbering scheme is used in Linux as well following what we did already for Intel Cannon Lake. Link: https://bugzilla.redhat.com/show_bug.cgi?id=1543769 Reported-by: Vivien FRASCA <vivien.frasca@gmail.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: cherryview: Associate IRQ descriptors to irqdomainMika Westerberg2018-05-021-4/+12
| | | | | | | | | | | | | | | | | | | | | | | When we dropped the custom Linux GPIO translation it resulted that the IRQ numbers changed slightly as well. Normally this would be fine because everyone is expected to use controller relative GPIO numbers and ACPI GpioIo/GpioInt resources. However, there is a certain set of Intel_Strago based Chromebooks where i8042 keyboard controller IRQ number is hardcoded be 182 (this is corrected with newer coreboot but the older ones still have the hardcoded Linux IRQ number). Because of this hardcoded IRQ number keyboard on those systems accidentally broke again. Fix this by iteratively associating IRQ descriptors to the chip irqdomain so that there are no gaps on those systems. Other systems are not affected. Fixes: 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") Link: https://bugzilla.kernel.org/show_bug.cgi?id=199463 Reported-by: Sultan Alsawaf <sultanxda@gmail.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: meson-axg: fix the range of aobus bankYixun Lan2018-05-021-1/+1
| | | | | | | | | | The GPIOAO bank is range from GPIOAO_0 to GPIOAO_13. Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC") Reported-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'gpio-v4.17-1' of ↵Linus Torvalds2018-04-051-3/+62
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.17 kernel cycle: New drivers: - Nintendo Wii GameCube GPIO, known as "Hollywood" - Raspberry Pi mailbox service GPIO expander - Spreadtrum main SC9860 SoC and IEC GPIO controllers. Improvements: - Implemented .get_multiple() callback for most of the high-performance industrial GPIO cards for the ISA bus. - ISA GPIO drivers now select the ISA_BUS_API instead of depending on it. This is merged with the same pattern for all the ISA drivers and some other Kconfig cleanups related to this. Cleanup: - Delete the TZ1090 GPIO drivers following the deletion of this SoC from the ARM tree. - Move the documentation over to driver-api to conform with the rest of the kernel documentation build. - Continue to make the GPIO drivers include only <linux/gpio/driver.h> and not the too broad <linux/gpio.h> that we want to get rid of. - Managed to remove VLA allocation from two drivers pending more fixes in this area for the next merge window. - Misc janitorial fixes" * tag 'gpio-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (77 commits) gpio: Add Spreadtrum PMIC EIC driver support gpio: Add Spreadtrum EIC driver support dt-bindings: gpio: Add Spreadtrum EIC controller documentation gpio: ath79: Fix potential NULL dereference in ath79_gpio_probe() pinctrl: qcom: Don't allow protected pins to be requested gpiolib: Support 'gpio-reserved-ranges' property gpiolib: Change bitmap allocation to kmalloc_array gpiolib: Extract mask allocation into subroutine dt-bindings: gpio: Add a gpio-reserved-ranges property gpio: mockup: fix a potential crash when creating debugfs entries gpio: pca953x: add compatibility for pcal6524 and pcal9555a gpio: dwapb: Add support for a bus clock gpio: Remove VLA from xra1403 driver gpio: Remove VLA from MAX3191X driver gpio: ws16c48: Implement get_multiple callback gpio: gpio-mm: Implement get_multiple callback gpio: 104-idi-48: Implement get_multiple callback gpio: 104-dio-48e: Implement get_multiple callback gpio: pcie-idio-24: Implement get_multiple/set_multiple callbacks gpio: pci-idio-16: Implement get_multiple callback ...
| * pinctrl: qcom: Don't allow protected pins to be requestedStephen Boyd2018-03-271-3/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues and reset the device. With a DT/ACPI property to describe the set of pins that are available for use, parse the available pins and set the irq valid bits for gpiolib to know what to consider 'valid'. This should avoid any issues with gpiolib. Furthermore, implement the pinmux_ops::request function so that pinmux can also make sure to not use pins that are unavailable. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Timur Tabi <timur@codeaurora.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'pinctrl-v4.17-1' of ↵Linus Torvalds2018-04-0370-7246/+13148
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control bulk updates from Linus Walleij: "New drivers: - Qualcomm SDM845: this is their new flagship SoC platform which seems to be targeted at premium mobile handsets. - Renesas R-Car M3-N SoC. - Renesas R8A77980 SoC. - NXP (ex Freescale) i.MX 6SLL SoC. - Mediatek MT2712 SoC. - Allwinner H6 SoC. Improvements: - Uniphier adds a few new functions and pins. - Renesas refactorings and additional pin definitions. - Improved pin groups for Axis Artpec6. Cleanup: - Drop the TZ1090 drivers. This platform is no longer maintained and is being deleted. - Drop ST-Ericsson U8540/U9540 support as this was never productified. - Overall minor fixes and janitorial" * tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits) pinctrl: uniphier: add UART hardware flow control pin-mux settings pinctrl: sunxi: add support for the Allwinner H6 main pin controller pinctrl: sunxi: change irq_bank_base to irq_bank_map pinctrl: sunxi: introduce IRQ bank conversion function pinctrl: sunxi: refactor irq related register function to have desc pinctrl: msm8998: Remove owner assignment from platform_driver pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group pinctrl: uniphier: add PXs2 Audio in/out pin-mux settings pinctrl/amd: poll InterruptEnable bits in enable_irq pinctrl: ocelot: fix gpio direction pinctrl: mtk: fix check warnings. pintcrl: mtk: support bias-disable of generic and special pins simultaneously pinctrl: add mt2712 pinctrl driver pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0 pinctrl: imx: Add pinctrl driver support for imx6sll dt-bindings: imx: update pinctrl doc for imx6sll pinctrl: intel: Implement intel_gpio_get_direction callback pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependency pinctrl: mediatek: mtk-common: use true and false for boolean values pinctrl: sunxi: always look for apb block ...
| * | pinctrl: uniphier: add UART hardware flow control pin-mux settingsKunihiko Hayashi2018-03-279-9/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UniPhier SoCs have the following pins for hardware flow control of UART: XRTS, XCTS and for modem control of UART: XDTR, XDSR, XDCD, XRI The port number with the flow control is SoC-dependent. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: add support for the Allwinner H6 main pin controllerIcenowy Zheng2018-03-273-0/+619
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC has two pin controllers, one main controller (called CPUX-PORT in user manual) and one controller in CPUs power domain (called CPUS-PORT in user manual). This commit introduces support for the main pin controller on H6. The pin bank A and B are not wired out and hidden from the SoC's documents, however it's shown that the "ATE" (an AC200 chip co-packaged with the H6 die) is connected to the main SoC die via these pin banks. The information about these banks is just copied from the BSP pinctrl driver, but re-formatted to fit the mainline pinctrl driver format. The GPIO functions are dropped, as they're impossible to use -- except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: change irq_bank_base to irq_bank_mapIcenowy Zheng2018-03-273-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: introduce IRQ bank conversion functionIcenowy Zheng2018-03-271-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some refactors in the sunxi pinctrl framework are needed. This commit introduces a IRQ bank conversion function, which replaces the "(bank_base + bank)" code in IRQ register access. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: refactor irq related register function to have descIcenowy Zheng2018-03-272-20/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | As the new H6 SoC has holes in the IRQ registers, refactor the IRQ related register function for getting the full pinctrl desc structure. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: msm8998: Remove owner assignment from platform_driverFabio Estevam2018-03-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platform_driver does not need to set the owner field, as this will be populated by the driver core. Generated by scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux groupKatsuhiro Suzuki2018-03-272-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch divides large pin-mux group 'aio' of UniPhier LD11/LD20 to 2 groups as following: aout1 : 8ch I2S output: AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2] aoutiec1: S/PDIF output : AO1IEC, AO1ARC Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: uniphier: add PXs2 Audio in/out pin-mux settingsKatsuhiro Suzuki2018-03-271-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UniPhier PXs2 SoC audio core use following 25 pins: ain1 : 2ch I2S input : AI1ADCCK, AI1BCK, AI1D0, AI1LRCK ain2 : 8ch I2S input : AI2ADCCK, AI2BCK, AI2D[0-3], AI2LRCK ainiec1 : S/PDIF input : XIRQ17 (for AO1IEC) aout2 : 8ch I2S output: AO2BCK, AO2D0, AO2DACCK, AO2LRCK PORT226, 227, 230 (for AO2D[1-3]) aout3 : 2ch I2S output: AO3BCK, AO3DMIX, AO3DACCK, AO3LRCK aoutiec1: S/PDIF output : PORT132(for AO1IEC) aoutiec2: S/PDIF output : AO2IEC Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl/amd: poll InterruptEnable bits in enable_irqDaniel Kurtz2018-03-261-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In certain cases interrupt enablement will be delayed relative to when the InterruptEnable bits are written. One example of this is when a GPIO's "debounce" logice is first enabled. After enabling debounce, there is a 900 us "warm up" period during which InterruptEnable[0] (bit 11) will read as 0 despite being written 1. During this time InterruptSts will not be updated, nor will interrupts be delivered, even if the GPIO's interrupt configuration has been written to the register. To work around this delay, poll the InterruptEnable bits after setting them to ensure interrupts have truly been enabled in hardware before returning from the irq_enable handler. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: ocelot: fix gpio directionAlexandre Belloni2018-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bits have to be cleared in DEVCPU_GCB:GPIO:GPIO_OE for input and set for output. ocelot_gpio_set_direction() got it wrong and this went unnoticed when the driver was reworked. Reported-by: Gregory Clement <gregory.clement@bootlin.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mtk: fix check warnings.Zhiyong Tao2018-03-265-1604/+802
| | | | | | | | | | | | | | | | | | | | | This patch fixes check warnings. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pintcrl: mtk: support bias-disable of generic and special pins simultaneouslyZhiyong Tao2018-03-261-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For generic pins, parameter "arg" is 0 or 1. For special pins, bias-disable is set by R0R1, so we need transmited "00" to set bias-disable When we set "bias-disable" as high-z property, the parameter should be "MTK_PUPD_SET_R1R0_00". Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: add mt2712 pinctrl driverZhiyong Tao2018-03-264-0/+2398
| | | | | | | | | | | | | | | | | | | | | | | | The commit includes mt2712 pinctrl driver. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0David Lechner2018-03-261-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes pcs_request_gpio() in the pinctrl-single driver when bits_per_mux != 0. It appears this was overlooked when the multiple pins per register feature was added. Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Signed-off-by: David Lechner <david@lechnology.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: imx: Add pinctrl driver support for imx6sllBai Ping2018-03-233-0/+368
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl driver support for imx6sll. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: intel: Implement intel_gpio_get_direction callbackJavier Arteaga2018-03-231-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows querying GPIO direction from the pad config register. If the pad is not in GPIO mode, return an error. Signed-off-by: Javier Arteaga <javier@emutex.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependencyMasahiro Yamada2018-03-231-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These configs select MFD_SYSCON, but do not depend on HAS_IOMEM. Compile testing on architecture without HAS_IOMEM causes "unmet direct dependencies" in Kconfig phase. Detected by "make ARCH=score allyesconfig". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mediatek: mtk-common: use true and false for boolean valuesGustavo A. R. Silva2018-03-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Assign true or false to boolean variables instead of an integer value. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: always look for apb blockAndre Przywara2018-03-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner pinctrl device tree binding suggests that a clock named "apb" would drive the pin controller IP. However (for legacy reasons) we rely on this clock actually being the first clock defined. Since named clocks can be in any order, let's explicitly check for a clock called "apb" if there is more than one clock referenced. Kudo to Maxime for suggesting this much more elegant approach. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: nomadik: Drop U8540/9540 supportLinus Walleij2018-03-237-2376/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The U8540 was an evolved version of the U8500, but it was never mass produced or put into products, only reference designs exist. The upstream support was never completed and it is unlikely that this will happen so drop the support for now to simplify maintenance of the U8500. Cc: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'sh-pfc-for-v4.17-tag2' of ↵Linus Walleij2018-03-2312-635/+3198
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.17 (take two) - Add USB pin groups on R-Car M3-N, - Add support for the new R-Car V3H SoC, - Add EtherAVB pin groups on R-Car V3M, - Miscellaneous fixes and cleanups.
| | * | pinctrl: sh-pfc: r8a77995: Deduplicate VIN4 pin definitionsUlrich Hecht2018-03-211-118/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitionsUlrich Hecht2018-03-211-236/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitionsUlrich Hecht2018-03-211-236/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77995: Correct VIN4 18-bit pinsUlrich Hecht2018-03-211-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RGB666 has a pin assignment that differs from the other formats. Fixes: fbd452aeb49e552e ("pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function") Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7796: Correct VIN4 18-bit pinsUlrich Hecht2018-03-211-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RGB666 has a pin assignment that differs from the other formats. Fixes: 8db6cbabac4f2a02 ("pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions") Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Correct VIN4 18-bit pinsUlrich Hecht2018-03-211-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RGB666 has a pin assignment that differs from the other formats. Fixes: 6b4de408105fc51e ("pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions") Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77995: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 66abd968d0ef3eb1 ("pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a77965: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: fa3e8b71b955af86 ("pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7796: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 41397032c4a17dff ("pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pins") Fixes: 9c99a63ec74f34f7 ("pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7795-es1: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: b25719eb938eb39a ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins") Fixes: 819fd4bfcc84805c ("pinctrl: sh-pfc: r8a7795: add EtherAVB support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7795: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 30c078de6f3785fe ("pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: Add SH_PFC_PIN_GROUP_ALIAS()Geert Uytterhoeven2018-03-211-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a macro to refer to another pin group with a different name. This will be used to rename wrongly-named pin groups, while retaining backwards compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii groupGeert Uytterhoeven2018-03-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin controller drivers for all R-Car Gen2 SoCs have entries for the EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2. Add the missing pin to restore consistency. Note that technically TX_ER is an optional signal in the MII bus, and thus could have its own group, but this is currently not supported by any R-Car Gen2 pin controller driver. Fixes: 19ef697d1eb7be06 ("sh-pfc: r8a7790: add EtherAVB pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77970: Add EtherAVB pin groupsSergei Shtylyov2018-03-141-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the EtherAVB pin groups to the R8A77970 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: Add R8A77980 PFC supportSergei Shtylyov2018-03-095-0/+2812
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PFC support for the R8A77980 SoC including pin groups for some on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM, and VIN... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: Add PORT_GP_CFG_25() helper macroSergei Shtylyov2018-03-091-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | They follow the style of the existing PORT_GP_CFG_<n>() macros and will be used by a follow-up patch for the R8A77980 SoC. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77965: Add USB3.0 host pins, groups and functionsTakeshi Kihara2018-03-051-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB30 (USB3.0 host) pin, group and function to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77965: Add USB2.0 host pins, groups and functionsTakeshi Kihara2018-03-051-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | Merge tag 'sh-pfc-for-v4.17-tag1' of ↵Linus Walleij2018-03-0210-49/+4657
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.17 - Add DU and VIN pin groups on R-Car D3, - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W, - Add support for the new R-Car M3-N SoC, - Small fixes and cleanups.
| | * | pinctrl: sh-pfc: r8a77965: Add support for INTC-EX IRQ pinsTakeshi Kihara2018-02-281-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most pins on the R8A77965 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Based on a similar patch for the R8A7795 PFC driver by Magnus Damm <damm+renesas@opensource.se>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and functionUlrich Hecht2018-02-261-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds VIN4 pins, groups and function for the R8A77995 (D3) SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functionsUlrich Hecht2018-02-261-0/+454
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds VIN4 and VIN5 pins, groups and functions for the R8A7795 SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functionsUlrich Hecht2018-02-261-0/+454
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds VIN4 and VIN5 pins, groups and functions for the R8A7796 SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 12:36:07 +0000