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* | pinctrl: core: Add missing EXPORT on pinctrl_register_mappingsRichard Fitzgerald2018-03-021-0/+1
| | | | | | | | | | | | | | | | | | Systems that don't have devicetree need pinctrl_register_mappings. It should be EXPORT_SYMBOL_GPL so that it can be called from pinctrl drivers built as modules. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8b: fix requesting GPIOs greater than GPIOZ_3Martin Blumenstingl2018-03-021-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Meson8b is a cost reduced variant of the Meson8 SoC. It's package size is smaller than Meson8. Unfortunately there are a few key differences which cannot be seen without close inspection of the code and the public S805 datasheet: - the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and GPIOX_15 GPIOs - the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and GPIOY_16 GPIOs - the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24, GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29 - the GPIOZ bank is missing completely - there is a new GPIO bank called "DIF" This means that Meson8b only has 83 actual GPIO lines. Without any holes there would be 130 GPIO lines in total (120 are inherited from Meson8 plus 10 new from the DIF bank). GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly the number of actual GPIO lines on Meson8b and also the value of meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6 (which used ID 100 prior to this patch, "base of the GPIO controller was 382) as an example: $ echo 482 > /sys/class/gpio/export export_store: invalid GPIO 482 This removes all non-existing pins from to dt-bindings header file (include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get compile-time (instead of runtime) errors if Meson8b .dts uses a pin that only exists on Meson8. Additionally the pinctrl-meson8b driver has to be updated to handle this new GPIO numbering. By default a struct meson_bank only handles GPIO banks where the pins are numbered consecutively because it calculates the bit offsets based on the GPIO IDs. This is solved by taking the original BANK() definition and splitting it into consecutive subsets (X0..11 and X16..21). The bit offsets for each new bank includes the skipped GPIOs (the definition of the "X0..11" bank is identical to the old "X" bank apart from the "last IRQ" field, the definition of the new, split "X16..21" bank takes the original "X" bank and adds 16 - the start of the new split bank - to the "first IRQ", pullen bit, pull bit, dir bit, out bit and in bit). Commit 984cffdeaeb7ea ("pinctrl: Fix gpio/pin mapping for Meson8b") fixed the same issue by setting "ngpio" (of the gpio_chip) to 130. Unfortunately this broke in db80f0e158e621 ("pinctrl: meson: get rid of unneeded domain structures"). The solution from this patch was considered to be better than the previous attempt at fixing this because it provides compile-time error checking for the GPIOs that exist on Meson8 but don't exist on Meson8b. The following pins were tested on an Odroid-C1 using the sysfs GPIO interface checking that their value (high or low) could be read: - GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6, GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19, GPIOX_20, GPIOX_21 - GPIOY_3, GPIOY_7, GPIOY_8 (some of these had to be pulled up because they were low by default, others were high by default so these had to be pulled down) Reported-by: Linus Lüssing <linus.luessing@c0d3.blue> Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: devicetree: Fix dt_to_map_one_config handling of hogsRichard Fitzgerald2018-03-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When dt_to_map_one_config() is called with a pinctrl_dev passed in, it should only be using this if the node being looked up is a hog. The code was always using the passed pinctrl_dev without checking whether the dt node referred to it. A pin controller can have pinctrl-n dependencies on other pin controllers in these cases: - the pin controller hardware is external, for example I2C, so needs other pin controller(s) to be setup to communicate with the hardware device. - it is a child of a composite MFD so its of_node is shared with the parent MFD and other children of that MFD. Any part of that MFD could have dependencies on other pin controllers. Because of this, dt_to_map_one_config() can't assume that if it has a pinctrl_dev passed in then the node it looks up must be a hog. It could be a reference to some other pin controller. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: stm32: Optimizes and enhances stm32gpio irqchipRadoslaw Pietrzyk2018-03-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | - removes unneeded irq_chip.irq_eoi callback - adds irq_chip.irq_set_wake callback for possible in the future GPIO wakeup - adds irq_chip.irq_ack callback Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Reviewed-by: Ludovic Barre <ludovic.barre@st.com> Tested-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: artpec-6: Add smaller groups for uartsJesper Nilsson2018-03-011-16/+50
| | | | | | | | | | | | | | | | | | | | | | | | Add group configuration for uarts that are cut down variants, the standard being full, i.e. all signals, flow control, i.e. rx/tx and cts/rts, and rx/tx only. This allows us to be more precise in which pins we're actually using. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Drop TZ1090 driversJames Hogan2018-03-014-3008/+0
| | | | | | | | | | | | | | | | | | | | | | Now that arch/metag/ has been removed, along with TZ1090 SoC support, remove the TZ1090 pinctrl drivers. They are of no value without the architecture and SoC platform code. Signed-off-by: James Hogan <jhogan@kernel.org> Cc: linux-gpio@vger.kernel.org Cc: linux-metag@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mcp23s08: add open drain configuration for irq outputPhil Reid2018-02-221-1/+6
| | | | | | | | | | | | | | | | | | | | | | The mcp23s08 series device can be configured for wired and interrupts using an external pull-up and open drain output via the IOCON_ODR bit. And "drive-open-drain" property to enable this. Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Phil Reid <preid@electromag.com.au> Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mcp23s08: fix probing of mcp23s18Phil Reid2018-02-221-2/+0
| | | | | | | | | | | | | | | | | | | | one_regmap_config is always null if mcp type is MCP_TYPE_S18. Remove the null check so that the mcp23s18 will probe. Fixes: 1781af563aef66c2eb7cda ("pinctrl: mcp23s08: spi: Fix duplicate pinctrl debugfs entries") Signed-off-by: Phil Reid <preid@electromag.com.au> Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl/amd: add get_direction handlerDaniel Kurtz2018-02-221-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On boot, gpiochip_add_data() initializes the FLAG_IS_OUT bit in desc->flags iff its gpio_chip does not have ->direction_input() handler, else it is initialized to 0, which implies the GPIO is an "input". Later, the sysfs "direction" handler will use gpiod_get_direction() to get the current direction, but if no ->get_direction() handler is installed, the result will just be the current (initial) value of flags, which will always be OUT irregardless of the initial register value. Add a get_direction() handler to pinctrl-amd to fix this and always provide the correct value for direction. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Re-use DEFINE_SHOW_ATTRIBUTE() macroAndy Shevchenko2018-02-221-78/+12
| | | | | | | | | | | | | | | | ...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: ocelot: make function ocelot_pinctrl_probe staticColin Ian King2018-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The function ocelot_pinctrl_probe is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: drivers/pinctrl/pinctrl-ocelot.c:465:5: warning: symbol 'ocelot_pinctrl_probe' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: add USB functions for STn8815Linus Walleij2018-02-131-1/+15
| | | | | | | | | | | | | | | | | | The MUSB block in the Nomadik has two pin settings: high speed or full speed. These correspond to two unique pin group settings: all pins set to function B for high speed and all set to function C for full speed. Full speed uses more pins than high speed. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: msm: Use dynamic GPIO numberingBjorn Andersson2018-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | The base of the TLMM gpiochip should not be statically defined as 0, fix this to not artificially restrict the existence of multiple pinctrl-msm devices. Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") Reported-by: Timur Tabi <timur@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mcp23s08: spi: Fix duplicate pinctrl debugfs entriesJan Kundrát2018-02-122-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a bit more involved because the pinctrl core so far always assumed that one device (with a unique dev_name) only contains a single pinctrl thing. This is not true for the mcp23s08 driver for chips connected over SPI. They have a "logical address" which means that several chips can share one physical CS signal. A downside of this patch are some possibly ugly names for the debugfs entries, such as "spi1.1-mcp23xxx-pinctrl.2", etc. Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mcp23s08: spi: Add HW address to gpio_chip.labelJan Kundrát2018-02-121-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When several devices are sharing one hardware SPI CS, there is no visual clue in `lsgpio` or in /sys/kernel/debug/gpio about which one is which one. Stuff depends on the enumeration order, and therefore lower chip addresses always go first, but that's just an implementation detail. This change includes the device-specific address in the debug output: gpiochip4: GPIOs 464-479, parent: spi/spi1.1, mcp23s17.2, can sleep: gpiochip3: GPIOs 480-495, parent: spi/spi1.1, mcp23s17.1, can sleep: Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mcp23s08: spi: Fix regmap debugfs entriesJan Kundrát2018-02-121-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI version of this chip allows several devices to be present on the same SPI bus via a local address. If this is in action and if the kernel has debugfs, however, the code attempts to create duplicate entries for the regmap's debugfs: mcp23s08 spi1.1: Failed to create debugfs directory This patch simply assigns a local name matching the device logical address to the `struct regmap_config`. No changes are needed for MCP23S18 because that device does not support any logical addressing. Similarly, I2C devices do not need any action, either, because they are already different in their I2C address. A similar problem is present for the pinctrl debugfs instance, but that one is not addressed by this patch. Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: Add sdm845 pinctrl driverKyle Yan2018-02-123-0/+1333
|/ | | | | | | | | This adds the pinctrl definitions for the TLMM of SDM845. Signed-off-by: Kyle Yan <kyan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.16-1' of ↵Linus Torvalds2018-02-02101-676/+12822
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.16 kernel cycle. Like with GPIO it is actually a bit calm this time. Core changes: - After lengthy discussions and partly due to my ignorance, we have merged a patch making pinctrl_force_default() and pinctrl_force_sleep() reprogram the states into the hardware of any hogged pins, even if they are already in the desired state. This only apply to hogged pins since groups of pins owned by drivers need to be managed by each driver, lest they could not do things like runtime PM and put pins to sleeping state even if the system as a whole is not in sleep. New drivers: - New driver for the Microsemi Ocelot SoC. This is used in ethernet switches. - The X-Powers AXP209 GPIO driver was extended to also deal with pin control and moved over from the GPIO subsystem. This circuit is a mixed-mode integrated circuit which is part of AllWinner designs. - New subdriver for the Qualcomm MSM8998 SoC, core of a high end mobile devices (phones) chipset. - New subdriver for the ST Microelectronics STM32MP157 MPU and STM32F769 MCU from the STM32 family. - New subdriver for the MediaTek MT7622 SoC. This is used for routers, repeater, gateways and such network infrastructure. - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC has multimedia features and target "smart devices", I guess in-car entertainment, in-flight entertainment, industrial control panels etc. General improvements: - Incremental improvements on the SH-PFC subdrivers for things like the CAN bus. - Enable the glitch filter on Baytrail GPIOs used for interrupts. - Proper handling of pins to GPIO ranges on the Semtec SX150X - An IRQ setup ordering fix on MCP23S08. - A good set of janitorial coding style fixes" * tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits) pinctrl: mcp23s08: fix irq setup order pinctrl: Forward declare struct device pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding pinctrl: stm32: add STM32F769 MCU support pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping pinctrl: sx150x: Register pinctrl before adding the gpiochip pinctrl: sx150x: Unregister the pinctrl on release pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe() pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show() pinctrl: pinmux: Use seq_putc() in pinmux_pins_show() pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show() pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call pinctrl: mediatek: mt7622: fix potential uninitialized value being returned pinctrl: uniphier: refactor drive strength get/set functions pinctrl: imx7ulp: constify struct imx_cfg_params_decode pinctrl: imx: constify struct imx_pinctrl_soc_info pinctrl: imx7d: simplify imx7d_pinctrl_probe pinctrl: imx: use struct imx_pinctrl_soc_info as a const pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly. pinctrl: qcom: Add msm8998 pinctrl driver ...
| * pinctrl: mcp23s08: fix irq setup orderDmitry Mastykin2018-01-301-4/+4
| | | | | | | | | | | | | | | | | | | | | | When using mcp23s08 module with gpio-keys, often (50% of boots) it fails to get irq numbers with message: "gpio-keys keys: Unable to get irq number for GPIO 0, error -6". Seems that irqs must be setup before devm_gpiochip_add_data(). Cc: stable@vger.kernel.org Signed-off-by: Dmitry Mastykin <mastichi@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2018-01-221-1/+2
| | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stm32: add STM32F769 MCU supportAlexandre Torgue2018-01-223-0/+1834
| | | | | | | | | | | | | | | | | | This patch which adds STM32F769 pinctrl and GPIO support, relies on the generic STM32 pinctrl driver. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Acked-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: Add a static gpio/pinctrl pin range mappingPeter Rosin2018-01-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Without such a range, gpiolib fails with -EPROBE_DEFER, pending the addition of the range. So, without a range, gpiolib will keep deferring indefinitely. Cc: stable@vger.kernel.org Fixes: 9e80f9064e73 ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver") Fixes: e10f72bf4b3e ("gpio: gpiolib: Generalise state persistence beyond sleep") Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: Register pinctrl before adding the gpiochipPeter Rosin2018-01-181-14/+21
| | | | | | | | | | | | | | | | | | | | Various gpiolib activity depend on the pinctrl to be up and kicking. Therefore, register the pinctrl before adding a gpiochip. Cc: stable@vger.kernel.org Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sx150x: Unregister the pinctrl on releasePeter Rosin2018-01-181-1/+1
| | | | | | | | | | | | | | | | | | | | There is no matching call to pinctrl_unregister, so switch to the managed devm_pinctrl_register to clean up properly when done. Cc: stable@vger.kernel.org Fixes: 9e80f9064e73 ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver") Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe()Wei Yongjun2018-01-181-3/+1
| | | | | | | | | | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show()Markus Elfring2018-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pinmux: Use seq_putc() in pinmux_pins_show()Markus Elfring2018-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show()Markus Elfring2018-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value callSean Wang2018-01-111-4/+4
| | | | | | | | | | | | | | | | | | Make consistent error handling of all mtk_hw_get_value occurrences using propagating error code from the internal instead of creating a new one. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: mt7622: fix potential uninitialized value being returnedSean Wang2018-01-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit d6ed93551320 ("pinctrl: mediatek: add pinctrl driver for MT7622 SoC") leads to the following static checker warning: drivers/pinctrl/mediatek/pinctrl-mt7622.c:1419 mtk_gpio_get() error: uninitialized symbol 'value'. 1412 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) 1413 { 1414 struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent); 1415 int value; 1416 1417 mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value); ^^^^^^^^^^^^^^^^ 1418 1419 return !!value; 1420 } The appropriate error handling must be added to avoid the potential error caused by uninitialized value being returned. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: uniphier: refactor drive strength get/set functionsMasahiro Yamada2018-01-111-85/+91
| | | | | | | | | | | | | | | | | | There is code duplication between uniphier_conf_pin_drive_get() and uniphier_conf_pin_drive_set(). Factor out the common code into uniphier_conf_get_drvctrl_data(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx7ulp: constify struct imx_cfg_params_decodeStefan Agner2018-01-113-3/+3
| | | | | | | | | | | | | | | | The decode parameters are constant mark them const. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx: constify struct imx_pinctrl_soc_infoStefan Agner2018-01-1111-11/+11
| | | | | | | | | | | | | | | | | | Now that imx_pinctrl_probe accepts const struct imx_pinctrl_soc_info we can constify all declarations of struct imx_pinctrl_soc_info. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx7d: simplify imx7d_pinctrl_probeStefan Agner2018-01-111-7/+3
| | | | | | | | | | | | | | | | | | | | | | Using of_device_get_match_data in imx7d_pinctrl_probe simplifies the function. Also get rid of the void pointer cast since imx_pinctrl_probe now accepts const struct imx_pinctrl_soc_info. Cc: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx: use struct imx_pinctrl_soc_info as a constStefan Agner2018-01-114-52/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs the struct imx_pinctrl_soc_info is passed through of_device_id.data which is const. Most variables are already const or otherwise not written. However, some fields are modified at runtime. Move those fields to the dynamically allocated struct imx_pinctrl. Fixes: b3060044e495 ("pinctrl: freescale: imx7d: make of_device_ids const") Cc: Shawn Guo <shawnguo@kernel.org> Cc: Arvind Yadav <arvind.yadav.cs@gmail.com> Cc: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly.hao_zhang2018-01-101-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin function can not be match correctly when SUNXI_PIN describe with mutiple variant and same function. such as: on pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */ PINCTRL_SUN4I_A10 | PINCTRL_SUN7I_A20), SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */ PINCTRL_SUN8I_R40)), it would always match to the first variant function (PINCTRL_SUN4I_A10, PINCTRL_SUN7I_A20) so we should add variant compare on it. Signed-off-by: hao_zhang <hao5781286@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add msm8998 pinctrl driverKhan, Imran2018-01-093-0/+1599
| | | | | | | | | | | | | | | | | | | | | | Add initial pinctrl driver to support pin configuration with pinctrl framework for msm8998. Signed-off-by: Imran Khan <kimran@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> [bjorn: Consolidated function groups] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: Combine two function calls into one in mcp23s08_dbg_show()Markus Elfring2018-01-091-6/+5
| | | | | | | | | | | | | | | | | | * Print a line break together with other data in a single function call. * Adjust indentation. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULLBai Ping2018-01-091-4/+48
| | | | | | | | | | | | | | | | | | | | | | On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers are available in a separate IOMUXC_SNVS module. Add support for the IOMUXC_SNVS module to the i.MX 6UL pinctrl driver. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Add Microsemi Ocelot SoC driverAlexandre Belloni2018-01-093-0/+523
| | | | | | | | | | | | | | | | | | | | The Microsemi Ocelot SoC has a few pins that can be used as GPIOs or take multiple other functions. Add a driver for the pinmuxing and the GPIOs. There is currently no support for interrupts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: remove redundant mux_setting clear in pinmux_disable_setting()Masahiro Yamada2018-01-091-2/+0
| | | | | | | | | | | | | | desc->mux_setting is set to NULL in pin_free() called just below. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'sh-pfc-for-v4.16-tag2' of ↵Linus Walleij2018-01-083-2/+371
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.16 (take two) - Add PWM pin groups on various R-Car Gen2 and RZ/G1 SoCs, - Add missing I2C5 pin groups on R-Car E2 and RZ/G1E, - Add SATA pin groups on R-Car H3 ES2.0.
| | * pinctrl: sh-pfc: r8a7795: Add SATA pins, groups, and functionsWolfram Sang2017-12-211-0/+24
| | | | | | | | | | | | | | | | | | | | | Tested with a Salvator-XS and H3 ES2.0. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7791: Add tpu groups and functionFabrizio Castro2017-12-191-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds tpu groups and function to r8a7743/r8a7791/r8a7793. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7794: Add i2c5 pin groups and functionBiju Das2017-12-191-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | Add i2c5 pin groups and function to r8a7745 PFC driver. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7794: Add tpu groups and functionFabrizio Castro2017-12-191-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds tpu groups and function to r8a7745/r8a7794. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7794: Add PWM[0123456] supportFabrizio Castro2017-12-191-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds PFC PWM[0123456] pin groups and functions, enabling PWM on the r8a7794 and r8a7745. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: armada-37xx: account for const type of of_device_id.dataJulia Lawall2018-01-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data field of an of_device_id structure has type const void *, so there is no need for a const-discarding cast when putting const values into such a structure. Done using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: axp209: account for const type of of_device_id.dataJulia Lawall2018-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The return value of of_device_get_match_data has type const void *. The desc field of the pctl structure also has a const type, so there is no need for the const-discarding cast between them. Done using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: at91-pio4: account for const type of of_device_id.dataJulia Lawall2018-01-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver creates a const structure that it stores in the data field of an of_device_id array. Adding const to the declaration of the location that receives the const value from the data field ensures that the compiler will continue to check that the value is not modified. Furthermore, the const-discarding cast on the extraction from the data field is no longer needed. Done using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 07:48:41 +0000