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path: root/drivers/ptp/ptp_clockmatrix.h
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* ptp: ptp_clockmatrix: Add .getmaxphase ptp_clock_info callbackRahul Rameshbabu2023-06-201-1/+1
| | | | | | | | | | | | Advertise the maximum offset the .adjphase callback is capable of supporting in nanoseconds for IDT ClockMatrix devices. Depend on ptp_clock_adjtime for handling out-of-range offsets. ptp_clock_adjtime returns -ERANGE instead of clamping out-of-range offsets. Cc: Richard Cochran <richardcochran@gmail.com> Cc: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: ptp_clockmatrix: return -EBUSY if phase pull-in is in progressMin Li2022-05-171-2/+0
| | | | | | | | | Also removes PEROUT_ENABLE_OUTPUT_MASK Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1652712427-14703-2-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* ptp: ptp_clockmatrix: Add PTP_CLK_REQ_EXTTS supportMin Li2022-05-171-0/+5
| | | | | | | | | | | | | | Use TOD_READ_SECONDARY for extts to keep TOD_READ_PRIMARY for gettime and settime exclusively. Before this change, TOD_READ_PRIMARY was used for both extts and gettime/settime, which would result in changing TOD read/write triggers between operations. Using TOD_READ_SECONDARY would make extts independent of gettime/settime operation Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1652712427-14703-1-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* ptp: clockmatrix: use rsmu driver to access i2c/spi busMin Li2021-09-271-97/+20
| | | | | | | | | | rsmu (Renesas Synchronization Management Unit ) driver is located in drivers/mfd and responsible for creating multiple devices including clockmatrix phc, which will then use the exposed regmap and mutex handle to access i2c/spi bus. Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF ↵Min Li2021-09-141-2/+45
| | | | | | | | | and WP Also correct how initialize_dco_operating_mode is called Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: ptp_clockmatrix: Add support for FW 5.2 (8A34005)Min Li2021-09-141-5/+12
| | | | | | | | So far we don't need to support new 5.2 functions but different register addresses Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: ptp_clockmatrix: Remove unused header declarations.Vincent Cheng2021-02-171-2/+0
| | | | | | | Removed unused header declarations. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.Vincent Cheng2021-02-171-0/+15
| | | | | | | | | | | | | | Part of the device initialization aligns the rising edge of the output clock to the internal 1 PPS clock. If the system APLL and DPLL is not locked, then the alignment will fail and there will be a fixed offset between the internal 1 PPS clock and the output clock. After loading the device firmware, poll the system APLL and DPLL for locked state prior to initialization, timing out after 2 seconds. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: clockmatrix: deprecate firmware older than 4.8.7Min Li2020-12-091-5/+6
| | | | | | | | | Add deprecated flag to indicate < v4.8.7. Fix idtcm_enable_tod() call correct settime(). Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-4-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* ptp: clockmatrix: Fix non-zero phase_adj is lost after snapMin Li2020-12-091-3/+2
| | | | | | | | | Fix non-zero phase_adj is lost after snap. Use ktime_sub to do ktime_t subtraction. Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-3-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* ptp: clockmatrix: remove 5 second delay before entering write phase modeMin Li2020-12-091-1/+0
| | | | | | | | Remove write phase mode 5 second setup delay, not needed. Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-2-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* ptp: clockmatrix: reset device and check BOOT_STATUSMin Li2020-12-091-2/+7
| | | | | | | | | | | | | | SM_RESET device only when loading full configuration and check for BOOT_STATUS. Also remove polling for write trigger done in _idtcm_settime(). Changes since v1: -Correct warnings from strict checkpatch Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1607442117-13661-1-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* ptp: ptp_clockmatrix: use i2c_master_send for i2c writeMin Li2020-08-191-0/+2
| | | | | | | | | | | | The old code for i2c write would break on some controllers, which fails at handling Repeated Start Condition. So we will just use i2c_master_send to handle write in one transanction. Changes since v1: - Remove indentation change Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: ptp_clockmatrix: update to support 4.8.7 firmwareMin Li2020-07-301-11/+50
| | | | | | | | | | | | With 4.8.7 firmware, adjtime can change delta instead of absolute time, which greately increases snap accuracy. PPS alignment doesn't have to be set for every single TOD change. Other minor changes includes: adding more debug logs, increasing snap accuracy for pre 4.8.7 firmware and supporting new tcs2bin format. Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: ptp_clockmatrix: Add adjphase() to support PHC write phase mode.Vincent Cheng2020-05-021-2/+6
| | | | | | | | Add idtcm_adjphase() to support PHC write phase mode. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ptp: Add a ptp clock driver for IDT ClockMatrix.Vincent Cheng2019-11-031-0/+104
The IDT ClockMatrix (TM) family includes integrated devices that provide eight PLL channels. Each PLL channel can be independently configured as a frequency synthesizer, jitter attenuator, digitally controlled oscillator (DCO), or a digital phase lock loop (DPLL). Typically these devices are used as timing references and clock sources for PTP applications. This patch adds support for the device. Co-developed-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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