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The sm8350_mxc's domain description incorrectly references
sm8150_mmcx_ao as a peer instead of sm8350_mxc_ao. Correct this typo.
Fixes: 639c85628757 ("soc: qcom: rpmhpd: Add SM8350 power domains")
Cc: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211020012639.1183806-1-dmitry.baryshkov@linaro.org
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Add SPM register information and initialization values for QCOM 8916
SoC.
Link: https://lore.kernel.org/linux-arm-msm/1429314549-6730-5-git-send-email-lina.iyer@linaro.org/
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
[stephan: rebase patch and fix conflicts]
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211004204955.21077-11-stephan@gerhold.net
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Add PM8150C and SMB2351 to the list of known PMIC models.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20211005024025.2037810-1-bjorn.andersson@linaro.org
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This patch adds feature negotiation and ssr ack feature between
local host and remote processor. Local host can negotiate on common
features supported with remote processor.
When ssr ack feature bit is set, the remote processor will tell local
host when it is reinitialized. All clients registered for falling edge
interrupts will be notified when the smp2p entries are cleared for ssr.
Signed-off-by: Chris Lew <clew@codeaurora.org>
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1633450403-21281-1-git-send-email-deesin@codeaurora.org
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Let's add a driver to read the stats from remote processor and
export to debugfs.
The driver creates "qcom_sleep_stats" directory in debugfs and
adds files for various low power mode available. Below is sample
output with command
cat /sys/kernel/debug/qcom_sleep_stats/ddr
count = 0
Last Entered At = 0
Last Exited At = 0
Accumulated Duration = 0
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
[mkshah: add subsystem sleep stats, create one file for each stat]
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1634107104-22197-3-git-send-email-mkshah@codeaurora.org
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Add IDs for PMK8001 and PMI8996. They also fall in the list of
'duplicated' IDs, where the same index was used for multiple chips.
Fixes: 7fda2b0bfbd9 ("soc: qcom: socinfo: import PMIC IDs from pmic-spmi")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211016190607.49866-1-dmitry.baryshkov@linaro.org
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The general expectation is that powering on a power-domain should make
the power domain deliver some power, and if a specific performance state
is needed further requests has to be made.
But in contrast with other power-domain implementations (e.g. rpmpd) the
RPMh does not have an interface to enable the power, so the driver has
to vote for a particular corner (performance level) in rpmh_power_on().
But the corner is never initialized, so a typical request to simply
enable the power domain would not actually turn on the hardware. Further
more, when no more clients vote for a performance state (i.e. the
aggregated vote is 0) the power domain would be turned off.
Fix both of these issues by always voting for a corner with non-zero
value, when the power domain is enabled.
The tracking of the lowest non-zero corner is performed to handle the
corner case if there's ever a domain with a non-zero lowest corner, in
which case both rpmh_power_on() and rpmh_rpmhpd_set_performance_state()
would be allowed to use this lowest corner.
Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20211005033732.2284447-1-bjorn.andersson@linaro.org
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Practically all modern Qualcomm platforms has a single reserved-memory
region for SMEM. So rather than having to describe SMEM in the form of a
node with a reference to a reserved-memory node, allow the SMEM device
to be instantiated directly from the reserved-memory node.
The current means of falling back to dereferencing the "memory-region"
is kept as a fallback, if it's determined that the SMEM node is a
reserved-memory node.
The "qcom,smem" compatible is added to the reserved_mem_matches list, to
allow the reserved-memory device to be probed.
In order to retain the readability of the code, the resolution of
resources is split from the actual ioremapping.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20210930182111.57353-4-bjorn.andersson@linaro.org
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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers
Samsung SoC drivers changes for v5.16
1. Convert Exynos ChipID and ASV driver to a module and make it a
default, instead of selected. The driver is not essential, so it
could be disabled, if needed.
2. Add support for Exynos850 and Exynos Auto v9 to Exynos ChipID and ASV
driver.
3. Get rid of HAVE_S3C_RTC because it was adding just another layer
instead of direct dependencies.
4. Minor cleanups.
* tag 'samsung-drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
soc: samsung: exynos-chipid: add exynosautov9 SoC support
rtc: s3c: remove HAVE_S3C_RTC in favor of direct dependencies
soc: samsung: exynos-chipid: Add Exynos850 support
dt-bindings: samsung: exynos-chipid: Document Exynos850 compatible
soc: samsung: exynos-chipid: Pass revision reg offsets
soc: samsung: pm_domains: drop unused is_off field
arm64: exynos: don't have ARCH_EXYNOS select EXYNOS_CHIPID
soc: samsung: exynos-chipid: do not enforce built-in
soc: samsung: exynos-chipid: convert to a module
soc: samsung: exynos-chipid: avoid soc_device_to_device()
soc: samsung: exynos-pmu: Fix compilation when nothing selects CONFIG_MFD_CORE
Link: https://lore.kernel.org/r/20211026094709.75692-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The product id of Exynos Auto v9 is "0xAAA8_0000". Add this id and its
name.
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20211021012017.158919-2-chanho61.park@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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Add chip-id support for Exynos850 SoC. Despite its "E3830" ID, the
actual SoC name is Exynos850 (Exynos3830 name is internal and outdated).
Format of Product_ID register in Exynos850 (offset 0x0):
[31:0] Product ID (identification)
Format of CHIPID_REV register in Exynos850 (offset 0x10):
[23:20] Main revision
[19:16] Sub revision
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20211014133508.1210-3-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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Old Exynos SoCs have both Product ID and Revision ID in one single
register, while new SoCs tend to have two separate registers for those
IDs. Implement handling of both cases by passing Revision ID register
offsets in driver data.
Previously existing macros for Exynos4210 (removed in this patch) were
incorrect:
#define EXYNOS_SUBREV_MASK (0xf << 4)
#define EXYNOS_MAINREV_MASK (0xf << 0)
Actual format of PRO_ID register in Exynos4210 (offset 0x0):
[31:12] Product ID
[9:8] Package information
[7:4] Main Revision Number
[3:0] Sub Revision Number
This patch doesn't change the behavior on existing platforms, so
'/sys/devices/soc0/revision' will show the same string as before.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Henrik Grimler <henrik@grimler.se>
Link: https://lore.kernel.org/r/20211014133508.1210-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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The 'is_off' member of internal state structure 'exynos_pm_domain' is
not used anymore.
Fixes: 2ed5f236716c ("ARM: EXYNOS: Detect power domain state on registration from DT")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211008075253.67961-1-krzysztof.kozlowski@canonical.com
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After converting the Exynos ChipID and ASV driver to a module, allow to
actually choose it to be a module, while being a default built-in. The
side effect is that driver could be now entirely disabled even for
kernel with ARCH_EXYNOS, but this is not a critical issue because driver
is not necessary for the proper platform boot.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sylwester Nawrocki <snawrocki@kernel.org>
Tested-by: Sylwester Nawrocki <snawrocki@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20210919093114.35987-4-krzysztof.kozlowski@canonical.com
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Exynos ChipID and ASV (Adaptive Supply Voltage) driver is not essential
to system boot and it can successfully be built and loaded as module.
This makes core kernel image smaller and reduces the memory footprint
when multi-platform kernel is booted on non-Exynos board. Usually it is
also distro-friendly.
Add multiple authors of the driver since its conversion from
mach-exynos, ordered alphabetically by first name.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sylwester Nawrocki <snawrocki@kernel.org>
Tested-by: Sylwester Nawrocki <snawrocki@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20210919093114.35987-3-krzysztof.kozlowski@canonical.com
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soc_device_to_device() seems to be discouraged [1] so remove it in favor
of printing info message with platform device. This will only change
the prefix in the info message from "soc soc0: " to "exynos-chipid
10000000.chipid:".
[1] https://lore.kernel.org/lkml/20191111052741.GB3176397@kroah.com/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sylwester Nawrocki <snawrocki@kernel.org>
Tested-by: Sylwester Nawrocki <snawrocki@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20210919093114.35987-2-krzysztof.kozlowski@canonical.com
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Commit 93618e344a5e ("soc: samsung: exynos-pmu: instantiate clkout
driver as MFD") adds a "devm_mfd_add_devices" call in the exynos-pmu
driver which depends on CONFIG_MFD_CORE. If no driver selects that
config, the build will fail if CONFIG_EXYNOS_PMU is enabled with the
following error:
drivers/soc/samsung/exynos-pmu.c:137: undefined reference to `devm_mfd_add_devices'
Fix this by making CONFIG_EXYNOS_PMU select CONFIG_MFD_CORE.
Fixes: 93618e344a5e ("soc: samsung: exynos-pmu: instantiate clkout driver as MFD")
Cc: <stable@vger.kernel.org>
Signed-off-by: David Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20210909222812.108614-1-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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Add driver support for the UART routing control. Users can perform
runtime configuration of the RX muxes among the UART controllers and
the UART IO pins.
The sysfs interface is also exported for the convenience of routing paths
check and update.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Tested-by: Lei YU <yulei.sh@bytedance.com>
Link: https://lore.kernel.org/r/20210927023053.6728-5-chiawei_wang@aspeedtech.com
Link: https://lore.kernel.org/r/20211022000616.481772-1-joel@jms.id.au'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers
NXP/FSL SoC driver updates for v5.16
DPIO Driver
- Code cleanup and fix compile warning
RCMP and Guts Driver
- Make use of the helper function devm_platform_ioremap_resource()
* tag 'soc-fsl-next-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: dpio: rename the enqueue descriptor variable
soc: fsl: dpio: use an explicit NULL instead of 0
soc: fsl: rcpm: Make use of the helper function devm_platform_ioremap_resource()
soc: fsl: guts: Make use of the helper function devm_platform_ioremap_resource()
Link: https://lore.kernel.org/r/20211022010027.11866-2-leoyang.li@nxp.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The struct qbman_eq_desc 'd' variable declaration is covering one of the
function parameters. This has no functional impact since this function
parameter was not used after the new declaration.
Even so, rename the variable so that we make the code more readable.
Fixes: 3b2abda7d28c ("soc: fsl: dpio: Replace QMAN array mode with ring mode enqueue")
Signed-off-by: Youri Querry <youri.querry_1@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
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Use an explicit NULL pointer when calling qbman_swp_enqueue_multiple()
instead of a plain integer. Without this fix, we get the following
compile time error.
drivers/soc/fsl/dpio/dpio-service.c:466:60: warning: Using plain integer as NULL pointer
Fixes: 9d98809711ae ("soc: fsl: dpio: Adding QMAN multiple enqueue interface")
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
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Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
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Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/drivers
Some new drivers changes for the Allwinner SoCs, converting to a helper
and improving logging.
* tag 'sunxi-drivers-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
bus: sun50i-de2: Adjust printing error message
soc: sunxi_sram: Make use of the helper function devm_platform_ioremap_resource()
Link: https://lore.kernel.org/r/ad0aa469-9e1b-4bb6-a116-92648ed774fa.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210908071716.772-1-caihuoqing@baidu.com
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.16:
- Select REGMAP_MMIO for i.MX GPCv2 driver to avoid build issue.
- A couple of i.MX GPCv2 driver changes from Marek Vasut to turn
domain->pgc into bitfield for i.MX8MM GPU domain support.
- A series from Lucas Stach adding support of i.MX8MM nested power
domains like VPUMIX and DISPMIX which contains the ADB and BLK_CTRL.
- An off-by-one fix on Lucas' i.MX8M blk-ctrl driver code.
* tag 'imx-drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: imx8m-blk-ctrl: off by one in imx8m_blk_ctrl_xlate()
soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
soc: imx: add i.MX8M blk-ctrl driver
soc: imx: gpcv2: support system suspend/resume
soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
soc: imx: gpcv2: add domain option to keep domain clocks enabled
soc: imx: gpcv2: add lockdep annotation
Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
soc: imx: gpcv2: allow to disable individual power domains
imx: soc: Select REGMAP_MMIO
soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
soc: imx: gpcv2: Turn domain->pgc into bitfield
Link: https://lore.kernel.org/r/20211016140138.1603-2-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The > comparison should be >= to prevent reading one element beyond the
end of the array. The onecell_data->domains[] array is allocated in
imx8m_blk_ctrl_probe() and it has "onecell_data->num_domains" elements.
Fixes: 5b340e7813d4 ("soc: imx: add i.MX8M blk-ctrl driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This adds the description for the i.MX8MM disp blk-ctrl.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of
SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX
power domains and interacts with the GPC power controller to provide the
peripherals in the power domain access to the NoC and ensures that those
peripherals are properly reset when their respective power domain is
brought back to life.
Software needs to do different things to make the bus handshake happen
after the GPC *MIX domain is powered up and before it is powered down.
As the requirements are quite different between the various blk-ctrls
there is a callback function provided to hook in the proper sequence.
The peripheral domains are quite uniform, they handle the soft clock
enables and resets in the blk-ctrl address space and sequencing with the
upstream GPC power domains.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Our usage of runtime PM to control the hierarchy of power domains is
slightly unusual and means that powering up a domain may fail in early
system resume, as runtime PM is still disallowed at this stage.
However the system suspend/resume path takes care of powering down/up
the power domains in the order defined by the device parent/child and
power-domain provider/consumer hierarachy. So we can just runtime
resume all our power-domain devices to allow the power-up to work
properly in the resume path. System suspend will still disable all
domains as intended.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Annotate the domains with bus clocks to keep those clocks enabled
as long as the domain is active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Some of the MIX domains are using clocks to drive the bus bridges. Those
must be enabled at all times, as long as the domain is powered up and
they don't have any other consumer than the power domain. Add an option
to keep the clocks attached to a domain enabled as long as the domain
is power up and only disable them after the domain is powered down.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Some of the GPCv2 power domains are nested inside each other without
visibility to lockdep at the genpd level, as they are in separate
driver instances and don't have a parent/child power-domain relationship.
Add a subclass annotation to the nested domains to let lockdep know that
it is okay to take the genpd lock in a nested fashion.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This reverts commit a77ebdd9f553. It turns out that the VPU domain has no
different requirements, even though the downstream ATF implementation seems
to suggest otherwise. Powering on the domain with the reset asserted works
fine. As the changed sequence has caused sporadic issues with the GPU
domains, just revert the change to go back to the working sequence.
Cc: <stable@vger.kernel.org> # 5.14
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Some board designs don't supply power to all of the power domains,
as they are not used anyways. In that case we must make sure to
not touch those power domains at all, as trying to power up a
domain that has no power supplied to it will obviously end in a
system crash. Allow to disable those domains via the standard DT
status property.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-By: Tim Harvey <tharvey@gateworks.com>
Tested-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The imx-gpcv2 driver needs Regmap MMIO. Select it, and fix:
drivers/soc/imx/gpcv2.c:420:34: error: array type has incomplete element type ‘struct regmap_range’
420 | static const struct regmap_range imx7_yes_ranges[] = {
| ^~~~~~~~~~~~~~~
drivers/soc/imx/gpcv2.c:421:17: error: implicit declaration of function ‘regmap_reg_range’; did you mean ‘remap_pfn_range’? [-Werror=implicit-function-declaration]
421 | regmap_reg_range(GPC_LPCR_A_CORE_BSC,
| ^~~~~~~~~~~~~~~~
| remap_pfn_range
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.
Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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There is currently the MX8MM GPU domain, which is in fact a composite domain
for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
time. This is currently not possible.
Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
register array. This way it is possible to configure all GPC_PGC_nCTRL
registers required in a particular domain.
This is a preparatory patch, no functional change.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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into arm/drivers
This pull request contains Broadcom ARM/ARM64 SoC drivers changes for
5.16, please pull the following:
- Cai updates the bcm-pmb and bcm63xx-power drivers to use the
devm_platform_ioremap_resource() helper
- Florian updates the Bus Interface Unit code to tune the 72116 and
72113 chips according to their existing counterparts. The GISB driver is
updated to be built as a non-removable module
* tag 'arm-soc/for-5.16/drivers' of https://github.com/Broadcom/stblinux:
bus: brcmstb_gisb: Allow building as module
soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72116
soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72113
soc: bcm63xx-power: Make use of the helper function devm_platform_ioremap_resource()
soc: bcm: bcm-pmb: Make use of the helper function devm_platform_ioremap_resource()
Link: https://lore.kernel.org/r/20211013174016.831348-3-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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72116 uses a quad core Brahma-B53 CPU complex which uses the same tuning
as done for previous chips, add that chip to the list.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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72113 uses a dual core Cortex-A72 CPU complex which requires tuning of
its bus interface unit the same way that the existing Cortex-A72 based
systems are tuned.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for v5.16
This drops the use of power-domains for exposing the load_state from the
QMP driver to clients, to avoid issues related to system suspend.
SMP2P becomes wakeup capable, to allow dying remoteprocs to wake up
Linux from suspend to perform recovery.
It adds RPM power-domain support for SM6350 and MSM8953 and base RPM
support for MSM8953 and QCM2290.
It adds support for MSM8996, SDM630 and SDM660 in the SPM driver, which
will enable the introduction of proper voltage scaling of the CPU
subsystem.
Support for releasing secondary CPUs on MSM8226 is introduced.
The Asynchronous Packet Router (APR) driver is extended to support the
new Generic Packet Router (GPR) variant, which is used to communicate
with the firmware in the new AudioReach audio driver.
Lastly it transitions a number of drivers to safer string functions, as
well as switching things to use devm_platform_ioremap_resource().
* tag 'qcom-drivers-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (40 commits)
soc: qcom: apr: Add GPR support
soc: dt-bindings: qcom: add gpr bindings
soc: qcom: apr: make code more reuseable
soc: dt-bindings: qcom: apr: deprecate qcom,apr-domain property
soc: dt-bindings: qcom: apr: convert to yaml
dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
dt-bindings: msm/dp: Remove aoss-qmp header
soc: qcom: aoss: Drop power domain support
dt-bindings: soc: qcom: aoss: Drop the load state power-domain
soc: qcom: smp2p: Add wakeup capability to SMP2P IRQ
dt-bindings: power: rpmpd: Add SM6350 to rpmpd binding
dt-bindings: soc: qcom: aoss: Add SM6350 compatible
soc: qcom: llcc: Disable MMUHWT retention
soc: qcom: smd-rpm: Add QCM2290 compatible
dt-bindings: soc: qcom: smd-rpm: Add QCM2290 compatible
firmware: qcom_scm: Add compatible for MSM8953 SoC
dt-bindings: firmware: qcom-scm: Document msm8953 bindings
soc: qcom: pdr: Prefer strscpy over strcpy
soc: qcom: rpmh-rsc: Make use of the helper function devm_platform_ioremap_resource_byname()
soc: qcom: gsbi: Make use of the helper function devm_platform_ioremap_resource()
...
Link: https://lore.kernel.org/r/20211012173442.1017010-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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drivers-for-5.16
v5.15-rc1 + 20210927135559.738-[23456]-srinivas.kandagatla@linaro.org
This immutable branch is based on v5.15-rc1 and contains the following
patches extending the existig APR driver to also implement GPR:
20210927135559.738-2-srinivas.kandagatla@linaro.org
20210927135559.738-3-srinivas.kandagatla@linaro.org
20210927135559.738-4-srinivas.kandagatla@linaro.org
20210927135559.738-5-srinivas.kandagatla@linaro.org
20210927135559.738-6-srinivas.kandagatla@linaro.org
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Strip out the load state power-domain support from the driver since the
low power mode signalling for the co-processors is now accessible through
the direct qmp message send interface.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-12-git-send-email-sibis@codeaurora.org
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Remote susbsystems notify fatal crash through smp2p interrupt.
When remoteproc crashes it can cause soc to come out of low power
state and may not allow again to enter in low power state until
crash is handled.
Mark smp2p interrupt wakeup capable so that interrupt handler is
executed and remoteproc crash can be handled in system resume path.
This patch marks interrupt wakeup capable but keeps wakeup disabled
by default. User space can enable it based on its requirement for
wakeup from suspend.
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632220467-27410-1-git-send-email-deesin@codeaurora.org
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drivers-for-5.16
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Not all upcoming usecases will have an interface to allow the aoss
driver to hook onto. Expose the send api and create a get function to
enable drivers to send their own messages to aoss.
Signed-off-by: Chris Lew <clew@codeaurora.org>
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1630420228-31075-2-git-send-email-deesin@codeaurora.org
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Disable MMUHWT retention for SC7280 as done for other platforms
to avoid more power burn.
Fixes: f6a07be63301 ("soc: qcom: llcc: Add configuration data for SC7280")
Signed-off-by: Naina Mehta <nainmeht@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210921055942.30600-1-saiprakash.ranjan@codeaurora.org
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