summaryrefslogtreecommitdiffstats
path: root/drivers/spi/Makefile
Commit message (Collapse)AuthorAgeFilesLines
*-. Merge remote-tracking branches 'spi/topic/spidev', 'spi/topic/st-ssc4' and ↵Mark Brown2017-07-031-0/+1
|\ \ | | | | | | | | | 'spi/topic/stm32' into spi-next
| | * spi: add driver for STM32 SPI controllerAmelie Delaunay2017-06-211-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | The STM32 Serial Peripheral Interface (SPI) can be used to communicate with external devices while using the specific synchronous protocol. It supports a half-duplex, full-duplex and simplex synchronous, serial communication with external devices with 4-bit to 16/32-bit per word. It has two 8x/16x 8-bit embedded Rx and TxFIFOs with DMA capability. It can operate in master or slave mode. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| |
| \
*-. \ Merge remote-tracking branches 'spi/topic/loopback', ↵Mark Brown2017-07-031-0/+1
|\ \ \ | | |/ | |/| | | | 'spi/topic/meson-spicc', 'spi/topic/mtk' and 'spi/topic/omap2-mcspi' into spi-next
| | * spi: Add Meson SPICC driverNeil Armstrong2017-05-241-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | The SPICC hardware block on the Amlogic SoCs is Communication oriented and can do Full-Duplex 8- to 32-bit width SPI transfers up to 30MHz. The current driver only supportd the PIO transfer mode since the DMA seems broken on available hardware. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: slave: Add SPI slave handler controlling system stateGeert Uytterhoeven2017-05-261-0/+1
| | | | | | | | | | | | | | | | | | Add an example SPI slave handler to allow remote control of system reboot, power off, halt, and suspend. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: slave: Add SPI slave handler reporting uptime at previous messageGeert Uytterhoeven2017-05-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add an example SPI slave handler responding with the uptime at the time of reception of the last SPI message. This can be used by an external microcontroller as a dead man's switch. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: core: Add support for registering SPI slave controllersGeert Uytterhoeven2017-05-261-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | Add support for registering SPI slave controllers using the existing SPI master framework: - SPI slave controllers must use spi_alloc_slave() instead of spi_alloc_master(), and should provide an additional callback "slave_abort" to abort an ongoing SPI transfer request, - SPI slave controllers are added to a new "spi_slave" device class, - SPI slave handlers can be bound to the SPI slave device represented by an SPI slave controller using a DT child node named "slave", - Alternatively, (un)binding an SPI slave handler to the SPI slave device represented by an SPI slave controller can be done by (un)registering the slave device through a sysfs virtual file named "slave". From the point of view of an SPI slave protocol handler, an SPI slave controller looks almost like an ordinary SPI master controller. The only exception is that a transfer request will block on the remote SPI master, and may be cancelled using spi_slave_abort(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: lantiq-ssc: add support for Lantiq SSC SPI controllerHauke Mehrtens2017-02-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | This driver supports the Lantiq SSC SPI controller in master mode. This controller is found on Intel (former Lantiq) SoCs like the Danube, Falcon, xRX200, xRX300. The hardware uses two hardware FIFOs one for received and one for transferred bytes. When the driver writes data into the transmit FIFO the complete word is taken from the FIFO into a shift register. The data from this shift register is then written to the wire. This driver uses the interrupts signaling the status of the FIFOs and not the shift register. It is also possible to use the interrupts for the shift register, but they will send a signal after every word. When using the interrupts for the shift register we get a signal when the last word is written into the shift register and not when it is written to the wire. After all FIFOs are empty the driver busy waits till the hardware is not busy any more and returns the transfer status. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'spi/topic/fsl-lpspi', 'spi/topic/imx', ↵Mark Brown2016-12-121-0/+1
|\ \ | | | | | | | | | 'spi/topic/jcore' and 'spi/topic/omap' into spi-next
| * | spi: imx: add lpspi bus driverGao Pan2016-11-221-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch adds lpspi driver to support new i.MX products which use lpspi instead of ecspi. The lpspi can continue operating in stop mode when an appropriate clock is available. It is also designed for low CPU overhead with DMA offloading of FIFO register accesses. Signed-off-by: Gao Pan <pandy.gao@nxp.com> Reviewed-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* / spi: Add support for Armada 3700 SPI ControllerRomain Perier2016-12-081-0/+1
|/ | | | | | | | | | | | | | | | | Marvell Armada 3700 SoC comprises an SPI Controller. This Controller supports up to 4 SPI slave devices, with dedicated chip selects,supports SPI mode 0/1/2 and 3, CPIO or Fifo mode with DMA transfers and different SPI transfer mode (Single, Dual or Quad). This commit adds basic driver support for FIFO mode. In this mode, dedicated registers are used to store the instruction, the address, the read mode and the data. Write and Read FIFO are used to store the outcoming or incoming data. The data FIFOs are accessible via DMA or by the CPU. Only the CPU is supported for now. Signed-off-by: Romain Perier <romain.perier@free-electrons.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'spi/topic/octeon', 'spi/topic/pic32-sqi', ↵Mark Brown2016-09-301-0/+2
|\ \ | | | | | | | | | 'spi/topic/pxa2xx' and 'spi/topic/qup' into spi-next
| * | spi: octeon: Add ThunderX driverJan Glauber2016-08-191-0/+2
| |/ | | | | | | | | | | | | | | | | | | Add ThunderX SPI driver using the shared part from the Octeon driver. The main difference of the ThunderX driver is that it is a PCI device so probing is different. The system clock settings can be specified in device tree. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| |
| \
*-. \ Merge remote-tracking branches 'spi/topic/fsl-espi', 'spi/topic/imx', ↵Mark Brown2016-09-301-0/+1
|\ \ \ | | |/ | |/| | | | 'spi/topic/jcore', 'spi/topic/loopback' and 'spi/topic/meson' into spi-next
| | * spi: add driver for J-Core SPI controllerRich Felker2016-08-081-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The J-Core "spi2" device is a PIO-based SPI master controller. It differs from "bitbang" devices in that that it's clocked in hardware rather than via soft clock modulation over gpio, and performs byte-at-a-time transfers between the cpu and SPI controller. This driver will be extended to support future versions of the J-Core SPI controller with DMA transfers when they become available. Signed-off-by: Rich Felker <dalias@libc.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: iproc-qspi: Add Broadcom iProc SoCs supportKamal Dasu2016-09-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | This spi driver uses the common spi-bcm-qspi driver and implements iProc SoCs specific interrupt controller. The common driver now calls the SoC handlers when present. Adding support for both muxed l1 and unmuxed interrupt sources. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: brcmstb-qspi: Broadcom settop platform driverKamal Dasu2016-09-141-1/+1
| | | | | | | | | | | | | | | | | | Adding the settop SoC platfrom driver, this driver is compatible with the settop MSPI+BSPI and MSPI only blocks implemented on the SoCs. Driver calls the spi-bcm-qspi probe(), remove() and pm_ops. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: bcm-qspi: Add Broadcom MSPI driverKamal Dasu2016-09-141-0/+1
|/ | | | | | | | | | | Master SPI driver for Broadcom settop, iProc SoCs. The driver is used for devices that use SPI protocol on BRCMSTB, NSP, NS2 SoCs. SoC platform driver call exported porbe(), remove() and suspend/resume pm_ops implemented in this common driver. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: octeon: Split driver into Octeon specific and common partsJan Glauber2016-07-241-0/+1
| | | | | | | | Separate driver probing from SPI transfer functions. Signed-off-by: Jan Glauber <jglauber@cavium.com> Tested-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pic32-sqi: add SPI driver for PIC32 SQI controller.Purna Chandra Mandal2016-04-181-0/+1
| | | | | | | | | | | | This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA transfer mode and supports half-duplex communication for single, dual and quad SPI transactions. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-pic32: Add PIC32 SPI master driverPurna Chandra Mandal2016-04-041-0/+1
| | | | | | | | | | | The PIC32 SPI driver is capable of performing SPI transfers using PIO or external DMA engine. GPIO controlled /CS support is made default in the driver for correct operation of the controller. This can be enabled by adding "cs-gpios" property of the SPI node in board dts file. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
*---. Merge remote-tracking branches 'spi/topic/lp8841', 'spi/topic/msg', ↵Mark Brown2016-03-111-2/+2
|\ \ \ | | | | | | | | | | | | 'spi/topic/pl022' and 'spi/topic/pxa2xx' into spi-next
| | | * Merge branch 'topic/acpi' of ↵Mark Brown2016-02-091-0/+1
| | | |\ | | | |/ | | |/| | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-pxa2xx
| | | * spi: pxa2xx: Remove CONFIG_SPI_PXA2XX_DMAJarkko Nikula2016-01-151-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After removal of legacy PXA DMA code by the commit 6356437e65c2 ("spi: spi-pxa2xx: remove legacy PXA DMA bits") the CONFIG_SPI_PXA2XX_DMA follows the CONFIG_SPI_PXA2XX and cannot be disabled alone. Therefore remove this config symbol and dead definitions from the spi-pxa2xx.h. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: master driver to enable RTC on ICPDAS LP-8841Sergei Ianovich2016-02-241-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICP DAS LP-8841 contains a DS-1302 RTC. This driver provides an SPI master which makes the RTC usable. The driver is not supposed to work with anything else. The driver uses the standard MicroWire half-duplex transfer timing. Master output is set on low clock and sensed by the RTC on the rising edge. Master input is set by the RTC on the trailing edge and is sensed by the master on low clock. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* / / spi: Add Analog Devices AXI SPI Engine controller supportLars-Peter Clausen2016-02-051-0/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the AXI SPI Engine controller which is a FPGA soft-peripheral which is used in some of Analog Devices' reference designs. The AXI SPI Engine controller is part of the SPI Engine framework[1] and allows memory mapped access to the SPI Engine control bus. This allows it to be used as a general purpose software driven SPI controller. The SPI Engine in addition offers some optional advanced acceleration and offloading capabilities, which are not part of this patch though and will be introduced separately. At the core of the SPI Engine framework is a small sort of co-processor that accepts a command stream and turns the commands into low-level SPI transactions. Communication is done through three memory mapped FIFOs in the register map of the AXI SPI Engine peripheral. One FIFO for the command stream and one each for transmit and receive data. The driver translates a spi_message in a command stream and writes it to the peripheral which executes it asynchronously. This allows it to perform very precise timings which are required for some SPI slave devices to achieve maximum performance (e.g. analog-to-digital and digital-to-analog converters). The execution flow is synchronized to the host system by a special synchronize instruction which generates a interrupt. [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
* / spi: add spi-loopback-test to build frameworkMartin Sperl2015-12-121-0/+1
|/ | | | | | | adding the spi-loopback-test module to Kconfig and Makefile Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835aux: add bcm2835 auxiliary spi device driverMartin Sperl2015-10-071-0/+1
| | | | | | | | | | | | | | | | | | The bcm2835 has 2 auxiliary spi bus masters spi1 and spi2. This implements the driver to enable these devices. The driver does not implement native chip-selects but uses the aribtrary GPIO-chip-selects provided by the spi-chipselect. Note that this driver relies on the fact that the clock is implemented by the clk-bcm2835-aux driver, which enables/disables the HW block when requesting/releasing the clock. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'spi/topic/ti-qspi', 'spi/topic/xcomm' and ↵Mark Brown2015-08-311-0/+1
|\ \ | | | | | | | | | 'spi/topic/xlp' into spi-next
| | * spi/xlp: SPI controller driver for Netlogic XLP SoCsKamlakant Patel2015-08-281-0/+1
| |/ | | | | | | | | | | | | | | Add SPI Master controller driver for the SPI interface on XLP8XX, XLP3XX, XLP2XX, XLP9XX and XLP5XX family of Netlogic XLP MIPS64 processors. Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* / spi: mediatek: Add spi bus for Mediatek MT8173Leilk Liu2015-08-071-0/+1
|/ | | | | | | This patch adds basic spi bus for MT8173. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'spi/topic/sirf', 'spi/topic/spidev' and ↵Mark Brown2015-06-181-0/+1
|\ \ | | | | | | | | | 'spi/topic/zynq' into spi-next
| | * spi: Add support for Zynq Ultrascale+ MPSoC GQSPI controllerRanjit Waghmode2015-06-121-0/+1
| |/ | | | | | | | | | | | | | | This patch adds support for GQSPI controller driver used by Zynq Ultrascale+ MPSoC Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| |
| \
*-. \ Merge remote-tracking branches 'spi/topic/pxa', 'spi/topic/rb4xx', ↵Mark Brown2015-06-181-1/+1
|\ \ \ | |_|/ |/| | | | | 'spi/topic/rspi', 'spi/topic/s3c64xx' and 'spi/topic/sh-msiof' into spi-next
| | * spi: Add SPI driver for Mikrotik RB4xx series boardsBert Vermeulen2015-04-181-0/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | This driver mediates access between the connected CPLD and other devices on the bus. The m25p80-compatible boot flash and (some models) MMC use regular SPI, bitbanged as required by the SoC. However the SPI-connected CPLD has a two-wire mode, in which two bits are transferred per SPI clock cycle. The second bit is transmitted with the SoC's CS2 pin. Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: spi-pxa2xx: remove legacy PXA DMA bitsDaniel Mack2015-06-091-1/+0
|/ | | | | | | | | | | | | | | | Generic DMA support was already implemented by commit cd7bed003404 ("spi/pxa2xx: break out the private DMA API usage into a separate file") which moved all the legacy PXA DMA implementation code into its own file. With generic DMA available for PXA, we can now just trash this file. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Mark Brown <broonie@linaro.org> [respin after pxa dmaengine support upstream] Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'spi/topic/sirf', 'spi/topic/spidev', ↵Mark Brown2015-02-081-0/+1
|\ \ | | | | | | | | | 'spi/topic/st-ssc' and 'spi/topic/ti-qspi' into spi-next
| | * spi: Add new driver for STMicroelectronics' SPI ControllerLee Jones2014-12-221-0/+1
| |/ | | | | | | | | | | | | This patch adds support for the SPI portion of ST's SSC device. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* / spi: add support for DLN-2 USB-SPI adapterLaurentiu Palcu2014-12-221-0/+1
|/ | | | | | | | | | | | | This adds support for Diolan DLN2 USB-SPI adapter. Information about the USB protocol interface can be found in the Programmer's Reference Manual [1], see section 5.4.6 for the SPI master module commands and responses. [1] https://www.diolan.com/downloads/dln-api-manual.pdf Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'spi/topic/fsl-dspi', 'spi/topic/fsl-espi', ↵Mark Brown2014-12-081-0/+2
|\ \ | | | | | | | | | 'spi/topic/gpio', 'spi/topic/img-spfi' and 'spi/topic/meson' into spi-next
| | * spi: meson: Add support for Amlogic Meson SPIFCBeniamino Galvani2014-11-241-0/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a driver for the Amlogic Meson SPIFC (SPI flash controller), which is one of the two SPI controllers available on the SoC. It doesn't support DMA and has a 64-byte unified transmit/receive buffer. The device is optimized for interfacing with SPI NOR memories and allows the execution of standard operations such as read, page program, sector erase, etc. in a simplified way, toggling a bit in a dedicated register. The driver doesn't use those predefined commands and relies only on custom transfers. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: Add driver for IMG SPFI controllerAndrew Bresticker2014-11-171-0/+1
|/ | | | | | | | | Add support for the Synchronous Peripheral Flash Interface (SPFI) master controller found on IMG SoCs. The SPFI controller supports 5 chip-select lines and single/dual/quad mode SPI transfers. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm53xx: driver for SPI controller on Broadcom bcma SoCRafał Miłecki2014-08-191-0/+1
| | | | | | | | | | | | | | | Broadcom 53xx ARM SoCs use bcma bus that contains various cores (AKA devices). If board has a serial flash, it's connected over SPI and the bcma bus includes a SPI controller. Example log from such a board: bus0: Found chip with id 53010, rev 0x00 and package 0x02 (...) bus0: Core 18 found: SPI flash controller (manuf 0x4BF, id 0x50A, rev 0x01, class 0x0) This patch adds a bcma driver for SPI core, it registers SPI master controller and "bcm53xxspiflash" SPI device. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* spi/rockchip: add driver for Rockchip RK3xxx SoCs integrated SPIaddy ke2014-07-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to facilitate understanding, rockchip SPI controller IP design looks similar in its registers to designware. But IC implementation is different from designware, So we need a dedicated driver for Rockchip RK3XXX SoCs integrated SPI. The main differences: - dma request line: rockchip SPI controller have two DMA request line for tx and rx. - Register offset: RK3288 dw SPI_CTRLR0 0x0000 0x0000 SPI_CTRLR1 0x0004 0x0004 SPI_SSIENR 0x0008 0x0008 SPI_MWCR NONE 0x000c SPI_SER 0x000c 0x0010 SPI_BAUDR 0x0010 0x0014 SPI_TXFTLR 0x0014 0x0018 SPI_RXFTLR 0x0018 0x001c SPI_TXFLR 0x001c 0x0020 SPI_RXFLR 0x0020 0x0024 SPI_SR 0x0024 0x0028 SPI_IPR 0x0028 NONE SPI_IMR 0x002c 0x002c SPI_ISR 0x0030 0x0030 SPI_RISR 0x0034 0x0034 SPI_TXOICR NONE 0x0038 SPI_RXOICR NONE 0x003c SPI_RXUICR NONE 0x0040 SPI_MSTICR NONE 0x0044 SPI_ICR 0x0038 0x0048 SPI_DMACR 0x003c 0x004c SPI_DMATDLR 0x0040 0x0050 SPI_DMARDLR 0x0044 0x0054 SPI_TXDR 0x0400 NONE SPI_RXDR 0x0800 NONE SPI_IDR NONE 0x0058 SPI_VERSION NONE 0x005c SPI_DR NONE 0x0060 - register configuration: such as SPI_CTRLRO in rockchip SPI controller: cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) | (CR0_SSD_ONE << CR0_SSD_OFFSET); cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); cr0 |= (rs->tmode << CR0_XFM_OFFSET); cr0 |= (rs->type << CR0_FRF_OFFSET); For more information, see RK3288 chip manual. - Wait for idle: Must ensure that the FIFO data has been sent out before the next transfer. Signed-off-by: addy ke <addy.ke@rock-chips.com> Signed-off-by: Mark Brown <broonie@linaro.org>
*-. Merge remote-tracking branches 'spi/topic/adi', 'spi/topic/atmel' and ↵Mark Brown2014-06-021-1/+2
|\ \ | | | | | | | | | 'spi/topic/cadence' into spi-next
| | * spi: Add driver for Cadence SPI controllerHarini Katakam2014-04-141-0/+1
| |/ |/| | | | | | | | | | | Add driver for Cadence SPI controller. This is used in Xilinx Zynq. Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
| * spi: convert spi-bfin-v3.c to a multiplatform driverScott Jiang2014-04-141-1/+1
|/ | | | | | | | Spi v3 controller is not only used on Blackfin. So rename it and use ioread/iowrite api to make it work on other platform. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
*-. Merge remote-tracking branches 'spi/topic/xilinx' and 'spi/topic/xtfpga' ↵Mark Brown2014-03-301-0/+1
|\ \ | | | | | | | | | into spi-next
| | * spi: add xtfpga SPI controller driverMax Filippov2014-03-131-0/+1
| |/ | | | | | | | | | | | | | | | | This simple SPI master controller is built into xtfpga bitstreams. It always transfers 16 bit words in SPI mode 0, automatically asserting CS on transfer start and deasserting on end. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
| |
| \
| \
| \
*---. \ Merge remote-tracking branches 'spi/topic/sunxi', 'spi/topic/tegra114', ↵Mark Brown2014-03-301-1/+2
|\ \ \ \ | | | |/ | | |/| | | | | 'spi/topic/ti-qspi', 'spi/topic/ti-ssp', 'spi/topic/topcliff-pch', 'spi/topic/txx9', 'spi/topic/xcomm' and 'spi/topic/xfer' into spi-next
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 02:02:14 +0000