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* spi: realtek-rtl: Add support for Realtek RTL838x/RTL839x SPI controllersBert Vermeulen2021-02-041-0/+1
| | | | | | | | | | | | | | | | | This driver likely also supports earlier (RTL8196) and later (RTL93xx) SoCs. The SPI hardware in these SoCs is specifically intended for connecting NOR bootflash chips, and only used for that in dozens of examined devices. However boiled down to basics, it's really just a half-duplex SPI controller. The hardware appears to have a vestigial second chip-select control, but it hasn't been seen in the wild and is thus not supported. Signed-off-by: Bert Vermeulen <bert@biot.com> Link: https://lore.kernel.org/r/20210120135928.246054-3-bert@biot.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: remove sirf prima/atlas driverArnd Bergmann2021-01-211-1/+0
| | | | | | | | | | | The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120161658.3820610-1-arnd@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge series "Remove ARM platform efm32" from Uwe Kleine-König ↵Mark Brown2021-01-151-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | <u.kleine-koenig@pengutronix.de> Uwe Kleine-König <uwe.kleine-koenig@pengutronix.de>: From: Uwe Kleine-König <uwe.kleine-koenig@pengutronix.de> Hello, there are no known active users of the efm32 platform. Given that the only machine that is supported has only 4 MiB of RAM its use is also quite limited. Back then it served as the platform to develop ARMv7-M support in Linux which was quite fun and still is a blissful memory. Still given that the code serves no purpose and this probably won't change anytime soon, remove all platform support. I'm unsure what to do with the device tree bindings. Should we delete them, too? Best regards Uwe Uwe Kleine-König (7): ARM: drop efm32 platform clk: Drop unused efm32gg driver clocksource: Drop unused efm32 timer code spi: Drop unused efm32 bus driver i2c: Drop unused efm32 bus driver tty: Drop unused efm32 serial driver MAINTAINERS: Remove deleted platform efm32 MAINTAINERS | 7 - arch/arm/Kconfig | 10 +- arch/arm/Kconfig.debug | 17 - arch/arm/Makefile | 1 - arch/arm/boot/dts/Makefile | 2 - arch/arm/boot/dts/efm32gg-dk3750.dts | 88 --- arch/arm/boot/dts/efm32gg.dtsi | 177 ----- arch/arm/configs/efm32_defconfig | 98 --- arch/arm/include/debug/efm32.S | 45 -- arch/arm/mach-efm32/Makefile | 2 - arch/arm/mach-efm32/Makefile.boot | 4 - arch/arm/mach-efm32/dtmachine.c | 16 - arch/arm/mm/Kconfig | 1 - drivers/clk/Makefile | 1 - drivers/clk/clk-efm32gg.c | 84 --- drivers/clocksource/Kconfig | 9 - drivers/clocksource/Makefile | 1 - drivers/clocksource/timer-efm32.c | 278 -------- drivers/i2c/busses/Kconfig | 7 - drivers/i2c/busses/Makefile | 1 - drivers/i2c/busses/i2c-efm32.c | 469 ------------- drivers/spi/Kconfig | 7 - drivers/spi/Makefile | 1 - drivers/spi/spi-efm32.c | 462 ------------ drivers/tty/serial/Kconfig | 13 - drivers/tty/serial/Makefile | 1 - drivers/tty/serial/efm32-uart.c | 852 ----------------------- include/linux/platform_data/efm32-spi.h | 15 - include/linux/platform_data/efm32-uart.h | 19 - include/uapi/linux/serial_core.h | 3 - 30 files changed, 1 insertion(+), 2690 deletions(-) delete mode 100644 arch/arm/boot/dts/efm32gg-dk3750.dts delete mode 100644 arch/arm/boot/dts/efm32gg.dtsi delete mode 100644 arch/arm/configs/efm32_defconfig delete mode 100644 arch/arm/include/debug/efm32.S delete mode 100644 arch/arm/mach-efm32/Makefile delete mode 100644 arch/arm/mach-efm32/Makefile.boot delete mode 100644 arch/arm/mach-efm32/dtmachine.c delete mode 100644 drivers/clk/clk-efm32gg.c delete mode 100644 drivers/clocksource/timer-efm32.c delete mode 100644 drivers/i2c/busses/i2c-efm32.c delete mode 100644 drivers/spi/spi-efm32.c delete mode 100644 drivers/tty/serial/efm32-uart.c delete mode 100644 include/linux/platform_data/efm32-spi.h delete mode 100644 include/linux/platform_data/efm32-uart.h base-commit: 5c8fe583cce542aa0b84adc939ce85293de36e5e -- 2.29.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
| * spi: Drop unused efm32 bus driverUwe Kleine-König2021-01-151-1/+0
| | | | | | | | | | | | | | | | | | Support for this machine was just removed, so drop the now unused spi bus driver, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20210114151630.128830-5-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra210-quad: Add support for Tegra210 QSPI controllerSowjanya Komatineni2021-01-061-0/+1
| | | | | | | | | | | | | | | | | | | | Tegra SoC has a Quad SPI controller starting from Tegra210. This patch adds support for Tegra210 QSPI controller. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-5-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: txx9: Remove driverThomas Bogendoerfer2021-01-051-1/+0
|/ | | | | | | | | CPU support for TX49xx is getting removed, so remove support SPI driver for it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Link: https://lore.kernel.org/r/20210105140305.141401-5-tsbogend@alpha.franken.de Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2020-10-241-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC platform updates from Olof Johansson: "SoC changes, a substantial part of this is cleanup of some of the older platforms that used to have a bunch of board files. In particular: - Remove non-DT i.MX platforms that haven't seen activity in years, it's time to remove them. - A bunch of cleanup and removal of platform data for TI/OMAP platforms, moving over to genpd for power/reset control (yay!) - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them closer to multiplatform support (not quite there yet, but getting close). There are a few other changes too, smaller fixlets, etc. For new platform support, the primary ones are: - New SoC: Hisilicon SD5203, ARM926EJ-S platform. - Cpufreq support for i.MX7ULP" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits) ARM: mstar: Select MStar intc ARM: stm32: Replace HTTP links with HTTPS ones ARM: debug: add UART early console support for SD5203 ARM: hisi: add support for SD5203 SoC ARM: omap3: enable off mode automatically clk: imx: imx35: Remove mx35_clocks_init() clk: imx: imx31: Remove mx31_clocks_init() clk: imx: imx27: Remove mx27_clocks_init() ARM: imx: Remove unused definitions ARM: imx35: Retrieve the IIM base address from devicetree ARM: imx3: Retrieve the AVIC base address from devicetree ARM: imx3: Retrieve the CCM base address from devicetree ARM: imx31: Retrieve the IIM base address from devicetree ARM: imx27: Retrieve the CCM base address from devicetree ARM: imx27: Retrieve the SYSCTRL base address from devicetree ARM: s3c64xx: bring back notes from removed debug-macro.S ARM: s3c24xx: fix Wunused-variable warning on !MMU ARM: samsung: fix PM debug build with DEBUG_LL but !MMU MAINTAINERS: mark linux-samsung-soc list non-moderated ARM: imx: Remove remnant board file support pieces ...
| * ARM: s3c24xx: move spi fiq handler into platformArnd Bergmann2020-08-191-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fiq handler needs access to some register definitions that should not be used directly by device drivers. Since this is closely related to the irqchip driver anyway, move it into the same place. Signed-off-by: Arnd Bergmann <arnd@arndb.de> [krzk: Add a header guard in include/linux/spi/s3c24xx-fiq.h, fix SPDX comment style, update maintainer's entry] Co-developed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200806182059.2431-23-krzk%40kernel.org Acked-by: Mark Brown <broonie@kernel.org>
* | spi: dw: Add Baikal-T1 SPI Controller glue driverSerge Semin2020-10-081-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | Baikal-T1 is equipped with three DW APB SSI-based MMIO SPI controllers. Two of them are pretty much normal: with IRQ, DMA, FIFOs of 64 words depth, 4x CSs, but the third one as being a part of the Baikal-T1 System Boot Controller has got a very limited resources: no IRQ, no DMA, only a single native chip-select and Tx/Rx FIFO with just 8 words depth available. In order to provide a transparent initial boot code execution the Boot SPI controller is also utilized by an vendor-specific IP-block, which exposes an SPI flash direct mapping interface. Since both direct mapping and SPI controller normal utilization are mutual exclusive only one of these interfaces can be used to access an external SPI slave device. That's why a dedicated mux is embedded into the System Boot Controller. All of that is taken into account in the Baikal-T1-specific DW APB SSI glue driver implemented by means of the DW SPI core module. Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20201007235511.4935-22-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge series "mtd: spi-nor: Move cadence-qaudspi to spi-mem framework" from ↵Mark Brown2020-06-191-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vignesh Raghavendra <vigneshr@ti.com>: This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX <vadivel.muruganx.ramuthevar@linux.intel.com> that intended to move cadence-quadspi driver to spi-mem framework Those patches were trying to accomplish too many things in a single set of patches and need to split into smaller patches. This is reduced version of above series. Changes that are intended to make migration easy are split into separate patches. Patches 1 to 3 drop features that cannot be supported under spi-mem at the moment (backward compatibility is maintained). Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to spi-mem and patch 7 moves the driver to drivers/spi folder. I have tested both INDAC mode (used by non TI platforms like Altera SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs. Patches to move move bindings over to "Documentation/devicetree/bindings/spi/" directory and also conversion of bindig doc to YAML will be posted separately. Support for Intel platform would follow that. Resend v3: Rebased onto v5.7-c1 v3: Split handling of probe deferral into separate patch (out of 5/6) Split dropping of redundant WREN to separate patch (out of 5/6) Fix a possible memleak due to lack of spi_master_put() Parse all SPI slave nodes in cqspi_setup_flash() Address misc comments from Tudor on v2 Rebase onto latest spi-nor/next v2: Rework patch 1/6 to keep "cdns,is-decoded-cs" property supported. Ramuthevar Vadivel Murugan (2): mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework spi: Move cadence-quadspi driver to drivers/spi/ Vignesh Raghavendra (6): mtd: spi-nor: cadence-quadspi: Make driver independent of flash geometry mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC mode mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on failure mtd: spi-nor: cadence-quadspi: Fix error path on failure to acquire reset lines mtd: spi-nor: cadence-quadspi: Handle probe deferral while requesting DMA channel mtd: spi-nor: cadence-quadspi: Drop redundant WREN in erase path drivers/mtd/spi-nor/controllers/Kconfig | 11 - drivers/mtd/spi-nor/controllers/Makefile | 1 - drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + .../spi-cadence-quadspi.c} | 541 +++++++----------- 5 files changed, 222 insertions(+), 343 deletions(-) rename drivers/{mtd/spi-nor/controllers/cadence-quadspi.c => spi/spi-cadence-quadspi.c} (74%) base-commit: b3a9e3b9622ae10064826dccb4f7a52bd88c7407 -- 2.26.2 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
| * spi: Move cadence-quadspi driver to drivers/spi/Ramuthevar Vadivel Murugan2020-06-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that cadence-quadspi has been converted to use spi-mem framework, move it under drivers/spi/ Update license header to match SPI subsystem style Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-9-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: add Renesas RPC-IF driverSergei Shtylyov2020-06-161-0/+1
|/ | | | | | | | | | | | | Add the SPI driver for the Renesas RPC-IF. It's the "front end" driver using the "back end" APIs in the main driver to talk to the real hardware. We only implement the 'spi-mem' interface -- there's no need to implement the usual SPI driver methods... Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Link: https://lore.kernel.org/r/1ece0e6c-71af-f0f1-709e-571f4b0b4853@cogentembedded.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Move Non-DMA code to the DW PCIe-SPI driverSerge Semin2020-05-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparation patch before adding the DW DMA support into the DW SPI MMIO driver. We need to unpin the Non-DMA-specific code from the intended to be generic DW APB SSI DMA code. This isn't that hard, since the most part of the spi-dw-mid.c driver in fact implements a generic DMA interface for the DW SPI controller driver. The only Intel MID specifics concern getting the max frequency from the MRST Clock Control Unit and fetching the DMA controller channels from corresponding PCIe DMA controller. Since first one is related with the SPI interface configuration we moved it' implementation into the DW PCIe-SPI driver module. After that former spi-dw-mid.c file can be just renamed to be the DW SPI DMA module optionally compiled in to the DW APB SSI core driver. Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Feng Tang <feng.tang@intel.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200529131205.31838-11-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Add core suffix to the DW APB SSI core source fileSerge Semin2020-05-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | Generic DMA support is going to be part of the DW APB SSI core object. In order to preserve the kernel loadable module name as spi-dw.ko, let's add the "-core" suffix to the object with generic DW APB SSI code and build it into the target spi-dw.ko driver. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Feng Tang <feng.tang@intel.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200529131205.31838-10-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-amd: Add AMD SPI controller driver supportSanjay R Mehta2020-04-271-0/+1
| | | | | | | | | | This driver supports SPI Controller for AMD SOCs.This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1587844788-33997-1-git-send-email-sanju.mehta@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'mtk-mtd-spi-move' of ↵Mark Brown2020-03-111-0/+1
|\ | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.7 spi: Rewrite mtk-quadspi spi-nor driver with spi-mem This patchset from Chuanhong Guo <gch981213@gmail.com> adds a spi-mem driver for Mediatek SPI-NOR controller, which already has limited support by mtk-quadspi. This new driver can make use of full quadspi capability of this controller.
| * spi: add support for mediatek spi-nor controllerChuanhong Guo2020-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a driver for mtk spi-nor controller using spi-mem interface. The same controller already has limited support provided by mtk-quadspi driver under spi-nor framework and this new driver is a replacement for the old one. Comparing to the old driver, this driver has following advantages: 1. It can handle any full-duplex spi transfer up to 6 bytes, and this is implemented using generic spi interface. 2. It take account into command opcode properly. The reading routine in this controller can only use 0x03 or 0x0b as opcode on 1-1-1 transfers, but old driver doesn't implement this properly. This driver checks supported opcode explicitly and use (1) to perform unmatched operations. 3. It properly handles SFDP reading. Old driver can't read SFDP due to the bug mentioned in (2). 4. It can do 1-2-2 and 1-4-4 fast reading on spi-nor. These two ops requires parsing SFDP, which isn't possible in old driver. And the old driver is only flagged to support 1-1-2 mode. 5. It takes advantage of the DMA feature in this controller for long reads and supports IRQ on DMA requests to free cpu cycles from polling status registers on long DMA reading. It achieves up to 17.5MB/s reading speed (1-4-4 mode) which is way faster than the old one. IRQ is implemented as optional to maintain backward compatibility. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/20200306085052.28258-3-gch981213@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: Add FSI-attached SPI controller driverEddie James2020-03-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There exists a set of SPI controllers on some POWER processors that may be accessed through the FSI bus. Add a driver to traverse the FSI CFAM engine that can access and drive the SPI controllers. This driver would typically be used by a baseboard management controller (BMC). The SPI controllers operate by means of programming a sequencing engine which automatically manages the usual SPI protocol buses. The driver programs each transfer into the sequencer as various operations specifying the slave chip and shifting data in and out on the lines. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20200306194118.18581-3-eajames@linux.ibm.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: Add generic SPI multiplexerChris Packham2020-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add a SPI device driver that sits in-band and provides a SPI controller which supports chip selects via a mux-control. This enables extra SPI devices to be connected with limited native chip selects. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20200204032838.20739-3-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: add driver for ar934x spi controllerChuanhong Guo2020-02-111-0/+1
|/ | | | | | | | | | | | This patch adds driver for SPI controller found in Qualcomm Atheros AR934x/QCA95xx SoCs. This controller is a superset of the already supported qca,ar7100-spi. Besides the bit-bang mode in spi-ath79.c, this new controller added a new "shift register" mode, allowing faster spi operations. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/20200210034152.49063-2-gch981213@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Add HiSilicon v3xx SPI NOR flash controller driverJohn Garry2020-01-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add the driver for the HiSilicon v3xx SPI NOR flash controller, commonly found in hi16xx chipsets. This is a different controller than that in drivers/mtd/spi-nor/hisi-sfc.c; indeed, the naming for that driver is poor, since it is really known as FMC, and can support other memory technologies. The driver module name is "hisi-sfc-v3xx", as recommended by HW designer, being an attempt to provide a distinct name - v3xx being the unique controller versioning. Only ACPI firmware is supported. DMA is not supported, and we just use polling mode for operation completion notification. The driver uses the SPI MEM OPs. Signed-off-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1575900490-74467-3-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2019-09-161-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "This contains driver changes that are tightly connected to SoC specific code. Aside from smaller cleanups and bug fixes, here is a list of the notable changes. New device drivers: - The Turris Mox router has a new "moxtet" bus driver for its on-board pluggable extension bus. The same platform also gains a firmware driver. - The Samsung Exynos family gains a new Chipid driver exporting using the soc device sysfs interface - A similar socinfo driver for Qualcomm Snapdragon chips. - A firmware driver for the NXP i.MX DSP IPC protocol using shared memory and a mailbox Other changes: - The i.MX reset controller driver now supports the NXP i.MX8MM chip - Amlogic SoC specific drivers gain support for the S905X3 and A311D chips - A rework of the TI Davinci framebuffer driver to allow important cleanups in the platform code - A couple of device drivers for removed ARM SoC platforms are removed. Most of the removals were picked up by other maintainers, this contains whatever was left" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (123 commits) bus: uniphier-system-bus: use devm_platform_ioremap_resource() soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access firmware: ti_sci: Allow for device shared and exclusive requests bus: imx-weim: remove incorrect __init annotations fbdev: remove w90x900/nuc900 platform drivers spi: remove w90x900 driver net: remove w90p910-ether driver net: remove ks8695 driver firmware: turris-mox-rwtm: Add sysfs documentation firmware: Add Turris Mox rWTM firmware driver dt-bindings: firmware: Document cznic,turris-mox-rwtm binding bus: moxtet: fix unsigned comparison to less than zero bus: moxtet: remove set but not used variable 'dummy' ARM: scoop: Use the right include dt-bindings: power: add Amlogic Everything-Else power domains bindings soc: amlogic: Add support for Everything-Else power domains controller fbdev: da8xx: use resource management for dma fbdev: da8xx-fb: drop a redundant if fbdev: da8xx-fb: use devm_platform_ioremap_resource() ...
| * spi: remove w90x900 driverArnd Bergmann2019-09-041-1/+0
| | | | | | | | | | | | | | | | | | The ARM w90x900 platform is getting removed, so this driver is obsolete. Link: https://lore.kernel.org/r/20190809202749.742267-8-arnd@arndb.de Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | spi: npcm-fiu: add NPCM FIU controller driverTomer Maimon2019-08-301-0/+1
|/ | | | | | | | | | | | | | | | | | Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20190828142513.228556-3-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Add spi driver for Socionext SynQuacer platformMasahisa Kojima2019-06-041-0/+1
| | | | | | | | | This patch adds support for controller found on synquacer platforms. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-mem: Add support for Zynq QSPI controllerNaga Sureshkumar Relli2019-04-051-0/+1
| | | | | | | Add support for QSPI controller driver used by Xilinx Zynq SOC. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: mt7621: Move SPI driver out of stagingStefan Roese2019-03-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch moves the MT7621 SPI driver, which is used on some Ralink / MediaTek MT76xx MIPS SoC's, out of the staging directory. No changes to the source code are done in this patch. This driver version was tested successfully on an MT7688 based platform with an SPI NOR on CS0 and an SPI NAND on CS1 without any issues (so far). This patch also documents the devicetree bindings for the MT7621 SPI device driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Rob Herring <robh@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: NeilBrown <neil@brown.name> Cc: Sankalp Negi <sankalpnegi2310@gmail.com> Cc: Chuanhong Guo <gch981213@gmail.com> Cc: John Crispin <john@phrozen.org> Cc: Armando Miraglia <arma2ff0@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: sifive: Add driver for the SiFive SPI controllerYash Shah2019-02-191-0/+1
| | | | | | | | | | Add driver for the SiFive SPI controller on the HiFive Unleashed board. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-mem: Add driver for NXP FlexSPI controllerYogesh Narayan Gaur2019-01-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add driver for NXP FlexSPI host controller (0) What is the FlexSPI controller? FlexSPI is a flexsible SPI host controller which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. It uses new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash devices (2 buses with 2 CS each). (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility on NXP LX2160ARDB and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512ab, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Tested-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Add a driver for the Freescale/NXP QuadSPI controllerFrieder Schrempf2019-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash chips (2 buses with 2 CS each). The controller does not support generic SPI messages. This patch also disables the build of the "old" driver and reuses its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Han Xu <han.xu@nxp.com> Reviewed-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Tested-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Tested-by: Han Xu <han.xu@nxp.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'spi/topic/mem' and 'spi/topic/mtd' into spi-nextMark Brown2018-12-201-0/+1
|\ \
| | * spi: Add QuadSPI driver for Atmel SAMA5D2Piotr Bugalski2018-11-071-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | Kernel contains QSPI driver strongly tied to MTD and nor-flash memory. New spi-mem interface allows usage also other memory types, especially much larger NAND with SPI interface. This driver works as SPI controller and is not related to MTD, however can work with NAND-flash or other peripherals using spi-mem interface. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Piotr Bugalski <bugalski.piotr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: npcm: add NPCM PSPI controller driverTomer Maimon2018-11-131-0/+1
| | | | | | | | | | | | | | Add Nuvoton NPCM BMC Peripheral SPI controller driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: Add MXIC controller driverMason Yang2018-11-051-0/+1
|/ | | | | | | | Add a driver for Macronix SPI controller IP. Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'mfd-next-4.20' of ↵Linus Torvalds2018-10-251-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "New Drivers - Add support for USART SPI to AT91* New Functionality - Add support for Audio CODECs to motorola-cpcap Fix-ups - DT documentation fix-ups; atmel-usart - Staticise functions/structs; spi-at91-usart, arizona-core - Constify; ti-lmu - Fix memory leaks; menelaus - Change device 'wake-up' status; ti_am335x_tscadc, max8997 - Power Management (suspend/resume) semantic changes; ti_am335x_adc, cros_ec, max8997 - SPDX churn; sec-core (+ headers), max* (+ headers), intel* (+ headers), - Trivial (whitespace, email addresses, alphabetisise); Kconfig, adp5520, intel_soc_pmic_* - Build as module; sec-irq - Use new %pOFn printk format for device_node.name; max77620 - Remove unused code; madera - Use generic MACROs; intel_msic, intel_soc_pmic_crc - Move to GPIOD; ti-lmu - Use managed resources; ti-lmu Bug Fixes - Add missing headers; at91-usart - Prevent device from entering low-power mode; arizona-core - Poll for BOOT_DONE to avoid still-booting NACK; madera-core - Prevent ADC read from shutting down device; mc13xxx-core" * tag 'mfd-next-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits) mfd: cros_ec: Avoid unneeded internal declaration warning mfd: ti-lmu: Use of_device_get_match_data() helper mfd: ti-lmu: Use managed resource for everything mfd: ti-lmu: Switch to GPIOD mfd: ti-lmu: constify mfd_cell tables mfd: max8997: Disable interrupt handling for suspend/resume cycle mfd: max8997: Enale irq-wakeup unconditionally mfd: arizona: Make array mclk_name static, shrinks object size MAINTAINERS: Add myself as designated reviewer of Intel MFD PMIC mfd: Convert Intel PMIC drivers to use SPDX identifier 1;5201;0c Reduce size of duplicated comments by switching to use SPDX identifier. mfd: Sort headers alphabetically for Intel PMIC drivers mfd: intel_soc_pmic_bxtwc: Chain power button IRQs as well mfd: intel_soc_pmic_crc: Use REGMAP_IRQ_REG() macro mfd: intel_soc_pmic_crc: Use DEFINE_RES_IRQ_NAMED() macro mfd: intel_msic: Use DEFINE_RES_IRQ() macro mfd: motorola-cpcap: Add audio-codec support mfd: mc13xxx-core: Fix PMIC shutdown when reading ADC values mfd: madera: Remove unused forward reference mfd: max77620: Convert to using %pOFn instead of device_node.name mfd: madera: Don't use regmap_read_poll_timeout to poll for BOOT_DONE ...
| * spi: at91-usart: Add driver for at91-usart as SPIRadu Pirea2018-09-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the driver for at91-usart in spi mode. The USART IP can be configured to work in many modes and one of them is SPI. The driver was tested on sama5d3-xplained and sama5d4-xplained boards with enc28j60 ethernet controller as slave. Signed-off-by: Radu Pirea <radu.pirea@microchip.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviwed-by: Mark Brown <broonie@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* | spi: spi-mem: add stm32 qspi controllerLudovic Barre2018-10-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The qspi controller is a specialized communication interface targeting single, dual or quad SPI Flash memories (NOR/NAND). It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory tested on: -NOR: mx66l51235l -NAND: MT29F2G01ABAGD Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-geni-qcom: Add SPI driver support for GENI based QUPGirish Mahadevan2018-10-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver supports GENI based SPI Controller in the Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable module supporting a wide range of serial interfaces including SPI. This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> Signed-off-by: Dilip Kota <dkota@codeaurora.org> Signed-off-by: Alok Chauhan <alokc@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: Introduce new driver for Qualcomm QuadSPI controllerGirish Mahadevan2018-10-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | New driver for Qualcomm QuadSPI(QSPI) controller that is used to communicate with slaves such as flash memory devices. The QSPI controller can operate in 2 or 4 wire mode but only supports SPI Mode 0. The controller can also operate in Single or Dual data rate modes. Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> Signed-off-by: Ryan Case <ryandcase@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: mediatek: add spi slave for Mediatek MT2712Leilk Liu2018-09-281-0/+1
| | | | | | | | | | | | | | This patch adds basic spi slave for MT2712. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: sprd: Add SPI driver for Spreadtrum SC9860Lanqing Liu2018-08-281-0/+1
|/ | | | | | | | This patch adds the SPI controller driver for Spreadtrum SC9860 platform. Signed-off-by: Lanqing Liu <lanqing.liu@spreadtrum.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: add SPI controller driver for UniPhier SoCKeiji Hayashibara2018-08-011-0/+1
| | | | | | | | | | | | | | | | | | Add SPI controller driver implemented in Socionext UniPhier SoCs. UniPhier SoCs have two types SPI controllers; SCSSI supports a single channel, and MCSSI supports multiple channels. This driver supports SCSSI only. This controller has 32bit TX/RX FIFO with depth of eight entry, and supports the SPI master mode only. This commit is implemented in PIO transfer mode, not DMA transfer. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Extend the core to ease integration of SPI memory controllersBoris Brezillon2018-05-111-0/+1
| | | | | | | | | | | | | | | | Some controllers are exposing high-level interfaces to access various kind of SPI memories. Unfortunately they do not fit in the current spi_controller model and usually have drivers placed in drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI memories in general. This is an attempt at defining a SPI memory interface which works for all kinds of SPI memories (NORs, NANDs, SRAMs). Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de> Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: remove forgotten CONFIG_SPI_BCM53XXRafał Miłecki2018-05-101-1/+0
| | | | | | | | | | | I accidentally sent an early version of patch removing spi-bcm53xx driver which got rid of .c and .h files *only*. I amended local commit but forgot to re-format the patch. This commit removes leftovers of dropped driver. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: remove blackfin related host driversArnd Bergmann2018-03-261-3/+0
| | | | | | | | | The blackfin architecture is getting removed, so these won't be needed any more. Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Aaron Wu <aaron.wu@analog.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
*-. Merge remote-tracking branches 'spi/topic/sh-msiof', 'spi/topic/slave', ↵Mark Brown2017-11-101-0/+1
|\ \ | | | | | | | | | 'spi/topic/spreadtrum' and 'spi/topic/tegra114' into spi-next
| | * spi: Add ADI driver for Spreadtrum platformBaolin Wang2017-09-191-0/+1
| |/ | | | | | | | | | | | | | | This patch adds ADI driver based on SPI framework for Spreadtrum SC9860 platform. Signed-off-by: Baolin Wang <baolin.wang@spreadtrum.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* / License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
*-. Merge remote-tracking branches 'spi/topic/spidev', 'spi/topic/st-ssc4' and ↵Mark Brown2017-07-031-0/+1
|\ \ | | | | | | | | | 'spi/topic/stm32' into spi-next
| | * spi: add driver for STM32 SPI controllerAmelie Delaunay2017-06-211-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | The STM32 Serial Peripheral Interface (SPI) can be used to communicate with external devices while using the specific synchronous protocol. It supports a half-duplex, full-duplex and simplex synchronous, serial communication with external devices with 4-bit to 16/32-bit per word. It has two 8x/16x 8-bit embedded Rx and TxFIFOs with DMA capability. It can operate in master or slave mode. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-02 10:49:15 +0000