summaryrefslogtreecommitdiffstats
path: root/drivers/usb/dwc2/core.c
Commit message (Collapse)AuthorAgeFilesLines
* usb: dwc2: Update Core Reset programming flow.Minas Harutyunyan2020-05-251-4/+19
| | | | | | | | | | | | | | | | Starting from core version 4.20a Core Reset flow is changed. Introduced new bit in GRSTCTL register - GRSTCTL_CSFTRST_DONE. Core Reset new programming flow steps are follow: 1. Set GRSTCTL_CSFTRST bit. 2. Wait for bit GRSTCTL_CSFTRST_DONE is set. 3. Clear GRSTCTL_CSFTRST and GRSTCTL_CSFTRST_DONE bits. Check core version functionality separated from dwc2_get_hwparams() to new dwc2_check_core_version() function because Core Reset flow depend on SNPSID. Signed-off-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: use a longer core rest timeout in dwc2_core_reset()Mathias Kresin2019-10-221-1/+1
| | | | | | | | | | | | | | | | | Testing on different generations of Lantiq MIPS SoC based boards, showed that it takes up to 1500 us until the core reset bit is cleared. The driver from the vendor SDK (ifxhcd) uses a 1 second timeout. Use the same timeout to fix wrong hang detections and make the driver work for Lantiq MIPS SoCs. At least till kernel 4.14 the hanging reset only caused a warning but the driver was probed successful. With kernel 4.19 errors out with EBUSY. Cc: linux-stable <stable@vger.kernel.org> # 4.19+ Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: use a longer AHB idle timeout in dwc2_core_reset()Martin Blumenstingl2019-07-031-1/+1
| | | | | | | | | | | | | | | | | | | | Use a 10000us AHB idle timeout in dwc2_core_reset() and make it consistent with the other "wait for AHB master IDLE state" ocurrences. This fixes a problem for me where dwc2 would not want to initialize when updating to 4.19 on a MIPS Lantiq VRX200 SoC. dwc2 worked fine with 4.14. Testing on my board shows that it takes 180us until AHB master IDLE state is signalled. The very old vendor driver for this SoC (ifxhcd) used a 1 second timeout. Use the same timeout that is used everywhere when polling for GRSTCTL_AHBIDLE instead of using a timeout that "works for one board" (180us in my case) to have consistent behavior across the dwc2 driver. Cc: linux-stable <stable@vger.kernel.org> # 4.19+ Acked-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: gadget: Move gadget phy init into core phy initJules Maselbas2019-05-031-0/+9
| | | | | | | | | | Most of the phy initialization is shared between host and gadget, this adds the turnaround configuration only used by gadgets to the global phy init. Acked-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Move phy init into coreJules Maselbas2019-05-031-0/+190
| | | | | | | | | | As the phy initialization is almost the same in host and gadget mode. This only move the phy initialization functions into core.c for now, the goal is to share theses functions between the two modes. Acked-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Modify dwc2_readl/writel functions prototypeGevorg Sahakyan2018-07-301-120/+121
| | | | | | | | | | | | Added hsotg argument to dwc2_readl/writel function prototype, and also instead of address pass offset of register. hsotg will contain flag field for endianness. Also customized dwc2_set_bit and dwc2_clear_bit function for dwc2_readl/writel functions. Signed-off-by: Gevorg Sahakyan <sahakyan@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Fix kernel doc's warnings.Grigor Tovmasyan2018-05-211-0/+7
| | | | | | | | | Added descriptions for all not described parameters. Fix all kernel doc's warnings. Acked-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Make dwc2_force_mode() staticGrigor Tovmasyan2018-03-131-1/+1
| | | | | | | | | Declared dwc2_force_mode() function as static, because it was used only in core.c file, for fixing sparse error. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Force mode optimizationsVardan Mikayelyan2018-03-131-47/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the dr_mode is USB_DR_MODE_OTG, forcing the mode is needed during driver probe to get the host and device specific HW parameters. Then we clear the force mode bits so that the core operates in OTG mode. The force mode bits should not be touched at any other time during the driver lifetime and they should be preserved whenever the GUSBCFG register is written to. The force mode bit values will persist across soft resets of the core. If the dr_mode is either USB_DR_MODE_HOST or USB_DR_MODE_PERIPHERAL, the force mode is set just once at probe to configure the core as either a host or peripheral. Given the above, we no longer need any other reset delays, force delays, or any forced modes anywhere else in the driver. So replace all calls to dwc2_core_reset_and_force_dr_mode() with dwc2_core_reset() and remove all other unnecessary delays. Also remove the dwc2_force_mode_if_needed() function since the "if needed" part is already taken care of by the polling in dwc2_force_mode(). Finally, remove all other calls to dwc2_clear_force_mode(). Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Add dwc2_enter_hibernation(), dwc2_exit_hibernation()Vardan Mikayelyan2018-03-131-0/+38
| | | | | | | | | | These are wrapper functions which are calling device or host enter/exit hibernation functions. Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Add host/device hibernation functionsVardan Mikayelyan2018-03-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | Add host/device hibernation functions which must be wrapped by core's dwc2_enter_hibernation()/dwc2_exit_hibernation() functions. Make dwc2_backup_global_registers dwc2_restore_global_register non-static to use them in both host/gadget sides. Added function names: dwc2_gadget_enter_hibernation() dwc2_gadget_exit_hibernation() dwc2_host_enter_hibernation() dwc2_host_exit_hibernation() Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Artur Petrosyan <arturp@synopsys.com> Signed-off-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Add helper functions for restore routineVardan Mikayelyan2018-03-131-0/+136
| | | | | | | | | | | | | | | Add common (host/device) helper functions, which will be called while exiting from hibernation, from both sides. dwc2_restore_essential_regs() dwc2_hib_restore_common() Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Artur Petrosyan <arturp@synopsys.com> Signed-off-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Changes in registers backup/restore functionsVardan Mikayelyan2018-03-131-2/+6
| | | | | | | | | | | | | | | | | | | Move hptxfsiz to host register's backup/restore functions, not needed to have it in global register's backup/restore functions. Add backup for glpmcfg, and read/write for gi2cctl and pcgcctl. As requires programming guide. Affected functions: dwc2_backup_host_registers() dwc2_restore_host_registers() dwc2_backup_global_registers() dwc2_restore_global_registers() Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: gadget: Fix dwc2_restore_device_registersVardan Mikayelyan2018-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | Add parameter remote_wakeup to dwc2_restore_device_registers() to be able to restore device registers according to programming guide for dwc-otg. It says that in case of rem_wakeup DCTL must not be restored here. Remove setting of DCTL_PWRONPRGDONE from this function, because it will be done in function responsible for exiting from hibernation. WA for enabled EPx's IN and OUT in DDMA mode. On entering to hibernation wrong value read and saved from DIEPDMAx, as result BNA interrupt asserted on hibernation exit by restoring from saved area. Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Artur Petrosyan <arturp@synopsys.com> Signed-off-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: gadget: Moved dtxfsiz backup array placeVardan Mikayelyan2018-03-131-6/+2
| | | | | | | | | | Moved dtxfsiz from dwc2_gregs_backup to dwc2_dregs_backup, because it is device register. Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Add hibernation field into dwc2_hw_paramsVardan Mikayelyan2018-03-131-1/+1
| | | | | | | | | | | | | | | Add parameter and it's initialization, needed for hibernation. Reimplement dwc2_set_param_power_down() to support hibernation too. Now 'power_down' parameter can be initialized with 0, 1 or 2. 0 - No 1 - Partial power down 2 - Hibernation Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Rename hibernation to partial_power_downVardan Mikayelyan2018-03-131-7/+7
| | | | | | | | | | | | | | | No-op change, only rename. This code was misnamed originally. It was only responsible for partial power down and not for hibernation. Rename core_params->hibernation to core_params->power_down, dwc2_set_param_hibernation() to dwc2_set_param_power_down(). Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Backup and restore PCGCCTL1 registerRazmik Karapetyan2018-03-131-0/+2
| | | | | | | | | | Backup PCGCCTL1 register when entering hibernation mode and restore it after exiting from hibernation, to keep active ACG feature. Signed-off-by: Razmik Karapetyan <razmik@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Add ACG support to the driverRazmik Karapetyan2018-03-131-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Added function for supporting Active Clock Gating functionality in the driver. PCGCCTL1 (Power and Clock Control) register will be used for controlling the core`s active clock gating feature, and the previously reserved 12th bit in GHWCFG4 now indicates that the controller supports the Dynamic Power Reduction (Active Clock Gating) during no traffic scenarios such as L0, idle, resume and suspend states. dwc2_enable_acg() function sets GATEEN bit in PCGCCTL1 register and enables ACG, if it supported. According to ACG functional specification, enabling of ACG feature in host mode done in host initialization, before turning Vbus on, specifically in dwc2_core_host_init function. Enabling of ACG feature in device mode done in device initialization, before clearing the SftDiscon bit in DCTL. This bit was cleared in dwc2_hsotg_core_connect() function.So dwc2_enable_acg() called before dwc2_core_connect() calls. Signed-off-by: Razmik Karapetyan <razmik@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Change TxFIFO and RxFIFO flushing flowMinas Harutyunyan2018-03-131-0/+10
| | | | | | | | | | Before flushing fifos required to check AHB master state and lush when AHB master is in IDLE state. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Update bit polling functionalitySevak Arakelyan2018-03-131-44/+64
| | | | | | | | | | | | | | | | Move dwc2_hsotg_wait_bit_set function to core.c so it can be used anywhere in the code. Added dwc2_hsotg_wait_bit_clear function in core.c. Replace all the parts of register bit polling code with dwc2_hsotg_wait_bit_set or dwc2_hsotg_wait_bit_clear functions calls depends on code logic. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Sevak Arakelyan <sevaka@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* USB: add SPDX identifiers to all remaining files in drivers/usb/Greg Kroah-Hartman2017-11-041-0/+1
| | | | | | | | | | | | | | | | | | | | | It's good to have SPDX identifiers in all files to make it easier to audit the kernel tree for correct licenses. Update the drivers/usb/ and include/linux/usb* files with the correct SPDX license identifier based on the license text in the file itself. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This work is based on a script and data from Thomas Gleixner, Philippe Ombredanne, and Kate Stewart. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kate Stewart <kstewart@linuxfoundation.org> Cc: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com> Acked-by: Johan Hovold <johan@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: dwc2: host: use msleep() for long delayNicholas Mc Guire2017-01-241-1/+1
| | | | | | | | | | | | ulseep_range() uses hrtimers and provides no advantage over msleep() for larger delays. Fix up the 100ms delays here passing the adjusted "min" value to msleep(). This helps reduce the load on the hrtimer subsystem. Link: http://lkml.org/lkml/2017/1/11/377 Fixes: commit 2938fc63e0c2 ("usb: dwc2: Properly account for the force mode delays") Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Avoid sleeping while holding hsotg->lockJohn Stultz2017-01-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basically when plugging in various cables in different orders, I'm occasionally seeing the following BUG splat: [ 86.215403] BUG: scheduling while atomic: kworker/u16:2/53/0x00000002 [ 86.219164] usb 1-1: USB disconnect, device number 9 [ 86.226845] Preemption disabled at:[ 86.230218] [<ffffff8008673558>] dwc2_conn_id_status_change+0x120/0x250 [ 86.236894] CPU: 0 PID: 53 Comm: kworker/u16:2 Tainted: G W 4.9.0-rc8-00051-gd5a7979-dirty #1702 [ 86.246836] Hardware name: HiKey Development Board (DT) [ 86.252100] Workqueue: dwc2 dwc2_conn_id_status_change [ 86.257279] Call trace: [ 86.259771] [<ffffff8008087c28>] dump_backtrace+0x0/0x1a0 [ 86.265210] [<ffffff8008087ddc>] show_stack+0x14/0x20 [ 86.270308] [<ffffff80084343f0>] dump_stack+0x90/0xb0 [ 86.275401] [<ffffff80080d8d94>] __schedule_bug+0x6c/0xb8 [ 86.280841] [<ffffff8008a07220>] __schedule+0x4f8/0x5b0 [ 86.286099] [<ffffff8008a073e8>] schedule+0x38/0xa0 [ 86.291017] [<ffffff8008a0a6cc>] schedule_hrtimeout_range_clock+0x8c/0xf0 [ 86.297846] [<ffffff8008a0a740>] schedule_hrtimeout_range+0x10/0x18 [ 86.304150] [<ffffff8008a0a4a0>] usleep_range+0x50/0x58 [ 86.309418] [<ffffff800866d8dc>] dwc2_wait_for_mode.isra.4+0x54/0xd0 [ 86.315815] [<ffffff800866f058>] dwc2_core_reset+0xe0/0x168 [ 86.321431] [<ffffff800867e364>] dwc2_hsotg_core_init_disconnected+0x2c/0x310 [ 86.328602] [<ffffff8008673568>] dwc2_conn_id_status_change+0x130/0x250 [ 86.335254] [<ffffff80080ccd48>] process_one_work+0x118/0x370 [ 86.341035] [<ffffff80080ccfe8>] worker_thread+0x48/0x498 [ 86.346473] [<ffffff80080d2eb0>] kthread+0xd0/0xe8 [ 86.351299] [<ffffff8008082e80>] ret_from_fork+0x10/0x50 This seems to be caused by the dwc2_wait_for_mode() calling usleep_range() while the hstog->lock spinlock is held, since we take that before calling dwc2_hsotg_core_init_disconnected(). This patch avoids the issue by adding an extra argument to dwc2_core_reset(), as suggested by John Youn, which allows us to skip the waiting, which should be unnecessary when calling from dwc2_hsotg_core_init_disconnected(). Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Cc: Amit Pundir <amit.pundir@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: John Youn <johnyoun@synopsys.com> Cc: Douglas Anderson <dianders@chromium.org> Cc: Chen Yu <chenyu56@huawei.com> Cc: Vardan Mikayelyan <mvardan@synopsys.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Felipe Balbi <felipe.balbi@linux.intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-usb@vger.kernel.org Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Fix usage of bool paramsJohn Youn2017-01-241-2/+2
| | | | | | | | Check these parameters only for true or false. There is no need to check for greater or less than 0. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Remove unused otg_ver parameterJohn Youn2017-01-241-5/+0
| | | | | | | | The otg_ver parameter only controls the SRP pulsing method and defaults to the 1.3 behavior. It is unused and can be removed. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Cleanup some checkpatch issuesJohn Youn2017-01-241-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | This commmit is the result of running checkpatch --fix. The results were verified for correctness. Some of the fixes result in line over 80 char which we will fix manually later. The following is a summary of what was done by checkpatch: * Remove externs on function prototypes. * Replace symbolic permissions with octal. * Align code to open parens. * Replace 'unsigned' with 'unsigned int'. * Remove unneccessary blank lines. * Add blank lines after declarations. * Add spaces around operators. * Remove unnecessary spaces after casts. * Replace 'x == NULL' with '!x'. * Replace kzalloc() with kcalloc(). * Concatenate multi-line strings. * Use the BIT() macro. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Declare the core params struct staticallyJohn Youn2016-11-181-6/+6
| | | | | | | | This makes it consistent with the hw_params struct and simplifies the memory management for future refactoring. Fix up usage in all files. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Add params.c fileJohn Youn2016-11-181-916/+2
| | | | | | | | Add a params.c file and move all driver parameter code there, including all the static parameter definitions. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Add msleep for host-onlyHeiko Stuebner2016-10-171-1/+10
| | | | | | | | | | | | Although a host-only controller should not have any associated delay, some rockchip SOC platforms will not show the correct host-values of registers until after a delay. So add a 50 ms sleep when in host-only mode. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Properly account for the force mode delaysJohn Youn2016-09-081-17/+14
| | | | | | | | | | | | | | | | When a force mode bit is set and the IDDIG debounce filter is enabled, there is a delay for the forced mode to take effect. This delay is due to the IDDIG debounce filter and is variable depending on the platform's PHY clock speed. To account for this delay we can poll for the expected mode. On a clear force mode, since we don't know what mode to poll for, delay for a fixed 100 ms. This is the maximum delay based on the slowest PHY clock speed. Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Add delay to core soft resetJohn Youn2016-09-081-0/+95
| | | | | | | | | | | | | | Add a delay to the core soft reset function to account for the IDDIG debounce filter. If the current mode is host, either due to the force mode bit being set (which persists after core reset) or the connector id pin, a core soft reset will temporarily reset the mode to device and a delay from the IDDIG debounce filter will occur before going back to host mode. Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc2: Move host-specific core functions into hcd.cJohn Youn2016-03-041-1776/+0
| | | | | | | | | | | Move host core initialization and host channel routines into hcd.c. This allows these functions to only be compiled in host-enabled driver configurations (DRD or host-only). Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: Move register save and restore functionsJohn Youn2016-03-041-183/+0
| | | | | | | | | | Move the register save and restore functions into the host and gadget specific files. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: Properly set even/odd frameDouglas Anderson2016-03-041-2/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting up ISO and INT transfers dwc2 needs to specify whether the transfer is for an even or an odd frame (or microframe if the controller is running in high speed mode). The controller appears to use this as a simple way to figure out if a transfer should happen right away (in the current microframe) or should happen at the start of the next microframe. Said another way: - If you set "odd" and the current frame number is odd it appears that the controller will try to transfer right away. Same thing if you set "even" and the current frame number is even. - If the oddness you set and the oddness of the frame number are _different_, the transfer will be delayed until the frame number changes. As I understand it, the above technique allows you to plan ahead of time where possible by always working on the next frame. ...but it still allows you to properly respond immediately to things that happened in the previous frame. The old dwc2_hc_set_even_odd_frame() didn't really handle this concept. It always looked at the frame number and setup the transfer to happen in the next frame. In some cases that meant that certain transactions would be transferred in the wrong frame. We'll try our best to set the even / odd to do the transfer in the scheduled frame. If that fails then we'll do an ugly "schedule ASAP". We'll also modify the scheduler code to handle this and not try to schedule a second transfer for the same frame. Note that this change relies on the work to redo the microframe scheduler. It can work atop ("usb: dwc2: host: Manage frame nums better in scheduler") but it works even better after ("usb: dwc2: host: Totally redo the microframe scheduler"). With this change my stressful USB test (USB webcam + USB audio + keyboards) has less audio crackling than before. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: Properly set the HFIRDouglas Anderson2016-03-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the most up to date version of the dwc2 databook, the FRINT field of the HFIR register should be programmed to: * 125 us * (PHY clock freq for HS) - 1 * 1000 us * (PHY clock freq for FS/LS) - 1 This is opposed to older versions of the doc that claimed it should be: * 125 us * (PHY clock freq for HS) * 1000 us * (PHY clock freq for FS/LS) In case you didn't spot it, the difference is the "- 1". Let's add the "- 1" to match the newest user manual. It's presumed that the "- 1" should have always been there and that this was always a documentation error. If some hardware needs the "- 1" and other hardware doesn't, we'll have to add a configuration parameter for it in the future. I checked things before and after this patch on rk3288 using a Total Phase Beagle 5000 analyzer. Before this patch, a low speed mouse shows constant Frame Timing Jitter errors. After this patch errors have gone away. Before this patch SOF packets move forward about 1 us per 4 ms. After this patch the SOF packets move backward about 1 us per 255 ms. Some specific SOF timestamps from the analyzer are below. Before: 6.603.790 6.603.916 6.604.041 6.604.166 ... 6.607.541 6.607.667 6.607.792 6.607.917 ... 6.611.417 6.611.543 6.611.668 6.611.793 After: 6.215.159 6.215.284 6.215.408 6.215.533 6.215.658 ... 6.470.658 6.470.783 6.470.907 ... 6.726.032 6.726.157 6.725.281 6.725.406 Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: fix split transfer schedule sequenceDouglas Anderson2016-03-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're supposed to keep outstanding splits in order. Keep track of a list of the order of splits and process channel interrupts in that order. Without this change and the following setup: * Rockchip rk3288 Chromebook, using port ff540000 -> Pluggable 7-port Hub with Charging (powered) -> Microsoft Wireless Keyboard 2000 in port 1. -> Das Keyboard in port 2. ...I find that I get dropped keys on the Microsoft keyboard (I'm sure there are other combinations that fail, but this documents my test). Specifically I've been typing "hahahahahahaha" on the keyboard and often see keys dropped or repeated. After this change the above setup works properly. This patch is based on a previous patch proposed by Yunzhi Li ("usb: dwc2: hcd: fix periodic transfer schedule sequence") Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: host: Get aligned DMA in a more supported wayDouglas Anderson2016-03-041-18/+3
| | | | | | | | | | | | | | | | | | | | | | All other host controllers who want aligned buffers for DMA do it a certain way. Let's do that too instead of working behind the USB core's back. This makes our interrupt handler not take forever and also rips out a lot of code, simplifying things a bunch. This also has the side effect of removing the 65535 max transfer size limit. NOTE: The actual code to allocate the aligned buffers is ripped almost completely from the tegra EHCI driver. At some point in the future we may want to add this functionality to the USB core to share more code everywhere. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: John Youn <johnyoun@synopsys.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: John Youn <johnyoun@synopsys.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: Add extra delay when forcing dr_modeJohn Youn2016-02-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | Fixes an issue found on rockchip rk3036 and rk3188 SOC platforms. For some reason, the existing msleep(25) is not enough after the force mode. The following patch was reported to fix the issue. This does increase the probe delay again slightly, but not up to the level it was before the original series of patches that this fixes. It does not cause any other issues when tested on Synopsys HAPS and Altera socfpga platforms. Need to revisit this series next release to see if we can address these issues without having an unconditional delay. Fixes: 09c96980dc72 ("usb: dwc2: Add functions to set and clear force mode") Reported-by: Caesar Wang <caesar.upstream@gmail.com> Reported-by: Michael Niewoehner <linux@mniewoehner.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Caesar Wang <caesar.upstream@gmail.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: Fix probe problem on bcm2835John Youn2016-02-031-6/+0
| | | | | | | | | | | | | | | Fixes an issue found on Raspberry PI platform that prevents probe. Don't skip setting the force mode if it's already set. Fixes: 09c96980dc72 ("usb: dwc2: Add functions to set and clear force mode") Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Reported-by: Stefan Wahren <stefan.wahren@i2se.com> Reported-by: Remi Pommarel <repk@triplefau.lt> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Tested-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* Revert "usb: dwc2: Move reset into dwc2_get_hwparams()"John Youn2016-02-031-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 263b7fb557f7 ("usb: dwc2: Move reset into dwc2_get_hwparams()") due to regression found on bcm2835 platform. USB ethernet fails, due to being unable to pick up proper parameters when performing a plain reset before reading hw params. Below shows the results of the gnptxfsiz and hptxfsiz with and before and after reverting this (from Stefan Wahren): So here is the probe result before Patch 1 is applied: [ 1.283148] dwc2 20980000.usb: Configuration mismatch. dr_mode forced to host [ 1.313894] dwc2 20980000.usb: gnptxfsiz=00201000 [ 1.314104] dwc2 20980000.usb: hptxfsiz=00000000 [ 1.353908] dwc2 20980000.usb: 256 invalid for host_nperio_tx_fifo_size. Check HW configuration. [ 1.354262] dwc2 20980000.usb: 512 invalid for host_perio_tx_fifo_size. Check HW configuration. [ 1.394249] dwc2 20980000.usb: DWC OTG Controller [ 1.394561] dwc2 20980000.usb: new USB bus registered, assigned bus number 1 [ 1.394917] dwc2 20980000.usb: irq 33, io mem 0x00000000 And here is the probe result after Patch 1 is applied: [ 1.280107] dwc2 20980000.usb: Configuration mismatch. dr_mode forced to host [ 1.353949] dwc2 20980000.usb: gnptxfsiz=01001000 [ 1.354166] dwc2 20980000.usb: hptxfsiz=02002000 [ 1.434301] dwc2 20980000.usb: DWC OTG Controller [ 1.434616] dwc2 20980000.usb: new USB bus registered, assigned bus number 1 [ 1.434973] dwc2 20980000.usb: irq 33, io mem 0x00000000 Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Reported-by: Stefan Wahren <stefan.wahren@i2se.com> Reported-by: Remi Pommarel <repk@triplefau.lt> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Tested-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc2: Reduce delay when forcing mode in resetJohn Youn2015-12-221-1/+1
| | | | | | | The delay for force mode is only 25ms according to the databook. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Improve handling of host and device hwparamsJohn Youn2015-12-221-21/+67
| | | | | | | | | | | Adds separate functions to get the host and device specific hardware parameters. The functions check whether the parameters need to be read at all, depending on dr_mode, and forces the mode only if necessary. This saves some delays during probe. This also adds two device mode parameters that will be used by the gadget. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Add functions to set and clear force modeJohn Youn2015-12-221-24/+125
| | | | | | | | | | | | | | Added functions to set force mode for host and device. These functions will check the current mode and only force if needed thus avoiding unnecessary force mode delays. However clearing the mode is currently done unconditionally and with the delay in place. This is needed during the connector ID status change interrupt in order to ensure that the mode has changed properly. This preserves the old behavior only for this case. The warning comment about this is moved into the clear mode condition. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Move reset into dwc2_get_hwparams()John Youn2015-12-221-0/+8
| | | | | | | | | The reset is required to get reset values of the hardware parameters but the force mode is not. Move the base reset into dwc2_get_hwparams() and do the reset and force mode afterwards. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Add functions to check the HW OTG configJohn Youn2015-12-221-0/+37
| | | | | | | | | | Added functions to query the GHWCFG2.OTG_MODE. This tells us whether the controller hardware is configured for OTG, device-only, or host-only. Signed-off-by: John Youn <johnyoun@synopsys.com> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Add dwc2_core_reset()John Youn2015-12-221-2/+20
| | | | | | | | | dwc2_core_reset() was previously renamed to dwc2_core_reset_and_dr_force_mode(). Now add back dwc2_core_reset() which performs only a basic core reset without forcing the mode. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Rename dwc2_core_reset()John Youn2015-12-221-4/+4
| | | | | | | | | | Renamed dwc2_core_reset() to dwc2_core_reset_and_force_dr_mode(). This describes what it is doing more accurately. This is in preparation of introducing a plain dwc2_core_reset() function that only performs the reset and doesn't force the mode. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Reorder AHBIDLE and CSFTRST in dwc2_core_reset()John Youn2015-12-221-8/+9
| | | | | | | | | | | According to the databook, the core soft reset should be done before checking for AHBIDLE. The gadget version of core reset had it correct but the hcd version did not. This fixes the hcd version. Signed-off-by: John Youn <johnyoun@synopsys.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc2: Avoid more calls to dwc2_core_reset()Douglas Anderson2015-12-221-17/+23
| | | | | | | | | | | | | | | | | | Calls to dwc2_core_reset() are currently very slow, taking at least 150ms (possibly more). It behooves us to take as many of these calls out as possible. It turns out that the calls in dwc2_fs_phy_init() and dwc2_hs_phy_init() should (as documented in the code) only be needed if we need to do a PHY SELECT. That means that if we see that we can avoid the PHY SELECT then we can avoid the reset. This patch appears to successfully bypass two resets (one per USB device) on rk3288-based ARM Chromebooks. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-02 17:09:15 +0000