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* clk: Fix debugfs reparenting NULL pointer dereferenceStephen Boyd2013-12-141-2/+1
* Merge tag 'clk-hisilicon' of git://git.kernel.org/pub/scm/linux/kernel/git/hz...Mike Turquette2013-12-126-0/+652
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| * clk: hi3620: add gate clock flagHaojian Zhuang2013-12-111-59/+59
| * clk: hi3620: fix wrong flags on dividerHaojian Zhuang2013-12-111-11/+11
| * clk: hisilicon: add common clock supportHaojian Zhuang2013-12-046-0/+652
* | Merge branch 'clk-next-shmobile' into clk-nextMike Turquette2013-12-125-0/+720
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| * | clk: shmobile: Add MSTP clock supportLaurent Pinchart2013-12-122-0/+230
| * | clk: shmobile: Add DIV6 clock supportLaurent Pinchart2013-12-122-0/+186
| * | clk: shmobile: Add R-Car Gen2 clocks supportLaurent Pinchart2013-12-123-0/+304
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* | clk: exynos5420: fix cpll clock register offsetsChander Kashyap2013-12-041-2/+2
* | Merge branch 'clk-tegra-next' of git://nv-tegra.nvidia.com/user/pdeschrijver/...Mike Turquette2013-12-0316-3008/+4678
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| * | clk: tegra: fix __clk_lookup() return value checksWei Yongjun2013-11-281-4/+4
| * | clk: tegra: Do not print errors for clk_round_rate()Thierry Reding2013-11-281-6/+3
| * | clk: tegra: Initialize DSI low-power clocksThierry Reding2013-11-261-0/+2
| * | clk: tegra: add FUSE clock deviceAlexandre Courbot2013-11-264-1/+4
| * | clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding2013-11-261-1/+3
| * | clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding2013-11-261-0/+1
| * | clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen2013-11-261-0/+2
| * | clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo2013-11-261-0/+27
| * | clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo2013-11-261-0/+26
| * | clk: tegra124: Add support for Tegra124 clocksPeter De Schrijver2013-11-262-0/+1371
| * | clk: tegra124: Add new peripheral clocksPeter De Schrijver2013-11-261-0/+69
| * | clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver2013-11-261-0/+22
| * | clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver2013-11-263-3/+22
| * | clk: tegra: add locking to periph clksPeter De Schrijver2013-11-262-19/+24
| * | clk: tegra: Add periph regs bank XPeter De Schrijver2013-11-261-0/+10
| * | clk: tegra: Add support for PLLSSPeter De Schrijver2013-11-262-2/+126
| * | clk: tegra: move tegra20 to common infraPeter De Schrijver2013-11-261-402/+255
| * | clk: tegra: move tegra30 to common infraPeter De Schrijver2013-11-261-895/+403
| * | clk: tegra: introduce common gen4 super clockPeter De Schrijver2013-11-264-74/+155
| * | clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver2013-11-265-74/+253
| * | clk: tegra: move periph clocks to common filePeter De Schrijver2013-11-266-581/+627
| * | clk: tegra: move audio clk to common filePeter De Schrijver2013-11-264-208/+402
| * | clk: tegra: add clkdev registration infraPeter De Schrijver2013-11-263-159/+179
| * | clk: tegra: add common infra for DT clocksPeter De Schrijver2013-11-262-0/+16
| * | clk: tegra: add header for common tegra clock IDsPeter De Schrijver2013-11-261-0/+213
| * | clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver2013-11-265-177/+175
| * | clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver2013-11-262-4/+7
| * | clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver2013-11-262-93/+111
| * | clk: tegra: Add TEGRA_PERIPH_NO_DIV flagPeter De Schrijver2013-11-262-3/+9
| * | clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver2013-11-266-108/+85
| * | clk: tegra: simplify periph clock dataPeter De Schrijver2013-11-267-584/+464
| * | clk: tegra: Fix clock rate computationThierry Reding2013-11-261-0/+2
| * | clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3dThierry Reding2013-11-261-4/+4
| * | clk: tegra: PLLE spread spectrum controlPeter De Schrijver2013-11-261-1/+29
| * | clk: tegra: Set the clk parent of host1x to pll_pAndrew Chew2013-11-261-0/+1
| * | clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver2013-11-262-33/+39
| * | clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2Mark Zhang2013-11-251-0/+3
| * | clk: tegra: Fix vde/2d/3d clock src offsetMark Zhang2013-11-251-10/+3
| * | clk: tegra: Correct sbc mux width & parentMark Zhang2013-11-251-6/+6
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-16 11:05:05 +0000