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* gianfar: add GRO supportWu Jiajun-B063782012-04-211-6/+7
| | | | | | | Replace netif_receive_skb with napi_gro_receive. Signed-off-by: Jiajun Wu <b06378@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* team: add per-port option for enabling/disabling portsJiri Pirko2012-04-211-0/+24
| | | | | Signed-off-by: Jiri Pirko <jpirko@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* team: allow to enable/disable portsJiri Pirko2012-04-213-18/+37
| | | | | | | | | | | | This patch changes content of hashlist (used to get port struct by computed index (0...en_port_count-1)). Now the hash list contains only enabled ports so userspace will be able to say what ports can be used for tx/rx. This becomes handy when userspace will need to disable ports which does not belong to active aggregator. By default, newly added port is enabled. Signed-off-by: Jiri Pirko <jpirko@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* team: lb: let userspace care about port macsJiri Pirko2012-04-211-12/+0
| | | | | | | Better to leave this for userspace Signed-off-by: Jiri Pirko <jpirko@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* sock: Introduce named constants for sk_reusePavel Emelyanov2012-04-213-5/+5
| | | | | | | | | Name them in a "backward compatible" manner, i.e. reuse or not are still 1 and 0 respectively. The reuse value of 2 means that the socket with it will forcibly reuse everyone else's port. Signed-off-by: Pavel Emelyanov <xemul@openvz.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* drivers/net: decouple ISA and ISA_DMA_APIArnd Bergmann2012-04-212-6/+6
| | | | | | | | | | The two options are separate, and some platforms (e.g. arm pxa) have ISA slots but no ISA dma controller, so they cannot build drivers using the DMA API functions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* sungem: use mdelay instead of udelay where necessaryArnd Bergmann2012-04-211-1/+1
| | | | | | | | | | Some architectures like ARM cannot handle large numbers as arguments to udelay, so the drivers should use mdelay when delaying for multiple miliseconds. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* donauboe: replace excessive udelay with msleepArnd Bergmann2012-04-211-1/+1
| | | | | | | | | No driver should spin the CPU for 10ms, so better use an msleep, which is allowed in the ->suspend function. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* 8390: select CRC32 supportArnd Bergmann2012-04-211-0/+1
| | | | | | | | | The ax88796 driver uses the CRC32 functions, so make sure that they are actually enabled. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* drivers/net: iwmc3200 depends on EXPERIMENTALArnd Bergmann2012-04-212-2/+3
| | | | | | | | | | | The iwmc3200 driver selects other code in Kconfig that depends on EXPERIMENTAL. Kconfig warns about this when CONFIG_EXPERIMENTAL is not already set, so logically, these options should also be marked experimental or promoted to stable. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* caif: include linux/io.hArnd Bergmann2012-04-211-0/+4
| | | | | | | | | | | | | | | | | The caif_shmcore requires io.h in order to use ioremap, so include that explicitly to compile in all configurations. Also add a note about the use of ioremap(), which is not a proper way to map a DMA buffer into kernel space. It's not completely clear what the intention is for using ioremap, but it is clear that the result of ioremap must not simply be accessed using kernel pointers but should use readl/writel or memcopy_{to,from}io. Assigning the result of ioremap to a regular pointer that can also be set to something else is not ok. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* drivers/net: add missing __devexit_p() annotationsArnd Bergmann2012-04-213-3/+3
| | | | | | | | | | Drivers that refer to a __devexit function in an operations structure need to annotate that pointer with __devexit_p so replace it with a NULL pointer when the section gets discarded. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* davinci_cpdma: export symbols used by other driversArnd Bergmann2012-04-211-1/+12
| | | | | | | | | The davinci_emac driver can be a module, so the symbols it needs from the cpdma driver must be exported. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: remove suspicious commentRichard Cochran2012-04-211-1/+0
| | | | | | | | | | The time stamping code in this driver appears to have been copied from the ixp4xx_eth.c driver, including this timing comment. I had actually measured the time stamp delay on an IXP425, but I really doubt that this value also applies here. Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: run the ptp bpf just once per packetRichard Cochran2012-04-211-3/+1
| | | | | | | | | This patch fixes code which needlessly ran the BPF twice per packet. Instead, we just run the classifier once and test whether the packet is any kind of PTP event message. Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: correct receive time stamp filteringTakahiro Shimizu2012-04-212-4/+20
| | | | | | | | | | | | | This patch fixes the driver so that multicast PTP event messages can be recognized by the hardware time stamping unit. The station address register must be set according to the desired transport type. [ RC - Rebased Takahiro's changes and wrote a commit message explaining the changes. ] Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: do not set the channel control registerTakahiro Shimizu2012-04-211-2/+0
| | | | | | | | | | | | We will let the pch_gbe code do that according to the receive time stamp filter. [ RC - Rebased Takahiro's changes and wrote a commit message explaining the changes. ] Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: improve coding styleTakahiro Shimizu2012-04-211-9/+9
| | | | | | | | | | | | | | | This patch clears up a few coding style issues: - Makes two function definitions a bit nicer looking. - Remove unneeded parentheses. - Simplify macros for register bits. [ RC - Rebased Takahiro's changes and wrote a commit message explaining the changes. ] Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: export a method to set the receive match addressTakahiro Shimizu2012-04-212-1/+3
| | | | | | | | | | | | The code in phc_gbe_main will need to call this method in order to set the station address register according to the receive time stamping filter. [ RC - Rebased Takahiro's changes and wrote a commit message explaining the changes. ] Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: reprogram multicast address register on resetTakahiro Shimizu2012-04-211-3/+57
| | | | | | | | | | | | | The reset logic after a Rx FIFO overrun will clear the programmed multicast addresses. This patch fixes the issue by reprogramming the registers after the reset. [ RC - Rebased Takahiro's changes and wrote a commit message explaining the changes. ] Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: simplify transmit time stamping flag testTakahiro Shimizu2012-04-211-3/+3
| | | | | | | | | | | | This patch makes logic surrounding the test of the transmit time stamping flag more readable. [ RC - Rebased Takahiro's changes and wrote a commit message explaining the changes. ] Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* pch_gbe: scale time stamps to nanosecondsTakahiro Shimizu2012-04-212-4/+2
| | | | | | | | | | | | | This patch fixes the helper functions that give the transmit and receive time stamps to return nanoseconds, instead of arbitrary clock ticks. [ RC - Rebased Takahiro's changes and wrote a commit message explaining the changes. ] Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: Convert all sysctl registrations to register_net_sysctlEric W. Biederman2012-04-201-7/+1
| | | | | | | | | | | | This results in code with less boiler plate that is a bit easier to read. Additionally stops us from using compatibility code in the sysctl core, hastening the day when the compatibility code can be removed. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Acked-by: Pavel Emelyanov <xemul@parallels.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: Move all of the network sysctls without a namespace into init_net.Eric W. Biederman2012-04-201-2/+2
| | | | | | | | | | | | | | | | This makes it clearer which sysctls are relative to your current network namespace. This makes it a little less error prone by not exposing sysctls for the initial network namespace in other namespaces. This is the same way we handle all of our other network interfaces to userspace and I can't honestly remember why we didn't do this for sysctls right from the start. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Acked-by: Pavel Emelyanov <xemul@parallels.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: remove MDIO_REG_ADDR_MASK in atl1c_mdio_read/writeHuang, Xiong2012-04-191-2/+2
| | | | | | | | | MDIO_REG_ADDR_MASK is already applied in function atl1c_write_phy_reg and atl1c_read_phy_reg Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: fix WoL(magic) issue for l2cb 1.1Huang, Xiong2012-04-192-28/+52
| | | | | | | | | | l2cb 1.1 hardware has a bug for magic wakeup, the workaround is to add pattern enable. WoL related registers are refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: refine atl1c_pcie_patchHuang, Xiong2012-04-192-18/+48
| | | | | | | | | | | | | bit PCIE_PHYMISC_FORCE_RCV_DET is only for l1c&l2c to fix WoL issue, other chips set bit5 of REG_MASTER_CTRL --- this way could save more power than the former, and the bit should be kept all time. l2cb 1.x has special setting for L0S/L1 l2cb 1.x & l1d 1.x should clear Vendor Message on some platforms, otherwise it will cause the root complex hang. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: refine/update ASPM configurationHuang, Xiong2012-04-192-122/+111
| | | | | | | | | | | | | | | | | some platforms(BIOS or OS) may change ASPM configuration in PCI Express Link Control Register directly and dynamically regardless the device driver installation. Checking if ASPM support during the driver init phase by reading PCI Express Link Contrl Register doesn't make sense. This refine/update assume L0S/L1 is defalut enabled as hw->ctrl_flags inited. atl1c_set_aspm will set real configuration based on chip capability to hardware register. atl1c_disable_l0s_l1 and register definition of REG_PM_CTRL are refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patchHuang, Xiong2012-04-191-1/+6
| | | | | | | | | | bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend clear it after resume to enable pclk(PCIE clock) switch to low frequency(25M) in some circumstances to save power. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: refine reg definition of REG_MASTER_CTRLHuang, Xiong2012-04-192-19/+24
| | | | | | | | | refine/update register REG_MASTER_CTRL definition according with hardware spec. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: clear PCIE error status in atl1c_reset_pcieHuang, Xiong2012-04-192-17/+11
| | | | | | | | | | clear PCIE error status (error log is write-1-clear). REG_PCIE_UC_SEVERITY is removed as it's a standard pcie register, and using kernle API to access it. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: remove dmar_dly_cnt and dmaw_dly_cntHuang, Xiong2012-04-192-4/+0
| | | | | | | | dmar_dly_cnt and dmaw_dly_cnt aren't used by hardware/driver any more. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: update right threshold for TSOHuang, Xiong2012-04-193-5/+9
| | | | | | | | | | atl1c_configure_tx used a wrong value of MAX_TX_OFFLOAD_THRESH(9KB) for TSO threshold. the right value should be 7KB Fast Ethernet controller doesn't support Jumbo frame. Signed-off-by: xiong <xiong@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: add module parameter for l1c_wait_until_idleHuang, Xiong2012-04-192-15/+24
| | | | | | | | | | | | l1c_wait_until_idle is called for serval modules (TXQ/RXQ/TXMAC/RXMAC). specific moudle have specific idle/busy status in reg REG_IDLE_STATUS. the previous code return wrongly if all modules are in idle status, regardless the 'stop' action is applied on individual module. Refine the reg REG_IDLE_STATUS definition as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: threshold for ASPM is changed based on chip capabilityHuang, Xiong2012-04-191-3/+4
| | | | | | | | | | threshold setting to control ASPM for diff chips are different. currently, all gigabit-capability chips have limited-ASPM under 100M throughput. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* stmmac: do not fail when probe and there is no csr clk definedGiuseppe CAVALLARO2012-04-192-7/+11
| | | | | | | | | | | | On some platforms, for example where we are doing the bring-up, the csr clock is not passed from the framework and the Ethernet device driver is failing when it can work w/o any issues and using the default values. So this patch just warnings the case of the csr clock cannot be acquired but w/o failing the probe step. I have just tested it on ST STiH415 SoC (ARM). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* stmmac: verify the dma_cfg platform fieldsGiuseppe CAVALLARO2012-04-194-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the dma parameters that can be passed from the platform have been moved from the plat_stmmacenet_data to the stmmac_dma_cfg. In case of this new structure is not well allocated the driver can fails. This is an example how this field is managed in ST platforms static struct stmmac_dma_cfg gmac_dma_setting = { .pbl = 32, }; static struct plat_stmmacenet_data stih415_ethernet_platform_data[] = { { .dma_cfg = &gmac_dma_setting, .has_gmac = 1, [snip] This patch so verifies that the dma_cfg passed from the platform. In case of it is NULL there is no reason that the driver has to fail and some default values can be passed. These are ok for all the Synopsys chips and could impact on performances, only. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> cc: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* stmmac: Move the mdio_register/_unregister in probe/removeFrancesco Virlinzi2012-04-191-18/+16
| | | | | | | | | | This patch moves the mdio_register/_unregister in probe/remove functions and this also is required when hibernation on disk is done. Signed-off-by: Francesco Virlinzi <francesco.virlinzi@st,com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st,com> Signed-off-by: David S. Miller <davem@davemloft.net>
* stmmac: use custom init/exit functions in pm opsFrancesco Virlinzi2012-04-191-4/+13
| | | | | | | | | | | Freeze and restore can call the custom init/exit functions. Also the patch adds a custom data field that can be used for storing platform data useful on restore the embedded setup (e.g. GPIO, SYSCFG). Signed-off-by: Francesco Virlinzi <francesco.virlinzi@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* iwlwifi: Remove inconsistent and redundant declarationDavid Spinadel2012-04-191-1/+0
| | | | | | | | | | | | Remove declaration of iwl_alloc_traffic_mem from iwl-agn.h, from methods that was exposed to support MVM. MVM doesn't have to use this declaration. CC: netdev@vger.kernel.org Signed-off-by: David Spinadel <david.spinadel@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* bonding: start slaves with link down for ARP monitorMichal Kubeček2012-04-191-12/+21
| | | | | | | | | | | | | | | | | Initialize slave device link state as down if ARP monitor is active and net_carrier_ok() returns zero. Also shift initial value of its last_arp_tx so that it doesn't immediately cause fake detection of "up" state. When ARP monitoring is used, initializing the slave device with up link state can cause ARP monitor to detect link failure before the device is really up (with igb driver, this can take more than two seconds). Signed-off-by: Michal Kubecek <mkubecek@suse.cz> Signed-off-by: Jay Vosburgh <fubar@us.ibm.com> Signed-off-by: Flavio Leitner <fbl@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: restore max-read-request-size in Device Conrol RegisterHuang, Xiong2012-04-182-11/+11
| | | | | | | | | | | | | in some platforms, we found the max-read-request-size in Device Control Register is set to 0 by (BIOS?) during bootup, this will cause the performance(throughput) very bad. Restore it to a min-value. register definition of REG_DEVICE_CTRL is removed, using kernel API to access it as it's a standard pcie register. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: using fixed TXQ configuration for l2cb and l1cHuang, Xiong2012-04-182-19/+28
| | | | | | | | | | using fixed TXQ config for l2cb and l1c regardless dmar_block to make tx-DMA more stable. register REG_TXQ_CTRL is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: remove dmaw_blockHuang, Xiong2012-04-182-5/+0
| | | | | | | | dmaw_block is never used in the driver, remove it. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: correct wrong definition of REG_DMA_CTRLHuang, Xiong2012-04-182-43/+32
| | | | | | | | | | some fields of REG_DMA_CTRL(15C0) are wrong, replace with the newest one. haredware uses fixed dma-write-block size, remove dmaw_block related code in function atl1c_configure_dma. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: wrong register used to stop TXQHuang, Xiong2012-04-181-1/+1
| | | | | | | | | function atl1c_stop_mac uses wrong register of REG_TWSI_CTRL to stop mac, replace it with REG_TXQ_CTRL. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: remove code related to rxq 1/2/3Huang, Xiong2012-04-182-19/+13
| | | | | | | | | remove code related to rxq 1/2/3 since multi-q not support. refine REG_RXQ_CTRL definition as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: split 2 32bit registers of TPD to 4 16bit registersHuang, Xiong2012-04-183-39/+22
| | | | | | | | | | TPD producer/consumer index is 16bit wide. 16bit read/write reduce the dependency of the 2 tpd rings (hi and lo) rename reg(157C/1580) to keep name coninsistency. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: remove SMB/CMB DMA related codeHuang, Xiong2012-04-183-57/+6
| | | | | | | | | | l1c & later chips don't support DMA for SMB. CMB is removed from hardware. reg(15C8) is used to trig interrupt by tpd threshold. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* atl1c: remove VPD registerHuang, Xiong2012-04-183-16/+4
| | | | | | | | | | | VPD register is only used for L1(devid=PCI_DEVICE_ID_ATTANSIC_L1) to access external NV-memory. l1c & later chip doesn't use it any more. PHY 0/1 registers occupy the last 2 slots of the dump table. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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