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* remove unused flush_tlb_pgtablesBenjamin Herrenschmidt2007-10-191-7/+0
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-10-182-2/+14
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| * [MIPS] time: Move R4000 clockevent device code to separate configurable fileRalf Baechle2007-10-181-0/+6
| * [MIPS] time: Delete dead cycles_per_jiffy, mips_timer_ack and null_timer_ackRalf Baechle2007-10-181-1/+0
| * [MIPS] Always do the ARC64_TWIDDLE_PC thing.Thomas Bogendoerfer2007-10-181-1/+8
* | mips: lock bitopsNick Piggin2007-10-181-1/+96
* | mips: fix bitopsNick Piggin2007-10-181-0/+6
* | bitops: introduce lock opsNick Piggin2007-10-181-0/+1
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* [MIPS] Alchemy: Renumber interrupts so irq_cpu can work.Ralf Baechle2007-10-173-342/+373
* [MIPS] Alchemy: Fix build by conversion to irq_cpu.c.Ralf Baechle2007-10-171-4/+6
* Remove dma_cache_(wback|inv|wback_inv) functionsRalf Baechle2007-10-171-0/+2
* remove include/asm-*/ipc.hAdrian Bunk2007-10-171-1/+0
* cleanup floppy.hJan Beulich2007-10-171-2/+0
* remove strict ansi check from __u64 in asm/types.hOlaf Hering2007-10-171-3/+3
* kill DECLARE_MUTEX_LOCKEDChristoph Hellwig2007-10-171-1/+0
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-10-165-93/+129
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| * [MIPS] Alchemy: Get rid of au1xxx_irq_map_t.Ralf Baechle2007-10-161-3/+3
| * [MIPS] Alchemy: Get rid of au_ffz().Ralf Baechle2007-10-161-7/+0
| * [MIPS] Alchemy: Get rid of au_ffs().Ralf Baechle2007-10-161-10/+0
| * [MIPS] Lasat: Fix build by conversion to irq_cpu.c.Ralf Baechle2007-10-161-1/+4
| * [MIPS] Lasat: Add #ifndef ... #endif include warpper to lasatint.h.Ralf Baechle2007-10-161-0/+4
| * [MIPS] IP22: Fix warning.Ralf Baechle2007-10-161-2/+2
| * [MIPS] MSP71XX: Add workarounds file.Ralf Baechle2007-10-161-0/+28
| * [MIPS] IP32: Fix build by conversion to irq_cpu.c.Ralf Baechle2007-10-161-70/+88
* | move a few definitions to au1000_xxs1500.cYoichi Yuasa2007-10-161-35/+0
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* add new prom.h for AU1x00Yoichi Yuasa2007-10-151-0/+13
* [MIPS] CFE: Add missing parenthesis.Ralf Baechle2007-10-131-1/+1
* [MIPS] R1: Fix hazard barriers to make kernels work on R2 also.Ralf Baechle2007-10-111-1/+53
* [MIPS] Kill num_online_cpus() loops.Ralf Baechle2007-10-111-2/+2
* [MIPS] SMP: Implement smp_call_function_mask().Ralf Baechle2007-10-111-0/+9
* [MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle2007-10-111-0/+3
* [MIPS] Convert list of CPU types from #define to enum.Ralf Baechle2007-10-111-70/+49
* [MIPS] Optimize get_unaligned / put_unaligned implementations.Ralf Baechle2007-10-111-6/+21
* [MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle2007-10-1167-1726/+1726
* [MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle2007-10-1126-467/+467
* [MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle2007-10-111-1/+4
* [MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.cYoichi Yuasa2007-10-111-7/+0
* [MIPS] Cobalt: Move UART base definition to arch/mips/cobalt/console.cYoichi Yuasa2007-10-111-2/+0
* [MIPS] Cobalt: Move PCI definitions to arch/mips/pci/fixup-cobalt.c.Yoichi Yuasa2007-10-111-24/+2
* [MIPS] Optimize __alloc_zeroed_user_highpage implementation.Ralf Baechle2007-10-111-1/+1
* [MIPS] i8253 PIT clocksource and clockevent driversRalf Baechle2007-10-111-0/+30
* [MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle2007-10-113-6/+8
* [MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.Ralf Baechle2007-10-111-8/+8
* [MIPS] Switch from to_tm to rtc_time_to_tmRalf Baechle2007-10-111-7/+0
* [MIPS] Deforest the function pointer jungle in the time code.Ralf Baechle2007-10-112-10/+4
* [MIPS] ARC: Get rid of mips_machgroupRalf Baechle2007-10-111-27/+3
* [MIPS] Split up war.hRalf Baechle2007-10-1124-97/+625
* [MIPS] Add gpio support to the BCM47XX platformAurelien Jarno2007-10-111-0/+59
* [MIPS] Move ARC code into arch/mips/fw/arcAurelien Jarno2007-10-114-4/+4
* [MIPS] Move CFE code into arch/mips/fw/cfeAurelien Jarno2007-10-112-0/+270
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