summaryrefslogtreecommitdiffstats
path: root/include/linux/irq.h
Commit message (Collapse)AuthorAgeFilesLines
* genirq: Add chip flag to force mask on suspendThomas Gleixner2011-03-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On suspend we disable all interrupts in the core code, but this does not mask the interrupt line in the default implementation as we use a lazy disable approach. That means we mark the interrupt disabled, but leave the hardware unmasked. That's an optimization because we avoid the hardware access for the common case where no interrupt happens after we marked it disabled. If an interrupt happens, then the interrupt flow handler masks the line at the hardware level and marks it pending. Suspend makes use of this delayed disable as it "disables" all interrupts when preparing the suspend transition. Right before the system goes into hardware suspend state it checks whether one of the interrupts which is marked as a wakeup interrupt came in after disabling it. Most interrupt chips have a separate register which selects the interrupts which can wake up the system from suspend, so we don't have to mask any on the non wakeup interrupts. But now we have to deal with brilliant designed hardware which lacks such a wakeup configuration facility. For such hardware it's necessary to mask all non wakeup interrupts before going into suspend in order to avoid the wakeup from random interrupts. Rather than working around this in the affected interrupt chip implementations we can solve this elegant in the core code itself. Add a flag IRQCHIP_MASK_ON_SUSPEND which can be set by the irq chip implementation to indicate, that the interrupts which are not selected as wakeup sources must be masked in the suspend path. Mask them in the loop which checks the wakeup interrupts pending flag. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> LKML-Reference: <alpine.LFD.2.00.1103112112310.2787@localhost6.localdomain6>
* genirq: Implement irq_data based move_*_irq() versionsThomas Gleixner2011-02-191-0/+4
| | | | | | | No need to lookup the irq descriptor when calling from a chip callback function which has irq_data already handy. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq; Add fasteoi irq_chip quirkThomas Gleixner2011-02-191-1/+3
| | | | | | | | | Some chips want irq_eoi() only called when an interrupt is actually handled. So they have checks for INPROGRESS and DISABLED in their irq_eoi callbacks. Add a chip flag, which allows to handle that in the generic code. No impact on the fastpath. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Add preflow handler supportThomas Gleixner2011-02-191-1/+2
| | | | | | | | | sparc64 needs to call a preflow handler on certain interrupts befor calling the action chain. Integrate it into handle_fasteoi_irq. Must be enabled via CONFIG_IRQ_FASTEOI_PREFLOW. No impact when disabled. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: David S. Miller <davem@davemloft.net>
* genirq: Consolidate set_chip_handler functionsThomas Gleixner2011-02-191-12/+39
| | | | | | No need to have separate functions if we have one plus inline wrappers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Reflect IRQ_MOVE_PCNTXT in irq_data stateThomas Gleixner2011-02-191-0/+8
| | | | | | Required by x86. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move wakeup state to irq_dataThomas Gleixner2011-02-191-0/+8
| | | | | | | Some irq_chips need to know the state of wakeup mode for setting the trigger type etc. Reflect it in irq_data state. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Add IRQCHIP_SET_TYPE_MASKED flagThomas Gleixner2011-02-191-0/+9
| | | | | | | | | | irq_chips, which require to mask the chip before changing the trigger type should set this flag. So the core takes care of it and the requirement for looking into desc->status in the chip goes away. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Lars-Peter Clausen <lars@metafoo.de>
* genirq: Add flags to irq_chipThomas Gleixner2011-02-191-0/+3
| | | | | | | | | Looking through irq_chip implementations I noticed that some of them have special requirements, like setting the type masked and therefor fiddle in irq_desc->status. Add a flag field, so the core code can handle it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Cleanup irq.hThomas Gleixner2011-02-191-33/+62
| | | | | | Put the constants into an enum and document them. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Mirror irq trigger type bits in irq_data.stateThomas Gleixner2011-02-191-1/+25
| | | | | | | | | | | | | | | | | That's the data structure chip functions get provided. Also allow them to signal the core code that they updated the flags in irq_data.state by returning IRQ_SET_MASK_OK_NOCOPY. The default is unchanged. The type bits should be accessed via: val = irqd_get_trigger_type(irqdata); and irqd_set_trigger_type(irqdata, val); Coders who access them directly will be tracked down and slapped with stinking trouts. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_AFFINITY_SET to coreThomas Gleixner2011-02-191-1/+8
| | | | | | Keep status in sync until last abuser is gone. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Mirror IRQ_PER_CPU and IRQ_NO_BALANCING in irq_data.stateThomas Gleixner2011-02-191-1/+15
| | | | | | | | | | | | | | That's the right data structure to look at for arch code. Accessor functions are provided. irqd_is_per_cpu(irqdata); irqd_can_balance(irqdata); Coders who access them directly will be tracked down and slapped with stinking trouts. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Make CHECK_IRQ_PER_CPU an inline and deprecate itThomas Gleixner2011-02-191-2/+6
| | | | | | | | Its' too ugly and needs to go. The only users are core code and parisc. Core code does not need it and parisc gets a new check once IRQ_PER_CPU is reflected in irq_data.state. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Remove CONFIG_IRQ_PER_CPUThomas Gleixner2011-02-191-5/+0
| | | | | | | | The saving of this switch is minimal versus the ifdef mess it creates. Simple enable PER_CPU unconditionally and remove the config switch. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Add IRQ_MOVE_PENDING to irq_data.stateThomas Gleixner2011-02-191-2/+18
| | | | | | | | | | | | chip implementations need to know about it. Keep status in sync until all users are fixed. Accessor function: irqd_is_setaffinity_pending(irqdata) Coders who access them directly will be tracked down and slapped with stinking trouts. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Add state field to irq_dataThomas Gleixner2011-02-191-0/+3
| | | | | | | | | | | Some chip implementations need to access certain status flags. With sparse irqs that requires a lookup of the irq descriptor. Add a state field which contains such flags. Name it in a way which will make coders happy to access it with the proper accessor functions. And it's easy to grep for. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_SUSPENDED to coreThomas Gleixner2011-02-191-2/+0
| | | | | | No users outside of core. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_MASKED to coreThomas Gleixner2011-02-191-1/+1
| | | | | | Keep status in sync until all users are fixed. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_PENDING flag to coreThomas Gleixner2011-02-191-1/+1
| | | | | | Keep status in sync until all users are fixed. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_DISABLED to coreThomas Gleixner2011-02-191-2/+2
| | | | | | Keep status in sync until all abusers are fixed. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_REPLAY and IRQ_WAITING to coreThomas Gleixner2011-02-191-4/+5
| | | | | | No users outside of core. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_ONESHOT to coreThomas Gleixner2011-02-191-1/+0
| | | | | | No users outside of core. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Add IRQ_INPROGRESS to coreThomas Gleixner2011-02-191-1/+5
| | | | | | | | | | | | | We need to maintain the flag for now in both fields status and istate. Add a CONFIG_GENERIC_HARDIRQS_NO_COMPAT switch to allow testing w/o the status one. Wrap the access to status IRQ_INPROGRESS in a inline which can be turned of with CONFIG_GENERIC_HARDIRQS_NO_COMPAT along with the define. There is no reason that anything outside of core looks at this. That needs some modifications, but we'll get there. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_POLL_INPROGRESS to coreThomas Gleixner2011-02-191-1/+0
| | | | | | No users outside of core. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Use modify_status for set_irq_nested_threadThomas Gleixner2011-02-191-3/+13
| | | | | | No need for a separate function in the core code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_SPURIOUS_DISABLED to core stateThomas Gleixner2011-02-191-1/+0
| | | | | | No users outside. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Move IRQ_AUTODETECT to internal stateThomas Gleixner2011-02-191-1/+0
| | | | | | No users outside of core Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Mark polled irqs and defer the real handlerThomas Gleixner2011-02-191-0/+1
| | | | | | | | | | | | | | With the chip.end() function gone we might run into a situation where a poll call runs and the real interrupt comes in, sees IRQ_INPROGRESS and disables the line. That might be a perfect working one, which will then be masked forever. So mark them polled while the poll runs. When the real handler sees IRQ_INPROGRESS it checks the poll flag and waits for the polling to complete. Add the necessary amount of sanity checks to it to avoid deadlocks. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Do not copy affinity before setThomas Gleixner2011-02-191-0/+11
| | | | | | | | | | | | | | | | While rumaging through arch code I found that there are a few workarounds which deal with the fact that the initial affinity setting from request_irq() copies the mask into irq_data->affinity before the chip code is called. In the normal path we unconditionally copy the mask when the chip code returns 0. Copy after the code is called and add a return code IRQ_SET_MASK_OK_NOCOPY for the chip functions, which prevents the copy. That way we see the real mask when the chip function decided to truncate it further as some arches do. IRQ_SET_MASK_OK is 0, which is the current behaviour. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Namespace cleanupThomas Gleixner2011-02-191-14/+65
| | | | | | | | | | | | | | | | The irq namespace has become quite convoluted. My bad. Clean it up and deprecate the old functions. All new functions follow the scheme: irq number based: irq_set/get/xxx/_xxx(unsigned int irq, ...) irq_data based: irq_data_set/get/xxx/_xxx(struct irq_data *d, ....) irq_desc based: irq_desc_get_xxx(struct irq_desc *desc) Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Add missing status flags to modification maskThomas Gleixner2011-02-051-1/+2
| | | | | | | | | The mask which filters out the valid bits which can be set via irq_modify_status() is missing IRQ_NO_BALANCING, which breaks UV. Add IRQ_PER_CPU as well to avoid another one line patch for 39. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Add single IRQ reservation helperPaul Mundt2010-10-261-0/+5
| | | | | | | | | | For cases that wish to reserve a single IRQ at a given place simply provide a wrapper in to the ranged reservation routine. Signed-off-by: Paul Mundt <lethal@linux-sh.org> LKML-Reference: <20101026071912.GD4733@linux-sh.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Sanitize dynamic irq handlingThomas Gleixner2010-10-121-4/+8
| | | | | | | | Use the cleanup functions of the dynamic allocator. No need to have separate implementations. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Remove irq_2_iommuThomas Gleixner2010-10-121-18/+0
| | | | | | | | | | | irq_2_iommu is now in the x86 code where it belongs. Remove all leftovers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
* genirq: Query arch for number of early descriptorsThomas Gleixner2010-10-121-0/+4
| | | | | | | | | | | sparse irq sets up NR_IRQS_LEGACY irq descriptors and archs then go ahead and allocate more. Use the unused return value of arch_probe_nr_irqs() to let the architecture return the number of early allocations. Fix up all users. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Implement irq reservationThomas Gleixner2010-10-121-0/+1
| | | | | | | | Mark a range of interrupts as allocated. In the SPARSE_IRQ=n case we need this to update the bitmap for the legacy irqs so the enumerator via irq_get_next_irq() works. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* genirq: Implement a sane sparse_irq allocatorThomas Gleixner2010-10-121-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current sparse_irq allocator has several short comings due to failures in the design or the lack of it: - Requires iteration over the number of active irqs to find a free slot (Some architectures have grown their own workarounds for this) - Removal of entries is not possible - Racy between create_irq_nr and destroy_irq (plugged by horrible callbacks) - Migration of active irq descriptors is not possible - No bulk allocation of irq ranges - Sprinkeled irq_desc references all over the place outside of kernel/irq/ (The previous chip functions series is addressing this issue) Implement a sane allocator which fixes the above short comings (though migration of active descriptors needs a full tree wide cleanup of the direct and mostly unlocked access to irq_desc). The new allocator still uses a radix_tree, but uses a bitmap for keeping track of allocated irq numbers. That allows: - Fast lookup of a free slot - Allows the removal of descriptors - Prevents the create/destroy race - Bulk allocation of consecutive irq ranges - Basic design is ready for migration of life descriptors after further cleanups The bitmap is also used in the SPARSE_IRQ=n case for lookup and raceless (de)allocation of irq numbers. So it removes the requirement for looping through the descriptor array to find slots. Right now it uses sparse_irq_lock to protect the bitmap and the radix tree, but after cleaning up all users we should be able convert that to a mutex and to switch the radix_tree and decriptor allocations to GFP_KERNEL. [ Folded in a bugfix from Yinghai Lu ] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Provide default irq init flagsThomas Gleixner2010-10-121-0/+6
| | | | | | | | | | | | Arch code sets it's own irq_desc.status flags right after boot and for dynamically allocated interrupts. That might involve iterating over a huge array. Allow ARCH_IRQ_INIT_FLAGS to set separate flags aside of IRQ_DISABLED which is the default. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Sanitize irq_data accessorsThomas Gleixner2010-10-121-4/+58
| | | | | | | | | | Get the data structure from the core and provide inline wrappers to access the irq_data members. Provide accessor inlines for irq_data as well. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Provide status modifierThomas Gleixner2010-10-121-2/+25
| | | | | | | | | Provide a irq_desc.status modifier function to cleanup the direct access to irq_desc in arch and driver code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Remove unsused inlineThomas Gleixner2010-10-121-7/+1
| | | | | | | move_irq() has no users. Remove it and simplify the ifdef forrest while at it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Distangle irq.hThomas Gleixner2010-10-121-279/+13
| | | | | | | Move irq_desc and internal functions out of irq.h Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Provide config option to disable deprecated codeThomas Gleixner2010-10-041-1/+7
| | | | | | | | | | This option covers now the old chip functions and the irq_desc data fields which are moving to struct irq_data. More stuff will follow. Pretty handy for testing a conversion, whether something broke or not. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Provide advanced irq chip functionsThomas Gleixner2010-10-041-16/+50
| | | | | | | | | | | | | | | | | | | | | | The low level irq chip functions want access to irq_desc->irq_data. Provide new functions which hand down irq_data instead of the irq number so these functions avoid to call irq_to_desc() which is a radix tree lookup in case of sparse irq. This provides all the old functions except one: end(). end() is a relict of __do_IRQ() and will just go away with the __do_IRQ() code. The replacement for set_affinity() has an extra argument "bool force". The reason for this is to notify the low level code, that the move has to be done right away and cannot be delayed until the next interrupt happens. That's necessary to handle the irq fixup on cpu unplug in the generic code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> LKML-Reference: <20100927121841.742126604@linutronix.de> Reviewed-by: H. Peter Anvin <hpa@zytor.com> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Convert core code to irq_dataThomas Gleixner2010-10-041-5/+5
| | | | | | | | Convert all references in the core code to orq, chip, handler_data, chip_data, msi_desc, affinity to irq_data.* Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Create irq_dataThomas Gleixner2010-10-041-27/+63
| | | | | | | | | | | | | | | | | | | | | | Low level chip functions need access to irq_desc->handler_data, irq_desc->chip_data and irq_desc->msi_desc. We hand down the irq number to the low level functions, so they need to lookup irq_desc. With sparse irq this means a radix tree lookup. We could hand down irq_desc itself, but low level chip functions have no need to fiddle with it directly and we want to restrict access to irq_desc further. Preparatory patch for new chip functions. Note, that the ugly anon union/struct is there to avoid a full tree wide clean up for now. This is not going to last 3 years like __do_IRQ() Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> LKML-Reference: <20100927121841.645542300@linutronix.de> Reviewed-by: H. Peter Anvin <hpa@zytor.com> Reviewed-by: Ingo Molnar <mingo@elte.hu>
* genirq: Cleanup irq_chip->typename leftoversThomas Gleixner2010-09-231-6/+0
| | | | | | | | | | | | 3 years transition phase is enough. Cleanup the last users and remove the cruft. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Leo Chen <leochen@broadcom.com> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Jeff Dike <jdike@addtoit.com> Cc: Chris Zankel <chris@zankel.net>
* genirq: Add CPU mask affinity hintPeter P Waskiewicz Jr2010-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch adds a cpumask affinity hint to the irq_desc structure, along with a registration function and a read-only proc entry for each interrupt. This affinity_hint handle for each interrupt can be used by underlying drivers that need a better mechanism to control interrupt affinity. The underlying driver can register a cpumask for the interrupt, which will allow the driver to provide the CPU mask for the interrupt to anything that requests it. The intent is to extend the userspace daemon, irqbalance, to help hint to it a preferred CPU mask to balance the interrupt into. [ tglx: Fixed compile warnings, added WARN_ON, made SMP only ] Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Cc: davem@davemloft.net Cc: arjan@linux.jf.intel.com Cc: bhutchings@solarflare.com LKML-Reference: <20100430214445.3992.41647.stgit@ppwaskie-hc2.jf.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* Merge branch 'x86-apic-for-linus' of ↵Linus Torvalds2010-03-031-0/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (25 commits) x86: Fix out of order of gsi x86: apic: Fix mismerge, add arch_probe_nr_irqs() again x86, irq: Keep chip_data in create_irq_nr and destroy_irq xen: Remove unnecessary arch specific xen irq functions. smp: Use nr_cpus= to set nr_cpu_ids early x86, irq: Remove arch_probe_nr_irqs sparseirq: Use radix_tree instead of ptrs array sparseirq: Change irq_desc_ptrs to static init: Move radix_tree_init() early irq: Remove unnecessary bootmem code x86: Add iMac9,1 to pci_reboot_dmi_table x86: Convert i8259_lock to raw_spinlock x86: Convert nmi_lock to raw_spinlock x86: Convert ioapic_lock and vector_lock to raw_spinlock x86: Avoid race condition in pci_enable_msix() x86: Fix SCI on IOAPIC != 0 x86, ia32_aout: do not kill argument mapping x86, irq: Move __setup_vector_irq() before the first irq enable in cpu online path x86, irq: Update the vector domain for legacy irqs handled by io-apic x86, irq: Don't block IRQ0_VECTOR..IRQ15_VECTOR's on all cpu's ...
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-07 06:13:18 +0000