From 3c09bae43ba92a07a6a7b7d42360deb32d289cc0 Mon Sep 17 00:00:00 2001 From: Chen Jie Date: Fri, 15 Aug 2014 16:56:58 +0800 Subject: MIPS: Use WSBH/DSBH/DSHD on Loongson 3A Signed-off-by: chenj Cc: linux-mips@linux-mips.org Cc: chenhc@lemote.com Patchwork: https://patchwork.linux-mips.org/patch/7542/ Patchwork: https://patchwork.linux-mips.org/patch/7550/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu-features.h | 10 ++++++++++ .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 + .../include/asm/mach-loongson/cpu-feature-overrides.h | 2 ++ arch/mips/include/uapi/asm/swab.h | 18 ++++++++++++++---- arch/mips/lib/csum_partial.S | 10 ++++++++-- arch/mips/net/bpf_jit.c | 2 +- 6 files changed, 36 insertions(+), 7 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index e079598ae051..3325f3eb248c 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -231,6 +231,16 @@ #define cpu_has_clo_clz cpu_has_mips_r #endif +/* + * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. + * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. + * This indicates the availability of WSBH and in case of 64 bit CPUs also + * DSBH and DSHD. + */ +#ifndef cpu_has_wsbh +#define cpu_has_wsbh cpu_has_mips_r2 +#endif + #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index cf8022872892..fa1f3cfbae8d 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -57,6 +57,7 @@ #define cpu_has_vint 0 #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 +#define cpu_has_wsbh 1 #define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index c0f3ef45c2c1..7d28f95b0512 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -59,4 +59,6 @@ #define cpu_has_watch 1 #define cpu_has_local_ebase 0 +#define cpu_has_wsbh IS_ENABLED(CONFIG_CPU_LOONGSON3) + #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h index ac9a8f9cd1fb..8f2d184dbe9f 100644 --- a/arch/mips/include/uapi/asm/swab.h +++ b/arch/mips/include/uapi/asm/swab.h @@ -13,12 +13,16 @@ #define __SWAB_64_THRU_32__ -#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) +#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ + defined(_MIPS_ARCH_LOONGSON3A) static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { __asm__( + " .set push \n" + " .set arch=mips32r2 \n" " wsbh %0, %1 \n" + " .set pop \n" : "=r" (x) : "r" (x)); @@ -29,8 +33,11 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x) static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { __asm__( + " .set push \n" + " .set arch=mips32r2 \n" " wsbh %0, %1 \n" " rotr %0, %0, 16 \n" + " .set pop \n" : "=r" (x) : "r" (x)); @@ -46,8 +53,11 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) static inline __attribute_const__ __u64 __arch_swab64(__u64 x) { __asm__( - " dsbh %0, %1\n" - " dshd %0, %0" + " .set push \n" + " .set arch=mips64r2 \n" + " dsbh %0, %1 \n" + " dshd %0, %0 \n" + " .set pop \n" : "=r" (x) : "r" (x)); @@ -55,5 +65,5 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x) } #define __arch_swab64 __arch_swab64 #endif /* __mips64 */ -#endif /* MIPS R2 or newer */ +#endif /* MIPS R2 or newer or Loongson 3A */ #endif /* _ASM_SWAB_H */ diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S index 9901237563c5..4c721e247ac9 100644 --- a/arch/mips/lib/csum_partial.S +++ b/arch/mips/lib/csum_partial.S @@ -277,9 +277,12 @@ LEAF(csum_partial) #endif /* odd buffer alignment? */ -#ifdef CONFIG_CPU_MIPSR2 +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3) + .set push + .set arch=mips32r2 wsbh v1, sum movn sum, v1, t7 + .set pop #else beqz t7, 1f /* odd buffer alignment? */ lui v1, 0x00ff @@ -726,9 +729,12 @@ LEAF(csum_partial) addu sum, v1 #endif -#ifdef CONFIG_CPU_MIPSR2 +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3) + .set push + .set arch=mips32r2 wsbh v1, sum movn sum, v1, odd + .set pop #else beqz odd, 1f /* odd buffer alignment? */ lui v1, 0x00ff diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c index 9f7ecbda250c..ae8cc8477389 100644 --- a/arch/mips/net/bpf_jit.c +++ b/arch/mips/net/bpf_jit.c @@ -1263,7 +1263,7 @@ jmp_cmp: emit_half_load(r_A, r_skb, off, ctx); #ifdef CONFIG_CPU_LITTLE_ENDIAN /* This needs little endian fixup */ - if (cpu_has_mips_r2) { + if (cpu_has_wsbh) { /* R2 and later have the wsbh instruction */ emit_wsbh(r_A, r_A, ctx); } else { -- cgit v1.2.3 From 092ea4660808cd441ccf3d415b80665dbe8712f4 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 20 Aug 2014 21:36:30 +0200 Subject: MIPS: Alchemy: devboards: sit and spin after poweroff On boards which don't support poweroff, systemd complains about this fact. In case poweroff fails, just sit and spin in the wait loop. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Cc: Manuel Lauss Patchwork: https://patchwork.linux-mips.org/patch/7558/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/platform.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c index 8df86eb94972..be139a0198b0 100644 --- a/arch/mips/alchemy/devboards/platform.c +++ b/arch/mips/alchemy/devboards/platform.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -53,6 +54,8 @@ static void db1x_power_off(void) { bcsr_write(BCSR_RESETS, 0); bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET); + while (1) /* sit and spin */ + cpu_wait(); } static void db1x_reset(char *c) -- cgit v1.2.3 From 7ec32e4965ae69976de0fb0f340496904e23e113 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 20 Aug 2014 21:36:31 +0200 Subject: MIPS: Alchemy: Update cpu-feature-overrides More features the Au1 core definitely doesn't have. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/7562/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h index 09f45e6afade..c5b6eef0efa7 100644 --- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h @@ -8,6 +8,12 @@ #define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H #define cpu_has_tlb 1 +#define cpu_has_tlbinv 0 +#define cpu_has_segments 0 +#define cpu_has_eva 0 +#define cpu_has_htw 0 +#define cpu_has_rixiex 0 +#define cpu_has_maar 0 #define cpu_has_4kex 1 #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 1 @@ -28,6 +34,8 @@ #define cpu_has_mdmx 0 #define cpu_has_mips3d 0 #define cpu_has_smartmips 0 +#define cpu_has_rixi 0 +#define cpu_has_mmips 0 #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 1 @@ -50,4 +58,8 @@ #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 +#define cpu_has_perf_cntr_intr_bit 0 +#define cpu_has_vz 0 +#define cpu_has_msa 0 + #endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */ -- cgit v1.2.3 From c02a505e5a7787ee7aa871152ba571e6c1d1dc62 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 20 Aug 2014 21:36:32 +0200 Subject: MIPS: Alchemy: DB1xxx: Explicitly set 50MHz clock for I2C/SPI units. Add an explicit call to set the desired rate to get the correct clock routing for the PSC clocks. It wasn't broken before, but now it's less affected by bootloader changes. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/7554/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/db1300.c | 3 ++- arch/mips/alchemy/devboards/db1550.c | 9 ++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index ef93ee3f6a2c..e476ae9472b9 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -762,9 +762,10 @@ int __init db1300_dev_setup(void) __raw_writel(PSC_SEL_CLK_SERCLK, (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); - /* I2C uses internal 48MHz EXTCLK1 */ + /* I2C driver wants 50MHz, get as close as possible */ c = clk_get(NULL, "psc3_intclk"); if (!IS_ERR(c)) { + clk_set_rate(c, 50000000); clk_prepare_enable(c); clk_put(c); } diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c index 7e89936f763e..0fd5177e35ab 100644 --- a/arch/mips/alchemy/devboards/db1550.c +++ b/arch/mips/alchemy/devboards/db1550.c @@ -34,12 +34,9 @@ static void __init db1550_hw_setup(void) void __iomem *base; unsigned long v; - /* complete SPI setup: link psc0_intclk to a 48MHz source, - * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) as well as PSC1_SYNC - * for AC97 on PB1550. + /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line) + * as well as PSC1_SYNC for AC97 on PB1550. */ - v = alchemy_rdsys(AU1000_SYS_CLKSRC); - alchemy_wrsys(v | 0x000001e0, AU1000_SYS_CLKSRC); v = alchemy_rdsys(AU1000_SYS_PINFUNC); alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC); @@ -586,11 +583,13 @@ int __init db1550_dev_setup(void) c = clk_get(NULL, "psc0_intclk"); if (!IS_ERR(c)) { + clk_set_rate(c, 50000000); clk_prepare_enable(c); clk_put(c); } c = clk_get(NULL, "psc2_intclk"); if (!IS_ERR(c)) { + clk_set_rate(c, db1550_spi_platdata.mainclk_hz); clk_prepare_enable(c); clk_put(c); } -- cgit v1.2.3 From c64bb5f0c26f6ea791270852217b7cb28553ba76 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 20 Aug 2014 21:36:33 +0200 Subject: MIPS: Alchemy: DB1300: Add touch penirq support wire up the WM9713 pendown irq support. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/7563/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/db1300.c | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index e476ae9472b9..1c64fdbe4c81 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -711,6 +712,46 @@ static struct platform_device db1300_lcd_dev = { /**********************************************************************/ +static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable) +{ + if (enable) + enable_irq(DB1300_AC97_PEN_INT); + else + disable_irq_nosync(DB1300_AC97_PEN_INT); +} + +static struct wm97xx_mach_ops db1300_wm97xx_ops = { + .irq_enable = db1300_wm97xx_irqen, + .irq_gpio = WM97XX_GPIO_3, +}; + +static int db1300_wm97xx_probe(struct platform_device *pdev) +{ + struct wm97xx *wm = platform_get_drvdata(pdev); + + /* external pendown indicator */ + wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN, + WM97XX_GPIO_POL_LOW, WM97XX_GPIO_STICKY, + WM97XX_GPIO_WAKE); + + /* internal "virtual" pendown gpio */ + wm97xx_config_gpio(wm, WM97XX_GPIO_3, WM97XX_GPIO_OUT, + WM97XX_GPIO_POL_LOW, WM97XX_GPIO_NOTSTICKY, + WM97XX_GPIO_NOWAKE); + + wm->pen_irq = DB1300_AC97_PEN_INT; + + return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops); +} + +static struct platform_driver db1300_wm97xx_driver = { + .driver.name = "wm97xx-touch", + .driver.owner = THIS_MODULE, + .probe = db1300_wm97xx_probe, +}; + +/**********************************************************************/ + static struct platform_device *db1300_dev[] __initdata = { &db1300_eth_dev, &db1300_i2c_dev, @@ -755,6 +796,9 @@ int __init db1300_dev_setup(void) i2c_register_board_info(0, db1300_i2c_devs, ARRAY_SIZE(db1300_i2c_devs)); + if (platform_driver_register(&db1300_wm97xx_driver)) + pr_warn("DB1300: failed to init touch pen irq support!\n"); + /* Audio PSC clock is supplied by codecs (PSC1, 2) */ __raw_writel(PSC_SEL_CLK_SERCLK, (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); -- cgit v1.2.3 From ff848c9f359ba4de478c01886d3664cd768defed Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Tue, 8 Apr 2014 16:09:02 +0100 Subject: MIPS: SEAD3: Regenerate defconfigs This is similar to a86dc812881fab40175f4d3c3028acf8627a3804 "MIPS: Regenerate malta defconfigs" Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6737/ Signed-off-by: Ralf Baechle --- arch/mips/configs/sead3_defconfig | 1 - arch/mips/configs/sead3micro_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/mips/configs/sead3_defconfig b/arch/mips/configs/sead3_defconfig index 0abe681c11a0..364649816e12 100644 --- a/arch/mips/configs/sead3_defconfig +++ b/arch/mips/configs/sead3_defconfig @@ -32,7 +32,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y diff --git a/arch/mips/configs/sead3micro_defconfig b/arch/mips/configs/sead3micro_defconfig index 2a0da5bf4b64..60bc0942bc37 100644 --- a/arch/mips/configs/sead3micro_defconfig +++ b/arch/mips/configs/sead3micro_defconfig @@ -33,7 +33,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y -- cgit v1.2.3 From bfe0307942366b729520718b1ddcd96fb9bd5391 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Tue, 8 Apr 2014 16:09:03 +0100 Subject: MIPS: SEAD3: Enable DEVTMPFS This is similar to 68f30ba7f8b9d666d1218eec97822ade0f23d9c3 "MIPS: Malta: Enable DEVTMPFS" Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6738/ Signed-off-by: Ralf Baechle --- arch/mips/configs/sead3_defconfig | 1 + arch/mips/configs/sead3micro_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/mips/configs/sead3_defconfig b/arch/mips/configs/sead3_defconfig index 364649816e12..dae9354b6256 100644 --- a/arch/mips/configs/sead3_defconfig +++ b/arch/mips/configs/sead3_defconfig @@ -31,6 +31,7 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/mips/configs/sead3micro_defconfig b/arch/mips/configs/sead3micro_defconfig index 60bc0942bc37..cd91a775c74e 100644 --- a/arch/mips/configs/sead3micro_defconfig +++ b/arch/mips/configs/sead3micro_defconfig @@ -32,6 +32,7 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y -- cgit v1.2.3 From 7fafb06831431ed7bc882c3cd7c981e3f41cfdb0 Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Thu, 21 Aug 2014 13:04:20 -0700 Subject: MIPS: Create common infrastructure for building built-in device-trees In preparation for moving the device-trees to a common location, introduce the config option BUILTIN_DTB, which can be selected by platforms that use a device-tree built into the kernel image, and create a Makefile to build the device-trees in arch/mips/boot/dts/. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: James Hogan Cc: Paul Burton Cc: David Daney Cc: John Crispin Cc: Jayachandran C Cc: Qais Yousef Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7564/ Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 +++ arch/mips/Makefile | 6 ++++++ arch/mips/boot/dts/Makefile | 3 +++ 3 files changed, 12 insertions(+) create mode 100644 arch/mips/boot/dts/Makefile diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 574c43000699..8a2663d806c9 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2482,6 +2482,9 @@ config USE_OF select OF_EARLY_FLATTREE select IRQ_DOMAIN +config BUILTIN_DTB + bool + endmenu config LOCKDEP_SUPPORT diff --git a/arch/mips/Makefile b/arch/mips/Makefile index bbac51e11179..bd642623f360 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -333,6 +333,12 @@ endif CLEAN_FILES += vmlinux.32 vmlinux.64 +# device-trees +core-$(CONFIG_BUILTIN_DTB) += arch/mips/boot/dts/ + +%.dtb %.dtb.S %.dtb.o: | scripts + $(Q)$(MAKE) $(build)=arch/mips/boot/dts arch/mips/boot/dts/$@ + archprepare: ifdef CONFIG_MIPS32_N32 @echo ' Checking missing-syscalls for N32' diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile new file mode 100644 index 000000000000..6bb41df59264 --- /dev/null +++ b/arch/mips/boot/dts/Makefile @@ -0,0 +1,3 @@ +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) + +clean-files += *.dtb.S -- cgit v1.2.3 From c8d333dfe4bab898fd87f4c3ae555f2c1388eb8f Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Thu, 21 Aug 2014 13:04:21 -0700 Subject: MIPS: Add support for building device-tree binaries Add a 'dtbs' Makefile target that just builds the device-tree binaries enabled by the configuration. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: James Hogan Cc: Paul Burton Cc: David Daney Cc: John Crispin Cc: Jayachandran C Cc: Qais Yousef Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7557/ Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 5 +++++ arch/mips/boot/.gitignore | 1 + arch/mips/boot/dts/Makefile | 7 ++++++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index bd642623f360..23cb94806fbc 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -339,6 +339,10 @@ core-$(CONFIG_BUILTIN_DTB) += arch/mips/boot/dts/ %.dtb %.dtb.S %.dtb.o: | scripts $(Q)$(MAKE) $(build)=arch/mips/boot/dts arch/mips/boot/dts/$@ +PHONY += dtbs +dtbs: scripts + $(Q)$(MAKE) $(build)=arch/mips/boot/dts dtbs + archprepare: ifdef CONFIG_MIPS32_N32 @echo ' Checking missing-syscalls for N32' @@ -373,6 +377,7 @@ define archhelp echo ' vmlinuz.srec - SREC zboot image' echo ' uImage - U-Boot image' echo ' uImage.gz - U-Boot image (gzip)' + echo ' dtbs - Device-tree blobs for enabled boards' echo echo ' These will be default as appropriate for a configured platform.' endef diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore index a73d6e2c4f64..d3962cd5ce0c 100644 --- a/arch/mips/boot/.gitignore +++ b/arch/mips/boot/.gitignore @@ -5,3 +5,4 @@ zImage zImage.tmp calc_vmlinuz_load_addr uImage +*.dtb diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 6bb41df59264..9b3da1f4bc6d 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -1,3 +1,8 @@ obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) -clean-files += *.dtb.S +targets += dtbs +targets += $(dtb-y) + +dtbs: $(addprefix $(obj)/, $(dtb-y)) + +clean-files += *.dtb *.dtb.S -- cgit v1.2.3 From e326479f2f5767be3341c305a4457c4a1405e5a7 Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Thu, 21 Aug 2014 13:04:22 -0700 Subject: MIPS: Octeon: Move device-trees to arch/mips/boot/dts/ Move the Octeon device-trees to arch/mips/boot/dts/ and update the Makefiles accordingly. Since Octeon requires the device-tree to be built into the kernel, select BUILTIN_DTB as well. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: James Hogan Cc: Paul Burton Cc: David Daney Cc: John Crispin Cc: Jayachandran C Cc: Qais Yousef Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7556/ Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 1 + arch/mips/boot/dts/Makefile | 2 + arch/mips/boot/dts/octeon_3xxx.dts | 590 ++++++++++++++++++++++++++++++ arch/mips/boot/dts/octeon_68xx.dts | 625 ++++++++++++++++++++++++++++++++ arch/mips/cavium-octeon/.gitignore | 2 - arch/mips/cavium-octeon/Makefile | 10 - arch/mips/cavium-octeon/octeon_3xxx.dts | 590 ------------------------------ arch/mips/cavium-octeon/octeon_68xx.dts | 625 -------------------------------- 8 files changed, 1218 insertions(+), 1227 deletions(-) create mode 100644 arch/mips/boot/dts/octeon_3xxx.dts create mode 100644 arch/mips/boot/dts/octeon_68xx.dts delete mode 100644 arch/mips/cavium-octeon/.gitignore delete mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts delete mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8a2663d806c9..a77ba5b81f61 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -742,6 +742,7 @@ config CAVIUM_OCTEON_SOC select ARCH_SPARSEMEM_ENABLE select SYS_SUPPORTS_SMP select NR_CPUS_DEFAULT_16 + select BUILTIN_DTB help This option supports all of the Octeon reference boards from Cavium Networks. It builds a kernel that dynamically determines the Octeon diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 9b3da1f4bc6d..51acad699ed0 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -1,3 +1,5 @@ +dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb + obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) targets += dtbs diff --git a/arch/mips/boot/dts/octeon_3xxx.dts b/arch/mips/boot/dts/octeon_3xxx.dts new file mode 100644 index 000000000000..fa33115bde33 --- /dev/null +++ b/arch/mips/boot/dts/octeon_3xxx.dts @@ -0,0 +1,590 @@ +/dts-v1/; +/* + * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-3860"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>, <0 17>, <0 18>, <0 19>, + <0 20>, <0 21>, <0 22>, <0 23>, + <0 24>, <0 25>, <0 26>, <0 27>, + <0 28>, <0 29>, <0 30>, <0 31>; + }; + + smi0: mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + phy0: ethernet-phy@0 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000001900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + + phy100: ethernet-phy@1 { + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy101: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy102: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy103: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <0 62>, <1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + mix1: ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + cavium,alt-phy-handle = <&phy100>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + cavium,alt-phy-handle = <&phy101>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + cavium,alt-phy-handle = <&phy102>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy5>; + cavium,alt-phy-handle = <&phy103>; + }; + ethernet@4 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x4>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@5 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x5>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@6 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x6>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@7 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x7>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@8 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x8>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@9 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x9>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@a { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xa>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@b { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xb>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@c { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xc>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@d { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xd>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@e { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xe>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@f { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xf>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy6>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy7>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy8>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy9>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <0 59>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 34>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 35>; + }; + + uart2: serial@1180000000400 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000400 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <1 16>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0x0 0x1d020000 0x10000>, + <5 0 0x0 0x1d040000 0x10000>, + <6 0 0x0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <20>; + cavium,t-ce = <60>; + cavium,t-oe = <60>; + cavium,t-we = <45>; + cavium,t-rd-hld = <35>; + cavium,t-wr-hld = <45>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <35>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <270>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <70>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + led0: led-display@4,0 { + compatible = "avago,hdsp-253x"; + reg = <4 0x20 0x20>, <4 0 0x20>; + }; + + cf0: compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + + usbn: usbn@1180068000000 { + compatible = "cavium,octeon-5750-usbn"; + reg = <0x11800 0x68000000 0x0 0x1000>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + usbc@16f0010000000 { + compatible = "cavium,octeon-5750-usbc"; + reg = <0x16f00 0x10000000 0x0 0x80000>; + interrupts = <0 56>; + }; + }; + }; + + aliases { + mix0 = &mix0; + mix1 = &mix1; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + flash0 = &flash0; + cf0 = &cf0; + uctl = &uctl; + usbn = &usbn; + led0 = &led0; + }; + }; diff --git a/arch/mips/boot/dts/octeon_68xx.dts b/arch/mips/boot/dts/octeon_68xx.dts new file mode 100644 index 000000000000..79b46fcb0a11 --- /dev/null +++ b/arch/mips/boot/dts/octeon_68xx.dts @@ -0,0 +1,625 @@ +/dts-v1/; +/* + * OCTEON 68XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-6880"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu2>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu2: interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 7) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pins connect to 16 consecutive CUI bits */ + interrupts = <7 0>, <7 1>, <7 2>, <7 3>, + <7 4>, <7 5>, <7 6>, <7 7>, + <7 8>, <7 9>, <7 10>, <7 11>, + <7 12>, <7 13>, <7 14>, <7 15>; + }; + + smi0: mdio@1180000003800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003800 0x0 0x40>; + + phy0: ethernet-phy@6 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <6>; + }; + + phy1: ethernet-phy@1 { + cavium,qlm-trim = "4,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy2: ethernet-phy@2 { + cavium,qlm-trim = "4,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + cavium,qlm-trim = "4,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + cavium,qlm-trim = "4,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000003880 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003880 0x0 0x40>; + + phy41: ethernet-phy@1 { + cavium,qlm-trim = "0,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy42: ethernet-phy@2 { + cavium,qlm-trim = "0,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy43: ethernet-phy@3 { + cavium,qlm-trim = "0,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy44: ethernet-phy@4 { + cavium,qlm-trim = "0,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi2: mdio@1180000003900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003900 0x0 0x40>; + + phy21: ethernet-phy@1 { + cavium,qlm-trim = "2,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy22: ethernet-phy@2 { + cavium,qlm-trim = "2,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy23: ethernet-phy@3 { + cavium,qlm-trim = "2,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy24: ethernet-phy@4 { + cavium,qlm-trim = "2,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi3: mdio@1180000003980 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003980 0x0 0x40>; + + phy11: ethernet-phy@1 { + cavium,qlm-trim = "3,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy12: ethernet-phy@2 { + cavium,qlm-trim = "3,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy13: ethernet-phy@3 { + cavium,qlm-trim = "3,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy14: ethernet-phy@4 { + cavium,qlm-trim = "3,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <6 40>, <6 32>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@4 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + }; + }; + + interface@3 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy11>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy12>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy13>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy14>; + }; + }; + + interface@2 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy21>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy22>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy23>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy24>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy41>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy42>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy43>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy44>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <3 32>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <3 33>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <3 36>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <3 37>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0 0x1d040000 0x10000>, + <6 0 0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <300>; + cavium,t-page = <25>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <0>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <300>; + cavium,t-pause = <0>; + cavium,t-wait = <300>; + cavium,t-page = <310>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <0>; + cavium,t-ce = <30>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <310>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0 0x200000>; + read-only; + }; + partition@200000 { + label = "kernel"; + reg = <0x200000 0x200000>; + }; + partition@400000 { + label = "cramfs"; + reg = <0x400000 0x3fe000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; + + led0: led-display@4,0 { + compatible = "avago,hdsp-253x"; + reg = <4 0x20 0x20>, <4 0 0x20>; + }; + + compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <3 44>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <3 44>; + big-endian-regs; + }; + }; + }; + + aliases { + mix0 = &mix0; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + smi2 = &smi2; + smi3 = &smi3; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uctl = &uctl; + led0 = &led0; + flash0 = &flash0; + }; + }; diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore deleted file mode 100644 index 39c968605ff6..000000000000 --- a/arch/mips/cavium-octeon/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.dtb.S -*.dtb diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 4e952043c922..42f5f1a4b40a 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -20,13 +20,3 @@ obj-y += executive/ obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o - -DTS_FILES = octeon_3xxx.dts octeon_68xx.dts -DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) - -obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) - -# Let's keep the .dtb files around in case we want to look at them. -.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) - -clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts deleted file mode 100644 index fa33115bde33..000000000000 --- a/arch/mips/cavium-octeon/octeon_3xxx.dts +++ /dev/null @@ -1,590 +0,0 @@ -/dts-v1/; -/* - * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. - * - * This device tree is pruned and patched by early boot code before - * use. Because of this, it contains a super-set of the available - * devices and properties. - */ -/ { - compatible = "cavium,octeon-3860"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&ciu>; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; /* Direct mapping */ - - ciu: interrupt-controller@1070000000000 { - compatible = "cavium,octeon-3860-ciu"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0 or 1) - * 2) Bit within the register (0..63) - */ - #interrupt-cells = <2>; - reg = <0x10700 0x00000000 0x0 0x7000>; - }; - - gpio: gpio-controller@1070000000800 { - #gpio-cells = <2>; - compatible = "cavium,octeon-3860-gpio"; - reg = <0x10700 0x00000800 0x0 0x100>; - gpio-controller; - /* Interrupts are specified by two parts: - * 1) GPIO pin number (0..15) - * 2) Triggering (1 - edge rising - * 2 - edge falling - * 4 - level active high - * 8 - level active low) - */ - interrupt-controller; - #interrupt-cells = <2>; - /* The GPIO pin connect to 16 consecutive CUI bits */ - interrupts = <0 16>, <0 17>, <0 18>, <0 19>, - <0 20>, <0 21>, <0 22>, <0 23>, - <0 24>, <0 25>, <0 26>, <0 27>, - <0 28>, <0 29>, <0 30>, <0 31>; - }; - - smi0: mdio@1180000001800 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001800 0x0 0x40>; - - phy0: ethernet-phy@0 { - compatible = "marvell,88e1118"; - marvell,reg-init = - /* Fix rx and tx clock transition timing */ - <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ - /* Adjust LED drive. */ - <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ - /* irq, blink-activity, blink-link */ - <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { - compatible = "marvell,88e1118"; - marvell,reg-init = - /* Fix rx and tx clock transition timing */ - <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ - /* Adjust LED drive. */ - <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ - /* irq, blink-activity, blink-link */ - <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy3: ethernet-phy@3 { - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy4: ethernet-phy@4 { - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - - phy6: ethernet-phy@6 { - reg = <6>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy7: ethernet-phy@7 { - reg = <7>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy9: ethernet-phy@9 { - reg = <9>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - smi1: mdio@1180000001900 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001900 0x0 0x40>; - - phy100: ethernet-phy@1 { - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy101: ethernet-phy@2 { - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy102: ethernet-phy@3 { - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy103: ethernet-phy@4 { - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - }; - - mix0: ethernet@1070000100000 { - compatible = "cavium,octeon-5750-mix"; - reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ - <0x11800 0xE0000000 0x0 0x300>, /* AGL */ - <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ - <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ - cell-index = <0>; - interrupts = <0 62>, <1 46>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy0>; - }; - - mix1: ethernet@1070000100800 { - compatible = "cavium,octeon-5750-mix"; - reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ - <0x11800 0xE0000800 0x0 0x300>, /* AGL */ - <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ - <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ - cell-index = <1>; - interrupts = <1 18>, < 1 46>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy1>; - }; - - pip: pip@11800a0000000 { - compatible = "cavium,octeon-3860-pip"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0xa0000000 0x0 0x2000>; - - interface@0 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy2>; - cavium,alt-phy-handle = <&phy100>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy3>; - cavium,alt-phy-handle = <&phy101>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy4>; - cavium,alt-phy-handle = <&phy102>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy5>; - cavium,alt-phy-handle = <&phy103>; - }; - ethernet@4 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x4>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@5 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x5>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@6 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x6>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@7 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x7>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@8 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x8>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@9 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x9>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@a { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xa>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@b { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xb>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@c { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xc>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@d { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xd>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@e { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xe>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@f { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xf>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - interface@1 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy6>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy7>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy8>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy9>; - }; - }; - }; - - twsi0: i2c@1180000001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001000 0x0 0x200>; - interrupts = <0 45>; - clock-frequency = <100000>; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; - tmp@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - }; - - twsi1: i2c@1180000001200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001200 0x0 0x200>; - interrupts = <0 59>; - clock-frequency = <100000>; - }; - - uart0: serial@1180000000800 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000800 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <0 34>; - }; - - uart1: serial@1180000000c00 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000c00 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <0 35>; - }; - - uart2: serial@1180000000400 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000400 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <1 16>; - }; - - bootbus: bootbus@1180000000000 { - compatible = "cavium,octeon-3860-bootbus"; - reg = <0x11800 0x00000000 0x0 0x200>; - /* The chip select number and offset */ - #address-cells = <2>; - /* The size of the chip select region */ - #size-cells = <1>; - ranges = <0 0 0x0 0x1f400000 0xc00000>, - <1 0 0x10000 0x30000000 0>, - <2 0 0x10000 0x40000000 0>, - <3 0 0x10000 0x50000000 0>, - <4 0 0x0 0x1d020000 0x10000>, - <5 0 0x0 0x1d040000 0x10000>, - <6 0 0x0 0x1d050000 0x10000>, - <7 0 0x10000 0x90000000 0>; - - cavium,cs-config@0 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <0>; - cavium,t-adr = <20>; - cavium,t-ce = <60>; - cavium,t-oe = <60>; - cavium,t-we = <45>; - cavium,t-rd-hld = <35>; - cavium,t-wr-hld = <45>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <35>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@4 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <4>; - cavium,t-adr = <320>; - cavium,t-ce = <320>; - cavium,t-oe = <320>; - cavium,t-we = <320>; - cavium,t-rd-hld = <320>; - cavium,t-wr-hld = <320>; - cavium,t-pause = <320>; - cavium,t-wait = <320>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@5 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <5>; - cavium,t-adr = <5>; - cavium,t-ce = <300>; - cavium,t-oe = <125>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <30>; - cavium,t-pause = <0>; - cavium,t-wait = <30>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <16>; - }; - cavium,cs-config@6 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <6>; - cavium,t-adr = <5>; - cavium,t-ce = <300>; - cavium,t-oe = <270>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <70>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,wait-mode; - cavium,bus-width = <16>; - }; - - flash0: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - led0: led-display@4,0 { - compatible = "avago,hdsp-253x"; - reg = <4 0x20 0x20>, <4 0 0x20>; - }; - - cf0: compact-flash@5,0 { - compatible = "cavium,ebt3000-compact-flash"; - reg = <5 0 0x10000>, <6 0 0x10000>; - cavium,bus-width = <16>; - cavium,true-ide; - cavium,dma-engine-handle = <&dma0>; - }; - }; - - dma0: dma-engine@1180000000100 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000100 0x0 0x8>; - interrupts = <0 63>; - }; - dma1: dma-engine@1180000000108 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000108 0x0 0x8>; - interrupts = <0 63>; - }; - - uctl: uctl@118006f000000 { - compatible = "cavium,octeon-6335-uctl"; - reg = <0x11800 0x6f000000 0x0 0x100>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; - /* 12MHz, 24MHz and 48MHz allowed */ - refclk-frequency = <12000000>; - /* Either "crystal" or "external" */ - refclk-type = "crystal"; - - ehci@16f0000000000 { - compatible = "cavium,octeon-6335-ehci","usb-ehci"; - reg = <0x16f00 0x00000000 0x0 0x100>; - interrupts = <0 56>; - big-endian-regs; - }; - ohci@16f0000000400 { - compatible = "cavium,octeon-6335-ohci","usb-ohci"; - reg = <0x16f00 0x00000400 0x0 0x100>; - interrupts = <0 56>; - big-endian-regs; - }; - }; - - usbn: usbn@1180068000000 { - compatible = "cavium,octeon-5750-usbn"; - reg = <0x11800 0x68000000 0x0 0x1000>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; - /* 12MHz, 24MHz and 48MHz allowed */ - refclk-frequency = <12000000>; - /* Either "crystal" or "external" */ - refclk-type = "crystal"; - - usbc@16f0010000000 { - compatible = "cavium,octeon-5750-usbc"; - reg = <0x16f00 0x10000000 0x0 0x80000>; - interrupts = <0 56>; - }; - }; - }; - - aliases { - mix0 = &mix0; - mix1 = &mix1; - pip = &pip; - smi0 = &smi0; - smi1 = &smi1; - twsi0 = &twsi0; - twsi1 = &twsi1; - uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; - flash0 = &flash0; - cf0 = &cf0; - uctl = &uctl; - usbn = &usbn; - led0 = &led0; - }; - }; diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts deleted file mode 100644 index 79b46fcb0a11..000000000000 --- a/arch/mips/cavium-octeon/octeon_68xx.dts +++ /dev/null @@ -1,625 +0,0 @@ -/dts-v1/; -/* - * OCTEON 68XX device tree skeleton. - * - * This device tree is pruned and patched by early boot code before - * use. Because of this, it contains a super-set of the available - * devices and properties. - */ -/ { - compatible = "cavium,octeon-6880"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&ciu2>; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; /* Direct mapping */ - - ciu2: interrupt-controller@1070100000000 { - compatible = "cavium,octeon-6880-ciu2"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0 or 7) - * 2) Bit within the register (0..63) - */ - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x10701 0x00000000 0x0 0x4000000>; - }; - - gpio: gpio-controller@1070000000800 { - #gpio-cells = <2>; - compatible = "cavium,octeon-3860-gpio"; - reg = <0x10700 0x00000800 0x0 0x100>; - gpio-controller; - /* Interrupts are specified by two parts: - * 1) GPIO pin number (0..15) - * 2) Triggering (1 - edge rising - * 2 - edge falling - * 4 - level active high - * 8 - level active low) - */ - interrupt-controller; - #interrupt-cells = <2>; - /* The GPIO pins connect to 16 consecutive CUI bits */ - interrupts = <7 0>, <7 1>, <7 2>, <7 3>, - <7 4>, <7 5>, <7 6>, <7 7>, - <7 8>, <7 9>, <7 10>, <7 11>, - <7 12>, <7 13>, <7 14>, <7 15>; - }; - - smi0: mdio@1180000003800 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00003800 0x0 0x40>; - - phy0: ethernet-phy@6 { - compatible = "marvell,88e1118"; - marvell,reg-init = - /* Fix rx and tx clock transition timing */ - <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ - /* Adjust LED drive. */ - <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ - /* irq, blink-activity, blink-link */ - <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ - reg = <6>; - }; - - phy1: ethernet-phy@1 { - cavium,qlm-trim = "4,sgmii"; - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy2: ethernet-phy@2 { - cavium,qlm-trim = "4,sgmii"; - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy3: ethernet-phy@3 { - cavium,qlm-trim = "4,sgmii"; - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy4: ethernet-phy@4 { - cavium,qlm-trim = "4,sgmii"; - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - smi1: mdio@1180000003880 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00003880 0x0 0x40>; - - phy41: ethernet-phy@1 { - cavium,qlm-trim = "0,sgmii"; - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy42: ethernet-phy@2 { - cavium,qlm-trim = "0,sgmii"; - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy43: ethernet-phy@3 { - cavium,qlm-trim = "0,sgmii"; - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy44: ethernet-phy@4 { - cavium,qlm-trim = "0,sgmii"; - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - smi2: mdio@1180000003900 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00003900 0x0 0x40>; - - phy21: ethernet-phy@1 { - cavium,qlm-trim = "2,sgmii"; - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy22: ethernet-phy@2 { - cavium,qlm-trim = "2,sgmii"; - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy23: ethernet-phy@3 { - cavium,qlm-trim = "2,sgmii"; - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy24: ethernet-phy@4 { - cavium,qlm-trim = "2,sgmii"; - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - smi3: mdio@1180000003980 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00003980 0x0 0x40>; - - phy11: ethernet-phy@1 { - cavium,qlm-trim = "3,sgmii"; - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy12: ethernet-phy@2 { - cavium,qlm-trim = "3,sgmii"; - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy13: ethernet-phy@3 { - cavium,qlm-trim = "3,sgmii"; - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy14: ethernet-phy@4 { - cavium,qlm-trim = "3,sgmii"; - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - mix0: ethernet@1070000100000 { - compatible = "cavium,octeon-5750-mix"; - reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ - <0x11800 0xE0000000 0x0 0x300>, /* AGL */ - <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ - <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ - cell-index = <0>; - interrupts = <6 40>, <6 32>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy0>; - }; - - pip: pip@11800a0000000 { - compatible = "cavium,octeon-3860-pip"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0xa0000000 0x0 0x2000>; - - interface@4 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy1>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy2>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy3>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy4>; - }; - }; - - interface@3 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy11>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy12>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy13>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy14>; - }; - }; - - interface@2 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy21>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy22>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy23>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy24>; - }; - }; - - interface@1 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - interface@0 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy41>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy42>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy43>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy44>; - }; - }; - }; - - twsi0: i2c@1180000001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001000 0x0 0x200>; - interrupts = <3 32>; - clock-frequency = <100000>; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; - tmp@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - }; - - twsi1: i2c@1180000001200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001200 0x0 0x200>; - interrupts = <3 33>; - clock-frequency = <100000>; - }; - - uart0: serial@1180000000800 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000800 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <3 36>; - }; - - uart1: serial@1180000000c00 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000c00 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <3 37>; - }; - - bootbus: bootbus@1180000000000 { - compatible = "cavium,octeon-3860-bootbus"; - reg = <0x11800 0x00000000 0x0 0x200>; - /* The chip select number and offset */ - #address-cells = <2>; - /* The size of the chip select region */ - #size-cells = <1>; - ranges = <0 0 0 0x1f400000 0xc00000>, - <1 0 0x10000 0x30000000 0>, - <2 0 0x10000 0x40000000 0>, - <3 0 0x10000 0x50000000 0>, - <4 0 0 0x1d020000 0x10000>, - <5 0 0 0x1d040000 0x10000>, - <6 0 0 0x1d050000 0x10000>, - <7 0 0x10000 0x90000000 0>; - - cavium,cs-config@0 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <0>; - cavium,t-adr = <10>; - cavium,t-ce = <50>; - cavium,t-oe = <50>; - cavium,t-we = <35>; - cavium,t-rd-hld = <25>; - cavium,t-wr-hld = <35>; - cavium,t-pause = <0>; - cavium,t-wait = <300>; - cavium,t-page = <25>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@4 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <4>; - cavium,t-adr = <320>; - cavium,t-ce = <320>; - cavium,t-oe = <320>; - cavium,t-we = <320>; - cavium,t-rd-hld = <320>; - cavium,t-wr-hld = <320>; - cavium,t-pause = <320>; - cavium,t-wait = <320>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@5 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <5>; - cavium,t-adr = <0>; - cavium,t-ce = <300>; - cavium,t-oe = <125>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <300>; - cavium,t-pause = <0>; - cavium,t-wait = <300>; - cavium,t-page = <310>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <16>; - }; - cavium,cs-config@6 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <6>; - cavium,t-adr = <0>; - cavium,t-ce = <30>; - cavium,t-oe = <125>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <30>; - cavium,t-pause = <0>; - cavium,t-wait = <30>; - cavium,t-page = <310>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,wait-mode; - cavium,bus-width = <16>; - }; - - flash0: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0 0x200000>; - read-only; - }; - partition@200000 { - label = "kernel"; - reg = <0x200000 0x200000>; - }; - partition@400000 { - label = "cramfs"; - reg = <0x400000 0x3fe000>; - }; - partition@7fe000 { - label = "environment"; - reg = <0x7fe000 0x2000>; - read-only; - }; - }; - - led0: led-display@4,0 { - compatible = "avago,hdsp-253x"; - reg = <4 0x20 0x20>, <4 0 0x20>; - }; - - compact-flash@5,0 { - compatible = "cavium,ebt3000-compact-flash"; - reg = <5 0 0x10000>, <6 0 0x10000>; - cavium,bus-width = <16>; - cavium,true-ide; - cavium,dma-engine-handle = <&dma0>; - }; - }; - - dma0: dma-engine@1180000000100 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000100 0x0 0x8>; - interrupts = <0 63>; - }; - dma1: dma-engine@1180000000108 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000108 0x0 0x8>; - interrupts = <0 63>; - }; - - uctl: uctl@118006f000000 { - compatible = "cavium,octeon-6335-uctl"; - reg = <0x11800 0x6f000000 0x0 0x100>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; - /* 12MHz, 24MHz and 48MHz allowed */ - refclk-frequency = <12000000>; - /* Either "crystal" or "external" */ - refclk-type = "crystal"; - - ehci@16f0000000000 { - compatible = "cavium,octeon-6335-ehci","usb-ehci"; - reg = <0x16f00 0x00000000 0x0 0x100>; - interrupts = <3 44>; - big-endian-regs; - }; - ohci@16f0000000400 { - compatible = "cavium,octeon-6335-ohci","usb-ohci"; - reg = <0x16f00 0x00000400 0x0 0x100>; - interrupts = <3 44>; - big-endian-regs; - }; - }; - }; - - aliases { - mix0 = &mix0; - pip = &pip; - smi0 = &smi0; - smi1 = &smi1; - smi2 = &smi2; - smi3 = &smi3; - twsi0 = &twsi0; - twsi1 = &twsi1; - uart0 = &uart0; - uart1 = &uart1; - uctl = &uctl; - led0 = &led0; - flash0 = &flash0; - }; - }; -- cgit v1.2.3 From 3229a6d865d78152fb2a25aa0cf97e1904cf18d8 Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Thu, 21 Aug 2014 13:04:23 -0700 Subject: MIPS: Lantiq: Move device-trees to arch/mips/boot/dts/ Move the Lantiq device-trees to arch/mips/boot/dts/ and update the Makefiles accordingly. There is currently only a single Lantiq device-tree (EASY50712), and it's required to be built into the kernel, so select BUILTIN_DTB for it. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: James Hogan Cc: Paul Burton Cc: David Daney Cc: John Crispin Cc: Jayachandran C Cc: Qais Yousef Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7559/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/danube.dtsi | 105 ++++++++++++++++++++++++++++++++++ arch/mips/boot/dts/easy50712.dts | 114 +++++++++++++++++++++++++++++++++++++ arch/mips/lantiq/Kconfig | 1 + arch/mips/lantiq/Makefile | 2 - arch/mips/lantiq/dts/Makefile | 1 - arch/mips/lantiq/dts/danube.dtsi | 105 ---------------------------------- arch/mips/lantiq/dts/easy50712.dts | 114 ------------------------------------- 8 files changed, 221 insertions(+), 222 deletions(-) create mode 100644 arch/mips/boot/dts/danube.dtsi create mode 100644 arch/mips/boot/dts/easy50712.dts delete mode 100644 arch/mips/lantiq/dts/Makefile delete mode 100644 arch/mips/lantiq/dts/danube.dtsi delete mode 100644 arch/mips/lantiq/dts/easy50712.dts diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 51acad699ed0..4f265ec447eb 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb +dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) diff --git a/arch/mips/boot/dts/danube.dtsi b/arch/mips/boot/dts/danube.dtsi new file mode 100644 index 000000000000..d4c59e003708 --- /dev/null +++ b/arch/mips/boot/dts/danube.dtsi @@ -0,0 +1,105 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,danube"; + + cpus { + cpu@0 { + compatible = "mips,mips24Kc"; + }; + }; + + biu@1F800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1F800000 0x800000>; + ranges = <0x0 0x1F800000 0x7FFFFF>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + reg = <0x80200 0x120>; + }; + + watchdog@803F0 { + compatible = "lantiq,wdt"; + reg = <0x803F0 0x10>; + }; + }; + + sram@1F000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram"; + reg = <0x1F000000 0x800000>; + ranges = <0x0 0x1F000000 0x7FFFFF>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + #clock-cells = <1>; + }; + + rcu0: rcu@203000 { + compatible = "lantiq,rcu-xway"; + reg = <0x203000 0x1000>; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + gptu@E100A00 { + compatible = "lantiq,gptu-xway"; + reg = <0xE100A00 0x100>; + }; + + serial@E100C00 { + compatible = "lantiq,asc"; + reg = <0xE100C00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + }; + + dma0: dma@E104100 { + compatible = "lantiq,dma-xway"; + reg = <0xE104100 0x800>; + }; + + ebu0: ebu@E105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xE105300 0x100>; + }; + + pci0: pci@E105400 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xE105400 0x400>; /* pci bridge */ + }; + }; +}; diff --git a/arch/mips/boot/dts/easy50712.dts b/arch/mips/boot/dts/easy50712.dts new file mode 100644 index 000000000000..143b8a37b5e4 --- /dev/null +++ b/arch/mips/boot/dts/easy50712.dts @@ -0,0 +1,114 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; /* 64 KB */ + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; /* 64 KB */ + }; + + partition@20000 { + label = "linux"; + reg = <0x20000 0x3d0000>; + }; + + partition@400000 { + label = "rootfs"; + reg = <0x400000 0x400000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xway"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; /* stp */ + lantiq,open-drain; + lantiq,pull = <0>; + }; + }; + }; + + etop@E180000 { + compatible = "lantiq,etop-xway"; + reg = <0xE180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <73 78>; + phy-mode = "rmii"; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + stp0: stp@E100BB0 { + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xE100BB0 0x40>; + + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + }; + + pci@E105400 { + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29 + >; + gpios-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + + }; +}; diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index c0021912131e..e10d33342b30 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -30,6 +30,7 @@ choice config DT_EASY50712 bool "Easy50712" depends on SOC_XWAY + select BUILTIN_DTB endchoice config PCI_LANTIQ diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index d6bdc579419f..690257ab86d6 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -6,8 +6,6 @@ obj-y := irq.o clk.o prom.o -obj-y += dts/ - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ diff --git a/arch/mips/lantiq/dts/Makefile b/arch/mips/lantiq/dts/Makefile deleted file mode 100644 index 6fa72dd641b2..000000000000 --- a/arch/mips/lantiq/dts/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_DT_EASY50712) := easy50712.dtb.o diff --git a/arch/mips/lantiq/dts/danube.dtsi b/arch/mips/lantiq/dts/danube.dtsi deleted file mode 100644 index d4c59e003708..000000000000 --- a/arch/mips/lantiq/dts/danube.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,danube"; - - cpus { - cpu@0 { - compatible = "mips,mips24Kc"; - }; - }; - - biu@1F800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1F800000 0x800000>; - ranges = <0x0 0x1F800000 0x7FFFFF>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x120>; - }; - - watchdog@803F0 { - compatible = "lantiq,wdt"; - reg = <0x803F0 0x10>; - }; - }; - - sram@1F000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram"; - reg = <0x1F000000 0x800000>; - ranges = <0x0 0x1F000000 0x7FFFFF>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - #clock-cells = <1>; - }; - - rcu0: rcu@203000 { - compatible = "lantiq,rcu-xway"; - reg = <0x203000 0x1000>; - }; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xEEFFFFF>; - reg = <0x10000000 0xEF00000>; - - gptu@E100A00 { - compatible = "lantiq,gptu-xway"; - reg = <0xE100A00 0x100>; - }; - - serial@E100C00 { - compatible = "lantiq,asc"; - reg = <0xE100C00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - }; - - dma0: dma@E104100 { - compatible = "lantiq,dma-xway"; - reg = <0xE104100 0x800>; - }; - - ebu0: ebu@E105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xE105300 0x100>; - }; - - pci0: pci@E105400 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "lantiq,pci-xway"; - bus-range = <0x0 0x0>; - ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ - 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ - reg = <0x7000000 0x8000 /* config space */ - 0xE105400 0x400>; /* pci bridge */ - }; - }; -}; diff --git a/arch/mips/lantiq/dts/easy50712.dts b/arch/mips/lantiq/dts/easy50712.dts deleted file mode 100644 index 143b8a37b5e4..000000000000 --- a/arch/mips/lantiq/dts/easy50712.dts +++ /dev/null @@ -1,114 +0,0 @@ -/dts-v1/; - -/include/ "danube.dtsi" - -/ { - chosen { - bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; /* 64 KB */ - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; /* 64 KB */ - }; - - partition@20000 { - label = "linux"; - reg = <0x20000 0x3d0000>; - }; - - partition@400000 { - label = "rootfs"; - reg = <0x400000 0x400000>; - }; - }; - }; - - gpio: pinmux@E100B10 { - compatible = "lantiq,pinctrl-xway"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; - }; - }; - - etop@E180000 { - compatible = "lantiq,etop-xway"; - reg = <0xE180000 0x40000>; - interrupt-parent = <&icu0>; - interrupts = <73 78>; - phy-mode = "rmii"; - mac-address = [ 00 11 22 33 44 55 ]; - }; - - stp0: stp@E100BB0 { - #gpio-cells = <2>; - compatible = "lantiq,gpio-stp-xway"; - gpio-controller; - reg = <0xE100BB0 0x40>; - - lantiq,shadow = <0xfff>; - lantiq,groups = <0x3>; - }; - - pci@E105400 { - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = < - 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29 - >; - gpios-reset = <&gpio 21 0>; - req-mask = <0x1>; /* GNT1 */ - }; - - }; -}; -- cgit v1.2.3 From f262b5f2d5820799fd58ae08eee4ec3fc97686ab Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Thu, 21 Aug 2014 13:04:24 -0700 Subject: MIPS: sead3: Move device-trees to arch/mips/boot/dts/ Move the SEAD-3 device-tree to arch/mips/boot/dts/ and update the Makefiles accordingly. Since SEAD-3 requires the device-tree to be built into the kernel, select BUILTIN_DTB when building for SEAD-3. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: James Hogan Cc: Paul Burton Cc: David Daney Cc: John Crispin Cc: Jayachandran C Cc: Qais Yousef Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7555/ Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 1 + arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/sead3.dts | 22 ++++++++++++++++++++++ arch/mips/mti-sead3/Makefile | 4 ---- arch/mips/mti-sead3/sead3.dts | 22 ---------------------- 5 files changed, 24 insertions(+), 26 deletions(-) create mode 100644 arch/mips/boot/dts/sead3.dts delete mode 100644 arch/mips/mti-sead3/sead3.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a77ba5b81f61..d7c8bd4e2f0e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -353,6 +353,7 @@ config MIPS_SEAD3 bool "MIPS SEAD3 board" select BOOT_ELF32 select BOOT_RAW + select BUILTIN_DTB select CEVT_R4K select CSRC_R4K select CSRC_GIC diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 4f265ec447eb..8df3d3ef0a85 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -1,5 +1,6 @@ dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb +dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) diff --git a/arch/mips/boot/dts/sead3.dts b/arch/mips/boot/dts/sead3.dts new file mode 100644 index 000000000000..e4b317d414f1 --- /dev/null +++ b/arch/mips/boot/dts/sead3.dts @@ -0,0 +1,22 @@ +/dts-v1/; + +/memreserve/ 0x00000000 0x00001000; // reserved +/memreserve/ 0x00001000 0x000ef000; // ROM data +/memreserve/ 0x000f0000 0x004cc000; // reserved + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mti,sead-3"; + + cpus { + cpu@0 { + compatible = "mti,mips14KEc", "mti,mips14Kc"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile index 071786fa234b..febf4334545e 100644 --- a/arch/mips/mti-sead3/Makefile +++ b/arch/mips/mti-sead3/Makefile @@ -19,9 +19,5 @@ obj-y += sead3-i2c-dev.o sead3-i2c.o \ obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o -obj-$(CONFIG_OF) += sead3.dtb.o CFLAGS_sead3-setup.o = -I$(src)/../../../scripts/dtc/libfdt - -$(obj)/%.dtb: $(obj)/%.dts - $(call if_changed,dtc) diff --git a/arch/mips/mti-sead3/sead3.dts b/arch/mips/mti-sead3/sead3.dts deleted file mode 100644 index e4b317d414f1..000000000000 --- a/arch/mips/mti-sead3/sead3.dts +++ /dev/null @@ -1,22 +0,0 @@ -/dts-v1/; - -/memreserve/ 0x00000000 0x00001000; // reserved -/memreserve/ 0x00001000 0x000ef000; // ROM data -/memreserve/ 0x000f0000 0x004cc000; // reserved - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mti,sead-3"; - - cpus { - cpu@0 { - compatible = "mti,mips14KEc", "mti,mips14Kc"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; -- cgit v1.2.3 From 36094619e419c306dc08d83f043bc9937cc63e03 Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Thu, 21 Aug 2014 13:04:25 -0700 Subject: MIPS: Netlogic: Move device-trees to arch/mips/boot/dts/ Move the Netlogic XLP device-trees to arch/mips/boot/dts/ and update the Makefiles accordingly. A built-in device-tree is optional, so select BUILTIN_DTB when it is requested. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: James Hogan Cc: Paul Burton Cc: David Daney Cc: John Crispin Cc: Jayachandran C Cc: Qais Yousef Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7560/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/Makefile | 4 ++ arch/mips/boot/dts/xlp_evp.dts | 118 +++++++++++++++++++++++++++++++++++++ arch/mips/boot/dts/xlp_fvp.dts | 118 +++++++++++++++++++++++++++++++++++++ arch/mips/boot/dts/xlp_gvp.dts | 77 ++++++++++++++++++++++++ arch/mips/boot/dts/xlp_svp.dts | 118 +++++++++++++++++++++++++++++++++++++ arch/mips/netlogic/Kconfig | 4 ++ arch/mips/netlogic/Makefile | 1 - arch/mips/netlogic/dts/Makefile | 4 -- arch/mips/netlogic/dts/xlp_evp.dts | 118 ------------------------------------- arch/mips/netlogic/dts/xlp_fvp.dts | 118 ------------------------------------- arch/mips/netlogic/dts/xlp_gvp.dts | 77 ------------------------ arch/mips/netlogic/dts/xlp_svp.dts | 118 ------------------------------------- 12 files changed, 439 insertions(+), 436 deletions(-) create mode 100644 arch/mips/boot/dts/xlp_evp.dts create mode 100644 arch/mips/boot/dts/xlp_fvp.dts create mode 100644 arch/mips/boot/dts/xlp_gvp.dts create mode 100644 arch/mips/boot/dts/xlp_svp.dts delete mode 100644 arch/mips/netlogic/dts/Makefile delete mode 100644 arch/mips/netlogic/dts/xlp_evp.dts delete mode 100644 arch/mips/netlogic/dts/xlp_fvp.dts delete mode 100644 arch/mips/netlogic/dts/xlp_gvp.dts delete mode 100644 arch/mips/netlogic/dts/xlp_svp.dts diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 8df3d3ef0a85..1638a3837caa 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -1,5 +1,9 @@ dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb +dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb +dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb +dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb +dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) diff --git a/arch/mips/boot/dts/xlp_evp.dts b/arch/mips/boot/dts/xlp_evp.dts new file mode 100644 index 000000000000..89ad04808c02 --- /dev/null +++ b/arch/mips/boot/dts/xlp_evp.dts @@ -0,0 +1,118 @@ +/* + * XLP8XX Device Tree Source for EVP boards + */ + +/dts-v1/; +/ { + model = "netlogic,XLP-EVP"; + compatible = "netlogic,xlp"; + #address-cells = <2>; + #size-cells = <2>; + + soc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG + 1 0 0 0x16000000 0x02000000>; // GBU chipselects + + serial0: serial@30000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x30100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + serial1: serial@31000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x31100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <18>; + }; + i2c0: ocores@32000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x32100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <30>; + }; + i2c1: ocores@33000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x33100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <31>; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + + dtt@4c { + compatible = "national,lm90"; + reg = <0x4c>; + }; + }; + pic: pic@4000 { + compatible = "netlogic,xlp-pic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0 0x4000 0x200>; + interrupt-controller; + }; + + nor_flash@1,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + reg = <1 0 0x1000000>; + + partition@0 { + label = "x-loader"; + reg = <0x0 0x100000>; /* 1M */ + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; /* 1M */ + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; /* 5M */ + }; + + partition@700000 { + label = "rootfs"; + reg = <0x700000 0x800000>; /* 8M */ + }; + + partition@f00000 { + label = "env"; + reg = <0xf00000 0x100000>; /* 1M */ + read-only; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; + }; +}; diff --git a/arch/mips/boot/dts/xlp_fvp.dts b/arch/mips/boot/dts/xlp_fvp.dts new file mode 100644 index 000000000000..63e62b7bd758 --- /dev/null +++ b/arch/mips/boot/dts/xlp_fvp.dts @@ -0,0 +1,118 @@ +/* + * XLP2XX Device Tree Source for FVP boards + */ + +/dts-v1/; +/ { + model = "netlogic,XLP-FVP"; + compatible = "netlogic,xlp"; + #address-cells = <2>; + #size-cells = <2>; + + soc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG + 1 0 0 0x16000000 0x02000000>; // GBU chipselects + + serial0: serial@30000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x30100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + serial1: serial@31000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x31100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <18>; + }; + i2c0: ocores@37100 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x37100 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <30>; + }; + i2c1: ocores@37120 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x37120 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <31>; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + + dtt@4c { + compatible = "national,lm90"; + reg = <0x4c>; + }; + }; + pic: pic@4000 { + compatible = "netlogic,xlp-pic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0 0x4000 0x200>; + interrupt-controller; + }; + + nor_flash@1,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + reg = <1 0 0x1000000>; + + partition@0 { + label = "x-loader"; + reg = <0x0 0x100000>; /* 1M */ + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; /* 1M */ + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; /* 5M */ + }; + + partition@700000 { + label = "rootfs"; + reg = <0x700000 0x800000>; /* 8M */ + }; + + partition@f00000 { + label = "env"; + reg = <0xf00000 0x100000>; /* 1M */ + read-only; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; + }; +}; diff --git a/arch/mips/boot/dts/xlp_gvp.dts b/arch/mips/boot/dts/xlp_gvp.dts new file mode 100644 index 000000000000..bb4ecd1d47fc --- /dev/null +++ b/arch/mips/boot/dts/xlp_gvp.dts @@ -0,0 +1,77 @@ +/* + * XLP9XX Device Tree Source for GVP boards + */ + +/dts-v1/; +/ { + model = "netlogic,XLP-GVP"; + compatible = "netlogic,xlp"; + #address-cells = <2>; + #size-cells = <2>; + + soc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG + 1 0 0 0x16000000 0x02000000>; // GBU chipselects + + serial0: serial@30000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x112100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <125000000>; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + pic: pic@110000 { + compatible = "netlogic,xlp-pic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0 0x110000 0x200>; + interrupt-controller; + }; + + nor_flash@1,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + reg = <1 0 0x1000000>; + + partition@0 { + label = "x-loader"; + reg = <0x0 0x100000>; /* 1M */ + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; /* 1M */ + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; /* 5M */ + }; + + partition@700000 { + label = "rootfs"; + reg = <0x700000 0x800000>; /* 8M */ + }; + + partition@f00000 { + label = "env"; + reg = <0xf00000 0x100000>; /* 1M */ + read-only; + }; + }; + + }; + + chosen { + bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; + }; +}; diff --git a/arch/mips/boot/dts/xlp_svp.dts b/arch/mips/boot/dts/xlp_svp.dts new file mode 100644 index 000000000000..1ebd00edaacc --- /dev/null +++ b/arch/mips/boot/dts/xlp_svp.dts @@ -0,0 +1,118 @@ +/* + * XLP3XX Device Tree Source for SVP boards + */ + +/dts-v1/; +/ { + model = "netlogic,XLP-SVP"; + compatible = "netlogic,xlp"; + #address-cells = <2>; + #size-cells = <2>; + + soc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG + 1 0 0 0x16000000 0x02000000>; // GBU chipselects + + serial0: serial@30000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x30100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + serial1: serial@31000 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0 0x31100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <133333333>; + interrupt-parent = <&pic>; + interrupts = <18>; + }; + i2c0: ocores@32000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x32100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <30>; + }; + i2c1: ocores@33000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x33100 0xa00>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <32000000>; + interrupt-parent = <&pic>; + interrupts = <31>; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + + dtt@4c { + compatible = "national,lm90"; + reg = <0x4c>; + }; + }; + pic: pic@4000 { + compatible = "netlogic,xlp-pic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0 0x4000 0x200>; + interrupt-controller; + }; + + nor_flash@1,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + reg = <1 0 0x1000000>; + + partition@0 { + label = "x-loader"; + reg = <0x0 0x100000>; /* 1M */ + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; /* 1M */ + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x500000>; /* 5M */ + }; + + partition@700000 { + label = "rootfs"; + reg = <0x700000 0x800000>; /* 8M */ + }; + + partition@f00000 { + label = "env"; + reg = <0xf00000 0x100000>; /* 1M */ + read-only; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; + }; +}; diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig index 4eb683aef7d7..0823321c10e0 100644 --- a/arch/mips/netlogic/Kconfig +++ b/arch/mips/netlogic/Kconfig @@ -4,6 +4,7 @@ if NLM_XLP_BOARD config DT_XLP_EVP bool "Built-in device tree for XLP EVP boards" default y + select BUILTIN_DTB help Add an FDT blob for XLP EVP boards into the kernel. This DTB will be used if the firmware does not pass in a DTB @@ -13,6 +14,7 @@ config DT_XLP_EVP config DT_XLP_SVP bool "Built-in device tree for XLP SVP boards" default y + select BUILTIN_DTB help Add an FDT blob for XLP VP boards into the kernel. This DTB will be used if the firmware does not pass in a DTB @@ -22,6 +24,7 @@ config DT_XLP_SVP config DT_XLP_FVP bool "Built-in device tree for XLP FVP boards" default y + select BUILTIN_DTB help Add an FDT blob for XLP FVP board into the kernel. This DTB will be used if the firmware does not pass in a DTB @@ -31,6 +34,7 @@ config DT_XLP_FVP config DT_XLP_GVP bool "Built-in device tree for XLP GVP boards" default y + select BUILTIN_DTB help Add an FDT blob for XLP GVP board into the kernel. This DTB will be used if the firmware does not pass in a DTB diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile index 7602d1386614..36d169b2ca6d 100644 --- a/arch/mips/netlogic/Makefile +++ b/arch/mips/netlogic/Makefile @@ -1,4 +1,3 @@ obj-$(CONFIG_NLM_COMMON) += common/ obj-$(CONFIG_CPU_XLR) += xlr/ obj-$(CONFIG_CPU_XLP) += xlp/ -obj-$(CONFIG_CPU_XLP) += dts/ diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile deleted file mode 100644 index 25c8e873ee25..000000000000 --- a/arch/mips/netlogic/dts/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o -obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o -obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o -obj-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb.o diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts deleted file mode 100644 index 89ad04808c02..000000000000 --- a/arch/mips/netlogic/dts/xlp_evp.dts +++ /dev/null @@ -1,118 +0,0 @@ -/* - * XLP8XX Device Tree Source for EVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-EVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x30100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - serial1: serial@31000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x31100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <18>; - }; - i2c0: ocores@32000 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x32100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <30>; - }; - i2c1: ocores@33000 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x33100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <31>; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - dtt@4c { - compatible = "national,lm90"; - reg = <0x4c>; - }; - }; - pic: pic@4000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x4000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; diff --git a/arch/mips/netlogic/dts/xlp_fvp.dts b/arch/mips/netlogic/dts/xlp_fvp.dts deleted file mode 100644 index 63e62b7bd758..000000000000 --- a/arch/mips/netlogic/dts/xlp_fvp.dts +++ /dev/null @@ -1,118 +0,0 @@ -/* - * XLP2XX Device Tree Source for FVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-FVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x30100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - serial1: serial@31000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x31100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <18>; - }; - i2c0: ocores@37100 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x37100 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <30>; - }; - i2c1: ocores@37120 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x37120 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <31>; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - dtt@4c { - compatible = "national,lm90"; - reg = <0x4c>; - }; - }; - pic: pic@4000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x4000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; diff --git a/arch/mips/netlogic/dts/xlp_gvp.dts b/arch/mips/netlogic/dts/xlp_gvp.dts deleted file mode 100644 index bb4ecd1d47fc..000000000000 --- a/arch/mips/netlogic/dts/xlp_gvp.dts +++ /dev/null @@ -1,77 +0,0 @@ -/* - * XLP9XX Device Tree Source for GVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-GVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x112100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <125000000>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - pic: pic@110000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x110000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; diff --git a/arch/mips/netlogic/dts/xlp_svp.dts b/arch/mips/netlogic/dts/xlp_svp.dts deleted file mode 100644 index 1ebd00edaacc..000000000000 --- a/arch/mips/netlogic/dts/xlp_svp.dts +++ /dev/null @@ -1,118 +0,0 @@ -/* - * XLP3XX Device Tree Source for SVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-SVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x30100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - serial1: serial@31000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x31100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <18>; - }; - i2c0: ocores@32000 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x32100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <30>; - }; - i2c1: ocores@33000 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x33100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <31>; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - dtt@4c { - compatible = "national,lm90"; - reg = <0x4c>; - }; - }; - pic: pic@4000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x4000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; -- cgit v1.2.3 From 011eeece0bb2e1b65b2d2fd618067425e8ccdbb4 Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Thu, 21 Aug 2014 13:04:26 -0700 Subject: MIPS: ralink: Move device-trees to arch/mips/boot/dts/ Move the Ralink device-trees to arch/mips/boot/dts/ and update the Makefiles accordingly. A built-in device-tree is optional, so select BUILTIN_DTB when it is requested. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: James Hogan Cc: Paul Burton Cc: David Daney Cc: John Crispin Cc: Jayachandran C Cc: Qais Yousef Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7561/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/Makefile | 4 +++ arch/mips/boot/dts/mt7620a.dtsi | 58 ++++++++++++++++++++++++++++++ arch/mips/boot/dts/mt7620a_eval.dts | 17 +++++++++ arch/mips/boot/dts/rt2880.dtsi | 58 ++++++++++++++++++++++++++++++ arch/mips/boot/dts/rt2880_eval.dts | 47 ++++++++++++++++++++++++ arch/mips/boot/dts/rt3050.dtsi | 68 +++++++++++++++++++++++++++++++++++ arch/mips/boot/dts/rt3052_eval.dts | 51 ++++++++++++++++++++++++++ arch/mips/boot/dts/rt3883.dtsi | 58 ++++++++++++++++++++++++++++++ arch/mips/boot/dts/rt3883_eval.dts | 17 +++++++++ arch/mips/ralink/Kconfig | 4 +++ arch/mips/ralink/Makefile | 2 -- arch/mips/ralink/dts/Makefile | 4 --- arch/mips/ralink/dts/mt7620a.dtsi | 58 ------------------------------ arch/mips/ralink/dts/mt7620a_eval.dts | 17 --------- arch/mips/ralink/dts/rt2880.dtsi | 58 ------------------------------ arch/mips/ralink/dts/rt2880_eval.dts | 47 ------------------------ arch/mips/ralink/dts/rt3050.dtsi | 68 ----------------------------------- arch/mips/ralink/dts/rt3052_eval.dts | 51 -------------------------- arch/mips/ralink/dts/rt3883.dtsi | 58 ------------------------------ arch/mips/ralink/dts/rt3883_eval.dts | 17 --------- 20 files changed, 382 insertions(+), 380 deletions(-) create mode 100644 arch/mips/boot/dts/mt7620a.dtsi create mode 100644 arch/mips/boot/dts/mt7620a_eval.dts create mode 100644 arch/mips/boot/dts/rt2880.dtsi create mode 100644 arch/mips/boot/dts/rt2880_eval.dts create mode 100644 arch/mips/boot/dts/rt3050.dtsi create mode 100644 arch/mips/boot/dts/rt3052_eval.dts create mode 100644 arch/mips/boot/dts/rt3883.dtsi create mode 100644 arch/mips/boot/dts/rt3883_eval.dts delete mode 100644 arch/mips/ralink/dts/Makefile delete mode 100644 arch/mips/ralink/dts/mt7620a.dtsi delete mode 100644 arch/mips/ralink/dts/mt7620a_eval.dts delete mode 100644 arch/mips/ralink/dts/rt2880.dtsi delete mode 100644 arch/mips/ralink/dts/rt2880_eval.dts delete mode 100644 arch/mips/ralink/dts/rt3050.dtsi delete mode 100644 arch/mips/ralink/dts/rt3052_eval.dts delete mode 100644 arch/mips/ralink/dts/rt3883.dtsi delete mode 100644 arch/mips/ralink/dts/rt3883_eval.dts diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 1638a3837caa..ca9c90e2cabf 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -4,6 +4,10 @@ dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb +dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb +dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb +dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb +dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) diff --git a/arch/mips/boot/dts/mt7620a.dtsi b/arch/mips/boot/dts/mt7620a.dtsi new file mode 100644 index 000000000000..08bf24fefe9f --- /dev/null +++ b/arch/mips/boot/dts/mt7620a.dtsi @@ -0,0 +1,58 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,mtk7620a-soc"; + + cpus { + cpu@0 { + compatible = "mips,mips24KEc"; + }; + }; + + cpuintc: cpuintc@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@10000000 { + compatible = "palmbus"; + reg = <0x10000000 0x200000>; + ranges = <0x0 0x10000000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc@0 { + compatible = "ralink,mt7620a-sysc"; + reg = <0x0 0x100>; + }; + + intc: intc@200 { + compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + memc@300 { + compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; + reg = <0x300 0x100>; + }; + + uartlite@c00 { + compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0xc00 0x100>; + + interrupt-parent = <&intc>; + interrupts = <12>; + + reg-shift = <2>; + }; + }; +}; diff --git a/arch/mips/boot/dts/mt7620a_eval.dts b/arch/mips/boot/dts/mt7620a_eval.dts new file mode 100644 index 000000000000..709f58132f5c --- /dev/null +++ b/arch/mips/boot/dts/mt7620a_eval.dts @@ -0,0 +1,17 @@ +/dts-v1/; + +/include/ "mt7620a.dtsi" + +/ { + compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; + model = "Ralink MT7620A evaluation board"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; +}; diff --git a/arch/mips/boot/dts/rt2880.dtsi b/arch/mips/boot/dts/rt2880.dtsi new file mode 100644 index 000000000000..182afde2f2e1 --- /dev/null +++ b/arch/mips/boot/dts/rt2880.dtsi @@ -0,0 +1,58 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,rt2880-soc"; + + cpus { + cpu@0 { + compatible = "mips,mips4KEc"; + }; + }; + + cpuintc: cpuintc@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@300000 { + compatible = "palmbus"; + reg = <0x300000 0x200000>; + ranges = <0x0 0x300000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc@0 { + compatible = "ralink,rt2880-sysc"; + reg = <0x0 0x100>; + }; + + intc: intc@200 { + compatible = "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + memc@300 { + compatible = "ralink,rt2880-memc"; + reg = <0x300 0x100>; + }; + + uartlite@c00 { + compatible = "ralink,rt2880-uart", "ns16550a"; + reg = <0xc00 0x100>; + + interrupt-parent = <&intc>; + interrupts = <8>; + + reg-shift = <2>; + }; + }; +}; diff --git a/arch/mips/boot/dts/rt2880_eval.dts b/arch/mips/boot/dts/rt2880_eval.dts new file mode 100644 index 000000000000..0a685db093d4 --- /dev/null +++ b/arch/mips/boot/dts/rt2880_eval.dts @@ -0,0 +1,47 @@ +/dts-v1/; + +/include/ "rt2880.dtsi" + +/ { + compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc"; + model = "Ralink RT2880 evaluation board"; + + memory@0 { + device_type = "memory"; + reg = <0x8000000 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + cfi@1f000000 { + compatible = "cfi-flash"; + reg = <0x1f000000 0x400000>; + + bank-width = <2>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + partition@30000 { + label = "uboot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + partition@40000 { + label = "calibration"; + reg = <0x40000 0x10000>; + read-only; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x3b0000>; + }; + }; +}; diff --git a/arch/mips/boot/dts/rt3050.dtsi b/arch/mips/boot/dts/rt3050.dtsi new file mode 100644 index 000000000000..e3203d414fee --- /dev/null +++ b/arch/mips/boot/dts/rt3050.dtsi @@ -0,0 +1,68 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc"; + + cpus { + cpu@0 { + compatible = "mips,mips24KEc"; + }; + }; + + cpuintc: cpuintc@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@10000000 { + compatible = "palmbus"; + reg = <0x10000000 0x200000>; + ranges = <0x0 0x10000000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc@0 { + compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc"; + reg = <0x0 0x100>; + }; + + intc: intc@200 { + compatible = "ralink,rt3052-intc", "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + memc@300 { + compatible = "ralink,rt3052-memc", "ralink,rt3050-memc"; + reg = <0x300 0x100>; + }; + + uartlite@c00 { + compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0xc00 0x100>; + + interrupt-parent = <&intc>; + interrupts = <12>; + + reg-shift = <2>; + }; + }; + + usb@101c0000 { + compatible = "ralink,rt3050-usb", "snps,dwc2"; + reg = <0x101c0000 40000>; + + interrupt-parent = <&intc>; + interrupts = <18>; + + status = "disabled"; + }; +}; diff --git a/arch/mips/boot/dts/rt3052_eval.dts b/arch/mips/boot/dts/rt3052_eval.dts new file mode 100644 index 000000000000..ec9e9a035541 --- /dev/null +++ b/arch/mips/boot/dts/rt3052_eval.dts @@ -0,0 +1,51 @@ +/dts-v1/; + +#include "rt3050.dtsi" + +/ { + compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc"; + model = "Ralink RT3052 evaluation board"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + cfi@1f000000 { + compatible = "cfi-flash"; + reg = <0x1f000000 0x800000>; + + bank-width = <2>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + partition@30000 { + label = "uboot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + partition@40000 { + label = "calibration"; + reg = <0x40000 0x10000>; + read-only; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x7b0000>; + }; + }; + + usb@101c0000 { + status = "ok"; + }; +}; diff --git a/arch/mips/boot/dts/rt3883.dtsi b/arch/mips/boot/dts/rt3883.dtsi new file mode 100644 index 000000000000..3b131dd0d5ac --- /dev/null +++ b/arch/mips/boot/dts/rt3883.dtsi @@ -0,0 +1,58 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,rt3883-soc"; + + cpus { + cpu@0 { + compatible = "mips,mips74Kc"; + }; + }; + + cpuintc: cpuintc@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@10000000 { + compatible = "palmbus"; + reg = <0x10000000 0x200000>; + ranges = <0x0 0x10000000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc@0 { + compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc"; + reg = <0x0 0x100>; + }; + + intc: intc@200 { + compatible = "ralink,rt3883-intc", "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + memc@300 { + compatible = "ralink,rt3883-memc", "ralink,rt3050-memc"; + reg = <0x300 0x100>; + }; + + uartlite@c00 { + compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0xc00 0x100>; + + interrupt-parent = <&intc>; + interrupts = <12>; + + reg-shift = <2>; + }; + }; +}; diff --git a/arch/mips/boot/dts/rt3883_eval.dts b/arch/mips/boot/dts/rt3883_eval.dts new file mode 100644 index 000000000000..e8df21a5d10d --- /dev/null +++ b/arch/mips/boot/dts/rt3883_eval.dts @@ -0,0 +1,17 @@ +/dts-v1/; + +/include/ "rt3883.dtsi" + +/ { + compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc"; + model = "Ralink RT3883 evaluation board"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; +}; diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 4a296655f446..77e8a9620e18 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -42,18 +42,22 @@ choice config DTB_RT2880_EVAL bool "RT2880 eval kit" depends on SOC_RT288X + select BUILTIN_DTB config DTB_RT305X_EVAL bool "RT305x eval kit" depends on SOC_RT305X + select BUILTIN_DTB config DTB_RT3883_EVAL bool "RT3883 eval kit" depends on SOC_RT3883 + select BUILTIN_DTB config DTB_MT7620A_EVAL bool "MT7620A eval kit" depends on SOC_MT7620 + select BUILTIN_DTB endchoice diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile index 98ae349827be..2c09c8aa0ae2 100644 --- a/arch/mips/ralink/Makefile +++ b/arch/mips/ralink/Makefile @@ -16,5 +16,3 @@ obj-$(CONFIG_SOC_RT3883) += rt3883.o obj-$(CONFIG_SOC_MT7620) += mt7620.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - -obj-y += dts/ diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile deleted file mode 100644 index 18194fa93e80..000000000000 --- a/arch/mips/ralink/dts/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o -obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o -obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o -obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o diff --git a/arch/mips/ralink/dts/mt7620a.dtsi b/arch/mips/ralink/dts/mt7620a.dtsi deleted file mode 100644 index 08bf24fefe9f..000000000000 --- a/arch/mips/ralink/dts/mt7620a.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,mtk7620a-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips24KEc"; - }; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc@0 { - compatible = "ralink,mt7620a-sysc"; - reg = <0x0 0x100>; - }; - - intc: intc@200 { - compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc@300 { - compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - }; - - uartlite@c00 { - compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - interrupt-parent = <&intc>; - interrupts = <12>; - - reg-shift = <2>; - }; - }; -}; diff --git a/arch/mips/ralink/dts/mt7620a_eval.dts b/arch/mips/ralink/dts/mt7620a_eval.dts deleted file mode 100644 index 709f58132f5c..000000000000 --- a/arch/mips/ralink/dts/mt7620a_eval.dts +++ /dev/null @@ -1,17 +0,0 @@ -/dts-v1/; - -/include/ "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; - model = "Ralink MT7620A evaluation board"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; -}; diff --git a/arch/mips/ralink/dts/rt2880.dtsi b/arch/mips/ralink/dts/rt2880.dtsi deleted file mode 100644 index 182afde2f2e1..000000000000 --- a/arch/mips/ralink/dts/rt2880.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,rt2880-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips4KEc"; - }; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - palmbus@300000 { - compatible = "palmbus"; - reg = <0x300000 0x200000>; - ranges = <0x0 0x300000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc@0 { - compatible = "ralink,rt2880-sysc"; - reg = <0x0 0x100>; - }; - - intc: intc@200 { - compatible = "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc@300 { - compatible = "ralink,rt2880-memc"; - reg = <0x300 0x100>; - }; - - uartlite@c00 { - compatible = "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - interrupt-parent = <&intc>; - interrupts = <8>; - - reg-shift = <2>; - }; - }; -}; diff --git a/arch/mips/ralink/dts/rt2880_eval.dts b/arch/mips/ralink/dts/rt2880_eval.dts deleted file mode 100644 index 0a685db093d4..000000000000 --- a/arch/mips/ralink/dts/rt2880_eval.dts +++ /dev/null @@ -1,47 +0,0 @@ -/dts-v1/; - -/include/ "rt2880.dtsi" - -/ { - compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc"; - model = "Ralink RT2880 evaluation board"; - - memory@0 { - device_type = "memory"; - reg = <0x8000000 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x400000>; - - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - partition@40000 { - label = "calibration"; - reg = <0x40000 0x10000>; - read-only; - }; - partition@50000 { - label = "linux"; - reg = <0x50000 0x3b0000>; - }; - }; -}; diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi deleted file mode 100644 index e3203d414fee..000000000000 --- a/arch/mips/ralink/dts/rt3050.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips24KEc"; - }; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc@0 { - compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc"; - reg = <0x0 0x100>; - }; - - intc: intc@200 { - compatible = "ralink,rt3052-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc@300 { - compatible = "ralink,rt3052-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - }; - - uartlite@c00 { - compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - interrupt-parent = <&intc>; - interrupts = <12>; - - reg-shift = <2>; - }; - }; - - usb@101c0000 { - compatible = "ralink,rt3050-usb", "snps,dwc2"; - reg = <0x101c0000 40000>; - - interrupt-parent = <&intc>; - interrupts = <18>; - - status = "disabled"; - }; -}; diff --git a/arch/mips/ralink/dts/rt3052_eval.dts b/arch/mips/ralink/dts/rt3052_eval.dts deleted file mode 100644 index ec9e9a035541..000000000000 --- a/arch/mips/ralink/dts/rt3052_eval.dts +++ /dev/null @@ -1,51 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc"; - model = "Ralink RT3052 evaluation board"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - partition@40000 { - label = "calibration"; - reg = <0x40000 0x10000>; - read-only; - }; - partition@50000 { - label = "linux"; - reg = <0x50000 0x7b0000>; - }; - }; - - usb@101c0000 { - status = "ok"; - }; -}; diff --git a/arch/mips/ralink/dts/rt3883.dtsi b/arch/mips/ralink/dts/rt3883.dtsi deleted file mode 100644 index 3b131dd0d5ac..000000000000 --- a/arch/mips/ralink/dts/rt3883.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,rt3883-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips74Kc"; - }; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc@0 { - compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc"; - reg = <0x0 0x100>; - }; - - intc: intc@200 { - compatible = "ralink,rt3883-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc@300 { - compatible = "ralink,rt3883-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - }; - - uartlite@c00 { - compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - interrupt-parent = <&intc>; - interrupts = <12>; - - reg-shift = <2>; - }; - }; -}; diff --git a/arch/mips/ralink/dts/rt3883_eval.dts b/arch/mips/ralink/dts/rt3883_eval.dts deleted file mode 100644 index e8df21a5d10d..000000000000 --- a/arch/mips/ralink/dts/rt3883_eval.dts +++ /dev/null @@ -1,17 +0,0 @@ -/dts-v1/; - -/include/ "rt3883.dtsi" - -/ { - compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc"; - model = "Ralink RT3883 evaluation board"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; -}; -- cgit v1.2.3 From 39bcb7969a84aab3dcdb857b261a87d5d888f5a7 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Wed, 23 Jul 2014 10:00:09 +0100 Subject: MIPS: BPF: Add new emit_long_instr macro This macro uses the capitalized UASM_* macros to emit 32 or 64-bit instructions depending on the kernel configurations. This allows us to remove a few CONFIG_64BIT ifdefs from the code. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7446/ Signed-off-by: Ralf Baechle --- arch/mips/net/bpf_jit.c | 51 ++++++++++++++++++------------------------------- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c index ae8cc8477389..b14e2148bee4 100644 --- a/arch/mips/net/bpf_jit.c +++ b/arch/mips/net/bpf_jit.c @@ -163,6 +163,19 @@ do { \ (ctx)->idx++; \ } while (0) +/* + * Similar to emit_instr but it must be used when we need to emit + * 32-bit or 64-bit instructions + */ +#define emit_long_instr(ctx, func, ...) \ +do { \ + if ((ctx)->target != NULL) { \ + u32 *p = &(ctx)->target[ctx->idx]; \ + UASM_i_##func(&p, ##__VA_ARGS__); \ + } \ + (ctx)->idx++; \ +} while (0) + /* Determine if immediate is within the 16-bit signed range */ static inline bool is_range16(s32 imm) { @@ -218,13 +231,6 @@ static inline void emit_ori(unsigned int dst, unsigned src, u32 imm, } } - -static inline void emit_daddu(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, daddu, dst, src1, src2); -} - static inline void emit_daddiu(unsigned int dst, unsigned int src, int imm, struct jit_ctx *ctx) { @@ -283,11 +289,7 @@ static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx) static inline void emit_stack_offset(int offset, struct jit_ctx *ctx) { - if (config_enabled(CONFIG_64BIT)) - emit_instr(ctx, daddiu, r_sp, r_sp, offset); - else - emit_instr(ctx, addiu, r_sp, r_sp, offset); - + emit_long_instr(ctx, ADDIU, r_sp, r_sp, offset); } static inline void emit_subu(unsigned int dst, unsigned int src1, @@ -365,10 +367,7 @@ static inline void emit_store_stack_reg(ptr reg, ptr base, unsigned int offset, struct jit_ctx *ctx) { - if (config_enabled(CONFIG_64BIT)) - emit_instr(ctx, sd, reg, offset, base); - else - emit_instr(ctx, sw, reg, offset, base); + emit_long_instr(ctx, SW, reg, offset, base); } static inline void emit_store(ptr reg, ptr base, unsigned int offset, @@ -381,10 +380,7 @@ static inline void emit_load_stack_reg(ptr reg, ptr base, unsigned int offset, struct jit_ctx *ctx) { - if (config_enabled(CONFIG_64BIT)) - emit_instr(ctx, ld, reg, offset, base); - else - emit_instr(ctx, lw, reg, offset, base); + emit_long_instr(ctx, LW, reg, offset, base); } static inline void emit_load(unsigned int reg, unsigned int base, @@ -458,10 +454,7 @@ static inline void emit_load_ptr(unsigned int dst, unsigned int src, int imm, struct jit_ctx *ctx) { /* src contains the base addr of the 32/64-pointer */ - if (config_enabled(CONFIG_64BIT)) - emit_instr(ctx, ld, dst, imm, src); - else - emit_instr(ctx, lw, dst, imm, src); + emit_long_instr(ctx, LW, dst, imm, src); } /* load a function pointer to register */ @@ -483,10 +476,7 @@ static inline void emit_load_func(unsigned int reg, ptr imm, /* Move to real MIPS register */ static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx) { - if (config_enabled(CONFIG_64BIT)) - emit_daddu(dst, src, r_zero, ctx); - else - emit_addu(dst, src, r_zero, ctx); + emit_long_instr(ctx, ADDU, dst, src, r_zero); } /* Move to JIT (32-bit) register */ @@ -623,10 +613,7 @@ static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset) if (ctx->flags & SEEN_MEM) { if (real_off % (RSIZE * 2)) real_off += RSIZE; - if (config_enabled(CONFIG_64BIT)) - emit_daddiu(r_M, r_sp, real_off, ctx); - else - emit_addiu(r_M, r_sp, real_off, ctx); + emit_long_instr(ctx, ADDIU, r_M, r_sp, real_off); } } -- cgit v1.2.3 From 02d31c7de1e799c1fc171d86cfac92240885ce7e Mon Sep 17 00:00:00 2001 From: Zubair Lutfullah Kakakhel Date: Wed, 16 Jul 2014 16:51:29 +0100 Subject: asm-generic: Add dma-contiguous.h This header is used by arm64 and x86 individually. Adding to asm-generic to avoid further code repetition while adding cma to mips. Signed-off-by: Zubair Lutfullah Kakakhel Acked-by: Michal Nazarewicz Cc: catalin.marinas@arm.com Cc: will.deacon@arm.com Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: arnd@arndb.de Cc: gregkh@linuxfoundation.org Cc: m.szyprowski@samsung.com Cc: x86@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-arch@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7357/ Signed-off-by: Ralf Baechle --- include/asm-generic/dma-contiguous.h | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 include/asm-generic/dma-contiguous.h diff --git a/include/asm-generic/dma-contiguous.h b/include/asm-generic/dma-contiguous.h new file mode 100644 index 000000000000..292c571750f0 --- /dev/null +++ b/include/asm-generic/dma-contiguous.h @@ -0,0 +1,9 @@ +#ifndef _ASM_GENERIC_DMA_CONTIGUOUS_H +#define _ASM_GENERIC_DMA_CONTIGUOUS_H + +#include + +static inline void +dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { } + +#endif -- cgit v1.2.3 From 2f06dbe4e4fcea81b719b025850350324a722366 Mon Sep 17 00:00:00 2001 From: Zubair Lutfullah Kakakhel Date: Wed, 16 Jul 2014 16:51:30 +0100 Subject: arm64: use generic dma-contiguous.h dma-contiguous.h is now in asm-generic. Use that to avoid code repetition in arm64. Signed-off-by: Zubair Lutfullah Kakakhel Acked-by: Michal Nazarewicz Acked-by: Catalin Marinas Cc: will.deacon@arm.com Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: arnd@arndb.de Cc: gregkh@linuxfoundation.org Cc: m.szyprowski@samsung.com Cc: x86@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-arch@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7358/ Signed-off-by: Ralf Baechle --- arch/arm64/include/asm/Kbuild | 1 + arch/arm64/include/asm/dma-contiguous.h | 28 ---------------------------- 2 files changed, 1 insertion(+), 28 deletions(-) delete mode 100644 arch/arm64/include/asm/dma-contiguous.h diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild index 0b3fcf86e6ba..92bf7cb0e2c2 100644 --- a/arch/arm64/include/asm/Kbuild +++ b/arch/arm64/include/asm/Kbuild @@ -9,6 +9,7 @@ generic-y += current.h generic-y += delay.h generic-y += div64.h generic-y += dma.h +generic-y += dma-contiguous.h generic-y += emergency-restart.h generic-y += early_ioremap.h generic-y += errno.h diff --git a/arch/arm64/include/asm/dma-contiguous.h b/arch/arm64/include/asm/dma-contiguous.h deleted file mode 100644 index 14c4c0ca7f2a..000000000000 --- a/arch/arm64/include/asm/dma-contiguous.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _ASM_DMA_CONTIGUOUS_H -#define _ASM_DMA_CONTIGUOUS_H - -#ifdef __KERNEL__ -#ifdef CONFIG_DMA_CMA - -#include - -static inline void -dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { } - -#endif -#endif - -#endif -- cgit v1.2.3 From 8057b30814e1c90e9425bb7b3be868b55bf5435c Mon Sep 17 00:00:00 2001 From: Zubair Lutfullah Kakakhel Date: Wed, 16 Jul 2014 16:51:31 +0100 Subject: x86: use generic dma-contiguous.h dma-contiguous.h is now in asm-generic. Use that to avoid code repetition in x86. Signed-off-by: Zubair Lutfullah Kakakhel Acked-by: Michal Nazarewicz Cc: catalin.marinas@arm.com Cc: will.deacon@arm.com Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: arnd@arndb.de Cc: gregkh@linuxfoundation.org Cc: m.szyprowski@samsung.com Cc: x86@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-arch@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7359/ Signed-off-by: Ralf Baechle --- arch/x86/include/asm/Kbuild | 1 + arch/x86/include/asm/dma-contiguous.h | 12 ------------ 2 files changed, 1 insertion(+), 12 deletions(-) delete mode 100644 arch/x86/include/asm/dma-contiguous.h diff --git a/arch/x86/include/asm/Kbuild b/arch/x86/include/asm/Kbuild index 3bf000fab0ae..d55a210a49bf 100644 --- a/arch/x86/include/asm/Kbuild +++ b/arch/x86/include/asm/Kbuild @@ -6,6 +6,7 @@ genhdr-y += unistd_x32.h generic-y += clkdev.h generic-y += cputime.h +generic-y += dma-contiguous.h generic-y += early_ioremap.h generic-y += mcs_spinlock.h generic-y += scatterlist.h diff --git a/arch/x86/include/asm/dma-contiguous.h b/arch/x86/include/asm/dma-contiguous.h deleted file mode 100644 index b4b38bacb404..000000000000 --- a/arch/x86/include/asm/dma-contiguous.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef ASMX86_DMA_CONTIGUOUS_H -#define ASMX86_DMA_CONTIGUOUS_H - -#ifdef __KERNEL__ - -#include - -static inline void -dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { } - -#endif -#endif -- cgit v1.2.3 From f46493826a79f6a2bf9d8a0030e627e0255bbf48 Mon Sep 17 00:00:00 2001 From: Zubair Lutfullah Kakakhel Date: Wed, 16 Jul 2014 16:51:32 +0100 Subject: MIPS: DMA: Add cma support Adds cma support to the MIPS architecture. cma uses memblock. However, mips uses bootmem. bootmem is informed about any regions reserved by memblock dma api is modified to use cma reserved memory regions when available Tested using cma_test. cma_test is a simple driver that assigns blocks of memory from cma reserved sections. Signed-off-by: Zubair Lutfullah Kakakhel Acked-by: Michal Nazarewicz Cc: catalin.marinas@arm.com Cc: will.deacon@arm.com Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: arnd@arndb.de Cc: gregkh@linuxfoundation.org Cc: m.szyprowski@samsung.com Cc: x86@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-arch@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7360/ Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 1 + arch/mips/include/asm/Kbuild | 1 + arch/mips/kernel/setup.c | 9 +++++++++ arch/mips/mm/dma-default.c | 37 +++++++++++++++++++++++++------------ 4 files changed, 36 insertions(+), 12 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d7c8bd4e2f0e..ad6badb6be71 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -29,6 +29,7 @@ config MIPS select GENERIC_ATOMIC64 if !64BIT select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select HAVE_DMA_ATTRS + select HAVE_DMA_CONTIGUOUS select HAVE_DMA_API_DEBUG select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 335e5290ec75..c0b09571a7a5 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -1,6 +1,7 @@ # MIPS headers generic-y += cputime.h generic-y += current.h +generic-y += dma-contiguous.h generic-y += emergency-restart.h generic-y += hash.h generic-y += local64.h diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 7c1fe2b42d40..b3b8f0d9d4a7 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include @@ -476,6 +478,7 @@ static void __init bootmem_init(void) * o bootmem_init() * o sparse_init() * o paging_init() + * o dma_continguous_reserve() * * At this stage the bootmem allocator is ready to use. * @@ -609,6 +612,7 @@ static void __init request_crashkernel(struct resource *res) static void __init arch_mem_init(char **cmdline_p) { + struct memblock_region *reg; extern void plat_mem_setup(void); /* call board setup routine */ @@ -675,6 +679,11 @@ static void __init arch_mem_init(char **cmdline_p) sparse_init(); plat_swiotlb_setup(); paging_init(); + + dma_contiguous_reserve(PFN_PHYS(max_low_pfn)); + /* Tell bootmem about cma reserved memblock section */ + for_each_memblock(reserved, reg) + reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT); } static void __init resource_init(void) diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 44b6dff5aba2..33ba3c558fe4 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -128,23 +129,30 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) { void *ret; + struct page *page = NULL; + unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) return ret; gfp = massage_gfp_flags(dev, gfp); - ret = (void *) __get_free_pages(gfp, get_order(size)); - - if (ret) { - memset(ret, 0, size); - *dma_handle = plat_map_dma_mem(dev, ret, size); - - if (!plat_device_is_coherent(dev)) { - dma_cache_wback_inv((unsigned long) ret, size); - if (!hw_coherentio) - ret = UNCAC_ADDR(ret); - } + if (IS_ENABLED(CONFIG_DMA_CMA) && !(gfp & GFP_ATOMIC)) + page = dma_alloc_from_contiguous(dev, + count, get_order(size)); + if (!page) + page = alloc_pages(gfp, get_order(size)); + + if (!page) + return NULL; + + ret = page_address(page); + memset(ret, 0, size); + *dma_handle = plat_map_dma_mem(dev, ret, size); + if (!plat_device_is_coherent(dev)) { + dma_cache_wback_inv((unsigned long) ret, size); + if (!hw_coherentio) + ret = UNCAC_ADDR(ret); } return ret; @@ -164,6 +172,8 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, { unsigned long addr = (unsigned long) vaddr; int order = get_order(size); + unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; + struct page *page = NULL; if (dma_release_from_coherent(dev, order, vaddr)) return; @@ -173,7 +183,10 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, if (!plat_device_is_coherent(dev) && !hw_coherentio) addr = CAC_ADDR(addr); - free_pages(addr, get_order(size)); + page = virt_to_page((void *) addr); + + if (!dma_release_from_contiguous(dev, page, count)) + __free_pages(page, get_order(size)); } static inline void __dma_sync_virtual(void *addr, size_t size, -- cgit v1.2.3 From fb02035083d9e2de1deba529b45835a698944f07 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Fri, 18 Jul 2014 10:51:30 +0100 Subject: MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks Define all the CCA bits outside the ifdef blocks for specific cores but also allow cores to override them if necessary. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7400/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/pgtable-bits.h | 41 ++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index e592f3687d6f..011b0dcf306e 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -224,38 +224,47 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) #define _CACHE_CACHABLE_NONCOHERENT 0 +#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED #elif defined(CONFIG_CPU_SB1) /* No penalty for being coherent on the SB1, so just use it for "noncoherent" spaces, too. Shouldn't hurt. */ -#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) -#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) -#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) #elif defined(CONFIG_CPU_LOONGSON3) /* Using COHERENT flag for NONCOHERENT doesn't hurt. */ -#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* LOONGSON */ #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ -#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* LOONGSON */ -#else - -#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ -#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ -#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ -#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ -#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ +#endif +#ifndef _CACHE_CACHABLE_NO_WA +#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_WA +#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_UNCACHED +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_NONCOHERENT +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_CE +#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_COW +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_CACHABLE_CUW +#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) +#endif +#ifndef _CACHE_UNCACHED_ACCELERATED +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) #endif #define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) -- cgit v1.2.3 From 80bc94d10466c710158d5f30c43625ed9fa59e78 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Fri, 18 Jul 2014 10:51:31 +0100 Subject: MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores Ingenic uses the CCA:1 bit to achieve write-combine memory writes. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7401/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/pgtable-bits.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 011b0dcf306e..e747bfa0be7e 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ +#elif defined(CONFIG_MACH_JZ4740) + +/* Ingenic uses the WA bit to achieve write-combine memory writes */ +#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) + #endif #ifndef _CACHE_CACHABLE_NO_WA -- cgit v1.2.3 From 4f12b91d2da577d81c580da62373fd37b31e0da1 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Fri, 18 Jul 2014 10:51:32 +0100 Subject: MIPS: cpu-probe: Set the write-combine CCA value on per core basis Different cores use different CCA values to achieve write-combine memory writes. For cores that do not support write-combine we set the default value to CCA:2 (uncached, non-coherent) which is the default value as set by the kernel. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7402/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu-info.h | 5 +++++ arch/mips/kernel/cpu-probe.c | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index d5f42c168001..a6c9ccb33c5c 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -79,6 +79,11 @@ struct cpuinfo_mips { #define NUM_WATCH_REGS 4 u16 watch_reg_masks[NUM_WATCH_REGS]; unsigned int kscratch_mask; /* Usable KScratch mask. */ + /* + * Cache Coherency attribute for write-combine memory writes. + * (shifted by _CACHE_SHIFT) + */ + unsigned int writecombine; } __attribute__((aligned(SMP_CACHE_BYTES))); extern struct cpuinfo_mips cpu_data[]; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index e34b10be782e..94c4a0c0a577 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -764,6 +765,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) break; case PRID_REV_LOONGSON3A: c->cputype = CPU_LOONGSON3; + c->writecombine = _CACHE_UNCACHED_ACCELERATED; __cpu_name[cpu] = "ICT Loongson-3"; set_elf_platform(cpu, "loongson3a"); break; @@ -798,67 +800,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { + c->writecombine = _CACHE_UNCACHED_ACCELERATED; switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_4KC: c->cputype = CPU_4KC; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 4Kc"; break; case PRID_IMP_4KEC: case PRID_IMP_4KECR2: c->cputype = CPU_4KEC; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 4KEc"; break; case PRID_IMP_4KSC: case PRID_IMP_4KSD: c->cputype = CPU_4KSC; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 4KSc"; break; case PRID_IMP_5KC: c->cputype = CPU_5KC; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 5Kc"; break; case PRID_IMP_5KE: c->cputype = CPU_5KE; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 5KE"; break; case PRID_IMP_20KC: c->cputype = CPU_20KC; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 20Kc"; break; case PRID_IMP_24K: c->cputype = CPU_24K; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 24Kc"; break; case PRID_IMP_24KE: c->cputype = CPU_24K; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 24KEc"; break; case PRID_IMP_25KF: c->cputype = CPU_25KF; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 25Kc"; break; case PRID_IMP_34K: c->cputype = CPU_34K; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 34Kc"; break; case PRID_IMP_74K: c->cputype = CPU_74K; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 74Kc"; break; case PRID_IMP_M14KC: c->cputype = CPU_M14KC; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS M14Kc"; break; case PRID_IMP_M14KEC: c->cputype = CPU_M14KEC; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS M14KEc"; break; case PRID_IMP_1004K: c->cputype = CPU_1004K; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 1004Kc"; break; case PRID_IMP_1074K: c->cputype = CPU_1074K; + c->writecombine = _CACHE_UNCACHED; __cpu_name[cpu] = "MIPS 1074Kc"; break; case PRID_IMP_INTERAPTIV_UP: @@ -932,6 +950,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); + c->writecombine = _CACHE_UNCACHED_ACCELERATED; switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_SB1: c->cputype = CPU_SB1; @@ -1063,6 +1082,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_JZRISC: c->cputype = CPU_JZRISC; + c->writecombine = _CACHE_UNCACHED_ACCELERATED; __cpu_name[cpu] = "Ingenic JZRISC"; break; default: @@ -1169,6 +1189,7 @@ void cpu_probe(void) c->processor_id = PRID_IMP_UNKNOWN; c->fpu_id = FPIR_IMP_NONE; c->cputype = CPU_UNKNOWN; + c->writecombine = _CACHE_UNCACHED; c->processor_id = read_c0_prid(); switch (c->processor_id & PRID_COMP_MASK) { -- cgit v1.2.3 From 4b050ba7a66c3ff26cc329ea4db0e9fb2d66a064 Mon Sep 17 00:00:00 2001 From: Markos Chandras Date: Fri, 18 Jul 2014 10:51:33 +0100 Subject: MIPS: pgtable.h: Implement the pgprot_writecombine function for MIPS Previously, the pgprot_writecombine function was simply defined as pgprot_uncached in include/asm-generic/pgtable.h. This is not optimal for cores that can actually do write-combine memory writes so define this function to take into account the core's cache coherency attribute to achieve such behavior. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7403/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/pgtable.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index df49a308085c..d6d1928539b1 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -366,6 +366,16 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot) return __pgprot(prot); } +static inline pgprot_t pgprot_writecombine(pgprot_t _prot) +{ + unsigned long prot = pgprot_val(_prot); + + /* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */ + prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine; + + return __pgprot(prot); +} + /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. -- cgit v1.2.3 From 31d6f57d3c65fd75c18ea9a3acebedc6cd60d656 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Sat, 27 Sep 2014 08:31:05 +0200 Subject: MIPS: ralink: remove deprecated IRQF_DISABLED Remove the use of the IRQF_DISABLED flag from arch/mips/ralink/timer.c It's a NOOP since 2.6.35 and it will be removed soon. Signed-off-by: Michael Opdenacker Cc: akpm@linux-foundation.org Cc: jkosina@suse.cz Cc: standby24x7@gmail.com Cc: rdunlap@infradead.org Cc: yongjun_wei@trendmicro.com.cn Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7886/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c index e38692a44e69..5bb29b3790ff 100644 --- a/arch/mips/ralink/timer.c +++ b/arch/mips/ralink/timer.c @@ -58,7 +58,7 @@ static irqreturn_t rt_timer_irq(int irq, void *_rt) static int rt_timer_request(struct rt_timer *rt) { - int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED, + int err = request_irq(rt->irq, rt_timer_irq, 0, dev_name(rt->dev), rt); if (err) { dev_err(rt->dev, "failed to request irq\n"); -- cgit v1.2.3