From f24284adcdeae963aacf0c9b17979c875069cd80 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Fri, 24 Feb 2006 21:37:50 +0000 Subject: [ARM] noMMU: block sys_fork in nommu mode The sys_fork is not supported in nommu mode. The other syscalls that is not supported in nommu mode are to be defined as cond_signal in kernel/sys_ni.c. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/kernel/sys_arm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index a491de2d9024..8170af471439 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -234,7 +234,12 @@ asmlinkage int sys_ipc(uint call, int first, int second, int third, */ asmlinkage int sys_fork(struct pt_regs *regs) { +#ifdef CONFIG_MMU return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL); +#else + /* can not support in nommu mode */ + return(-EINVAL); +#endif } /* Clone a task - this clones the calling program thread. -- cgit v1.2.3 From 0157903e840f970c90880426505cbb8be5ddde68 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Fri, 24 Feb 2006 21:41:25 +0000 Subject: [ARM] noMMU: removes TLB codes in nommu mode This patch removes TLB related codes in nommu mode. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- include/asm-arm/tlb.h | 9 +++++++++ include/asm-arm/tlbflush.h | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h index f49bfb78c221..cb740025d413 100644 --- a/include/asm-arm/tlb.h +++ b/include/asm-arm/tlb.h @@ -19,6 +19,14 @@ #include #include + +#ifndef CONFIG_MMU + +#include +#include + +#else /* !CONFIG_MMU */ + #include /* @@ -82,4 +90,5 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) #define tlb_migrate_finish(mm) do { } while (0) +#endif /* CONFIG_MMU */ #endif diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index 0c2acc944a0a..d64b180200fa 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -11,6 +11,13 @@ #define _ASMARM_TLBFLUSH_H #include + +#ifndef CONFIG_MMU + +#define tlb_flush(tlb) ((void) tlb) + +#else /* CONFIG_MMY */ + #include #define TLB_V3_PAGE (1 << 0) @@ -423,4 +430,6 @@ extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte #endif +#endif /* CONFIG_MMU */ + #endif -- cgit v1.2.3 From fb1c7762b9b1f3c53daf0e700e977d77a29bcf04 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 24 Feb 2006 21:44:56 +0000 Subject: [ARM] Fix typo in tlbflush.h s/CONFIG_MMY/CONFIG_MMU/ Signed-off-by: Russell King --- include/asm-arm/tlbflush.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index d64b180200fa..728992451dd1 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -16,7 +16,7 @@ #define tlb_flush(tlb) ((void) tlb) -#else /* CONFIG_MMY */ +#else /* CONFIG_MMU */ #include -- cgit v1.2.3 From 0f44ba1d1e67201c0c58af26eb441fa7014c89ec Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 24 Feb 2006 21:04:56 +0000 Subject: [ARM] Move read of processor ID out of lookup_processor_type() Read the processor ID at boot, and save it in "processor_id" as we did before. Later, when we re-parse the CPU type in the setup.c code, re-use the value stored in "processor_id". This allows a cleaner work-around for noMMU devices without CP#15. Signed-off-by: Russell King --- arch/arm/kernel/head.S | 15 +++++++++------ arch/arm/kernel/setup.c | 4 ++-- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 1aca1775b28f..571d6d584919 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -82,6 +82,7 @@ ENTRY(stext) msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode @ and irqs disabled + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? beq __error_p @ yes, error 'p' @@ -156,6 +157,7 @@ ENTRY(secondary_startup) * as it has already been validated by the primary processor. */ msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type movs r10, r5 @ invalid processor? moveq r0, #'p' @ yes, error 'p' @@ -450,19 +452,19 @@ __error: * (and therefore, we are not in the correct address space). We have to * calculate the offset. * + * r9 = cpuid * Returns: * r3, r4, r6 corrupted * r5 = proc_info pointer in physical address space - * r9 = cpuid + * r9 = cpuid (preserved) */ .type __lookup_processor_type, %function __lookup_processor_type: adr r3, 3f - ldmda r3, {r5, r6, r9} - sub r3, r3, r9 @ get offset between virt&phys + ldmda r3, {r5 - r7} + sub r3, r3, r7 @ get offset between virt&phys add r5, r5, r3 @ convert virt addresses to add r6, r6, r3 @ physical address space - mrc p15, 0, r9, c0, c0 @ get processor id 1: ldmia r5, {r3, r4} @ value, mask and r4, r4, r9 @ mask wanted bits teq r3, r4 @@ -477,10 +479,11 @@ __lookup_processor_type: * This provides a C-API version of the above function. */ ENTRY(lookup_processor_type) - stmfd sp!, {r4 - r6, r9, lr} + stmfd sp!, {r4 - r7, r9, lr} + mov r9, r0 bl __lookup_processor_type mov r0, r5 - ldmfd sp!, {r4 - r6, r9, pc} + ldmfd sp!, {r4 - r7, r9, pc} /* * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 08974cbe9824..b7cd280bfd63 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -278,7 +278,7 @@ int cpu_architecture(void) * These functions re-use the assembly code in head.S, which * already provide the required functionality. */ -extern struct proc_info_list *lookup_processor_type(void); +extern struct proc_info_list *lookup_processor_type(unsigned int); extern struct machine_desc *lookup_machine_type(unsigned int); static void __init setup_processor(void) @@ -290,7 +290,7 @@ static void __init setup_processor(void) * types. The linker builds this table for us from the * entries in arch/arm/mm/proc-*.S */ - list = lookup_processor_type(); + list = lookup_processor_type(processor_id); if (!list) { printk("CPU configuration botched (ID %08x), unable " "to continue.\n", processor_id); -- cgit v1.2.3 From 74945c8616a50074277e18641baaae7464006766 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 16 Mar 2006 14:44:36 +0000 Subject: [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h Move the hardware PMD and PTE page table definitions from pgtable.h into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary. Signed-off-by: Russell King --- arch/arm/mach-sa1100/assabet.c | 1 + arch/arm/mm/proc-arm1020.S | 1 + arch/arm/mm/proc-arm1020e.S | 1 + arch/arm/mm/proc-arm1022.S | 1 + arch/arm/mm/proc-arm1026.S | 1 + arch/arm/mm/proc-arm6_7.S | 1 + arch/arm/mm/proc-arm720.S | 1 + arch/arm/mm/proc-arm920.S | 1 + arch/arm/mm/proc-arm922.S | 1 + arch/arm/mm/proc-arm925.S | 1 + arch/arm/mm/proc-arm926.S | 1 + arch/arm/mm/proc-sa110.S | 1 + arch/arm/mm/proc-sa1100.S | 1 + arch/arm/mm/proc-v6.S | 1 + arch/arm/mm/proc-xscale.S | 1 + include/asm-arm/pgalloc.h | 5 +++ include/asm-arm/pgtable-hwdef.h | 88 +++++++++++++++++++++++++++++++++++++++++ include/asm-arm/pgtable.h | 80 ------------------------------------- 18 files changed, 108 insertions(+), 80 deletions(-) create mode 100644 include/asm-arm/pgtable-hwdef.h diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index a599bb0d4ab8..c58f12ba7a93 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 82ec954e45b6..5f460d717253 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 7375fe930f72..3e5ea5508839 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 6ca639094d6f..f778545d57a2 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 10317e4f55d2..148c111fde73 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 8e7e1e70ab05..540359b475d0 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index a13e0184d343..72b0819326db 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index d16513899999..e57d3b8de4b7 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 23b8ed97f4e3..3170b37f82f2 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index ee95c52db513..eb78850addaa 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 7d042dc20c47..23ad5027d90c 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index bd330c4075a1..c916a6cae404 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 91b89124c0d7..41f21f2dd8ff 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -23,6 +23,7 @@ #include #include #include +#include #include /* diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 92f3ca31b7b9..9a7e7c096aa9 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "proc-macros.S" diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 2d3823ec3153..3e7e6a8f4109 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h index bc18ff405181..c4ac2e67768d 100644 --- a/include/asm-arm/pgalloc.h +++ b/include/asm-arm/pgalloc.h @@ -10,10 +10,15 @@ #ifndef _ASMARM_PGALLOC_H #define _ASMARM_PGALLOC_H +#include +#include #include #include #include +#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) +#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) + /* * Since we have only two-level page tables, these are trivial */ diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h new file mode 100644 index 000000000000..1d033495cc75 --- /dev/null +++ b/include/asm-arm/pgtable-hwdef.h @@ -0,0 +1,88 @@ +/* + * linux/include/asm-arm/pgtable-hwdef.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ASMARM_PGTABLE_HWDEF_H +#define _ASMARM_PGTABLE_HWDEF_H + +/* + * Hardware page table definitions. + * + * + Level 1 descriptor (PMD) + * - common + */ +#define PMD_TYPE_MASK (3 << 0) +#define PMD_TYPE_FAULT (0 << 0) +#define PMD_TYPE_TABLE (1 << 0) +#define PMD_TYPE_SECT (2 << 0) +#define PMD_BIT4 (1 << 4) +#define PMD_DOMAIN(x) ((x) << 5) +#define PMD_PROTECTION (1 << 9) /* v5 */ +/* + * - section + */ +#define PMD_SECT_BUFFERABLE (1 << 2) +#define PMD_SECT_CACHEABLE (1 << 3) +#define PMD_SECT_AP_WRITE (1 << 10) +#define PMD_SECT_AP_READ (1 << 11) +#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ +#define PMD_SECT_APX (1 << 15) /* v6 */ +#define PMD_SECT_S (1 << 16) /* v6 */ +#define PMD_SECT_nG (1 << 17) /* v6 */ +#define PMD_SECT_SUPER (1 << 18) /* v6 */ + +#define PMD_SECT_UNCACHED (0) +#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) +#define PMD_SECT_WT (PMD_SECT_CACHEABLE) +#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) +#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) + +/* + * - coarse table (not used) + */ + +/* + * + Level 2 descriptor (PTE) + * - common + */ +#define PTE_TYPE_MASK (3 << 0) +#define PTE_TYPE_FAULT (0 << 0) +#define PTE_TYPE_LARGE (1 << 0) +#define PTE_TYPE_SMALL (2 << 0) +#define PTE_TYPE_EXT (3 << 0) /* v5 */ +#define PTE_BUFFERABLE (1 << 2) +#define PTE_CACHEABLE (1 << 3) + +/* + * - extended small page/tiny page + */ +#define PTE_EXT_XN (1 << 0) /* v6 */ +#define PTE_EXT_AP_MASK (3 << 4) +#define PTE_EXT_AP0 (1 << 4) +#define PTE_EXT_AP1 (2 << 4) +#define PTE_EXT_AP_UNO_SRO (0 << 4) +#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) +#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) +#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) +#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ +#define PTE_EXT_APX (1 << 9) /* v6 */ +#define PTE_EXT_SHARED (1 << 10) /* v6 */ +#define PTE_EXT_NG (1 << 11) /* v6 */ + +/* + * - small page + */ +#define PTE_SMALL_AP_MASK (0xff << 4) +#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) +#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) +#define PTE_SMALL_AP_URO_SRW (0xaa << 4) +#define PTE_SMALL_AP_URW_SRW (0xff << 4) + +#endif diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 70e00d08345e..e595ae24efe2 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -136,81 +136,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) -/* - * Hardware page table definitions. - * - * + Level 1 descriptor (PMD) - * - common - */ -#define PMD_TYPE_MASK (3 << 0) -#define PMD_TYPE_FAULT (0 << 0) -#define PMD_TYPE_TABLE (1 << 0) -#define PMD_TYPE_SECT (2 << 0) -#define PMD_BIT4 (1 << 4) -#define PMD_DOMAIN(x) ((x) << 5) -#define PMD_PROTECTION (1 << 9) /* v5 */ -/* - * - section - */ -#define PMD_SECT_BUFFERABLE (1 << 2) -#define PMD_SECT_CACHEABLE (1 << 3) -#define PMD_SECT_AP_WRITE (1 << 10) -#define PMD_SECT_AP_READ (1 << 11) -#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ -#define PMD_SECT_APX (1 << 15) /* v6 */ -#define PMD_SECT_S (1 << 16) /* v6 */ -#define PMD_SECT_nG (1 << 17) /* v6 */ -#define PMD_SECT_SUPER (1 << 18) /* v6 */ - -#define PMD_SECT_UNCACHED (0) -#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) -#define PMD_SECT_WT (PMD_SECT_CACHEABLE) -#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) -#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) - -/* - * - coarse table (not used) - */ - -/* - * + Level 2 descriptor (PTE) - * - common - */ -#define PTE_TYPE_MASK (3 << 0) -#define PTE_TYPE_FAULT (0 << 0) -#define PTE_TYPE_LARGE (1 << 0) -#define PTE_TYPE_SMALL (2 << 0) -#define PTE_TYPE_EXT (3 << 0) /* v5 */ -#define PTE_BUFFERABLE (1 << 2) -#define PTE_CACHEABLE (1 << 3) - -/* - * - extended small page/tiny page - */ -#define PTE_EXT_XN (1 << 0) /* v6 */ -#define PTE_EXT_AP_MASK (3 << 4) -#define PTE_EXT_AP0 (1 << 4) -#define PTE_EXT_AP1 (2 << 4) -#define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) -#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) -#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) -#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ -#define PTE_EXT_APX (1 << 9) /* v6 */ -#define PTE_EXT_SHARED (1 << 10) /* v6 */ -#define PTE_EXT_NG (1 << 11) /* v6 */ - -/* - * - small page - */ -#define PTE_SMALL_AP_MASK (0xff << 4) -#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) -#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) -#define PTE_SMALL_AP_URO_SRW (0xaa << 4) -#define PTE_SMALL_AP_URW_SRW (0xff << 4) - /* * "Linux" PTE definitions. * @@ -236,11 +161,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #ifndef __ASSEMBLY__ -#include - -#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) -#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) - /* * The following macros handle the cache and bufferable bits... */ -- cgit v1.2.3 From 48fa14f7618fe89cac9b807b05b66df4b595fc7e Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 16 Mar 2006 14:52:33 +0000 Subject: [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG Rather than having a growing dependency line, use select to set these configuration symbols. Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 3b79d0e23455..57a48d92ac41 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -266,12 +266,18 @@ config CPU_32v6K # This defines the compiler instruction set which depends on the machine type. config CPU_32v3 bool + select TLS_REG_EMUL if SMP + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v4 bool + select TLS_REG_EMUL if SMP + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v5 bool + select TLS_REG_EMUL if SMP + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v6 bool @@ -417,7 +423,6 @@ config CPU_BPREDICT_DISABLE config TLS_REG_EMUL bool - default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3) help An SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to @@ -436,7 +441,6 @@ config HAS_TLS_REG config NEEDS_SYSCALL_FOR_CMPXCHG bool - default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3) help SMP on a pre-ARMv6 processor? Well OK then. Forget about fast user space cmpxchg support. -- cgit v1.2.3 From 7d420896256a4bffe44202f282fbdd4c74d779a8 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 23 Mar 2006 12:59:08 +0000 Subject: [ARM] 3391/1: use PLAT8250_DEV_PLATFORM{,1} for platform device id instead of 0/1 Patch from Lennert Buytenhek This patch changes iop3xx and omap2 and to use PLAT8250_DEV_PLATFORM{,1} as platform device id instead of just hardcoding 0/1 directly. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop3xx/iop331-setup.c | 4 ++-- arch/arm/mach-omap2/serial.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-iop3xx/iop331-setup.c b/arch/arm/mach-iop3xx/iop331-setup.c index 2d6abe5be14d..7b7b6eea3846 100644 --- a/arch/arm/mach-iop3xx/iop331-setup.c +++ b/arch/arm/mach-iop3xx/iop331-setup.c @@ -103,7 +103,7 @@ static struct plat_serial8250_port iop33x_uart1_data[] = { static struct platform_device iop33x_uart0 = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev.platform_data = iop33x_uart0_data, .num_resources = 2, .resource = iop33x_uart0_resources, @@ -111,7 +111,7 @@ static struct platform_device iop33x_uart0 = { static struct platform_device iop33x_uart1 = { .name = "serial8250", - .id = 1, + .id = PLAT8250_DEV_PLATFORM1, .dev.platform_data = iop33x_uart1_data, .num_resources = 2, .resource = iop33x_uart1_resources, diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 24dd374224af..0884bc7c23b7 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -167,7 +167,7 @@ void __init omap_serial_init() static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, -- cgit v1.2.3 From 9c42954dfd50d02963cd453fb84bfef3967af2f0 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 23 Mar 2006 16:59:37 +0000 Subject: [ARM] Move enable_irq and disable_irq to assembler.h 5d25ac038a317d454a4321cba955f756400835a5 broke VFP builds due to enable_irq not being defined as an assembly macro. Move it to assembler.h so everyone can use it. Signed-off-by: Russell King --- arch/arm/kernel/entry-header.S | 18 ------------------ arch/arm/vfp/entry.S | 1 + include/asm-arm/assembler.h | 27 ++++++++++++++++++++++----- 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 55c99cdab7d6..f1c2fd5b63e4 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -37,24 +37,6 @@ #endif .endm -#if __LINUX_ARM_ARCH__ >= 6 - .macro disable_irq - cpsid i - .endm - - .macro enable_irq - cpsie i - .endm -#else - .macro disable_irq - msr cpsr_c, #PSR_I_BIT | SVC_MODE - .endm - - .macro enable_irq - msr cpsr_c, #SVC_MODE - .endm -#endif - .macro get_thread_info, rd mov \rd, sp, lsr #13 mov \rd, \rd, lsl #13 diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index 9ab1abfbe7ad..7b595547c1c8 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -18,6 +18,7 @@ #include #include #include +#include #include .globl do_vfp diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index f31ac92b6c7f..d53bafa9bf1c 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h @@ -80,16 +80,33 @@ instr regs /* - * Save the current IRQ state and disable IRQs. Note that this macro - * assumes FIQs are enabled, and that the processor is in SVC mode. + * Enable and disable interrupts */ - .macro save_and_disable_irqs, oldcpsr - mrs \oldcpsr, cpsr #if __LINUX_ARM_ARCH__ >= 6 + .macro disable_irq cpsid i + .endm + + .macro enable_irq + cpsie i + .endm #else - msr cpsr_c, #PSR_I_BIT | MODE_SVC + .macro disable_irq + msr cpsr_c, #PSR_I_BIT | SVC_MODE + .endm + + .macro enable_irq + msr cpsr_c, #SVC_MODE + .endm #endif + +/* + * Save the current IRQ state and disable IRQs. Note that this macro + * assumes FIQs are enabled, and that the processor is in SVC mode. + */ + .macro save_and_disable_irqs, oldcpsr + mrs \oldcpsr, cpsr + disable_irq .endm /* -- cgit v1.2.3 From c76b6b41d0ae29e1127d9f81cb687cabda57c14c Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Fri, 24 Mar 2006 09:53:18 +0000 Subject: [ARM] nommu: rename compressed/head.S symbols to a new style This patch renames symbols to a new style to prepare mpu support code merging. e.g. __armv4_cache_on --> __armv4_mmu_cache_on Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 82 ++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index db3389d8e027..491c7e4c9ac6 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -358,7 +358,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size str r1, [r0] mov pc, lr -__armv4_cache_on: +__armv4_mmu_cache_on: mov r12, lr bl __setup_mmu mov r0, #0 @@ -367,24 +367,24 @@ __armv4_cache_on: mrc p15, 0, r0, c1, c0, 0 @ read control reg orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x0030 - bl __common_cache_on + bl __common_mmu_cache_on mov r0, #0 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs mov pc, r12 -__arm6_cache_on: +__arm6_mmu_cache_on: mov r12, lr bl __setup_mmu mov r0, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 mov r0, #0x30 - bl __common_cache_on + bl __common_mmu_cache_on mov r0, #0 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 mov pc, r12 -__common_cache_on: +__common_mmu_cache_on: #ifndef DEBUG orr r0, r0, #0x000d @ Write buffer, mmu #endif @@ -471,12 +471,12 @@ call_cache_fn: adr r12, proc_types proc_types: .word 0x41560600 @ ARM6/610 .word 0xffffffe0 - b __arm6_cache_off @ works, but slow - b __arm6_cache_off + b __arm6_mmu_cache_off @ works, but slow + b __arm6_mmu_cache_off mov pc, lr -@ b __arm6_cache_on @ untested -@ b __arm6_cache_off -@ b __armv3_cache_flush +@ b __arm6_mmu_cache_on @ untested +@ b __arm6_mmu_cache_off +@ b __armv3_mmu_cache_flush .word 0x00000000 @ old ARM ID .word 0x0000f000 @@ -486,14 +486,14 @@ proc_types: .word 0x41007000 @ ARM7/710 .word 0xfff8fe00 - b __arm7_cache_off - b __arm7_cache_off + b __arm7_mmu_cache_off + b __arm7_mmu_cache_off mov pc, lr .word 0x41807200 @ ARM720T (writethrough) .word 0xffffff00 - b __armv4_cache_on - b __armv4_cache_off + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off mov pc, lr .word 0x00007000 @ ARM7 IDs @@ -506,41 +506,41 @@ proc_types: .word 0x4401a100 @ sa110 / sa1100 .word 0xffffffe0 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush .word 0x6901b110 @ sa1110 .word 0xfffffff0 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush @ These match on the architecture ID .word 0x00020000 @ ARMv4T .word 0x000f0000 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush .word 0x00050000 @ ARMv5TE .word 0x000f0000 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush .word 0x00060000 @ ARMv5TEJ .word 0x000f0000 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush .word 0x00070000 @ ARMv6 .word 0x000f0000 - b __armv4_cache_on - b __armv4_cache_off - b __armv6_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv6_mmu_cache_flush .word 0 @ unrecognised type .word 0 @@ -562,7 +562,7 @@ proc_types: cache_off: mov r3, #12 @ cache_off function b call_cache_fn -__armv4_cache_off: +__armv4_mmu_cache_off: mrc p15, 0, r0, c1, c0 bic r0, r0, #0x000d mcr p15, 0, r0, c1, c0 @ turn MMU and cache off @@ -571,15 +571,15 @@ __armv4_cache_off: mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 mov pc, lr -__arm6_cache_off: +__arm6_mmu_cache_off: mov r0, #0x00000030 @ ARM6 control reg. - b __armv3_cache_off + b __armv3_mmu_cache_off -__arm7_cache_off: +__arm7_mmu_cache_off: mov r0, #0x00000070 @ ARM7 control reg. - b __armv3_cache_off + b __armv3_mmu_cache_off -__armv3_cache_off: +__armv3_mmu_cache_off: mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off mov r0, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 @@ -601,7 +601,7 @@ cache_clean_flush: mov r3, #16 b call_cache_fn -__armv6_cache_flush: +__armv6_mmu_cache_flush: mov r1, #0 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB @@ -609,7 +609,7 @@ __armv6_cache_flush: mcr p15, 0, r1, c7, c10, 4 @ drain WB mov pc, lr -__armv4_cache_flush: +__armv4_mmu_cache_flush: mov r2, #64*1024 @ default: 32K dcache size (*2) mov r11, #32 @ default: 32 byte line size mrc p15, 0, r3, c0, c0, 1 @ read cache type @@ -637,7 +637,7 @@ no_cache_id: mcr p15, 0, r1, c7, c10, 4 @ drain WB mov pc, lr -__armv3_cache_flush: +__armv3_mmu_cache_flush: mov r1, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr -- cgit v1.2.3 From 686f8c5d77149f78ff6090dde774b2e43a7319b2 Mon Sep 17 00:00:00 2001 From: Todd Poynor Date: Sat, 25 Mar 2006 18:15:24 +0000 Subject: include/linux/clk.h is betraying its ARM origins include/linux/clk.h is betraying its ARM origins. Signed-off-by: Todd Poynor Signed-off-by: Russell King --- include/linux/clk.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/clk.h b/include/linux/clk.h index 12848f81bb37..5ca8c6fddb56 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -8,8 +8,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef ASMARM_CLOCK_H -#define ASMARM_CLOCK_H +#ifndef __LINUX_CLK_H +#define __LINUX_CLK_H struct device; -- cgit v1.2.3 From 091c539f08a6700e0cca8cd620c3d72dd9f9e2bb Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 25 Mar 2006 21:37:29 +0000 Subject: [ARM] SMP: don't set cpu_*_map in smp_prepare_boot_cpu The recent addition of boot_cpu_init() implements the initialisation of the online, present and possible cpu maps for the boot CPU, so there is no reason to duplicate this in the architecture smp_prepare_boot_cpu() hook. Signed-off-by: Russell King --- arch/arm/kernel/smp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 02aa300c4633..1370d726dc10 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -337,9 +337,6 @@ void __init smp_prepare_boot_cpu(void) unsigned int cpu = smp_processor_id(); per_cpu(cpu_data, cpu).idle = current; - - cpu_set(cpu, cpu_present_map); - cpu_set(cpu, cpu_online_map); } static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg) -- cgit v1.2.3 From 48a03ae863e0031def037fc828d7ea1a29b6fb7b Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Sat, 25 Mar 2006 21:57:57 +0000 Subject: [ARM] 3385/1: Battery support for sharp zaurus sl-5500 (collie) Patch from Pavel Machek This adds support for battery reading on collie. Collie slowly charges battery even with charging disabled, so I did not yet enable fast charge. Signed-off-by: Pavel Machek Signed-off-by: Russell King --- arch/arm/mach-sa1100/collie_pm.c | 278 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 278 insertions(+) create mode 100644 arch/arm/mach-sa1100/collie_pm.c diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c new file mode 100644 index 000000000000..696d7d29c8a5 --- /dev/null +++ b/arch/arm/mach-sa1100/collie_pm.c @@ -0,0 +1,278 @@ +/* + * Based on spitz_pm.c and sharp code. + * + * Copyright (C) 2001 SHARP + * Copyright 2005 Pavel Machek + * + * Distribute under GPLv2. + * + * Li-ion batteries are angry beasts, and they like to explode. This driver is not finished, + * and sometimes charges them when it should not. If it makes angry lithium to come your way... + * ...well, you have been warned. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../drivers/mfd/ucb1x00.h" + +static struct ucb1x00 *ucb; +static int ad_revise; + +#define ADCtoPower(x) ((330 * x * 2) / 1024) + +static void collie_charger_init(void) +{ + int err; + + if (sharpsl_param.adadj != -1) { + ad_revise = sharpsl_param.adadj; + } + + /* Register interrupt handler. */ + if ((err = request_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr, SA_INTERRUPT, + "ACIN", sharpsl_ac_isr))) { + printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_AC_IN); + return; + } + if ((err = request_irq(COLLIE_IRQ_GPIO_CO, sharpsl_chrg_full_isr, SA_INTERRUPT, + "CO", sharpsl_chrg_full_isr))) { + free_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr); + printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_CO); + return; + } + + ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON | + COLLIE_TC35143_GPIO_BBAT_ON); + return; +} + +static void collie_measure_temp(int on) +{ + if (on) + ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0); + else + ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON); +} + +static void collie_charge(int on) +{ + if (on) { + printk("Should start charger\n"); + } else { + printk("Should stop charger\n"); + } +#ifdef I_AM_SURE + + /* Zaurus seems to contain LTC1731 ; it should know when to + * stop charging itself, so setting charge on should be + * relatively harmless (as long as it is not done too often). + */ +#define CF_BUF_CTRL_BASE 0xF0800000 +#define SCOOP_REG(adr) (*(volatile unsigned short*)(CF_BUF_CTRL_BASE+(adr))) +#define SCOOP_REG_GPWR SCOOP_REG(SCOOP_GPWR) + + if (on) { + set_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON); + } else { + reset_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON); + } +#endif +} + +static void collie_discharge(int on) +{ +} + +static void collie_discharge1(int on) +{ +} + +static void collie_presuspend(void) +{ +} + +static void collie_postsuspend(void) +{ +} + +static int collie_should_wakeup(unsigned int resume_on_alarm) +{ + return 0; +} + +static unsigned long collie_charger_wakeup(void) +{ + return 0; +} + +int collie_read_backup_battery(void) +{ + int voltage; + + ucb1x00_adc_enable(ucb); + + /* Gives 75..130 */ + ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_BBAT_ON, 0); + voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC); + + ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON); + ucb1x00_adc_disable(ucb); + + printk("Backup battery = %d(%d)\n", ADCtoPower(voltage), voltage); + + return ADCtoPower(voltage); +} + +int collie_read_main_battery(void) +{ + int voltage, voltage_rev, voltage_volts; + + ucb1x00_adc_enable(ucb); + ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON); + ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_MBAT_ON, 0); + /* gives values 160..255 with battery removed... and + 145..255 with battery inserted. (on AC), goes as low as + 80 on DC. */ + voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC); + + ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON); + ucb1x00_adc_disable(ucb); + + voltage_rev = voltage + ((ad_revise * voltage) / 652); + voltage_volts = ADCtoPower(voltage_rev); + + printk("Main battery = %d(%d)\n", voltage_volts, voltage); + + if (voltage != -1) + return voltage_volts; + else + return voltage; +} + +int collie_read_temp(void) +{ + int voltage; + + /* According to Sharp, temp must be > 973, main battery must be < 465, + FIXME: sharpsl_pm.c has both conditions negated? FIXME: values + are way out of range? */ + + ucb1x00_adc_enable(ucb); + ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0); + /* >1010 = battery removed, 460 = 22C ?, higer = lower temp ? */ + voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD0, UCB_SYNC); + ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON); + ucb1x00_adc_disable(ucb); + + printk("Battery temp = %d\n", voltage); + return voltage; +} + +static unsigned long read_devdata(int which) +{ + switch (which) { + case SHARPSL_BATT_VOLT: + return collie_read_main_battery(); + case SHARPSL_BATT_TEMP: + return collie_read_temp(); + case SHARPSL_ACIN_VOLT: + return 0x1; + case SHARPSL_STATUS_ACIN: { + int ret = GPLR & COLLIE_GPIO_AC_IN; + printk("AC status = %d\n", ret); + return ret; + } + case SHARPSL_STATUS_FATAL: { + int ret = GPLR & COLLIE_GPIO_MAIN_BAT_LOW; + printk("Fatal bat = %d\n", ret); + return ret; + } + default: + return ~0; + } +} + +struct battery_thresh collie_battery_levels[] = { + { 368, 100}, + { 358, 25}, + { 356, 5}, + { 0, 0}, +}; + +struct sharpsl_charger_machinfo collie_pm_machinfo = { + .init = collie_charger_init, + .read_devdata = read_devdata, + .discharge = collie_discharge, + .discharge1 = collie_discharge1, + .charge = collie_charge, + .measure_temp = collie_measure_temp, + .presuspend = collie_presuspend, + .postsuspend = collie_postsuspend, + .charger_wakeup = collie_charger_wakeup, + .should_wakeup = collie_should_wakeup, + .bat_levels = 3, + .bat_levels_noac = collie_battery_levels, + .bat_levels_acin = collie_battery_levels, + .status_high_acin = 368, + .status_low_acin = 358, + .status_high_noac = 368, + .status_low_noac = 358, +}; + +static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev) +{ + sharpsl_pm.machinfo = &collie_pm_machinfo; + ucb = pdev->ucb; + return 0; +} + +static struct ucb1x00_driver collie_pm_ucb_driver = { + .add = collie_pm_ucb_add, +}; + +static struct platform_device *collie_pm_device; + +static int __init collie_pm_init(void) +{ + int ret; + + collie_pm_device = platform_device_alloc("sharpsl-pm", -1); + if (!collie_pm_device) + return -ENOMEM; + + collie_pm_device->dev.platform_data = &collie_pm_machinfo; + ret = platform_device_add(collie_pm_device); + + if (ret) + platform_device_put(collie_pm_device); + + if (!ret) + ret = ucb1x00_register_driver(&collie_pm_ucb_driver); + + return ret; +} + +static void __exit collie_pm_exit(void) +{ + ucb1x00_unregister_driver(&collie_pm_ucb_driver); + platform_device_unregister(collie_pm_device); +} + +module_init(collie_pm_init); +module_exit(collie_pm_exit); -- cgit v1.2.3 From 1310eda4bec331fd951a8cbe80619f050f9036fc Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Sat, 25 Mar 2006 21:57:59 +0000 Subject: [ARM] 3397/1: AT91RM9200 Header update Patch from Andrew Victor This patch updates the hardware header to include definitions for the Memory Controller registers. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91rm9200/at91rm9200_sys.h | 100 ++++++++++++++++++++++- 1 file changed, 99 insertions(+), 1 deletion(-) diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h index 9bfffdbf1e0b..2910d359f919 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h @@ -172,6 +172,7 @@ #define AT91_PMC_MDIV_4 (3 << 8) #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ + #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ @@ -286,8 +287,32 @@ #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ +#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ +#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ +#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ +#define AT91_MC_ABTSZ_BYTE (0 << 8) +#define AT91_MC_ABTSZ_HALFWORD (1 << 8) +#define AT91_MC_ABTSZ_WORD (2 << 8) +#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ +#define AT91_MC_ABTTYP_DATAREAD (0 << 10) +#define AT91_MC_ABTTYP_DATAWRITE (1 << 10) +#define AT91_MC_ABTTYP_FETCH (2 << 10) +#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ +#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ +#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ +#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ +#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ +#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ +#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ +#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ + #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ + #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ +#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ +#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ +#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ +#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ /* External Bus Interface (EBI) registers */ #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ @@ -309,8 +334,10 @@ /* Static Memory Controller (SMC) registers */ #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ +#define AT91_SMC_NWS_(x) ((x) << 0) #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ +#define AT91_SMC_TDF_(x) ((x) << 8) #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ #define AT91_SMC_DBW_16 (1 << 13) @@ -322,7 +349,78 @@ #define AT91_SMC_ACSS_2 (2 << 16) #define AT91_SMC_ACSS_3 (3 << 16) #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ +#define AT91_SMC_RWSETUP_(x) ((x) << 24) #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ - +#define AT91_SMC_RWHOLD_(x) ((x) << 28) + +/* SDRAM Controller registers */ +#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ +#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ +#define AT91_SDRAMC_MODE_NORMAL (0 << 0) +#define AT91_SDRAMC_MODE_NOP (1 << 0) +#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) +#define AT91_SDRAMC_MODE_LMR (3 << 0) +#define AT91_SDRAMC_MODE_REFRESH (4 << 0) +#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ +#define AT91_SDRAMC_DBW_32 (0 << 4) +#define AT91_SDRAMC_DBW_16 (1 << 4) + +#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ +#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ + +#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ +#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ +#define AT91_SDRAMC_NC_8 (0 << 0) +#define AT91_SDRAMC_NC_9 (1 << 0) +#define AT91_SDRAMC_NC_10 (2 << 0) +#define AT91_SDRAMC_NC_11 (3 << 0) +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_SDRAMC_NR_11 (0 << 2) +#define AT91_SDRAMC_NR_12 (1 << 2) +#define AT91_SDRAMC_NR_13 (2 << 2) +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ +#define AT91_SDRAMC_NB_2 (0 << 4) +#define AT91_SDRAMC_NB_4 (1 << 4) +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ +#define AT91_SDRAMC_CAS_2 (2 << 5) +#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ +#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ +#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ + +#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ +#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ +#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ + +/* Burst Flash Controller register */ +#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ +#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ +#define AT91_BFC_BFCOM_DISABLED (0 << 0) +#define AT91_BFC_BFCOM_ASYNC (1 << 0) +#define AT91_BFC_BFCOM_BURST (2 << 0) +#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ +#define AT91_BFC_BFCC_MCK (1 << 2) +#define AT91_BFC_BFCC_DIV2 (2 << 2) +#define AT91_BFC_BFCC_DIV4 (3 << 2) +#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ +#define AT91_BFC_PAGES (7 << 8) /* Page Size */ +#define AT91_BFC_PAGES_NO_PAGE (0 << 8) +#define AT91_BFC_PAGES_16 (1 << 8) +#define AT91_BFC_PAGES_32 (2 << 8) +#define AT91_BFC_PAGES_64 (3 << 8) +#define AT91_BFC_PAGES_128 (4 << 8) +#define AT91_BFC_PAGES_256 (5 << 8) +#define AT91_BFC_PAGES_512 (6 << 8) +#define AT91_BFC_PAGES_1024 (7 << 8) +#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ +#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ +#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ +#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ +#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ #endif -- cgit v1.2.3 From 80ed354725825035616fb369a8c38ff77494695c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 25 Mar 2006 21:58:00 +0000 Subject: [ARM] 3398/1: Fix the VFP registers loading/storing base address Patch from Catalin Marinas The current VFP code corrupts the VFP registers (including the control ones) if more than one floating point application is executed at the same time. This patch fixes the updating of the load/store base addresses for the VFP registers. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/vfp/vfphw.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index de4ca1223c58..b7ed57e00cd4 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -102,7 +102,6 @@ vfp_support_entry: VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading @ nonexistant reg on rev0 VFPFSTMIA r4 @ save the working registers - add r4, r4, #8*16+4 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 @ and point r4 at the word at the @ start of the register dump @@ -111,10 +110,9 @@ no_old_VFP_process: DBGSTR1 "load state %p", r10 str r10, [r3] @ update the last_VFP_context pointer @ Load the saved state back into the VFP - add r4, r10, #8*16+4 - ldmia r4, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 VFPFLDMIA r10 @ reload the working registers while @ FPEXC is in a safe state + ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write? VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing @ nonexistant reg on rev0 -- cgit v1.2.3 From 3ee357f0f38a5fddebab18500c290d3879a2d89c Mon Sep 17 00:00:00 2001 From: Malcolm Parsons Date: Sat, 25 Mar 2006 21:58:03 +0000 Subject: [ARM] 3399/1: Fix link problem when CONFIG_PRINTK is disabled Patch from Malcolm Parsons Printking a backtrace requires printk, so disable backtrace code when printk is disabled. Without this patch, a kernel with CONFIG_PRINTK disabled does not link: arch/arm/lib/lib.a(backtrace.o): In function `c_backtrace': arch/arm/lib/backtrace.S:(.text+0x108): undefined reference to `printk' arch/arm/lib/backtrace.S:(.text+0x11c): undefined reference to `printk' arch/arm/lib/lib.a(backtrace.o):(.fixup+0x8): undefined reference to `printk' Signed-off-by: Malcolm Parsons Signed-off-by: Russell King --- arch/arm/lib/backtrace.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S index 68a21c0f3f52..3bdc8c6949c5 100644 --- a/arch/arm/lib/backtrace.S +++ b/arch/arm/lib/backtrace.S @@ -29,7 +29,7 @@ ENTRY(__backtrace) ENTRY(c_backtrace) -#ifndef CONFIG_FRAME_POINTER +#if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK) mov pc, lr #else -- cgit v1.2.3 From 2ce9804fbd9d4da75fb5bb53331b46b614a7d5c3 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Sat, 25 Mar 2006 22:44:05 +0000 Subject: [ARM] 3030/2: fix permission check in the obscur cmpxchg syscall Patch from Nicolas Pitre Quoting RMK: |pte_write() just says that the page _may_ be writable. It doesn't say |that the MMU is programmed to allow writes. If pte_dirty() doesn't |return true, that means that the page is _not_ writable from userspace. |If you write to it from kernel mode (without using put_user) you'll |bypass the MMU read-only protection and may end up writing to a page |owned by two separate processes. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 03924bcc6129..d566d5f4574d 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -506,7 +506,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) if (!pmd_present(*pmd)) goto bad_access; pte = pte_offset_map_lock(mm, pmd, addr, &ptl); - if (!pte_present(*pte) || !pte_write(*pte)) { + if (!pte_present(*pte) || !pte_dirty(*pte)) { pte_unmap_unlock(pte, ptl); goto bad_access; } -- cgit v1.2.3