From 1f9d87d08e4a2299e86f8a1600aedf87ecd3b636 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Aug 2020 16:18:50 +0200 Subject: arm64: dts: meson: vim3: correct led polarity The LEDs on the vim3 are active when the gpio is high, not low. Fixes: c6d29c66e582 ("arm64: dts: meson-g12b-khadas-vim3: add initial device-tree") Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200803141850.172704-1-jbrunet@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 94f75b446504..73783692e30e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -41,13 +41,13 @@ led-white { label = "vim3:white:sys"; - gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; + gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-red { label = "vim3:red"; - gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>; + gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; }; }; -- cgit v1.2.3 From 7c9c06246cea90f6b0cc4fcfe28505832362691c Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Aug 2020 16:21:58 +0200 Subject: arm64: dts: meson: vim3: make sound card common to all variants The vim3 sound card definition should be same all the vim3 variants Move the definition to the appropriate device tree file. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200803142158.173402-1-jbrunet@baylibre.com --- .../boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 88 --------------------- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 90 ++++++++++++++++++++++ 2 files changed, 90 insertions(+), 88 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi index 224c890d32d3..f42cf4b8af2d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi @@ -5,8 +5,6 @@ * Copyright (c) 2019 Christian Hewitt */ -#include - / { model = "Khadas VIM3"; @@ -47,69 +45,6 @@ regulator-boot-on; regulator-always-on; }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-KHADAS-VIM3"; - audio-aux-devs = <&tdmout_a>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; }; &cpu0 { @@ -154,18 +89,6 @@ clock-latency = <50000>; }; -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; @@ -182,14 +105,3 @@ status = "okay"; }; -&tdmif_a { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 73783692e30e..7b46555ac55a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { aliases { @@ -161,6 +162,62 @@ }; }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "G12B-KHADAS-VIM3"; + audio-aux-devs = <&tdmout_a>; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_a>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; + wifi32k: wifi32k { compatible = "pwm-clock"; #clock-cells = <0>; @@ -169,6 +226,14 @@ }; }; +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + &cec_AO { pinctrl-0 = <&cec_ao_a_h_pins>; pinctrl-names = "default"; @@ -221,6 +286,18 @@ amlogic,tx-delay-ns = <2>; }; +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; @@ -368,6 +445,19 @@ }; }; + +&tdmif_a { + status = "okay"; +}; + +&tdmout_a { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + &uart_A { status = "okay"; pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; -- cgit v1.2.3 From cbb2f09abcd635888508338d4436771fe07688d1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 16 Jul 2020 18:18:17 +0100 Subject: arm64: dts: renesas: r8a774e1: Add PCIe device nodes Add PCIe{0,1} device nodes for R8A774E1 SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594919915-5225-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 47 ++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 0f86cfd52425..aaa55f9449f5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1517,12 +1517,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; + }; - /* placeholder */ + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; hdmi0: hdmi@fead0000 { -- cgit v1.2.3 From 2f3c7323aba207b5cf1e769b8f48ce726531de4a Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 16 Jul 2020 18:18:19 +0100 Subject: arm64: dts: renesas: r8a774e1: Add SATA controller node Add the SATA controller node to the RZ/G2H SoC specific dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594919915-5225-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index aaa55f9449f5..832abe712e6c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1499,6 +1499,18 @@ status = "disabled"; }; + sata: sata@ee300000 { + compatible = "renesas,sata-r8a774e1", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 815>; + iommus = <&ipmmu_hc 2>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v1.2.3 From 92b2c276e15c7f93f1148329a1f713c51b26f652 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 16 Jul 2020 18:18:21 +0100 Subject: arm64: dts: renesas: r8a774e1: Add USB2.0 phy and host (EHCI/OHCI) device nodes Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2H SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594919915-5225-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 55 ++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 832abe712e6c..0c4b921cbb3c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1406,45 +1406,76 @@ }; ohci0: usb@ee080000 { + compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; - - /* placeholder */ }; ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; reg = <0 0xee0a0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; status = "disabled"; - - /* placeholder */ }; ehci0: usb@ee080100 { + compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; - - /* placeholder */ }; ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; status = "disabled"; - - /* placeholder */ }; usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a774e1", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; status = "disabled"; - - /* placeholder */ }; usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a774e1", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; status = "disabled"; - - /* placeholder */ }; sdhi0: mmc@ee100000 { -- cgit v1.2.3 From 0faf5f952b4ec26a9b7ed5f537403e7fd32f57d5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 16 Jul 2020 18:18:25 +0100 Subject: arm64: dts: renesas: r8a774e1: Add USB3.0 device nodes Add usb3.0 phy, host and function device nodes on RZ/G2H SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594919915-5225-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 0c4b921cbb3c..84a7539afc92 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -845,11 +845,16 @@ }; usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a774e1-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; #phy-cells = <0>; status = "disabled"; - - /* placeholder */ }; dmac0: dma-controller@e6700000 { @@ -1392,17 +1397,25 @@ }; xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a774e1", + "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; status = "disabled"; - - /* placeholder */ }; usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a774e1-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; status = "disabled"; - - /* placeholder */ }; ohci0: usb@ee080000 { -- cgit v1.2.3 From 896c62d4369c2c8ec3af3b0f74d66da2de697ff7 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 16 Jul 2020 18:18:28 +0100 Subject: arm64: dts: renesas: r8a774e1: Add USB-DMAC and HSUSB device nodes Add usb dmac and hsusb device nodes to the RZ/G2H SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594919915-5225-14-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 40 ++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 84a7539afc92..52b26162d1db 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -838,10 +838,48 @@ }; hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a774e1", + "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; status = "disabled"; + }; - /* placeholder */ + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a774e1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a774e1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; }; usb3_phy0: usb-phy@e65ee000 { -- cgit v1.2.3 From 8183a7938cfec0569d77755af5ce5ff5589f3540 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 16 Jul 2020 18:18:30 +0100 Subject: arm64: dts: renesas: r8a774e1: Add audio support Add sound support for the RZ/G2H SoC (a.k.a. R8A774E1). Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594919915-5225-16-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 476 +++++++++++++++++++++++++++++- 1 file changed, 474 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 52b26162d1db..58e04cdb4454 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1416,6 +1416,19 @@ }; rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -1423,17 +1436,476 @@ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774E1_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; status = "disabled"; - /* placeholder */ + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; + }; ssi2: ssi-2 { - /* placeholder */ + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; + }; + xhci0: usb@ee000000 { compatible = "renesas,xhci-r8a774e1", "renesas,rcar-gen3-xhci"; -- cgit v1.2.3 From cfc7ba103fbd3f6c4b55380dd64649f4102097ac Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 16 Jul 2020 18:18:35 +0100 Subject: arm64: dts: renesas: r8a774e1: Add VIN and CSI-2 nodes Add VIN and CSI-2 nodes to RZ/G2H (R8A774E1) SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594919915-5225-21-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 334 ++++++++++++++++++++++++++++++ 1 file changed, 334 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 58e04cdb4454..5eecd79b58d5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1415,6 +1415,246 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin7>; + }; + }; + }; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -2136,6 +2376,100 @@ status = "disabled"; }; + csi20: csi2@fea80000 { + compatible = "renesas,r8a774e1-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774e1-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; + }; + hdmi0: hdmi@fead0000 { reg = <0 0xfead0000 0 0x10000>; status = "disabled"; -- cgit v1.2.3 From 992d7a8b88c83c05664b649fc54501ce58e19132 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 17 Jul 2020 21:33:21 +0900 Subject: arm64: dts: renesas: ulcb: add full-pwr-cycle-in-suspend into eMMC nodes Add full-pwr-cycle-in-suspend property to do a graceful shutdown of the eMMC device in system suspend. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1594989201-24228-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index ff88af8e39d3..a2e085db87c5 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -469,6 +469,7 @@ mmc-hs200-1_8v; mmc-hs400-1_8v; non-removable; + full-pwr-cycle-in-suspend; status = "okay"; }; -- cgit v1.2.3 From eb302bb9c7ab9bbf8358b97b5f8b1c363af48239 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 17 Jul 2020 18:00:25 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7: Enable HSUSB, USB2.0 and xHCI Enable support for HSUSB, USB2.0 and xHCI on iWave RZ/G1H carrier board. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Biju Das Link: https://lore.kernel.org/r/1595005225-11519-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 42 +++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index e90aaf1c94f0..f4910e709b87 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -131,6 +131,30 @@ }; }; +&hsusb { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pci0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + /* Disable hsusb to enable USB2.0 host mode support on J2 */ + /* status = "okay"; */ +}; + +&pci1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pci2 { + /* Disable xhci to enable USB2.0 host mode support on J23 bottom port */ + /* status = "okay"; */ +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii"; @@ -168,6 +192,16 @@ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; function = "ssi"; }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1_pwen"; + function = "usb1"; + }; }; &rcar_sound { @@ -222,3 +256,11 @@ &ssi4 { shared-pin; }; + +&usbphy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; -- cgit v1.2.3 From 73aa5b7c941145b7a1a53f31b6a71dfe98007870 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 5 Aug 2020 15:26:34 +0100 Subject: ARM: dts: iwg22d-sodimm: Fix dt nodes sorting Some r8a7745-iwg22d-sodimm.dts device nodes are not sorted alphabetically. This patch fixes the sorting of nodes and also fixes a typo in the stmpe node. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20200805142634.12252-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 112 ++++++++++++++-------------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index b15b1b088a32..1c7b37a01f0a 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -53,42 +53,6 @@ clock-frequency = <26000000>; }; - rsnd_sgtl5000: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vccq_panel: regulator-vccq-panel { - compatible = "regulator-fixed"; - regulator-name = "Panel VccQ"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - enable-active-high; - }; - backlight_lcd: backlight { compatible = "pwm-backlight"; pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>; @@ -107,19 +71,40 @@ }; }; }; -}; -&du { - pinctrl-0 = <&du0_pins>; - pinctrl-names = "default"; + vccq_panel: regulator-vccq-panel { + compatible = "regulator-fixed"; + regulator-name = "Panel VccQ"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + enable-active-high; + }; - status = "okay"; + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; - ports { - port@0 { - endpoint { - remote-endpoint = <&lcd_in>; - }; + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; }; }; }; @@ -150,6 +135,21 @@ status = "okay"; }; +&du { + pinctrl-0 = <&du0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&lcd_in>; + }; + }; + }; +}; + &hscif1 { pinctrl-0 = <&hscif1_pins>; pinctrl-names = "default"; @@ -171,6 +171,15 @@ status = "okay"; clock-frequency = <400000>; + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; + stmpe811@44 { compatible = "st,stmpe811"; reg = <0x44>; @@ -179,7 +188,7 @@ /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; - /* ADC converstion time: 80 clocks */ + /* ADC conversion time: 80 clocks */ st,sample-time = <4>; /* 12-bit ADC */ st,mod-12b = <1>; @@ -203,15 +212,6 @@ st,touch-det-delay = <5>; }; }; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&audio_clock>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; }; &pci1 { -- cgit v1.2.3 From 4304d880a1c3676f21e60dc3bb919ff6e7d10ebf Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 6 Aug 2020 19:31:48 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7: Enable cmt0 Enable cmt0 support on r8a7742-iwg21d-q7 board. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/20200806183152.11809-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index f4910e709b87..b3461a61a4bf 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -131,6 +131,10 @@ }; }; +&cmt0 { + status = "okay"; +}; + &hsusb { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From b4a43810f596b55cb29b37ce4212ac7319661fb7 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 6 Aug 2020 19:31:50 +0100 Subject: ARM: dts: r8a7742: Add PWM SoC support Add the definitions for pwm[0123456] to the SoC .dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/20200806183152.11809-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 70 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 9743b4242801..41c89e04cf17 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -917,6 +917,76 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required -- cgit v1.2.3 From 02b24822953571d3ef83029e53bcd011d39dcb39 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 6 Aug 2020 19:31:52 +0100 Subject: ARM: dts: r8a7742: Add TPU support Add TPU support to R8A7742 SoC DT. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/20200806183152.11809-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 41c89e04cf17..4a8d27dff9f7 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -328,6 +328,17 @@ reg = <0 0xe6060000 0 0x250>; }; + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7742", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = ; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7742-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit v1.2.3 From 6a62f64305c65e78db290c0ca153759b6b9ca130 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 7 Aug 2020 18:49:52 +0100 Subject: ARM: dts: r8a7742: Add DU support Add a Display Unit (DU) node to r8a7742 SoC DT. Boards that want to enable the DU need to specify the output topology. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200807174954.14448-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 4a8d27dff9f7..a979a4b3de61 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -1509,6 +1509,41 @@ resets = <&cpg 408>; }; + du: display@feb00000 { + compatible = "renesas,du-r8a7742"; + reg = <0 0xfeb00000 0 0x70000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + }; + }; + }; + }; + prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; -- cgit v1.2.3 From 549f43917ab32947f723aaa26975a1d6282d72c7 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 7 Aug 2020 18:49:53 +0100 Subject: ARM: dts: r8a7742: Add LVDS support Add LVDS encoder node to r8a7742 SoC DT. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200807174954.14448-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index a979a4b3de61..be1053cef315 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -1534,11 +1534,65 @@ port@1 { reg = <1>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; }; }; port@2 { reg = <2>; du_out_lvds1: endpoint { + remote-endpoint = <&lvds1_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7742-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + lvds1: lvds@feb94000 { + compatible = "renesas,r8a7742-lvds"; + reg = <0 0xfeb94000 0 0x14>; + clocks = <&cpg CPG_MOD 725>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 725>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_in: endpoint { + remote-endpoint = <&du_out_lvds1>; + }; + }; + port@1 { + reg = <1>; + lvds1_out: endpoint { }; }; }; -- cgit v1.2.3 From a3855ebcded87ff8368e61139d98c891a842e7b2 Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Mon, 10 Aug 2020 10:22:07 +0100 Subject: arm64: dts: renesas: r8a774e1: Add FCPF and FCPV instances Add FCPF and FCPV instances to the r8a774e1 dtsi. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200810092208.27320-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 5eecd79b58d5..f85f0f0222a9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2376,6 +2376,70 @@ status = "disabled"; }; + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 615>; + }; + + fcpf1: fcp@fe951000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe951000 0 0x200>; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 614>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 607>; + }; + + fcpvb1: fcp@fe92f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 606>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 611>; + }; + + fcpvi1: fcp@fe9bf000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 610>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + csi20: csi2@fea80000 { compatible = "renesas,r8a774e1-csi2"; reg = <0 0xfea80000 0 0x10000>; -- cgit v1.2.3 From 4398ab2367fa0394170543845041d26afcefe421 Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Mon, 10 Aug 2020 10:22:08 +0100 Subject: arm64: dts: renesas: r8a774e1: Add VSP instances The RZ/G2H (R8A774E1) has 6 VSP instances. Based on the work done for r8a7795 SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200810092208.27320-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 66 +++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index f85f0f0222a9..abaa6d7f6b31 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2376,6 +2376,72 @@ status = "disabled"; }; + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; -- cgit v1.2.3 From e7cc614be7886b464a429f83162171128c205b2e Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 10 Aug 2020 18:12:39 +0100 Subject: arm64: dts: renesas: r8a774b1-hihope-rzg2n-ex: Enable sata Enable sata interface on HiHope RZ/G2N board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20200810171239.30401-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts index a3edd55113df..60d7c8adea02 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts +++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts @@ -14,3 +14,8 @@ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n", "renesas,r8a774b1"; }; + +/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ +&sata { + status = "okay"; +}; -- cgit v1.2.3 From ebe5f898b60b341bd223d835dd3d7d77a5b38979 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 10 Aug 2020 18:41:56 +0100 Subject: ARM: dts: r8a7742: Add PCIe Controller device node Add a device node for the PCIe controller on the Renesas RZ/G1H (r8a7742) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200810174156.30880-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index be1053cef315..5070e2a87231 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -188,6 +188,13 @@ clock-frequency = <0>; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + pmu-0 { compatible = "arm,cortex-a15-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -1509,6 +1516,34 @@ resets = <&cpg 408>; }; + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7742", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, + <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7742"; reg = <0 0xfeb00000 0 0x70000>; -- cgit v1.2.3 From f22d0550b83570b10e8f4a474d9629fd4ad76db7 Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Wed, 12 Aug 2020 15:02:11 +0100 Subject: arm64: dts: renesas: r8a774e1: Populate DU device node Populate the DU device node properties in R8A774E1 SoC dtsi. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200812140217.24251-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index abaa6d7f6b31..4b57c1ea762c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2623,22 +2623,39 @@ }; du: display@feb00000 { + compatible = "renesas,du-r8a774e1"; reg = <0 0xfeb00000 0 0x80000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.3"; status = "disabled"; - /* placeholder */ + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; + ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; + du_out_rgb: endpoint { + }; }; port@1 { reg = <1>; + du_out_hdmi0: endpoint { + }; }; port@2 { reg = <2>; + du_out_lvds0: endpoint { + }; }; }; }; -- cgit v1.2.3 From 5698b68de784f483fa4ea405a49097854c4886e4 Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Wed, 12 Aug 2020 15:02:14 +0100 Subject: arm64: dts: renesas: r8a774e1: Populate HDMI encoder node Populate HDMI node properties in R8A774E1 SoC dtsi. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200812140217.24251-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 4b57c1ea762c..79efcd73cc46 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2601,22 +2601,32 @@ }; hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a774e1-hdmi", + "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A774E1_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 729>; status = "disabled"; - /* placeholder */ - ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; }; port@1 { reg = <1>; }; port@2 { + /* HDMI sound */ reg = <2>; }; }; @@ -2650,6 +2660,7 @@ port@1 { reg = <1>; du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; }; }; port@2 { -- cgit v1.2.3 From 112441c24bcdf806335ae0f52e1b4107c6a962ec Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Wed, 12 Aug 2020 15:02:16 +0100 Subject: arm64: dts: renesas: r8a774e1: Add LVDS device node Add the LVDS device node to R8A774E1 to SoC dtsi and connect it with the DU node. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200812140217.24251-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 79efcd73cc46..f783ad8aeafa 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2666,6 +2666,33 @@ port@2 { reg = <2>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a774e1-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { }; }; }; -- cgit v1.2.3 From 2e23a1db4840e6adf4072802d4d91edf4a375b90 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 12 Aug 2020 15:02:17 +0100 Subject: arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks Setup up the required clocks for the DU to be functional. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200812140217.24251-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts index cdbe527e9340..12f9242e263b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts @@ -24,3 +24,14 @@ reg = <0x5 0x00000000 0x0 0x80000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; -- cgit v1.2.3 From afdac0bfbd49e46f7046c7f4bad6daa4a3ebf6fc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 12 Aug 2020 16:00:48 +0100 Subject: ARM: dts: r8a7742: Add QSPI support Add QSPI DT node to R8A7742 SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200812150048.27721-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 5070e2a87231..009827708bf4 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -701,6 +701,22 @@ status = "disabled"; }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7742", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7742", "renesas,rcar-gen2-scifa", "renesas,scifa"; -- cgit v1.2.3 From 82ffb35c2ce63ef8e0325f75eb48022abcf8edbe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Horia=20Geant=C4=83?= Date: Wed, 15 Jul 2020 18:26:01 +0300 Subject: ARM: dts: imx6sl: fix rng node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit rng DT node was added without a compatible string. i.MX driver for RNGC (drivers/char/hw_random/imx-rngc.c) also claims support for RNGB, and is currently used for i.MX25. Let's use this driver also for RNGB block in i.MX6SL. Fixes: e29fe21cff96 ("ARM: dts: add device tree source for imx6sl SoC") Signed-off-by: Horia Geantă Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 1c7180f28539..91a8c54d5e11 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -939,8 +939,10 @@ }; rngb: rngb@21b4000 { + compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb"; reg = <0x021b4000 0x4000>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>; }; weim: weim@21b8000 { -- cgit v1.2.3 From 79428026bdbd7802221e8c70b66eff4ed215494a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Horia=20Geant=C4=83?= Date: Wed, 15 Jul 2020 18:26:02 +0300 Subject: ARM: dts: imx6sll: add rng MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node for the RNGB block. Signed-off-by: Horia Geantă Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index fb5d3bc50c6b..0b622201a1f3 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -786,6 +786,13 @@ clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; }; + rngb: rng@21b4000 { + compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>; + }; + ocotp: efuse@21bc000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 92afd5786d9048454bbf7e207d015daf127e557d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Horia=20Geant=C4=83?= Date: Wed, 15 Jul 2020 18:26:03 +0300 Subject: ARM: dts: imx6ull: add rng MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node for the RNGB block. Signed-off-by: Horia Geantă Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index fcde7f77ae42..9bf67490ac49 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -68,6 +68,13 @@ clock-names = "dcp"; }; + rngb: rng@2284000 { + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; + reg = <0x02284000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; reg = <0x02290000 0x4000>; -- cgit v1.2.3 From 383689f4b8486830447a3cfb479a364b21aa9de3 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 21 Jul 2020 15:22:56 +0800 Subject: ARM: dts: imx6qp-sabreauto: enable pcie Add the reset-gpio property, and enable PCIe on iMX6QP SABREAUTO board. Signed-off-by: Richard Zhu Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qp-sabreauto.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts index 639d9dd35377..2bb3bfb18ec3 100644 --- a/arch/arm/boot/dts/imx6qp-sabreauto.dts +++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts @@ -47,7 +47,8 @@ }; &pcie { - status = "disabled"; + reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; + status = "okay"; }; &sata { -- cgit v1.2.3 From f7e630bcae48279659c31ba974cbf9cf596c2300 Mon Sep 17 00:00:00 2001 From: Chris Healy Date: Wed, 22 Jul 2020 13:33:41 -0700 Subject: ARM: dts: ZII: Disable HW Ethernet switch reset GPIOs Disable Ethernet switch reset GPIO with ZII platforms that have it enabled. HW switch reset results in a reset of the copper PHYs inside of the switch. We want to avoid this reset of the copper PHYs in the switch as this results in unnecessary broader network disruption on a soft reboot of the application processor. With the HW GPIO removed, the switch driver still performs a soft reset of the switch core which has been shown to sufficiently meet our needs with other ZII platforms that do not have the HW switch reset GPIO defined. Signed-off-by: Chris Healy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 2 -- arch/arm/boot/dts/vf610-zii-spb4.dts | 2 -- arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 2 -- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 2 -- 4 files changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 64e0e9509226..50da0c94e1b7 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -172,7 +172,6 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <2>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; ports { #address-cells = <1>; @@ -356,7 +355,6 @@ pinctrl_switch: switch-grp { fsl,pins = < VF610_PAD_PTB28__GPIO_98 0x3061 - VF610_PAD_PTE2__GPIO_107 0x1042 >; }; diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts index 9e5187ba3fa6..6c6ec46fd015 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -129,7 +129,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -326,7 +325,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 569614b08f04..73fdace4cb42 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -118,7 +118,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -293,7 +292,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index b6b0f302b7b4..fe600ab2e4bd 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -143,7 +143,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -333,7 +332,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; -- cgit v1.2.3 From cac849e9bbc8e86095ba5cf306b55ea4eff29125 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Wed, 22 Jul 2020 11:30:12 +0200 Subject: ARM: dts: imx6qdl: add TQMa6{S,Q,QP} SoM Add device trees for TQMa6S, TQMa6Q, and TQMa6QP embedded modules. The A and B SoM variants are for hardware revisions that differ in how the I2C devices are connected. For details, see [1]. This is a combination of the patches "arm: dt: imx6qdl: add tqma6[qdl] som on mba6 mainboard", "arm: dt: tqma6: add spi with spi nor flash on SOM", "arm: dt: add basic support for tqma6qp on mba6", and "arm: dt: imx6qdl-tqma6: use generic jedec,spi-nor" from the TQMa6x BSP, with the MBa6 specific parts removed. [1] https://support.tq-group.com/en/arm/tqma6x/linux/ptxdist/overview Signed-off-by: Markus Niebel [bst@pengutronix.de: remove unnecessary container node in the iomuxc node] Signed-off-by: Bastian Krause [p.zabel@pengutronix.de: merged patches from TQMa6x BSP REV.0114, separated MBa6 DTs, fixed checkpatch and dtbs_check warnings, added no-sd(io) properties to eMMC, added SPDX license identifiers and commit message] Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-tqma6a.dtsi | 16 +++ arch/arm/boot/dts/imx6dl-tqma6b.dtsi | 16 +++ arch/arm/boot/dts/imx6q-tqma6a.dtsi | 16 +++ arch/arm/boot/dts/imx6q-tqma6b.dtsi | 15 +++ arch/arm/boot/dts/imx6qdl-tqma6.dtsi | 202 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-tqma6a.dtsi | 28 +++++ arch/arm/boot/dts/imx6qdl-tqma6b.dtsi | 28 +++++ arch/arm/boot/dts/imx6qp-tqma6b.dtsi | 16 +++ 8 files changed, 337 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-tqma6a.dtsi create mode 100644 arch/arm/boot/dts/imx6dl-tqma6b.dtsi create mode 100644 arch/arm/boot/dts/imx6q-tqma6a.dtsi create mode 100644 arch/arm/boot/dts/imx6q-tqma6b.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-tqma6.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-tqma6a.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-tqma6b.dtsi create mode 100644 arch/arm/boot/dts/imx6qp-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6dl-tqma6a.dtsi b/arch/arm/boot/dts/imx6dl-tqma6a.dtsi new file mode 100644 index 000000000000..e891ef9b0091 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tqma6a.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-tqma6a.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-tqma6b.dtsi b/arch/arm/boot/dts/imx6dl-tqma6b.dtsi new file mode 100644 index 000000000000..38cd8501a886 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tqma6b.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tqma6a.dtsi b/arch/arm/boot/dts/imx6q-tqma6a.dtsi new file mode 100644 index 000000000000..ab4c07c13a13 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tqma6a.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6a.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tqma6b.dtsi b/arch/arm/boot/dts/imx6q-tqma6b.dtsi new file mode 100644 index 000000000000..7224c376c318 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tqma6b.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + */ + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi new file mode 100644 index 000000000000..29bcce20f5f3 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +#include +#include + +/ { + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "supply-3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + m25p80: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 + /* eCSPI1 SS1 */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; +}; + +&pmic { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vddcore: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-always-on; + }; + + reg_snvs_3v: vsnvs { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vgen2_1v2_eth: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen4_1v8: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_1v8_eth: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + non-removable; + disable-wp; + no-sd; + no-sdio; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmccard: mmccard@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi new file mode 100644 index 000000000000..c18a06cf7929 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + }; + + sensor@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi new file mode 100644 index 000000000000..a7460075f517 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel + */ + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + }; + + sensor@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-tqma6b.dtsi b/arch/arm/boot/dts/imx6qp-tqma6b.dtsi new file mode 100644 index 000000000000..bb6ff7c64b27 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tqma6b.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + */ + +#include "imx6q.dtsi" +#include "imx6qp.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; -- cgit v1.2.3 From 4133a90e637ee616ad2becb861ae6416b368e9b6 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 23 Jul 2020 13:43:36 +0800 Subject: ARM: dts: imx7d-sdb: Add nodes for audio sound card Configure the SAI device node, configure audio clock and pinctrl. Enable the audio sound card, which use the SAI1 and wm8960, and enable headphone detection. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 81 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 17cca8a9f77b..b50b19f2d0f1 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -146,6 +146,24 @@ }; }; }; + + sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "AMIC", + "AMIC", "MICB"; + }; }; &adc1 { @@ -363,6 +381,13 @@ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; clock-names = "mclk"; wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <12288000>; }; }; @@ -391,6 +416,28 @@ vin-supply = <&sw2_reg>; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <36864000>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -550,6 +597,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ >; }; @@ -615,6 +663,33 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + pinctrl_spi4: spi4grp { fsl,pins = < MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 @@ -776,4 +851,10 @@ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 >; }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; }; -- cgit v1.2.3 From f1e38466a939f96cb87e23b90ce4e7b7813bb68f Mon Sep 17 00:00:00 2001 From: Vabhav Sharma Date: Fri, 24 Jul 2020 17:04:42 +0530 Subject: arm64: dts: ls1028a: qds: enable lpuart1 LPUART nodes by default are disabled in LS1028A device tree, Enabling LPUART1 node Acked-by: Fugang Duan Signed-off-by: Vabhav Sharma Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index e4f00c2b6608..13cdc958ba3e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -313,6 +313,10 @@ status = "okay"; }; +&lpuart0 { + status = "okay"; +}; + &sai1 { status = "okay"; }; -- cgit v1.2.3 From a553f90b6714504633e6356e04c41264904a1e85 Mon Sep 17 00:00:00 2001 From: Simon Shields Date: Tue, 28 Jul 2020 15:11:11 +0200 Subject: ARM: dts: exynos: Add sound support to Midas Update the never-mainlined "samsung,trats2-audio" binding and instead use the new "samsung,midas-audio" binding. Signed-off-by: Simon Shields [s.nawrocki: fixed DAPM routing entries for MICBIAS1/2, adjusted to new cpu/codec binding, corrected the regulator nodes indexing] Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 42 +++++++++++++++- arch/arm/boot/dts/exynos4412-i9300.dts | 4 ++ arch/arm/boot/dts/exynos4412-midas.dtsi | 78 ++++++++++++++++++++++++----- arch/arm/boot/dts/exynos4412-n710x.dts | 37 +++++++++++++- 4 files changed, 145 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 53b3ca3effab..89ed81fb348d 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -33,7 +33,7 @@ }; }; - lcd_vdd3_reg: voltage-regulator-7 { + lcd_vdd3_reg: voltage-regulator-10 { compatible = "regulator-fixed"; regulator-name = "LCD_VDD_2.2V"; regulator-min-microvolt = <2200000>; @@ -42,7 +42,7 @@ enable-active-high; }; - ps_als_reg: voltage-regulator-8 { + ps_als_reg: voltage-regulator-11 { compatible = "regulator-fixed"; regulator-name = "LED_A_3.0V"; regulator-min-microvolt = <3000000>; @@ -171,6 +171,44 @@ status = "okay"; }; +&sound { + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + "SPK", "SPKOUTRN", + "SPK", "SPKOUTRP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "MICBIAS1", + "IN1LN", "MICBIAS1", + "Main Mic", "MICBIAS1", + + "IN1RP", "Sub Mic", + "IN1RN", "Sub Mic", + + "IN2LP:VXRN", "MICBIAS2", + "Headset Mic", "MICBIAS2", + + "IN2RN", "FM In", + "IN2RP:VXRP", "FM In"; +}; + +&submic_bias_reg { + gpio = <&gpf2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + &touchkey_reg { gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/exynos4412-i9300.dts index f8125a945f8d..3691802b69c5 100644 --- a/arch/arm/boot/dts/exynos4412-i9300.dts +++ b/arch/arm/boot/dts/exynos4412-i9300.dts @@ -20,3 +20,7 @@ reg = <0x40000000 0x40000000>; }; }; + +&sound { + fm-sel-gpios = <&gpl0 3 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 2c8111c6b065..8e7a03228d7b 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -102,6 +102,30 @@ status = "disabled"; }; + vbatt_reg: voltage-regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "VBATT"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + mic_bias_reg: voltage-regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpf1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + submic_bias_reg: voltage-regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "SUB_MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -266,16 +290,18 @@ clock-names = "ext_clock"; }; - sound { - compatible = "samsung,trats2-audio"; - samsung,i2s-controller = <&i2s0>; - samsung,model = "Trats2"; - samsung,audio-codec = <&wm1811>; - samsung,audio-routing = - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - "SPK", "SPKOUTRN", - "SPK", "SPKOUTRP"; + sound: sound { + compatible = "samsung,midas-audio"; + model = "Midas"; + mic-bias-supply = <&mic_bias_reg>; + submic-bias-supply = <&submic_bias_reg>; + + cpu { + sound-dai = <&i2s0 0>; + }; + codec { + sound-dai = <&wm1811>; + }; }; thermistor-ap { @@ -597,11 +623,37 @@ wm1811: wm1811@1a { compatible = "wlf,wm1811"; reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; - DCVDD-supply = <&ldo3_reg>; + clocks = <&pmu_system_controller 0>, + <&max77686 MAX77686_CLK_PMIC>; + clock-names = "MCLK1", "MCLK2"; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpx3>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + #sound-dai-cells = <0>; + + wlf,gpio-cfg = <0x3 0x0 0x0 0x0 0x0 0x0 + 0x0 0x8000 0x0 0x0 0x0>; + wlf,micbias-cfg = <0x2f 0x2b>; + + wlf,lineout1-feedback; + wlf,lineout1-se; + wlf,lineout2-se; + wlf,ldoena-always-driven; + + AVDD2-supply = <&vbatt_reg>; DBVDD1-supply = <&ldo3_reg>; + DBVDD2-supply = <&vbatt_reg>; + DBVDD3-supply = <&vbatt_reg>; + DCVDD-supply = <&ldo3_reg>; + CPVDD-supply = <&vbatt_reg>; + SPKVDD1-supply = <&vbatt_reg>; + SPKVDD2-supply = <&vbatt_reg>; wlf,ldo1ena = <&gpj0 4 0>; + wlf,ldo2ena = <&gpj0 4 0>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index 4189e1fb204c..2361d89a79a8 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -13,7 +13,7 @@ /* bootargs are passed in by bootloader */ - cam_vdda_reg: voltage-regulator-7 { + cam_vdda_reg: voltage-regulator-10 { compatible = "regulator-fixed"; regulator-name = "CAM_SENSOR_CORE_1.2V"; regulator-min-microvolt = <1200000>; @@ -74,6 +74,41 @@ status = "okay"; }; +&sound { + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "MICBIAS2", + "IN1LN", "MICBIAS2", + "Headset Mic", "MICBIAS2", + + "IN1RP", "Sub Mic", + "IN1RN", "Sub Mic", + + "IN2LP:VXRN", "Main Mic", + "IN2LN", "Main Mic", + + "IN2RN", "FM In", + "IN2RP:VXRP", "FM In"; +}; + +&submic_bias_reg { + regulator-always-on; +}; + &touchkey_reg { gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>; status = "okay"; -- cgit v1.2.3 From a084c9d2042d43f0b7b514d040e635d8b1fb643a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 29 Jun 2020 22:38:59 +0200 Subject: dt-bindings: arm: samsung: Do not require clkout on Exynos5260 and Exynos7 The PMU (Power Management Unit) driver is a clkout clock provider (for clock signal monitoring) only for certain Exynos SoCs. It was never implemented for Exynos5260 and Exynos7. This fixes dtschema validator warnings like: system-controller@105c0000: '#clock-cells' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/samsung/pmu.yaml | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml index c9651892710e..686c13c14e32 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml @@ -85,12 +85,28 @@ properties: required: - compatible - reg - - '#clock-cells' - - clock-names - - clocks additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + then: + required: + - '#clock-cells' + - clock-names + - clocks + examples: - | #include -- cgit v1.2.3 From 91b440ed2542510ef33ede55c12465b61c8acfa6 Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Mon, 10 Aug 2020 13:22:07 +0100 Subject: ARM: dts: exynos: add prefetch properties for L2C-310 cache Add the devicetree properties to enable instruction and data prefetch on exynos4210 and exynos4412 which use the L2C-310 cache. No other Exynos chip appears to be using this L2 cache hardware. This follows the default bits being set in the l2c_aux_val register for the Exynos platform, which can now be cleared as a result. Signed-off-by: Guillaume Tucker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210.dtsi | 2 ++ arch/arm/boot/dts/exynos4412.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 33435ce79ce4..73360f29d53e 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -102,6 +102,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <2 2 1>; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7002832eb4c0..c74b1be12671 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -218,6 +218,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <3 2 1>; arm,double-linefill = <1>; -- cgit v1.2.3 From 7db1aa6ff9811b4ba24814d8eb40b21555ca0492 Mon Sep 17 00:00:00 2001 From: Alexander Kochetkov Date: Mon, 3 Aug 2020 17:30:22 +0300 Subject: arm64: dts: allwinner: replace numerical constant with CCU_CLKX Signed-off-by: Alexander Kochetkov Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200803143022.25909-1-al.kochet@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8dfbcd144072..73e9b7345257 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -51,7 +51,7 @@ reg = <0>; enable-method = "psci"; next-level-cache = <&L2>; - clocks = <&ccu 21>; + clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; }; @@ -62,7 +62,7 @@ reg = <1>; enable-method = "psci"; next-level-cache = <&L2>; - clocks = <&ccu 21>; + clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; }; @@ -73,7 +73,7 @@ reg = <2>; enable-method = "psci"; next-level-cache = <&L2>; - clocks = <&ccu 21>; + clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; }; @@ -84,7 +84,7 @@ reg = <3>; enable-method = "psci"; next-level-cache = <&L2>; - clocks = <&ccu 21>; + clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; }; -- cgit v1.2.3 From a371b1bdf2b85840de7e3267eaedef9a585541c0 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 8 Aug 2020 21:18:22 -0500 Subject: arm64: dts: allwinner: Mark timer as stopped in suspend When possible, system firmware on 64-bit Allwinner platforms disables OSC24M during system suspend. Since this oscillator is the clock source for the ARM architectural timer, this causes the timer to stop counting. Therefore, the ARM architectural timer must not be marked as NONSTOP on these platforms, or the time will be wrong after system resume. Adding the arm,no-tick-in-suspend property forces the kernel to ignore the ARM architectural timer when calculating sleeptime; it falls back to reading the RTC. Note that this only affects deep suspend, not s2idle. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200809021822.5285-1-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 1 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 73e9b7345257..cf379e38b3a0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -157,6 +157,7 @@ timer { compatible = "arm,armv8-timer"; allwinner,erratum-unknown1; + arm,no-tick-in-suspend; interrupts = , , , Date: Tue, 4 Aug 2020 17:01:32 -0500 Subject: arm64: dts: agilex: increase shared memory size to 32Mb Increase the shared memory size from 16Mb to 32Mb so that we can properly handle the image authorization for 12+ Mb RBF/JIC files. Signed-off-by: Richard Gong Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 9d7f19e97df7..d81dd8622258 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -20,7 +20,7 @@ service_reserved: svcbuffer@0 { compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; + reg = <0x0 0x0 0x0 0x2000000>; alignment = <0x1000>; no-map; }; -- cgit v1.2.3 From 19d3e9a0bdd57b90175f30390edeb06851f5f9f3 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 10 Mar 2020 14:02:48 -0700 Subject: ARM: dts: omap4: Fix sgx clock rate for 4430 We currently have a different clock rate for droid4 compared to the stock v3.0.8 based Android Linux kernel: # cat /sys/kernel/debug/clk/dpll_*_m7x2_ck/clk_rate 266666667 307200000 # cat /sys/kernel/debug/clk/l3_gfx_cm:clk:0000:0/clk_rate 307200000 Let's fix this by configuring sgx to use 153.6 MHz instead of 307.2 MHz. Looks like also at least duover needs this change to avoid hangs, so let's apply it for all 4430. This helps a bit with thermal issues that seem to be related to memory corruption when using sgx. It seems that other driver related issues still remain though. Cc: Arthur Demchenkov Cc: Merlijn Wajer Cc: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 2 +- arch/arm/boot/dts/omap443x.dtsi | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 0282b9de3384..52e829827505 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -410,7 +410,7 @@ status = "disabled"; }; - target-module@56000000 { + sgx_module: target-module@56000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5600fe00 0x4>, <0x5600fe10 0x4>; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index 8ed510ab00c5..cb309743de5d 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi @@ -74,3 +74,13 @@ }; /include/ "omap443x-clocks.dtsi" + +/* + * Use dpll_per for sgx at 153.6MHz like droid4 stock v3.0.8 Android kernel + */ +&sgx_module { + assigned-clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 24>, + <&dpll_per_m7x2_ck>; + assigned-clock-rates = <0>, <153600000>; + assigned-clock-parents = <&dpll_per_m7x2_ck>; +}; -- cgit v1.2.3 From 23807f8cbaeb4b1b92a0eafd37264eca23c9437a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 16 Jul 2020 14:57:31 +0200 Subject: ARM: dts: omap: add channel to DSI panels The standard binding for DSI requires that the channel number of the panel is encoded in DT. This adds the channel number in all OMAP3-5 boards in preparation for using common infrastructure. Reviewed-by: Laurent Pinchart Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 3 ++- arch/arm/boot/dts/omap3-n950.dts | 3 ++- arch/arm/boot/dts/omap3.dtsi | 3 +++ arch/arm/boot/dts/omap4-sdp.dts | 6 ++++-- arch/arm/boot/dts/omap4.dtsi | 6 ++++++ arch/arm/boot/dts/omap5.dtsi | 6 ++++++ 6 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index 1990239cc6af..12b67f10d952 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -207,8 +207,9 @@ }; }; - lcd0: display { + lcd0: panel@0 { compatible = "panel-dsi-cm"; + reg = <0>; label = "lcd0"; vddi-supply = <&lcd_regulator>; reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 31d47a1fad84..80cf4e1177da 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -225,8 +225,9 @@ }; }; - lcd0: display { + lcd0: panel@0 { compatible = "nokia,himalaya", "panel-dsi-cm"; + reg = <0>; label = "lcd0"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index cf22a7e1c63c..9dcae1f2bc99 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -941,6 +941,9 @@ ti,hwmods = "dss_dsi1"; clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; rfbi: encoder@48050800 { diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 79e7a41ecb7e..1e02513f8150 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -662,8 +662,9 @@ }; }; - lcd0: display { + lcd0: panel@0 { compatible = "tpo,taal", "panel-dsi-cm"; + reg = <0>; label = "lcd0"; reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ @@ -687,8 +688,9 @@ }; }; - lcd1: display { + lcd1: panel@0 { compatible = "tpo,taal", "panel-dsi-cm"; + reg = <0>; label = "lcd1"; reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 52e829827505..6557e69c4e48 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -572,6 +572,9 @@ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; }; @@ -604,6 +607,9 @@ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 5da9cff7a53c..ab05527dc02e 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -516,6 +516,9 @@ status = "disabled"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; + + #address-cells = <1>; + #size-cells = <0>; }; }; @@ -547,6 +550,9 @@ status = "disabled"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; + + #address-cells = <1>; + #size-cells = <0>; }; }; -- cgit v1.2.3 From 86ea53b42b6f8b3d066d2b8b42df433d5a6b42be Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 16 Jul 2020 14:57:32 +0200 Subject: ARM: dts: omap4-droid4: add panel compatible Add Droid 4 specific compatible value in addition to the generic one, so that we have the ability to add panel specific quirks in the future. Reviewed-by: Laurent Pinchart Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index 12b67f10d952..dad772ce6446 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -208,7 +208,7 @@ }; lcd0: panel@0 { - compatible = "panel-dsi-cm"; + compatible = "motorola,droid4-panel", "panel-dsi-cm"; reg = <0>; label = "lcd0"; vddi-supply = <&lcd_regulator>; -- cgit v1.2.3 From 95d4208075e8f022b14503076ff0f488c7748867 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 16 Jul 2020 14:57:33 +0200 Subject: ARM: dts: omap4-droid4: add panel orientation Add information about panel orientation, so that the system boots into a properly rotated shell. Reviewed-by: Laurent Pinchart Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index dad772ce6446..d5ded4f794df 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -218,6 +218,7 @@ width-mm = <50>; height-mm = <89>; + rotation = <90>; panel-timing { clock-frequency = <0>; /* Calculated by dsi */ -- cgit v1.2.3 From 31bdd786f900c13f4ba47a96e8e6c6ed18731ea9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Johnson=20CH=20Chen=20=28=E9=99=B3=E6=98=AD=E5=8B=B3=29?= Date: Thu, 6 Aug 2020 02:28:48 +0000 Subject: ARM: dts: am335x: add common dtsi for MOXA UC-8100 series Add am335x-moxa-uc-8100-common.dtsi for many products of MOXA UC-8100 series, and remove common nodes from am335x-moxa-uc-8100-me-t.dts. Signed-off-by: Johnson Chen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi | 427 ++++++++++++++++++++++ arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts | 404 +------------------- 2 files changed, 428 insertions(+), 403 deletions(-) create mode 100644 arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi new file mode 100644 index 000000000000..98d8ed4ad967 --- /dev/null +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 MOXA Inc. - https://www.moxa.com/ + * + * Author: Johnson Chen + */ + +#include "am33xx.dtsi" + +/ { + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + vbat: vbat-regulator { + compatible = "regulator-fixed"; + }; + + /* Power supply provides a fixed 3.3V @3A */ + vmmcsd_fixed: vmmcsd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + buttons: push_button { + compatible = "gpio-keys"; + }; + +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins>; + + minipcie_pins: pinmux_minipcie { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ + >; + }; + + push_button_pins: pinmux_push_button { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + + /* Slave 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ + + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc0_pins_default: pinmux_mmc0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ + >; + }; + + mmc2_pins_default: pinmux_mmc2_pins { + pinctrl-single,pins = < + /* eMMC */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ + >; + }; + + spi0_pins: pinmux_spi0 { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + +}; + +&uart0 { + /* Console */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + /* UART 1 setting */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart5 { + /* UART 2 setting */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + compatible = "ti,tps65910"; + reg = <0x2d>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + pagesize = <16>; + reg = <0x50>; + }; + + rtc_wdt: rtc_wdt@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <400000>; + gpio_xten: gpio_xten@27 { + compatible = "nxp,pca9535"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x27>; + }; +}; + +&usb0 { + dr_mode = "host"; +}; + +&usb1 { + dr_mode = "host"; +}; + + +#include "tps65910.dtsi" +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "vmmc_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* Power */ +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; + + ethphy0: ethernet-phy@4 { + reg = <4>; + }; + + ethphy1: ethernet-phy@5 { + reg = <5>; + }; +}; + +&cpsw_emac0 { + status = "okay"; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + status = "okay"; + phy-handle = <ðphy1>; + phy-mode = "rmii"; + dual_emac_res_vlan = <2>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; + +&mmc1 { + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-0 = <&mmc0_pins_default>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + pinctrl-0 = <&mmc2_pins_default>; + ti,non-removable; + status = "okay"; +}; + +&buttons { + pinctrl-names = "default"; + pinctrl-0 = <&push_button_pins>; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + label = "push_button"; + linux,code = <0x100>; + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI Busses */ +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + m25p80@0 { + compatible = "mx25l6405d"; + spi-max-frequency = <40000000>; + + reg = <0>; + spi-cpol; + spi-cpha; + #address-cells = <1>; + #size-cells = <1>; + + /* reg : The partition's offset and size within the mtd bank. */ + partitions@0 { + label = "MLO"; + reg = <0x0 0x80000>; + }; + + partitions@1 { + label = "U-Boot"; + reg = <0x80000 0x100000>; + }; + + partitions@2 { + label = "U-Boot Env"; + reg = <0x180000 0x20000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts index f03e72cada41..0c7949d21bd9 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts @@ -4,39 +4,19 @@ * * Author: SZ Lin (林上智) */ - /dts-v1/; -#include "am33xx.dtsi" +#include "am335x-moxa-uc-8100-common.dtsi" / { model = "Moxa UC-8100-ME-T"; compatible = "moxa,uc-8100-me-t", "ti,am33xx"; - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - memory { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; - vbat: vbat-regulator { - compatible = "regulator-fixed"; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: vmmcsd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - leds { compatible = "gpio-leds"; led1 { @@ -88,237 +68,17 @@ default-state = "off"; }; }; - - buttons: push_button { - compatible = "gpio-keys"; - }; - -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_pins>; - - minipcie_pins: pinmux_minipcie { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ - >; - }; - - push_button_pins: pinmux_push_button { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ - - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc0_pins_default: pinmux_mmc0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ - >; - }; - - mmc2_pins_default: pinmux_mmc2_pins { - pinctrl-single,pins = < - /* eMMC */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ - >; - }; - - spi0_pins: pinmux_spi0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - -}; - -&uart0 { - /* Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - /* UART 1 setting */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart5 { - /* UART 2 setting */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - tpm: tpm@20 { compatible = "infineon,slb9645tt"; reg = <0x20>; }; - - tps: tps@2d { - compatible = "ti,tps65910"; - reg = <0x2d>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - }; - - rtc_wdt: rtc_wdt@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; }; -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <400000>; - gpio_xten: gpio_xten@27 { - compatible = "nxp,pca9535"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x27>; - }; -}; - -&usb0 { - dr_mode = "host"; -}; - -&usb1 { - dr_mode = "host"; -}; - -#include "tps65910.dtsi" - &tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; @@ -336,168 +96,6 @@ regulator-boot-on; regulator-always-on; }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&mac { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - - ethphy1: ethernet-phy@5 { - reg = <5>; - }; -}; - -&cpsw_emac0 { - status = "okay"; - phy-handle = <ðphy0>; - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - status = "okay"; - phy-handle = <ðphy1>; - phy-mode = "rmii"; - dual_emac_res_vlan = <2>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&mmc1 { - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-0 = <&mmc0_pins_default>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-0 = <&mmc2_pins_default>; - non-removable; - status = "okay"; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins>; - #address-cells = <1>; - #size-cells = <0>; - - button@0 { - label = "push_button"; - linux,code = <0x100>; - gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; }; }; -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - - m25p80@0 { - compatible = "mx25l6405d"; - spi-max-frequency = <40000000>; - - reg = <0>; - spi-cpol; - spi-cpha; - #address-cells = <1>; - #size-cells = <1>; - - /* reg : The partition's offset and size within the mtd bank. */ - partitions@0 { - label = "MLO"; - reg = <0x0 0x80000>; - }; - - partitions@1 { - label = "U-Boot"; - reg = <0x80000 0x100000>; - }; - - partitions@2 { - label = "U-Boot Env"; - reg = <0x180000 0x20000>; - }; - }; -}; -- cgit v1.2.3 From 03e23ca9ff8343feec87fe89c1b6c3fb3a179711 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Sun, 9 Aug 2020 23:58:03 -0500 Subject: ARM: dts: am33xx: add ocp label Add label to the ocp node in the AM33xx SoC include so that it can be referenced in board-level files like am335x-pocketbeagle.dts Signed-off-by: Drew Fustini Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 5cb4cc37cb6d..1ab54ee9dd72 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -172,7 +172,7 @@ * for the moment, just use a fake OCP bus entry to represent * the whole bus hierarchy. */ - ocp { + ocp: ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From bbdb5d129dafba02d4c8e745f9d0e856a33f287a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Aug 2020 07:57:20 -0500 Subject: ARM: dts: omap3: Add cpu trips and cooling map for omap34/36 families Currently, OMAP3_THERMAL is disabled by default, so the bandgap sensor is unavailable, and enabling it will somewhat increase power consumption. However for boards which operate near their thermal limit, OMAP3_THERMAL can be enabled and monitored to keep the processor from either running too fast, or shutdown when it's deemed to be operating at an unsafe thermal limit at the expense of increased power consumption. The OMAP3530, OMAP3630, and DM3730 all show thresholds of 90C and 105C depending on commercial or extended temperature ratings. This patch expands the thermal information to include the limits of 80C for alert and 90C critical based on commercial temperature rating. It sets the coolings-cells for the 34xx and 36xx CPU's which will start to throttle back their maximum frequency when the bangap sensor reads above the alert temerature of 80C. For boards who which to increase the temperatures for extended temperature ratings, these can be changed on their respective device trees with something like: &cpu_alert0 { temperature = <90000>; /* millicelsius */ }; &cpu_crit { temperature = <105000>; /* millicelsius */ }; Signed-off-by: Adam Ford Tested-by: H. Nikolaus Schaller # on GTA04A5 with dm3730cbp100 Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-cpu-thermal.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/omap34xx.dtsi | 1 + arch/arm/boot/dts/omap36xx.dtsi | 1 + 3 files changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi index aee46fa8c055..1ed837859374 100644 --- a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi @@ -17,4 +17,25 @@ cpu_thermal: cpu_thermal { /* sensor ID */ thermal-sensors = <&bandgap 0>; + + cpu_trips: trips { + cpu_alert0: cpu_alert { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cpu_cooling_maps: cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 9c3ee4ac8165..c0dcc75833a8 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -20,6 +20,7 @@ operating-points-v2 = <&cpu0_opp_table>; clock-latency = <300000>; /* From legacy driver */ + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 9c3beefc0fe0..fadbf308feff 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -25,6 +25,7 @@ vbb-supply = <&abb_mpu_iva>; clock-latency = <300000>; /* From omap-cpufreq driver */ + #cooling-cells = <2>; }; }; -- cgit v1.2.3 From 27831102b89b43f4d6c3f8b371c1cb358d165680 Mon Sep 17 00:00:00 2001 From: Xia Jiang Date: Fri, 14 Aug 2020 15:11:58 +0800 Subject: arm: dts: mt2701: Add jpeg enc device tree node Add jpeg enc device tree node. Signed-off-by: Xia Jiang Reviewed-by: Tomasz Figa Link: https://lore.kernel.org/r/20200814071202.25067-27-xia.jiang@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 39b3a2f4bef4..fade14284017 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -569,6 +569,19 @@ <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; + jpegenc: jpegenc@1500a000 { + compatible = "mediatek,mt2701-jpgenc", + "mediatek,mtk-jpgenc"; + reg = <0 0x1500a000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_VENC>; + clock-names = "jpgenc"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, + <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; + }; + vdecsys: syscon@16000000 { compatible = "mediatek,mt2701-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; -- cgit v1.2.3 From acfa13abf03dac0a0a775328feceabe241a7fa3e Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 15 Jul 2020 14:49:08 +0800 Subject: arm64: dts: ls1088a: add more thermal zone support There are 2 thermal zones in ls1088a soc. Add the other thermal zone node to enable it. Also update the values in calibration table to make the temperatures monitored more precise. Signed-off-by: Yuantian Tang Reviewed-by: Amit Kucheria Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 94 +++++++++++++++----------- 1 file changed, 56 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 169f4742ae3b..b961a896ede7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -130,19 +130,19 @@ }; thermal-zones { - cpu_thermal: cpu-thermal { + core-cluster { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 0>; trips { - cpu_alert: cpu-alert { + core_cluster_alert: core-cluster-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu-crit { + core-cluster-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; @@ -151,7 +151,7 @@ cooling-maps { map0 { - trip = <&cpu_alert>; + trip = <&core_cluster_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -164,6 +164,20 @@ }; }; }; + + soc { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + + trips { + soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; timer { @@ -210,45 +224,49 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; interrupts = <0 23 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = /* Calibration data group 1 */ - <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 + <0x00000000 0x00000023 + 0x00000001 0x0000002a + 0x00000002 0x00000030 + 0x00000003 0x00000037 + 0x00000004 0x0000003d + 0x00000005 0x00000044 + 0x00000006 0x0000004a + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005e + 0x0000000a 0x00000064 + 0x0000000b 0x0000006b /* Calibration data group 2 */ - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 + 0x00010000 0x00000022 + 0x00010001 0x0000002a + 0x00010002 0x00000032 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000052 + 0x00010007 0x0000005a + 0x00010008 0x00000062 + 0x00010009 0x0000006a /* Calibration data group 3 */ - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d + 0x00020000 0x00000021 + 0x00020001 0x0000002b + 0x00020002 0x00000035 + 0x00020003 0x00000040 + 0x00020004 0x0000004a + 0x00020005 0x00000054 + 0x00020006 0x0000005e /* Calibration data group 4 */ - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; + 0x00030000 0x00000010 + 0x00030001 0x0000001c + 0x00030002 0x00000027 + 0x00030003 0x00000032 + 0x00030004 0x0000003e + 0x00030005 0x00000049 + 0x00030006 0x00000054 + 0x00030007 0x00000060>; little-endian; #thermal-sensor-cells = <1>; }; -- cgit v1.2.3 From 0a0c5d13617fb52a66c4980f40faa42a1007d3b4 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 15 Jul 2020 14:49:09 +0800 Subject: arm64: dts: ls208xa: add more thermal zone support There are 7 thermal zones in ls208xa soc. Add the other thermal zone nodes to enable them. Signed-off-by: Yuantian Tang Reviewed-by: Amit Kucheria Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 141 +++++++++++++++++++++++-- 1 file changed, 132 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 41102dacc2e1..cc36c969dd9d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -79,20 +79,62 @@ }; thermal-zones { - cpu_thermal: cpu-thermal { + ddr-controller1 { polling-delay-passive = <1000>; polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + trips { + ddr-ctrler1-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + ddr-controller2 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 2>; + + trips { + ddr-ctrler2-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + ddr-controller3 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 3>; + + trips { + ddr-ctrler3-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + core-cluster1 { + polling-delay-passive = <1000>; + polling-delay = <5000>; thermal-sensors = <&tmu 4>; trips { - cpu_alert: cpu-alert { - temperature = <75000>; + core_cluster1_alert: core-cluster1-alert { + temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu-crit { - temperature = <85000>; + + core-cluster1-crit { + temperature = <95000>; hysteresis = <2000>; type = "critical"; }; @@ -100,14 +142,95 @@ cooling-maps { map0 { - trip = <&cpu_alert>; + trip = <&core_cluster1_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + core-cluster2 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 5>; + + trips { + core_cluster2_alert: core-cluster2-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster2-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster2_alert>; + cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + core-cluster3 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 6>; + + trips { + core_cluster3_alert: core-cluster3-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster3-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster3_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + core-cluster4 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 7>; + + trips { + core_cluster4_alert: core-cluster4-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster4-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster4_alert>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; -- cgit v1.2.3 From b9c7113bbdda65343d8c5d6f48cbfd8835cd003d Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Fri, 24 Jul 2020 14:05:31 +0800 Subject: arm64: dts: imx8mm-evk: add two parameters for samsung picophy tuning With these two parameters tuning, it can pass USB eye diagram at evk board. Reviewed-by: Jun Li Signed-off-by: Peter Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 0f1d7f8aeac4..7c652b898114 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -324,6 +324,8 @@ srp-disable; adp-disable; usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; port { -- cgit v1.2.3 From 14e292fce8fd5e018a6499c42ad7a4526bf4b49f Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Fri, 24 Jul 2020 14:05:32 +0800 Subject: arm64: dts: imx8mn-evk: add two parameters for samsung picophy tuning With these two parameters tuning, it can pass USB eye diagram at evk board. Signed-off-by: Peter Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 98f5324b1dbe..5662ba4358a5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -132,6 +132,8 @@ srp-disable; adp-disable; usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; port { -- cgit v1.2.3 From fc8004dffcfd47a1206460b54de91528c803bd64 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Wed, 29 Jul 2020 10:25:54 +0200 Subject: ARM: dts: imx7: add QSPI In preparation for an update of the TQ-Systems TQMa7x/MBa7x DTS, add the QSPI controller to imx7s.dtsi. Based-on-patch-by: Han Xu Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 1cfaf410aa43..85b8eddd77f2 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1162,6 +1162,19 @@ status = "disabled"; }; + qspi: spi@30bb0000 { + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + sdma: sdma@30bd0000 { compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; -- cgit v1.2.3 From e42fb04e9834ea97dd84649050669603c9468a17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Thu, 30 Jul 2020 12:13:46 +0200 Subject: ARM: dts: imx6dl-yapp4: Add ethernet aliases MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add aliases for ethernet switch ports to allow bootloader to fix MAC addresses to the ones stored in onboard configuration EEPROM. Ursa has only one ethernet port populated (eth2) so alias for the first port has to be removed on this board. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 9 +++++++-- arch/arm/boot/dts/imx6dl-yapp4-ursa.dts | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index c4a235d212b6..207f510cb518 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -8,6 +8,11 @@ #include / { + aliases: aliases { + ethernet1 = ð1; + ethernet2 = ð2; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; @@ -135,13 +140,13 @@ }; }; - port@2 { + eth2: port@2 { reg = <2>; label = "eth2"; phy-handle = <&phy_port2>; }; - port@3 { + eth1: port@3 { reg = <3>; label = "eth1"; phy-handle = <&phy_port3>; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts index a1173bf5bff5..f6ae24efd4aa 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts +++ b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts @@ -17,6 +17,10 @@ }; }; +&aliases { + /delete-property/ ethernet1; +}; + &backlight { status = "okay"; }; -- cgit v1.2.3 From 8da4716d08bcdf72f621668fa5bebd7bdfb4ad3e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 30 Jul 2020 21:04:05 +0800 Subject: ARM: dts: imx27: Change nand node name to nand-controller Change i.MX27 nand node name from "nand" to "nand-controller" to be compliant with yaml schema, it requires the nodename to be "nand-controller". Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index fc0b318f8733..7bc132737a37 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -558,7 +558,7 @@ }; }; - nfc: nand@d8000000 { + nfc: nand-controller@d8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx27-nand"; -- cgit v1.2.3 From 1758088842619e489a926fb5dc4757ce80ff9615 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 30 Jul 2020 21:04:06 +0800 Subject: ARM: dts: imx: Change gpmi nand node name to nand-controller Change i.MX SoCs nand node name from "gpmi-nand" to "nand-controller" to be compliant with yaml schema, it requires the nodename to be "nand-controller". Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-evk.dts | 2 +- arch/arm/boot/dts/imx23.dtsi | 2 +- arch/arm/boot/dts/imx28-apf28.dts | 2 +- arch/arm/boot/dts/imx28-apx4devkit.dts | 2 +- arch/arm/boot/dts/imx28-evk.dts | 2 +- arch/arm/boot/dts/imx28-m28cu3.dts | 2 +- arch/arm/boot/dts/imx28.dtsi | 2 +- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 2 +- arch/arm/boot/dts/imx6ul.dtsi | 2 +- arch/arm/boot/dts/imx7s.dtsi | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 0b2701ca2921..8cbaf1c81174 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -53,7 +53,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; status = "okay"; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 18289f6fb1f3..7f4c602454a5 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -76,7 +76,7 @@ status = "disabled"; }; - gpmi-nand@8000c000 { + nand-controller@8000c000 { compatible = "fsl,imx23-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts index 3ed2b328f7ef..14a92fe59770 100644 --- a/arch/arm/boot/dts/imx28-apf28.dts +++ b/arch/arm/boot/dts/imx28-apf28.dts @@ -17,7 +17,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; status = "okay"; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index c5acc19c982d..b86be320496b 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -13,7 +13,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; status = "okay"; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 96c1d106bc64..7e2b0f198dfa 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -97,7 +97,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg &gpmi_pins_evk>; diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts index 91bd6deffee5..865ac3d573c7 100644 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/imx28-m28cu3.dts @@ -17,7 +17,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { #address-cells = <1>; #size-cells = <1>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index a2b799c56f8f..94dfbf5b3f34 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -100,7 +100,7 @@ status = "disabled"; }; - gpmi: gpmi-nand@8000c000 { + gpmi: nand-controller@8000c000 { compatible = "fsl,imx28-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 43edbf1156c7..de6daa7b38aa 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -159,7 +159,7 @@ clocks = <&clks IMX6QDL_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@112000 { + gpmi: nand-controller@112000 { compatible = "fsl,imx6q-gpmi-nand"; reg = <0x00112000 0x2000>, <0x00114000 0x2000>; reg-names = "gpmi-nand", "bch"; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index b480dfa9e251..dfdca1804f9f 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -213,7 +213,7 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@1806000{ + gpmi: nand-controller@1806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 2b088f210331..d7d9f3e46b92 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -174,7 +174,7 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; - gpmi: gpmi-nand@1806000 { + gpmi: nand-controller@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 85b8eddd77f2..84d9cc13afb9 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1221,7 +1221,7 @@ clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; }; - gpmi: gpmi-nand@33002000{ + gpmi: nand-controller@33002000{ compatible = "fsl,imx7d-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From bee062810f42a4e1716a619d088118e0cfa157cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Fri, 31 Jul 2020 14:00:06 +0200 Subject: =?UTF-8?q?dt-bindings:=20arm:=20fsl:=20Add=20Y=20Soft=20IOTA?= =?UTF-8?q?=C2=A0Orion=20board?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree binding for Orion - new board variant in the Y Soft IOTA family. Signed-off-by: Michal Vokáč Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6da9d734cdb7..788a8871fb82 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -188,6 +188,7 @@ properties: - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3 - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board + - ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board - const: fsl,imx6dl -- cgit v1.2.3 From e642c831ebdd560b5f3ffa731f1e8280eecca2f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Fri, 31 Jul 2020 14:00:07 +0200 Subject: =?UTF-8?q?ARM:=20dts:=20imx6dl-yapp4:=20Add=20Y=20Soft=20IOTA?= =?UTF-8?q?=C2=A0Orion=20board?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree for new variant of the Y Soft IOT appliance. The board is based on Hydra with the following changes: - faster SoC (1GHz), 4GB RAM and 64GB eMMC - removed miniPCIe - removed Audio jack - removed uSD slot - removed RJ10 serial - HDMI replaced by USB host Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-yapp4-orion.dts | 50 ++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-orion.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..eec0d61874a4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -482,6 +482,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-wandboard-revd1.dtb \ imx6dl-yapp4-draco.dtb \ imx6dl-yapp4-hydra.dtb \ + imx6dl-yapp4-orion.dtb \ imx6dl-yapp4-ursa.dtb \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts new file mode 100644 index 000000000000..0428720417ef --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2020 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Orion i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-orion", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; -- cgit v1.2.3 From 37d7b7a5baca43722d332e190a3c86ac0c4341e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Fri, 31 Jul 2020 14:00:08 +0200 Subject: ARM: dts: imx6dl-yapp4: Add support for OLED based on different controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OLED display consist of an OLED panel and a display controller. The displays that were used on yapp4 platform were based on a SSD1305 controller. These displays are now discontinued and we need to add support for a replacement. The new display is based on SSD1309 controller and requires slightly different configuration (mirror + segment offset). We want to support both display types so it does no matter which one was used on the assembly line. Hence the displays are placed at different I2C addresses. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 15 ++++++++++++++- arch/arm/boot/dts/imx6dl-yapp4-hydra.dts | 6 +++++- arch/arm/boot/dts/imx6dl-yapp4-orion.dts | 6 +++++- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 207f510cb518..46927a020943 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -316,7 +316,20 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - oled: oled@3d { + oled_1309: oled@3c { + compatible = "solomon,ssd1309fb-i2c"; + reg = <0x3c>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,segment-no-remap; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + oled_1305: oled@3d { compatible = "solomon,ssd1305fb-i2c"; reg = <0x3d>; solomon,height = <64>; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts index 6010d3d872ab..a19609c7c7c0 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts +++ b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts @@ -29,7 +29,11 @@ status = "okay"; }; -&oled { +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts index 0428720417ef..884b236746bb 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts +++ b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts @@ -25,7 +25,11 @@ status = "okay"; }; -&oled { +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { status = "okay"; }; -- cgit v1.2.3 From 71c7c2d9a2fe16f20878f507a60e3aee0246c17b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 5 Aug 2020 17:13:07 +0200 Subject: ARM: dts: imx25-pinfunc: add missing and fix wrong SPI related defintions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I used the i.MX25 Reference Manual (Rev 2 01/2011) as source for these additions and fixes. No mainline dts is affected by the fixes (nor obviously by the additions). Signed-off-by: Uwe Kleine-König Reviewed-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pinfunc.h | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index 111bfdcbe552..e14140e62b9b 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -87,6 +87,7 @@ #define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 #define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 #define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 +#define MX25_PAD_EB1__CSPI3_SS1 0x044 0x25c 0x4c0 0x06 0x000 #define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 #define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 @@ -112,6 +113,7 @@ #define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000 #define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 +#define MX25_PAD_NF_CE0__CSPI1_SS3 0x05c 0x26c 0x490 0x01 0x000 #define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 #define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 @@ -122,6 +124,7 @@ #define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 #define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 #define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 +#define MX25_PAD_LBA__CSPI3_RDY 0x064 0x274 0x4b0 0x06 0x000 #define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 #define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 @@ -286,6 +289,7 @@ #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 #define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000 +#define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000 #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 #define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 @@ -298,7 +302,7 @@ #define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 #define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 #define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 -#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000 +#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x4b8 0x07 0x001 #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 #define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 @@ -310,23 +314,25 @@ #define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 #define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 #define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 -#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000 +#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x4ac 0x07 0x001 #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 #define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 #define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 #define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 -#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000 +#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x4b0 0x07 0x001 #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 /* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ #define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 #define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 +#define MX25_PAD_CSI_D6__CSPI3_SS0 0x130 0x328 0x4bc 0x07 0x001 #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 #define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 +#define MX25_PAD_CSI_D7__CSPI3_SS1 0x134 0x32c 0x4c0 0x07 0x001 #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 #define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 @@ -417,10 +423,12 @@ #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 #define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000 #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 +#define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000 #define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 #define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 +#define MX25_PAD_UART2_CTS__CSPI3_SS3 0x18c 0x384 0x4c8 0x06 0x001 /* * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD @@ -446,14 +454,17 @@ #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 #define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA1__CSPI2_RDY 0x19c 0x394 0x498 0x01 0x001 #define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 #define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 #define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA2__CSPI2_SS0 0x1a0 0x398 0x4a4 0x01 0x001 #define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 #define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 #define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA3__CSPI2_SS1 0x1a4 0x39c 0x4a8 0x01 0x001 #define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 #define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 @@ -564,11 +575,14 @@ #define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 #define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 #define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 +#define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000 #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 +#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 #define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 #define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 +#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 #define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 #define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 @@ -593,6 +607,7 @@ #define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 #define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 +#define MX25_PAD_VSTBY_ACK__CSPI1_SS3 0x218 0x40c 0x490 0x02 0x001 #define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 #define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 -- cgit v1.2.3 From d923d839429c42efda01ffd2d73bff9097495f9d Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Wed, 5 Aug 2020 18:39:04 +0800 Subject: ARM: dts: imx6qdl-sabresd: Support headphone and microphone detection Add "DMIC" rounting, headphone and microphone detect gpio for sound card, then output sound can switch between headphone and speaker. input sound can switch between DMIC and AMIC. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 68b3e68cb8df..7dddcab9d53f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -105,9 +105,13 @@ "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", - "IN3R", "AMIC"; + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC"; mux-int-port = <2>; mux-ext-port = <3>; + hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>; + mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; }; backlight_lvds: backlight-lvds { -- cgit v1.2.3 From 675abeb9fc0e24a25eb5f95a948e3738aef64875 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 5 Aug 2020 15:58:17 +0200 Subject: ARM: dts: imx6q-bx50v3: Add IRQ support for internal switch This adds missing interrupt support for the internal Marvell switch, so that the kernel does not have to keep polling the PHYs on the bit-banged MDIO bus all the time. Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-bx50v3.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 1938b04199c4..1fb67cd2b2a1 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -102,10 +102,15 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch: switch@0 { compatible = "marvell,mv88e6085"; /* 88e6240*/ reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + switch_ports: ports { #address-cells = <1>; #size-cells = <0>; @@ -117,22 +122,32 @@ switchphy0: switchphy@0 { reg = <0>; + interrupt-parent = <&switch>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; }; switchphy1: switchphy@1 { reg = <1>; + interrupt-parent = <&switch>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; switchphy2: switchphy@2 { reg = <2>; + interrupt-parent = <&switch>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; }; switchphy3: switchphy@3 { reg = <3>; + interrupt-parent = <&switch>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; }; switchphy4: switchphy@4 { reg = <4>; + interrupt-parent = <&switch>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; }; }; }; -- cgit v1.2.3 From b86d3d21cd4c9bc18cbcf3b668565cf1e31023d5 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Wed, 12 Aug 2020 14:50:19 -0500 Subject: ARM: dts: imx6dl-yapp4: Add reg property to the lp5562 channel node Add the reg property to each channel node. This update is to accommodate the multicolor framework. In addition to the accommodation this allows the LEDs to be placed on any channel and allow designs to skip channels as opposed to requiring sequential order. Acked-by: Pavel Machek Signed-off-by: Dan Murphy CC: Shawn Guo CC: Sascha Hauer CC: Pengutronix Kernel Team CC: Fabio Estevam CC: NXP Linux Team Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 46927a020943..7d2c72562c73 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -263,29 +263,35 @@ reg = <0x30>; clock-mode = /bits/ 8 <1>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; - chan0 { + chan@0 { chan-name = "R"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <0>; }; - chan1 { + chan@1 { chan-name = "G"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <1>; }; - chan2 { + chan@2 { chan-name = "B"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <2>; }; - chan3 { + chan@3 { chan-name = "W"; led-cur = /bits/ 8 <0x0>; max-cur = /bits/ 8 <0x0>; + reg = <3>; }; }; -- cgit v1.2.3 From 0b784a7b1c53c3989e9ee2dfdd3fc9b6b14b5256 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 13 Aug 2020 22:24:10 +0200 Subject: ARM: dts: imx25-pinfunc: Fix GPT function names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the reference manual of the i.MX25 the function name for the GPT capture input is called CAPIN1. So fix the names to follow the same naming scheme as used for the other pads and functions. Also add one missing pad function. There are no mainline users that needs adaption. Signed-off-by: Uwe Kleine-König Acked-by: Rob Herring Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pinfunc.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index e14140e62b9b..f984b702efc5 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -288,7 +288,7 @@ #define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 -#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000 +#define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000 #define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000 #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 @@ -404,7 +404,7 @@ #define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 #define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 -#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000 +#define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000 #define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 #define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 @@ -421,7 +421,7 @@ #define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 -#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000 +#define MX25_PAD_UART2_RTS__GPT1_CAPIN1 0x188 0x380 0x000 0x03 0x000 #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 #define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000 @@ -575,6 +575,7 @@ #define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 #define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 #define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 +#define MX25_PAD_GPIO_C__GPT2_CAPIN1 0x1fc 0x3f8 0x000 0x04 0x000 #define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000 #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 #define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 -- cgit v1.2.3 From d3762a4713b1a5b2fbc0e7ea98e78948667021f9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 18 Aug 2020 22:59:46 -0300 Subject: arm64: dts: imx8m: Add the ENET PPS interrupt The i.MX8M SoCs have a fourth ENET interrupt dedicated to PPS (Pulse Per Second). Add support for it. Suggested-by: Rogerio Nunes Signed-off-by: Fabio Estevam Reviewed-by: Fugang Duan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 3 ++- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 3 ++- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 3 ++- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 76f040e4be5e..b83f400def8b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -854,7 +854,8 @@ reg = <0x30be0000 0x10000>; interrupts = , , - ; + , + ; clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET_TIMER>, diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 9385dd7d1a2f..746faf1cf2fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -741,7 +741,8 @@ reg = <0x30be0000 0x10000>; interrupts = , , - ; + , + ; clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, <&clk IMX8MN_CLK_ENET1_ROOT>, <&clk IMX8MN_CLK_ENET_TIMER>, diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9de2aa1c573c..cad2dd790bec 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -713,7 +713,8 @@ reg = <0x30be0000 0x10000>; interrupts = , , - ; + , + ; clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, <&clk IMX8MP_CLK_SIM_ENET_ROOT>, <&clk IMX8MP_CLK_ENET_TIMER>, diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index f70435cf9ad5..0d02ccdb0abc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1031,7 +1031,8 @@ reg = <0x30be0000 0x10000>; interrupts = , , - ; + , + ; clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, <&clk IMX8MQ_CLK_ENET1_ROOT>, <&clk IMX8MQ_CLK_ENET_TIMER>, -- cgit v1.2.3 From d0081bd02a037c1b867c4d3a5cb0878fb321cb08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Thu, 20 Aug 2020 10:50:56 +0200 Subject: arm64: dts: imx8mq: Add NWL MIPI DSI controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a node for the Northwest Logic MIPI DSI IP core, "disabled" by default. This also adds the necessary port to LCDIF. Signed-off-by: Guido Günther Reviewed-by: Fabio Estevam Tested-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 49 +++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 0d02ccdb0abc..4c7d2146bce2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -523,6 +523,12 @@ <&clk IMX8MQ_VIDEO_PLL1_OUT>; assigned-clock-rates = <0>, <0>, <0>, <594000000>; status = "disabled"; + + port@0 { + lcdif_mipi_dsi: endpoint { + remote-endpoint = <&mipi_dsi_lcdif_in>; + }; + }; }; iomuxc: pinctrl@30330000 { @@ -899,6 +905,49 @@ }; }; + mipi_dsi: mipi-dsi@30a00000 { + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30a00000 0x300>; + clocks = <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, + <&clk IMX8MQ_SYS1_PLL_266M>; + assigned-clock-rates = <80000000>, <266000000>, <20000000>; + interrupts = ; + mux-controls = <&mux 0>; + power-domains = <&pgc_mipi>; + phys = <&dphy>; + phy-names = "dphy"; + resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, + <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; + reset-names = "byte", "dpi", "esc", "pclk"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_dsi_lcdif_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + }; + }; + dphy: dphy@30a00300 { compatible = "fsl,imx8mq-mipi-dphy"; reg = <0x30a00300 0x100>; -- cgit v1.2.3 From e8151ef3578c9529f1b69f08bfcfd1e67e676e82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Thu, 20 Aug 2020 10:50:57 +0200 Subject: arm64: dts: imx8mq-librem5-devkit: Enable the LCD panel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable LCD panel output by adding nodes for the NWL DSI host controller, the Rocktech panel and the eLCDIF display controller. Signed-off-by: Guido Günther Reviewed-by: Fabio Estevam Tested-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5-devkit.dts | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 6900ac274f5b..51fdc969f3d5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -834,6 +834,39 @@ }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "rocktech,jh057n00900"; + reg = <0>; + backlight = <&backlight_dsi>; + reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + iovcc-supply = <®_1v8_p>; + vcc-supply = <®_2v8_p>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + &pgc_gpu { power-supply = <&buck3_reg>; }; -- cgit v1.2.3 From 32b0aaa59da62a5b4c2f3e7ca44f10853259572b Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Fri, 21 Aug 2020 14:17:55 +0200 Subject: dt-bindings: arm: fsl: Add the librem 5 phone Add entries for the imx8mq based Librem 5 phone. The "Birch" and "Chestnut" hardware revisions are supported by r2. The "Dogwood" revision by r3. See https://puri.sm/products/librem-5/ and https://developer.puri.sm/Librem5/ for the schematics and more information. Signed-off-by: Martin Kepplinger Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 788a8871fb82..ac6327cf53fd 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -369,6 +369,8 @@ properties: - fsl,imx8mq-evk # i.MX8MQ EVK Board - google,imx8mq-phanbell # Google Coral Edge TPU - purism,librem5-devkit # Purism Librem5 devkit + - purism,librem5r2 # Purism Librem5 phone "Chestnut" + - purism,librem5r3 # Purism Librem5 phone "Dogwood" - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk - const: fsl,imx8mq -- cgit v1.2.3 From 8f0216b006e5f553d28c4c1a991b5234693a49cb Mon Sep 17 00:00:00 2001 From: "Angus Ainslie (Purism)" Date: Fri, 21 Aug 2020 14:17:53 +0200 Subject: arm64: dts: Add a device tree for the Librem 5 phone MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a devicetree description for the Librem 5 phone. 4 hardware revisions have been available. Some revisions include changes that need different software to be run. So far, r3 ("Dogwood") is one such example, see: "Aspen" r0 not supported (very few devices exist) "Birch" r1 supported by r2 "Chestnut" r2 added by this patch "Dogwood" r3 added by this patch "Evergreen" r4 tba / most likely supported by r3 See https://puri.sm/products/librem-5/ for more information. This boots to a working console with working WWAN modem, wifi usdhc, IMU sensor device, proximity sensor, haptic motor, gpio keys, GNSS and LEDs. Signed-off-by: Martin Kepplinger Signed-off-by: Angus Ainslie (Purism) Signed-off-by: Guido Günther Reviewed-by: Daniel Baluta (for the audio part) Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../arm64/boot/dts/freescale/imx8mq-librem5-r2.dts | 29 + .../arm64/boot/dts/freescale/imx8mq-librem5-r3.dts | 27 + arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1105 ++++++++++++++++++++ 4 files changed, 1163 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a39f0a1723e0..97335205b600 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -35,6 +35,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts new file mode 100644 index 000000000000..d77fc5df3f06 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Purism SPC +// +// Librem 5 Chestnut + +/dts-v1/; + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r2"; + compatible = "purism,librem5r2", "purism,librem5", "fsl,imx8mq"; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4192000>; /* uV */ + ti,charge-current = <1600000>; /* uA */ + ti,termination-current = <66000>; /* uA */ +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; +}; + +&proximity { + proximity-near-level = <220>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts new file mode 100644 index 000000000000..6704ea2c72a3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Purism SPC + +/dts-v1/; + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r3"; + compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4200000>; /* uV */ + ti,charge-current = <1500000>; /* uA */ + ti,termination-current = <144000>; /* uA */ +}; + +&proximity { + proximity-near-level = <25>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi new file mode 100644 index 000000000000..c3e290703fe8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -0,0 +1,1105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2020 Purism SPC + */ + +/dts-v1/; + +#include "dt-bindings/input/input.h" +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/usb/pd.h" +#include "imx8mq.dtsi" + +/ { + model = "Purism Librem 5"; + compatible = "purism,librem5", "fsl,imx8mq"; + + backlight_dsi: backlight-dsi { + compatible = "led-backlight"; + leds = <&led_backlight>; + }; + + pmic_osc: clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic_osc"; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keys>; + + vol-down { + label = "VOL_DOWN"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + vol-up { + label = "VOL_UP"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reg_aud_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopwr>; + regulator-name = "AUDIO_PWR_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_gnss: regulator-gnss { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gnsspwr>; + regulator-name = "GNSS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_hub: regulator-hub { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hub_pwr>; + regulator-name = "HUB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_3v4: regulator-lcd-3v4 { + compatible = "regulator-fixed"; + regulator-name = "LCD_3V4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsibiasen>; + vin-supply = <®_vsys_3v4>; + gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_sen: regulator-vdd-sen { + compatible = "regulator-fixed"; + regulator-name = "VDD_SEN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vsys_3v4: regulator-vsys-3v4 { + compatible = "regulator-fixed"; + regulator-name = "VSYS_3V4"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + reg_wifi_3v3: regulator-wifi-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3_WIFI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + simple-audio-card,name = "Librem 5"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Microphone", "Digital Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic", + "DMICDAT", "Digital Mic"; + simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + frame-master; + bitclock-master; + }; + }; + + sound-wwan { + compatible = "simple-audio-card"; + simple-audio-card,name = "Modem"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sai6>; + frame-inversion; + }; + + simple-audio-card,codec { + sound-dai = <&bm818_codec>; + frame-master; + bitclock-master; + }; + }; + + bm818_codec: sound-wwan-codec { + compatible = "broadmobi,bm818", "option,gtm601"; + #sound-dai-cells = <0>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&pwm1 0 1000000000 0>; + pwm-names = "enable"; + vcc-supply = <®_vdd_3v3>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: ddrc-opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_5v>; + + pmic-5v { + gpio-hog; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + input; + }; +}; + +&iomuxc { + pinctrl_audiopwr: audiopwrgrp { + fsl,pins = < + /* AUDIO_POWER_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x83 + >; + }; + + pinctrl_bl: blgrp { + fsl,pins = < + /* BACKLINGE_EN */ + MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 + >; + }; + + pinctrl_charger_in: chargeringrp { + fsl,pins = < + /* CHRG_INT */ + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x00 + /* CHG_STATUS_B */ + MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 + >; + }; + + pinctrl_dsibiasen: dsibiasengrp { + fsl,pins = < + /* DSI_BIAS_EN */ + MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x83 + >; + }; + + pinctrl_dsien: dsiengrp { + fsl,pins = < + /* DSI_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 + >; + }; + + pinctrl_ecspi1: ecspigrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x83 + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x83 + >; + }; + + pinctrl_gauge: gaugegrp { + fsl,pins = < + /* BAT_LOW */ + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x80 + >; + }; + + pinctrl_gnsspwr: gnsspwrgrp { + fsl,pins = < + /* GPS3V3_EN */ + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x83 + >; + }; + + pinctrl_haptic: hapticgrp { + fsl,pins = < + /* MOTO */ + MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + /* HEADPHONE_DET_1V8 */ + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x180 + >; + }; + + pinctrl_hub_pwr: hubpwrgrp { + fsl,pins = < + /* HUB_PWR_3V3_EN */ + MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x83 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026 + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 + >; + }; + + pinctrl_keys: keysgrp { + fsl,pins = < + /* VOL- */ + MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 + /* VOL+ */ + MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 + >; + }; + + pinctrl_led_b: ledbgrp { + fsl,pins = < + /* LED_B */ + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x06 + >; + }; + + pinctrl_led_g: ledggrp { + fsl,pins = < + /* LED_G */ + MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x06 + >; + }; + + pinctrl_led_r: ledrgrp { + fsl,pins = < + /* LED_R */ + MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x06 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + /* INT_MAG */ + MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x80 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + /* PMIC_NINT */ + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 + >; + }; + + pinctrl_pmic_5v: pmic5vgrp { + fsl,pins = < + /* PMIC_5V */ + MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x80 + >; + }; + + pinctrl_prox: proxgrp { + fsl,pins = < + /* INT_LIGHT */ + MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x80 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + /* RTC_INT */ + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + >; + }; + + pinctrl_sai6: sai6grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 + >; + }; + + pinctrl_tcpc: tcpcgrp { + fsl,pins = < + /* TCPC_INT */ + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + /* TYPEC_MUX_EN */ + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x83 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf + MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + /* nWDOG */ + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f + >; + }; +}; + +&i2c1 { + clock-frequency = <387000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + typec_pd: usb-pd@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + connector { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb_con_ss: endpoint { + remote-endpoint = <&typec_ss>; + }; + }; + }; + }; + }; + + pmic: pmic@4b { + compatible = "rohm,bd71837"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + clocks = <&pmic_osc>; + clock-names = "osc"; + clock-output-names = "pmic_clk"; + interrupt-parent = <&gpio1>; + interrupts = <7 GPIO_ACTIVE_LOW>; + interrupt-names = "irq"; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <900000>; + rohm,dvs-idle-voltage = <850000>; + rohm,dvs-suspend-voltage = <800000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + rohm,dvs-run-voltage = <900000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + rohm,dvs-run-voltage = <1000000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "BUCK7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "BUCK8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + /* leave on for snvs power button */ + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + /* leave on for snvs power button */ + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + /* VDD_PHY_0V9 - MIPI and HDMI domains */ + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + /* VDD_PHY_3V3 - USB domain */ + regulator-name = "LDO7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + clock-frequency = <387000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + magnetometer@1e { + compatible = "st,lsm9ds1-magn"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + vdd-supply = <®_vdd_sen>; + vddio-supply = <®_vdd_1v8>; + }; + + regulator@3e { + compatible = "tps65132"; + reg = <0x3e>; + + outp { + regulator-name = "LCD_AVDD"; + vin-supply = <®_lcd_3v4>; + }; + + outn { + regulator-name = "LCD_AVEE"; + vin-supply = <®_lcd_3v4>; + }; + }; + + proximity: prox@60 { + compatible = "vishay,vcnl4040"; + reg = <0x60>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_prox>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + }; + + accel_gyro: accel-gyro@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + vdd-supply = <®_vdd_sen>; + vddio-supply = <®_vdd_1v8>; + }; +}; + +&i2c3 { + clock-frequency = <387000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + mic-cfg = <0x200>; + DCVDD-supply = <®_aud_1v8>; + DBVDD-supply = <®_aud_1v8>; + AVDD-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + MICVDD-supply = <®_aud_1v8>; + PLLVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_vsys_3v4>; + SPKVDD2-supply = <®_vsys_3v4>; + gpio-cfg = < + 0x0000 /* n/c */ + 0x0001 /* gpio2, 1: default */ + 0x0013 /* gpio3, 2: dmicclk */ + 0x0000 /* n/c, 3: default */ + 0x8014 /* gpio5, 4: dmic_dat */ + 0x0000 /* gpio6, 5: default */ + >; + }; + + backlight@36 { + compatible = "ti,lm36922"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bl>; + #address-cells = <1>; + #size-cells = <0>; + enable-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + vled-supply = <®_vsys_3v4>; + ti,ovp-microvolt = <25000000>; + + led_backlight: led@0 { + reg = <0>; + label = ":backlight"; + linux,default-trigger = "backlight"; + led-max-microamp = <20000>; + }; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1440>; + }; +}; + +&i2c4 { + clock-frequency = <387000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + bat: fuel-gauge@36 { + compatible = "maxim,max17055"; + reg = <0x36>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gauge>; + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; + maxim,rsns-microohm = <5000>; + }; + + bq25895: charger@6a { + compatible = "ti,bq25895", "ti,bq25890"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_in>; + interrupt-parent = <&gpio3>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + phys = <&usb3_phy0>; + ti,precharge-current = <130000>; /* uA */ + ti,minimum-sys-voltage = <3700000>; /* uV */ + ti,boost-voltage = <5000000>; /* uV */ + ti,boost-max-current = <500000>; /* uA */ + ti,use-vinmin-threshold = <1>; /* enable VINDPM */ + ti,vinmin-threshold = <3900000>; /* uV */ + monitored-battery = <&bat>; + }; +}; + +&pgc_gpu { + power-supply = <&buck3_reg>; +}; + +&pgc_mipi { + power-supply = <&ldo5_reg>; +}; + +&pgc_vpu { + power-supply = <&buck4_reg>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_haptic>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_b>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_g>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_r>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; + assigned-clock-rates = <786432000>, <722534400>; + status = "okay"; +}; + +&sai6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai6>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { /* TPS - GPS - DEBUG */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; + + gnss { + compatible = "globaltop,pa6h"; + vcc-supply = <®_gnss>; + current-speed = <9600>; + }; +}; + +&uart3 { /* SMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_hub>; + status = "okay"; +}; + +&usb_dwc3_0 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "otg"; + snps,dis_u3_susphy_quirk; + status = "okay"; + + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip USB2642 */ + hub@1 { + compatible = "usb424,2640"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mass-storage@1 { + compatible = "usb424,4041"; + reg = <1>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + vmmc-supply = <®_vdd_3v3>; + power-supply = <®_vdd_1v8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_wifi_3v3>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + cap-sdio-irq; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; -- cgit v1.2.3 From 8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 15 Aug 2020 20:22:23 +0200 Subject: ARM: dts: meson: move the L2 cache-controller inside the SoC node All IO mapped SoC peripherals should be within the "soc" node. Move the L2 cache-controller there as well since it's the only one not following this pattern. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Tested-by: Kevin Hilman Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20200815182223.408965-1-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index eadb0832bcfc..7649dd1e0b9e 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -11,13 +11,6 @@ #size-cells = <1>; interrupt-parent = <&gic>; - L2: cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -172,6 +165,13 @@ }; }; + L2: cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + periph: bus@c4300000 { compatible = "simple-bus"; reg = <0xc4300000 0x10000>; -- cgit v1.2.3 From c3b1d561869a03e2f10465309be35f939d4dd8e8 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 24 Aug 2020 14:19:44 -0700 Subject: ARM: dts: aspeed: Remove flash layout from Facebook AST2500 Common dtsi Remove FMC flash layout from ast2500-facebook-netbmc-common.dtsi because flash size and layout varies across different Facebook AST2500 OpenBMC platforms. Signed-off-by: Tao Ren Link: https://lore.kernel.org/r/20200824211948.12852-2-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi index 7468f102bd76..c0c43b8644ee 100644 --- a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi +++ b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi @@ -47,25 +47,12 @@ status = "okay"; m25p,fast-read; label = "spi0.0"; - -#include "facebook-bmc-flash-layout.dtsi" }; fmc_flash1: flash@1 { status = "okay"; m25p,fast-read; label = "spi0.1"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x2000000>; - label = "flash1"; - }; - }; }; }; -- cgit v1.2.3 From f883a606097d0017079b0e40125aac47ab221616 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 24 Aug 2020 14:19:45 -0700 Subject: ARM: dts: aspeed: cmm: Set 32MB FMC flash layout Set 32MB FMC flash layout in CMM device tree explicitly because the flash layout settings were removed from "ast2500-facebook-netbmc-common.dtsi". Signed-off-by: Tao Ren Link: https://lore.kernel.org/r/20200824211948.12852-3-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index 7bc7df7ed428..2fb8b147f489 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -1571,3 +1571,20 @@ &sdhci1 { status = "disabled"; }; + +&fmc_flash0 { +#include "facebook-bmc-flash-layout.dtsi" +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; +}; -- cgit v1.2.3 From 11c4124d5343b86e828c7c120cb8d1ece720dd0c Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 24 Aug 2020 14:19:46 -0700 Subject: ARM: dts: aspeed: yamp: Set 32MB FMC flash layout Set 32MB FMC flash layout in Yamp device tree explicitly because flash layout settings were removed from "ast2500-facebook-netbmc-common.dtsi". Signed-off-by: Tao Ren Link: https://lore.kernel.org/r/20200824211948.12852-4-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts index fe2e11c2da15..5e6105874217 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts @@ -108,3 +108,20 @@ &i2c13 { status = "okay"; }; + +&fmc_flash0 { +#include "facebook-bmc-flash-layout.dtsi" +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; +}; -- cgit v1.2.3 From ac6cec4c3acfb5fc64533d6b2b79c4c8020d2974 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 24 Aug 2020 14:19:47 -0700 Subject: ARM: dts: aspeed: minipack: Update 64MB FMC flash layout Set 64Mb FMC flash layout in Minipack device tree explicitly because the flash layout was removed from "ast2500-facebook-netbmc-common.dtsi". Please note "data0" partition' size is updated to 4MB to be consistent with other Facebook OpenBMC platforms. Signed-off-by: Tao Ren Link: https://lore.kernel.org/r/20200824211948.12852-5-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts | 47 +++++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts index 88ce4ff9f47e..c34741dbd268 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts @@ -88,17 +88,60 @@ */ &fmc_flash0 { partitions { - data0@1c00000 { - reg = <0x1c00000 0x2400000>; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * u-boot partition: 384KB. + */ + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; }; + + /* + * u-boot environment variables: 128KB. + */ + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "env"; + }; + + /* + * FIT image: 59.5 MB. + */ + fit@80000 { + reg = <0x80000 0x3b80000>; + label = "fit"; + }; + + /* + * "data0" partition (4MB) is reserved for persistent + * data store. + */ + data0@3800000 { + reg = <0x3c00000 0x400000>; + label = "data0"; + }; + + /* + * "flash0" partition (covering the entire flash) is + * explicitly created to avoid breaking legacy applications. + */ flash0@0 { reg = <0x0 0x4000000>; + label = "flash0"; }; }; }; &fmc_flash1 { partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + flash1@0 { reg = <0x0 0x4000000>; }; -- cgit v1.2.3 From bc8d756d5ba03f2a7b5365ae76c8925fbc1f4b70 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 24 Aug 2020 14:19:48 -0700 Subject: ARM: dts: aspeed: Add Facebook Wedge400 BMC Add initial version of device tree for Facebook Wedge400 (AST2500) BMC. Signed-off-by: Tao Ren Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200824211948.12852-6-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts | 420 +++++++++++++++++++++ 2 files changed, 421 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..e252cfff1830 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1371,6 +1371,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ aspeed-bmc-facebook-wedge100.dtb \ + aspeed-bmc-facebook-wedge400.dtb \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-ibm-rainier.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts new file mode 100644 index 000000000000..ad1fcad3676c --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2019 Facebook Inc. +/dts-v1/; + +#include +#include "ast2500-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Wedge 400 BMC"; + compatible = "facebook,wedge400-bmc", "aspeed,ast2500"; + + aliases { + /* + * PCA9548 (2-0070) provides 8 channels connecting to + * SCM (System Controller Module). + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * PCA9548 (8-0070) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * PCA9548 (11-0076) provides 8 channels connecting to + * FCM (Fan Controller Module). + */ + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + + spi2 = &spi_gpio; + }; + + chosen { + stdout-path = &uart1; + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; + }; + + /* + * GPIO-based SPI Master is required to access SPI TPM, because + * full-duplex SPI transactions are not supported by ASPEED SPI + * Controllers. + */ + spi_gpio: spi-gpio { + status = "okay"; + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; + gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + tpmdev@0 { + compatible = "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +/* + * Both firmware flashes are 128MB on Wedge400 BMC. + */ +&fmc_flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * u-boot partition: 384KB. + */ + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; + }; + + /* + * u-boot environment variables: 128KB. + */ + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "env"; + }; + + /* + * FIT image: 123.5 MB. + */ + fit@80000 { + reg = <0x80000 0x7b80000>; + label = "fit"; + }; + + /* + * "data0" partition (4MB) is reserved for persistent + * data store. + */ + data0@3800000 { + reg = <0x7c00000 0x800000>; + label = "data0"; + }; + + /* + * "flash0" partition (covering the entire flash) is + * explicitly created to avoid breaking legacy applications. + */ + flash0@0 { + reg = <0x0 0x8000000>; + label = "flash0"; + }; + }; +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x8000000>; + label = "flash1"; + }; + }; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +/* + * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC + * communication. + */ +&i2c0 { + status = "okay"; + multi-master; + bus-frequency = <1000000>; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&sdhci1 { + /* + * DMA mode needs to be disabled to avoid conflicts with UHCI + * Controller in AST2500 SoC. + */ + sdhci-caps-mask = <0x0 0x580000>; +}; -- cgit v1.2.3 From fe84b8fd24d0fca26ce7a5f95beb66037decf7bf Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 24 Aug 2020 11:29:54 -0700 Subject: ARM: dts: aspeed: wedge40: Update FMC flash0 label Update FMC flash0's label to "spi0.0" so it's consistent with all the other Facebook OpenBMC platforms. Signed-off-by: Tao Ren Link: https://lore.kernel.org/r/20200824182955.7988-2-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts index 8ac23ff6b09e..3f2a48fa77b3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts @@ -48,7 +48,7 @@ flash@0 { status = "okay"; m25p,fast-read; - label = "fmc0"; + label = "spi0.0"; #include "facebook-bmc-flash-layout.dtsi" }; }; -- cgit v1.2.3 From 7c32a9d95c9af768cf6d192f0b2f72f22d8c2cde Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 24 Aug 2020 11:29:55 -0700 Subject: ARM: dts: aspeed: wedge40: Update UART4 pin settings Enable UART4's NRTS4 (A19) pin because the pin is used for RS485 software emulation. Signed-off-by: Tao Ren Link: https://lore.kernel.org/r/20200824182955.7988-3-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts index 3f2a48fa77b3..8c426ba2f8ab 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts @@ -71,7 +71,8 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; + &pinctrl_rxd4_default + &pinctrl_ndts4_default>; }; &uart5 { -- cgit v1.2.3 From edb1a2e256473e4b5ab953e099096645d4508a4e Mon Sep 17 00:00:00 2001 From: Eddie James Date: Mon, 17 Aug 2020 12:53:06 -0500 Subject: ARM: dts: aspeed: rainier: Enable XDMA engine Fix the VGA reserved memory node, and add the XDMA engine node, enable it, and point it's memory region to the VGA memory. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index b94421f6cbd5..d64ff64b8020 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -52,9 +52,10 @@ }; vga_memory: region@bf000000 { - no-map; - reg = <0xbf000000 0x01000000>; /* 16M */ - }; + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; }; gpio-keys { @@ -1121,3 +1122,8 @@ spi-max-frequency = <100000000>; }; }; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; -- cgit v1.2.3 From 4a6c1be2f9d951d61239ec440c17a5c517c730ba Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 24 Aug 2020 17:04:33 +0200 Subject: dt-bindings: gpu: mali-utgard: Add Allwinner R40 compatible Allwinner R40 SoC contains Mali400, so add its specific compatible to bindings. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200824150434.951693-2-jernej.skrabec@siol.net --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml index 6226d31ec4b7..d4d785790eaa 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml @@ -25,6 +25,7 @@ properties: - allwinner,sun4i-a10-mali - allwinner,sun7i-a20-mali - allwinner,sun8i-h3-mali + - allwinner,sun8i-r40-mali - allwinner,sun50i-a64-mali - rockchip,rk3036-mali - rockchip,rk3066-mali @@ -129,6 +130,7 @@ allOf: enum: - allwinner,sun4i-a10-mali - allwinner,sun7i-a20-mali + - allwinner,sun8i-r40-mali - allwinner,sun50i-a64-mali - allwinner,sun50i-h5-mali - amlogic,meson8-mali -- cgit v1.2.3 From 12bb1887be9dc8ca88fccd4da4d8d9eaae561239 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 24 Aug 2020 17:04:34 +0200 Subject: ARM: dts: sun8i: r40: Add Mali node R40 has Mali400 GP2 GPU. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200824150434.951693-3-jernej.skrabec@siol.net --- arch/arm/boot/dts/sun8i-r40.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index b782041e0e04..b82031b19893 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -743,6 +743,28 @@ #size-cells = <0>; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + }; + gmac: ethernet@1c50000 { compatible = "allwinner,sun8i-r40-gmac"; syscon = <&ccu>; -- cgit v1.2.3 From 64faa1053197bd69204bdebe815aeb2447991481 Mon Sep 17 00:00:00 2001 From: Stefan Monnier Date: Fri, 21 Aug 2020 13:18:33 -0400 Subject: ARM: dts: sun4i: Enable HDMI support on the Mele A1000 Enable the display pipeline and HDMI output. Signed-off-by: Stefan Monnier Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200821171833.28177-1-monnier@iro.umontreal.ca --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 8692b11a83c3..af8ab736fd3c 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -60,6 +60,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -133,6 +144,20 @@ status = "okay"; }; +&de { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; -- cgit v1.2.3 From 0552942ffded1e30ca561b89d7e615292f4ed5b7 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:14:48 +0800 Subject: dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi There is no one use "allwinner,sun9i-a80-sc-nmi". The A80 uses "allwinner,sun9i-a80-nmi". Let's fix it. Signed-off-by: Yangtao Li Signed-off-by: Maxime Ripard Acked-by: Rob Herring Link: https://lore.kernel.org/r/fb081585c4fedcb9b8b95e5f16879dff482c9717.1595572867.git.frank@allwinnertech.com --- .../bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index 7cd6b8bacfa0..d8fe2d9a307b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -29,7 +29,7 @@ properties: - items: - const: allwinner,sun8i-a83t-r-intc - const: allwinner,sun6i-a31-r-intc - - const: allwinner,sun9i-a80-sc-nmi + - const: allwinner,sun9i-a80-nmi - items: - const: allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc -- cgit v1.2.3 From 5805c747f4db9ca679391559519c25aac734436b Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:15:53 +0800 Subject: dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller Add a binding for A100's nmi controller. Signed-off-by: Yangtao Li Signed-off-by: Maxime Ripard Acked-by: Rob Herring Link: https://lore.kernel.org/r/953b76413563551b82dd11cadbc99c695f74f721.1595572867.git.frank@allwinnertech.com --- .../bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index d8fe2d9a307b..8acca0ae3129 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -33,6 +33,9 @@ properties: - items: - const: allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc + - items: + - const: allwinner,sun50i-a100-nmi + - const: allwinner,sun9i-a80-nmi - items: - const: allwinner,sun50i-h6-r-intc - const: allwinner,sun6i-a31-r-intc -- cgit v1.2.3 From 0dea1794f3b4bca45affd8ae7eb0ac33fa1c0599 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:18:24 +0800 Subject: arm64: allwinner: A100: add the basical Allwinner A100 DTSI file Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds the basical DTSI file of it, including the clock, i2c, pins, sid, ths, nmi, and UART support. Signed-off-by: Yangtao Li Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/815a458de74b79eb649972de786e647be3846424.1595572867.git.frank@allwinnertech.com --- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 +++++++++++++++++++++++++ 1 file changed, 364 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi new file mode 100644 index 000000000000..cc321c04f121 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (c) 2020 Yangtao Li + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + dcxo24M: dcxo24M-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "dcxo24M"; + #clock-cells = <0>; + }; + + iosc: internal-osc-clk { + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + #clock-cells = <0>; + }; + + osc32k: osc32k-clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x3fffffff>; + + ccu: clock@3001000 { + compatible = "allwinner,sun50i-a100-ccu"; + reg = <0x03001000 0x1000>; + clocks = <&dcxo24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, <0x03022000 0x2000>, + <0x03024000 0x2000>, <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + efuse@3006000 { + compatible = "allwinner,sun50i-a100-sid", + "allwinner,sun50i-a64-sid"; + reg = <0x03006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: calib@14 { + reg = <0x14 8>; + }; + }; + + pio: pinctrl@300b000 { + compatible = "allwinner,sun50i-a100-pinctrl"; + reg = <0x0300b000 0x400>; + interrupts = , + , + , + , + , + , + ; + clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB9", "PB10"; + function = "uart0"; + }; + }; + + uart0: serial@5000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@5000400 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@5000800 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@5000c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@5001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x05001000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + i2c0: i2c@5002000 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@5002400 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@5002800 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@5002c00 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ths: thermal-sensor@5070400 { + compatible = "allwinner,sun50i-a100-ths"; + reg = <0x05070400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + + r_ccu: clock@7010000 { + compatible = "allwinner,sun50i-a100-r-ccu"; + reg = <0x07010000 0x300>; + clocks = <&dcxo24M>, <&osc32k>, <&iosc>, + <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + r_intc: interrupt-controller@7010320 { + compatible = "allwinner,sun50i-a100-nmi", + "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x07010320 0xc>; + interrupts = ; + }; + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun50i-a100-r-pinctrl"; + reg = <0x07022000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c0_pins: r-i2c0-pins { + pins = "PL0", "PL1"; + function = "s_i2c0"; + }; + + r_i2c1_pins: r-i2c1-pins { + pins = "PL8", "PL9"; + function = "s_i2c1"; + }; + }; + + r_uart: serial@7080000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07080000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_R_APB2_UART>; + resets = <&r_ccu RST_R_APB2_UART>; + status = "disabled"; + }; + + r_i2c0: i2c@7081400 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x07081400 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_APB2_I2C0>; + resets = <&r_ccu RST_R_APB2_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_i2c1: i2c@7081800 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x07081800 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_APB2_I2C1>; + resets = <&r_ccu RST_R_APB2_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + thermal-zones { + cpu-thermal-zone { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + ddr-thermal-zone { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; + + gpu-thermal-zone { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + }; +}; -- cgit v1.2.3 From 1c09280f0b214dfdb7b78336ff5c871108e5f3a9 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:20:12 +0800 Subject: dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings Document board compatible names for Allwinner A100 Perf1 Board. Signed-off-by: Yangtao Li Signed-off-by: Maxime Ripard Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/0368996b732f300d0b5719e51dbd4322fa09053d.1595572867.git.frank@allwinnertech.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index efc9118233b4..5957a22c2e95 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -16,6 +16,11 @@ properties: compatible: oneOf: + - description: Allwinner A100 Perf1 Board + items: + - const: allwinner,a100-perf1 + - const: allwinner,sun50i-a100 + - description: Allwinner A23 Evaluation Board items: - const: allwinner,sun8i-a23-evb -- cgit v1.2.3 From 95c83906380e77f5081b231bba625bdebc57d592 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:21:05 +0800 Subject: arm64: allwinner: A100: add support for Allwinner Perf1 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A100 perf1 is an Allwinner A100-based SBC, with the following features: - 1GiB DDR3 DRAM - AXP803 PMIC - 2 USB 2.0 ports - MicroSD slot and on-board eMMC module - on-board Nand flash - ··· Adds initial support for it, including UART and PMU. Signed-off-by: Yangtao Li Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/30f4a3fc6ac84d05094e2c3b89d1dddc8ff6b7fc.1595572867.git.frank@allwinnertech.com --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-a100-allwinner-perf1.dts | 180 +++++++++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 916d10d5b87c..211d1e9d4701 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts new file mode 100644 index 000000000000..d34c2bb1079f --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (c) 2020 Yangtao Li + */ + +/dts-v1/; + +#include "sun50i-a100.dtsi" + +/{ + model = "Allwinner A100 Perf1"; + compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pio { + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_eldo1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_dldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; + vcc-ph-supply = <®_dcdc1>; +}; + +&r_pio { + /* + * FIXME: We can't add that supply for now since it would + * create a circular dependency between pinctrl, the regulator + * and the RSB Bus. + * + * vcc-pl-supply = <®_aldo3>; + */ +}; + +&r_i2c0 { + status = "okay"; + + axp803: pmic@34 { + compatible = "x-powers,axp803"; + reg = <0x34>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dram-1"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-pl"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io-usb-pd-emmc-nand-card"; +}; + +®_dcdc2 { + regulator-always-on; + /* + * FIXME: update min and max before support dvfs. + */ + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd-sys-usb-dram"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram-2"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pg-dcxo-wifi"; +}; + +®_dldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe-csi"; +}; + +®_dldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ldo-avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avcc-csi"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc-lvds-csi-efuse-emmc-nand"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi"; +}; + +®_eldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-mipi-lcd"; +}; + +®_fldo1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus-usb"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ctp"; + status = "okay"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; -- cgit v1.2.3 From 578450883bb1ff878ac8e3d38060802b222adcbe Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 14 Aug 2020 18:30:35 +0100 Subject: arm64: dts: renesas: r8a774a1: Add PCIe EP nodes Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20200814173037.17822-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 8e80f50132ad..8f4820c6ce6b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2371,6 +2371,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774a1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a774a1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; -- cgit v1.2.3 From d12d16205f7993da195002eea24b7467deb9ac8c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 14 Aug 2020 18:30:36 +0100 Subject: arm64: dts: renesas: r8a774b1: Add PCIe EP nodes Add PCIe EP nodes to R8A774B1 (RZ/G2N) SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20200814173037.17822-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 49e5addcfd97..b078782119a1 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2240,6 +2240,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774b1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a774b1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; -- cgit v1.2.3 From 0c77ecdcfcd35e97c677e49a8516a0b10c1e8fb7 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 14 Aug 2020 18:30:37 +0100 Subject: arm64: dts: renesas: r8a774c0: Add PCIe EP node Add PCIe EP node to R8A774C0 (RZ/G2E) SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20200814173037.17822-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 42171190cce4..10e79f2c0c4e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1698,6 +1698,25 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774c0-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + status = "disabled"; + }; + vspb0: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; -- cgit v1.2.3 From 5a81ade1dd284a25c25b7582e94e33e5690c3da5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 16 Aug 2020 20:07:32 +0100 Subject: ARM: dts: r8a7742: Add CAN support Add the definitions for can0 and can1 to the r8a7742 SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200816190732.6905-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 009827708bf4..0fc52b27ae64 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -36,6 +36,14 @@ clock-frequency = <0>; }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -951,6 +959,32 @@ status = "disabled"; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; -- cgit v1.2.3 From be571bec2cfdb7aaa096d547aa8a1559a0c0cc90 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 16 Aug 2020 20:33:14 +0100 Subject: ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically Sort the DT nodes alphabetically so that its easier to maintain. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200816193316.7641-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi index 85aff429d408..6e8df79bea94 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -35,13 +35,6 @@ clock-frequency = <20000000>; }; -&pfc { - mmc1_pins: mmc1 { - groups = "mmc1_data4", "mmc1_ctrl"; - function = "mmc1"; - }; -}; - &mmcif1 { pinctrl-0 = <&mmc1_pins>; pinctrl-names = "default"; @@ -51,3 +44,10 @@ non-removable; status = "okay"; }; + +&pfc { + mmc1_pins: mmc1 { + groups = "mmc1_data4", "mmc1_ctrl"; + function = "mmc1"; + }; +}; -- cgit v1.2.3 From c0ed2ee793f1f5c15d88c0dd458504b7b2aa9d6a Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 16 Aug 2020 20:33:15 +0100 Subject: ARM: dts: r8a7742-iwg21m: Add RTC support Enable BQ32000 RTC which is connected to I2C0 on the iWave RainboW-G21M-q7 SOM. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200816193316.7641-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi index 6e8df79bea94..0f26807f92b8 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -35,6 +35,21 @@ clock-frequency = <20000000>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &mmcif1 { pinctrl-0 = <&mmc1_pins>; pinctrl-names = "default"; @@ -46,6 +61,11 @@ }; &pfc { + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + mmc1_pins: mmc1 { groups = "mmc1_data4", "mmc1_ctrl"; function = "mmc1"; -- cgit v1.2.3 From 7da4d2a8c6bc927870aa81d52af68a9bb944be33 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 19 Aug 2020 09:08:41 +0100 Subject: arm64: dts: renesas: r8a774e1-hihope-rzg2h: Enable HS400 mode This patch enables HS400 mode on HiHope RZ/G2H board. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200819080841.3475-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts index 12f9242e263b..9525d5ed6fce 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts @@ -35,3 +35,7 @@ clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; + +&sdhi3 { + mmc-hs400-1_8v; +}; -- cgit v1.2.3 From 4c508a44d400c9e5be7e18733ae0e7377b2fdec6 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 25 Aug 2020 12:00:29 +0200 Subject: dt-bindings: dma: allwinner,sun50i-a64-dma: Add R40 compatible R40 has DMA engine which is basically the same as that in A64, with only known difference being number of request sources and number of channels. Add compatible for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200825100030.1145356-2-jernej.skrabec@siol.net --- .../devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index 9e53472be194..372679dbd216 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -19,9 +19,12 @@ properties: description: The cell is the request line number. compatible: - enum: - - allwinner,sun50i-a64-dma - - allwinner,sun50i-h6-dma + oneOf: + - const: allwinner,sun50i-a64-dma + - const: allwinner,sun50i-h6-dma + - items: + - const: allwinner,sun8i-r40-dma + - const: allwinner,sun50i-a64-dma reg: maxItems: 1 -- cgit v1.2.3 From 5822bfed6472340f882b43d5c2f2629091191c9d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 25 Aug 2020 12:00:30 +0200 Subject: ARM: dts: sun8i: r40: Add DMA node Allwinner R40 SoC has DMA with 16 channels and 31 request sources. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200825100030.1145356-3-jernej.skrabec@siol.net --- arch/arm/boot/dts/sun8i-r40.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index b82031b19893..d481fe7989b8 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -198,6 +198,18 @@ interrupts = ; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-r40-dma", + "allwinner,sun50i-a64-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + dma-channels = <16>; + dma-requests = <31>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + spi0: spi@1c05000 { compatible = "allwinner,sun8i-r40-spi", "allwinner,sun8i-h3-spi"; -- cgit v1.2.3 From c05a4bff5c509afda0ee60009d62b5abc0e08311 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Sat, 22 Aug 2020 17:10:20 +0200 Subject: dt-bindings: arm: at91: Add GARDENA smart Gateway (Art. 19000) board Document devicetree's bindings for the GARDENA smart Gateway with article number 19000, based on the SAM9G25 Atmel SoC. Signed-off-by: Reto Schneider Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20200822151023.31629-1-code@reto-schneider.ch --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 31b0c54fa2cf..614c91956798 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -41,6 +41,7 @@ properties: - overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board - overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN - overkiz,smartkiz # Overkiz SmartKiz Board + - gardena,smart-gateway-at91sam # GARDENA smart Gateway (Article No. 19000) - const: atmel,at91sam9g25 - const: atmel,at91sam9x5 - const: atmel,at91sam9 -- cgit v1.2.3 From 25ffa0dde53c14cd6ddc938e39f70db4f8837591 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Sat, 22 Aug 2020 17:10:21 +0200 Subject: ARM: at91: Add GARDENA smart Gateway (Art. 19000) support This patch adds support for the GARDENA smart Gateway, which is based on the Atmel AT91SAM9G25. It is equipped with 128 MiB of DDR2 RAM and 256 MiB NAND storage. Please note that this gateway is not actually based on a AT91SAM9x5 EK board, but is close enough to allow its DT to be used. Co-developed-by: Stefan Roese Co-developed-by: Michael Zimmermann Signed-off-by: Stefan Roese Signed-off-by: Michael Zimmermann Signed-off-by: Reto Schneider Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20200822151023.31629-2-code@reto-schneider.ch --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/at91sam9g25-gardena-smart-gateway.dts | 158 +++++++++++++++++++++ 2 files changed, 159 insertions(+) create mode 100644 arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..04244e6fafa5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -43,6 +43,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91-smartkiz.dtb \ at91-wb45n.dtb \ at91sam9g15ek.dtb \ + at91sam9g25-gardena-smart-gateway.dtb \ at91sam9g25ek.dtb \ at91sam9g35ek.dtb \ at91sam9x25ek.dtb \ diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts new file mode 100644 index 000000000000..7da70aeeb528 --- /dev/null +++ b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the GARDENA smart Gateway (Article No. 19000) + * + * Copyright (C) 2020 GARDENA GmbH + */ + +/dts-v1/; + +#include "at91sam9g25.dtsi" +#include "at91sam9x5ek.dtsi" +#include + +/ { + model = "GARDENA smart Gateway (Article No. 19000)"; + compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9g25", "atmel,at91sam9x5", + "atmel,at91sam9"; + + aliases { + serial1 = &usart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user_btn1 { + label = "USER_BTN1"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + 1wire_cm { + status = "disabled"; + }; + + leds { + compatible = "gpio-leds"; + + power_blue { + label = "smartgw:power:blue"; + gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power_green { + label = "smartgw:power:green"; + gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + power_red { + label = "smartgw:power:red"; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_blue { + label = "smartgw:radio:blue"; + gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_green { + label = "smartgw:radio:green"; + gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_red { + label = "smartgw:radio:red"; + gpios = <&pioC 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_blue { + label = "smartgw:internet:blue"; + gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_green { + label = "smartgw:internet:green"; + gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_red { + label = "smartgw:internet:red"; + gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat { + label = "smartgw:heartbeat"; + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + pb18 { + status = "disabled"; + }; + + pd21 { + status = "disabled"; + }; + }; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&usart0 { + status = "disabled"; +}; + +&usart2 { + status = "disabled"; +}; + +&usart3 { + status = "okay"; + + pinctrl-0 = <&pinctrl_usart3 + &pinctrl_usart3_rts + &pinctrl_usart3_cts + >; +}; + +&watchdog { + status = "okay"; +}; + +&mmc0 { + status = "disabled"; +}; + +&mmc1 { + status = "disabled"; +}; + +&spi0 { + status = "disabled"; +}; + +&i2c0 { + status = "disabled"; +}; + +&adc0 { + status = "disabled"; +}; + +&ssc0 { + status = "disabled"; +}; -- cgit v1.2.3 From a2e385f5374d09c76d3e081a847f30e0b91045a6 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Sat, 22 Aug 2020 18:19:18 +0200 Subject: dt-bindings: ARM: add bindings for the Meraki MR32 mark the Meraki MR32 and its SoC (BCM53016) as supported in the bindings documentation file. A quick look on Broadcom BCM5301x series umbrella website reveals: "BCM53012 and BCM53016 with dual-core Cortex-A9 CPU at 1 GHz, 256KB L2 cache, 16-bit DDR2 interface, USB3 integrated switch, GPHYs and packet accelerator". As far as I can tell, Broadcom considers the SoC to be a version of the BCM53012. Signed-off-by: Christian Lamparter Acked-by: Scott Branden Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index d48313c7ae45..988e0bbb2a62 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -83,6 +83,8 @@ properties: - brcm,bcm953012er - brcm,bcm953012hr - brcm,bcm953012k + - meraki,mr32 - const: brcm,brcm53012 + - const: brcm,brcm53016 - const: brcm,bcm4708 ... -- cgit v1.2.3 From 0ea4b29d149586667d96767f1fc8e57ee942c1b0 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Sat, 22 Aug 2020 18:19:19 +0200 Subject: ARM: dts: BCM5301X: Specify PWM in the DT The BCM53016 in the Meraki MR32 uses the on-chip PWM controller to drive a tri-color RGB LED. Since I plan to use the PWM, I made a label for the pwm's pinmux node. This way, it can be easily referenced.... And Also included a label for the i2c since I'm going to need it in the future too. Signed-off-by: Christian Lamparter Acked-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 2d9b4dd05830..45cd8c7411dd 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -350,6 +350,14 @@ }; }; + pwm: pwm@18002000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18002000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + mdio: mdio@18003000 { compatible = "brcm,iproc-mdio"; reg = <0x18003000 0x8>; @@ -417,12 +425,12 @@ function = "spi"; }; - i2c { + pinmux_i2c: i2c { groups = "i2c_grp"; function = "i2c"; }; - pwm { + pinmux_pwm: pwm { groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; function = "pwm"; -- cgit v1.2.3 From 5e396bb05b89e23e98e6d75749b77502e68210a4 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Sat, 22 Aug 2020 18:19:20 +0200 Subject: ARM: dts: BCM5301X: Specify uart2 in the DT The BCM53016 in the Meraki MR32 utilizes the third "uart2" to connect to a on-board Bluetooth-LE 4.0 BCM20732 chip. Signed-off-by: Christian Lamparter Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 45cd8c7411dd..eb1290fed235 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -392,6 +392,15 @@ reg = <0x18105000 0x1000>; }; + uart2: serial@18008000 { + compatible = "ns16550a"; + reg = <0x18008000 0x20>; + clocks = <&iprocslow>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + i2c0: i2c@18009000 { compatible = "brcm,iproc-i2c"; reg = <0x18009000 0x50>; -- cgit v1.2.3 From c4cd6fcae46fd14aed8665b7cf66d0954765a873 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Sat, 22 Aug 2020 18:19:21 +0200 Subject: ARM: dts: BCM5301X: Specify pcie2 in the DT The SoC supports three pcie ports. Currently, only pcie0 and pcie1 are enabled. This patch adds the pcie2 port as well. Signed-off-by: Christian Lamparter Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index eb1290fed235..9d9e8fe3f6ae 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -252,6 +252,10 @@ reg = <0x00013000 0x1000>; }; + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; + usb2: usb2@21000 { reg = <0x00021000 0x1000>; -- cgit v1.2.3 From ee30214a4a79f1cea0b71d5412ba366a4b498937 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 25 Aug 2020 19:13:56 +0200 Subject: dt-bindings: media: allwinner, sun4i-a10-ir: Add R40 compatible Allwinner R40 has very similar IR core to that found in A31. Add compatible for R40 and while at it, sort compatibles by family. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200825171358.1286902-2-jernej.skrabec@siol.net --- Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml index 7838804700d6..5fa19d4aeaf3 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml @@ -18,10 +18,13 @@ properties: oneOf: - const: allwinner,sun4i-a10-ir - const: allwinner,sun5i-a13-ir + - const: allwinner,sun6i-a31-ir - items: - const: allwinner,sun8i-a83t-ir - const: allwinner,sun6i-a31-ir - - const: allwinner,sun6i-a31-ir + - items: + - const: allwinner,sun8i-r40-ir + - const: allwinner,sun6i-a31-ir - items: - const: allwinner,sun50i-a64-ir - const: allwinner,sun6i-a31-ir -- cgit v1.2.3 From 166405e1f89acf7b24d95b90dbd1f78ec1ab3ec6 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 25 Aug 2020 19:13:57 +0200 Subject: ARM: dts: sun8i: r40: Add IR nodes Allwinner R40 has two IR cores, add nodes for them. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200825171358.1286902-3-jernej.skrabec@siol.net --- arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d481fe7989b8..dff9a3dc1fba 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -513,6 +513,16 @@ function = "i2c4"; }; + ir0_pins: ir0-pins { + pins = "PB4"; + function = "ir0"; + }; + + ir1_pins: ir1-pins { + pins = "PB23"; + function = "ir1"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -591,6 +601,32 @@ clocks = <&osc24M>; }; + ir0: ir@1c21800 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21800 0x400>; + pinctrl-0 = <&ir0_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; + clock-names = "apb", "ir"; + interrupts = ; + resets = <&ccu RST_BUS_IR0>; + status = "disabled"; + }; + + ir1: ir@1c21c00 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21c00 0x400>; + pinctrl-0 = <&ir1_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; + clock-names = "apb", "ir"; + interrupts = ; + resets = <&ccu RST_BUS_IR1>; + status = "disabled"; + }; + ths: thermal-sensor@1c24c00 { compatible = "allwinner,sun8i-r40-ths"; reg = <0x01c24c00 0x100>; -- cgit v1.2.3 From 44406428f5764d7a71be3bafd642c8e02cdd5468 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 25 Aug 2020 19:13:58 +0200 Subject: ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable IR BananaPi M2 Ultra has IR receiver connected to IR0. Enable it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200825171358.1286902-4-jernej.skrabec@siol.net --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 42d62d1ba1dc..ca6088c87855 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -164,6 +164,10 @@ #include "axp22x.dtsi" +&ir0 { + status = "okay"; +}; + &mmc0 { vmmc-supply = <®_dcdc1>; bus-width = <4>; -- cgit v1.2.3 From 73225f0b4cd1056baedf73e5aff74108e5e5a4ab Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 25 Aug 2020 19:35:19 +0200 Subject: dt-bindings: sram: allwinner, sun4i-a10-system-control: Add R40 compatibles Allwinner R40 has system controller similar to that in A10. Add compatibles for system controller and sram c1 region. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200825173523.1289379-2-jernej.skrabec@siol.net --- .../bindings/sram/allwinner,sun4i-a10-system-control.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index f5825935fd22..6ebcbc153691 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -33,6 +33,9 @@ properties: - const: allwinner,sun4i-a10-system-control - const: allwinner,sun8i-a23-system-control - const: allwinner,sun8i-h3-system-control + - items: + - const: allwinner,sun8i-r40-system-control + - const: allwinner,sun4i-a10-system-control - const: allwinner,sun50i-a64-sram-controller deprecated: true - const: allwinner,sun50i-a64-system-control @@ -86,6 +89,9 @@ patternProperties: - items: - const: allwinner,sun8i-h3-sram-c1 - const: allwinner,sun4i-a10-sram-c1 + - items: + - const: allwinner,sun8i-r40-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 - items: - const: allwinner,sun50i-a64-sram-c1 - const: allwinner,sun4i-a10-sram-c1 -- cgit v1.2.3 From 3566b0869179779d3abc4b605dcc9d2121d67672 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 25 Aug 2020 19:35:20 +0200 Subject: ARM: dts: sun8i: r40: Add node for system controller Allwinner R40 has system controller and SRAM C1 region similar to that in A10. Add nodes for them. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200825173523.1289379-3-jernej.skrabec@siol.net --- arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index dff9a3dc1fba..0c7526365896 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -190,6 +190,29 @@ }; }; + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-r40-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-r40-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; -- cgit v1.2.3 From 228f1e6ab55f60f8cb3208dffc118afa6514b6af Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 3 Aug 2020 17:44:30 +0200 Subject: arm64: tegra: Add ID EEPROMs on Jetson AGX Xavier The P2888 processor module contains an EEPROM that provides means of identifying the module. The P2822 carrier board contains the same EEPROM with information identifying the carrier board. Both of them ar accessed via the GEN_I2C1 bus. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 13 +++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 4c005b811233..0ea0bd83cb8e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -57,6 +57,21 @@ status = "okay"; }; + i2c@3160000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + vcc-supply = <&vdd_1v8ls>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + /* SDMMC1 (SD/MMC) */ mmc@3400000 { cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 90b6ea5467fa..4d8a0e10250f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -23,6 +23,19 @@ }; }; + i2c@3160000 { + eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + + vcc-supply = <&vdd_1v8ls>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + ddc: i2c@31c0000 { status = "okay"; }; -- cgit v1.2.3 From a41315610bab6f152280975500f33e3b069e10ff Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:41:08 +0200 Subject: arm64: tegra: Wire up pinctrl states for all DPAUX controllers All four DPAUX controllers on Tegra194 control the pin configuration of their companion I2C controllers. Wire up all the pinctrl states for the I2C controllers so that their pins can be correctly muxed when needed. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 48160f48003a..466872a4512f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -329,6 +329,9 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C4>; reset-names = "i2c"; + pinctrl-0 = <&state_dpaux1_i2c>; + pinctrl-1 = <&state_dpaux1_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; @@ -343,10 +346,14 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C6>; reset-names = "i2c"; + pinctrl-0 = <&state_dpaux0_i2c>; + pinctrl-1 = <&state_dpaux0_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; - gen7_i2c: i2c@31c0000 { + /* shares pads with dpaux2 */ + dp_aux_ch2_i2c: i2c@31c0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x031c0000 0x10000>; interrupts = ; @@ -356,10 +363,14 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C7>; reset-names = "i2c"; + pinctrl-0 = <&state_dpaux2_i2c>; + pinctrl-1 = <&state_dpaux2_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; - gen9_i2c: i2c@31e0000 { + /* shares pads with dpaux3 */ + dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x031e0000 0x10000>; interrupts = ; @@ -369,6 +380,9 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C9>; reset-names = "i2c"; + pinctrl-0 = <&state_dpaux3_i2c>; + pinctrl-1 = <&state_dpaux3_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; -- cgit v1.2.3 From 78bc57ffa809222ff56c05181afe38fea1068ad8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:41:09 +0200 Subject: arm64: tegra: Add VBUS supply for micro USB port on Jetson Nano The VBUS supply for the micro USB port on Jetson Nano is derived from the main system supply and always on. Describe in nevertheless to fix warnings during boot. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 2282ea1c6279..b8d1fa72e177 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -541,6 +541,8 @@ mode = "peripheral"; usb-role-switch; + vbus-supply = <&vdd_5v0_usb>; + connector { compatible = "gpio-usb-b-connector", "usb-b-connector"; @@ -843,4 +845,14 @@ vin-supply = <&avdd_1v05_pll>; }; + + vdd_5v0_usb: regulator@8 { + compatible = "regulator-fixed"; + + regulator-name = "VDD_5V_USB"; + regulator-min-microvolt = <50000000>; + regulator-max-microvolt = <50000000>; + + vin-supply = <&vdd_5v0_sys>; + }; }; -- cgit v1.2.3 From da415b71cd4fe0f02dbe7c044392e74c6d091e26 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:41:10 +0200 Subject: arm64: tegra: Disable SD card write-protection on Jetson Nano There is no GPIO hooked up to the write-protection pin of the SD slot. Make sure to describe this properly in device tree to avoid errors or warnings being emitted by the operating system. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index b8d1fa72e177..553a5585edac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -576,6 +576,7 @@ bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + disable-wp; vqmmc-supply = <&vddio_sdmmc>; vmmc-supply = <&vdd_3v3_sd>; -- cgit v1.2.3 From 0cc6ba3ce87c2845689599a87ee993d1aec9ca89 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:41:11 +0200 Subject: arm64: tegra: Describe display controller outputs for Tegra210 Both display controllers can drive both DSI and both SOR outputs on Tegra210. Describe this in device tree so that the operating system doesn't have to guess. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 829f786af133..27d4e3f134ca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -194,6 +194,7 @@ iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,outputs = <&dsia &dsib &sor0 &sor1>; nvidia,head = <0>; }; @@ -208,10 +209,11 @@ iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,outputs = <&dsia &dsib &sor0 &sor1>; nvidia,head = <1>; }; - dsi@54300000 { + dsia: dsi@54300000 { compatible = "nvidia,tegra210-dsi"; reg = <0x0 0x54300000 0x0 0x00040000>; clocks = <&tegra_car TEGRA210_CLK_DSIA>, @@ -248,7 +250,7 @@ status = "disabled"; }; - dsi@54400000 { + dsib: dsi@54400000 { compatible = "nvidia,tegra210-dsi"; reg = <0x0 0x54400000 0x0 0x00040000>; clocks = <&tegra_car TEGRA210_CLK_DSIB>, @@ -284,7 +286,7 @@ status = "disabled"; }; - sor@54540000 { + sor0: sor@54540000 { compatible = "nvidia,tegra210-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = ; @@ -304,7 +306,7 @@ status = "disabled"; }; - sor@54580000 { + sor1: sor@54580000 { compatible = "nvidia,tegra210-sor1"; reg = <0x0 0x54580000 0x0 0x00040000>; interrupts = ; -- cgit v1.2.3 From 562da8b494c4e2f72d0789a03e6ccd9dc14d3f25 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:42:45 +0200 Subject: arm64: tegra: Use valid PWM period for VDD_GPU on Tegra210 The PWM on Tegra210 can run at a maximum frequency of 48 MHz and cannot reach the minimum period is 5334 ns. The currently configured period of 4880 ns is not within the valid range, so set it to 8000 ns. This value was taken from the downstream DTS files and seems to work fine. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 6a4b50aaa25d..85ee7e6b71ac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -337,7 +337,7 @@ vdd_gpu: regulator@100 { compatible = "pwm-regulator"; - pwms = <&pwm 1 4880>; + pwms = <&pwm 1 8000>; regulator-name = "VDD_GPU"; regulator-min-microvolt = <710000>; regulator-max-microvolt = <1320000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 553a5585edac..c55716c336c1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -821,7 +821,7 @@ vdd_gpu: regulator@6 { compatible = "pwm-regulator"; - pwms = <&pwm 1 4880>; + pwms = <&pwm 1 8000>; regulator-name = "VDD_GPU"; regulator-min-microvolt = <710000>; -- cgit v1.2.3 From 818ae79a50da560c645e022170bed8401eea452e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 21 Jul 2020 17:10:55 +0200 Subject: arm64: tegra: Properly size register regions for GPU on Tegra194 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather than 256 MiB. Reported-by: Terje Bergström Signed-off-by: Thierry Reding Reviewed-By: Terje Bergström Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 466872a4512f..421b9e0883d9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1412,8 +1412,8 @@ gpu@17000000 { compatible = "nvidia,gv11b"; - reg = <0x17000000 0x10000000>, - <0x18000000 0x10000000>; + reg = <0x17000000 0x1000000>, + <0x18000000 0x1000000>; interrupts = , ; interrupt-names = "stall", "nonstall"; -- cgit v1.2.3 From b6e5aac243b9d178b3c944fa69ffbd248ab150c0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 15 Aug 2020 12:26:27 +0200 Subject: ARM: dts: ux500-golden: Add S6E63M0 DSI display Add the Samsung S6E63M0 video mode DSI display to the Samsung GT-S8190/Golden mobile phone. Signed-off-by: Linus Walleij Cc: Stephan Gerhold Link: https://lore.kernel.org/r/20200815102627.3532646-1-linus.walleij@linaro.org --- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 91 ++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 1e26b711d43d..a1093cb37dc7 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -316,6 +316,28 @@ }; }; }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_default_mode>; + + dsi-controller@a0351000 { + panel@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + vdd3-supply = <&panel_reg_3v0>; + vci-supply = <&panel_reg_1v8>; + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* ESD (electrostatic discharge) detection interrupt */ + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "esd"; + pinctrl-names = "default"; + pinctrl-0 = <&display_default_mode>; + }; + }; + }; }; gpio-keys { @@ -415,6 +437,40 @@ pinctrl-names = "default"; pinctrl-0 = <&wlan_en_default>; }; + + /* MIC5366 GPIO-controlled regulator */ + panel_reg_1v8: regulator-panel-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "panel-fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO219 */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <200>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reg_default_mode>; + }; + + /* MIC5366 GPIO-controlled regulator */ + panel_reg_3v0: regulator-panel-3v0 { + compatible = "regulator-fixed"; + + regulator-name = "panel-fixed-supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <200>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reg_default_mode>; + }; }; &pinctrl { @@ -476,6 +532,41 @@ }; }; + mcde { + dsi_default_mode: dsi_default { + default_mux1 { + /* Mux in VSI0 used for DSI TE */ + function = "lcd"; + groups = + "lcdvsi0_a_1"; /* VSI0 for LCD */ + }; + default_cfg1 { + pins = + "GPIO68_E1"; /* VSI0 */ + ste,config = <&in_nopull>; + }; + }; + }; + + display { + display_default_mode: display_default { + golden_cfg1 { + pins = "GPIO139_C9"; /* MIPI_DSI0_RESET_N */ + ste,config = <&gpio_out_lo>; + }; + golden_cfg2 { + pins = "GPIO82_C1"; /* LDI_ESD_DET */ + ste,config = <&gpio_in_pu>; + }; + }; + panel_reg_default_mode: panel_reg_default { + golden_cfg1 { + pins = "GPIO219_AG10"; /* LCD_PWR_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + proximity { proximity_default: proximity_default { golden_cfg1 { -- cgit v1.2.3 From 2bfdd113d0ee1ea40fbb49f181fea352a7e5e1a7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 19 Aug 2020 18:04:24 -0300 Subject: ARM: dts: imx: Fix the SPI chipselect polarity The conversion of the spi-imx driver to use GPIO descriptors in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors") helped to detect the following SPI chipselect polarity mismatch on an imx6q-sabresd: [ 4.854337] m25p80@0 enforce active low on chipselect handle Prior to the above commit, the chipselect polarity passed via cs-gpios property was ignored and considered active-low. The reason for such mismatch is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam Reviewed-by: Linus Walleij Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi | 4 ++-- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 2 +- arch/arm/boot/dts/imx50-evk.dts | 2 +- arch/arm/boot/dts/imx51-apf51dev.dts | 4 ++-- arch/arm/boot/dts/imx53-m53menlo.dts | 2 +- arch/arm/boot/dts/imx53-smd.dts | 2 +- arch/arm/boot/dts/imx53-tqma53.dtsi | 8 ++++---- arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 3 ++- arch/arm/boot/dts/imx6dl-aristainetos_4.dts | 2 +- arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 4 ++-- arch/arm/boot/dts/imx6dl-prtrvt.dts | 4 ++-- arch/arm/boot/dts/imx6dl-prtvt7.dts | 2 +- arch/arm/boot/dts/imx6q-ba16.dtsi | 2 +- arch/arm/boot/dts/imx6q-bx50v3.dtsi | 2 +- arch/arm/boot/dts/imx6q-cm-fx6.dts | 2 +- arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 2 +- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/imx6q-dms-ba16.dts | 2 +- arch/arm/boot/dts/imx6q-gw5400-a.dts | 2 +- arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi | 6 +++--- arch/arm/boot/dts/imx6q-prti6q.dts | 6 +++--- arch/arm/boot/dts/imx6q-var-dt6customboard.dts | 4 ++-- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 10 +++++----- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-emcon.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 8 ++++---- arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-pico.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-ts4900.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-ts7970.dtsi | 8 ++++---- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 2 +- arch/arm/boot/dts/imx6sl-evk.dts | 2 +- arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 2 +- arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi | 2 +- arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi | 2 +- arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 2 +- arch/arm/boot/dts/imx6ull-colibri.dtsi | 2 +- arch/arm/boot/dts/imx7-colibri.dtsi | 2 +- arch/arm/boot/dts/imx7d-sdb.dts | 2 +- arch/arm/boot/dts/imx7d-zii-rmu2.dts | 2 +- arch/arm/boot/dts/imx7d-zii-rpu2.dts | 2 +- 56 files changed, 82 insertions(+), 81 deletions(-) diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi index 52c95248e25d..303f920201c5 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi @@ -18,8 +18,8 @@ }; &cspi1 { - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, - <&gpio4 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index bf883e45576a..344e77790152 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -65,7 +65,7 @@ &cspi1 { pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts index a25da415cb02..878e89c20190 100644 --- a/arch/arm/boot/dts/imx50-evk.dts +++ b/arch/arm/boot/dts/imx50-evk.dts @@ -20,7 +20,7 @@ &cspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cspi>; - cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>; status = "okay"; flash: m25p32@1 { diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index 563c1aae8c0c..c66f274ba4e9 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@ -74,8 +74,8 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, + <&gpio4 25 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts index 719ed5ca454a..f98691ae4415 100644 --- a/arch/arm/boot/dts/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -104,7 +104,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>; status = "okay"; spidev@0 { diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index ec9fb8940ffa..9be44e807188 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -58,7 +58,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; status = "okay"; zigbee: mc1323@0 { diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index 9a6cb138adf3..7e7f9f3b3906 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi @@ -50,8 +50,8 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, - <&gpio3 24 0>, <&gpio3 25 0>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, + <&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -251,8 +251,8 @@ &cspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cspi>; - cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, - <&gpio1 21 0>; + cs-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>, <&gpio1 19 GPIO_ACTIVE_LOW>, + <&gpio1 21 GPIO_ACTIVE_LOW>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi index 289feab42b88..24859d0c09c1 100644 --- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi +++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi @@ -119,7 +119,8 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, + <&gpio2 16 GPIO_ACTIVE_LOW>, <&gpio2 17 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 809ca5611072..5c7e85300695 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -61,7 +61,7 @@ }; &ecspi2 { - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts index 9eb2b73951b2..b4a9523e325b 100644 --- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts @@ -67,7 +67,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { @@ -80,7 +80,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; status = "okay"; tpm@0 { diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts index fa882458957b..5ac84445e9cc 100644 --- a/arch/arm/boot/dts/imx6dl-prtrvt.dts +++ b/arch/arm/boot/dts/imx6dl-prtrvt.dts @@ -37,7 +37,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -52,7 +52,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 306b4f7bf762..ae6da241f13e 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -219,7 +219,7 @@ }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index fc81f2f4b62d..e4578ed3371e 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -134,7 +134,7 @@ }; &ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 1fb67cd2b2a1..02812e6cb302 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -155,7 +155,7 @@ }; &ecspi5 { - cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index cab9e92531c7..bfb530f29d9d 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -255,7 +255,7 @@ }; &ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index 87f0aa897086..236fc205c389 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -59,7 +59,7 @@ }; &ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio4 11 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index f9df207b2778..fa2307d8ce86 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -99,7 +99,7 @@ &ecspi5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi5>; - cs-gpios = <&gpio1 12 0>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; flash: m25p80@0 { diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts index 57761f3172fa..48fb47e715f6 100644 --- a/arch/arm/boot/dts/imx6q-dms-ba16.dts +++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts @@ -42,7 +42,7 @@ }; &ecspi5 { - cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index b6e2b580051d..4cde45d5c90c 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -132,7 +132,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi index 2618eccfe50d..1a6dcf77fb13 100644 --- a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi @@ -15,9 +15,9 @@ /* Quad/Dual SoMs have 3 chip-select signals */ &ecspi4 { fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, - <&gpio3 29 GPIO_ACTIVE_HIGH>, - <&gpio3 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, + <&gpio3 29 GPIO_ACTIVE_LOW>, + <&gpio3 25 GPIO_ACTIVE_LOW>; }; &pinctrl_ecspi4 { diff --git a/arch/arm/boot/dts/imx6q-prti6q.dts b/arch/arm/boot/dts/imx6q-prti6q.dts index de6cbaab8b49..d112b50f8c5d 100644 --- a/arch/arm/boot/dts/imx6q-prti6q.dts +++ b/arch/arm/boot/dts/imx6q-prti6q.dts @@ -158,7 +158,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -171,7 +171,7 @@ }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio4 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; status = "okay"; @@ -195,7 +195,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts index a57c2e3a8435..63550351340d 100644 --- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts @@ -144,8 +144,8 @@ }; &ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>, - <&gpio4 10 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, + <&gpio4 10 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index dbdd7db60325..30fa349f9d05 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -127,7 +127,7 @@ /* Apalis SPI1 */ &ecspi1 { - cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "disabled"; @@ -135,7 +135,7 @@ /* Apalis SPI2 */ &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index d954661fa055..e21f6ac864e5 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -91,7 +91,7 @@ }; &ecspi4 { - cs-gpios = <&gpio3 20 0>; + cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index d38630d4b892..ead7ba27e105 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -110,23 +110,23 @@ }; &ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW + &gpio4 10 GPIO_ACTIVE_LOW + &gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; }; &ecspi4 { - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 0930194fd960..4e2a309c93fa 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -94,7 +94,7 @@ /* Colibri SSP */ &ecspi4 { - cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index ebe7a8bddf04..648f5fcb72e6 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -30,7 +30,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 0>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi index 35e230f991f1..7228b894a763 100644 --- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -168,8 +168,8 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, - <&gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 27 GPIO_ACTIVE_LOW>; }; &ecspi4 { diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index a46ea98228c2..f6182a9d201c 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -182,7 +182,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index b5f934b8a239..55f368e192c0 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -212,7 +212,7 @@ }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi index d6b074597518..f68f9dada5b0 100644 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -252,7 +252,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index 11f84ee7b88f..6c943a517ad7 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -134,7 +134,7 @@ &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi index 0a1ffff9eb75..441d8ce97aa4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi @@ -129,7 +129,7 @@ }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi index e4231331f04e..eb1ad28946d3 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi @@ -203,7 +203,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; - cs-gpios = <&gpio2 26 0>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi index 81c7ebb4b3fb..265f5f3dbff6 100644 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -245,16 +245,16 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, - <&gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 27 GPIO_ACTIVE_LOW>; }; /* SPI0 */ &ecspi4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, - <&gpio3 29 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, + <&gpio3 29 GPIO_ACTIVE_LOW>; status = "okay"; /* default boot source: workaround #1 for errata ERR006282 */ diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 185a1a31ca39..a0917823c244 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -316,7 +316,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 4bbe54e1ddb5..92d09a3ebe0e 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -247,7 +247,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index c63e1bc1ad3a..1243677b5f97 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -232,7 +232,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 0>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index bc43c75f1745..e361df26a168 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -71,7 +71,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; - cs-gpios = <&gpio4 24 0>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; som_flash: flash@0 { compatible = "m25p80", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-pico.dtsi b/arch/arm/boot/dts/imx6qdl-pico.dtsi index 39dfd90c2c6b..5de4ccb97916 100644 --- a/arch/arm/boot/dts/imx6qdl-pico.dtsi +++ b/arch/arm/boot/dts/imx6qdl-pico.dtsi @@ -167,7 +167,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 55f736dbee0b..afe477f32984 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -267,7 +267,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 0>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; status = "disabled"; /* pin conflict with WEIM NOR */ diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 95f9ddab5996..fdc3aa9d544d 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -308,7 +308,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 0>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 7dddcab9d53f..f824c9abd11a 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -189,7 +189,7 @@ }; &ecspi1 { - cs-gpios = <&gpio4 9 0>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi index 267c956d8910..f88da757edda 100644 --- a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi +++ b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi @@ -95,7 +95,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -108,7 +108,7 @@ }; &ecspi2 { - cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi index f0be516dc28e..e6aa0c33754d 100644 --- a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi @@ -165,7 +165,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -179,9 +179,9 @@ &ecspi2 { cs-gpios = < - &gpio5 31 GPIO_ACTIVE_HIGH - &gpio7 12 GPIO_ACTIVE_HIGH - &gpio5 18 GPIO_ACTIVE_HIGH + &gpio5 31 GPIO_ACTIVE_LOW + &gpio7 12 GPIO_ACTIVE_LOW + &gpio5 18 GPIO_ACTIVE_LOW >; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 5af9ce977b12..66b15748e287 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -316,7 +316,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index b1b069e723d2..7a3827548cab 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -129,7 +129,7 @@ }; &ecspi1 { - cs-gpios = <&gpio4 11 0>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index d25e27d0315f..5547916870c7 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -93,7 +93,7 @@ &ecspi4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi index a35be2a369b3..770f59b23102 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -84,7 +84,7 @@ }; &ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi index 61ba21a605a8..2a449a3c1ae2 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi @@ -14,7 +14,7 @@ }; &ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 8d5f8dc6ad58..f1513e676c2f 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -106,7 +106,7 @@ &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 6cf95939121d..4436556624d6 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -68,7 +68,7 @@ /* Colibri SPI */ &ecspi1 { - cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; }; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index e18e89dec879..62b771c1d5a9 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -60,7 +60,7 @@ &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; - cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; }; &fec1 { diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index b50b19f2d0f1..ac0751bc1177 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -187,7 +187,7 @@ &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; tsc2046@0 { diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts index e5e20b07f184..331b6d259bba 100644 --- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rmu2.dts @@ -39,7 +39,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts index cbf0dbb4c198..893bd30aa2a3 100644 --- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -193,7 +193,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { -- cgit v1.2.3 From fe92538086a86d91c7ce91ff0994de9db321ed29 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 10:49:20 +0200 Subject: ARM: dts: imx6q-kontron-samx6i: Remove old fsl,spi-num-chipselects The property "fsl,spi-num-chipselects" is gone since commit 790739c4417c ("dt-bindings: spi: Convert imx cspi to json-schema"). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi index 1a6dcf77fb13..4d6a0c3e8455 100644 --- a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi @@ -14,7 +14,6 @@ /* Quad/Dual SoMs have 3 chip-select signals */ &ecspi4 { - fsl,spi-num-chipselects = <3>; cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 29 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From c883db9a9306dea5d907287b74b926258ea7422d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 19:20:15 +0200 Subject: dt-bindings: arm: fsl: Add Beacon i.MX8M Mini Development Kit binding Document the binding for Beacon EmbeddedWorks i.MX8M Mini Development Kit board. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index ac6327cf53fd..7ab9d34159f1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -345,6 +345,7 @@ properties: - description: i.MX8MM based Boards items: - enum: + - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - fsl,imx8mm-evk # i.MX8MM EVK Board - const: fsl,imx8mm -- cgit v1.2.3 From 7f6d6e484b9341fd13ec8da42982ca8d2ca54cde Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 29 Aug 2020 00:30:34 +0200 Subject: ARM: dts: ux500-skomer: Add KTD253 backlight This enables the KTD253 backlight found on the Samsung GT-S7710 "Skomer". Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20200828223034.40983-1-linus.walleij@linaro.org --- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index d6f6ac04a48a..27722c42b61c 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -108,15 +108,12 @@ }; }; - /* - * FIXME: this is not quite GPIO backlight. This is a - * KTD253 one-wire GPIO-controlled backlight. It can - * work as a GPIO backlight. - */ - gpio_bl: backlight { - compatible = "gpio-backlight"; + ktd253: backlight { + compatible = "kinetic,ktd253"; /* GPIO 69 */ - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; pinctrl-names = "default"; pinctrl-0 = <&gpio_backlight_default_mode>; }; @@ -409,7 +406,7 @@ reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&display_default_mode>; - backlight = <&gpio_bl>; + backlight = <&ktd253>; }; }; }; -- cgit v1.2.3 From bcf7206fe9c35e048e1dc90cf62216b0f5eaf091 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 14 Aug 2020 17:27:19 +0800 Subject: arm64: dts: imx8mp: Update pinfunc header file Update some pins' name and adjust pin options to i.MX8MP pinfunc header file according to latest reference manual. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 360 ++++++++----------------- 1 file changed, 114 insertions(+), 246 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h index 319ab34cab3e..0fef066471ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h @@ -11,384 +11,318 @@ * */ #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__SJC_FAIL 0x014 0x274 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__SJC_ACTIVE 0x018 0x278 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 #define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 #define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK 0x020 0x280 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__SJC_DONE 0x020 0x280 0x000 0x7 0x0 #define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 #define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV 0x024 0x284 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__USDHC1_TEST_TRIG 0x024 0x284 0x000 0x7 0x0 #define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY 0x028 0x288 0x554 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT 0x028 0x288 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__USDHC2_TEST_TRIG 0x028 0x288 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY 0x028 0x288 0x554 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 #define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__ECSPI1_TEST_TRIG 0x02C 0x28C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 #define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 #define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__ECSPI2_TEST_TRIG 0x030 0x290 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 #define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 #define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT 0x034 0x294 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__FLEXSPI_TEST_TRIG 0x034 0x294 0x000 0x7 0x0 #define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 #define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP 0x038 0x298 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__RAWNAND_TEST_TRIG 0x038 0x298 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__HSIOMIX_usb1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__OCOTP_FUSE_LATCHED 0x03C 0x29C 0x000 0x7 0x0 #define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__HSIOMIX_usb2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 #define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 -#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0 0x040 0x2A0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__CAAM_RNG_OSC_OBS 0x040 0x2A0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 #define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1 0x044 0x2A4 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__CSU_CSU_ALARM_AUT00 0x044 0x2A4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__HSIOMIX_usb1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2 0x048 0x2A8 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__CSU_CSU_ALARM_AUT01 0x048 0x2A8 0x000 0x7 0x0 #define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 #define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__CSU_CSU_ALARM_AUT02 0x04C 0x2AC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 #define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__HSIOMIX_usb2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 #define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x050 0x2B0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__CSU_CSU_INT_DEB 0x050 0x2B0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0 #define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 #define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 -#define MX8MP_IOMUXC_ENET_MDC__SIM_M_HADDR15 0x054 0x2B4 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 #define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03 0x058 0x2B8 0x4CC 0x3 0x0 #define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__SIM_M_HADDR16 0x058 0x2B8 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02 0x05C 0x2BC 0x4C8 0x3 0x0 #define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TD3__SIM_M_HADDR17 0x05C 0x2BC 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 #define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01 0x060 0x2C0 0x4C4 0x3 0x0 #define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TD2__SIM_M_HADDR18 0x060 0x2C0 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00 0x064 0x2C4 0x4C0 0x3 0x0 #define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 -#define MX8MP_IOMUXC_ENET_TD1__SIM_M_HADDR19 0x064 0x2C4 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CLK 0x068 0x2C8 0x000 0x3 0x0 #define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 -#define MX8MP_IOMUXC_ENET_TD0__SIM_M_HADDR20 0x068 0x2C8 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT 0x06C 0x2CC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT 0x06C 0x2CC 0x000 0x3 0x0 #define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__SIM_M_HADDR21 0x06C 0x2CC 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 #define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 #define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22 0x070 0x2D0 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 #define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23 0x074 0x2D4 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 #define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24 0x078 0x2D8 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 #define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25 0x07C 0x2DC 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 +#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 #define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26 0x080 0x2E0 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_CLK 0x084 0x2E4 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CLK 0x084 0x2E4 0x000 0x3 0x0 #define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD2__SIM_M_HADDR27 0x084 0x2E4 0x000 0x7 0x0 #define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 #define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF_IN 0x088 0x2E8 0x544 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1_IN 0x088 0x2E8 0x544 0x3 0x0 #define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 #define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD3__SIM_M_HADDR28 0x088 0x2E8 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 #define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 #define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 #define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_CLK__SIM_M_HADDR29 0x08C 0x2EC 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 #define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 #define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 #define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_CMD__SIM_M_HADDR30 0x090 0x2F0 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 #define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__SIM_M_HADDR31 0x094 0x2F4 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 #define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 #define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 #define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__SIM_M_HBURST00 0x098 0x2F8 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 #define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 #define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__SIM_M_HBURST01 0x09C 0x2FC 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 #define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 #define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 #define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__SIM_M_HBURST02 0x0A0 0x300 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 #define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 #define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__SIM_M_HRESP 0x0A4 0x304 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 #define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 #define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 #define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__TPSMP_HDATA05 0x0A8 0x308 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 #define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 #define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__TPSMP_HDATA06 0x0AC 0x30C 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 #define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 #define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 #define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__TPSMP_HDATA07 0x0B0 0x310 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 #define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__ECSPI3_TEST_TRIG 0x0B4 0x314 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 #define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 #define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__USDHC3_TEST_TRIG 0x0B8 0x318 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0BC 0x31C 0x000 0x6 0x0 #define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 #define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 #define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 #define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0C0 0x320 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_CLK__OBSERVE_MUX_OUT00 0x0C0 0x320 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 #define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 #define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 -#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_CLK 0x0C4 0x324 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK 0x0C4 0x324 0x000 0x4 0x0 #define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0C4 0x324 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_CMD__OBSERVE_MUX_OUT01 0x0C4 0x324 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 +#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 #define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x0C8 0x328 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02 0x0C8 0x328 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 #define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 #define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 -#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x1 +#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x2 #define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0CC 0x32C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_DATA1__OBSERVE_MUX_OUT03 0x0CC 0x32C 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF_OUT 0x0D0 0x330 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x1 +#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF1_OUT 0x0D0 0x330 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x2 #define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0D0 0x330 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__OBSERVE_MUX_OUT04 0x0D0 0x330 0x000 0x7 0x0 #define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN 0x0D4 0x334 0x544 0x3 0x1 -#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 +#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1 +#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 #define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 #define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 #define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 #define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_WP__SIM_M_HMASTLOCK 0x0DC 0x33C 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_ALE__RAWNAND_ALE 0x0E0 0x340 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x0E0 0x340 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 -#define MX8MP_IOMUXC_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 +#define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 #define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 #define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_ALE__SIM_M_HPROT00 0x0E0 0x340 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 +#define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 #define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__SIM_M_HPROT01 0x0E4 0x344 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 #define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 #define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__SIM_M_HPROT02 0x0E8 0x348 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 #define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 #define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__SIM_M_HPROT03 0x0EC 0x34C 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 #define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 #define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__SIM_M_HADDR00 0x0F0 0x350 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_CLE__RAWNAND_CLE 0x0F4 0x354 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x0F4 0x354 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 #define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 #define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CLE__SIM_M_HADDR01 0x0F4 0x354 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__RAWNAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 #define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 #define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__SIM_M_HADDR02 0x0F8 0x358 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__RAWNAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 #define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 #define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__SIM_M_HADDR03 0x0FC 0x35C 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__RAWNAND_DATA02 0x100 0x360 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x100 0x360 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 #define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 @@ -396,82 +330,71 @@ #define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 #define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__SIM_M_HADDR04 0x100 0x360 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__RAWNAND_DATA03 0x104 0x364 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x104 0x364 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 #define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 #define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 #define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__SIM_M_HADDR05 0x104 0x364 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__RAWNAND_DATA04 0x108 0x368 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x108 0x368 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 #define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__SIM_M_HADDR06 0x108 0x368 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__RAWNAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__SIM_M_HADDR07 0x10C 0x36C 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__RAWNAND_DATA06 0x110 0x370 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x110 0x370 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__SIM_M_HADDR08 0x110 0x370 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__RAWNAND_DATA07 0x114 0x374 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x114 0x374 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__SIM_M_HADDR09 0x114 0x374 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_DQS__RAWNAND_DQS 0x118 0x378 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DQS__NAND_DQS 0x118 0x378 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 #define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 #define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DQS__SIM_M_HADDR10 0x118 0x378 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__RAWNAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 #define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 #define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 #define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 #define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__SIM_M_HADDR11 0x11C 0x37C 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__RAWNAND_READY_B 0x120 0x380 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x120 0x380 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 #define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 #define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__SIM_M_HADDR12 0x120 0x380 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_WE_B__RAWNAND_WE_B 0x124 0x384 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x124 0x384 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 #define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 #define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_WE_B__SIM_M_HADDR13 0x124 0x384 0x000 0x7 0x0 -#define MX8MP_IOMUXC_NAND_WP_B__RAWNAND_WP_B 0x128 0x388 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x128 0x388 0x000 0x0 0x0 #define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 #define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 #define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 #define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_WP_B__SIM_M_HADDR14 0x128 0x388 0x000 0x7 0x0 #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 @@ -481,33 +404,33 @@ #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 #define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK 0x130 0x390 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0x130 0x390 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 #define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 #define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 #define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 #define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 #define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 @@ -517,33 +440,27 @@ #define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 #define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x148 0x3A8 0x508 0x1 0x1 #define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK 0x14C 0x3AC 0x4F4 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_CLK 0x14C 0x3AC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0x14C 0x3AC 0x000 0x3 0x0 #define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x150 0x3B0 0x4F8 0x1 0x1 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 #define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x154 0x3B4 0x4FC 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 #define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x158 0x3B8 0x500 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 #define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x15C 0x3BC 0x504 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 #define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 #define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 @@ -569,27 +486,21 @@ #define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 -#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC 0x170 0x3D0 0x510 0x1 0x1 #define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 #define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 -#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK 0x174 0x3D4 0x50C 0x1 0x1 #define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 0x178 0x3D8 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 0x17C 0x3DC 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 0x180 0x3E0 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 0x184 0x3E4 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 @@ -609,11 +520,10 @@ #define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_CLK 0x194 0x3F4 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_CLK 0x194 0x3F4 0x000 0x3 0x0 #define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI5_MCLK 0x198 0x3F8 0x4F0 0x1 0x1 #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 #define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 #define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 @@ -624,16 +534,14 @@ #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 #define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00 0x19C 0x3FC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 #define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01 0x1A0 0x400 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 @@ -641,8 +549,7 @@ #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02 0x1A4 0x404 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 @@ -650,22 +557,18 @@ #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 #define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 -#define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE 0x1A8 0x408 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 #define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 -#define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT 0x1AC 0x40C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 #define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 0x1B0 0x410 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__TPSMP_CLK 0x1B0 0x410 0x000 0x7 0x0 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 @@ -673,15 +576,13 @@ #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 -#define MX8MP_IOMUXC_SAI2_MCLK__TPSMP_HDATA_DIR 0x1B4 0x414 0x000 0x7 0x0 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN 0x1B8 0x418 0x544 0x4 0x2 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF1_IN 0x1B8 0x418 0x544 0x4 0x2 #define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 -#define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00 0x1B8 0x418 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 @@ -689,16 +590,14 @@ #define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 #define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_CLK 0x1BC 0x41C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__TPSMP_HTRANS01 0x1BC 0x41C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x1BC 0x41C 0x000 0x6 0x0 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 -#define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00 0x1C0 0x420 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 @@ -706,8 +605,7 @@ #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 -#define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01 0x1C4 0x424 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 @@ -715,30 +613,26 @@ #define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 #define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 -#define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02 0x1C8 0x428 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 #define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 #define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 0x1CC 0x42C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__TPSMP_HDATA03 0x1CC 0x42C 0x000 0x7 0x0 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 #define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_OUT 0x1D0 0x430 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT 0x1D0 0x430 0x000 0x4 0x0 #define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_IN 0x1D0 0x430 0x544 0x6 0x3 -#define MX8MP_IOMUXC_SAI3_MCLK__TPSMP_HDATA04 0x1D0 0x430 0x000 0x7 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT 0x1D4 0x434 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_IN 0x1D0 0x430 0x544 0x6 0x3 +#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0x1D4 0x434 0x000 0x0 0x0 #define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 #define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 #define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 #define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 #define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN 0x1D8 0x438 0x544 0x0 0x4 +#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0x1D8 0x438 0x544 0x0 0x4 #define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 #define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 #define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 @@ -746,7 +640,7 @@ #define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 #define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 #define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 @@ -754,125 +648,105 @@ #define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 #define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 #define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_SCLK__TPSMP_HDATA08 0x1E0 0x440 0x000 0x7 0x0 #define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 #define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 #define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 #define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_MOSI__TPSMP_HDATA09 0x1E4 0x444 0x000 0x7 0x0 #define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 #define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 #define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 #define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_MISO__TPSMP_HDATA10 0x1E8 0x448 0x000 0x7 0x0 #define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 #define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 #define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 #define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_SS0__TPSMP_HDATA11 0x1EC 0x44C 0x000 0x7 0x0 #define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 #define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 #define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 #define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_SCLK__TPSMP_HDATA12 0x1F0 0x450 0x000 0x7 0x0 #define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 #define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 #define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 #define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_MOSI__TPSMP_HDATA13 0x1F4 0x454 0x000 0x7 0x0 #define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_MISO__TPSMP_HDATA14 0x1F8 0x458 0x000 0x7 0x0 #define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 #define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 #define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 0x1F8 0x458 0x000 0x4 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1 0x1F8 0x458 0x000 0x4 0x0 #define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 #define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 -#define MX8MP_IOMUXC_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 #define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_SS0__TPSMP_HDATA15 0x1FC 0x45C 0x000 0x7 0x0 #define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 #define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 #define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 #define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C1_SCL__TPSMP_HDATA16 0x200 0x460 0x000 0x7 0x0 #define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 #define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 #define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 #define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C1_SDA__TPSMP_HDATA17 0x204 0x464 0x000 0x7 0x0 #define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 #define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 #define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 #define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C2_SCL__TPSMP_HDATA18 0x208 0x468 0x000 0x7 0x0 #define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 #define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 #define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 #define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 #define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C2_SDA__TPSMP_HDATA19 0x20C 0x46C 0x000 0x7 0x0 #define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 #define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 #define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 #define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 #define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C3_SCL__TPSMP_HDATA20 0x210 0x470 0x000 0x7 0x0 #define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 #define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 #define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 #define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 #define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C3_SDA__TPSMP_HDATA21 0x214 0x474 0x000 0x7 0x0 #define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 #define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 #define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 #define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__TPSMP_HDATA22 0x218 0x478 0x000 0x7 0x0 #define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 #define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 #define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 #define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C4_SDA__TPSMP_HDATA23 0x21C 0x47C 0x000 0x7 0x0 #define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 #define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 #define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 #define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART1_RXD__TPSMP_HDATA24 0x220 0x480 0x000 0x7 0x0 #define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 #define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 #define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 #define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART1_TXD__TPSMP_HDATA25 0x224 0x484 0x000 0x7 0x0 #define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 #define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 #define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 #define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 #define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART2_RXD__TPSMP_HDATA26 0x228 0x488 0x000 0x7 0x0 #define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 #define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 #define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 #define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 #define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART2_TXD__TPSMP_HDATA27 0x22C 0x48C 0x000 0x7 0x0 #define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 #define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 #define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 @@ -881,7 +755,6 @@ #define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 #define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 #define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART3_RXD__TPSMP_HDATA28 0x230 0x490 0x000 0x7 0x0 #define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 #define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 #define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 @@ -890,16 +763,14 @@ #define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 #define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 #define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART3_TXD__TPSMP_HDATA29 0x234 0x494 0x000 0x7 0x0 #define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 #define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 #define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 #define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 -#define MX8MP_IOMUXC_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 +#define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 #define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 #define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 #define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART4_RXD__TPSMP_HDATA30 0x238 0x498 0x000 0x7 0x0 #define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 #define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 #define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 @@ -907,23 +778,20 @@ #define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 #define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 #define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART4_TXD__TPSMP_HDATA31 0x23C 0x49C 0x000 0x7 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x240 0x4A0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x240 0x4A0 0x000 0x0 0x0 #define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 #define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 #define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__AUDIOMIX_test_out00 0x240 0x4A0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x244 0x4A4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x244 0x4A4 0x000 0x0 0x0 #define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 #define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 #define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__AUDIOMIX_test_out01 0x244 0x4A4 0x000 0x6 0x0 -#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x248 0x4A8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x248 0x4A8 0x000 0x0 0x0 #define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 #define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 #define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x24C 0x4AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x24C 0x4AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 #define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 #define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 #define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 -- cgit v1.2.3 From 843b993c2d0b5e9aa22965234b914625ed3d3713 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 19 Aug 2020 19:02:19 -0300 Subject: arm64: dts: imx8m: Fix the SPI chipselect polarity The conversion of the spi-imx driver to use GPIO descriptors in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors") helped to detect the following SPI chipselect polarity mismatch on an imx6q-sabresd for example: [ 4.854337] m25p80@0 enforce active low on chipselect handle Prior to the above commit, the chipselect polarity passed via cs-gpios property was ignored and considered active-low. The reason for such mismatch is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam Reviewed-by: Linus Walleij Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index baa5f997d018..9ac17b284f20 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -70,7 +70,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; eeprom@0 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts index 6b3581366d67..bfad4b885905 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts @@ -15,7 +15,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From fa1652340af8ddb04b6f789f9edf318d7ef5ef75 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 21 Aug 2020 09:59:38 -0300 Subject: arm64: dts: imx8mm-evk: Add flexspi support imx8mm-evk has a quad SPI-NOR flash on the flexspi bus. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 7c652b898114..d85206f9e834 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -12,6 +12,10 @@ model = "FSL i.MX8MM EVK board"; compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + aliases { + spi0 = &flexspi; + }; + chosen { stdout-path = &uart2; }; @@ -135,6 +139,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -423,6 +443,17 @@ >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 -- cgit v1.2.3 From 6a62bc369dcf73444af0c1e1effd36f24da7b843 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 11:05:03 +0200 Subject: arm64: dts: imx8mm-evk: remove orphaned pinctrl-names property The "pinctrl-names" property in iomux node does not make sense on its own (without "pinctrl-X"). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index d85206f9e834..e590a0570dda 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -388,8 +388,6 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl_fec1: fec1grp { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -- cgit v1.2.3 From e9d594e8d49753df6d2db80c3224b8b141e41672 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 11:05:04 +0200 Subject: arm64: dts: imx8mn-evk: remove orphaned pinctrl-names property The "pinctrl-names" property in iomux node does not make sense on its own (without "pinctrl-X"). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 5662ba4358a5..76e0225729b1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -176,8 +176,6 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -- cgit v1.2.3 From 1197989df7209aff7db232085842c814855de138 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 11:05:05 +0200 Subject: arm64: dts: imx8mp-evk: remove orphaned pinctrl-names property The "pinctrl-names" property in iomux node does not make sense on its own (without "pinctrl-X"). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 3da1fff3d6fd..3d535f1b3440 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -124,8 +124,6 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 -- cgit v1.2.3 From 0e825b32c033e1998d0ebaf247f5dab3c340e3bf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 13:15:04 +0200 Subject: arm64: dts: imx8mm-evk: Replace deprecated phy reset properties Use preferred properties of phy node instead of deprecated phy-reset-gpios (and others). This avoids copying deprecated code into future DTSes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index e590a0570dda..01366ac3f26e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -123,8 +123,6 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; - phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - phy-reset-duration = <10>; fsl,magic-packet; status = "okay"; @@ -135,6 +133,8 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; -- cgit v1.2.3 From b73af7fca916e9b5e0d11f01bf49f1807fae91b6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 13:15:05 +0200 Subject: arm64: dts: imx8mq-evk: Replace deprecated phy reset properties Use preferred properties of phy node instead of deprecated phy-reset-gpios (and others). This avoids copying deprecated code into future DTSes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index c9241abf0df3..8aa9cd8e495a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -137,8 +137,6 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; - phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <10>; fsl,magic-packet; status = "okay"; @@ -149,6 +147,8 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; -- cgit v1.2.3 From 348eb3e4782e0dcdfbbb88de398cfe3128e3caa7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 13:15:06 +0200 Subject: arm64: dts: imx8mq-phanbell: Replace deprecated phy reset properties Use preferred properties of phy node instead of deprecated phy-reset-gpios (and others). This avoids copying deprecated code into future DTSes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts index 77ab568fae67..3f541ddf0768 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts @@ -262,9 +262,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <10>; - phy-reset-post-delay = <50>; phy-handle = <ðphy0>; fsl,magic-packet; status = "okay"; @@ -275,6 +272,9 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; }; }; }; -- cgit v1.2.3 From 6ea2d1ef4e1f2d7fd3a4c1cb07f8816206b6691b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 13:15:07 +0200 Subject: arm64: dts: imx8mq-sr-som: Replace deprecated phy reset properties Use preferred properties of phy node instead of deprecated phy-reset-gpios (and others). This avoids copying deprecated code into future DTSes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi index 602c870a7ccb..404c46671b96 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi @@ -20,8 +20,6 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; - phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <2>; fsl,magic-packet; status = "okay"; @@ -32,6 +30,8 @@ ethphy0: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <2000>; }; }; }; -- cgit v1.2.3 From 072edea3cf985b2354c415195e7b9ef930ce68be Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 13:15:08 +0200 Subject: arm64: dts: imx8mq-thor96: Replace deprecated phy reset properties Use preferred properties of phy node instead of deprecated phy-reset-gpios (and others). This avoids copying deprecated code into future DTSes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-thor96.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts b/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts index b4795a032fa2..5d5aa6537225 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts @@ -122,7 +122,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; phy-handle = <ðphy>; fsl,magic-packet; status = "okay"; @@ -134,6 +133,7 @@ ethphy: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; }; }; -- cgit v1.2.3 From a265046dd85c9cb8bc2b1281a9745a4675797ff4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 19:20:17 +0200 Subject: arm64: dts: imx8mm-beacon-som: Align regulator names with schema Device tree schema expects regulator names to be lowercase. This fixes dtbs_check warnings like: pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-6]$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-beacon-som.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 94911b1707ef..f627e82ad929 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -79,7 +79,7 @@ regulators { buck1_reg: BUCK1 { - regulator-name = "BUCK1"; + regulator-name = "buck1"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; @@ -88,7 +88,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "BUCK2"; + regulator-name = "buck2"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; @@ -100,7 +100,7 @@ buck3_reg: BUCK3 { // BUCK5 in datasheet - regulator-name = "BUCK3"; + regulator-name = "buck3"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; regulator-boot-on; @@ -109,7 +109,7 @@ buck4_reg: BUCK4 { // BUCK6 in datasheet - regulator-name = "BUCK4"; + regulator-name = "buck4"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -118,7 +118,7 @@ buck5_reg: BUCK5 { // BUCK7 in datasheet - regulator-name = "BUCK5"; + regulator-name = "buck5"; regulator-min-microvolt = <1605000>; regulator-max-microvolt = <1995000>; regulator-boot-on; @@ -127,7 +127,7 @@ buck6_reg: BUCK6 { // BUCK8 in datasheet - regulator-name = "BUCK6"; + regulator-name = "buck6"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-boot-on; @@ -135,7 +135,7 @@ }; ldo1_reg: LDO1 { - regulator-name = "LDO1"; + regulator-name = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -143,7 +143,7 @@ }; ldo2_reg: LDO2 { - regulator-name = "LDO2"; + regulator-name = "ldo2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; @@ -151,7 +151,7 @@ }; ldo3_reg: LDO3 { - regulator-name = "LDO3"; + regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -159,7 +159,7 @@ }; ldo4_reg: LDO4 { - regulator-name = "LDO4"; + regulator-name = "ldo4"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -167,7 +167,7 @@ }; ldo6_reg: LDO6 { - regulator-name = "LDO6"; + regulator-name = "ldo6"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; -- cgit v1.2.3 From 31c78242b4c6d9a619b4441dfffebeb07dd9ce29 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 19:20:18 +0200 Subject: arm64: dts: imx8mm-beacon-som: Fix atmel,24c64 EEPROM compatible Correct the EEPROM node compatible to match device tree schema (invalid space, unknown ID) to fix dtbs_check warnings: arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dt.yaml: eeprom@50: compatible: ['microchip, at24c64d', 'atmel,24c64'] is not valid under any of the given schemas arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dt.yaml: eeprom@50: compatible:0: 'microchip, at24c64d' does not match '^[a-zA-Z][a-zA-Z0-9,+\\-._]+$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index f627e82ad929..620a124dfb5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -184,7 +184,7 @@ status = "okay"; eeprom@50 { - compatible = "microchip, at24c64d", "atmel,24c64"; + compatible = "microchip,24c64", "atmel,24c64"; pagesize = <32>; read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x50>; -- cgit v1.2.3 From 674b05798f407f5ad6a12a5858a7b135d9e7c748 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Aug 2020 19:20:19 +0200 Subject: arm64: dts: imx8mm-evk: Align regulator names with schema Device tree schema expects regulator names to be lowercase. This fixes dtbs_check warnings like: pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-6]$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 01366ac3f26e..38134d201eef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -171,7 +171,7 @@ regulators { buck1_reg: BUCK1 { - regulator-name = "BUCK1"; + regulator-name = "buck1"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; @@ -180,7 +180,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "BUCK2"; + regulator-name = "buck2"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; @@ -192,7 +192,7 @@ buck3_reg: BUCK3 { // BUCK5 in datasheet - regulator-name = "BUCK3"; + regulator-name = "buck3"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; regulator-boot-on; @@ -201,7 +201,7 @@ buck4_reg: BUCK4 { // BUCK6 in datasheet - regulator-name = "BUCK4"; + regulator-name = "buck4"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -210,7 +210,7 @@ buck5_reg: BUCK5 { // BUCK7 in datasheet - regulator-name = "BUCK5"; + regulator-name = "buck5"; regulator-min-microvolt = <1605000>; regulator-max-microvolt = <1995000>; regulator-boot-on; @@ -219,7 +219,7 @@ buck6_reg: BUCK6 { // BUCK8 in datasheet - regulator-name = "BUCK6"; + regulator-name = "buck6"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-boot-on; @@ -227,7 +227,7 @@ }; ldo1_reg: LDO1 { - regulator-name = "LDO1"; + regulator-name = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -235,7 +235,7 @@ }; ldo2_reg: LDO2 { - regulator-name = "LDO2"; + regulator-name = "ldo2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; @@ -243,7 +243,7 @@ }; ldo3_reg: LDO3 { - regulator-name = "LDO3"; + regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -251,7 +251,7 @@ }; ldo4_reg: LDO4 { - regulator-name = "LDO4"; + regulator-name = "ldo4"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -259,7 +259,7 @@ }; ldo6_reg: LDO6 { - regulator-name = "LDO6"; + regulator-name = "ldo6"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; -- cgit v1.2.3 From aa551bd7a04159cf2ca8806abe5da8012b59d058 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Aug 2020 13:12:09 +0200 Subject: arm64: dts: qcom: msm8992: Fix UART interrupt property "interrupt" is not a valid property. Fixes: 7f8bcc0c4cfe ("arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200829111209.32685-1-krzk@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 188fff2095f1..8626b3a50eda 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -335,7 +335,7 @@ blsp2_uart2: serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; - interrupt = ; + interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; -- cgit v1.2.3 From bca4339bda0989e49189c164795b120eb261970c Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 28 Aug 2020 13:13:47 +0530 Subject: arm64: dts: qcom: sdm845-db845c: Fix hdmi nodes As per binding documentation, we should have dsi as node 0 and hdmi audio as node 1, so fix it Reported-by: Dmitry Baryshkov Fixes: aef9a119dfb9 ("arm64: dts: qcom: sdm845-db845c: Add hdmi bridge nodes") Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20200828074347.3788518-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index a2a98680ccf5..99d33955270e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -451,16 +451,16 @@ port@0 { reg = <0>; - lt9611_out: endpoint { - remote-endpoint = <&hdmi_con>; + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; }; }; - port@1 { - reg = <1>; + port@2 { + reg = <2>; - lt9611_a: endpoint { - remote-endpoint = <&dsi0_out>; + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; }; }; }; -- cgit v1.2.3 From 681a607ad21a4db5877e6287f666ba3622ca84cf Mon Sep 17 00:00:00 2001 From: Tanmay Shah Date: Mon, 17 Aug 2020 20:36:57 -0700 Subject: arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node This node defines alternate DP HPD functionality of GPIO. Reviewed-by: Stephen Boyd Signed-off-by: Tanmay Shah Link: https://lore.kernel.org/r/20200818033657.16074-1-tanmay@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d46b3833e52f..b0dd8596e660 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1447,6 +1447,19 @@ gpio-ranges = <&tlmm 0 0 120>; wakeup-parent = <&pdc>; + dp_hot_plug_det: dp-hot-plug-det { + pinmux { + pins = "gpio117"; + function = "dp_hot"; + }; + + pinconf { + pins = "gpio117"; + bias-disable; + input-enable; + }; + }; + qspi_clk: qspi-clk { pinmux { pins = "gpio63"; -- cgit v1.2.3 From 79493db5bb573017767b4f48b0fc69bfd01b82d2 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 18 Aug 2020 12:04:43 -0400 Subject: arm64: dts: qcom: sm8150: fix up primary USB nodes The compatible for hsphy has out of place indentation, and the assigned clock rate for GCC_USB30_PRIM_MASTER_CLK is incorrect, the clock doesn't support a rate of 150000000. Use a rate of 200000000 to match downstream. Fixes: b33d2868e8d3 ("arm64: dts: qcom: sm8150: Add USB and PHY device nodes") Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200818160445.14008-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index b86a7ead3006..ab8680c6672e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -767,7 +767,7 @@ usb_1_hsphy: phy@88e2000 { compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; + "qcom,usb-snps-hs-7nm-phy"; reg = <0 0x088e2000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -833,7 +833,7 @@ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; + assigned-clock-rates = <19200000>, <200000000>; interrupts = , , -- cgit v1.2.3 From f126991607edd11d0b0e9f9007f556146083921a Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 18 Aug 2020 12:04:44 -0400 Subject: arm64: dts: qcom: use sm8150 gpucc dt-bindings Constants were used to allow merging separately from the dt-bindings, switch to symbolic names now that dt-bindings have landed. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200818160445.14008-2-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index ab8680c6672e..62d49e81483e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include / { @@ -621,15 +622,15 @@ ; interrupt-names = "hfi", "gmu"; - clocks = <&gpucc 0>, - <&gpucc 3>, - <&gpucc 6>, + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - power-domains = <&gpucc 0>, - <&gpucc 1>; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0x400>; @@ -674,12 +675,12 @@ , , ; - clocks = <&gpucc 0>, + clocks = <&gpucc GPU_CC_AHB_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; clock-names = "ahb", "bus", "iface"; - power-domains = <&gpucc 0>; + power-domains = <&gpucc GPU_CX_GDSC>; }; tlmm: pinctrl@3100000 { -- cgit v1.2.3 From 0e6aa9db44e7bbba7efeff3b4fc1fa61bab318c2 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 18 Aug 2020 12:04:45 -0400 Subject: arm64: dts: qcom: use sm8250 gpucc dt-bindings Constants were used to allow merging separately from the dt-bindings, switch to symbolic names now that dt-bindings have landed. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200818160445.14008-3-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 377172e8967b..b82d8f40fa42 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1127,15 +1128,15 @@ ; interrupt-names = "hfi", "gmu"; - clocks = <&gpucc 0>, - <&gpucc 3>, - <&gpucc 6>, + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - power-domains = <&gpucc 0>, - <&gpucc 1>; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0x400>; @@ -1181,12 +1182,12 @@ , , ; - clocks = <&gpucc 0>, + clocks = <&gpucc GPU_CC_AHB_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; clock-names = "ahb", "bus", "iface"; - power-domains = <&gpucc 0>; + power-domains = <&gpucc GPU_CX_GDSC>; }; slpi: remoteproc@5c00000 { -- cgit v1.2.3 From efe788361f72914017515223414d3f20abe4b403 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 18 Aug 2020 20:25:14 +0530 Subject: arm64: dts: qcom: sc7180: Fix the LLCC base register size There is one LLCC logical bank(LLCC0) on SC7180 SoC and the size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct the size and fix copy paste mistake carried over from SDM845. Reviewed-by: Douglas Anderson Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order") Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node") Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index b0dd8596e660..d3e6008cf3fb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2631,7 +2631,7 @@ system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; + reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = ; }; -- cgit v1.2.3 From bd77d0ad7a698f5e04edf02328d11e808a71d87c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 19 Aug 2020 00:15:05 +0530 Subject: arm64: dts: rockchip: Fix power routing to support POE on rk3399-roc-pc When POE used, the current power routing is failing to power-up the PMIC regulators which cause Linux boot hangs. This patch is trying to update the power routing in order to support Type C0 and POE powering methods. As per the schematics, sys_12v is a common output power regulator when type c and POE power being used. sys_12v is supplied by dc_12v which is supplied from MP8859 in type c0 power routing and sys_12v is supplied by MP8009 PoE PD in POE power supply routing. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh Link: https://lore.kernel.org/r/20200818184505.30064-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts | 18 ++++++++++++++++-- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 12 ++++++++++-- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts index 2acb3d500fb9..754627d97144 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts @@ -11,6 +11,16 @@ model = "Firefly ROC-RK3399-PC Mezzanine Board"; compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; + /* MP8009 PoE PD */ + poe_12v: poe-12v { + compatible = "regulator-fixed"; + regulator-name = "poe_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + vcc3v3_ngff: vcc3v3-ngff { compatible = "regulator-fixed"; regulator-name = "vcc3v3_ngff"; @@ -22,7 +32,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; + vin-supply = <&sys_12v>; }; vcc3v3_pcie: vcc3v3-pcie { @@ -34,10 +44,14 @@ pinctrl-0 = <&vcc3v3_pcie_en>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; + vin-supply = <&sys_12v>; }; }; +&sys_12v { + vin-supply = <&poe_12v>; +}; + &pcie_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index b85ec31cd283..e7a459fa4322 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -110,6 +110,14 @@ regulator-max-microvolt = <5000000>; }; + sys_12v: sys-12v { + compatible = "regulator-fixed"; + regulator-name = "sys_12v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; + /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -141,7 +149,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; + vin-supply = <&sys_12v>; }; vcca_0v9: vcca-0v9 { @@ -186,7 +194,7 @@ regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; + vin-supply = <&sys_12v>; }; vdd_log: vdd-log { -- cgit v1.2.3 From bc1f9bff0629a15e3de1ef106ac03cba930227dd Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 18 Aug 2020 16:37:27 +0200 Subject: arm64: dts: rockchip: change spdif fallback compatible on rk3308 A test with the command below shows that the compatible string "rockchip,rk3308-spdif", "rockchip,rk3328-spdif" is already in use, but is not added to a document. The current fallback string "rockchip,rk3328-spdif" points to a data set enum RK_SPDIF_RK3366 in rockchip_spdif.c that is not used both in the mainline as in the manufacturer kernel. (Of the enum only RK_SPDIF_RK3288 is used.) So if the properties don't change we might as well use the first SoC in line as fallback string and add the description for rk3308 as: "rockchip,rk3308-spdif", "rockchip,rk3066-spdif" make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/rockchip-spdif.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200818143727.5882-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index e8b754d415d8..2560b98771ca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -574,7 +574,7 @@ }; spdif_tx: spdif-tx@ff3a0000 { - compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif"; + compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; reg = <0x0 0xff3a0000 0x0 0x1000>; interrupts = ; clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; -- cgit v1.2.3 From 75a0a65a301f557bf0306d7983f8cf31ac91de56 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 7 Aug 2020 15:18:23 +0530 Subject: dt-bindings: arm: rockchip: Update ROCKPi 4 binding ROCKPi 4 has 3 variants of hardware platforms called ROCKPi 4A, 4B, and 4C. - ROCKPi 4A has no Wif/BT. - ROCKPi 4B has AP6256 Wifi/BT, PoE. - ROCKPi 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled GPIO pin change compared to 4B, 4C So, update the existing ROCKPi 4 binding to support ROCKPi 4A/B/C hardware platforms. Signed-off-by: Jagan Teki Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200807094826.12019-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index db2e35796795..7025d00c06cc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -430,8 +430,12 @@ properties: - const: radxa,rock - const: rockchip,rk3188 - - description: Radxa ROCK Pi 4 + - description: Radxa ROCK Pi 4A/B/C items: + - enum: + - radxa,rockpi4a + - radxa,rockpi4b + - radxa,rockpi4c - const: radxa,rockpi4 - const: rockchip,rk3399 -- cgit v1.2.3 From b5edb04673700125bfd1d13e6c14747b1ecba522 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 7 Aug 2020 15:18:24 +0530 Subject: arm64: dts: rockchip: Mark rock-pi-4 as rock-pi-4a dts ROCKPi 4 has 3 variants of hardware platforms called RockPI 4A, 4B, and 4C. - ROCKPi 4A has no Wif/BT. - ROCKPi 4B has AP6256 Wifi/BT, PoE. - ROCKPi 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled GPIO pin change compared to 4B, 4C So move common nodes, properties into dtsi file and include on respective variant dts files. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200807094826.12019-2-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 +- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 735 --------------------- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 732 ++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts | 13 + 4 files changed, 746 insertions(+), 736 deletions(-) delete mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index b87b1f773083..42f9e1861461 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -33,7 +33,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts deleted file mode 100644 index 60f98a3e19d8..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts +++ /dev/null @@ -1,735 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar - * Copyright (c) 2019 Pragnesh Patel - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Radxa ROCK Pi 4"; - compatible = "radxa,rockpi4", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc12v_dcin: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_lan: vcc3v3-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_lan"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_codec: LDO_REG1 { - regulator-name = "vcc1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc0v9_hdmi: LDO_REG7 { - regulator-name = "vcc0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_cam: SWITCH_REG1 { - regulator-name = "vcc_cam"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_mipi: SWITCH_REG2 { - regulator-name = "vcc_mipi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc_3v0>; - audio-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pmu_io_domains { - status = "okay"; - - pmu1830-supply = <&vcc_3v0>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; - num-lanes = <4>; - pinctrl-0 = <&pcie_clkreqnb_cpm>; - pinctrl-names = "default"; - vpcie0v9-supply = <&vcc_0v9>; - vpcie1v8-supply = <&vcc_1v8>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio0 { - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, - <2 RK_PC5 1 &pcfg_pull_up_20ma>, - <2 RK_PC6 1 &pcfg_pull_up_20ma>, - <2 RK_PC7 1 &pcfg_pull_up_20ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0-typec-en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - status = "okay"; - - vref-supply = <&vcc_1v8>; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - status = "okay"; - - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi new file mode 100644 index 000000000000..e163f438f836 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -0,0 +1,732 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Pragnesh Patel + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_lan: vcc3v3-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_codec: LDO_REG1 { + regulator-name = "vcc1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc0v9_hdmi: LDO_REG7 { + regulator-name = "vcc0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_cam: SWITCH_REG1 { + regulator-name = "vcc_cam"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_mipi: SWITCH_REG2 { + regulator-name = "vcc_mipi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc_3v0>; + audio-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + + pmu1830-supply = <&vcc_3v0>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + pinctrl-names = "default"; + vpcie0v9-supply = <&vcc_0v9>; + vpcie1v8-supply = <&vcc_1v8>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio0 { + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0-typec-en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + status = "okay"; + + vref-supply = <&vcc_1v8>; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + status = "okay"; + + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts new file mode 100644 index 000000000000..89f2af5e111d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Pragnesh Patel + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4A"; + compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399"; +}; -- cgit v1.2.3 From c1075b7fcca81f58ebc5d723f07b23f84ae93daa Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 7 Aug 2020 15:18:25 +0530 Subject: arm64: dts: rockchip: Add Radxa ROCK Pi 4B support RockPI 4B has AP6256 Wifi/BT, so enable them in 4B dts instead of enable in common dtsi. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200807094826.12019-3-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 23 ------------ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 42 ++++++++++++++++++++++ 3 files changed, 43 insertions(+), 23 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 42f9e1861461..8832d05c2571 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index e163f438f836..678a336010bf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -584,17 +584,6 @@ pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; }; &sdmmc { @@ -663,18 +652,6 @@ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - }; }; &uart2 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts new file mode 100644 index 000000000000..f0055ce2fda0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Pragnesh Patel + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4B"; + compatible = "radxa,rockpi4b", "radxa,rockpi4", "rockchip,rk3399"; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; -- cgit v1.2.3 From 93e0e8ce5fdf549f1715dad00bfbb21b2f69ba8e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 7 Aug 2020 15:18:26 +0530 Subject: arm64: dts: rockchip: Add Radxa ROCK Pi 4C support Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled GPIO pin change compared to 4B, 4C. So, add or enable difference nodes/properties in 4C dts by including common dtsi. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200807094826.12019-4-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 51 ++++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 8832d05c2571..02cdb3c4a6c1 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts new file mode 100644 index 000000000000..4c7ebb1c5d2d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4C"; + compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399"; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; + +&vcc5v0_host { + gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host_en { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +}; -- cgit v1.2.3 From cb1cc137a2c148cbe60e5065afa1a09e176e0269 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 8 Aug 2020 18:06:16 +0200 Subject: dt-bindings: Add vendor prefix for Shenzhen Zkmagic Technology Co., Ltd. Add vendor prefix for Shenzhen Zkmagic Technology Co., Ltd. Signed-off-by: Johan Jonker Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200808160618.15445-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2baee2c817c1..bfdefbd21985 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1198,6 +1198,8 @@ patternProperties: description: Shenzhen Zidoo Technology Co., Ltd. "^zii,.*": description: Zodiac Inflight Innovations + "^zkmagic,.*": + description: Shenzhen Zkmagic Technology Co., Ltd. "^zte,.*": description: ZTE Corp. "^zyxel,.*": -- cgit v1.2.3 From 0dc8c62c92d4df35a001b613ebe10f95e4ebf776 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 8 Aug 2020 18:06:17 +0200 Subject: dt-bindings: arm: rockchip: add Zkmagic A95X Z2 description Add Zkmagic A95X Z2 description for a board with rk3318 processor. Signed-off-by: Johan Jonker Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200808160618.15445-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 7025d00c06cc..251c3ca22e1b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -559,4 +559,9 @@ properties: items: - const: tronsmart,orion-r68-meta - const: rockchip,rk3368 + + - description: Zkmagic A95X Z2 + items: + - const: zkmagic,a95x-z2 + - const: rockchip,rk3318 ... -- cgit v1.2.3 From 964ed0807b5f7b42b8a6ad48531ae9312e19599d Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 8 Aug 2020 18:06:18 +0200 Subject: arm64: dts: rockchip: add rk3318 A95X Z2 board The rk3318 A95X Z2 boards are sold as TV box. No further documentation is given, but from the dts files extracted it seems that the rk3318 processor is simulair to the rk3328. This dts file contains only the basic nodes that have support in the mainline kernel. Features: CPU: RK3318 Quad-Core Cortex-A53 GPU: Mali-450 RAM: 2/4GB DDR3 ROM: EMMC 16/32/64GB HDMI: HDMI 2.0a for 4k@60Hz Ethernet: 10/100M standard RJ-45 WiFi: 2.4G+5G WIFI, 802.11 b/g/n Bluetooth: 4.0 1 x USB 3.0 1 x USB 2.0 1 x Micro SD card slot 1 x SPDIF 1 x AV 1 x DC IN Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200808160618.15445-4-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 374 ++++++++++++++++++++++++ 2 files changed, 375 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 02cdb3c4a6c1..d53efdf4cb5a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts new file mode 100644 index 000000000000..30c73ef25370 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include "rk3328.dtsi" + +/ { + model = "A95X Z2"; + compatible = "zkmagic,a95x-z2", "rockchip,rk3318"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "recovery"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&cyx_led_pin>; + pinctrl-names = "default"; + + cyx_led: led-0 { + default-state = "on"; + gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_LOW>; + label = "CYX_LED"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + /* Power tree */ + vccio_1v8: vccio-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vccio_3v3: vccio-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&otg_vbus_drv>; + pinctrl-names = "default"; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vccio_3v3>; + }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&analog_sound { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cpu0_opp_table { + opp-1200000000 { + status = "disabled"; + }; + + opp-1296000000 { + status = "disabled"; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gmac2phy { + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + clock_in_out = "output"; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_log>; +}; + +&hdmi { + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&io_domains { + pmuio-supply = <&vccio_3v3>; + vccio1-supply = <&vccio_3v3>; + vccio2-supply = <&vccio_1v8>; + vccio3-supply = <&vccio_3v3>; + vccio4-supply = <&vccio_1v8>; + vccio5-supply = <&vccio_3v3>; + vccio6-supply = <&vccio_3v3>; + status = "okay"; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + cyx_led_pin: cyx-led-pin { + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin_pull_up: pwm0-pin-pull-up { + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>; + }; + }; + + pwm1 { + pwm1_pin_pull_up: pwm1-pin-pull-up { + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc1 { + clk_32k_out: clk-32k-out { + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pin_pull_up>; + pinctrl-names = "active"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pin_pull_up>; + pinctrl-names = "active"; + status = "okay"; +}; + +&saradc { + vref-supply = <&vccio_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <125000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &clk_32k_out>; + pinctrl-names = "default"; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spdif { + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; +}; + +&soc_crit { + temperature = <115000>; /* millicelsius */ +}; + +&target { + temperature = <105000>; /* millicelsius */ +}; + +&threshold { + temperature = <90000>; /* millicelsius */ +}; + +&tsadc { + rockchip,hw-tshut-temp = <120000>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + phy-supply = <&vcc_otg_vbus>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; -- cgit v1.2.3 From 4be8df7b3bcd46a75f7e297ef310234975a437d8 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 13 Aug 2020 20:17:11 +0200 Subject: arm64: dts: rockchip: fix cpu-supply for rk3328-evb The property cpu-supply should be added to each cpu separately, so fix that for rk3328-evb. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200813181711.15906-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts index 1969dab84138..a48767931af6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts @@ -70,6 +70,18 @@ cpu-supply = <&vdd_arm>; }; +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + &emmc { bus-width = <8>; cap-mmc-highspeed; -- cgit v1.2.3 From b282ae0511cdb6f17cb5052de20288245a8ecd00 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 13 Aug 2020 20:02:41 +0200 Subject: ARM: dts: rockchip: update cpu supplies on rk3288 The use of cpu0-supply for cpu0 alone is deprecated, so add cpu-supply to each cpu separately and update all existing rk3288 boards that use this property. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200813180241.14660-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-miqi.dts | 14 +++++++++++++- arch/arm/boot/dts/rk3288-popmetal.dts | 14 +++++++++++++- arch/arm/boot/dts/rk3288-r89.dts | 14 +++++++++++++- arch/arm/boot/dts/rk3288-vyasa.dts | 14 +++++++++++++- 4 files changed, 52 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 213c9eb84f76..8a3992105151 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -81,7 +81,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &emmc { diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 6a51940398b5..160ed8b932fb 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -103,7 +103,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &emmc { diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index a258c7ae5329..e5ba901c7dcb 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -91,7 +91,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &gmac { diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 1a20854a1317..aa50f8ed4ca0 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -125,7 +125,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &emmc { -- cgit v1.2.3 From 9ab4a7312bf31611f3a9c95470f15b3f2bcd83e3 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 13 Aug 2020 19:24:50 +0200 Subject: ARM: dts: rockchip: rk3066a: add label to cpu@1 Add label to cpu@1 for later use. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200813172451.13754-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index b599394d149d..252750c97f97 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -36,7 +36,7 @@ clock-latency = <40000>; clocks = <&cru ARMCLK>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; -- cgit v1.2.3 From 20e464c0f12a9b1930adb0365326037d5b060cee Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 13 Aug 2020 19:24:51 +0200 Subject: ARM: dts: rockchip: update cpu supplies on rk3066a The use of cpu0-supply for cpu0 alone is deprecated, so add cpu-supply to each cpu separately and update all existing rk3066a boards. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200813172451.13754-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 6 +++++- arch/arm/boot/dts/rk3066a-marsboard.dts | 6 +++++- arch/arm/boot/dts/rk3066a-rayeager.dts | 6 +++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 0a56a2f1bc4d..eba7a1344976 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -63,7 +63,11 @@ }; &cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; }; &i2c1 { diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index 7e01f6406a86..6b121658d93c 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -47,7 +47,11 @@ }; &cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; }; &i2c1 { diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index f9db6bb9fa11..309518403d86 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -128,7 +128,11 @@ }; &cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; }; &emac { -- cgit v1.2.3 From 0cf10e6f94335495f90fc62fb75d9569f6a603fb Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 21:08:20 +0200 Subject: ARM: dts: rockchip: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Link: https://lore.kernel.org/r/20200830190820.20583-1-freifunk@adrianschmutzler.de Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-evb.dtsi | 2 +- arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 2 +- arch/arm/boot/dts/rk3288-firefly.dtsi | 2 +- arch/arm/boot/dts/rk3288-miqi.dts | 2 +- arch/arm/boot/dts/rk3288-popmetal.dts | 2 +- arch/arm/boot/dts/rk3288-r89.dts | 2 +- arch/arm/boot/dts/rk3288-rock2-square.dts | 2 +- arch/arm/boot/dts/rk3288-tinker.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 018802df4c0e..c4ca73b40d4a 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -247,7 +247,7 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &gpu { diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index 61435d8ee37b..36efa36b7190 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -61,7 +61,7 @@ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &i2c0 { diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index e5c4fd4ea67e..7fb582302b32 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -191,7 +191,7 @@ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &gpu { diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 8a3992105151..cf54d5ffff2f 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -120,7 +120,7 @@ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 160ed8b932fb..8c7376d64bc4 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -161,7 +161,7 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index e5ba901c7dcb..55467bc30fa6 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -119,7 +119,7 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index 3cca4d0f9b09..c4d1d142d8c6 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -156,7 +156,7 @@ }; &gmac { - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi index 90e9be443fe6..9c1e38c54eae 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi @@ -137,7 +137,7 @@ snps,reset-delays-us = <0 10000 1000000>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &gpu { -- cgit v1.2.3 From 9caff35d7eba8e15c996c694a282fd38b2ea345e Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 22:11:12 +0200 Subject: arm64: dts: rockchip: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Link: https://lore.kernel.org/r/20200830201112.1934-1-freifunk@adrianschmutzler.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi index 1c52f47c43a6..87fabc64cc39 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi @@ -134,7 +134,7 @@ pinctrl-0 = <&rmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index b058ce999e3b..ecce16ecc9c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -183,7 +183,7 @@ snps,reset-delays-us = <0 10000 1000000>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index 236ab0f1b206..2582fa4b90e2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -167,7 +167,7 @@ pinctrl-0 = <&rmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &i2c0 { @@ -198,7 +198,7 @@ }; &io_domains { - status = "ok"; + status = "okay"; audio-supply = <&vcc_io>; gpio30-supply = <&vcc_io>; -- cgit v1.2.3 From 7d076e1fc9a659102e69ae678dc2191c53135c1a Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 24 Aug 2020 15:50:37 +0800 Subject: ARM: dts: imx6sx-sdb: Add headphone detection for sound card Headphone detection is triggered by GPIO, then driver can switch between speaker and headphone. Signed-off-by: Shengjiu Wang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index b8c23eba9dc7..1351d7f70a54 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -153,6 +153,8 @@ sound { compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; model = "wm8962-audio"; ssi-controller = <&ssi2>; audio-codec = <&codec>; @@ -165,6 +167,7 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <6>; + hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; }; panel { @@ -468,6 +471,12 @@ >; }; + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 -- cgit v1.2.3 From b2b8d526d7f5393cd1a76232dd6b04b9fe209291 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 24 Aug 2020 15:50:38 +0800 Subject: ARM: dts: imx6sl-evk: Add headphone detection for sound card Headphone detection is triggered by GPIO, then driver can switch between speaker and headphone. Signed-off-by: Shengjiu Wang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 7a3827548cab..25f6f2fb1555 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -94,6 +94,8 @@ sound { compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; model = "wm8962-audio"; ssi-controller = <&ssi2>; audio-codec = <&codec>; @@ -106,6 +108,7 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; + hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; }; panel { @@ -343,6 +346,12 @@ >; }; + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 -- cgit v1.2.3 From 5f50799dd4d1bd2b1faeb7ab4f235a239cc200a1 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 24 Aug 2020 15:50:39 +0800 Subject: ARM: dts: imx6sll-evk: Add audio sound card node Add audio sound card node, which depends on codec node, SSI node, audmux node. Signed-off-by: Shengjiu Wang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 73 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index c755cbdb7cde..32b3d82fec53 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -132,6 +132,31 @@ }; }; }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + model = "wm8962-audio"; + audio-cpu = <&ssi2>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; }; &cpu0 { @@ -247,6 +272,27 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + }; +}; + &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; @@ -274,6 +320,10 @@ status = "okay"; }; +&ssi2 { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -330,6 +380,22 @@ }; &iomuxc { + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + >; + }; + pinctrl_reg_sd3_vmmc: sd3vmmcgrp { fsl,pins = < MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 @@ -449,6 +515,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 + >; + }; + pinctrl_lcd: lcdgrp { fsl,pins = < MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 -- cgit v1.2.3 From 82455594c001348c3dbb118ecd8fb8cbbc96b826 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 24 Aug 2020 09:29:39 -0300 Subject: ARM: dts: imx6qdl-gw553x: Remove unneeded #address-cells/#size-cells The following dtc warning is seen when building with W=1: arch/arm/boot/dts/imx6qdl-gw553x.dtsi:65.12-110.4: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Remove the unneeded #address-cells/#size-cells properties to fix the issue. Fixes: 64bf0a0af18d ("ARM: dts: imx6qdl-gw: add Gateworks System Controller support") Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi index db30de5d6490..faf9a3ba61b2 100644 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi @@ -64,8 +64,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; user-pb { label = "user_pb"; -- cgit v1.2.3 From 2eedac079ae45bbd377def090dd0b509b5568c32 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 24 Aug 2020 09:15:46 +0200 Subject: arm64: dts: imx8mm-beacon-baseboard: Correct LED default state There is no LED default state "none". leds-gpio driver maps it to "off", so correct them to fix dtbs_check warnings like: arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dt.yaml: leds: led0:default-state:0: 'none' is not one of ['on', 'off', 'keep'] Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 9ac17b284f20..5b5af8b381df 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -10,19 +10,19 @@ led0 { label = "gen_led0"; gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led1 { label = "gen_led1"; gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led2 { label = "gen_led2"; gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led3 { -- cgit v1.2.3 From 663effe570d1a798b7a5ae5cc614de615b55714a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Aug 2020 21:35:31 +0200 Subject: dt-bindings: arm: fsl: Fix Toradex Colibri i.MX 8 binding The Toradex Colibri i.MX 8 Evaluation board has two Toradex compatibles so it needs separate entry. This fixes dtbs_check warning: arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dt.yaml: /: compatible: ['toradex,colibri-imx8x-eval-v3', 'toradex,colibri-imx8x', 'fsl,imx8qxp'] is not valid under any of the given schemas (Possible causes of the failure): arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dt.yaml: /: compatible: ['toradex,colibri-imx8x-eval-v3', 'toradex,colibri-imx8x', 'fsl,imx8qxp'] is too long Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 7ab9d34159f1..9abc0477fb75 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -382,7 +382,13 @@ properties: - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board - fsl,imx8qxp-mek # i.MX8QXP MEK Board - toradex,colibri-imx8x # Colibri iMX8X Module + - const: fsl,imx8qxp + + - description: Toradex Colibri i.MX8 Evaluation Board + items: + - enum: - toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3 + - const: toradex,colibri-imx8x - const: fsl,imx8qxp - description: -- cgit v1.2.3 From 3db8904fa9764041aab7cdef8a935ee857a2bee7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Aug 2020 21:35:32 +0200 Subject: dt-bindings: arm: fsl: Add ZII Ultra boards binding Document the binding for Zodiac Inflight Innovations Ultra Boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 9abc0477fb75..0596f55aeee9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -376,6 +376,14 @@ properties: - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk - const: fsl,imx8mq + - description: Zodiac Inflight Innovations Ultra Boards + items: + - enum: + - zii,imx8mq-ultra-rmb3 + - zii,imx8mq-ultra-zest + - const: zii,imx8mq-ultra + - const: fsl,imx8mq + - description: i.MX8QXP based Boards items: - enum: -- cgit v1.2.3 From 878cc5a2ca17223cb1064cf6f58f35d347e9ec62 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Aug 2020 21:35:35 +0200 Subject: arm64: dts: imx8mq-evk: Add hog suffix to wl-reg-on According to device tree specification, device node names should be somewhat generic and reflecting the function of the device so add the "hog" suffix to wl-reg-on GPIO hog. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 8aa9cd8e495a..a088831d2e24 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -157,7 +157,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi_reset>; - wl-reg-on { + wl-reg-on-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; output-high; -- cgit v1.2.3 From 86d3eedddfd8d1ce96b1437b193ba665b6ce4c50 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Aug 2020 21:35:36 +0200 Subject: arm64: dts: imx8mq-zii-ultra: Add hog suffixes to GPIO hogs According to device tree specification, device node names should be somewhat generic and reflecting the function of the device so add the "hog" suffixes to all GPIO hog nodes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 0d1088dcaa02..fa7a041ffcfd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -229,28 +229,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio3_hog>; - usb-emulation { + usb-emulation-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-low; line-name = "usb-emulation"; }; - usb-mode1 { + usb-mode1-hog { gpio-hog; gpios = <11 GPIO_ACTIVE_HIGH>; output-high; line-name = "usb-mode1"; }; - usb-pwr { + usb-pwr-hog { gpio-hog; gpios = <12 GPIO_ACTIVE_LOW>; output-high; line-name = "usb-pwr-ctrl-en-n"; }; - usb-mode2 { + usb-mode2-hog { gpio-hog; gpios = <13 GPIO_ACTIVE_HIGH>; output-high; -- cgit v1.2.3 From ed23822eb24b6df608aedb007e569c2cc99f5c2c Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 22:03:33 +0200 Subject: arm64: dts: broadcom: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi index a9b92e52d50e..43aa5e9c0020 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -151,7 +151,7 @@ }; &nand { - status = "ok"; + status = "okay"; nandcs@0 { compatible = "brcm,nandcs"; reg = <0>; -- cgit v1.2.3 From 6534dfbbfab3dee8eb903df9b68556405ab3fa36 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 28 Aug 2020 14:05:55 +0100 Subject: arm64: dts: broadcom: Fix SP805 clock-names The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for Broadcom platforms to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Signed-off-by: Andre Przywara Reviewed-by: Ray Jui Acked-by: Florian Fainelli Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 15f7b0ed3836..6a5fc55f0a4e 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -576,7 +576,7 @@ reg = <0x66090000 0x1000>; interrupts = ; clocks = <&iprocslow>, <&iprocslow>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; gpio_g: gpio@660a0000 { diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 0098dfdef96c..b425b12c3ed2 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -438,7 +438,7 @@ reg = <0x000c0000 0x1000>; interrupts = ; clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; timeout-sec = <60>; }; -- cgit v1.2.3 From 334b6b6638a27e6993b1d9c267b453fb2246b77d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 24 Aug 2020 21:18:16 +0200 Subject: dt-bindings: arm: fsl: Add binding for Variscite VAR-SOM-MX8MM module Add a binding for the Variscite VAR-SOM-MX8MM System on Module. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0596f55aeee9..53d639ce5374 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -347,6 +347,7 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - fsl,imx8mm-evk # i.MX8MM EVK Board + - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - const: fsl,imx8mm - description: i.MX8MN based Boards -- cgit v1.2.3 From 97e875b701cf48f4b4398aa58b328f7d892c9b17 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 24 Aug 2020 21:18:17 +0200 Subject: dt-bindings: arm: fsl: Add binding for Variscite Symphony board with VAR-SOM-MX8MM Add a binding for the Variscite Symphony evaluation kit board with VAR-SOM-MX8MM System on Module. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 53d639ce5374..37cef8653541 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -350,6 +350,12 @@ properties: - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - const: fsl,imx8mm + - description: Variscite VAR-SOM-MX8MM based boards + items: + - const: variscite,var-som-mx8mm-symphony + - const: variscite,var-som-mx8mm + - const: fsl,imx8mm + - description: i.MX8MN based Boards items: - enum: -- cgit v1.2.3 From bf6b832f5ebe9097257e55aff3273d06a559861d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 24 Aug 2020 21:18:18 +0200 Subject: arm64: dts: imx8mm-var-som: Add Variscite VAR-SOM-MX8MM System on Module Add DTSI of Variscite VAR-SOM-MX8MM System on Module in a basic version, delivered with Variscite Symphony Evaluation kit. This version comes with: - 2 GB of RAM, - 16 GB eMMC, - Gigabit Ethernet PHY, - 802.11 ac/a/b/g/n WiFi with 4.2 Bluetooth (Cypress CYW43353), - CAN bus, - Audio codec (not yet configured in DTSI). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 553 ++++++++++++++++++++++ 1 file changed, 553 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi new file mode 100644 index 000000000000..c371cb34b3f7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright (C) 2020 Krzysztof Kozlowski + */ + +#include "imx8mm.dtsi" + +/ { + model = "Variscite VAR-SOM-MX8MM module"; + compatible = "variscite,var-som-mx8mm", "fsl,imx8mm"; + + chosen { + stdout-path = &uart4; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth_phy>; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, + <&gpio1 0 GPIO_ACTIVE_LOW>; + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + /* Resistive touch controller */ + touchscreen@0 { + reg = <0>; + compatible = "ti,ads7846"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + + ti,x-min = /bits/ 16 <125>; + touchscreen-size-x = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + touchscreen-size-y = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + touchscreen-max-pressure = /bits/ 16 <255>; + touchscreen-average-samples = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-supply = <®_eth_phy>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /* TODO: configure audio, as of now just put a placeholder */ + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + status = "disabled"; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* Bluetooth */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; +}; + +/* WIFI */ +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD */ +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x41 + >; + }; + + pinctrl_reg_eth_phy: regethphygrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- cgit v1.2.3 From d65faff66128df72329481df7abd580e6f51d710 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 24 Aug 2020 21:18:19 +0200 Subject: arm64: dts: imx8mm-var-som-symphony: Add Variscite Symphony board with VAR-SOM-MX8MM Add a DTS for Variscite Symphony evaluation kit with VAR-SOM-MX8MM System on Module. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mm-var-som-symphony.dts | 246 +++++++++++++++++++++ 2 files changed, 247 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 97335205b600..296c84aef3f4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts new file mode 100644 index 000000000000..0bca737964d5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Krzysztof Kozlowski + */ + +/dts-v1/; + +#include "imx8mm-var-som.dtsi" + +/ { + model = "Variscite VAR-SOM-MX8MM Symphony evaluation board"; + compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm"; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + back { + label = "Back"; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "Heartbeat"; + gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +ðphy { + reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + wakeup-source; + + /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ + usb3-sata-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "usb3_sata_sel"; + }; + + som-vselect-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "som_vselect"; + }; + + enet-sel-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "enet_sel"; + }; + }; + + extcon_usbotg1: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + int-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + status = "okay"; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio5>; + interrupts = <4 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + wakeup-source; + }; +}; + +/* Header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; +}; + +&usbotg2 { + dr_mode = "host"; + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + /delete-property/ usb-role-switch; + /* + * FIXME: having USB2 enabled hangs the boot just after: + * [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller + * [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1 + * [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00 + * [ 1.977203] hub 1-0:1.0: USB hub found + * [ 1.980987] hub 1-0:1.0: 1 port detected + */ + status = "disabled"; +}; + +&iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 + >; + }; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 + >; + }; + + pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; +}; -- cgit v1.2.3 From 355d7d0124fd0990ba6da74f959fbfe0ccf09c25 Mon Sep 17 00:00:00 2001 From: Chris Healy Date: Mon, 24 Aug 2020 20:04:06 -0700 Subject: dt-bindings: nvmem: Add syscon to Vybrid OCOTP driver Add syscon compatibility with Vybrid OCOTP driver binding. This is required to access the UID. Fixes: 623069946952 ("nvmem: Add DT binding documentation for Vybrid OCOTP driver") Signed-off-by: Chris Healy Reviewed-by: Stefan Agner Reviewed-by: Fabio Estevam Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt b/Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt index 56ed481c3e26..72ba628f6d0b 100644 --- a/Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt @@ -2,7 +2,7 @@ On-Chip OTP Memory for Freescale Vybrid Required Properties: compatible: - - "fsl,vf610-ocotp" for VF5xx/VF6xx + - "fsl,vf610-ocotp", "syscon" for VF5xx/VF6xx #address-cells : Should be 1 #size-cells : Should be 1 reg : Address and length of OTP controller and fuse map registers @@ -11,7 +11,7 @@ Required Properties: Example for Vybrid VF5xx/VF6xx: ocotp: ocotp@400a5000 { - compatible = "fsl,vf610-ocotp"; + compatible = "fsl,vf610-ocotp", "syscon"; #address-cells = <1>; #size-cells = <1>; reg = <0x400a5000 0xCF0>; -- cgit v1.2.3 From f2dc2359b75e1fd345fd710862f73db20dc55864 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 28 Aug 2020 14:05:56 +0100 Subject: arm64: dts: freescale: Fix SP805 clock-names The SP805 binding sets the order of the clock-names to be: "wdog_clk", "apb_pclk" (in exactly that order). Change the order in the DTs for Freescale platforms to match that. The two clocks given in all nodes are actually the same, so that does not change any behaviour. Signed-off-by: Andre Przywara Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++++++++-------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 0efeb8fa773e..13c0163939ad 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -722,14 +722,14 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: watchdog@c010000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; sai1: audio-controller@f100000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index b961a896ede7..c909ad12cfec 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -676,56 +676,56 @@ compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: wdt@c010000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core2_watchdog: wdt@c020000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc020000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core3_watchdog: wdt@c030000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc030000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core0_watchdog: wdt@c100000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core1_watchdog: wdt@c110000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core2_watchdog: wdt@c120000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc120000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core3_watchdog: wdt@c130000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc130000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; fsl_mc: fsl-mc@80c000000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index cc36c969dd9d..bf72918fe545 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -354,56 +354,56 @@ compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: wdt@c010000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core0_watchdog: wdt@c100000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core1_watchdog: wdt@c110000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster3_core0_watchdog: wdt@c200000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc200000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster3_core1_watchdog: wdt@c210000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc210000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster4_core0_watchdog: wdt@c300000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc300000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster4_core1_watchdog: wdt@c310000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc310000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; crypto: crypto@8000000 { -- cgit v1.2.3 From a4a3550e0db8b31ffafe223427cce9fa6cee0eff Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 21:22:28 +0200 Subject: arm64: dts: imx8mq-librem5-devkit: Add missing clock-cells to PMIC The PMIC node can be a clock provider (for its 32 kHz clock) and authors of imx8mq-librem5-devkit.dts apparently wanted this because they added input clock and clock-output-names. Add necessary clock-cells to the PMIC node. Signed-off-by: Krzysztof Kozlowski Reviewed-and-tested-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 51fdc969f3d5..a80e53428c2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -285,6 +285,7 @@ pinctrl-0 = <&pinctrl_pmic>; clocks = <&pmic_osc>; clock-names = "osc"; + #clock-cells = <0>; clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; interrupts = <3 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From fc7f54fb13b807c556770a69468188947981a400 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Aug 2020 09:54:35 +0100 Subject: ARM: dts: r8a7742-iwg21m: Add SPI NOR support Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200825085435.8744-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi index 0f26807f92b8..5621c9ed698f 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -35,6 +35,16 @@ clock-frequency = <20000000>; }; +&gpio0 { + /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */ + qspi_en { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "QSPI_EN"; + }; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -70,4 +80,45 @@ groups = "mmc1_data4", "mmc1_ctrl"; function = "mmc1"; }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x000c0000>; + read-only; + }; + partition@c0000 { + label = "env"; + reg = <0x000c0000 0x00002000>; + }; + partition@c2000 { + label = "user"; + reg = <0x000c2000 0x0013e000>; + }; + }; + }; }; -- cgit v1.2.3 From 557e64084abae2a31f494ac51e4cec549a3bf5ae Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Tue, 25 Aug 2020 11:44:55 +0100 Subject: arm64: dts: renesas: r8a774e1: Add PWM device nodes This patch adds PWM[0123456] device nodes to the RZ/G2H (a.k.a R8A774E1) device tree. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200825104455.18000-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 64 ++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index f783ad8aeafa..f5909ced7679 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1246,11 +1246,73 @@ }; pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; #pwm-cells = <2>; status = "disabled"; + }; - /* placeholder */ + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; }; scif0: serial@e6e60000 { -- cgit v1.2.3 From bce8ac223e760a603a555d592bbdb589b6625537 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 27 Aug 2020 14:49:57 +0900 Subject: arm64: dts: renesas: r8a77961: Enable Sound / Audio-DMAC This patch enables Sound and Audio-DMAC for R-Car M3-W+ (R8A77961). It is tested on R-Car M3-W+ Salvator-XS board. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87h7sovdvt.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 483 +++++++++++++++++++++++++++++- 1 file changed, 475 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 542c44c7dbca..23e6d6529e58 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1228,27 +1228,494 @@ }; rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - /* placeholder */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A77961_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + rcar_sound,dvc { - dvc0: dvc-0 { }; - dvc1: dvc-1 { }; + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; }; rcar_sound,src { - src0: src-0 { }; - src1: src-1 { }; + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; }; rcar_sound,ssi { - ssi0: ssi-0 { }; - ssi1: ssi-1 { }; - ssi2: ssi-2 { }; + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; + }; }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a77961", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a77961", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, + <&ipmmu_mp 18>, <&ipmmu_mp 19>, + <&ipmmu_mp 20>, <&ipmmu_mp 21>, + <&ipmmu_mp 22>, <&ipmmu_mp 23>, + <&ipmmu_mp 24>, <&ipmmu_mp 25>, + <&ipmmu_mp 26>, <&ipmmu_mp 27>, + <&ipmmu_mp 28>, <&ipmmu_mp 29>, + <&ipmmu_mp 30>, <&ipmmu_mp 31>; }; xhci0: usb@ee000000 { -- cgit v1.2.3 From 93b72bfa6e2499df18ef2cef2c88e6656f6d94d9 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 23 Jul 2020 16:11:36 -0500 Subject: arm64: dts: ti: k3-am65: Fix interconnect node names The various CBASS interconnect nodes on K3 AM65x SoCs are defined using the node name "interconnect". This is not a valid node name as per the dt-schema. Fix these node names to use the standard name used for SoC interconnects, "bus". Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200723211137.26641-2-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am65.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 27c0406b10ba..d84c0bc05023 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -61,7 +61,7 @@ interrupts = ; }; - cbass_main: interconnect@100000 { + cbass_main: bus@100000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -88,7 +88,7 @@ <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; - cbass_mcu: interconnect@28380000 { + cbass_mcu: bus@28380000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -106,7 +106,7 @@ <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ - cbass_wakeup: interconnect@42040000 { + cbass_wakeup: bus@42040000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 995504b6fa47005d20104f20922e65e4ad8d3e50 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 23 Jul 2020 16:11:37 -0500 Subject: arm64: dts: ti: k3-j721e: Fix interconnect node names The various CBASS interconnect nodes on K3 J721E SoCs are defined using the node name "interconnect". This is not a valid node name as per the dt-schema. Fix these node names to use the standard name used for SoC interconnects, "bus". Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200723211137.26641-3-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index d035b61e0e16..f787aa73aaae 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -120,7 +120,7 @@ interrupts = ; }; - cbass_main: interconnect@100000 { + cbass_main: bus@100000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -155,7 +155,7 @@ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - cbass_mcu_wakeup: interconnect@28380000 { + cbass_mcu_wakeup: bus@28380000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From b366b2409c97e476cda7d83819d9b4851d2f57b1 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 26 Aug 2020 11:29:20 +0300 Subject: arm64: dts: ti: k3-am6: Add crypto accelarator node Add crypto accelarator node for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES, and AEAD suites. [t-kristo@ti.com: Modifications based on introduction of yaml binding] Signed-off-by: Keerthy Signed-off-by: Tero Kristo Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200826082921.19143-2-t-kristo@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 24ef18fe77df..e12759ce7918 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -112,6 +112,28 @@ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; }; + crypto: crypto@4e00000 { + compatible = "ti,am654-sa2ul"; + reg = <0x0 0x4e00000 0x0 0x1200>; + power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; + status = "okay"; + + dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, + <&main_udmap 0x4001>; + dma-names = "tx", "rx1", "rx2"; + dma-coherent; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x0 0x4e10000 0x0 0x7d>; + interrupts = ; + clocks = <&k3_clks 136 1>; + }; + }; + main_pmx0: pinmux@11c000 { compatible = "pinctrl-single"; reg = <0x0 0x11c000 0x0 0x2e4>; -- cgit v1.2.3 From 8ebcaaae8017466f62cf36e1d0023faa1d5f924c Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 26 Aug 2020 11:29:21 +0300 Subject: arm64: dts: ti: k3-j721e-main: Add crypto accelerator node Add crypto accelarator node for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES, and AEAD suites. [t-kristo@ti.com: Modifications based on introduction of yaml binding] Signed-off-by: Keerthy Signed-off-by: Tero Kristo Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200826082921.19143-3-t-kristo@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 12ceea9b3c9a..10f00d7a0c3b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -304,6 +304,29 @@ }; }; + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x0 0x4e00000 0x0 0x1200>; + power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; + + status = "okay"; + + dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, + <&main_udmap 0x4001>; + dma-names = "tx", "rx1", "rx2"; + dma-coherent; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x0 0x4e10000 0x0 0x7d>; + interrupts = ; + clocks = <&k3_clks 264 1>; + }; + }; + main_pmx0: pinmux@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ -- cgit v1.2.3 From 74b5742b59b19f4ae9c53ae719161928d9768879 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 25 Aug 2020 12:21:38 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file The commit eb9f9173d01f ("arm64: dts: ti: k3-j721e-common-proc-board: Add IPC sub-mailbox nodes") has added the sub-mailbox nodes used by various remote processors and disabled the unused mailbox clusters directly in the k3-j721e-common-proc-board dts file. Move all of these nodes into the k3-j721e-som-p0.dtsi file instead to co-locate all the mailboxes and the soon to be added DDR reserved-memory carveout nodes used by remoteprocs within the same dtsi file. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200825172145.13186-2-s-anna@ti.com --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 93 ---------------------- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 93 ++++++++++++++++++++++ 2 files changed, 93 insertions(+), 93 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index e8fc01d97ada..c355692796a9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -286,99 +286,6 @@ status = "disabled"; }; -&mailbox0_cluster0 { - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &main_sdhci0 { /* eMMC */ non-removable; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 8fa3361e5e45..44a7e03b60d8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -72,3 +72,96 @@ #size-cells = <1>; }; }; + +&mailbox0_cluster0 { + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + interrupts = <424>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; -- cgit v1.2.3 From eb9a2a637ae5b23d7881f28fb83d11c88a371229 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 25 Aug 2020 12:21:39 -0500 Subject: arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional 288 KB of L2 configurable SRAM/Cache. These subsystems do not have an MMU but contain a Region Address Translator (RAT) sub-module for translating 32-bit processor addresses into larger bus addresses. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Add the DT nodes for these DSP processor sub-systems in the common k3-j721e-main.dtsi file. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: C66x_0 DSP: j7-c66_0-fw C66x_1 DSP: j7-c66_1-fw Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200825172145.13186-3-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 10f00d7a0c3b..52f3373e6d0f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1349,4 +1349,30 @@ assigned-clocks = <&k3_clks 253 1>; assigned-clock-parents = <&k3_clks 253 5>; }; + + c66_0: dsp@4d80800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x80800000 0x00 0x00048000>, + <0x4d 0x80e00000 0x00 0x00008000>, + <0x4d 0x80f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <142>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 142 1>; + firmware-name = "j7-c66_0-fw"; + }; + + c66_1: dsp@4d81800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x81800000 0x00 0x00048000>, + <0x4d 0x81e00000 0x00 0x00008000>, + <0x4d 0x81f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <143>; + ti,sci-proc-ids = <0x04 0xff>; + resets = <&k3_reset 143 1>; + firmware-name = "j7-c66_1-fw"; + }; }; -- cgit v1.2.3 From a55babbf00d71f285bbd52433a859862cc3223fb Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 25 Aug 2020 12:21:40 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs Add the required 'mboxes' property to both the C66x DSP processors for the TI J721E common processor board. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the DSPs. The nodes are therefore added in the common k3-j721e-som-p0.dtsi file so that all of these can be co-located. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200825172145.13186-4-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 44a7e03b60d8..20defa0530e5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -165,3 +165,11 @@ &mailbox0_cluster11 { status = "disabled"; }; + +&c66_0 { + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; +}; + +&c66_1 { + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; +}; -- cgit v1.2.3 From e379ba840a7e2c8fb275722226154339077b8f37 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 25 Aug 2020 12:21:41 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs Two carveout reserved memory nodes each have been added for each of the C66x DSP remote processor devices present within the MAIN voltage domain for the TI J721E EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc devices, and the second region will furnish the static carveout regions for the firmware memory. The minimum granularity on the Cache settings on C66x DSP cores is 16 MB, so the DMA memory regions are chosen such that they are in separate 16 MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts. The current carveout addresses and sizes are defined statically for each device. The C66x DSP processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables to allocate the memory for firmware memory segments. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200825172145.13186-5-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 20defa0530e5..eeffaf9bf471 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -25,6 +25,30 @@ alignment = <0x1000>; no-map; }; + + c66_1_dma_memory_region: c66-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: c66-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c66_0_dma_memory_region: c66-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: c66-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; }; }; @@ -168,8 +192,12 @@ &c66_0 { mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + memory-region = <&c66_0_dma_memory_region>, + <&c66_0_memory_region>; }; &c66_1 { mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + memory-region = <&c66_1_dma_memory_region>, + <&c66_1_memory_region>; }; -- cgit v1.2.3 From 804a4cc7fe3cc7207b25c63f21ea82f1b77d19ae Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 25 Aug 2020 12:21:42 -0500 Subject: arm64: dts: ti: k3-j721e-main: Add C71x DSP node The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN voltage domain containing the next-generation C711 CPU core. The subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of L2 configurable SRAM/Cache. This subsystem has a CMMU but is not used currently. The inter-processor communication between the main A72 cores and the C711 processor is achieved through shared memory and a Mailbox. Add the DT node for this DSP processor sub-system in the common k3-j721e-main.dtsi file. The following firmware name is used by default for the C71x core, and can be overridden in a board dts file if desired: C71x_0 DSP: j7-c71_0-fw Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200825172145.13186-6-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 52f3373e6d0f..00a36a14efe7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1375,4 +1375,16 @@ resets = <&k3_reset 143 1>; firmware-name = "j7-c66_1-fw"; }; + + c71_0: dsp@64800000 { + compatible = "ti,j721e-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <15>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 15 1>; + firmware-name = "j7-c71_0-fw"; + }; }; -- cgit v1.2.3 From cf53928fa0d9120d9c5336504e1c836e453f446a Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 25 Aug 2020 12:21:43 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP Add the required 'mboxes' property to the C71x DSP processor for the TI J721E common processor board. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the DSPs. The nodes are therefore added in the common k3-j721e-som-p0.dtsi file so that all of these can be co-located. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200825172145.13186-7-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index eeffaf9bf471..bb37651a0014 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -201,3 +201,7 @@ memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; + +&c71_0 { + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; +}; -- cgit v1.2.3 From 1939d37f94937cf5082ee2612b76106cb3d90978 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 25 Aug 2020 12:21:44 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP Two carveout reserved memory nodes have been added for the lone C71x DSP remote processor device present within the MAIN voltage domain for the TI J721E EVM boards. These nodes are assigned to the respective rproc device node as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor does support a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. The firmware images currently do not need any RSC_CARVEOUT entries either in their resource tables to allocate the memory for firmware memory segments. The reserved memory nodes can be disabled later on if there is no use-case defined to use the C71x DSP remoteproc processor. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200825172145.13186-8-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index bb37651a0014..0e28be492ac2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -49,6 +49,18 @@ reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; }; }; @@ -204,4 +216,6 @@ &c71_0 { mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; }; -- cgit v1.2.3 From 67cfbb62132e4210b4c4785b0ca1fbe4cafb7c4d Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 25 Aug 2020 12:21:45 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores Add a reserved memory node to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the remote processors running RTOS on the TI J721E EVM boards. 28 MB of memory is reserved for this purpose, and this accounts for all the vrings and vring buffers between all the possible pairs of remote processors. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20200825172145.13186-9-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 0e28be492ac2..d69d90c8b5e3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -61,6 +61,12 @@ reg = <0x00 0xa8100000 0x00 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; }; -- cgit v1.2.3 From 269a5641b1ed0ac00e9d75b43985407b34540d77 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Sun, 2 Aug 2020 22:23:56 +0530 Subject: arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed Per errata i2104 documented in AM65x device errata document (TI document number SPRZ452E, revised June 2019), Gen3 operation is not supported for both PCIe Root Complex and Endpoint modes of operation. See: https://www.ti.com/lit/er/sprz452e/sprz452e.pdf Restrict speed to Gen2 to address the errata. Signed-off-by: Sekhar Nori Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200802165356.10285-1-nsekhar@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index e12759ce7918..76e0edc4ad5c 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -704,7 +704,7 @@ ti,syscon-pcie-mode = <&pcie0_mode>; bus-range = <0x0 0xff>; num-viewport = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = ; msi-map = <0x0 &gic_its 0x0 0x10000>; @@ -718,7 +718,7 @@ ti,syscon-pcie-mode = <&pcie0_mode>; num-ib-windows = <16>; num-ob-windows = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = ; }; @@ -736,7 +736,7 @@ ti,syscon-pcie-mode = <&pcie1_mode>; bus-range = <0x0 0xff>; num-viewport = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = ; msi-map = <0x0 &gic_its 0x10000 0x10000>; @@ -750,7 +750,7 @@ ti,syscon-pcie-mode = <&pcie1_mode>; num-ib-windows = <16>; num-ob-windows = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = ; }; -- cgit v1.2.3 From 6e043c658e7917200e6251d1fa67b64c332f0531 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 31 Aug 2020 12:56:55 -0500 Subject: arm64: dts: stratix10/agilex: add the ptp_ref clock Add the ptp_ref clock for the GMACs. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------ arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index a6fb01c7ab34..0f893984c256 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -145,8 +145,8 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC0_CLK>; - clock-names = "stmmaceth"; + clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -163,8 +163,8 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC1_CLK>; - clock-names = "stmmaceth"; + clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -181,8 +181,8 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC2_CLK>; - clock-names = "stmmaceth"; + clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index d81dd8622258..e1c0fcba5c20 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -149,8 +149,8 @@ snps,multicast-filter-bins = <256>; iommus = <&smmu 1>; altr,sysmgr-syscon = <&sysmgr 0x44 0>; - clocks = <&clkmgr AGILEX_EMAC0_CLK>; - clock-names = "stmmaceth"; + clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; status = "disabled"; }; @@ -167,8 +167,8 @@ snps,multicast-filter-bins = <256>; iommus = <&smmu 2>; altr,sysmgr-syscon = <&sysmgr 0x48 8>; - clocks = <&clkmgr AGILEX_EMAC1_CLK>; - clock-names = "stmmaceth"; + clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; status = "disabled"; }; @@ -185,8 +185,8 @@ snps,multicast-filter-bins = <256>; iommus = <&smmu 3>; altr,sysmgr-syscon = <&sysmgr 0x4c 16>; - clocks = <&clkmgr AGILEX_EMAC2_CLK>; - clock-names = "stmmaceth"; + clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; status = "disabled"; }; -- cgit v1.2.3 From 7ec3e67307f8611b5db7f76048505df9393563ea Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Fri, 28 Aug 2020 13:40:50 -0700 Subject: arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt This is essentialy a squash of a bunch of history of trogdor and lazor dt updates from the chromium kernel tree. I don't claim any credit other than wanting to more easily boot upstream kernel on these devices. I've tried to add cc tags for all the original authors. Cc: Stephen Boyd Cc: Douglas Anderson Cc: Matthias Kaehlcke Cc: Atul Dhudase Cc: Venkata Lakshmi Narayana Gubba Cc: Evan Green Cc: Cheng-Yi Chiang Cc: Ajit Pandey Cc: Alexandru Stan Cc: Sujit Kautkar Signed-off-by: Rob Clark Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20200828204052.2085508-1-robdclark@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 5 + .../boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 24 + .../boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 18 + .../boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 15 + arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 192 +++ .../boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 15 + arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts | 14 + arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 191 +++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1348 ++++++++++++++++++++ 9 files changed, 1822 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d8f1466e6758..5899101526a7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -19,6 +19,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts new file mode 100644 index 000000000000..ae4c23a4fe65 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-lazor.dtsi" + +/ { + model = "Google Lazor (rev0)"; + compatible = "google,lazor-rev0", "qcom,sc7180"; +}; + +&sn65dsi86_out { + /* + * Lane 0 was incorrectly mapped on the cable, but we've now decided + * that the cable is canon and in -rev1+ we'll make a board change + * that means we no longer need the swizzle. + */ + lane-polarities = <1 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts new file mode 100644 index 000000000000..73e59cf7752a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +#include "sc7180-trogdor-lazor-r1.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor (rev1+) with LTE"; + compatible = "google,lazor-sku0", "qcom,sc7180"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts new file mode 100644 index 000000000000..3151ae31c1cc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-lazor.dtsi" + +/ { + model = "Google Lazor (rev1+)"; + compatible = "google,lazor", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi new file mode 100644 index 000000000000..180ef9e04306 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +#include "sc7180.dtsi" + +ap_ec_spi: &spi6 {}; +ap_h1_spi: &spi0 {}; + +#include "sc7180-trogdor.dtsi" + +/ { + panel: panel { + compatible = "boe,nv133fhm-n62"; + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; + + ports { + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; +}; + +&ap_sar_sensor { + status = "okay"; +}; + +ap_ts_pen_1v8: &i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +&ts_reset_l { + pinconf { + /* This pin is not connected on -rev0, pull up to park. */ + /delete-property/bias-disable; + bias-pull-up; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "ESIM_MISO", + "ESIM_MOSI", + "ESIM_CLK", + "ESIM_CS_L", + "", + "", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "AP_RAM_ID2", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "AP_RAM_ID1", + "AP_SKU_ID2", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "AP_RAM_ID0", + "EN_PP3300_DX_EDP", + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "", + "", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "TRACKPAD_INT_1V8_ODL", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "DBG_SPI_HOLD_L", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "EN_PP3300_CODEC", + "EN_PP3300_HUB", + "", + "", + "", + "", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "EDP_BRIJ_EN", + "AP_SKU_ID0", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi new file mode 100644 index 000000000000..44956e3165a1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts fragment for LTE SKUs + * + * Copyright 2020 Google LLC. + */ + +&ap_sar_sensor { + label = "proximity-wifi-lte"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn", + "qcom/sc7180-trogdor/modem/qdsp6sw.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts new file mode 100644 index 000000000000..1123c02bd539 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor board device tree source + * + * Copyright 2020 Google LLC. + */ + +#include "sc7180-trogdor-r1.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Trogdor (rev1+) with LTE"; + compatible = "google,trogdor-sku0", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts new file mode 100644 index 000000000000..0a281c24841c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor board device tree source + * + * Copyright 2020 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" + +ap_ec_spi: &spi6 {}; +ap_h1_spi: &spi0 {}; + +#include "sc7180-trogdor.dtsi" + +/ { + model = "Google Trogdor (rev1+)"; + compatible = "google,trogdor", "qcom,sc7180"; + + panel: panel { + compatible = "auo,b116xa01"; + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; + + ports { + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; +}; + +&ap_sar_sensor_i2c { + /* Not hooked up */ + status = "disabled"; +}; + +ap_ts_pen_1v8: &i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + +&sdhc_2 { + status = "okay"; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "ESIM_MISO", + "ESIM_MOSI", + "ESIM_CLK", + "ESIM_CS_L", + "FP_TO_AP_IRQ_L", + "FP_RST_L", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "FPMCU_BOOT0", + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "PEN_RST_ODL", + "AP_RAM_ID1", + "AP_RAM_ID2", + "PEN_IRQ_L", + "FPMCU_SEL", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "AP_RAM_ID0", + "EN_PP3300_DX_EDP", + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "", + "", + "AMP_DIN", + "PEN_PDCT_L", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "TRACKPAD_INT_1V8_ODL", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "DBG_SPI_HOLD_L", + "AP_SPI_CS0_L", + "SD_CD_ODL", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "EN_PP3300_CODEC", + "EN_PP3300_HUB", + "", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "EDP_BRIJ_EN", + "AP_SKU_ID0", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi new file mode 100644 index 000000000000..a6b9beb29be9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -0,0 +1,1348 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor device tree source (common between revisions) + * + * Copyright 2019 Google LLC. + */ + +#include +#include +#include + +/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the board dts. + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &aop_mem; +/delete-node/ &sec_apps_mem; +/delete-node/ &tz_mem; + +/* Increase the size from 2MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x84400000 0x0 0x800000>; +}; + +/ { + reserved-memory { + atf_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + mpss_mem: memory@86000000 { + reg = <0x0 0x86000000 0x0 0x8c00000>; + no-map; + }; + + camera_mem: memory@8ec00000 { + reg = <0x0 0x8ec00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8f600000 { + reg = <0 0x8f600000 0 0x500000>; + no-map; + }; + + wlan_mem: memory@94100000 { + reg = <0x0 0x94100000 0x0 0x200000>; + no-map; + }; + + mba_mem: memory@94400000 { + reg = <0x0 0x94400000 0x0 0x200000>; + no-map; + }; + }; + + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart3; + serial0 = &uart8; + wifi0 = &wifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* FIXED REGULATORS - parents above children */ + + /* This is the top level supply and variable voltage */ + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + /* This divides ppvar_sys by 2, so voltage is variable */ + src_vph_pwr: src-vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "src_vph_pwr"; + + /* EC turns on with switchcap_on; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; + + pp5000_a: pp5000-a-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp5000_a"; + + /* EC turns on with en_pp5000_a; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_a: pp3300-a-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_a"; + + /* EC turns on with en_pp3300_a; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + /* + * Actually should be pp3300 but that's practically an alias for + * pp3300_a so we use pp3300's vin-supply here to avoid one more + * node. + */ + vin-supply = <&ppvar_sys>; + }; + + pp3300_audio: + pp3300_codec: pp3300-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_codec"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_codec>; + + vin-supply = <&pp3300_a>; + }; + + pp3300_dx_edp: + pp3300_ts: pp3300-dx-edp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_dx_edp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_dx_edp>; + + vin-supply = <&pp3300_a>; + }; + + pp3300_fp_tp: pp3300-fp-tp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_fp_tp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + /* AP turns on with PP1800_VIO_OUT; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp3300_a>; + }; + + /* BOARD-SPECIFIC TOP LEVEL NODES */ + + backlight: backlight { + compatible = "pwm-backlight"; + + pwms = <&cros_ec_pwm 1>; + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + power-supply = <&ppvar_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_edp_bklten>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pen_pdct_l>; + + pen-insert { + label = "Pen Insert"; + + /* Insert = low, eject = high */ + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + }; + + max98357a: audio-codec-0 { + compatible = "maxim,max98357a"; + pinctrl-names = "default"; + pinctrl-0 = <&_en>; + sdmode-gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + + pwmleds { + compatible = "pwm-leds"; + keyboard_backlight: keyboard-backlight { + status = "disabled"; + label = "cros_ec::kbd_backlight"; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&qfprom { + vcc-supply = <&pp1800_l11a>; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* TODO: Increase frequency after testing */ + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&apps_rsc { + pm6150-rpmh-regulators { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vddpx_1: + vdd2: + pp1125_s1a: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + /* + * pp2040_s5a (smps5) and pp1056_s4a (smps4) are just + * inputs to other rails on AOP-managed PMICs on trogdor. + * The system is already configured to manage these rails + * automatically (enable when needed, adjust voltage for + * headroom) so we won't specify anything here. + * + * NOTE: though the rails have a voltage implied by their + * name, the automatic headroom calculation might not result + * in them being that voltage. ...and that's OK. + * Specifically the only point of these rails is to provide + * an input source for other rails and if we can satisify the + * needs of those other rails with a lower source voltage then + * we save power. + */ + + pp1200_l1a: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pp1000_l2a: ldo2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + pp1000_l3a: ldo3 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = ; + }; + + vdd_qlink_lv: + vdd_qlink_lv_ck: + vdd_qusb_hs0_core: + vdd_ufs1_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_csi3_0p9: + vdda_mipi_dsi0_pll: + vdda_pll_cc_ebi01: + vdda_qrefs_0p9: + vdda_usb_ss_dp_core: + pp900_l4a: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <928000>; + regulator-initial-mode = ; + }; + + pp2700_l5a: ldo5 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + ebi0_cal: + ebi1_cal: + vddio_ck_ebi0: + vddio_ck_ebi1: + vddio_ebi0: + vddq: + pp600_l6a: ldo6 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <648000>; + regulator-initial-mode = ; + }; + + vdd_cx_wlan: + pp800_l9a: ldo9 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vdd1: + vddpx_3: + vddpx_7: + vio_in: + pp1800_l10a: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdda_apc1_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_bb_clk: + pp1800_l11a: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + mcp_vccq: + pp1800_l12a_r: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pp1800_l13a: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pp1800_prox: + pp1800_l14a: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pp1800_alc5682: + pp1800_l15a: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pp2700_l16a: ldo16 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vdda_qusb_hs0_3p1: + vdd_pdphy: + pp3100_l17a: ldo17 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + pp1800_pen: + pp1800_l18a: ldo18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + mcp_vcc: + pp2850_l19a: ldo19 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + pm6150l-rpmh-regulators { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + pp1300_s8c: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + pp1800_l1c: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdd_wcss_adc_dac: + pp1300_l2c: ldo2 { + regulator-min-microvolt = <1168000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + pp1200_brij: + vdd_ufs1_1p2: + vdda_csi0_1p25: + vdda_csi1_1p25: + vdda_csi2_1p25: + vdda_csi3_1p25: + vdda_hv_ebi0: + vdda_mipi_dsi0_1p2: + vdda_usb_ss_dp_1p2: + vddpx_10: + pp1200_l3c: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ld_pp1800_esim_l4c: + vddpx_5: + pp1800_l4c: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vddpx_6: + pp1800_l5c: ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_2: + ppvar_l6c: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + pp3300_hub: + pp3300_l7c: ldo7 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + pp1800_brij_vccio: + pp1800_edp_vpll: + pp1800_l8c: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pp2950_l9c: ldo9 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + pp3300_l10c: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + pp3300_l11c: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + src_vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&ap_ec_spi { + status = "okay"; + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <94 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_ec_int_l>; + spi-max-frequency = <3000000>; + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pdupdate { + compatible = "google,cros-ec-pd-update"; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +&ap_h1_spi { + status = "okay"; + cr50: tpm@0 { + compatible = "google,cr50"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_ap_int_odl>; + spi-max-frequency = <800000>; + interrupt-parent = <&tlmm>; + interrupts = <42 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + +edp_brij_i2c: &i2c2 { + status = "okay"; + clock-frequency = <400000>; + + sn65dsi86_bridge: bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&pp1800_edp_vpll>; + vccio-supply = <&pp1800_brij_vccio>; + vcca-supply = <&pp1200_brij>; + vcc-supply = <&pp1200_brij>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK3>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; +}; + +ap_sar_sensor_i2c: &i2c5 { + status = "okay"; + clock-frequency = <400000>; + + ap_sar_sensor: proximity@28 { + compatible = "semtech,sx9310"; + reg = <0x28>; + #io-channel-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&p_sensor_int_l>; + + interrupt-parent = <&tlmm>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&pp3300_a>; + svdd-supply = <&pp1800_prox>; + + status = "disabled"; + label = "proximity-wifi"; + }; +}; + +ap_tp_i2c: &i2c7 { + status = "okay"; + clock-frequency = <400000>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_1v8_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <58 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&pp3300_fp_tp>; + + wakeup-source; + }; +}; + +hp_i2c: &i2c9 { + status = "okay"; + clock-frequency = <400000>; + + alc5682: codec@1a { + compatible = "realtek,rt5682i"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_irq>; + + #sound-dai-cells = <1>; + + interrupt-parent = <&tlmm>; + /* + * This will get ignored because the interrupt type + * is set in rt5682.c. + */ + interrupts = <28 IRQ_TYPE_EDGE_BOTH>; + + AVDD-supply = <&pp1800_alc5682>; + MICVDD-supply = <&pp3300_codec>; + VBAT-supply = <&pp3300_audio>; + + realtek,dmic1-data-pin = <1>; + realtek,dmic1-clk-pin = <1>; + realtek,jd-src = <1>; + }; +}; + +&ipa { + status = "okay"; + + /* + * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the + * modem needs to cover certain init steps (GSI init), and + * the AP needs to wait for it. + */ + modem-init; +}; + +&mdp { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&pm6150_pwrkey { + status = "disabled"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_mpss { + status = "okay"; + compatible = "qcom,sc7180-mss-pil"; + iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; + memory-region = <&mba_mem &mpss_mem>; + + /* This gets overridden for SKUs with LTE support. */ + firmware-name = "qcom/sc7180-trogdor/modem-nolte/mba.mbn", + "qcom/sc7180-trogdor/modem-nolte/qdsp6sw.mbn"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + vmmc-supply = <&mcp_vcc>; + vqmmc-supply = <&mcp_vccq>; +}; + +&sdhc_2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + vmmc-supply = <&pp2950_l9c>; + vqmmc-supply = <&ppvar_l6c>; + + cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; +}; + +ap_spi_fp: &spi10 { + cros_ec_fp: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>, <&fpmcu_sel>; + spi-max-frequency = <3000000>; + }; +}; + +#include +#include + +&uart3 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3991-bt"; + vddio-supply = <&pp1800_l10a>; + vddxo-supply = <&pp1800_l1c>; + vddrf-supply = <&pp1300_l2c>; + vddch0-supply = <&pp3300_l10c>; + max-speed = <3200000>; + clocks = <&rpmhcc RPMH_RF_CLK2>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + vdd-supply = <&vdd_qusb_hs0_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + qcom,imp-res-offset-value = <8>; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + qcom,bias-ctrl-value = <0x22>; + qcom,charge-ctrl-value = <3>; + qcom,hsdisc-trim-value = <0>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core>; +}; + +&venus { + video-firmware { + iommus = <&apps_smmu 0x0c42 0x0>; + }; +}; + +&wifi { + status = "okay"; + vdd-0.8-cx-mx-supply = <&vdd_cx_wlan>; + vdd-1.8-xo-supply = <&pp1800_l1c>; + vdd-1.3-rfa-supply = <&pp1300_l2c>; + vdd-3.3-ch0-supply = <&pp3300_l10c>; + vdd-3.3-ch1-supply = <&pp3300_l11c>; + + wifi-firmware { + iommus = <&apps_smmu 0xc2 0x1>; + }; +}; + +/* PINCTRL - additions to nodes defined in sc7180.dtsi */ + +&qspi_cs0 { + pinconf { + pins = "gpio68"; + bias-disable; + }; +}; + +&qspi_clk { + pinconf { + pins = "gpio63"; + bias-disable; + }; +}; + +&qspi_data01 { + pinconf { + pins = "gpio64", "gpio65"; + + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; + }; +}; + +&qup_i2c2_default { + pinconf { + pins = "gpio15", "gpio16"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c4_default { + pinconf { + pins = "gpio115", "gpio116"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c5_default { + pinconf { + pins = "gpio25", "gpio26"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c7_default { + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c9_default { + pinconf { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_spi0_default { + pinconf { + pins = "gpio34", "gpio35", "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi6_default { + pinconf { + pins = "gpio59", "gpio60", "gpio61", "gpio62"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi10_default { + pinconf { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_uart3_default { + pinconf-cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + bias-pull-down; + }; + + pinconf-rts-tx { + /* We'll drive RTS and TX, so no pull */ + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + pins = "gpio41"; + bias-pull-up; + }; +}; + +&qup_uart8_default { + pinconf-tx { + pins = "gpio44"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&pm6150_gpio { + status = "disabled"; /* No GPIOs are connected */ +}; + +&pm6150l_gpio { + gpio-line-names = "AP_SUSPEND", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&tlmm { + /* + * pinctrl settings for pins that have no real owners. + */ + pinctrl-names = "default"; + pinctrl-0 = <&bios_flash_wp_l>, <&ap_suspend_l_neuter>; + + amp_en: amp-en { + pinmux { + pins = "gpio23"; + function = "gpio"; + }; + + pinconf { + pins = "gpio23"; + bias-pull-down; + }; + }; + + ap_ec_int_l: ap-ec-int-l { + pinmux { + pins = "gpio94"; + function = "gpio"; + input-enable; + }; + + pinconf { + pins = "gpio94"; + bias-pull-up; + }; + }; + + ap_edp_bklten: ap-edp-bklten { + pinmux { + pins = "gpio12"; + function = "gpio"; + }; + + pinconf { + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + + /* Force backlight to be disabled to match state at boot. */ + output-low; + }; + }; + + ap_suspend_l_neuter: ap-suspend-l-neuter { + pinmux { + pins = "gpio27"; + function = "gpio"; + }; + + pinconf { + pins = "gpio27"; + bias-disable; + }; + }; + + bios_flash_wp_l: bios-flash-wp-l { + pinmux { + pins = "gpio66"; + function = "gpio"; + input-enable; + }; + + pinconf { + pins = "gpio66"; + bias-disable; + }; + }; + + dp_hot_plug_det: dp-hot-plug-det { + pinmux { + pins = "gpio117"; + function = "dp_hot"; + }; + + config { + pins = "gpio117"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + edp_brij_en: edp-brij-en { + pinmux { + pins = "gpio104"; + function = "gpio"; + }; + + pinconf { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + }; + }; + + edp_brij_irq: edp-brij-irq { + pinmux { + pins = "gpio11"; + function = "gpio"; + }; + + pinconf { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + en_pp3300_codec: en-pp3300-codec { + pinmux { + pins = "gpio83"; + function = "gpio"; + }; + + pinconf { + pins = "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + + en_pp3300_dx_edp: en-pp3300-dx-edp { + pinmux { + pins = "gpio30"; + function = "gpio"; + }; + + pinconf { + pins = "gpio30"; + drive-strength = <2>; + bias-disable; + }; + }; + + fpmcu_boot0: fpmcu-boot0 { + pinmux { + pins = "gpio10"; + function = "gpio"; + }; + + pinconf { + pins = "gpio10"; + bias-disable; + drive-strength = <2>; + output-low; + }; + }; + + fpmcu_sel: fpmcu-sel { + pinmux { + pins = "gpio22"; + function = "gpio"; + }; + + pinconf { + pins = "gpio22"; + bias-disable; + drive-strength = <2>; + output-high; + }; + }; + + fp_rst_l: fp-rst-l { + pinmux { + pins = "gpio5"; + function = "gpio"; + }; + + pinconf { + pins = "gpio5"; + bias-disable; + drive-strength = <2>; + output-high; + }; + }; + + fp_to_ap_irq_l: fp-to-ap-irq-l { + pinmux { + pins = "gpio4"; + function = "gpio"; + input-enable; + }; + + pinconf { + pins = "gpio4"; + + /* Has external pullup */ + bias-disable; + }; + }; + + + h1_ap_int_odl: h1-ap-int-odl { + pinmux { + pins = "gpio42"; + function = "gpio"; + input-enable; + }; + + pinconf { + pins = "gpio42"; + bias-pull-up; + }; + }; + + hp_irq: hp-irq { + pinmux { + pins = "gpio28"; + function = "gpio"; + }; + + pinconf { + pins = "gpio28"; + bias-pull-up; + }; + }; + + pen_irq_l: pen-irq-l { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + + /* Has external pullup */ + bias-disable; + }; + }; + + pen_pdct_l: pen-pdct-l { + pinmux { + pins = "gpio52"; + function = "gpio"; + }; + + pinconf { + pins = "gpio52"; + + /* Has external pullup */ + bias-disable; + }; + }; + + pen_rst_odl: pen-rst-odl { + pinmux { + pins = "gpio18"; + function = "gpio"; + }; + + pinconf { + pins = "gpio18"; + bias-disable; + drive-strength = <2>; + + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; /* TODO: Remove this? */ + }; + }; + + p_sensor_int_l: p-sensor-int-l { + pinmux { + pins = "gpio24"; + function = "gpio"; + input-enable; + }; + + pinconf { + pins = "gpio24"; + bias-pull-up; + }; + }; + + trackpad_int_1v8_odl: trackpad-int-1v8-odl { + pinmux { + pins = "gpio58"; + function = "gpio"; + }; + + pinconf { + pins = "gpio58"; + + /* Has external pullup */ + bias-disable; + }; + }; + + ts_int_l: ts-int-l { + pinmux { + pins = "gpio9"; + function = "gpio"; + }; + + pinconf { + pins = "gpio9"; + bias-pull-up; + }; + }; + + ts_reset_l: ts-reset-l { + pinmux { + pins = "gpio8"; + function = "gpio"; + }; + + pinconf { + pins = "gpio8"; + bias-disable; + drive-strength = <2>; + }; + }; +}; -- cgit v1.2.3 From 1e1129b65ef3f72dbccf24de56b700a181b45227 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Aug 2020 16:24:58 +0200 Subject: arm64: dts: exynos: Replace deprecated "gpios" i2c-gpio property in Exynos5433 "gpios" property is deprecated. Update the Exynos5433 DTS to fix dtbs_checks warnings like: arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: i2c-gpio-0: 'sda-gpios' is a required property arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: i2c-gpio-0: 'scl-gpios' is a required property Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Reviewed-by: Sylwester Nawrocki Link: https://lore.kernel.org/r/20200829142501.31478-7-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 250fc01de78d..6246cce2a15e 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -87,8 +87,8 @@ i2c_max98504: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */ - &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >; + sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 7e98d540f21fde5768b4d28f8b3016ac080735b0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Aug 2020 16:24:59 +0200 Subject: arm64: dts: exynos: Add compatibles to sysreg nodes System register nodes, implementing syscon binding, should use appropriate compatible. This fixes dtbs_check warnings: arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: syscon@13b80000: compatible: ['syscon'] is not valid under any of the given schemas Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sylwester Nawrocki Link: https://lore.kernel.org/r/20200829142501.31478-8-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 74ac4ac75865..b2eebdd88c3c 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1015,17 +1015,17 @@ }; syscon_disp: syscon@13b80000 { - compatible = "syscon"; + compatible = "samsung,exynos5433-sysreg", "syscon"; reg = <0x13b80000 0x1010>; }; syscon_cam0: syscon@120f0000 { - compatible = "syscon"; + compatible = "samsung,exynos5433-sysreg", "syscon"; reg = <0x120f0000 0x1020>; }; syscon_cam1: syscon@145f0000 { - compatible = "syscon"; + compatible = "samsung,exynos5433-sysreg", "syscon"; reg = <0x145f0000 0x1038>; }; -- cgit v1.2.3 From 68f4babbc63772ab4d7f99e97f3c93f9547703de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Aug 2020 19:25:30 +0200 Subject: ARM: dts: exynos: Move fixed clocks under root node in Exynos3250 The fixed clocks are kept under dedicated node fixed-rate-clocks, thus a fake "reg" was added. This is not correct with dtschema as fixed-clock binding does not have a "reg" property: arch/arm/boot/dts/exynos3250-artik5-eval.dt.yaml: clock@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200829172532.29358-2-krzk@kernel.org --- arch/arm/boot/dts/exynos3250.dtsi | 42 ++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index d3fb45a56527..c67c70e46794 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -97,33 +97,25 @@ }; }; - fixed-rate-clocks { - #address-cells = <1>; - #size-cells = <0>; - - xusbxti: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xusbxti"; - }; + xusbxti: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xusbxti"; + }; - xxti: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xxti"; - }; + xxti: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xxti"; + }; - xtcxo: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xtcxo"; - }; + xtcxo: clock-2 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xtcxo"; }; pmu { -- cgit v1.2.3 From 547141b56c6cdc34727917d4ddd315321640f6df Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Sun, 19 Jul 2020 10:31:29 +0530 Subject: arm64: tegra: Enable ACONNECT, ADMA and AGIC on Jetson Nano These devices are required for audio sub system and current patch ensures probe path of these devices gets tested. Later sound card support would be added which can use these devices at runtime. Signed-off-by: Sameer Pujar Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index c55716c336c1..ba892cd4b5a9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -624,6 +624,18 @@ pinctrl-1 = <&dvfs_pwm_inactive_state>; }; + aconnect@702c0000 { + status = "okay"; + + dma@702e2000 { + status = "okay"; + }; + + interrupt-controller@702f9000 { + status = "okay"; + }; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; -- cgit v1.2.3 From 177208f7b06d1669514cc465268c8432f577b7fd Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Sun, 19 Jul 2020 10:31:30 +0530 Subject: arm64: tegra: Add DT binding for AHUB components This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194. Bindings for following modules are added. * AHUB added as a child node under ACONNECT * AHUB includes many HW accelerators and below components are added as its children. * ADMAIF * I2S * DMIC * DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does not have this module) Signed-off-by: Sameer Pujar Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 217 ++++++++++++++++++++++++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 225 ++++++++++++++++++++++++++++++- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 140 +++++++++++++++++++ 3 files changed, 580 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 34d249d85da7..7869aeccee1a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -85,7 +85,7 @@ ranges = <0x02900000 0x0 0x02900000 0x200000>; status = "disabled"; - dma-controller@2930000 { + adma: dma-controller@2930000 { compatible = "nvidia,tegra186-adma"; reg = <0x02930000 0x20000>; interrupt-parent = <&agic>; @@ -140,6 +140,221 @@ clock-names = "clk"; status = "disabled"; }; + + tegra_ahub: ahub@2900800 { + compatible = "nvidia,tegra186-ahub"; + reg = <0x02900800 0x800>; + clocks = <&bpmp TEGRA186_CLK_AHUB>; + clock-names = "ahub"; + assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900800 0x02900800 0x11800>; + status = "disabled"; + + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + }; + + tegra_i2s1: i2s@2901000 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901000 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S1>, + <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + }; + + tegra_i2s2: i2s@2901100 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901100 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S2>, + <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + }; + + tegra_i2s3: i2s@2901200 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901200 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S3>, + <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + }; + + tegra_i2s4: i2s@2901300 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901300 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S4>, + <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + }; + + tegra_i2s5: i2s@2901400 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901400 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S5>, + <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + }; + + tegra_i2s6: i2s@2901500 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901500 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S6>, + <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S6"; + status = "disabled"; + }; + + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + }; }; mc: memory-controller@2c00000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 421b9e0883d9..311c1c86d9b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -83,7 +83,7 @@ ranges = <0x02900000 0x02900000 0x200000>; status = "disabled"; - dma-controller@2930000 { + adma: dma-controller@2930000 { compatible = "nvidia,tegra194-adma", "nvidia,tegra186-adma"; reg = <0x02930000 0x20000>; @@ -140,6 +140,229 @@ clock-names = "clk"; status = "disabled"; }; + + tegra_ahub: ahub@2900800 { + compatible = "nvidia,tegra194-ahub", + "nvidia,tegra186-ahub"; + reg = <0x02900800 0x800>; + clocks = <&bpmp TEGRA194_CLK_AHUB>; + clock-names = "ahub"; + assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900800 0x02900800 0x11800>; + status = "disabled"; + + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra194-admaif", + "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + }; + + tegra_i2s1: i2s@2901000 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901000 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S1>, + <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + }; + + tegra_i2s2: i2s@2901100 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901100 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S2>, + <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + }; + + tegra_i2s3: i2s@2901200 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901200 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S3>, + <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + }; + + tegra_i2s4: i2s@2901300 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901300 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S4>, + <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + }; + + tegra_i2s5: i2s@2901400 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901400 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S5>, + <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + }; + + tegra_i2s6: i2s@2901500 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901500 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S6>, + <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S6"; + status = "disabled"; + }; + + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra194-dspk", + "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA194_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra194-dspk", + "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA194_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + }; }; pinmux: pinmux@2430000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 27d4e3f134ca..0b288308ef8b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1383,6 +1383,146 @@ clock-names = "clk"; status = "disabled"; }; + + tegra_ahub: ahub@702d0800 { + compatible = "nvidia,tegra210-ahub"; + reg = <0x702d0800 0x800>; + clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; + clock-names = "ahub"; + assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x702d0000 0x702d0000 0x0000e400>; + status = "disabled"; + + tegra_admaif: admaif@702d0000 { + compatible = "nvidia,tegra210-admaif"; + reg = <0x702d0000 0x800>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10"; + status = "disabled"; + }; + + tegra_i2s1: i2s@702d1000 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1000 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S0>, + <&tegra_car TEGRA210_CLK_I2S0_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + }; + + tegra_i2s2: i2s@702d1100 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1100 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S1>, + <&tegra_car TEGRA210_CLK_I2S1_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + }; + + tegra_i2s3: i2s@702d1200 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1200 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S2>, + <&tegra_car TEGRA210_CLK_I2S2_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + }; + + tegra_i2s4: i2s@702d1300 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1300 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S3>, + <&tegra_car TEGRA210_CLK_I2S3_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + }; + + tegra_i2s5: i2s@702d1400 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1400 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S4>, + <&tegra_car TEGRA210_CLK_I2S4_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + }; + + tegra_dmic1: dmic@702d4000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4000 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@702d4100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4100 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@702d4200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4200 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + }; }; spi@70410000 { -- cgit v1.2.3 From de653d045636091100efcbe5c83f78ebb5211ff4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Aug 2020 19:25:32 +0200 Subject: ARM: dts: exynos: Remove snps, dwc2 compatible in Exynos3250 The binding for DesignWare HS OTG USB 2.0 in Samsung SoCs take only one compatible. This fixes dtbs_check warnings like: arch/arm/boot/dts/exynos3250-artik5-eval.dt.yaml: hsotg@12480000: compatible: ['samsung,s3c6400-hsotg', 'snps,dwc2'] is not valid under any of the given schemas (Possible causes of the failure): Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200829172532.29358-4-krzk@kernel.org --- arch/arm/boot/dts/exynos3250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index c67c70e46794..a1e93fb7f694 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -354,7 +354,7 @@ }; hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg", "snps,dwc2"; + compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; interrupts = ; clocks = <&cmu CLK_USBOTG>; -- cgit v1.2.3 From df63dce2d60b354ca6755708223d6e3b24c8af6c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:28 +0200 Subject: ARM: dts: exynos: Silence i2c-gpio dtschema warning in Galaxy I9100 The name of I2C controller over GPIO lines node ends with '-gpio' which confuses dtschema: /arch/arm/boot/dts/exynos4210-i9100.dt.yaml: /: i2c-gpio: {'compatible': ['i2c-gpio'], ... 'maxim,over-volt': [[4500]]}} is not of type 'array' From schema: lib/python3.6/site-packages/dtschema/schemas/gpio/gpio-consumer.yaml Add a '-0' suffix to silence it. This pattern on naming i2c-gpio is already present in many other dts. No functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-1-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 6d0c04d77a39..3eb11cc2c3c5 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -123,7 +123,7 @@ reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; }; - i2c_max17042_fuel: i2c-gpio { + i2c_max17042_fuel: i2c-gpio-0 { compatible = "i2c-gpio"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 57d4449fd443ca3deb6e9d1842c998df36ec8162 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:29 +0200 Subject: ARM: dts: exynos: Correct GPU regulator properties in Galaxy I9100 The regulator property 'regulator-microvolt-offset' should be put next to regulator definition, not consumer. The property 'regulator-microsecs-delay' is not valid at all. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-2-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 3eb11cc2c3c5..6fa57d1fa1d7 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -304,8 +304,6 @@ status = "okay"; mali-supply = <&vg3d_breg>; - regulator-microvolt-offset = <50000>; - regulator-microsecs-delay = <50>; }; &hsotg { @@ -524,6 +522,7 @@ regulator-name = "G3D_1.1V"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1200000>; + regulator-microvolt-offset = <50000>; regulator-always-on; }; -- cgit v1.2.3 From 10c977cc029b031332501db051eee4965e3bb770 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:30 +0200 Subject: ARM: dts: exynos: Correct S3C RTC bindings and enable it in Galaxy I9100 The S3C RTC requires 32768 Hz clock as input which is provided by PMIC (Maxim MAX8997). However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround: 1. Enable the "clock" regulator in PMIC, 2. Add a fixed-clock to fill missing clock phandle reference in S3C RTC. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-i9100.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-i9100.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-3-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 6fa57d1fa1d7..d63274c8539d 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -209,6 +209,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; thermal-zones { @@ -568,6 +575,11 @@ regulator-max-microvolt = <4100000>; regulator-always-on; }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; }; }; }; @@ -688,6 +700,12 @@ }; }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_0 { status = "okay"; -- cgit v1.2.3 From 83d50121a09ab4c0836a3773a309757f777fef7e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:31 +0200 Subject: ARM: dts: exynos: Correct S3C RTC bindings and enable it in Origen The S3C RTC requires 32768 Hz clock as input which is provided by PMIC (Maxim MAX8997). However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround: 1. Enable the "clock" regulator in PMIC, 2. Add a fixed-clock to fill missing clock phandle reference in S3C RTC. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-origen.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-origen.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200830135200.24304-4-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-origen.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 890525b10d22..747221bbb856 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -100,6 +100,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; display-timings { @@ -286,6 +293,11 @@ regulator-boot-on; regulator-always-on; }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; }; }; }; @@ -331,6 +343,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &tmu { -- cgit v1.2.3 From 9ce975bf6b4b014c928392775c7957a65a81e365 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:32 +0200 Subject: ARM: dts: exynos: Correct S3C RTC bindings and enable it in Trats The S3C RTC requires 32768 Hz clock as input which is provided by PMIC (Maxim MAX8997). However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround: 1. Enable the "clock" regulator in PMIC, 2. Add a fixed-clock to fill missing clock phandle reference in S3C RTC. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-trats.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-trats.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200830135200.24304-5-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-trats.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 5cc96f04a4fa..634f009b622e 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -132,6 +132,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; thermal-zones { @@ -444,10 +451,21 @@ regulator-name = "SAFEOUT2"; regulator-boot-on; }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; }; }; }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_0 { bus-width = <8>; non-removable; -- cgit v1.2.3 From e416f0cabf0bcb329a824767e7a5d255979be961 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:33 +0200 Subject: ARM: dts: exynos: Correct S3C RTC bindings and enable it in Universal C210 The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround - add a fixed-clock to fill missing clock phandle reference in S3C RTC. The "clock" regulator in PMIC is already present and enabled. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-universal_c210.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-universal_c210.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200830135200.24304-6-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 99ce53b120ac..9479e41bdc2a 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -39,6 +39,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; vemmc_reg: voltage-regulator { @@ -537,6 +544,12 @@ status = "okay"; }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_0 { bus-width = <8>; non-removable; -- cgit v1.2.3 From eb7e538dceda761baae45e61c10be7d6694b3ce5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:34 +0200 Subject: ARM: dts: exynos: Correct S3C RTC bindings in SMDKv310 The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround - a fixed-clock to fill missing clock phandle reference in S3C RTC. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-smdkv310.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-smdkv310.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-7-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 77fc11e593ad..0b0e86737b26 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -40,6 +40,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; }; @@ -148,6 +155,11 @@ }; }; +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_2 { bus-width = <4>; pinctrl-names = "default"; -- cgit v1.2.3 From b9294408b9a316e60292583fe07271052ac093c0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:35 +0200 Subject: ARM: dts: exynos: Add and enable 32 kHz modem clock in Galaxy I9100 The PMIC has a 32768 Hz clock used by the modem which is implemented by driver as a regulator. Add and enable it to be sure modem get's its signal. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-8-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index d63274c8539d..1d200a5e1b72 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -580,6 +580,11 @@ regulator-name = "EN32KHZ_AP"; regulator-always-on; }; + + EN32KHZ_CP { + regulator-name = "EN32KHZ_CP"; + regulator-always-on; + }; }; }; }; -- cgit v1.2.3 From 8bdca79f584dd7912cf41b7c2497f70ee0ff449f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:37 +0200 Subject: ARM: dts: exynos: Add and enable 32 kHz modem clock in Trats The PMIC has a 32768 Hz clock used by the modem which is implemented by driver as a regulator. Add and enable it to be sure modem get's its signal. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-10-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-trats.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 634f009b622e..0f3af293d9d3 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -456,6 +456,11 @@ regulator-name = "EN32KHZ_AP"; regulator-always-on; }; + + EN32KHZ_CP { + regulator-name = "EN32KHZ_CP"; + regulator-always-on; + }; }; }; }; -- cgit v1.2.3 From 64fb61e11fa28b6fd69904d054fcf08be54a0856 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:40 +0200 Subject: ARM: dts: exynos: Align SPI GPIO node name with dtschema in Universal C210 The device tree schema expects SPI controller to be named "spi", otherwise dtbs_check complain with a warning like: arch/arm/boot/dts/exynos4210-universal_c210.dt.yaml: spi-lcd: $nodename:0: 'spi-lcd' does not match '^spi(@.*|-[0-9a-f])*$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-13-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 9479e41bdc2a..93a28c70be84 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -119,7 +119,7 @@ enable-active-high; }; - spi-lcd { + spi-3 { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From f11d702242a3c91c9a9b0fa9ad6eb6d0f7218c51 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:41 +0200 Subject: ARM: dts: exynos: Replace deprecated GPIO spi-gpio properties in Universal C210 "gpio-sck" and "gpio-mosi" are deprecated so update the DTS to fix dtbs_checks warnings like: arch/arm/boot/dts/exynos4210-universal_c210.dt.yaml: spi-lcd: gpio-sck: False schema does not allow [[85, 1, 0]] Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200830135200.24304-14-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 93a28c70be84..3d596c6260b1 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -124,8 +124,8 @@ #address-cells = <1>; #size-cells = <0>; - gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From a51e695cafc74700586f7b6fc9953707d2ff24e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:42 +0200 Subject: ARM: dts: exynos: Align SPI GPIO node name with dtschema in Galaxy I9100 The device tree schema expects SPI controller to be named "spi", otherwise dtbs_check complain with a warning like: arch/arm/boot/dts/exynos4210-i9100.dt.yaml: spi-lcd: $nodename:0: 'spi-lcd' does not match '^spi(@.*|-[0-9a-f])*$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-15-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 1d200a5e1b72..5623e17889a5 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -147,7 +147,7 @@ }; }; - spi-lcd { + spi-3 { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 1708f56081e239a29ed8646aa7fde6853235d93f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:43 +0200 Subject: ARM: dts: exynos: Override thermal by label in Exynos4210 Using full paths to extend or override a device tree node is error prone since if there was a typo error, a new node will be created instead of extending the node as it was desired. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-16-krzk@kernel.org --- arch/arm/boot/dts/exynos4210.dtsi | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 73360f29d53e..fddc661ded28 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -365,26 +365,24 @@ }; }; }; +}; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert0: cpu-alert-0 { - temperature = <85000>; /* millicelsius */ - }; - cpu_alert1: cpu-alert-1 { - temperature = <100000>; /* millicelsius */ - }; - cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - }; - }; - }; - }; +&cpu_alert0 { + temperature = <85000>; /* millicelsius */ +}; + +&cpu_alert1 { + temperature = <100000>; /* millicelsius */ +}; + +&cpu_alert2 { + temperature = <110000>; /* millicelsius */ +}; + +&cpu_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu 0>; }; &gic { -- cgit v1.2.3 From ed32017c73449b3f5892d69d5ddbbe425b433660 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:44 +0200 Subject: ARM: dts: exynos: Override thermal by label in Galaxy I9000 Using full paths to extend or override a device tree node is error prone since if there was a typo error, a new node will be created instead of extending the node as it was desired. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-17-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 5623e17889a5..799b69e1a93a 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -217,21 +217,6 @@ clock-frequency = <32768>; }; }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz */ - cooling-device = <&cpu0 2 2>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 4 4>; - }; - }; - }; - }; }; &camera { @@ -242,6 +227,19 @@ cpu0-supply = <&varm_breg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + &ehci { status = "okay"; -- cgit v1.2.3 From 03ebf390c4e9b70a0802ebfc8d2cfe24ad43ae7a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:45 +0200 Subject: ARM: dts: exynos: Override thermal by label in Trats Using full paths to extend or override a device tree node is error prone since if there was a typo error, a new node will be created instead of extending the node as it was desired. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-18-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-trats.dts | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 0f3af293d9d3..12bfd4428c90 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -140,22 +140,6 @@ clock-frequency = <32768>; }; }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; - }; - }; - }; - }; - }; &camera { @@ -168,6 +152,19 @@ cpu0-supply = <&varm_breg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; + }; + }; +}; + &dsi_0 { vddcore-supply = <&vusb_reg>; vddio-supply = <&vmipi_reg>; -- cgit v1.2.3 From 5d2bb6621caa66f6912f91b4565ee945aea20258 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:46 +0200 Subject: ARM: dts: exynos: Add CPU cooling in Exynos4210 Origen Add missing cooling devices for CPU thermal zones in Exynos4210 Origen board. This allows to scale down CPU frequency (and voltage) in case of thermal pressure. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-19-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-origen.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 747221bbb856..7d2cfbafefb2 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -129,6 +129,19 @@ cpu0-supply = <&buck1_reg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + &exynos_usbphy { status = "okay"; }; -- cgit v1.2.3 From bd031c725d7499b6c77be554c6b4a7cb79f1b765 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:47 +0200 Subject: ARM: dts: exynos: Add CPU cooling in SMDKv310 Add missing cooling devices for CPU thermal zones in Exynos4210 SMDKv310 board. This allows to scale down CPU frequency (and voltage) in case of thermal pressure. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-20-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-smdkv310.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 0b0e86737b26..c5609afa6101 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -50,6 +50,19 @@ }; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + &i2c_0 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 9102399b7fd63e4bd44e48e89d35784031844bb6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:48 +0200 Subject: ARM: dts: exynos: Add CPU cooling in Universal C210 Add missing cooling devices for CPU thermal zones in Exynos4210 Universal C310 board. This allows to scale down CPU frequency (and voltage) in case of thermal pressure. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-21-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 3d596c6260b1..d1edadb73580 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -199,6 +199,19 @@ cpu0-supply = <&vdd_arm_reg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + &ehci { status = "okay"; phys = <&exynos_usbphy 1>; -- cgit v1.2.3 From 2b857a10d544c8471dabfef7e862840c52b8bf66 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:49 +0200 Subject: ARM: dts: exynos: Align MHL GPIO pin configuration with dtschema on Galaxy I9100 Align the name of mag-mhl-gpio node to avoid dtschema confusion and dtbs_check warning: arch/arm/boot/dts/exynos4210-i9100.dt.yaml: pinctrl@11000000: mag-mhl-gpio: {'samsung,pins': ['gpd0-2'], 'samsung,pin-function': [[3]], 'samsung,pin-pud': [[0]]} is not of type 'array' From schema: dtschema/schemas/gpio/gpio-consumer.yaml Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-22-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 799b69e1a93a..5370ee477186 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -681,7 +681,7 @@ samsung,pin-val = <0>; }; - mag_mhl_gpio: mag-mhl-gpio { + mag_mhl_gpio: mag-mhl { samsung,pins = "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; -- cgit v1.2.3 From a26fe748716e3055d4ce9be698cf44248819aa85 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:51 +0200 Subject: ARM: dts: exynos: Correct compatible of fixed clocks in Midas boards The fixed clocks implemented by Samsung clock drivers use only one compatible so drop the additional "fixed-clock" to fix dtbs_check warnings like: arch/arm/boot/dts/exynos4412-i9300.dt.yaml: xxti: compatible:0: 'fixed-clock' was expected From schema: Documentation/devicetree/bindings/clock/fixed-clock.yaml arch/arm/boot/dts/exynos4412-i9300.dt.yaml: xxti: compatible: ['samsung,clock-xxti', 'fixed-clock'] is too long arch/arm/boot/dts/exynos4412-i9300.dt.yaml: xxti: compatible: Additional items are not allowed ('fixed-clock' was unexpected) arch/arm/boot/dts/exynos4412-i9300.dt.yaml: xxti: '#clock-cells' is a required property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-24-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-midas.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 8e7a03228d7b..32d2e539b2dd 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -37,12 +37,12 @@ fixed-rate-clocks { xxti { - compatible = "samsung,clock-xxti", "fixed-clock"; + compatible = "samsung,clock-xxti"; clock-frequency = <0>; }; xusbxti { - compatible = "samsung,clock-xusbxti", "fixed-clock"; + compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; }; -- cgit v1.2.3 From eeb62f3d1d33f8b6ccb889d8cf9376cc72cab7b0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:52 +0200 Subject: ARM: dts: exynos: Add S5M8767 clocks for RTC in Exynos4412 Origen Add node for clock controller of Samsung S5M8767 PMIC. This provides the 32768 Hz clock required by S3C RTC. Except making the S3C RTC working, this also fixes dtbs_check warnings: arch/arm/boot/dts/exynos4412-origen.dt.yaml: rtc@10070000: clocks: [[7, 346]] is too short arch/arm/boot/dts/exynos4412-origen.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-25-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-origen.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 8b11ad391252..4c52ca6dbe57 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "exynos4412.dtsi" +#include #include #include #include "exynos-mfc-reserved-memory.dtsi" @@ -129,6 +130,13 @@ <1200000>, <1200000>, <1200000>, <1200000>; + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "s5m8767_ap", "s5m8767_cp", + "s5m8767_bt"; + }; + regulators { ldo1_reg: LDO1 { regulator-name = "VDD_ALIVE"; @@ -499,6 +507,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; &sdhci_2 { -- cgit v1.2.3 From e4cf0a4dba7f0bd579dc96f24d8e6134995005c5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:53 +0200 Subject: ARM: dts: exynos: Override thermal by label in Midas Using full paths to extend or override a device tree node is error prone since if there was a typo error, a new node will be created instead of extending the node as it was desired. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-26-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-midas.dtsi | 34 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 32d2e539b2dd..7e7c243ff196 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -319,25 +319,6 @@ pulldown-ohm = <100000>; /* 100K */ io-channels = <&adc 2>; /* Battery temperature */ }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, - <&cpu1 13 13>, - <&cpu2 13 13>, - <&cpu3 13 13>; - }; - }; - }; - }; }; &adc { @@ -406,6 +387,21 @@ cpu0-supply = <&buck2_reg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &csis_0 { status = "okay"; vddcore-supply = <&ldo8_reg>; -- cgit v1.2.3 From 1f2448dcb9a28b658de08128dc3f38bd1a2ab980 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:54 +0200 Subject: ARM: dts: exynos: Override thermal by label in Exynos4412 Odroids Using full paths to extend or override a device tree node is error prone since if there was a typo error, a new node will be created instead of extending the node as it was desired. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-27-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 34 ++++++++---------- arch/arm/boot/dts/exynos4412-odroidu3.dts | 46 +++++++++++-------------- 2 files changed, 36 insertions(+), 44 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index a5c1ce1e396c..2983e91bc7dd 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -66,25 +66,6 @@ clock-frequency = <24000000>; }; }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - cooling_map0: map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - cooling_map1: map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, - <&cpu1 13 13>, - <&cpu2 13 13>, - <&cpu3 13 13>; - }; - }; - }; - }; }; &bus_dmc { @@ -174,6 +155,21 @@ }; }; +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 8ff243ba4542..b8549d846f86 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -37,31 +37,6 @@ #cooling-cells = <2>; cooling-levels = <0 102 170 230>; }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, - <&cpu2 9 9>, <&cpu3 9 9>, - <&fan0 1 2>; - }; - map1 { - trip = <&cpu_alert2>; - cooling-device = <&cpu0 15 15>, - <&cpu1 15 15>, - <&cpu2 15 15>, - <&cpu3 15 15>, - <&fan0 2 3>; - }; - map2 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - }; - }; - }; }; &adc { @@ -76,6 +51,27 @@ regulator-max-microvolt = <3300000>; }; +&cpu_thermal { + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, + <&cpu2 9 9>, <&cpu3 9 9>, + <&fan0 1 2>; + }; + map1 { + trip = <&cpu_alert2>; + cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, + <&cpu2 15 15>, <&cpu3 15 15>, + <&fan0 2 3>; + }; + map2 { + trip = <&cpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + }; +}; + &hdmicec { needs-hpd; }; -- cgit v1.2.3 From ffed15b889a4d8cfb8c324e238bf308757b1995b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:55 +0200 Subject: ARM: dts: exynos: Add CPU cooling in Exynos4412 Origen Add missing cooling devices for CPU thermal zones in Exynos4412 Origen board. This allows to scale down CPU frequency (and voltage) in case of thermal pressure. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-28-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-origen.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 4c52ca6dbe57..c2e793b69e7d 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -75,6 +75,21 @@ cpu0-supply = <&buck2_reg>; }; +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &exynos_usbphy { status = "okay"; }; -- cgit v1.2.3 From 4134628c38dad06ef69b79fac33fc3d04b81f78e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:56 +0200 Subject: ARM: dts: exynos: Add CPU cooling in SMDK4412 Add missing cooling devices for CPU thermal zones in Exynos4412 SMDK4412 board. This allows to scale down CPU frequency (and voltage) in case of thermal pressure. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-29-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-smdk4412.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index e70fb6e601f0..3667fa048e0f 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -40,6 +40,21 @@ }; }; +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &keypad { samsung,keypad-num-rows = <3>; samsung,keypad-num-columns = <8>; -- cgit v1.2.3 From 173ab0310fb44b73093b7aed9a9e6c4916bc059d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:57 +0200 Subject: ARM: dts: exynos: Add CPU cooling in Tiny4412 Add missing cooling devices for CPU thermal zones in Exynos4412 Tiny4412 board. This allows to scale down CPU frequency (and voltage) in case of thermal pressure. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-30-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-tiny4412.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 3a91de8a8082..7512c86e634e 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -78,6 +78,21 @@ }; }; +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &fimd { pinctrl-0 = <&lcd_clk>, <&lcd_data24>; pinctrl-names = "default"; -- cgit v1.2.3 From 1716af24998a27f9509791e07d3dcef00538e4c2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:58 +0200 Subject: ARM: dts: exynos: Correct S3C RTC bindings in SMDK4412 The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However the PMIC is not described in DTS at all so at least add a workaround to model its clock with fixed-clock and silence dtbs_check warnings like: arch/arm/boot/dts/exynos4412-smdk4412.dt.yaml: rtc@10070000: clocks: [[7, 346]] is too short arch/arm/boot/dts/exynos4412-smdk4412.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-31-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 3667fa048e0f..49971203a8aa 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -37,6 +37,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; }; @@ -142,6 +149,11 @@ }; }; +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_2 { bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; -- cgit v1.2.3 From 6511f11a49825a3ef0fc6529bee84716d58f3c4d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:51:59 +0200 Subject: ARM: dts: exynos: Correct S3C RTC bindings in Tiny4412 The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However the PMIC is not described in DTS at all so at least add a workaround to model its clock with fixed-clock. This fixes S3C RTC and silences dtbs_check warnings like: arch/arm/boot/dts/exynos4412-tiny4412.dt.yaml: rtc@10070000: clocks: [[7, 346]] is too short arch/arm/boot/dts/exynos4412-tiny4412.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-32-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-tiny4412.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 7512c86e634e..017b26108bb0 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -65,6 +65,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; panel { @@ -110,6 +117,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &sdhci_2 { -- cgit v1.2.3 From a6b5a1977c6b42dd1b9830f3f6eddc10409d82a1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Aug 2020 15:52:00 +0200 Subject: ARM: dts: exynos: Correct whitespace and indentation issues Remove double space after '=' and fix indentation in Exynos3250, Exynos4210 and Exynos4412 boards. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200830135200.24304-33-krzk@kernel.org --- arch/arm/boot/dts/exynos3250-monk.dts | 2 +- arch/arm/boot/dts/exynos3250-rinato.dts | 2 +- arch/arm/boot/dts/exynos4210-trats.dts | 138 ++++++++++++------------ arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 +- arch/arm/boot/dts/exynos4412-i9300.dts | 2 +- arch/arm/boot/dts/exynos4412-i9305.dts | 2 +- arch/arm/boot/dts/exynos4412-n710x.dts | 2 +- arch/arm/boot/dts/exynos4412-trats2.dts | 2 +- 8 files changed, 77 insertions(+), 77 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index ca29d7ed8216..9d77a73bc92b 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -26,7 +26,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x1ff00000>; + reg = <0x40000000 0x1ff00000>; }; firmware@205f000 { diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index aba8350cfdaf..3df003af0d15 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -30,7 +30,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x1ff00000>; + reg = <0x40000000 0x1ff00000>; }; firmware@205f000 { diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 12bfd4428c90..a226bec56a45 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -318,135 +318,135 @@ regulators { valive_reg: LDO2 { - regulator-name = "VALIVE_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; }; vusb_reg: LDO3 { - regulator-name = "VUSB_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; }; vmipi_reg: LDO4 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; vpda_reg: LDO6 { - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; vcam_reg: LDO7 { - regulator-name = "CAM_ISP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; vusbdac_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V_C210"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "VUSB+VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; vccpda_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; }; vpll_reg: LDO10 { - regulator-name = "VPLL_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; + regulator-name = "VPLL_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; }; vtcam_reg: LDO12 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; vcclcd_reg: LDO13 { - regulator-name = "VCC_3.3V_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "VCC_3.3V_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; vlcd_reg: LDO15 { - regulator-name = "VLCD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; + regulator-name = "VLCD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; }; camsensor_reg: LDO16 { - regulator-name = "CAM_SENSOR_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; tflash_reg: LDO17 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; }; vddq_reg: LDO21 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; }; varm_breg: BUCK1 { - regulator-name = "VARM_1.2V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; }; vint_breg: BUCK2 { - regulator-name = "VINT_1.1V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; }; camisp_breg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; }; vmem_breg: BUCK5 { - regulator-name = "VMEM_1.2V_C210"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; + regulator-name = "VMEM_1.2V_C210"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; }; vccsub_breg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; }; safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; + regulator-name = "SAFEOUT1"; }; safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; + regulator-name = "SAFEOUT2"; + regulator-boot-on; }; EN32KHZ_AP { diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d1edadb73580..08284e8f3624 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -49,7 +49,7 @@ }; vemmc_reg: voltage-regulator { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "VMEM_VDD_2_8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -111,7 +111,7 @@ }; tsp_reg: voltage-regulator { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "TSP_2_8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/exynos4412-i9300.dts index 3691802b69c5..07fbcf845c49 100644 --- a/arch/arm/boot/dts/exynos4412-i9300.dts +++ b/arch/arm/boot/dts/exynos4412-i9300.dts @@ -17,7 +17,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-i9305.dts b/arch/arm/boot/dts/exynos4412-i9305.dts index 54a2a55dbf70..6bc3d897f432 100644 --- a/arch/arm/boot/dts/exynos4412-i9305.dts +++ b/arch/arm/boot/dts/exynos4412-i9305.dts @@ -10,7 +10,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index 2361d89a79a8..a47b7f35fc80 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -8,7 +8,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x80000000>; }; /* bootargs are passed in by bootloader */ diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index aac533933c61..7b447b63007e 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -18,7 +18,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; }; chosen { -- cgit v1.2.3 From cd972fe90008adf49de0790250c1275480ac5cdc Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Tue, 1 Sep 2020 17:38:58 -0700 Subject: ARM: dts: s5pv210: Enable audio on Aries boards Both the Galaxy S and the Fascinate4G have a WM8994 codec, but they differ slightly in their jack detection and micbias configuration. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 10 ++++ arch/arm/boot/dts/s5pv210-fascinate4g.dts | 98 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/s5pv210-galaxys.dts | 85 +++++++++++++++++++++++++++ 3 files changed, 193 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 822207f63ee0..a3f83f668ce1 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -47,6 +47,11 @@ }; }; + bt_codec: bt_sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <0>; + }; + vibrator_pwr: regulator-fixed-0 { compatible = "regulator-fixed"; regulator-name = "vibrator-en"; @@ -624,6 +629,11 @@ }; }; +&i2s0 { + dmas = <&pdma0 9>, <&pdma0 10>, <&pdma0 11>; + status = "okay"; +}; + &mfc { memory-region = <&mfc_left>, <&mfc_right>; }; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index 65eed01cfced..ca064359dd30 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -35,6 +35,80 @@ linux,code = ; }; }; + + headset_micbias_reg: regulator-fixed-3 { + compatible = "regulator-fixed"; + regulator-name = "Headset_Micbias"; + gpio = <&gpj2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_micbias_ena>; + }; + + main_micbias_reg: regulator-fixed-4 { + compatible = "regulator-fixed"; + regulator-name = "Main_Micbias"; + gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&main_micbias_ena>; + }; + + sound { + compatible = "samsung,fascinate4g-wm8994"; + + model = "Fascinate4G"; + + extcon = <&fsa9480>; + + main-micbias-supply = <&main_micbias_reg>; + headset-micbias-supply = <&headset_micbias_reg>; + + earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; + + io-channels = <&adc 3>; + io-channel-names = "headset-detect"; + headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_HIGH>; + headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; + + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "Main Mic", + "IN1LN", "Main Mic", + + "IN1RP", "Headset Mic", + "IN1RN", "Headset Mic", + + "Modem Out", "Modem TX", + "Modem RX", "Modem In", + + "Bluetooth SPK", "TX", + "RX", "Bluetooth Mic"; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_det &earpath_sel>; + + cpu { + sound-dai = <&i2s0>, <&bt_codec>; + }; + + codec { + sound-dai = <&wm8994>; + }; + }; }; &fg { @@ -51,6 +125,12 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep_cfg>; + headset_det: headset-det { + samsung,pins = "gph0-6", "gph3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + fg_irq: fg-irq { samsung,pins = "gph3-3"; samsung,pin-function = ; @@ -58,6 +138,24 @@ samsung,pin-drv = ; }; + headset_micbias_ena: headset-micbias-ena { + samsung,pins = "gpj2-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + earpath_sel: earpath-sel { + samsung,pins = "gpj2-6"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + main_micbias_ena: main-micbias-ena { + samsung,pins = "gpj4-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + /* Based on vendor kernel v2.6.35.7 */ sleep_cfg: sleep-cfg { PIN_SLP(gpa0-0, PREV, NONE); diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index 5d10dd67eacc..560f830b6f6b 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -72,6 +72,73 @@ pinctrl-0 = <&fm_irq &fm_rst>; }; }; + + micbias_reg: regulator-fixed-3 { + compatible = "regulator-fixed"; + regulator-name = "MICBIAS"; + gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&micbias_reg_ena>; + }; + + sound { + compatible = "samsung,aries-wm8994"; + + model = "Aries"; + + extcon = <&fsa9480>; + + main-micbias-supply = <&micbias_reg>; + headset-micbias-supply = <&micbias_reg>; + + earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; + + io-channels = <&adc 3>; + io-channel-names = "headset-detect"; + headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_LOW>; + headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; + + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "Main Mic", + "IN1LN", "Main Mic", + + "IN1RP", "Headset Mic", + "IN1RN", "Headset Mic", + + "IN2LN", "FM In", + "IN2RN", "FM In", + + "Modem Out", "Modem TX", + "Modem RX", "Modem In", + + "Bluetooth SPK", "TX", + "RX", "Bluetooth Mic"; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_det &earpath_sel>; + + cpu { + sound-dai = <&i2s0>, <&bt_codec>; + }; + + codec { + sound-dai = <&wm8994>; + }; + }; }; &aliases { @@ -88,6 +155,12 @@ samsung,pin-drv = ; }; + headset_det: headset-det { + samsung,pins = "gph0-6", "gph3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + fm_irq: fm-irq { samsung,pins = "gpj2-4"; samsung,pin-function = ; @@ -102,6 +175,12 @@ samsung,pin-drv = ; }; + earpath_sel: earpath-sel { + samsung,pins = "gpj2-6"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + massmemory_en: massmemory-en { samsung,pins = "gpj2-7"; samsung,pin-function = ; @@ -109,6 +188,12 @@ samsung,pin-drv = ; }; + micbias_reg_ena: micbias-reg-ena { + samsung,pins = "gpj4-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + /* Based on CyanogenMod 3.0.101 kernel */ sleep_cfg: sleep-cfg { PIN_SLP(gpa0-0, PREV, NONE); -- cgit v1.2.3 From 58f984941d4524018ac0634c1e101bc6bbd4d257 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 31 Aug 2020 19:11:23 +0200 Subject: ARM: dts: at91: fix cpu node The reg property is mandatory for cpu nodes, also fix the #address-cells of the cpus node that has to be at least 1. Signed-off-by: Alexandre Belloni Reviewed-by: Nicolas Ferre Link: https://lore.kernel.org/r/20200831171129.3886857-2-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/at91rm9200.dtsi | 5 +++-- arch/arm/boot/dts/at91sam9260.dtsi | 5 +++-- arch/arm/boot/dts/at91sam9261.dtsi | 5 +++-- arch/arm/boot/dts/at91sam9263.dtsi | 5 +++-- arch/arm/boot/dts/at91sam9g45.dtsi | 5 +++-- arch/arm/boot/dts/at91sam9n12.dtsi | 5 +++-- arch/arm/boot/dts/at91sam9rl.dtsi | 5 +++-- arch/arm/boot/dts/at91sam9x5.dtsi | 5 +++-- arch/arm/boot/dts/sam9x60.dtsi | 5 +++-- 9 files changed, 27 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index a5040f5ea641..231313e4c926 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -39,12 +39,13 @@ ssc2 = &ssc2; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm920t"; device_type = "cpu"; + reg = <0>; }; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 6afbb48e7ff0..85041ad5e29a 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -36,12 +36,13 @@ ssc0 = &ssc0; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 5ed3d745ac86..bb6480afc6f6 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -33,12 +33,13 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 5c990cfae254..a94fa2ae482c 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -35,12 +35,13 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 1fbee2a7785f..8fe2dbd39040 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -41,12 +41,13 @@ pwm0 = &pwm0; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index a994d076dc7e..9e1dc0070193 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -37,12 +37,13 @@ pwm0 = &pwm0; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 4d70194fd808..b737f21f1b4c 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -38,12 +38,13 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 948fe99ab6c3..442d3b8cda69 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -39,12 +39,13 @@ pwm0 = &pwm0; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index d10843da4a85..3a9fa40b2b1c 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -32,12 +32,13 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; -- cgit v1.2.3 From cd6228b782ae16566abb94022660568cbb0be76a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 31 Aug 2020 19:11:25 +0200 Subject: ARM: dts: at91: fix sram nodes The ranges, #address-cells and #size-cells properties are mandatory, add them to the sram nodes. Signed-off-by: Alexandre Belloni Reviewed-by: Nicolas Ferre Link: https://lore.kernel.org/r/20200831171129.3886857-4-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/at91rm9200.dtsi | 3 +++ arch/arm/boot/dts/at91sam9260.dtsi | 3 +++ arch/arm/boot/dts/at91sam9261.dtsi | 3 +++ arch/arm/boot/dts/at91sam9263.dtsi | 6 ++++++ arch/arm/boot/dts/at91sam9g20.dtsi | 3 +++ arch/arm/boot/dts/at91sam9g45.dtsi | 3 +++ arch/arm/boot/dts/at91sam9n12.dtsi | 3 +++ arch/arm/boot/dts/at91sam9rl.dtsi | 3 +++ arch/arm/boot/dts/at91sam9x5.dtsi | 3 +++ arch/arm/boot/dts/at91sam9xe.dtsi | 3 +++ arch/arm/boot/dts/sam9x60.dtsi | 3 +++ arch/arm/boot/dts/sama5d2.dtsi | 7 +++++++ arch/arm/boot/dts/sama5d3.dtsi | 6 ++++++ arch/arm/boot/dts/sama5d4.dtsi | 6 ++++++ 14 files changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 231313e4c926..1724e14d9994 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -71,6 +71,9 @@ sram: sram@200000 { compatible = "mmio-sram"; reg = <0x00200000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00200000 0x4000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 85041ad5e29a..f6ac5346f910 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -74,6 +74,9 @@ sram0: sram@2ff000 { compatible = "mmio-sram"; reg = <0x002ff000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x002ff000 0x2000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index bb6480afc6f6..980cc308fec5 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -65,6 +65,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x28000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x28000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index a94fa2ae482c..a321c68be64f 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -67,11 +67,17 @@ sram0: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x14000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x14000>; }; sram1: sram@500000 { compatible = "mmio-sram"; reg = <0x00500000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00500000 0x4000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 4117cf880508..86b4e943089a 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -22,6 +22,9 @@ sram1: sram@2fc000 { compatible = "mmio-sram"; reg = <0x002fc000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x002fc000 0x8000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 8fe2dbd39040..984b5292a129 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -79,6 +79,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x10000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 9e1dc0070193..5c27ead05284 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -69,6 +69,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x8000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index b737f21f1b4c..eb5bea473bc8 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -76,6 +76,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x10000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 442d3b8cda69..a5a1838c2524 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -77,6 +77,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x8000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi index 3f9d8caf8b0a..f571f77779c3 100644 --- a/arch/arm/boot/dts/at91sam9xe.dtsi +++ b/arch/arm/boot/dts/at91sam9xe.dtsi @@ -19,5 +19,8 @@ sram1: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x4000>; }; }; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 3a9fa40b2b1c..3e85c2a0d198 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -62,6 +62,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x100000>; }; ahb { diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index d7f25706892d..ddd7f9b05aa2 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -94,6 +94,9 @@ ns_sram: sram@200000 { compatible = "mmio-sram"; reg = <0x00200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00200000 0x20000>; }; ahb { @@ -106,6 +109,10 @@ compatible = "mmio-sram"; no-memory-wc; reg = <0x00100000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00100000 0x2400>; + }; usb0: gadget@300000 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 0bb5b6fa0748..4f9001188511 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -83,6 +83,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x20000>; }; ahb { @@ -1073,6 +1076,9 @@ compatible = "mmio-sram"; no-memory-wc; reg = <0x200000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x2400>; }; usb0: gadget@500000 { diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 2d9f853ab15f..1aca4b462f52 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -81,6 +81,9 @@ ns_sram: sram@210000 { compatible = "mmio-sram"; reg = <0x00210000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00210000 0x10000>; }; ahb { @@ -93,6 +96,9 @@ compatible = "mmio-sram"; no-memory-wc; reg = <0x100000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x100000 0x2400>; }; usb0: gadget@400000 { -- cgit v1.2.3 From dfe3a98aac4fd179cce67451bc0c3972bd8c6116 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:05 +0200 Subject: ARM: dts: exynos: Correct compatible for Exynos5 GIC Exynos5250 and Exynso54xx SoCs have ARM GIC 400. Correct the compatibles to match dtschema and fix the dtbs_check warnings like: arch/arm/boot/dts/exynos5420-peach-pit.dt.yaml: interrupt-controller@10481000: compatible: ['arm,gic-400', 'arm,cortex-a15-gic', 'arm,cortex-a9-gic'] is not valid under any of the given schemas Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-2-krzk@kernel.org --- arch/arm/boot/dts/exynos5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 22eb951c614c..9660104be4c9 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -86,7 +86,7 @@ }; gic: interrupt-controller@10481000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x10481000 0x1000>, -- cgit v1.2.3 From 1fa7c1ac2365fd53f891789138932380bdb4488c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:06 +0200 Subject: ARM: dts: exynos: Correct compatible for Exynos5260 GIC Exynos5260 SoCs have ARM GIC 400. Correct the compatibles to match dtschema and fix the dtbs_check warnings like: arch/arm/boot/dts/exynos5260-xyref5260.dt.yaml: interrupt-controller@10481000: compatible: ['arm,cortex-a15-gic', 'arm,cortex-a9-gic'] is not valid under any of the given schemas Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-3-krzk@kernel.org --- arch/arm/boot/dts/exynos5260.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 154df70128f3..9b45e052cca9 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -162,7 +162,7 @@ }; gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; #address-cells = <0>; #size-cells = <0>; -- cgit v1.2.3 From 2495ddd2d17c20573463ac9c90ae6a83b79d7aa9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:07 +0200 Subject: ARM: dts: exynos: Remove unneeded address/size cells in Exynos5260 GIC The Exynos5260 GIC node does not have any children so remove the address and size cells as they are not needed by DT bindings. The size-cells of '0' were also incorrect. This fixes dtbs_check warning: arch/arm/boot/dts/exynos5260-xyref5260.dt.yaml: interrupt-controller@10481000: #size-cells:0:0: 1 was expected Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-4-krzk@kernel.org --- arch/arm/boot/dts/exynos5260.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 9b45e052cca9..973448c4ad93 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -164,8 +164,6 @@ gic: interrupt-controller@10481000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; - #address-cells = <0>; - #size-cells = <0>; interrupt-controller; reg = <0x10481000 0x1000>, <0x10482000 0x2000>, -- cgit v1.2.3 From 8dec8385bee4f77e9d09a897a01cab8643c78a7d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:08 +0200 Subject: ARM: dts: exynos: Correct S3C RTC bindings in SMDK5410 The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However the PMIC is not described in DTS at all so at least add a workaround to model its clock with a fixed-clock. This fixes S3C RTC and silences dtbs_check warnings like: arch/arm/boot/dts/exynos5410-smdk5410.dt.yaml: rtc@101e0000: clocks: [[5, 317]] is too short arch/arm/boot/dts/exynos5410-smdk5410.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-5-krzk@kernel.org --- arch/arm/boot/dts/exynos5410-smdk5410.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 5282b5deca86..2a3ade77a2de 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -29,6 +29,13 @@ #clock-cells = <0>; }; + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + firmware@2037000 { compatible = "samsung,secure-firmware"; reg = <0x02037000 0x1000>; @@ -79,6 +86,11 @@ }; }; +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sromc { pinctrl-names = "default"; pinctrl-0 = <&srom_ctl>, <&srom_ebi>; -- cgit v1.2.3 From 41af0d2ea1b03282b9f6da8b610ac30768893518 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:09 +0200 Subject: ARM: dts: exynos: Silence i2c-gpio dtschema warning in Exynos5250 Arndale The name of I2C controller over GPIO lines node ends with '-gpio' which confuses dtschema: arch/arm/boot/dts/exynos5250-arndale.dt.yaml: soc: i2c-gpio: {'pinctrl-names': ['default'], ... 'phandle': [[65]]} is not of type 'array' From schema: lib/python3.6/site-packages/dtschema/schemas/gpio/gpio-consumer.yaml Add a '-10' (there are already 0-9 I2C controllers on the SoC) suffix to silence it. This pattern on naming i2c-gpio is already present in many other dts. No functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-6-krzk@kernel.org --- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 59872d83da6e..ec94af640cd5 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -624,7 +624,7 @@ * For unknown reasons HDMI-DDC does not work with Exynos I2C * controllers. Lets use software I2C over GPIO pins as a workaround. */ - i2c_ddc: i2c-gpio { + i2c_ddc: i2c-10 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_gpio_bus>; status = "okay"; -- cgit v1.2.3 From 9e7fe41778c6644fd8d5e43dc59daad8ad66e9a8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:10 +0200 Subject: ARM: dts: exynos: Correct whitespace and indentation issues in Exynos5 Remove double space after '=' and fix indentation in Exynos5250, Exynos5410 and Exynos5420 DTS files. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-7-krzk@kernel.org --- arch/arm/boot/dts/exynos5.dtsi | 8 +++---- arch/arm/boot/dts/exynos5250-arndale.dts | 10 ++++----- arch/arm/boot/dts/exynos5250-spring.dts | 30 +++++++++++++-------------- arch/arm/boot/dts/exynos5250.dtsi | 8 +++---- arch/arm/boot/dts/exynos5410-odroidxu.dts | 8 +++---- arch/arm/boot/dts/exynos5410.dtsi | 12 +++++------ arch/arm/boot/dts/exynos5420.dtsi | 16 +++++++------- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++-- 8 files changed, 48 insertions(+), 48 deletions(-) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 9660104be4c9..9ce9fb3fc190 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -211,13 +211,13 @@ }; prng: rng@10830400 { - compatible = "samsung,exynos5250-prng"; - reg = <0x10830400 0x200>; + compatible = "samsung,exynos5250-prng"; + reg = <0x10830400 0x200>; }; trng: rng@10830600 { - compatible = "samsung,exynos5250-trng"; - reg = <0x10830600 0x100>; + compatible = "samsung,exynos5250-trng"; + reg = <0x10830600 0x100>; }; g2d: g2d@10850000 { diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index ec94af640cd5..f2bcce167b2d 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -243,11 +243,11 @@ s5m8767,pmic-buck3-dvs-voltage = <1100000>; s5m8767,pmic-buck4-dvs-voltage = <1200000>; s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, - <&gpd1 1 GPIO_ACTIVE_HIGH>, - <&gpd1 2 GPIO_ACTIVE_HIGH>; + <&gpd1 1 GPIO_ACTIVE_HIGH>, + <&gpd1 2 GPIO_ACTIVE_HIGH>; s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, - <&gpx2 4 GPIO_ACTIVE_HIGH>, - <&gpx2 5 GPIO_ACTIVE_HIGH>; + <&gpx2 4 GPIO_ACTIVE_HIGH>, + <&gpx2 5 GPIO_ACTIVE_HIGH>; s5m8767_osc: clocks { compatible = "samsung,s5m8767-clk"; @@ -544,7 +544,7 @@ samsung,i2c-max-bus-freq = <40000>; samsung,i2c-slave-addr = <0x38>; - sata_phy_i2c:sata-phy@38 { + sata_phy_i2c: sata-phy@38 { compatible = "samsung,exynos-sataphy-i2c"; reg = <0x38>; }; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 3d501926c227..b6fcf847fc2f 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -114,12 +114,12 @@ wakeup-source; s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ - <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ - <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ + <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ + <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ - <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ - <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ + <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ + <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ /* * The following arrays of DVS voltages are not used, since we are @@ -127,26 +127,26 @@ * to please the driver. */ s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; clocks { compatible = "samsung,s5m8767-clk"; #clock-cells = <1>; clock-output-names = "en32khz_ap", - "en32khz_cp", - "en32khz_bt"; + "en32khz_cp", + "en32khz_bt"; }; regulators { diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index e3dbe4166836..0249d16e187f 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -723,7 +723,7 @@ #dma-requests = <1>; }; - gsc_0: gsc@13e00000 { + gsc_0: gsc@13e00000 { compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = ; @@ -733,7 +733,7 @@ iommus = <&sysmmu_gsc0>; }; - gsc_1: gsc@13e10000 { + gsc_1: gsc@13e10000 { compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = ; @@ -743,7 +743,7 @@ iommus = <&sysmmu_gsc1>; }; - gsc_2: gsc@13e20000 { + gsc_2: gsc@13e20000 { compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = ; @@ -753,7 +753,7 @@ iommus = <&sysmmu_gsc2>; }; - gsc_3: gsc@13e30000 { + gsc_3: gsc@13e30000 { compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 4f9297ae0763..75b4150c26d7 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -109,10 +109,10 @@ assigned-clock-parents = <&clock CLK_FOUT_EPLL>, <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <96000000>, - <19200000>; + assigned-clock-rates = <0>, + <0>, + <96000000>, + <19200000>; }; &cpu0_thermal { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index abe75b9e39f5..60a87684b1af 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -238,16 +238,16 @@ #include "exynos5420-trip-points.dtsi" }; cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" }; cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" }; cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" }; }; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c76460b70532..83580f076a58 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1199,20 +1199,20 @@ #include "exynos5420-trip-points.dtsi" }; cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" }; cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" }; cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" }; gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_gpu>; + #include "exynos5420-trip-points.dtsi" }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index afe090578e8f..b1cf9414ce17 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -333,8 +333,8 @@ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; tRFC-min-tck = <17>; tRRD-min-tck = <2>; -- cgit v1.2.3 From 7e86ef5cc89609cbad8b9dd2f476789c638dbb92 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:11 +0200 Subject: ARM: dts: exynos: Override thermal by label in Exynos5250 Using full paths to extend or override a device tree node is error prone since if there was a typo error, a new node will be created instead of extending the node as it was desired. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-8-krzk@kernel.org --- arch/arm/boot/dts/exynos5250.dtsi | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 0249d16e187f..488d3f9fab59 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -1085,26 +1085,6 @@ }; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; - - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 15 15>, - <&cpu1 15 15>; - }; - }; - }; - }; - timer { compatible = "arm,armv7-timer"; interrupts = , @@ -1120,6 +1100,24 @@ }; }; +&cpu_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu 0>; + + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 15 15>, + <&cpu1 15 15>; + }; + }; +}; + &dp { power-domains = <&pd_disp1>; clocks = <&clock CLK_DP>; -- cgit v1.2.3 From ac88a60a276b596ad4ba0b69806502f94f4c2be1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:12 +0200 Subject: ARM: dts: exynos: Add max77686 clocks for S3C RTC in SMDK5250 Add clock-cells to max77686 PMIC node so its 32 kHz clocks could be used later in the S3C RTC node. Except making the S3C RTC working, this also fixes dtbs_check warnings: arch/arm/boot/dts/exynos5250-smdk5250.dt.yaml: rtc@101e0000: clocks: [[2, 337]] is too short arch/arm/boot/dts/exynos5250-smdk5250.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-9-krzk@kernel.org --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 5c42df024adf..00af7fb65080 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -7,6 +7,7 @@ */ /dts-v1/; +#include #include #include #include "exynos5250.dtsi" @@ -129,13 +130,14 @@ reg = <0x50>; }; - max77686@9 { + max77686: pmic@9 { compatible = "maxim,max77686"; reg = <0x09>; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; + #clock-cells = <1>; wakeup-source; voltage-regulators { @@ -368,6 +370,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; &sata { -- cgit v1.2.3 From a2d86d420fa446913df2885a6db8abe559e067eb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:13 +0200 Subject: ARM: dts: exynos: Use S5M8767 clock in S3C RTC in Exynos5250 Spring Use the 32 kHz clock from S5M8767 PMIC in the S3C RTC node. Except making the S3C RTC working, this also fixes dtbs_check warnings: arch/arm/boot/dts/exynos5250-spring.dt.yaml: rtc@101e0000: clocks: [[2, 337]] is too short arch/arm/boot/dts/exynos5250-spring.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-10-krzk@kernel.org --- arch/arm/boot/dts/exynos5250-spring.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index b6fcf847fc2f..166a0d287633 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -7,6 +7,7 @@ */ /dts-v1/; +#include #include #include #include @@ -141,7 +142,7 @@ <1200000>, <1200000>, <1200000>, <1200000>; - clocks { + s5m8767_osc: clocks { compatible = "samsung,s5m8767-clk"; #clock-cells = <1>; clock-output-names = "en32khz_ap", @@ -522,6 +523,12 @@ }; }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + &sd1_bus4 { samsung,pin-drv = ; }; -- cgit v1.2.3 From d872e4e98751903f7cb131123aae9399d1a0c1cc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:14 +0200 Subject: ARM: dts: exynos: Silence DP HPD pinctrl dtschema warning in Exynos5250 Spring The pin configuration of Display Port HPD GPIO emds with '-gpio' which confuses dtschema: arch/arm/boot/dts/exynos5250-spring.dt.yaml: pinctrl@11400000: dp-hpd-gpio: {'samsung,pins': ['gpc3-0'], ... 'samsung,pin-drv': [[0]], 'phandle': [[23]]} is not of type 'array' From schema: lib/python3.6/site-packages/dtschema/schemas/gpio/gpio-consumer.yaml Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-11-krzk@kernel.org --- arch/arm/boot/dts/exynos5250-spring.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 166a0d287633..a92ade33779c 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -457,7 +457,7 @@ samsung,pin-drv = ; }; - dp_hpd_gpio: dp-hpd-gpio { + dp_hpd_gpio: dp-hpd { samsung,pins = "gpc3-0"; samsung,pin-function = ; samsung,pin-pud = ; -- cgit v1.2.3 From 18f99f24a9704caeca4178d0955c0e9654629346 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Aug 2020 15:18:05 +0100 Subject: ARM: dts: r8a7742: Add IPMMU DT nodes Add the five IPMMU instances found in the r8a7742 to DT with a disabled status. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200825141805.27105-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 0fc52b27ae64..c62e26876f95 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -412,6 +412,54 @@ #thermal-sensor-cells = <0>; }; + ipmmu_sy0: iommu@e6280000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@e6290000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@ec680000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@fe951000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; -- cgit v1.2.3 From a0be3c32b15675e9f9dc0d3dc4e0361c019b93d8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Aug 2020 17:27:15 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller Enable PCIe Controller and set PCIe bus clock frequency. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200825162718.5838-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index b3461a61a4bf..df85e516a3c0 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -159,6 +159,18 @@ /* status = "okay"; */ }; +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + /* SW2[6] determines which connector is activated + * ON = PCIe X4 (connector-J7) + * OFF = mini-PCIe (connector-J26) + */ + status = "okay"; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii"; -- cgit v1.2.3 From ff9e786f0ee0cc33aedabaa56678cb45d3c1ca0b Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Thu, 27 Aug 2020 15:53:14 +0100 Subject: arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Add FDP1 device nodes to R8A774E1 (RZ/G2H) SoC dtsi. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200827145315.26261-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index f5909ced7679..34fdb9a0c325 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2504,6 +2504,26 @@ renesas,fcp = <&fcpvi1>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; -- cgit v1.2.3 From 912d3c5383f7a68b1293aaaa378b9c3373e48a91 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 27 Aug 2020 15:53:15 +0100 Subject: arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores Enable cpuidle (core shutdown) support for RZ/G2H CA5x cores. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200827145315.26261-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 34fdb9a0c325..ae1ffa204237 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -127,6 +127,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; @@ -141,6 +142,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -154,6 +156,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -167,6 +170,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -180,6 +184,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; #cooling-cells = <2>; dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; @@ -194,6 +199,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -206,6 +212,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -218,6 +225,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -236,6 +244,28 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <700>; + exit-latency-us = <700>; + min-residency-us = <5000>; + }; + }; }; extal_clk: extal { -- cgit v1.2.3 From e9f0fb53ac88c1ccf3728b47c687838b6054f481 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 27 Aug 2020 19:19:18 +0100 Subject: arm64: dts: renesas: Add HiHope RZ/G2H board with idk-1110wr display The HiHope RZ/G2H is advertised as compatible with panel idk-1110wr from Advantech, however the panel isn't sold alongside the board. New dts, enabling the lvds node to get the panel to work with HiHope RZ/G2H. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200827181918.30130-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d7902294faf3..46445474cf3e 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb +dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts new file mode 100644 index 000000000000..3b7339127bc0 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H sub board connected + * to an Advantech IDK-1110WR 10.1" LVDS panel + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a774e1-hihope-rzg2h-ex.dts" +#include "hihope-rzg2-ex-lvds.dtsi" +#include "rzg2-advantech-idk-1110wr-panel.dtsi" + +&lvds0 { + status = "okay"; +}; -- cgit v1.2.3 From cd5b0321ed32b79c020abc2b54e8ab129611447c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 1 Sep 2020 09:54:17 +0200 Subject: ARM: dts: exynos: Use S2MPS11 clock in S3C RTC in SMDK5420 Use the 32 kHz clock from S2MPS11 PMIC in the S3C RTC node. Except making the S3C RTC working, this also fixes dtbs_check warnings: arch/arm/boot/dts/exynos5420-smdk5420.dt.yaml: rtc@101e0000: clocks: [[2, 317]] is too short arch/arm/boot/dts/exynos5420-smdk5420.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200901075417.22481-14-krzk@kernel.org --- arch/arm/boot/dts/exynos5420-smdk5420.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 83fa800fa1eb..4e49d8095b29 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "exynos5420.dtsi" #include "exynos5420-cpus.dtsi" +#include #include / { @@ -401,6 +402,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; &usbdrd_phy0 { -- cgit v1.2.3 From 1bd3fe23ffcab2e271416282fa34a17a7c694c19 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Wed, 26 Aug 2020 22:42:50 +0200 Subject: dt-bindings: arm: fsl: add compatible string for Tolino Shine 2 HD This adds a compatible string for the Tolino Shine 2 HD eBook reader. Signed-off-by: Andreas Kemnade Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 37cef8653541..685d39f625f9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -216,6 +216,7 @@ properties: items: - enum: - fsl,imx6sl-evk # i.MX6 SoloLite EVK Board + - kobo,tolino-shine2hd - kobo,tolino-shine3 - const: fsl,imx6sl -- cgit v1.2.3 From 9c7016f1ca6d5126ae6fb616114f63b3dc4ce830 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Wed, 26 Aug 2020 22:42:51 +0200 Subject: ARM: dts: imx: add devicetree for Tolino Shine 2 HD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a devicetree for the Tolino Shine 2 HD Ebook reader. It is based on boards marked with "37NB-E60QF0+4A2". It is equipped with an i.MX6SL SoC. Expected to work: - Buttons - Wifi - Touchscreen - LED - uSD - USB - RTC Not working due to missing drivers: - Backlight (requires NTXEC driver) - EPD Not working due to unknown reasons: - deep sleep (echo standby >/sys/power/state works), wakeup fails when imx_gpc_pre_suspend(true) was called. Signed-off-by: Andreas Kemnade Reviewed-by: Jonathan Neuschäfer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts | 588 +++++++++++++++++++++++++++ 2 files changed, 589 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index eec0d61874a4..245cdc445bc0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -586,6 +586,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-zii-rdu2.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ + imx6sl-tolino-shine2hd.dtb \ imx6sl-tolino-shine3.dtb \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SLL) += \ diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts new file mode 100644 index 000000000000..caa279608803 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for the Tolino Shine 2 HD ebook reader + * + * Name on mainboard is: 37NB-E60QF0+4A2 or 37NB-E60QF0+4A3 + * Serials start with: E60QF2 + * + * Copyright 2020 Andreas Kemnade + */ + +/dts-v1/; + +#include +#include +#include "imx6sl.dtsi" + +/ { + model = "Tolino Shine 2 HD"; + compatible = "kobo,tolino-shine2hd", "fsl,imx6sl"; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + cover { + label = "Cover"; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + + fl { + label = "Frontlight"; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + power { + label = "Power"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + on { + label = "tolinoshine2hd:white:on"; + gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; + status = "okay"; + + /* TODO: embedded controller at 0x43 (driver missing) */ + +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; + clock-frequency = <100000>; + status = "okay"; + + zforce: touchscreen@50 { + compatible = "neonode,zforce"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_zforce>; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ldo1_reg>; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + x-size = <1072>; + y-size = <1448>; + }; + + /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + ricoh619: pmic@32 { + compatible = "ricoh,rc5t619"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; + reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + system-power-controller; + + regulators { + dcdc1_reg: DCDC1 { + regulator-name = "DCDC1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <900000>; + regulator-suspend-min-microvolt = <900000>; + }; + }; + + /* Core3_3V3 */ + dcdc2_reg: DCDC2 { + regulator-name = "DCDC2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3100000>; + regulator-suspend-min-microvolt = <3100000>; + }; + }; + + dcdc3_reg: DCDC3 { + regulator-name = "DCDC3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V2 */ + dcdc4_reg: DCDC4 { + regulator-name = "DCDC4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V8 */ + dcdc5_reg: DCDC5 { + regulator-name = "DCDC5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1700000>; + regulator-suspend-min-microvolt = <1700000>; + }; + }; + + /* IR_3V3 */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-boot-on; + }; + + /* Core1_3V3 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3000000>; + regulator-suspend-min-microvolt = <3000000>; + }; + }; + + /* Core5_1V2 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-boot-on; + }; + + /* SPD_3V3 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + }; + + /* DDR_0V6 */ + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-always-on; + regulator-boot-on; + }; + + /* VDD_PWM */ + ldo7_reg: LDO7 { + regulator-name = "LDO7"; + regulator-always-on; + regulator-boot-on; + }; + + /* ldo_1v8 */ + ldo8_reg: LDO8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "LDO9"; + regulator-boot-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "LDO10"; + regulator-boot-on; + }; + + ldortc1_reg: LDORTC1 { + regulator-name = "LDORTC1"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 + MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 + MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x17059 + MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x17059 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 + MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 + MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 + MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 + MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 + MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 + MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 + MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 + MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 + MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 + MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 + MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 + MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 + MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 + MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 + MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 + MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 + MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 + MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 + MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 + MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 + MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 + MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 + MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 + MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 + MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059 + >; + }; + + pinctrl_ricoh_gpio: ricoh_gpiogrp { + fsl,pins = < + MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ + MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ + MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2grp-sleep { + fsl,pins = < + MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 + MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 + MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 + MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grp-sleep { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; + + pinctrl_zforce: zforcegrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ + MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x10059 /* TP_RST */ + >; + }; +}; + +®_vdd1p1 { + vin-supply = <&dcdc2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&dcdc2_reg>; +}; + +®_arm { + vin-supply = <&dcdc3_reg>; +}; + +®_soc { + vin-supply = <&dcdc1_reg>; +}; + +®_pu { + vin-supply = <&dcdc1_reg>; +}; + +&snvs_rtc { + /* + * We are using the RTC in the PMIC, but this one is not disabled + * in imx6sl.dtsi. + */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; + non-removable; + status = "okay"; + + /* internal uSD card */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; + + /* + * 37NB-E60QF0+4A2: CyberTan WC121 (BCM43362) SDIO WiFi + * 37NB-E60QF0+4A3: RTL8189F SDIO WiFi + */ +}; + +&usbotg1 { + pinctrl-names = "default"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; -- cgit v1.2.3 From aa71d0648318eee0ac986eb2700e40cefbfb11d0 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 31 Aug 2020 17:14:13 +0800 Subject: arm64: dts: imx8mm: Split the imx8mm evk board dts to a common dtsi There are two type of i.MX8MM EVK board, one is populated with LPDDR4(default dts), and one is populated with DDR4. these two boards share most of the board design, but still have some difference. imx8mm-evk has emmc support, imx8mm-ddr4-evk has gpmi nand support. And also, the BT/WIFI module is different. So move the common dts part into imx8mm-evk.dtsi for reuse. Signed-off-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 528 ++------------------------ arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 470 +++++++++++++++++++++++ 2 files changed, 506 insertions(+), 492 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 38134d201eef..de53f1c2bf72 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -1,12 +1,12 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; #include -#include "imx8mm.dtsi" +#include "imx8mm-evk.dtsi" / { model = "FSL i.MX8MM EVK board"; @@ -15,87 +15,6 @@ aliases { spi0 = &flexspi; }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_wlf>; - wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai3>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; }; &ddrc { @@ -118,27 +37,6 @@ }; }; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - }; -}; - &flexspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi>; @@ -155,219 +53,6 @@ }; }; -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 8>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - &usdhc3 { assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; assigned-clock-rates = <400000000>; @@ -380,67 +65,7 @@ status = "okay"; }; -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - &iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_gpio_wlf: gpiowlfgrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - pinctrl_flexspi: flexspigrp { fsl,pins = < MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 @@ -452,133 +77,52 @@ >; }; - pinctrl_pmic: pmicirq { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3grp100mhz { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi new file mode 100644 index 000000000000..5256d18028a2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8mm.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wm8524: audio-codec { + #sound-dai-cells = <0>; + compatible = "wlf,wm8524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_wlf>; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8524-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + simple-audio-card,routing = + "Left Line Out Jack", "LINEVOUTL", + "Right Line Out Jack", "LINEVOUTR"; + + cpudai: simple-audio-card,cpu { + sound-dai = <&sai3>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8524>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_gpio_wlf: gpiowlfgrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- cgit v1.2.3 From 7e767ab5c43d993c88363761333b12e2a9b0a5ec Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 31 Aug 2020 17:14:14 +0800 Subject: arm64: dts: imx8mm: Add imx8mm ddr4 evk board support Add the board dts support for i.MX8MM DDR4 EVK board. Signed-off-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts | 57 +++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 296c84aef3f4..54b7a345d0e4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts new file mode 100644 index 000000000000..6c079c0a3a48 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dtsi" + +/ { + model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; + compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; + + leds { + pinctrl-0 = <&pinctrl_gpio_led_2>; + + status { + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + + pinctrl_gpio_led_2: gpioled2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; +}; -- cgit v1.2.3 From 612a392fc04eed6b7ed1752f706fb40c6ad0bbb0 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 31 Aug 2020 17:14:12 +0800 Subject: dt-bindings: arm: fsl: Add imx8mm ddr4 evk board Add entry for i.MX8MM DDR4 EVK board and update the comments for imx8mm-evk as it is populated with LPDDR4. Signed-off-by: Jacky Bai Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 685d39f625f9..71acf14da715 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -347,6 +347,7 @@ properties: items: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit + - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - const: fsl,imx8mm -- cgit v1.2.3 From 0a96ec9bddd1622267e42b75994f21615a5d1f85 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:37 +0200 Subject: arm64: dts: imx8mm-beacon: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix. This fixes dtbs_check warnings like: pinctrl@30330000: 'pcal6414-gpio', 'pmicirq', 'usdhc1grp100mhz', 'usdhc1grp200mhz', 'usdhc1grpgpio', 'usdhc2grp100mhz', 'usdhc2grp200mhz', 'usdhc2grpgpio', 'usdhc3grp100mhz', 'usdhc3grp200mhz' do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 8 ++++---- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 5b5af8b381df..d6b9dedd168f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -210,7 +210,7 @@ >; }; - pinctrl_pcal6414: pcal6414-gpio { + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 >; @@ -240,7 +240,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -259,7 +259,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -271,7 +271,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 620a124dfb5f..502faf6144b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -290,7 +290,7 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; @@ -309,7 +309,7 @@ >; }; - pinctrl_usdhc1_gpio: usdhc1grpgpio { + pinctrl_usdhc1_gpio: usdhc1gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 >; @@ -326,7 +326,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 @@ -337,7 +337,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 @@ -364,7 +364,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -380,7 +380,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 -- cgit v1.2.3 From a6a355ede5747b668da056fbacdb75ac1ea71fc4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:39 +0200 Subject: arm64: dts: imx8mm-evk: Add 32.768 kHz clock to PMIC The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary parent allows to probe the bd718x7 clock driver fixing boot errors: bd718xx-clk bd71847-clk.1.auto: No parent clk found bd718xx-clk: probe of bd71847-clk.1.auto failed with error -22 Signed-off-by: Krzysztof Kozlowski Acked-By: Matti Vaittinen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 5256d18028a2..8bb44f7e50f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -126,6 +126,10 @@ interrupts = <3 GPIO_ACTIVE_LOW>; rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + regulators { buck1_reg: BUCK1 { regulator-name = "buck1"; -- cgit v1.2.3 From fc54664e0bbfea639e720e838b48298fbaf59af4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:40 +0200 Subject: arm64: dts: imx8mm-evk: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index de53f1c2bf72..4e2820d19244 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -94,7 +94,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -110,7 +110,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 8bb44f7e50f7..f572b7d207f4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -390,13 +390,13 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; }; - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; @@ -424,7 +424,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 >; @@ -442,7 +442,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -454,7 +454,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 -- cgit v1.2.3 From a304ae85b9db6b1ba01b17f3c53b9fd7d091f62f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:41 +0200 Subject: arm64: dts: imx8mm-ddr4-evk: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index a1e5483dbbbe..3ac8f9d3c372 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -155,7 +155,7 @@ }; &iomuxc { - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; -- cgit v1.2.3 From 9cfa2dda4b81c7872cda9a635e16675b70fa2e7f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:42 +0200 Subject: arm64: dts: imx8mn-ddr4-evk: Align regulator names with schema Device tree schema expects regulator names to be lowercase. Changing to lowercase has multiple effects: 1. LDO6 supply is now properly configured, because regulator driver looks for supplies by lowercase name, 2. User-visible names via sysfs or debugfs are now lowercase, 2. dtbs_check warnings are fixed: pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-6]$' Signed-off-by: Krzysztof Kozlowski Acked-By: Matti Vaittinen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 3ac8f9d3c372..8f7155716c84 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -60,7 +60,7 @@ regulators { buck1_reg: BUCK1 { - regulator-name = "BUCK1"; + regulator-name = "buck1"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; @@ -69,7 +69,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "BUCK2"; + regulator-name = "buck2"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; @@ -79,14 +79,14 @@ buck3_reg: BUCK3 { // BUCK5 in datasheet - regulator-name = "BUCK3"; + regulator-name = "buck3"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; }; buck4_reg: BUCK4 { // BUCK6 in datasheet - regulator-name = "BUCK4"; + regulator-name = "buck4"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -95,7 +95,7 @@ buck5_reg: BUCK5 { // BUCK7 in datasheet - regulator-name = "BUCK5"; + regulator-name = "buck5"; regulator-min-microvolt = <1605000>; regulator-max-microvolt = <1995000>; regulator-boot-on; @@ -104,7 +104,7 @@ buck6_reg: BUCK6 { // BUCK8 in datasheet - regulator-name = "BUCK6"; + regulator-name = "buck6"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-boot-on; @@ -112,7 +112,7 @@ }; ldo1_reg: LDO1 { - regulator-name = "LDO1"; + regulator-name = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -120,7 +120,7 @@ }; ldo2_reg: LDO2 { - regulator-name = "LDO2"; + regulator-name = "ldo2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; @@ -128,7 +128,7 @@ }; ldo3_reg: LDO3 { - regulator-name = "LDO3"; + regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -136,7 +136,7 @@ }; ldo4_reg: LDO4 { - regulator-name = "LDO4"; + regulator-name = "ldo4"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -144,7 +144,7 @@ }; ldo6_reg: LDO6 { - regulator-name = "LDO6"; + regulator-name = "ldo6"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; -- cgit v1.2.3 From a09854718247e070f5e69670a6ae73e158224503 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:43 +0200 Subject: arm64: dts: imx8mn-evk: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 76e0225729b1..7f4b904e9982 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -223,13 +223,13 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; }; - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; @@ -248,7 +248,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 >; @@ -266,7 +266,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -278,7 +278,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 @@ -306,7 +306,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -322,7 +322,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 -- cgit v1.2.3 From ad5260e07c1aff916e4aec2a2907fab83fe85975 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:44 +0200 Subject: arm64: dts: imx8mq-evk: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index a088831d2e24..7c6808814856 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -407,7 +407,7 @@ >; }; - pinctrl_reg_usdhc2: regusdhc2grpgpio { + pinctrl_reg_usdhc2: regusdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; -- cgit v1.2.3 From ae560c43c824ce2c3c0349dff60a2fc210909f24 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:45 +0200 Subject: arm64: dts: imx8mq-librem5-devkit: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index a80e53428c2f..10f30ff85fd3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -735,7 +735,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd @@ -752,7 +752,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf @@ -769,13 +769,13 @@ >; }; - pinctrl_usdhc2_pwr: usdhc2grppwr { + pinctrl_usdhc2_pwr: usdhc2pwrgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ >; @@ -792,7 +792,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd @@ -803,7 +803,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf -- cgit v1.2.3 From cf551b1f44486f7c361c4cf81b7b50a8dbf46d92 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:46 +0200 Subject: arm64: dts: imx8mq-phanbell: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts index 3f541ddf0768..d6d3a3d5abc3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts @@ -365,7 +365,7 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; @@ -395,7 +395,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 @@ -412,7 +412,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 @@ -429,7 +429,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -448,7 +448,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 @@ -460,7 +460,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 -- cgit v1.2.3 From 02485f4aa1bd9e85756d17a1b6ba6fcae9de345c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:47 +0200 Subject: arm64: dts: imx8mq-pico-pi: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts index 59da96b7143f..f4d5748a7bd6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts @@ -297,7 +297,7 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; @@ -335,7 +335,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 @@ -351,7 +351,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 @@ -367,7 +367,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 >; @@ -385,7 +385,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 @@ -397,7 +397,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 -- cgit v1.2.3 From 32e67c15b6db796938be47145d6052d3ccceb4e3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:48 +0200 Subject: arm64: dts: imx8mq-sr-som: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi index 404c46671b96..0187890a90c5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi @@ -275,7 +275,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd @@ -292,7 +292,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf -- cgit v1.2.3 From f05b12564d11fe5591bbc039847045248be562e5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:49 +0200 Subject: arm64: dts: imx8mq-hummingboard-pulse: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts index bfd91c1ed6a5..366693f31992 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts @@ -214,13 +214,13 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 >; }; - pinctrl_usdhc2_vmmc: usdhc2vmmcgpio { + pinctrl_usdhc2_vmmc: usdhc2vmmcgpiogrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 >; @@ -238,7 +238,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd @@ -250,7 +250,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf -- cgit v1.2.3 From a1172ceb52e68470389091b5248377ab95015006 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 28 Aug 2020 18:47:50 +0200 Subject: arm64: dts: imx8qxp-colibri: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi index 75f17a29f81e..f38acff0d25c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi @@ -494,7 +494,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 @@ -511,7 +511,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 @@ -554,7 +554,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ @@ -566,7 +566,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ -- cgit v1.2.3 From e3e61bce5f0851592a1ac62efdac78b5aaa4c09c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 2 Sep 2020 18:32:23 +0200 Subject: arm64: dts: imx8mm-var-som: Add 32.768 kHz clock to PMIC The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary parent allows to probe the bd718x7 clock driver fixing boot errors: bd718xx-clk bd71847-clk.1.auto: No parent clk found bd718xx-clk: probe of bd71847-clk.1.auto failed with error -22 Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index c371cb34b3f7..9c6e91243ba0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -140,6 +140,10 @@ interrupts = <8 GPIO_ACTIVE_LOW>; rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + regulators { buck1_reg: BUCK1 { regulator-name = "buck1"; -- cgit v1.2.3 From ed13ffc597e6395b4bf20d04b66035c73a6ee86d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Aug 2020 11:40:24 +0200 Subject: ARM: dts: vf: Fix PCA95xx GPIO expander properties on ZII CFU1 The PCA95xx GPIO expander requires GPIO controller properties to operate properly. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 50da0c94e1b7..96495d965163 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -225,6 +225,7 @@ compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; + #gpio-cells = <2>; }; lm75@48 { -- cgit v1.2.3 From d77a99a8a853ef18334b2777eef4cf931944036e Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 31 Aug 2020 15:27:49 +0200 Subject: ARM: dts: imx6qdl: move iomuxc compatible assignment out of root node The common imx6qdl.dtsi already defines the iomuxc phandle. Make use of it in the imx6dl.dtsi and imx6q.dtsi. Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 8 ++++---- arch/arm/boot/dts/imx6q.dtsi | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 77b65a402e19..fdd81fdc3f35 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -88,10 +88,6 @@ }; aips1: bus@2000000 { - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6dl-iomuxc"; - }; - pxp: pxp@20f0000 { reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; @@ -298,6 +294,10 @@ compatible = "fsl,imx6dl-hdmi"; }; +&iomuxc { + compatible = "fsl,imx6dl-iomuxc"; +}; + &ipu1_csi1 { ipu1_csi1_from_ipu1_csi1_mux: endpoint { remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 78a4d64929f3..5277e3903291 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -182,10 +182,6 @@ status = "disabled"; }; }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6q-iomuxc"; - }; }; sata: sata@2200000 { @@ -427,6 +423,10 @@ }; }; +&iomuxc { + compatible = "fsl,imx6q-iomuxc"; +}; + &ipu1_csi1 { ipu1_csi1_from_mipi_vc1: endpoint { remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; -- cgit v1.2.3 From f3e7dae323ab9226974d94d6b40f801d9f2091b0 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 31 Aug 2020 15:30:18 +0200 Subject: ARM: dts: imx6qdl: add enet_out clk support Like the other i-MX devices the i.MX6 family can output the enet tx clock on the pad to feed the connected device. Add the missing clk here to avoid local fixups like: arch/arm/boot/dts/imx6qdl-tx6.dtsi. Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index de6daa7b38aa..7a8837cbe21b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1043,8 +1043,9 @@ <0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>, <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp"; + clock-names = "ipg", "ahb", "ptp", "enet_out"; fsl,stop-mode = <&gpr 0x34 27>; status = "disabled"; }; -- cgit v1.2.3 From e8a3d7064c34a02b86c0e512644e8c1d790464d6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Sep 2020 08:27:43 +0200 Subject: ARM: dts: imx28-m28: Align GPMI NAND node name with schema Device tree schema expects NAND controller to be named "nand-controller", otherwise dtbs_check complain with a warning like: arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dt.yaml: gpmi-nand@8000c000: $nodename:0: 'gpmi-nand@8000c000' does not match '^nand-controller(@.*)?' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-m28.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi index 0bac72d5351f..2bdb4c093545 100644 --- a/arch/arm/boot/dts/imx28-m28.dtsi +++ b/arch/arm/boot/dts/imx28-m28.dtsi @@ -16,7 +16,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { #address-cells = <1>; #size-cells = <1>; pinctrl-names = "default"; -- cgit v1.2.3 From 75a4a04e78c624d5ee1bf466a1395725a3f6e04c Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Fri, 4 Sep 2020 12:20:36 +0200 Subject: ARM: dts: samsung: odroid-xu3: Move assigned-clock* properties to i2s0 node The purpose of those assigned-clock-* properties is to configure clock for for the I2S device so move them to respective node. This suppresses the dtbs_check warning: arch/arm/boot/dts/exynos5422-odroidxu3.dt.yaml: sound: 'clocks' is a dependency of 'assigned-clocks' Reported-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 60 ++++++++++------------- 1 file changed, 27 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index c3c2d85267da..b5ec4f47eb3a 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -29,30 +29,6 @@ "HiFi Playback", "Mixer DAI TX", "Mixer DAI RX", "HiFi Capture"; - assigned-clocks = <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MOUT_USER_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, - <0>, - <0>, - <0>, - <0>, - <196608001>, - <(196608002 / 2)>, - <196608000>; - cpu { sound-dai = <&i2s0 0>, <&i2s0 1>; }; @@ -62,13 +38,6 @@ }; }; -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, - <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <(196608000 / 256)>, - <196608000>; -}; - &hsi2c_5 { status = "okay"; max98090: max98090@10 { @@ -84,6 +53,31 @@ &i2s0 { status = "okay"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; + assigned-clocks = <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MOUT_USER_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&i2s0 CLK_I2S_RCLK_SRC>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_SCLK_I2S>; + + assigned-clock-rates = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <196608001>, + <(196608002 / 2)>, + <196608000>; + }; -- cgit v1.2.3 From 975bcbce5b16d4bf7282efda134e12dca122bafb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 2 Sep 2020 17:57:32 +0200 Subject: ARM: dts: exynos: Remove I2C9 samsung, i2c-slave-addr from Exynos5250 boards The property samsung,i2c-slave-addr in I2C9 controller on Exynos5250 Arndale and SMDK5250 boards, is not actually needed. There is only one master on this bus. It's not clear why this property was added at first place. Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200902155733.20271-1-krzk@kernel.org --- arch/arm/boot/dts/exynos5250-arndale.dts | 1 - arch/arm/boot/dts/exynos5250-smdk5250.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index f2bcce167b2d..d37479ea4fa2 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -542,7 +542,6 @@ status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; sata_phy_i2c: sata-phy@38 { compatible = "samsung,exynos-sataphy-i2c"; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 00af7fb65080..bd8827c69ff1 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -326,7 +326,6 @@ status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; sata_phy_i2c: sata-phy@38 { compatible = "samsung,exynos-sataphy-i2c"; -- cgit v1.2.3 From d3604c91566a8b06683482e0c7e2fa9473aa8b9a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 2 Sep 2020 17:57:33 +0200 Subject: ARM: dts: exynos: Silence SATA PHY warning in Exynos5250 The SATA PHY in Exynos5250 SoCs has two interfaces and two device nodes: 1. sata-phy@12170000 2. i2c-9/i2c@38 The first node represents the actual SATA PHY device with phy-cells. The second represents an additional I2C interface, needed by the driver to communicate with the SATA PHY device. It is not a PHY-provider in the terms of dtschema so rename it to silence dtbs_check warning: arch/arm/boot/dts/exynos5250-arndale.dt.yaml: sata-phy@38: '#phy-cells' is a required property From schema: lib/python3.6/site-packages/dtschema/schemas/phy/phy-provider.yaml This second device node is also a property of SoC, not a board so move it there. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200902155733.20271-2-krzk@kernel.org --- arch/arm/boot/dts/exynos5250-arndale.dts | 9 ++++----- arch/arm/boot/dts/exynos5250-smdk5250.dts | 9 ++++----- arch/arm/boot/dts/exynos5250.dtsi | 6 ++++++ 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index d37479ea4fa2..79546f11af26 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -542,11 +542,6 @@ status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <40000>; - - sata_phy_i2c: sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; }; &i2s0 { @@ -618,6 +613,10 @@ samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; }; +&sata_phy_i2c { + status = "okay"; +}; + &soc { /* * For unknown reasons HDMI-DDC does not work with Exynos I2C diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index bd8827c69ff1..186790f39e4d 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -326,11 +326,6 @@ status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <40000>; - - sata_phy_i2c: sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; }; &i2s0 { @@ -382,6 +377,10 @@ samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; }; +&sata_phy_i2c { + status = "okay"; +}; + &spi_1 { status = "okay"; cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 488d3f9fab59..e09db3cecbff 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -473,6 +473,12 @@ clocks = <&clock CLK_SATA_PHYI2C>; clock-names = "i2c"; status = "disabled"; + + sata_phy_i2c: sata-phy-i2c@38 { + compatible = "samsung,exynos-sataphy-i2c"; + reg = <0x38>; + status = "disabled"; + }; }; spi_0: spi@12d20000 { -- cgit v1.2.3 From b7ecb51b2d9bd12c80c24d2fd1cadedd35e7cb7e Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 4 Sep 2020 11:38:50 +0100 Subject: arm64: dts: renesas: r8a774e1: Add PCIe EP nodes Add PCIe EP nodes for R8A774E1 Soc dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20200904103851.3946-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index ae1ffa204237..574ef623ae9b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2468,6 +2468,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774e1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a774e1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + status = "disabled"; + }; + vspbc: vsp@fe920000 { compatible = "renesas,vsp2"; reg = <0 0xfe920000 0 0x8000>; -- cgit v1.2.3 From 34a459187180d4049b00fcf12fad6603011d4d7a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 28 Aug 2020 15:20:14 +0100 Subject: ARM: dts: arm: Fix SP804 users The SP804 DT nodes for Realview, MPS2 and VExpress were not complying with the binding: it requires either one or three clocks, but does not allow exactly two clocks. Simply duplicate the first clock to satisfy the binding requirement. For MPS2, we triple the clock, and add the clock-names property, as this is required by the Linux primecell driver. Try to make the clock-names more consistent on the way. Link: https://lore.kernel.org/r/20200828142018.43298-3-andre.przywara@arm.com Acked-by: Linus Walleij Signed-off-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/arm-realview-pb11mp.dts | 16 ++++++++-------- arch/arm/boot/dts/mps2.dtsi | 6 ++++-- arch/arm/boot/dts/vexpress-v2p-ca9.dts | 4 ++-- 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 9748e0fe800f..564e2eee2c24 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -568,8 +568,8 @@ clocks = <&sp810_syscon 0>, <&sp810_syscon 1>, <&pclk>; - clock-names = "timerclk0", - "timerclk1", + clock-names = "timer0clk", + "timer1clk", "apb_pclk"; }; @@ -582,8 +582,8 @@ clocks = <&sp810_syscon 2>, <&sp810_syscon 3>, <&pclk>; - clock-names = "timerclk2", - "timerclk3", + clock-names = "timer0clk", + "timer1clk", "apb_pclk"; }; @@ -645,16 +645,16 @@ timer45: timer@10018000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x10018000 0x1000>; - clocks = <&timclk>, <&pclk>; - clock-names = "timer", "apb_pclk"; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; timer67: timer@10019000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x10019000 0x1000>; - clocks = <&timclk>, <&pclk>; - clock-names = "timer", "apb_pclk"; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index 96fb5a5cf4d3..48c34fa282af 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -161,9 +161,11 @@ }; timer2: dual-timer@2000 { - compatible = "arm,sp804"; + compatible = "arm,sp804", "arm,primecell"; reg = <0x2000 0x1000>; - clocks = <&sysclk>; + clocks = <&sysclk>, <&sysclk>, <&sysclk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; interrupts = <10>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 623246f37448..6cddea25a292 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -122,8 +122,8 @@ reg = <0x100e4000 0x1000>; interrupts = <0 48 4>, <0 49 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "timclk", "apb_pclk"; + clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; -- cgit v1.2.3 From a894c6dd56c99a44d550f65fbe87d00377b9dc3d Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 28 Aug 2020 14:05:59 +0100 Subject: ARM: dts: arm: Fix SP805 clocks The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for ARM Ltd. platforms to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. For MPS2 we only specify one clock so far, but the binding requires two clocks to be named. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. So since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Link: https://lore.kernel.org/r/20200828130602.42203-8-andre.przywara@arm.com Reviewed-by: Linus Walleij Signed-off-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/arm-realview-eb.dtsi | 2 +- arch/arm/boot/dts/arm-realview-pb11mp.dts | 4 ++-- arch/arm/boot/dts/arm-realview-pbx.dtsi | 4 ++-- arch/arm/boot/dts/mps2.dtsi | 4 ++-- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 2 +- arch/arm/boot/dts/vexpress-v2m.dtsi | 2 +- arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 4 ++-- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +- arch/arm/boot/dts/vexpress-v2p-ca9.dts | 2 +- 9 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index fe0207b88053..a534a8e444d9 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -390,7 +390,7 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x10010000 0x1000>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 564e2eee2c24..0c7dabef4a5f 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -546,7 +546,7 @@ interrupt-parent = <&intc_pb11mp>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; @@ -556,7 +556,7 @@ interrupt-parent = <&intc_pb11mp>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; timer01: timer@10011000 { diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index f61bd59ae5ba..ac95667ed781 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -381,7 +381,7 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x1000f000 0x1000>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; @@ -389,7 +389,7 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x10010000 0x1000>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index 48c34fa282af..37f5023f529c 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -199,8 +199,8 @@ arm,primecell-periphid = <0x00141805>; reg = <0x8000 0x1000>; interrupts = <0>; - clocks = <&sysclk>; - clock-names = "apb_pclk"; + clocks = <&sysclk>, <&sysclk>; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index a88ee5294d35..4f7220b11f2d 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -280,7 +280,7 @@ reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@110000 { diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index 5e48b641068a..2ac41ed3a57c 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -198,7 +198,7 @@ reg = <0x0f000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@11000 { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index f82fa34c90be..e63c5c0bfb43 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -87,8 +87,8 @@ status = "disabled"; reg = <0 0x2b060000 0 0x1000>; interrupts = <0 98 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; + clocks = <&sys_pll>, <&sys_pll>; + clock-names = "wdog_clk", "apb_pclk"; }; gic: interrupt-controller@2c001000 { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 3ac95a179452..012d40a7228c 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -128,7 +128,7 @@ reg = <0 0x2a490000 0 0x1000>; interrupts = <0 98 4>; clocks = <&oscclk6a>, <&oscclk6a>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; hdlcd@2b000000 { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 6cddea25a292..4c5847955856 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -132,7 +132,7 @@ reg = <0x100e5000 0x1000>; interrupts = <0 51 4>; clocks = <&oscclk2>, <&oscclk2>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; scu@1e000000 { -- cgit v1.2.3 From b83ded8a31e314545727bd5ee852a1f65a6ad1e9 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 28 Aug 2020 14:05:54 +0100 Subject: arm64: dts: arm: Fix SP805 clock-names The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for ARM Ltd. platforms to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Link: https://lore.kernel.org/r/20200828130602.42203-3-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 2 +- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index eeee51f1251b..40d95c58b55e 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -251,7 +251,7 @@ reg = <0x0f0000 0x10000>; interrupts = <7>; clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@110000 { diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index 001a0a3c7f66..4c4a381d2c75 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -195,7 +195,7 @@ reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@110000 { -- cgit v1.2.3 From 1aedefe13ba263d0d7d1cfbb38aadebbd5bab34e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:08 -0500 Subject: arm64: dts: ti: k3-j721e: Use lower case hexadecimal Device tree convention uses lower case a-f for hexadecimals. Fix the same. Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Acked-by: Suman Anna Link: https://lore.kernel.org/r/20200903130015.21361-2-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index f787aa73aaae..1bb8235d9ffb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -127,7 +127,7 @@ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ -- cgit v1.2.3 From 05e393c596c4495d79f0cbeacb0f0a0e0b6f89d5 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:09 -0500 Subject: arm64: dts: ti: k3-am65-main: Use lower case hexadecimal Device tree convention uses lower case a-f for hexadecimals. Fix the same. Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Acked-by: Suman Anna Link: https://lore.kernel.org/r/20200903130015.21361-3-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 76e0edc4ad5c..d53d1ead4bb6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -344,9 +344,9 @@ <0x4090 0x3>; /* SERDES1 lane select */ }; - dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 { + dss_oldi_io_ctrl: dss_oldi_io_ctrl@41e0 { compatible = "syscon"; - reg = <0x0000041E0 0x14>; + reg = <0x0000041e0 0x14>; }; ehrpwm_tbclk: syscon@4140 { -- cgit v1.2.3 From 91e5f404e42bc189bb0e447d30041de737ad24bf Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:10 -0500 Subject: arm64: dts: ti: k3-am65*: Use generic gpio for node names Use gpio@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Acked-by: Suman Anna Link: https://lore.kernel.org/r/20200903130015.21361-4-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++-- arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index d53d1ead4bb6..a2fc508e59a6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -661,7 +661,7 @@ }; }; - main_gpio0: main_gpio0@600000 { + main_gpio0: gpio@600000 { compatible = "ti,am654-gpio", "ti,keystone-gpio"; reg = <0x0 0x600000 0x0 0x100>; gpio-controller; @@ -676,7 +676,7 @@ clock-names = "gpio"; }; - main_gpio1: main_gpio1@601000 { + main_gpio1: gpio@601000 { compatible = "ti,am654-gpio", "ti,keystone-gpio"; reg = <0x0 0x601000 0x0 0x100>; gpio-controller; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index a1ffe88d9664..0765700a8ba8 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -80,7 +80,7 @@ ti,interrupt-ranges = <0 712 16>; }; - wkup_gpio0: wkup_gpio0@42110000 { + wkup_gpio0: gpio@42110000 { compatible = "ti,am654-gpio", "ti,keystone-gpio"; reg = <0x42110000 0x100>; gpio-controller; -- cgit v1.2.3 From 86e67b591e6d993d98567143451883a5618c196e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:11 -0500 Subject: arm64: dts: ti: k3-am65*: Use generic clock for syscon clock names serdes and ehrpwm_tbclk nodes should be using clock@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Acked-by: Suman Anna Acked-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20200903130015.21361-5-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index a2fc508e59a6..63a1299cb0b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -327,12 +327,12 @@ reg = <0x00000210 0x4>; }; - serdes0_clk: serdes_clk@4080 { + serdes0_clk: clock@4080 { compatible = "syscon"; reg = <0x00004080 0x4>; }; - serdes1_clk: serdes_clk@4090 { + serdes1_clk: clock@4090 { compatible = "syscon"; reg = <0x00004090 0x4>; }; @@ -349,7 +349,7 @@ reg = <0x0000041e0 0x14>; }; - ehrpwm_tbclk: syscon@4140 { + ehrpwm_tbclk: clock@4140 { compatible = "ti,am654-ehrpwm-tbclk", "syscon"; reg = <0x4140 0x18>; #clock-cells = <1>; -- cgit v1.2.3 From dcccf77067e4274953e8944d9730bb7ae2964c28 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:12 -0500 Subject: arm64: dts: ti: k3-*: Use generic pinctrl for node names Use pinctrl@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Acked-by: Suman Anna Link: https://lore.kernel.org/r/20200903130015.21361-6-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++-- arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 63a1299cb0b2..1dd488cb15c6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -134,7 +134,7 @@ }; }; - main_pmx0: pinmux@11c000 { + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; reg = <0x0 0x11c000 0x0 0x2e4>; #pinctrl-cells = <1>; @@ -142,7 +142,7 @@ pinctrl-single,function-mask = <0xffffffff>; }; - main_pmx1: pinmux@11c2e8 { + main_pmx1: pinctrl@11c2e8 { compatible = "pinctrl-single"; reg = <0x0 0x11c2e8 0x0 0x24>; #pinctrl-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 0765700a8ba8..bb498be2f0a4 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -39,7 +39,7 @@ reg = <0x43000014 0x4>; }; - wkup_pmx0: pinmux@4301c000 { + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; reg = <0x4301c000 0x118>; #pinctrl-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 00a36a14efe7..1d2a7c05b6f3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -327,7 +327,7 @@ }; }; - main_pmx0: pinmux@11c000 { + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x0 0x11c000 0x0 0x2b4>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index c4a48e8d420a..9ad0266598ad 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -53,7 +53,7 @@ reg = <0x0 0x43000014 0x0 0x4>; }; - wkup_pmx0: pinmux@4301c000 { + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x178>; -- cgit v1.2.3 From 4c19fb9ce266561ab122880a02e873ee8c3668e4 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:13 -0500 Subject: arm64: dts: ti: k3-am65-base-board Use generic camera for node name instead of ov5640 Use camera@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Acked-by: Suman Anna Link: https://lore.kernel.org/r/20200903130015.21361-7-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index b8a8a0fcb8af..86c9074cb070 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -257,7 +257,7 @@ pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; - ov5640@3c { + ov5640: camera@3c { compatible = "ovti,ov5640"; reg = <0x3c>; -- cgit v1.2.3 From 9a8ecd414322ceb377cecb4795e3f3d7d7020952 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:14 -0500 Subject: arm64: dts: ti: k3-am65-wakeup: Use generic temperature-sensor for node name Use temperature-sensor@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna Suggested-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Reviewed-by: Suman Anna Acked-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20200903130015.21361-8-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index bb498be2f0a4..ed42f13e7663 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -95,7 +95,7 @@ clock-names = "gpio"; }; - wkup_vtm0: thermal@42050000 { + wkup_vtm0: temperature-sensor@42050000 { compatible = "ti,am654-vtm"; reg = <0x42050000 0x25c>; power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; -- cgit v1.2.3 From e5c956c4f36cdd59e775f2285af9a1683374c5a5 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 3 Sep 2020 08:00:15 -0500 Subject: arm64: dts: ti: k3-*: Fix up node_name_chars_strict warnings Building with W=2 throws up a bunch of easy to fixup warnings.. node_name_chars_strict is one of them.. Knock those out. Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200903130015.21361-9-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 +++--- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 4 ++-- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 16 ++++++++-------- .../arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi | 12 ++++++------ arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 18 +++++++++--------- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 6 +++--- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 2 +- 8 files changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 1dd488cb15c6..533525229a8d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -305,7 +305,7 @@ no-1-8-v; }; - scm_conf: scm_conf@100000 { + scm_conf: scm-conf@100000 { compatible = "syscon", "simple-mfd"; reg = <0 0x00100000 0 0x1c000>; #address-cells = <1>; @@ -344,7 +344,7 @@ <0x4090 0x3>; /* SERDES1 lane select */ }; - dss_oldi_io_ctrl: dss_oldi_io_ctrl@41e0 { + dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { compatible = "syscon"; reg = <0x0000041e0 0x14>; }; @@ -445,7 +445,7 @@ ti,interrupt-ranges = <0 392 32>; }; - main_navss { + main-navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 51ca4b4d4c21..29aaf8dca6f6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -6,7 +6,7 @@ */ &cbass_mcu { - mcu_conf: scm_conf@40f00000 { + mcu_conf: scm-conf@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x40f00000 0x0 0x20000>; #address-cells = <1>; @@ -116,7 +116,7 @@ }; }; - mcu_navss { + mcu-navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 86c9074cb070..d12dd89f3405 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -29,7 +29,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - secure_ddr: secure_ddr@9e800000 { + secure_ddr: secure-ddr@9e800000 { reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ alignment = <0x1000>; no-map; @@ -70,14 +70,14 @@ >; }; - push_button_pins_default: push_button__pins_default { + push_button_pins_default: push-button-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ @@ -93,13 +93,13 @@ >; }; - wkup_pca554_default: wkup_pca554_default { + wkup_pca554_default: wkup-pca554-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ >; }; - mcu_cpsw_pins_default: mcu_cpsw_pins_default { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ @@ -116,7 +116,7 @@ >; }; - mcu_mdio_pins_default: mcu_mdio1_pins_default { + mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ @@ -167,7 +167,7 @@ >; }; - main_mmc1_pins_default: main_mmc1_pins_default { + main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ @@ -180,7 +180,7 @@ >; }; - usb1_pins_default: usb1_pins_default { + usb1_pins_default: usb1-pins-default { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi index cdc3d40c3f60..9021c738056b 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi @@ -2,13 +2,13 @@ #include -mpu0_thermal: mpu0_thermal { +mpu0_thermal: mpu0-thermal { polling-delay-passive = <250>; /* milliseconds */ polling-delay = <500>; /* milliseconds */ thermal-sensors = <&wkup_vtm0 0>; trips { - mpu0_crit: mpu0_crit { + mpu0_crit: mpu0-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; @@ -16,13 +16,13 @@ mpu0_thermal: mpu0_thermal { }; }; -mpu1_thermal: mpu1_thermal { +mpu1_thermal: mpu1-thermal { polling-delay-passive = <250>; /* milliseconds */ polling-delay = <500>; /* milliseconds */ thermal-sensors = <&wkup_vtm0 1>; trips { - mpu1_crit: mpu1_crit { + mpu1_crit: mpu1-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; @@ -30,13 +30,13 @@ mpu1_thermal: mpu1_thermal { }; }; -mcu_thermal: mcu_thermal { +mcu_thermal: mcu-thermal { polling-delay-passive = <250>; /* milliseconds */ polling-delay = <500>; /* milliseconds */ thermal-sensors = <&wkup_vtm0 2>; trips { - mcu_crit: mcu_crit { + mcu_crit: mcu-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c355692796a9..648267284582 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -86,13 +86,13 @@ }; &main_pmx0 { - sw10_button_pins_default: sw10_button_pins_default { + sw10_button_pins_default: sw10-button-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ >; }; - main_mmc1_pins_default: main_mmc1_pins_default { + main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -106,14 +106,14 @@ >; }; - main_usbss0_pins_default: main_usbss0_pins_default { + main_usbss0_pins_default: main-usbss0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; - main_usbss1_pins_default: main_usbss1_pins_default { + main_usbss1_pins_default: main-usbss1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; @@ -153,7 +153,7 @@ >; }; - mcasp10_pins_default: mcasp10_pins_default { + mcasp10_pins_default: mcasp10-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ @@ -167,7 +167,7 @@ >; }; - audi_ext_refclk2_pins_default: audi_ext_refclk2_pins_default { + audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ >; @@ -175,7 +175,7 @@ }; &wkup_pmx0 { - sw11_button_pins_default: sw11_button_pins_default { + sw11_button_pins_default: sw11-button-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ >; @@ -194,7 +194,7 @@ >; }; - mcu_cpsw_pins_default: mcu_cpsw_pins_default { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ @@ -211,7 +211,7 @@ >; }; - mcu_mdio_pins_default: mcu_mdio1_pins_default { + mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 1d2a7c05b6f3..ea57d07777ba 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -86,7 +86,7 @@ ti,interrupt-ranges = <8 392 56>; }; - main_navss { + main-navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; @@ -888,7 +888,7 @@ no-1-8-v; }; - usbss0: cdns_usb@4104000 { + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; dma-coherent; @@ -918,7 +918,7 @@ }; }; - usbss1: cdns_usb@4114000 { + usbss1: cdns-usb@4114000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4114000 0x00 0x100>; dma-coherent; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 9ad0266598ad..e581cb1d87ee 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -249,7 +249,7 @@ }; }; - mcu_navss { + mcu-navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index d69d90c8b5e3..5dc3ba739131 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -71,7 +71,7 @@ }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup_i2c0_pins_default { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ -- cgit v1.2.3 From 78efa6a766eb38282351208031e29289afe9f570 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Wed, 12 Aug 2020 14:50:20 -0500 Subject: ARM: dts: ste-href: Add reg property to the LP5521 channel nodes Add the reg property to each channel node. This update is to accommodate the multicolor framework. In addition to the accommodation this allows the LEDs to be placed on any channel and allow designs to skip channels as opposed to requiring sequential order. Signed-off-by: Dan Murphy Acked-by: Pavel Machek Acked-by: Linus Walleij CC: Linus Walleij Link: https://lore.kernel.org/r/20200812195020.13568-7-dmurphy@ti.com Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href.dtsi | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 33e3b0b3c53d..ff47cbf6ed3b 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -58,16 +58,21 @@ reg = <0x33>; label = "lp5521_pri"; clock-mode = /bits/ 8 <2>; - chan0 { + #address-cells = <1>; + #size-cells = <0>; + chan@0 { + reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; linux,default-trigger = "heartbeat"; }; - chan1 { + chan@1 { + reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan2 { + chan@2 { + reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; @@ -77,15 +82,20 @@ reg = <0x34>; label = "lp5521_sec"; clock-mode = /bits/ 8 <2>; - chan0 { + #address-cells = <1>; + #size-cells = <0>; + chan@0 { + reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan1 { + chan@1 { + reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan2 { + chan@2 { + reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; -- cgit v1.2.3 From 4564363351e2680e55edc23c7953aebd2acb4ab7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 3 Sep 2020 10:01:52 +0200 Subject: ARM: dts: bcm2711: Enable the display pipeline Now that all the drivers have been adjusted for it, let's bring in the necessary device tree changes. The VEC and PV3 are left out for now, since it will require a more specific clock setup. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard Reviewed-by: Hoegeun Kwon Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/cfce2276d172d3d9c4d34d966b58fd47f77c4e46.1599120059.git-series.maxime@cerno.tech --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 48 +++++++++++++ arch/arm/boot/dts/bcm2711.dtsi | 122 +++++++++++++++++++++++++++++++++- 2 files changed, 169 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 222d7825e1ab..ca24c2c737ab 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -68,6 +68,14 @@ }; }; +&ddc0 { + status = "okay"; +}; + +&ddc1 { + status = "okay"; +}; + &firmware { firmware_clocks: clocks { compatible = "raspberrypi,firmware-clocks"; @@ -163,6 +171,38 @@ "RGMII_TXD3"; }; +&hdmi0 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + status = "okay"; +}; + +&hdmi1 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + status = "okay"; +}; + +&hvs { + clocks = <&firmware_clocks 4>; +}; + +&pixelvalve0 { + status = "okay"; +}; + +&pixelvalve1 { + status = "okay"; +}; + +&pixelvalve2 { + status = "okay"; +}; + +&pixelvalve4 { + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; @@ -231,3 +271,11 @@ &vchiq { interrupts = ; }; + +&vc4 { + status = "okay"; +}; + +&vec { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 00bcaed1be32..4847dd305317 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -12,6 +12,18 @@ interrupt-parent = <&gicv2>; + vc4: gpu { + compatible = "brcm,bcm2711-vc5"; + status = "disabled"; + }; + + clk_27MHz: clk-27M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "27MHz-clock"; + }; + clk_108MHz: clk-108M { #clock-cells = <0>; compatible = "fixed-clock"; @@ -238,6 +250,27 @@ status = "disabled"; }; + pixelvalve0: pixelvalve@7e206000 { + compatible = "brcm,bcm2711-pixelvalve0"; + reg = <0x7e206000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pixelvalve1: pixelvalve@7e207000 { + compatible = "brcm,bcm2711-pixelvalve1"; + reg = <0x7e207000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pixelvalve2: pixelvalve@7e20a000 { + compatible = "brcm,bcm2711-pixelvalve2"; + reg = <0x7e20a000 0x100>; + interrupts = ; + status = "disabled"; + }; + pwm1: pwm@7e20c800 { compatible = "brcm,bcm2835-pwm"; reg = <0x7e20c800 0x28>; @@ -248,10 +281,25 @@ status = "disabled"; }; - hvs@7e400000 { + pixelvalve4: pixelvalve@7e216000 { + compatible = "brcm,bcm2711-pixelvalve4"; + reg = <0x7e216000 0x100>; + interrupts = ; + status = "disabled"; + }; + + hvs: hvs@7e400000 { + compatible = "brcm,bcm2711-hvs"; interrupts = ; }; + pixelvalve3: pixelvalve@7ec12000 { + compatible = "brcm,bcm2711-pixelvalve3"; + reg = <0x7ec12000 0x100>; + interrupts = ; + status = "disabled"; + }; + dvp: clock@7ef00000 { compatible = "brcm,brcm2711-dvp"; reg = <0x7ef00000 0x10>; @@ -259,6 +307,78 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + hdmi0: hdmi@7ef00700 { + compatible = "brcm,bcm2711-hdmi0"; + reg = <0x7ef00700 0x300>, + <0x7ef00300 0x200>, + <0x7ef00f00 0x80>, + <0x7ef00f80 0x80>, + <0x7ef01b00 0x200>, + <0x7ef01f00 0x400>, + <0x7ef00200 0x80>, + <0x7ef04300 0x100>, + <0x7ef20000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + clock-names = "hdmi", "bvb", "audio", "cec"; + resets = <&dvp 0>; + ddc = <&ddc0>; + dmas = <&dma 10>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + ddc0: i2c@7ef04500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <97500>; + status = "disabled"; + }; + + hdmi1: hdmi@7ef05700 { + compatible = "brcm,bcm2711-hdmi1"; + reg = <0x7ef05700 0x300>, + <0x7ef05300 0x200>, + <0x7ef05f00 0x80>, + <0x7ef05f80 0x80>, + <0x7ef06b00 0x200>, + <0x7ef06f00 0x400>, + <0x7ef00280 0x80>, + <0x7ef09300 0x100>, + <0x7ef20000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + ddc = <&ddc1>; + clock-names = "hdmi", "bvb", "audio", "cec"; + resets = <&dvp 1>; + dmas = <&dma 17>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + ddc1: i2c@7ef09500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <97500>; + status = "disabled"; + }; }; /* -- cgit v1.2.3 From 7505340245ff6dfcb184ab7ef64270cc8d4f69a8 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Tue, 8 Sep 2020 15:01:00 -0500 Subject: ARM: dts: aspeed: tacoma: Add IBM Operation Panel I2C device Set I2C bus 0 to multi-master mode and add the panel device that will register as a slave. Signed-off-by: Eddie James Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200908200101.64974-5-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 5f4ee67ac787..4d070d6ba09f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include +#include #include / { @@ -438,7 +439,13 @@ }; &i2c0 { + multi-master; status = "okay"; + + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; }; &i2c1 { -- cgit v1.2.3 From d270bb09f4b1f8ccce8a9492faac1f7f74752e05 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Tue, 8 Sep 2020 15:01:01 -0500 Subject: ARM: dts: aspeed: rainier: Add IBM Operation Panel I2C device Set I2C bus 7 to multi-master mode and add the panel device that will register as a slave. Signed-off-by: Eddie James Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200908200101.64974-6-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index d64ff64b8020..1fa233d2da26 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include +#include #include / { @@ -699,6 +700,7 @@ }; &i2c7 { + multi-master; status = "okay"; si7021-a20@20 { @@ -832,6 +834,11 @@ }; }; + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; + dps: dps310@76 { compatible = "infineon,dps310"; reg = <0x76>; -- cgit v1.2.3 From c82bf6e133d30e0f9172a20807814fa28aef0f67 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 12 Aug 2020 20:54:00 +0930 Subject: ARM: aspeed: g5: Do not set sirq polarity A feature was added to the aspeed vuart driver to configure the vuart interrupt (sirq) polarity according to the LPC/eSPI strapping register. Systems that depend on a active low behaviour (sirq_polarity set to 0) such as OpenPower boxes also use LPC, so this relationship does not hold. Jeremy confirms that the s2600st which is strapped for eSPI also does not have this relationship. The property was added for a Tyan S7106 system which is not supported in the kernel tree. Should this or other systems wish to use this feature of the driver they should add it to the machine specific device tree. Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...") Signed-off-by: Joel Stanley Tested-by: Jeremy Kerr Reviewed-by: Jeremy Kerr Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200812112400.2406734-1-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 9c91afb2b404..a93009aa2f04 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -425,7 +425,6 @@ interrupts = <8>; clocks = <&syscon ASPEED_CLK_APB>; no-loopback-test; - aspeed,sirq-polarity-sense = <&syscon 0x70 25>; status = "disabled"; }; -- cgit v1.2.3 From 9d955478a89b4a1ff4e7442216f2822dee8fde73 Mon Sep 17 00:00:00 2001 From: Dafna Hirschfeld Date: Thu, 3 Sep 2020 16:28:19 +0200 Subject: arm64: dts: mt8173-elm: fix supported values for regulator-allowed-modes of da9211 According to the datasheet the allowed modes for the da9211 regulator are sync and auto mode. This should be changed in the devicetree. This also fix an error message 'BUCKA: invalid regulator-allowed-modes element 0' since value 0 is invalid. Fixes: 689b937beddeb ("arm64: dts: mediatek: add mt8173 elm and hana board") Signed-off-by: Dafna Hirschfeld Tested-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20200903142819.24487-1-dafna.hirschfeld@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index a5a12b2599a4..bdec719a6b62 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include "mt8173.dtsi" @@ -294,7 +295,8 @@ regulator-max-microamp = <4400000>; regulator-ramp-delay = <10000>; regulator-always-on; - regulator-allowed-modes = <0 1>; + regulator-allowed-modes = ; }; da9211_vgpu_reg: BUCKB { -- cgit v1.2.3 From c0d66c560ea23615c6d049547154c1a0f7f633c2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 4 Sep 2020 13:00:00 +0200 Subject: arm: dts: mt7623: move display nodes to separate mt7623n.dtsi mt7623a has no graphics support so move nodes from generic mt7623.dtsi to mt7623n.dtsi Fixes: 1f6ed2245946 ("arm: dts: mt7623: add Mali-450 device node") Suggested-by: David Woodhouse Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20200904110002.88966-3-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 123 ----------------------- arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 2 +- arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 2 +- arch/arm/boot/dts/mt7623n.dtsi | 134 ++++++++++++++++++++++++++ 4 files changed, 136 insertions(+), 125 deletions(-) create mode 100644 arch/arm/boot/dts/mt7623n.dtsi diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 3a6b856e5b74..aea6809500d7 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -14,7 +14,6 @@ #include #include #include -#include #include #include @@ -297,17 +296,6 @@ clock-names = "system-clk", "rtc-clk"; }; - smi_common: smi@1000c000 { - compatible = "mediatek,mt7623-smi-common", - "mediatek,mt2701-smi-common"; - reg = <0 0x1000c000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_SMI>, - <&mmsys CLK_MM_SMI_COMMON>, - <&infracfg CLK_INFRA_SMI>; - clock-names = "apb", "smi", "async"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - pwrap: pwrap@1000d000 { compatible = "mediatek,mt7623-pwrap", "mediatek,mt2701-pwrap"; @@ -339,17 +327,6 @@ reg = <0 0x10200100 0 0x1c>; }; - iommu: mmsys_iommu@10205000 { - compatible = "mediatek,mt7623-m4u", - "mediatek,mt2701-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2>; - #iommu-cells = <1>; - }; - efuse: efuse@10206000 { compatible = "mediatek,mt7623-efuse", "mediatek,mt8173-efuse"; @@ -725,94 +702,6 @@ status = "disabled"; }; - g3dsys: syscon@13000000 { - compatible = "mediatek,mt7623-g3dsys", - "mediatek,mt2701-g3dsys", - "syscon"; - reg = <0 0x13000000 0 0x200>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mali: gpu@13040000 { - compatible = "mediatek,mt7623-mali", "arm,mali-450"; - reg = <0 0x13040000 0 0x30000>; - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", - "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", - "pp"; - clocks = <&topckgen CLK_TOP_MMPLL>, - <&g3dsys CLK_G3DSYS_CORE>; - clock-names = "bus", "core"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; - resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt7623-mmsys", - "mediatek,mt2701-mmsys", - "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb0: larb@14010000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x14010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <0>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt7623-imgsys", - "mediatek,mt2701-imgsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <2>; - clocks = <&imgsys CLK_IMG_SMI_COMM>, - <&imgsys CLK_IMG_SMI_COMM>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - }; - - jpegdec: jpegdec@15004000 { - compatible = "mediatek,mt7623-jpgdec", - "mediatek,mt2701-jpgdec"; - reg = <0 0x15004000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; - iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, - <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; - }; - vdecsys: syscon@16000000 { compatible = "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", @@ -821,18 +710,6 @@ #clock-cells = <1>; }; - larb1: larb@16010000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <1>; - clocks = <&vdecsys CLK_VDEC_CKGEN>, - <&vdecsys CLK_VDEC_LARB>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; - }; - hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 2b760f90f38c..344f8c65c4aa 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -6,7 +6,7 @@ /dts-v1/; #include -#include "mt7623.dtsi" +#include "mt7623n.dtsi" #include "mt6323.dtsi" / { diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index 0447748f9fa0..f8efcc364bc3 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include "mt7623.dtsi" +#include "mt7623n.dtsi" #include "mt6323.dtsi" / { diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi new file mode 100644 index 000000000000..a47e82468895 --- /dev/null +++ b/arch/arm/boot/dts/mt7623n.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2017-2020 MediaTek Inc. + * Author: Sean Wang + * Ryder Lee + * + */ + +#include "mt7623.dtsi" +#include + +/ { + g3dsys: syscon@13000000 { + compatible = "mediatek,mt7623-g3dsys", + "mediatek,mt2701-g3dsys", + "syscon"; + reg = <0 0x13000000 0 0x200>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mali: gpu@13040000 { + compatible = "mediatek,mt7623-mali", "arm,mali-450"; + reg = <0 0x13040000 0 0x30000>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", + "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", + "pp"; + clocks = <&topckgen CLK_TOP_MMPLL>, + <&g3dsys CLK_G3DSYS_CORE>; + clock-names = "bus", "core"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; + resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt7623-mmsys", + "mediatek,mt2701-mmsys", + "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb0: larb@14010000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x14010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + larb1: larb@16010000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKGEN>, + <&vdecsys CLK_VDEC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + clocks = <&imgsys CLK_IMG_SMI_COMM>, + <&imgsys CLK_IMG_SMI_COMM>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt7623-imgsys", + "mediatek,mt2701-imgsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + iommu: mmsys_iommu@10205000 { + compatible = "mediatek,mt7623-m4u", + "mediatek,mt2701-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2>; + #iommu-cells = <1>; + }; + + jpegdec: jpegdec@15004000 { + compatible = "mediatek,mt7623-jpgdec", + "mediatek,mt2701-jpgdec"; + reg = <0 0x15004000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; + }; + + smi_common: smi@1000c000 { + compatible = "mediatek,mt7623-smi-common", + "mediatek,mt2701-smi-common"; + reg = <0 0x1000c000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_SMI>, + <&mmsys CLK_MM_SMI_COMMON>, + <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi", "async"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; +}; -- cgit v1.2.3 From 2c78f4bd2b67225ca396f0b37249cad271301142 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Fri, 4 Sep 2020 13:00:01 +0200 Subject: arm: dts: mt7623: add display subsystem related device nodes Add display subsystem related device nodes for MT7623. Signed-off-by: chunhui dai Signed-off-by: Bibby Hsieh Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich Tested-by: Frank Wunderlich Cc: Chun-Kuang Hu Link: https://lore.kernel.org/r/20200904110002.88966-4-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 72 +++++++++++ arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 72 +++++++++++ arch/arm/boot/dts/mt7623n.dtsi | 172 ++++++++++++++++++++++++++ 3 files changed, 316 insertions(+) diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 344f8c65c4aa..f41f221e56ca 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -21,6 +21,19 @@ stdout-path = "serial2:115200n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + cpus { cpu@0 { proc-supply = <&mt6323_vproc_reg>; @@ -114,10 +127,18 @@ }; }; +&bls { + status = "okay"; +}; + &btif { status = "okay"; }; +&cec { + status = "okay"; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -128,6 +149,21 @@ status = "okay"; }; +&dpi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; +}; + ð { status = "okay"; @@ -199,6 +235,42 @@ }; }; +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index f8efcc364bc3..1b9b9a8145a7 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -24,6 +24,19 @@ stdout-path = "serial2:115200n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + cpus { cpu@0 { proc-supply = <&mt6323_vproc_reg>; @@ -106,10 +119,18 @@ }; }; +&bls { + status = "okay"; +}; + &btif { status = "okay"; }; +&cec { + status = "okay"; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -120,6 +141,21 @@ status = "okay"; }; +&dpi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; +}; + ð { status = "okay"; @@ -203,6 +239,42 @@ }; }; +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi index a47e82468895..1880ac9e32cf 100644 --- a/arch/arm/boot/dts/mt7623n.dtsi +++ b/arch/arm/boot/dts/mt7623n.dtsi @@ -10,6 +10,11 @@ #include / { + aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + g3dsys: syscon@13000000 { compatible = "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", @@ -131,4 +136,171 @@ clock-names = "apb", "smi", "async"; power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; }; + + ovl: ovl@14007000 { + compatible = "mediatek,mt7623-disp-ovl", + "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma@14008000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + mediatek,larb = <&larb0>; + }; + + wdma@14009000 { + compatible = "mediatek,mt7623-disp-wdma", + "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + mediatek,larb = <&larb0>; + }; + + bls: pwm@1400a000 { + compatible = "mediatek,mt7623-disp-pwm", + "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, + <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + color: color@1400b000 { + compatible = "mediatek,mt7623-disp-color", + "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi: dsi@1400c000 { + compatible = "mediatek,mt7623-dsi", + "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex@1400e000 { + compatible = "mediatek,mt7623-disp-mutex", + "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + + rdma1: rdma@14012000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + + dpi0: dpi@14014000 { + compatible = "mediatek,mt7623-dpi", + "mediatek,mt2701-dpi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI1_DIGL>, + <&mmsys CLK_MM_DPI1_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + + hdmi0: hdmi@14015000 { + compatible = "mediatek,mt7623-hdmi", + "mediatek,mt2701-hdmi"; + reg = <0 0x14015000 0 0x400>; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLL>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + cec = <&cec>; + status = "disabled"; + }; + + mipi_tx0: mipi-dphy@10010000 { + compatible = "mediatek,mt7623-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + cec: cec@10012000 { + compatible = "mediatek,mt7623-cec", + "mediatek,mt8173-cec"; + reg = <0 0x10012000 0 0xbc>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_CEC>; + status = "disabled"; + }; + + hdmi_phy: phy@10209100 { + compatible = "mediatek,mt7623-hdmi-phy", + "mediatek,mt2701-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + hdmiddc0: i2c@11013000 { + compatible = "mediatek,mt7623-hdmi-ddc", + "mediatek,mt8173-hdmi-ddc"; + interrupts = ; + reg = <0 0x11013000 0 0x1C>; + clocks = <&pericfg CLK_PERI_I2C3>; + clock-names = "ddc-i2c"; + status = "disabled"; + }; +}; + +&pio { + hdmi_pins_a: hdmi-default { + pins-hdmi { + pinmux = ; + input-enable; + bias-pull-down; + }; + }; + + hdmi_ddc_pins_a: hdmi_ddc-default { + pins-hdmi-ddc { + pinmux = , + ; + }; + }; }; -- cgit v1.2.3 From 8cf333f8367af98b395ee4c32d26eba2f3487127 Mon Sep 17 00:00:00 2001 From: Alex Ryabchenko Date: Fri, 4 Sep 2020 13:00:02 +0200 Subject: arm: dts: mt7623: add lima related regulator GPU needs additional regulator, add it to devicetree of bpi-r2 Signed-off-by: Alex Ryabchenko Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20200904110002.88966-5-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index f41f221e56ca..826912545ef1 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -79,6 +79,13 @@ regulator-always-on; }; + reg_vgpu: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed_vgpu"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -283,6 +290,11 @@ status = "okay"; }; +&mali { + mali-supply = <®_vgpu>; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc0_pins_default>; @@ -402,4 +414,3 @@ &u3phy2 { status = "okay"; }; - -- cgit v1.2.3 From ad1edcdf477d4e7228d87018ed27d8f7012f6a84 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:17 +0200 Subject: dt-bindings: samsung: pmu: document S5Pv210 Add compatible for the Samsung S5Pv210 SoC PMU. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-2-krzk@kernel.org --- Documentation/devicetree/bindings/arm/samsung/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml index 686c13c14e32..f67c8851530e 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml @@ -24,6 +24,7 @@ select: - samsung,exynos5420-pmu - samsung,exynos5433-pmu - samsung,exynos7-pmu + - samsung-s5pv210-pmu required: - compatible @@ -40,6 +41,7 @@ properties: - samsung,exynos5420-pmu - samsung,exynos5433-pmu - samsung,exynos7-pmu + - samsung-s5pv210-pmu - const: syscon reg: -- cgit v1.2.3 From 2c6658c607a3af2ed7bd41dc57a3dd31537d023e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:20 +0200 Subject: ARM: dts: s5pv210: fix pinctrl property of "vibrator-en" regulator in Aries Fix typo in pinctrl property of "vibrator-en" fixed regulator in Aries family of boards. The error caused lack of pin configuration for the GPIO used in vibrator. Fixes: 04568cb58a43 ("ARM: dts: s5pv210: Disable pull for vibrator enable GPIO on Aries boards") Signed-off-by: Krzysztof Kozlowski Cc: Link: https://lore.kernel.org/r/20200907161141.31034-5-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aries.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index a3f83f668ce1..6ba23562da46 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -59,7 +59,7 @@ gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctr-0 = <&vibrator_ena>; + pinctrl-0 = <&vibrator_ena>; }; touchkey_vdd: regulator-fixed-1 { -- cgit v1.2.3 From ea4e792f3c8931fffec4d700cf6197d84e9f35a6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:21 +0200 Subject: ARM: dts: s5pv210: remove DMA controller bus node name to fix dtschema warnings There is no need to keep DMA controller nodes under AMBA bus node. Remove the "amba" node to fix dtschema warnings like: amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Krzysztof Kozlowski Tested-by: Jonathan Bakker Link: https://lore.kernel.org/r/20200907161141.31034-6-krzk@kernel.org --- arch/arm/boot/dts/s5pv210.dtsi | 49 ++++++++++++++++++------------------------ 1 file changed, 21 insertions(+), 28 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 1b0ee884e91d..84e4447931de 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -128,35 +128,28 @@ }; }; - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - pdma0: dma@e0900000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0900000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <19>; - clocks = <&clocks CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; + pdma0: dma@e0900000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xe0900000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <19>; + clocks = <&clocks CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; - pdma1: dma@e0a00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0a00000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <20>; - clocks = <&clocks CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; + pdma1: dma@e0a00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xe0a00000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <20>; + clocks = <&clocks CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; }; adc: adc@e1700000 { -- cgit v1.2.3 From d38cae370e5f2094cbc38db3082b8e9509ae52ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:22 +0200 Subject: ARM: dts: s5pv210: move fixed clocks under root node The fixed clocks are kept under dedicated 'external-clocks' node, thus a fake 'reg' was added. This is not correct with dtschema as fixed-clock binding does not have a 'reg' property. Moving fixed clocks out of 'soc' to root node fixes multiple dtbs_check warnings: external-clocks: $nodename:0: 'external-clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' external-clocks: #size-cells:0:0: 0 is not one of [1, 2] external-clocks: oscillator@0:reg:0: [0] is too short external-clocks: oscillator@1:reg:0: [1] is too short external-clocks: 'ranges' is a required property oscillator@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Tested-by: Jonathan Bakker Link: https://lore.kernel.org/r/20200907161141.31034-7-krzk@kernel.org --- arch/arm/boot/dts/s5pv210.dtsi | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 84e4447931de..5c760a6d7955 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -52,34 +52,26 @@ }; }; + xxti: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xxti"; + #clock-cells = <0>; + }; + + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xusbxti"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - external-clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - xxti: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <0>; - clock-output-names = "xxti"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - clock-output-names = "xusbxti"; - #clock-cells = <0>; - }; - }; - onenand: onenand@b0600000 { compatible = "samsung,s5pv210-onenand"; reg = <0xb0600000 0x2000>, -- cgit v1.2.3 From bb98fff84ad1ea321823759edaba573a16fa02bd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:23 +0200 Subject: ARM: dts: s5pv210: move PMU node out of clock controller The Power Management Unit (PMU) is a separate device which has little common with clock controller. Moving it to one level up (from clock controller child to SoC) allows to remove fake simple-bus compatible and dtbs_check warnings like: clock-controller@e0100000: $nodename:0: 'clock-controller@e0100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Krzysztof Kozlowski Tested-by: Jonathan Bakker Link: https://lore.kernel.org/r/20200907161141.31034-8-krzk@kernel.org --- arch/arm/boot/dts/s5pv210.dtsi | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 5c760a6d7955..46221a5c8ce5 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -92,19 +92,16 @@ }; clocks: clock-controller@e0100000 { - compatible = "samsung,s5pv210-clock", "simple-bus"; + compatible = "samsung,s5pv210-clock"; reg = <0xe0100000 0x10000>; clock-names = "xxti", "xusbxti"; clocks = <&xxti>, <&xusbxti>; #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + }; - pmu_syscon: syscon@e0108000 { - compatible = "samsung-s5pv210-pmu", "syscon"; - reg = <0xe0108000 0x8000>; - }; + pmu_syscon: syscon@e0108000 { + compatible = "samsung-s5pv210-pmu", "syscon"; + reg = <0xe0108000 0x8000>; }; pinctrl0: pinctrl@e0200000 { -- cgit v1.2.3 From 6c17a2974abf68a58517f75741b15c4aba42b4b8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:24 +0200 Subject: ARM: dts: s5pv210: remove dedicated 'audio-subsystem' node The 'audio-subsystem' node is an artificial creation, not representing real hardware. The hardware is described by its nodes - AUDSS clock controller and I2S0. Remove the 'audio-subsystem' node along with its undocumented compatible to fix dtbs_check warnings like: audio-subsystem: $nodename:0: 'audio-subsystem' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Krzysztof Kozlowski Tested-by: Jonathan Bakker Link: https://lore.kernel.org/r/20200907161141.31034-9-krzk@kernel.org --- arch/arm/boot/dts/s5pv210.dtsi | 65 +++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 36 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 46221a5c8ce5..2871351ab907 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -223,43 +223,36 @@ status = "disabled"; }; - audio-subsystem { - compatible = "samsung,s5pv210-audss", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_audss: clock-controller@eee10000 { - compatible = "samsung,s5pv210-audss-clock"; - reg = <0xeee10000 0x1000>; - clock-names = "hclk", "xxti", - "fout_epll", - "sclk_audio0"; - clocks = <&clocks DOUT_HCLKP>, <&xxti>, - <&clocks FOUT_EPLL>, - <&clocks SCLK_AUDIO0>; - #clock-cells = <1>; - }; + clk_audss: clock-controller@eee10000 { + compatible = "samsung,s5pv210-audss-clock"; + reg = <0xeee10000 0x1000>; + clock-names = "hclk", "xxti", + "fout_epll", + "sclk_audio0"; + clocks = <&clocks DOUT_HCLKP>, <&xxti>, + <&clocks FOUT_EPLL>, + <&clocks SCLK_AUDIO0>; + #clock-cells = <1>; + }; - i2s0: i2s@eee30000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0xeee30000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <16>; - dma-names = "rx", "tx", "tx-sec"; - dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; - clock-names = "iis", - "i2s_opclk0", - "i2s_opclk1"; - clocks = <&clk_audss CLK_I2S>, - <&clk_audss CLK_I2S>, - <&clk_audss CLK_DOUT_AUD_BUS>; - samsung,idma-addr = <0xc0010000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; + i2s0: i2s@eee30000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0xeee30000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <16>; + dma-names = "rx", "tx", "tx-sec"; + dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; + clock-names = "iis", + "i2s_opclk0", + "i2s_opclk1"; + clocks = <&clk_audss CLK_I2S>, + <&clk_audss CLK_I2S>, + <&clk_audss CLK_DOUT_AUD_BUS>; + samsung,idma-addr = <0xc0010000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + #sound-dai-cells = <0>; + status = "disabled"; }; i2s1: i2s@e2100000 { -- cgit v1.2.3 From e59cb2fb3b33605cc75fab9fb0dd8cf2eee3019e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:26 +0200 Subject: ARM: dts: s5pv210: add RTC 32 KHz clock in Aquilla The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However there is no such clock provider but rather a regulator driver which registers the clock as a regulator. This is an old driver which will not be updated so add a workaround - a fixed-clock to fill missing clock phandle reference in S3C RTC. This fixes dtbs_check warnings: rtc@e2800000: clocks: [[2, 145]] is too short rtc@e2800000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-11-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aquila.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 14969b6529e8..eaeb0e921aaa 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -32,6 +32,13 @@ 0x40000000 0x18000000>; }; + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -228,6 +235,11 @@ regulator-always-on; }; + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + vichg_reg: ENVICHG { regulator-name = "VICHG"; }; @@ -326,6 +338,11 @@ status = "okay"; }; +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci0 { bus-width = <4>; non-removable; -- cgit v1.2.3 From 086c4498b0cc87fdb09188f3da7056e898814948 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:27 +0200 Subject: ARM: dts: s5pv210: add RTC 32 KHz clock in Aries family The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However there is no such clock provider but rather a regulator driver which registers the clock as a regulator. This is an old driver which will not be updated so add a workaround - a fixed-clock to fill missing clock phandle reference in S3C RTC. This fixes dtbs_check warnings: rtc@e2800000: clocks: [[2, 145]] is too short rtc@e2800000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Tested-by: Jonathan Bakker Link: https://lore.kernel.org/r/20200907161141.31034-12-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aries.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 6ba23562da46..86c3b26fd21e 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -47,6 +47,13 @@ }; }; + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + bt_codec: bt_sco { compatible = "linux,bt-sco"; #sound-dai-cells = <0>; @@ -825,6 +832,11 @@ samsung,pwm-outputs = <1>; }; +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci1 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From ebb105b59c7566a249cf0ee1cfc86386f04cd442 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:28 +0200 Subject: ARM: dts: s5pv210: add RTC 32 KHz clock in Goni The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However there is no such clock provider but rather a regulator driver which registers the clock as a regulator. This is an old driver which will not be updated so add a workaround - a fixed-clock to fill missing clock phandle reference in S3C RTC. This fixes dtbs_check warnings: rtc@e2800000: clocks: [[2, 145]] is too short rtc@e2800000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-13-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-goni.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index fbbd93707404..c8714bf0b6e4 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -33,6 +33,13 @@ 0x50000000 0x08000000>; }; + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -224,6 +231,11 @@ regulator-max-microvolt = <1200000>; regulator-always-on; }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; }; }; }; @@ -308,6 +320,11 @@ status = "okay"; }; +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci0 { bus-width = <4>; non-removable; -- cgit v1.2.3 From 37dea4fa9888e72bc7239c1c495be92901cd3e7f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:29 +0200 Subject: ARM: dts: s5pv210: add RTC 32 KHz clock in SMDKC110 The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However the PMIC is not described in DTS at all so at least add a workaround to model its clock with a fixed-clock. This fixes dtbs_check warnings: rtc@e2800000: clocks: [[2, 145]] is too short rtc@e2800000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-14-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-smdkc110.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/s5pv210-smdkc110.dts index e5aec6c526fb..0c623b78af72 100644 --- a/arch/arm/boot/dts/s5pv210-smdkc110.dts +++ b/arch/arm/boot/dts/s5pv210-smdkc110.dts @@ -30,6 +30,13 @@ device_type = "memory"; reg = <0x20000000 0x20000000>; }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; &xusbxti { @@ -54,6 +61,8 @@ &rtc { status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &i2c0 { -- cgit v1.2.3 From 7260b363457a22b8723d5cbc43fee67397896d07 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:30 +0200 Subject: ARM: dts: s5pv210: add RTC 32 KHz clock in SMDKV210 The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However the PMIC is not described in DTS at all so at least add a workaround to model its clock with a fixed-clock. This fixes dtbs_check warnings: rtc@e2800000: clocks: [[2, 145]] is too short rtc@e2800000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-15-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 84b38f185199..1f20622da719 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -31,6 +31,13 @@ reg = <0x20000000 0x40000000>; }; + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + ethernet@18000000 { compatible = "davicom,dm9000"; reg = <0xA8000000 0x2 0xA8000002 0x2>; @@ -147,6 +154,8 @@ &rtc { status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &sdhci0 { -- cgit v1.2.3 From fd595722c1048c021a4c0427afbb807d4a5dbe0b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:31 +0200 Subject: ARM: dts: s5pv210: add RTC 32 KHz clock in Torbreck The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However the PMIC is not described in DTS at all so at least add a workaround to model its clock with a fixed-clock. This fixes dtbs_check warnings: rtc@e2800000: clocks: [[2, 145]] is too short rtc@e2800000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-16-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-torbreck.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/s5pv210-torbreck.dts index cd25e72ccd84..e18259737684 100644 --- a/arch/arm/boot/dts/s5pv210-torbreck.dts +++ b/arch/arm/boot/dts/s5pv210-torbreck.dts @@ -30,6 +30,13 @@ device_type = "memory"; reg = <0x20000000 0x20000000>; }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; &xusbxti { @@ -54,6 +61,8 @@ &rtc { status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &sdhci0 { -- cgit v1.2.3 From 0e2774e180817bd2925f508a48e1e2a28aea5265 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:32 +0200 Subject: ARM: dts: s5pv210: use defines for GPIO flags in Aquila Replace hard-coded flags with defines for readability. No functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-17-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aquila.dts | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index eaeb0e921aaa..25d4ab4a52c5 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -11,6 +11,7 @@ */ /dts-v1/; +#include #include #include "s5pv210.dtsi" @@ -50,7 +51,7 @@ regulator-name = "V_TF_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&mp05 4 0>; + gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -73,8 +74,8 @@ i2c_pmic: i2c-pmic { compatible = "i2c-gpio"; - gpios = <&gpj4 0 0>, /* sda */ - <&gpj4 3 0>; /* scl */ + gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpj4 3 GPIO_ACTIVE_HIGH>; /* scl */ i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; @@ -84,13 +85,13 @@ reg = <0x66>; max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>, - <&gph0 4 0>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, <1200000>, <1200000>; max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; regulators { -- cgit v1.2.3 From 0f2e43cf3d638312bbaca0f23b96f1d5ced249f1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:33 +0200 Subject: ARM: dts: s5pv210: use defines for GPIO flags in Goni Replace hard-coded flags with defines for readability. No functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-18-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-goni.dts | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index c8714bf0b6e4..77d1c5144afd 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -11,6 +11,7 @@ */ /dts-v1/; +#include #include #include "s5pv210.dtsi" @@ -51,7 +52,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; reg = <0>; - gpio = <&mp05 4 0>; + gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -77,15 +78,15 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; reg = <3>; - gpio = <&gpj1 3 0>; + gpio = <&gpj1 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; i2c_pmic: i2c-pmic { compatible = "i2c-gpio"; - gpios = <&gpj4 0 0>, /* sda */ - <&gpj4 3 0>; /* scl */ + gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpj4 3 GPIO_ACTIVE_HIGH>; /* scl */ i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; @@ -95,13 +96,13 @@ reg = <0x66>; max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>, - <&gph0 4 0>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, <1200000>, <1200000>; max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; regulators { @@ -395,8 +396,8 @@ clock-frequency = <16000000>; clocks = <&camera 0>; clock-names = "mclk"; - nreset-gpios = <&gpb 2 0>; - nstby-gpios = <&gpb 0 0>; + nreset-gpios = <&gpb 2 GPIO_ACTIVE_HIGH>; + nstby-gpios = <&gpb 0 GPIO_ACTIVE_HIGH>; port { noon010pc30_ep: endpoint { -- cgit v1.2.3 From c272f1cc9492d61dac362d2064ec41ca97fcb1e2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:34 +0200 Subject: ARM: dts: s5pv210: use defines for IRQ flags in SMDKV210 Replace hard-coded flags with defines for readability. No functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-19-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 1f20622da719..1e1570d66d89 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -15,6 +15,7 @@ */ /dts-v1/; +#include #include #include "s5pv210.dtsi" @@ -42,7 +43,7 @@ compatible = "davicom,dm9000"; reg = <0xA8000000 0x2 0xA8000002 0x2>; interrupt-parent = <&gph1>; - interrupts = <1 4>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; local-mac-address = [00 00 de ad be ef]; davicom,no-eeprom; }; -- cgit v1.2.3 From b5c528ba9759294b658b050c8a0f2a0f22aaa4d3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:35 +0200 Subject: ARM: dts: s5pv210: use defines for IRQ flags in Goni Replace hard-coded flags with defines for readability. No functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-20-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-goni.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index 77d1c5144afd..20f1c2773805 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -12,6 +12,7 @@ /dts-v1/; #include +#include #include #include "s5pv210.dtsi" @@ -366,7 +367,7 @@ compatible = "atmel,maxtouch"; reg = <0x4a>; interrupt-parent = <&gpj0>; - interrupts = <5 2>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; atmel,x-line = <17>; atmel,y-line = <11>; -- cgit v1.2.3 From 1ed7f6d0bab2f1794f1eb4ed032e90575552fd21 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:40 +0200 Subject: ARM: dts: s5pv210: align SPI GPIO node name with dtschema in Aries The device tree schema expects SPI controller to be named "spi", otherwise dtbs_check complain with a warning like: spi-gpio-0: $nodename:0: 'spi-gpio-0' does not match '^spi(@.*|-[0-9a-f])*$' Signed-off-by: Krzysztof Kozlowski Tested-by: Jonathan Bakker Link: https://lore.kernel.org/r/20200907161141.31034-25-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aries.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 86c3b26fd21e..bd4450dbdcb6 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -545,7 +545,7 @@ value = <0x5200>; }; - spi_lcd: spi-gpio-0 { + spi_lcd: spi-2 { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From adfe14797e17b2538d78eb2cb1eef5fd2fb74125 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 10 Sep 2020 12:41:43 +0930 Subject: ARM: dts: rainier: Disable internal pull-downs on eMMC pins There's a veritable tug-of-war going on in the design, so disable one of the warring parties. Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20200910031143.2997298-1-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 1fa233d2da26..21ae880c7530 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -180,6 +180,10 @@ status = "okay"; }; +&pinctrl_emmc_default { + bias-disable; +}; + &emmc { status = "okay"; }; -- cgit v1.2.3 From 3b4a0564553804ed7783b8931a39b0e3a255f801 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 4 Sep 2020 09:58:11 +0300 Subject: ARM: dts: n9, n950: Remove nokia,nvm-size property Remove nokia,nvm-size property as it is no longer needed. The driver can nowadays figure out the size so do not specify it in DT. Signed-off-by: Sakari Ailus Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n9.dts | 1 - arch/arm/boot/dts/omap3-n950.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts index 2495a696cec6..d211bcc31174 100644 --- a/arch/arm/boot/dts/omap3-n9.dts +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -23,7 +23,6 @@ vana-supply = <&vaux3>; clocks = <&isp 0>; clock-frequency = <9600000>; - nokia,nvm-size = <(16 * 64)>; flash-leds = <&as3645a_flash &as3645a_indicator>; port { smia_1_1: endpoint { diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 80cf4e1177da..0f5da73d620c 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -76,7 +76,6 @@ vana-supply = <&vaux3>; clocks = <&isp 0>; clock-frequency = <9600000>; - nokia,nvm-size = <(16 * 64)>; flash-leds = <&as3645a_flash &as3645a_indicator>; port { smia_1_1: endpoint { -- cgit v1.2.3 From fe93b72551ee59afddbd0a8ae23dc152f9e61759 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 21:38:59 +0200 Subject: ARM: dts: omap: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-evm-ui.dtsi | 4 ++-- arch/arm/boot/dts/am3517-evm.dts | 2 +- arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi | 2 +- arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi | 2 +- arch/arm/boot/dts/omap3-beagle-xm.dts | 4 ++-- arch/arm/boot/dts/omap3-beagle.dts | 6 +++--- arch/arm/boot/dts/omap3-cm-t3517.dts | 2 +- arch/arm/boot/dts/omap3-cm-t3530.dts | 2 +- arch/arm/boot/dts/omap3-cm-t3730.dts | 2 +- arch/arm/boot/dts/omap3-cm-t3x.dtsi | 4 ++-- arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 4 ++-- arch/arm/boot/dts/omap3-gta04.dtsi | 8 ++++---- arch/arm/boot/dts/omap3-ha-lcd.dts | 2 +- arch/arm/boot/dts/omap3-igep0020-common.dtsi | 2 +- arch/arm/boot/dts/omap3-n900.dts | 6 +++--- arch/arm/boot/dts/omap3-n950.dts | 4 ++-- arch/arm/boot/dts/omap3-overo-common-dvi.dtsi | 2 +- arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi | 2 +- arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi | 2 +- arch/arm/boot/dts/omap3-pandora-common.dtsi | 4 ++-- arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi | 2 +- arch/arm/boot/dts/omap3-thunder.dts | 2 +- arch/arm/boot/dts/omap34xx.dtsi | 2 +- arch/arm/boot/dts/omap36xx.dtsi | 2 +- arch/arm/boot/dts/omap4-duovero-parlor.dts | 4 ++-- arch/arm/boot/dts/omap4-panda-common.dtsi | 6 +++--- arch/arm/boot/dts/omap4-sdp.dts | 8 ++++---- arch/arm/boot/dts/omap5-board-common.dtsi | 4 ++-- arch/arm/boot/dts/omap5-cm-t54.dts | 6 +++--- 29 files changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi index 250c40da2535..7d8f32bf70db 100644 --- a/arch/arm/boot/dts/am3517-evm-ui.dtsi +++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi @@ -183,14 +183,14 @@ }; &mcbsp1 { - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_pins>; }; &mcbsp2 { - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 04f20e7680b1..0d2fac98ce7d 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -176,7 +176,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi index 395e05f10d36..7d0468a23781 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi @@ -79,7 +79,7 @@ }; &dss { - status = "ok"; + status = "okay"; vdds_dsi-supply = <&vpll2>; vdda_video-supply = <&video_reg>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi index b0f6613e6d54..533a47bc4a53 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi @@ -115,7 +115,7 @@ }; &dss { - status = "ok"; + status = "okay"; vdds_dsi-supply = <&vpll2>; vdda_video-supply = <&vpll2>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 05077f3c75cd..252507cf300b 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -389,7 +389,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < @@ -406,7 +406,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 79bc710c05fc..f9f34b8458e9 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -386,7 +386,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; @@ -400,7 +400,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; @@ -413,7 +413,7 @@ }; &gpmc { - status = "ok"; + status = "okay"; ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ /* Chip select 0 */ diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index 632f52efdf98..3b8349094baa 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -147,7 +147,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts index 32dbaeaed147..bc545ee23e71 100644 --- a/arch/arm/boot/dts/omap3-cm-t3530.dts +++ b/arch/arm/boot/dts/omap3-cm-t3530.dts @@ -49,7 +49,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 683819bf0915..48e48b0c8190 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -87,7 +87,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index cdb632df152a..e61b8a2bfb7d 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -246,7 +246,7 @@ }; &venc { - status = "ok"; + status = "okay"; port { venc_out: endpoint { @@ -257,7 +257,7 @@ }; &mcbsp2 { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi index ac3d996cec5c..2c19d6e255bd 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -337,7 +337,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; @@ -361,7 +361,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index ecc45862b4f3..c8745bc800f7 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -822,27 +822,27 @@ }; &mcbsp1 { /* FM Transceiver PCM */ - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_pins>; }; &mcbsp2 { /* TPS65950 I2S */ - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; }; &mcbsp3 { /* Bluetooth PCM */ - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp3_pins>; }; &mcbsp4 { /* GSM voice PCM */ - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp4_pins>; diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts index b3f7f9966c3c..643283f0c3db 100644 --- a/arch/arm/boot/dts/omap3-ha-lcd.dts +++ b/arch/arm/boot/dts/omap3-ha-lcd.dts @@ -100,7 +100,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi index 91caa50b74c4..af8aa5f0feb7 100644 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi @@ -245,7 +245,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index bc24e3dc7cda..32335d4ce478 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -1083,7 +1083,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_sdi_pins>; @@ -1106,7 +1106,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; @@ -1119,7 +1119,7 @@ }; &mcbsp2 { - status = "ok"; + status = "okay"; }; &ssi_port1 { diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 0f5da73d620c..b2f480022ff6 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -204,13 +204,13 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&vdac>; }; &dsi { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dsi_pins>; diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi index c9e62e414abb..339a51fa4119 100644 --- a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi @@ -48,7 +48,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi index 185ce53de0ec..1d6e88f99eb3 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi @@ -76,7 +76,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi index 7fe0f9148232..7e30f9d45790 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi @@ -75,7 +75,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index 150d5be42d27..37608af6c07f 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -702,7 +702,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; @@ -718,7 +718,7 @@ pinctrl-names = "default"; pinctrl-0 = < &dss_dpi_pins >; - status = "ok"; + status = "okay"; vdds_dsi-supply = <&vpll2>; port { diff --git a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi index b8b9fcc41ef1..2dbb687d4df2 100644 --- a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi @@ -46,7 +46,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts index f7930f198ce5..d82cab8e213a 100644 --- a/arch/arm/boot/dts/omap3-thunder.dts +++ b/arch/arm/boot/dts/omap3-thunder.dts @@ -64,7 +64,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index c0dcc75833a8..feaa43b78535 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -183,7 +183,7 @@ }; &ssi { - status = "ok"; + status = "okay"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index fadbf308feff..05fe5ed127b0 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -235,7 +235,7 @@ }; &ssi { - status = "ok"; + status = "okay"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index 4548d87534e3..b294c22177cb 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -171,11 +171,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 3e78caefa2b8..609a8dea946b 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -566,7 +566,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { @@ -577,12 +577,12 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; port { diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 1e02513f8150..afb49a2d6963 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -648,11 +648,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &dsi1 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; port { @@ -678,7 +678,7 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; port { @@ -704,7 +704,7 @@ }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; port { diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index edf1906016c8..d8f13626cfd1 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -743,11 +743,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; /* vdda-supply populated in board specific dts file */ diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index e78d3718f145..ca759b7b8a58 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -653,7 +653,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; @@ -677,12 +677,12 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&ldo4_reg>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo4_reg>; pinctrl-names = "default"; -- cgit v1.2.3 From 0893a701a281633b69d3d1376da2b0e0cab4859c Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 21:48:41 +0200 Subject: ARM: dts: dra7xx: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 6 +++--- arch/arm/boot/dts/am57xx-sbc-am57x.dts | 4 ++-- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra72-evm-common.dtsi | 6 +++--- arch/arm/boot/dts/dra76-evm.dts | 4 ++-- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index b3a0206ebd6c..1809f97d491d 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -582,13 +582,13 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&ldoln_reg>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo4_reg>; port { @@ -599,7 +599,7 @@ }; &pcie1_rc { - status = "ok"; + status = "okay"; gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/am57xx-sbc-am57x.dts index ce5bf1d92eab..beef63e8a005 100644 --- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts +++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts @@ -120,7 +120,7 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&ldoln_reg>; @@ -148,7 +148,7 @@ }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo4_reg>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index a952d934fcf2..bda6f7eeef4f 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -565,7 +565,7 @@ }; &dcan1 { - status = "ok"; + status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 9273a7d6fa29..7506e415b08f 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -467,7 +467,7 @@ }; &dcan1 { - status = "ok"; + status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; @@ -536,11 +536,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; port { hdmi_out: endpoint { diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 803981cc762e..81590ef36937 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -522,12 +522,12 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&ldo5_reg>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo1_reg>; -- cgit v1.2.3 From ca6bfe9721b28b34bb4566f15ad6e7f6b878c8fe Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 21:50:09 +0200 Subject: ARM: dts: am43xx: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- arch/arm/boot/dts/am437x-sbc-t43.dts | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index b28e5c8cd02a..7c1ee35e6a1c 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1024,7 +1024,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/am437x-sbc-t43.dts index 94cf07ea27f7..8ea3780f939d 100644 --- a/arch/arm/boot/dts/am437x-sbc-t43.dts +++ b/arch/arm/boot/dts/am437x-sbc-t43.dts @@ -136,7 +136,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pinctrl_default>; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index de4fc78498a0..76f48ff051e8 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -948,7 +948,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; -- cgit v1.2.3 From 67e97cc60d8a366216d33a9284d9f704dfb331f7 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 7 Sep 2020 23:21:20 +0300 Subject: ARM: dts: am5729: beagleboneai: switch to new cpsw switch drv Switch BeagleBone AI to use new cpsw switch driver. It has one Ext. port only and fits dual_mac mode with no issues. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am5729-beagleboneai.dts | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/am5729-beagleboneai.dts b/arch/arm/boot/dts/am5729-beagleboneai.dts index e9c7f44126e7..149cfafb90bf 100644 --- a/arch/arm/boot/dts/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/am5729-beagleboneai.dts @@ -488,25 +488,29 @@ status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; - phy0: ethernet-phy@1 { + phy0: ethernet-phy@4 { reg = <4>; eee-broken-100tx; eee-broken-1000t; }; }; -&mac { - slaves = <1>; +&mac_sw { status = "okay"; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&phy0>; phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; &ocp { -- cgit v1.2.3 From d56fe359e6b60a1075c61319e18b3315fbf9a960 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 7 Sep 2020 23:21:21 +0300 Subject: ARM: dts: am57xx-idk: switch to new cpsw switch drv Switch all am571/2/4-idk boards to use new cpsw switch driver. Those boards have 2 Ext. port wired and configured in dual_mac mode by default. Hence, dual_mac mode has been preserved the same way between legacy and new driver it's safe to switch drivers. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am571x-idk.dts | 27 --------------------------- arch/arm/boot/dts/am572x-idk.dts | 5 ----- arch/arm/boot/dts/am574x-idk.dts | 5 ----- arch/arm/boot/dts/am57xx-idk-common.dtsi | 14 +++++++++----- 4 files changed, 9 insertions(+), 42 deletions(-) diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 391a92e24472..e81078c2d00d 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -208,30 +208,3 @@ pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; }; - -&mac_sw { - pinctrl-names = "default", "sleep"; - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <ðphy0_sw>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1_sw>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - ethphy0_sw: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1_sw: ethernet-phy@1 { - reg = <1>; - }; -}; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 1a3af4b54308..6504265f3f7e 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -27,8 +27,3 @@ pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; - -&mac { - status = "okay"; - dual_emac; -}; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index c9275d0c62cf..37758761cd88 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -36,11 +36,6 @@ pinctrl-2 = <&mmc2_pins_default>; }; -&mac { - status = "okay"; - dual_emac; -}; - &m_can0 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 1c77006cccd1..9fcb8944aa3e 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -448,19 +448,23 @@ ext-clk-src; }; -&cpsw_emac0 { +&mac_sw { + status = "okay"; +}; + +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { ethphy0: ethernet-phy@0 { reg = <0>; }; -- cgit v1.2.3 From ea952beb292b5a66b3e636c5936b979a3af77cc0 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 7 Sep 2020 23:21:22 +0300 Subject: ARM: dts: beagle-x15: switch to new cpsw switch drv Switch all TI AM5728 BeagleBoard-X15 boards to use new cpsw switch driver. Those boards have 2 Ext. port wired and configured in dual_mac mode by default. Hence, dual_mac mode has been preserved the same way between legacy and new driver it's safe to switch drivers. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index 1809f97d491d..6b82ecf803c5 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -451,7 +451,7 @@ <&dra7_pmx_core 0x3f8>; }; -&davinci_mdio { +&davinci_mdio_sw { phy0: ethernet-phy@1 { reg = <1>; }; @@ -461,21 +461,20 @@ }; }; -&mac { +&mac_sw { status = "okay"; - dual_emac; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&phy0>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <&phy1>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; &mmc1 { -- cgit v1.2.3 From 56d6c721f2dc618b0aa19f457c3e19547390e4a7 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 7 Sep 2020 23:21:23 +0300 Subject: ARM: dts: dra7x-evm: switch to new cpsw switch drv Switch all TI DRA7x boards to use new cpsw switch driver. Those boards configured in dual_mac mode by default. Hence, dual_mac mode has been preserved the same way between legacy and new driver it's safe to switch drivers. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 13 ++++++------- arch/arm/boot/dts/dra71-evm.dts | 14 +++++++------- arch/arm/boot/dts/dra72-evm-common.dtsi | 4 ---- arch/arm/boot/dts/dra72-evm-revc.dts | 14 +++++++------- arch/arm/boot/dts/dra72-evm.dts | 13 +++++++++---- arch/arm/boot/dts/dra76-evm.dts | 14 ++++++-------- 6 files changed, 35 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index bda6f7eeef4f..38530dbb89a0 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -537,24 +537,23 @@ ti,no-idle-on-init; }; -&mac { +&mac_sw { status = "okay"; - dual_emac; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { ethphy0: ethernet-phy@2 { reg = <2>; }; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 10da51bee42f..cad58f733bd6 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -219,26 +219,26 @@ vqmmc-supply = <&evm_1v8_sw>; }; -&mac { +&mac_sw { mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - dual_emac; + status = "okay"; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&dp83867_0>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <&dp83867_1>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { dp83867_0: ethernet-phy@2 { reg = <2>; ti,rx-internal-delay = ; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 7506e415b08f..b65b2dd094d0 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -462,10 +462,6 @@ }; }; -&mac { - status = "okay"; -}; - &dcan1 { status = "okay"; pinctrl-names = "default", "sleep", "active"; diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index 54dab0f212d1..f242b937f88c 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -77,26 +77,26 @@ interrupts = <30 IRQ_TYPE_EDGE_FALLING>; }; -&mac { +&mac_sw { mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - dual_emac; + status = "okay"; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&dp83867_0>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <&dp83867_1>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { dp83867_0: ethernet-phy@2 { reg = <2>; ti,rx-internal-delay = ; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 6ea9936f7d9c..5f62f92eb96c 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -69,17 +69,22 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; }; -&mac { - slaves = <1>; +&mac_sw { mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; + status = "okay"; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; -&davinci_mdio { +&davinci_mdio_sw { ethphy0: ethernet-phy@3 { reg = <3>; }; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 81590ef36937..9bd01ae40b1d 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -475,25 +475,23 @@ status = "disabled"; }; -&mac { +&mac_sw { status = "okay"; - - dual_emac; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&dp83867_0>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <&dp83867_1>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { dp83867_0: ethernet-phy@2 { reg = <2>; ti,rx-internal-delay = ; -- cgit v1.2.3 From fa46e7e7dc6dc4aba2620c79f1c8ac59bc5a1dd3 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 7 Sep 2020 23:21:24 +0300 Subject: ARM: dts: am57xx-cl-som-am57x: switch to new cpsw switch drv Switch CompuLab CL-SOM-AM57x board to use new cpsw switch driver. Those board configured in dual_mac mode by default. Hence, dual_mac mode has been preserved the same way between legacy and new driver it's safe to switch drivers. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 34ca761aeded..0d5fe2bfb683 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -546,27 +546,26 @@ }; }; -&mac { +&mac_sw { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_pins_default>; pinctrl-1 = <&cpsw_pins_sleep>; - dual_emac; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <0>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_pins_default>; pinctrl-1 = <&davinci_mdio_pins_sleep>; -- cgit v1.2.3 From ec9bc5bedb2000902c3fcf3a844964d099231881 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 7 Sep 2020 23:21:25 +0300 Subject: ARM: dts: dra7: drop legacy cpsw dt node All dra7/am57 boards converted to use new driver, so drop legacy cpsw dt node. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 54 ------------------------------------------ arch/arm/boot/dts/dra7.dtsi | 4 ++-- 2 files changed, 2 insertions(+), 56 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 27a6a83cc60c..703ba6a26272 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -3038,60 +3038,6 @@ */ ti,no-idle; - mac: ethernet@0 { - compatible = "ti,dra7-cpsw","ti,cpsw"; - clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x784CFE14>; - cpts_clock_shift = <29>; - reg = <0x0 0x1000 - 0x1200 0x2e00>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * rx_thresh_pend - * rx_pend - * tx_pend - * misc_pend - */ - interrupts = , - , - , - ; - ranges = <0 0 0x4000>; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&gmac_main_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - }; - - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; - }; - - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; - }; - }; - mac_sw: switch@0 { compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; reg = <0x0 0x4000>; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index cca6b123856f..4e1bbc0198eb 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -37,8 +37,8 @@ serial7 = &uart8; serial8 = &uart9; serial9 = &uart10; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; d_can0 = &dcan1; d_can1 = &dcan2; spi0 = &qspi; -- cgit v1.2.3 From 1652dbf7363a6c3e9a3ea96da550f6003fa8e01f Mon Sep 17 00:00:00 2001 From: Eddie Huang Date: Tue, 12 Nov 2019 19:03:27 +0800 Subject: arm64: dts: mt8183: add scp node Add scp node to mt8183 and mt8183-evb Signed-off-by: Erin Lo Signed-off-by: Pi-Hsun Shih Signed-off-by: Eddie Huang Link: https://lore.kernel.org/r/20191112110330.179649-5-pihsun@chromium.org Link: https://lore.kernel.org/r/20200909081422.2412795-1-pihsun@chromium.org [mb: squashed both patches] Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 11 ++++++++++ arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 30 ++++++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 12 +++++++++++ 3 files changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index ae405bd8f06b..cba2d8933e79 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -25,6 +25,17 @@ chosen { stdout-path = "serial0:921600n8"; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + scp_mem_reserved: scp_mem_region { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + }; }; &auxadc { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index f0a070535b34..85f7c33ba446 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -90,6 +90,18 @@ regulator-max-microvolt = <3300000>; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem_reserved: scp_mem_region { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + }; + max98357a: codec0 { compatible = "maxim,max98357a"; sdmode-gpios = <&pio 175 0>; @@ -524,6 +536,13 @@ }; }; + scp_pins: scp { + pins_scp_uart { + pinmux = , + ; + }; + }; + spi0_pins: spi0 { pins_spi{ pinmux = , @@ -651,6 +670,17 @@ }; }; +&scp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + + cros_ec { + compatible = "google,cros-ec-rpmsg"; + mtk,rpmsg-name = "cros-ec-rpmsg"; + }; +}; + &soc_data { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 102105871db2..f9b60e3d085c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -339,6 +339,18 @@ clock-names = "spi", "wrap"; }; + scp: scp@10500000 { + compatible = "mediatek,mt8183-scp"; + reg = <0 0x10500000 0 0x80000>, + <0 0x105c0000 0 0x19080>; + reg-names = "sram", "cfg"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_SCPSYS>; + clock-names = "main"; + memory-region = <&scp_mem_reserved>; + status = "disabled"; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8183-timer", "mediatek,mt6765-timer"; -- cgit v1.2.3 From 152a1b4c3e7c16fe8ea9a3171fcb29c5ce030ebb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 4 Sep 2020 12:06:32 +0530 Subject: dt-bindings: arm: qcom: Document SM8250 SoC and boards Document the SM8250 SoC binding and also the boards using it. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200904063637.28632-2-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 6031aee0f5a8..1adc8a33a3e4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -40,6 +40,7 @@ description: | sdm630 sdm660 sdm845 + sm8250 The 'board' element must be one of the following strings: @@ -165,4 +166,10 @@ properties: - qcom,ipq6018-cp01-c1 - const: qcom,ipq6018 + - items: + - enum: + - qcom,qrb5165-rb5 + - qcom,sm8250-mtp + - const: qcom,sm8250 + ... -- cgit v1.2.3 From bb1dfb4da1d031380cd631dd0d6884d4e79a8d51 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 4 Sep 2020 12:06:33 +0530 Subject: arm64: dts: qcom: sm8250: Rename UART2 node to UART12 The UART12 node has been mistakenly mentioned as UART2. Let's fix that for both SM8250 SoC and MTP board and also add pinctrl definition for it. Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file") Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200904063637.28632-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 ++++++++++- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 6894f8490dae..6e2f7ae1d621 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -17,7 +17,7 @@ compatible = "qcom,sm8250-mtp"; aliases { - serial0 = &uart2; + serial0 = &uart12; }; chosen { @@ -371,7 +371,7 @@ gpio-reserved-ranges = <28 4>, <40 4>; }; -&uart2 { +&uart12 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index b82d8f40fa42..c9021685e03d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -936,11 +936,13 @@ status = "disabled"; }; - uart2: serial@a90000 { + uart12: serial@a90000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a90000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart12_default>; interrupts = ; status = "disabled"; }; @@ -1881,6 +1883,13 @@ bias-disable; }; }; + + qup_uart12_default: qup-uart12-default { + mux { + pins = "gpio34", "gpio35"; + function = "qup12"; + }; + }; }; adsp: remoteproc@17300000 { -- cgit v1.2.3 From b1d2674e612119639842c91b70d25cd17480511f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 4 Sep 2020 12:06:34 +0530 Subject: arm64: dts: qcom: Add basic devicetree support for QRB5165 RB5 Add basic devicetree support for Qualcomm Technologies, Inc. Robotics RB5 platform. This board is one of the 96Boards CE platform targeted for Robotics usecases from Qualcomm. This basic devicetree support includes regulators, onboard debug UART, I2C, SPI, and UFS support. Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200904063637.28632-4-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 432 +++++++++++++++++++++++++++++++ 2 files changed, 433 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qrb5165-rb5.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5899101526a7..359811894eac 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts new file mode 100644 index 000000000000..f201e064b3e7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Linaro Ltd. + */ + +/dts-v1/; + +#include +#include +#include "sm8250.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Robotics RB5"; + compatible = "qcom,qrb5165-rb5", "qcom,sm8250"; + + aliases { + serial0 = &uart12; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dc12v: dc12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "DC12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vbat: vbat-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + vin-supply = <&vreg_l11c_3p3>; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + }; + + vbat_som: vbat-som-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT_SOM"; + vin-supply = <&dc12v>; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + }; + + vdc_3v3: vdc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDC_3V3"; + vin-supply = <&dc12v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdc_5v: vdc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDC_5V"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vreg_l11c_3p3>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + vreg_s4a_1p8: vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&apps_rsc { + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_l1f_1p1: ldo1 { + regulator-name = "vreg_l1f_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p2: ldo2 { + regulator-name = "vreg_l2f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l6f_2p8: ldo6 { + regulator-name = "vreg_l6f_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p7: ldo7 { + regulator-name = "vreg_l7a_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_ts_3p0: ldo13 { + regulator-name = "vreg_l13a_ts_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l18a_0p92: ldo18 { + regulator-name = "vreg_l18a_0p92"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_s6a_0p95: smps6 { + regulator-name = "vreg_s6a_0p95"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p2: ldo2 { + regulator-name = "vreg_l2c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p7: ldo4 { + regulator-name = "vreg_l4c_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_cam_vcm0_2p85: ldo7 { + regulator-name = "vreg_l7c_cam_vcm0_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p0: ldo10 { + regulator-name = "vreg_l10c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-name = "vreg_l11c_3p3"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3296000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_s8c_1p3: smps8 { + regulator-name = "vreg_s8c_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + }; +}; + +/* LS-I2C0 */ +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +/* LS-I2C1 */ +&i2c15 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +/* CAN */ +&spi0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <40 4>; +}; + +&uart12 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + vcc-supply = <&vreg_l17a_3p0>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <800000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-max-microamp = <89900>; + vdda-pll-supply = <&vreg_l9a_1p2>; + vdda-pll-max-microamp = <18800>; +}; -- cgit v1.2.3 From b5cbd84e499a714eec05da4722dc2c1aceca4daf Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 4 Sep 2020 12:06:35 +0530 Subject: arm64: dts: qcom: qrb5165-rb5: Add onboard LED support Only User4, WLAN and BT LEDs are added for now. These GPIOs are coming from PM8150. Rest are coming from LPG block which is not supported yet! Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200904063637.28632-5-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index f201e064b3e7..312316e23298 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -32,6 +32,32 @@ regulator-always-on; }; + leds { + compatible = "gpio-leds"; + + user4 { + label = "green:user4"; + gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "panic-indicator"; + default-state = "off"; + }; + + wlan { + label = "yellow:wlan"; + gpios = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt { + label = "blue:bt"; + gpios = <&pm8150_gpios 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + }; + vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; -- cgit v1.2.3 From 6c6a6d81f586e0b953c76e9ebcef5c4d3b33c653 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 4 Sep 2020 12:06:36 +0530 Subject: arm64: dts: qcom: qrb5165-rb5: Add gpio-line-names for TLMM block Add gpio-line-names property for QRB5165 RB5 board for naming all GPIOs exposed by TLMM block. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200904063637.28632-6-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 181 +++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 312316e23298..cf6dc0ec1640 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -431,6 +431,187 @@ &tlmm { gpio-reserved-ranges = <40 4>; + gpio-line-names = + "GPIO-MM", + "GPIO-NN", + "GPIO-OO", + "GPIO-PP", + "GPIO-A", + "GPIO-C", + "GPIO-E", + "GPIO-D", + "I2C0-SDA", + "I2C0-SCL", + "GPIO-TT", /* GPIO_10 */ + "NC", + "GPIO_12_I2C_SDA", + "GPIO_13_I2C_SCL", + "GPIO-X", + "GPIO_15_RGMII_INT", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", + "HST_BT_UART_RX", + "HST_WLAN_EN", /* GPIO_20 */ + "HST_BT_EN", + "GPIO-AAA", + "GPIO-BBB", + "GPIO-CCC", + "GPIO-Z", + "GPIO-DDD", + "GPIO-BB", + "GPIO_28_CAN_SPI_MISO", + "GPIO_29_CAN_SPI_MOSI", + "GPIO_30_CAN_SPI_CLK", /* GPIO_30 */ + "GPIO_31_CAN_SPI_CS", + "GPIO-UU", + "NC", + "UART1_TXD_SOM", + "UART1_RXD_SOM", + "UART0_CTS", + "UART0_RTS", + "UART0_TXD", + "UART0_RXD", + "SPI1_MISO", /* GPIO_40 */ + "SPI1_MOSI", + "SPI1_CLK", + "SPI1_CS", + "I2C1_SDA", + "I2C1_SCL", + "GPIO-F", + "GPIO-JJ", + "Board_ID1", + "Board_ID2", + "NC", /* GPIO_50 */ + "NC", + "SPI0_MISO", + "SPI0_MOSI", + "SPI0_SCLK", + "SPI0_CS", + "GPIO-QQ", + "GPIO-RR", + "USB2LAN_RESET", + "USB2LAN_EXTWAKE", + "NC", /* GPIO_60 */ + "NC", + "NC", + "LT9611_INT", + "GPIO-AA", + "USB_CC_DIR", + "GPIO-G", + "GPIO-LL", + "USB_DP_HPD_1P8", + "NC", + "NC", /* GPIO_70 */ + "SD_CMD", + "SD_DAT3", + "SD_SCLK", + "SD_DAT2", + "SD_DAT1", + "SD_DAT0", /* BOOT_CFG3 */ + "SD_UFS_CARD_DET_N", + "GPIO-II", + "PCIE0_RST_N", + "PCIE0_CLK_REQ_N", /* GPIO_80 */ + "PCIE0_WAKE_N", + "GPIO-CC", + "GPIO-DD", + "GPIO-EE", + "GPIO-FF", + "GPIO-GG", + "GPIO-HH", + "GPIO-VV", + "GPIO-WW", + "NC", /* GPIO_90 */ + "NC", + "GPIO-K", + "GPIO-I", + "CSI0_MCLK", + "CSI1_MCLK", + "CSI2_MCLK", + "CSI3_MCLK", + "GPIO-AA", /* CSI4_MCLK */ + "GPIO-BB", /* CSI5_MCLK */ + "GPIO-KK", /* GPIO_100 */ + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CCI_I2C_SDA3", + "CCI_I2C_SCL3", + "GPIO-L", + "NC", /* GPIO_110 */ + "NC", + "ACCEL_INT", + "GYRO_INT", + "GPIO-J", + "GPIO-YY", + "GPIO-H", + "GPIO-ZZ", + "NC", + "NC", + "NC", /* GPIO_120 */ + "NC", + "MAG_INT", + "MAG_DRDY_INT", + "HST_SW_CTRL", + "GPIO-M", + "GPIO-N", + "GPIO-O", + "GPIO-P", + "PS_INT", + "WSA1_EN", /* GPIO_130 */ + "USB_HUB_RESET", + "SDM_FORCE_USB_BOOT", + "I2S1_CLK_HDMI", + "I2S1_DATA0_HDMI", + "I2S1_WS_HDMI", + "GPIO-B", + "GPIO_137", /* To LT9611_I2S_MCLK_3V3 */ + "PCM_CLK", + "PCM_DI", + "PCM_DO", /* GPIO_140 */ + "PCM_FS", + "HST_SLIM_CLK", + "HST_SLIM_DATA", + "GPIO-U", + "GPIO-Y", + "GPIO-R", + "GPIO-Q", + "GPIO-S", + "GPIO-T", + "GPIO-V", /* GPIO_150 */ + "GPIO-W", + "DMIC_CLK1", + "DMIC_DATA1", + "DMIC_CLK2", + "DMIC_DATA2", + "WSA_SWR_CLK", + "WSA_SWR_DATA", + "DMIC_CLK3", + "DMIC_DATA3", + "I2C4_SDA", /* GPIO_160 */ + "I2C4_SCL", + "SPI3_CS1", + "SPI3_CS2", + "SPI2_MISO_LS3", + "SPI2_MOSI_LS3", + "SPI2_CLK_LS3", + "SPI2_ACCEL_CS_LS3", + "SPI2_CS1", + "NC", + "GPIO-SS", /* GPIO_170 */ + "GPIO-XX", + "SPI3_MISO", + "SPI3_MOSI", + "SPI3_CLK", + "SPI3_CS", + "HST_BLE_SNS_UART_TX", + "HST_BLE_SNS_UART_RX", + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; }; &uart12 { -- cgit v1.2.3 From 70ff10d5e38fc1a3e57332ebe055a53425245482 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 4 Sep 2020 12:06:37 +0530 Subject: arm64: dts: qcom: qrb5165-rb5: Add gpio-line-names for PM8150(B&L) Add gpio-line-names for the GPIO pins exposed by PM8150, PM8150B and PM8150L PMIC nodes. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200904063637.28632-7-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 47 ++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index cf6dc0ec1640..1528a865f1f8 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -412,6 +412,53 @@ status = "okay"; }; +&pm8150_gpios { + gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; + gpio-line-names = + "NC", + "OPTION2", + "PM_GPIO-F", + "PM_SLP_CLK_IN", + "OPTION1", + "VOL_UP_N", + "PM8250_GPIO7", /* Blue LED */ + "SP_ARI_PWR_ALARM", + "GPIO_9_P", /* Yellow LED */ + "GPIO_10_P"; /* Green LED */ +}; + +&pm8150b_gpios { + gpio-line-names = + "NC", + "NC", + "NC", + "NC", + "HAP_BOOST_EN", /* SOM */ + "SMB_STAT", /* SOM */ + "NC", + "NC", + "SDM_FORCE_USB_BOOT", + "NC", + "NC", + "NC"; +}; + +&pm8150l_gpios { + gpio-line-names = + "NC", + "PM3003A_EN", + "NC", + "NC", + "PM_GPIO5", /* HDMI RST_N */ + "PM_GPIO-A", /* PWM */ + "PM_GPIO7", + "NC", + "NC", + "PM_GPIO-B", + "NC", + "PM3003A_MODE"; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit v1.2.3 From 3cc006b395e267b03d42758d6c7c1d03ed7c78d0 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 7 Sep 2020 18:19:37 +0900 Subject: dt-bindings: arm: renesas: Document R-Car V3U SoC DT bindings Add device tree bindings documentation for Renesas R-Car V3U (r8a779a0). Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1599470390-29719-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 0d4dabb4a164..9f8c33537fc5 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -281,6 +281,10 @@ properties: - renesas,draak # Draak (RTP0RC77995SEB0010S) - const: renesas,r8a77995 + - description: R-Car V3U (R8A779A0) + items: + - const: renesas,r8a779a0 + - description: RZ/N1D (R9A06G032) items: - enum: -- cgit v1.2.3 From 2e95492de6d9a289a7c246d8c2f66fc2b53b2b00 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 7 Sep 2020 18:19:39 +0900 Subject: dt-bindings: power: renesas,rcar-sysc: Document r8a779a0 SYSC bindings Document bindings for the R-Car V3U (aka R8A779A0) SYSC block. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1599470390-29719-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index ec2aaeee78dc..99e8042ac111 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -40,6 +40,7 @@ properties: - renesas,r8a77980-sysc # R-Car V3H - renesas,r8a77990-sysc # R-Car E3 - renesas,r8a77995-sysc # R-Car D3 + - renesas,r8a779a0-sysc # R-Car V3U reg: maxItems: 1 -- cgit v1.2.3 From 461cb5952e35255265df64020344ceaf3d888263 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 7 Sep 2020 18:19:41 +0900 Subject: dt-bindings: reset: renesas,rst: Document r8a779a0 reset module Document bindings for the R-Car V3U (R8A779A0) reset module. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1599470390-29719-6-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml index 2849ce45703c..620cd0538bbe 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -47,6 +47,7 @@ properties: - renesas,r8a77980-rst # R-Car V3H - renesas,r8a77990-rst # R-Car E3 - renesas,r8a77995-rst # R-Car D3 + - renesas,r8a779a0-rst # R-Car V3U reg: maxItems: 1 -- cgit v1.2.3 From b08892556b3f19d95d356b33692247de8303fe05 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 10 Sep 2020 21:02:49 +0900 Subject: dt-bindings: arm: renesas: Document Renesas Falcon boards Add device tree bindings documentation for Renesas R-Car V3U Falcon CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1599739372-30669-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 9f8c33537fc5..01a6d0c571ad 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -283,6 +283,14 @@ properties: - description: R-Car V3U (R8A779A0) items: + - enum: + - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S) + - const: renesas,r8a779a0 + + - items: + - enum: + - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S) + - const: renesas,falcon-cpu - const: renesas,r8a779a0 - description: RZ/N1D (R9A06G032) -- cgit v1.2.3 From f05f2c21187a58753e3754c27cf48f72610b37db Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 1 Aug 2020 23:43:35 +0530 Subject: arm64: dts: qcom: sc7180: Add LPASS clock controller nodes Update the clock controller nodes for Low power audio subsystem functionality. Reviewed-by: Douglas Anderson Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/1596305615-5894-2-git-send-email-tdas@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d3e6008cf3fb..41b20b1cd8a3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -3325,6 +3326,29 @@ qcom,msa-fixed-perm; status = "disabled"; }; + + lpasscc: clock-controller@62d00000 { + compatible = "qcom,sc7180-lpasscorecc"; + reg = <0 0x62d00000 0 0x50000>, + <0 0x62780000 0 0x30000>; + reg-names = "lpass_core_cc", "lpass_audio_cc"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpass_hm: clock-controller@63000000 { + compatible = "qcom,sc7180-lpasshm"; + reg = <0 0x63000000 0 0x28>; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; }; thermal-zones { -- cgit v1.2.3 From 7345e5c1853d7173bf06923c29f93c0308ac89e5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Sep 2020 08:32:14 +0100 Subject: arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata Enable sata interface on HiHope RZ/G2H board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20200907073214.13929-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts index 265355e0de5f..812995939841 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts @@ -13,3 +13,8 @@ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h", "renesas,r8a774e1"; }; + +/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ +&sata { + status = "okay"; +}; -- cgit v1.2.3 From 4c32a2b34e62d1ab3325902f2a3b065f266cc4f3 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Sep 2020 15:45:09 +0100 Subject: ARM: dts: r8a7742: Add VIN DT nodes Add VIN[0123] instances found in the r8a7742 SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20200907144509.8861-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index c62e26876f95..24647cf13c2b 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -1103,6 +1103,50 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 808>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required -- cgit v1.2.3 From 8368ca1540f0ff5bf4cfe92b1ea7fc8045f61d50 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Sep 2020 16:55:39 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support Add support for the SPI NOR device which is connected to MSIOF0 interface on the iWave RainboW-G21d-q7 board. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200907155541.2011-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index df85e516a3c0..a88858e1afbb 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -141,6 +141,32 @@ status = "okay"; }; +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + flash1: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "user"; + reg = <0x00000000 0x00200000>; + }; + }; + }; +}; + &pci0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; @@ -182,6 +208,11 @@ function = "i2c2"; }; + msiof0_pins: msiof0 { + groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx"; + function = "msiof0"; + }; + scifa2_pins: scifa2 { groups = "scifa2_data_c"; function = "scifa2"; -- cgit v1.2.3 From 68ee7720a01cf20e1de20a2e770b6568db18c253 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Sep 2020 16:55:40 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7: Add can1 support to carrier board This patch enables CAN1 interface exposed through connector J20 on the carrier board. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200907155541.2011-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index a88858e1afbb..7291c9799c5b 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -131,10 +131,26 @@ }; }; +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &cmt0 { status = "okay"; }; +&gpio1 { + can-trx-en-gpio{ + gpio-hog; + gpios = <28 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "can-trx-en-gpio"; + }; +}; + &hsusb { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; @@ -203,6 +219,11 @@ function = "avb"; }; + can1_pins: can1 { + groups = "can1_data_b"; + function = "can1"; + }; + i2c2_pins: i2c2 { groups = "i2c2_b"; function = "i2c2"; -- cgit v1.2.3 From 8feb348406115e2cc5508efd6f94173a112b8c7c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Sep 2020 16:55:41 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication Add support for LED trigger on SD2 interface. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200907155541.2011-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index 7291c9799c5b..c2c05c9685d1 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -52,6 +52,16 @@ clock-frequency = <26000000>; }; + leds { + compatible = "gpio-leds"; + + sdhi2_led { + label = "sdio-led"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + }; + reg_1p5v: 1p5v { compatible = "regulator-fixed"; regulator-name = "1P5V"; -- cgit v1.2.3 From 834c310f541839b6f4e0d9ca527a64f71b0d141b Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 10 Sep 2020 21:02:51 +0900 Subject: arm64: dts: renesas: Add Renesas R8A779A0 SoC support Add initial support for the Renesas R8A77990 (R-Car V3U) support. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1599739372-30669-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 133 ++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779a0.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi new file mode 100644 index 000000000000..6cf77ce9aa93 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car V3U (R8A779A0) SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a779a0"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76_0>; + }; + + L3_CA76_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779A0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779a0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779a0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779a0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = ; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- cgit v1.2.3 From 63070d7c2270e8de8abef8f6f20e192bcc1d50de Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 10 Sep 2020 21:02:52 +0900 Subject: arm64: dts: renesas: Add Renesas Falcon boards support Initial support for the Renesas Falcon CPU and BreakOut boards support. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1599739372-30669-5-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 46 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 22 +++++++++++ 3 files changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 46445474cf3e..dffefe030a76 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -54,3 +54,5 @@ dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb + +dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi new file mode 100644 index 000000000000..4ba269a4cec8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Falcon CPU board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a779a0.dtsi" + +/ { + model = "Renesas Falcon CPU board"; + compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; + + memory@700000000 { + device_type = "memory"; + reg = <0x7 0x00000000 0x0 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts new file mode 100644 index 000000000000..8eda70e5a82b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Falcon CPU and BreakOut boards + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779a0-falcon-cpu.dtsi" + +/ { + model = "Renesas Falcon CPU and Breakout boards based on r8a779a0"; + compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"; + + aliases { + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; -- cgit v1.2.3 From ec88a9c344d9fd8c3b11bff1f99a0b6248ae256d Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Sat, 22 Aug 2020 18:19:23 +0200 Subject: ARM: BCM5301X: Add DT for Meraki MR32 add support for the Cisco Meraki MR32. This is a dual-band enterprise class 802.11ac access point. The unit was donated by Chris Blake. Thank you! SoC: Broadcom BCM53016A1 (1 GHz, 2 cores) RAM: 128 MiB NAND: 128 MiB Spansion S34ML01G2 (~114 MiB useable) ETH: 1GBit Ethernet Port - PoE WIFI1: Broadcom BCM43520 an+ac (2x2:2 - id: 0x4352) WIFI2: Broadcom BCM43520 bgn (2x2:2 - id: 0x4352) WIFI3: Broadcom BCM43428 abgn (1x1:1 - id: 43428) BLE: Broadcom BCM20732 (ttyS1) LEDS: 1 x Programmable RGB Status LED (driven by a PWM) 1 x White LED (GPIO) 1 x Orange LED Fault Indicator (GPIO) 2 x LAN Activity / Speed LEDs (On the RJ45 Port) BUTTON: one Reset button MISC: AT24C64 8KiB EEPROM (i2c - stores Ethernet MAC) ina219 hardware monitor (i2c) Kensington Lock SERIAL: WARNING: The serial port needs a TTL/RS-232 3V3 level converter! The Serial setting is 115200-8-N-1. The board has a populated right angle 1x4 0.1" pinheader. The pinout is: VCC, RX, TX, GND. Odd stuff: - uart0 clock frequency is 62.5 MHz. - The LEDs are labeled as SYS-LED1 through SYS-LED3 because of the silkscreen on the PCB. - the original u-boot has been compiled with most functions and commands disabled. The u-boot env isn't setup properly either and as a result, the bcm47xxpart probing is not working. Hence, the nand partitions are specified through a "fixed-partition" binding. - The "WICED SMART(TM)" Bluetooth LE 4.0 BCM20732 chip is connected to uart2 of the SoC. The BCM20732 does not provide a HCI. So the linux' bluetooth stack is useless. The mock-up node with the compatible binding and enable-gpios property is provided solely as documentation. Signed-off-by: Christian Lamparter Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 197 +++++++++++++++++++++++++++++ 2 files changed, 198 insertions(+) create mode 100644 arch/arm/boot/dts/bcm53016-meraki-mr32.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..d254ca2a942d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -127,6 +127,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-luxul-xwr-3150-v1.dtb \ bcm47094-netgear-r8500.dtb \ bcm47094-phicomm-k3.dtb \ + bcm53016-meraki-mr32.dtb \ bcm94708.dtb \ bcm94709.dtb \ bcm953012er.dtb \ diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts new file mode 100644 index 000000000000..3b978dc8997a --- /dev/null +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Meraki MR32 / Codename: Espresso + * + * Copyright (C) 2018-2020 Christian Lamparter + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include + +/ { + compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708"; + model = "Meraki MR32"; + + chosen { + bootargs = " console=ttyS0,115200n8 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + device_type = "memory"; + }; + + aliases { + serial1 = &uart2; + }; + + leds { + compatible = "gpio-leds"; + + sysled3 { + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + sysled2 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + red { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_INDICATOR; + color = ; + pwms = <&pwm 0 50000 0>; + max-brightness = <255>; + }; + + green { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_POWER; + color = ; + pwms = <&pwm 1 50000 0>; + max-brightness = <255>; + }; + + blue { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_INDICATOR; + color = ; + pwms = <&pwm 2 50000 0>; + max-brightness = <255>; + }; + }; + + i2c { + /* + * The platform provided I2C does not budge. + * This is a replacement until I can figure + * out what are the missing bits... + */ + + compatible = "i2c-gpio"; + sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <10>; /* close to 100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + current_sense: ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + }; + }; +}; + +&uart0 { + clock-frequency = <62500000>; + /delete-property/ clocks; +}; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + status = "okay"; + /* + * bluetooth-le { + * compatible = "brcm,bcm20732"; + * enable-gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + *}; + */ +}; + +&gmac1 { + status = "disabled"; +}; +&gmac2 { + status = "disabled"; +}; +&gmac3 { + status = "disabled"; +}; + +&pwm { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_pwm>; +}; + +&nandcs { + nand-ecc-algo = "hw"; + + partitions { + /* + * The partition autodetection does not work for this device. + * It will only detect the "nvram" partition with an incorrect size. + * [ 1.721667] 1 bcm47xxpart partitions found on MTD device brcmnand.0 + * [ 1.727962] Creating 1 MTD partitions on "brcmnand.0": + * [ 1.733117] 0x000000400000-0x000008000000 : "nvram" + */ + + compatible = "fixed-partitions"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + partition0@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition1@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + read-only; + }; + + partition2@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + read-only; + }; + + partition3@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + read-only; + }; + + partition4@800000 { + label = "ubi"; + reg = <0x800000 0x7780000>; + }; + }; +}; -- cgit v1.2.3 From 5d00306e3aae170658e27413b6d7bf211547ea0f Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 21:54:41 +0200 Subject: ARM: dts: NSP: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958525xmc.dts | 2 +- arch/arm/boot/dts/bcm958625k.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index 716da62f5788..21f922dc6019 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -196,7 +196,7 @@ }; &sdio { - status = "ok"; + status = "okay"; }; &uart0 { diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 7b84b54436ed..7782b61c51a1 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -208,7 +208,7 @@ &sdio { bus-width = <4>; no-1-8-v; - status = "ok"; + status = "okay"; }; &srab { -- cgit v1.2.3 From 9d6693369fc782b33168255fe3cd760796dba59c Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 28 Aug 2020 14:06:00 +0100 Subject: ARM: dts: Cygnus: Fix SP805 clocks The SP805 DT binding requires two clocks to be specified, but the Broadcom Cygnus DT currently only specifies one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara Reviewed-by: Ray Jui Acked-by: Florian Fainelli Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 35bdd0969f0a..dacaef2c14ca 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -234,8 +234,8 @@ compatible = "arm,sp805" , "arm,primecell"; reg = <0x18009000 0x1000>; interrupts = ; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "wdog_clk", "apb_pclk"; }; gpio_ccm: gpio@1800a000 { -- cgit v1.2.3 From f5146e5da4333cc1c8660877001e88b1a05a1dd5 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 28 Aug 2020 14:06:01 +0100 Subject: ARM: dts: NSP: Fix SP805 clock-names The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for the Broadcom NSP platform to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Signed-off-by: Andre Przywara Reviewed-by: Ray Jui Acked-by: Florian Fainelli Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 0346ea621f0f..371b4fda6390 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -438,7 +438,7 @@ reg = <0x39000 0x1000>; interrupts = ; clocks = <&iprocslow>, <&iprocslow>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; lcpll0: lcpll0@3f100 { -- cgit v1.2.3 From be7e6bd01cdacbf0fcaa281756963f77b619d8d2 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 26 Aug 2020 19:38:01 +0100 Subject: ARM: dts: broadcom: Fix SP804 node The DT binding for SP804 requires to have an "arm,primecell" compatible string. Add this string so that the Linux primecell bus driver picks the device up and activates the clock. Signed-off-by: Andre Przywara Tested-by: Florian Fainelli [florian: added compatible to ccbtimer1] Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 371b4fda6390..8ba5097157e1 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -368,7 +368,7 @@ }; ccbtimer0: timer@34000 { - compatible = "arm,sp804"; + compatible = "arm,sp804", "arm,primecell"; reg = <0x34000 0x1000>; interrupts = , ; @@ -377,7 +377,7 @@ }; ccbtimer1: timer@35000 { - compatible = "arm,sp804"; + compatible = "arm,sp804", "arm,primecell"; reg = <0x35000 0x1000>; interrupts = , ; -- cgit v1.2.3 From 81921a37145e0c6581ab913129c3c2a604704eee Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 16 Jul 2020 17:05:32 +0530 Subject: arm64: dts: qcom: sc7180: add interconnect bindings for display This change adds the interconnect bindings to the MDSS node. This will establish Display to DDR path for bus bandwidth voting. Reviewed-by: Rob Clark Signed-off-by: Krishna Manikandan Link: https://lore.kernel.org/r/1594899334-19772-1-git-send-email-kalyan_t@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 41b20b1cd8a3..90debb4e4c11 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2766,6 +2766,9 @@ interrupt-controller; #interrupt-cells = <1>; + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnect-names = "mdp0-mem"; + iommus = <&apps_smmu 0x800 0x2>; #address-cells = <2>; -- cgit v1.2.3 From 137154871cf469af0e8def123511c37096583919 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 1 Sep 2020 19:50:25 +0530 Subject: arm64: dts: qcom: sdm845: Add OPP tables and power-domains for venus Add the OPP tables in order to be able to vote on the performance state of a power-domain. Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/1598970026-7199-5-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 40 ++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2884577dcb77..86457d9bc229 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3639,8 +3639,10 @@ interrupts = ; power-domains = <&videocc VENUS_GDSC>, <&videocc VCODEC0_GDSC>, - <&videocc VCODEC1_GDSC>; - power-domain-names = "venus", "vcodec0", "vcodec1"; + <&videocc VCODEC1_GDSC>, + <&rpmhpd SDM845_CX>; + power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; + operating-points-v2 = <&venus_opp_table>; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, @@ -3662,6 +3664,40 @@ video-core1 { compatible = "venus-encoder"; }; + + venus_opp_table: venus-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-533000097 { + opp-hz = /bits/ 64 <533000097>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; }; videocc: clock-controller@ab00000 { -- cgit v1.2.3 From ef8e58f837e6f5659ca8dc2c49dfe3eaf17a02e1 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 1 Sep 2020 19:50:26 +0530 Subject: arm64: dts: qcom: sc7180: Add OPP tables and power-domains for venus Add the OPP tables in order to be able to vote on the performance state of a power-domain Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/1598970026-7199-6-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 90debb4e4c11..0a80a5ccbe50 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2705,8 +2705,10 @@ reg = <0 0x0aa00000 0 0xff000>; interrupts = ; power-domains = <&videocc VENUS_GDSC>, - <&videocc VCODEC0_GDSC>; - power-domain-names = "venus", "vcodec0"; + <&videocc VCODEC0_GDSC>, + <&rpmhpd SC7180_CX>; + power-domain-names = "venus", "vcodec0", "cx"; + operating-points-v2 = <&venus_opp_table>; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, @@ -2727,6 +2729,35 @@ video-encoder { compatible = "venus-encoder"; }; + + venus_opp_table: venus-opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-340000000 { + opp-hz = /bits/ 64 <340000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-434000000 { + opp-hz = /bits/ 64 <434000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-500000097 { + opp-hz = /bits/ 64 <500000097>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; }; videocc: clock-controller@ab00000 { -- cgit v1.2.3 From 5a4d9f3e18f5e2281f50e7f644e1f9a1589d900b Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Thu, 13 Aug 2020 11:30:33 -0700 Subject: arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zones The 'sustainable_power' attribute provides an estimate of the sustained power that can be dissipated at the desired control temperature. One could argue that this value is not necessarily the same for all devices with the same SoC, which may have different form factors or thermal designs. However there are reasons to specify a (default) value at SoC level for SC7180: most importantly, if no value is specified at all the power_allocator thermal governor (aka 'IPA') estimates a value, using the minimum power of all cooling devices of the zone, which can result in overly aggressive thermal throttling. For most devices an approximate conservative value should be more useful than the minimum guesstimate of power_allocator. Devices that need a different value can overwrite it in their .dts. Also the thermal zones for SC7180 have a high level of granularity (essentially one for each function block), which makes it more likely that the default value just works for many devices. The values correspond to 1901 MHz for the big cores, and 1804 MHz for the small cores. The values were determined by limiting the CPU frequencies to different max values and launching a bunch of processes that cause high CPU load ('while true; do true; done &' is simple and does a good job). A frequency is deemed sustainable if the CPU temperatures don't rise (consistently) above the second trip point ('control temperature', 95 degC in this case). Once the highest sustainable frequency is found, the sustainable power can be calculated by multiplying the energy consumption per core at this frequency (which can be found in /sys/kernel/debug/energy_model/) with the number of cores that are specified as cooling devices. The sustainable frequencies were determined at room temperature on a device without heat sink or other passive cooling elements. Reviewed-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20200813113030.1.I89c33c4119eaffb986b1e8c1bc6f0e30267089cd@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 0a80a5ccbe50..a43f8fe9b472 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3391,6 +3391,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 1>; + sustainable-power = <768>; trips { cpu0_alert0: trip-point0 { @@ -3439,6 +3440,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 2>; + sustainable-power = <768>; trips { cpu1_alert0: trip-point0 { @@ -3487,6 +3489,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 3>; + sustainable-power = <768>; trips { cpu2_alert0: trip-point0 { @@ -3535,6 +3538,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 4>; + sustainable-power = <768>; trips { cpu3_alert0: trip-point0 { @@ -3583,6 +3587,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 5>; + sustainable-power = <768>; trips { cpu4_alert0: trip-point0 { @@ -3631,6 +3636,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 6>; + sustainable-power = <768>; trips { cpu5_alert0: trip-point0 { @@ -3679,6 +3685,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 9>; + sustainable-power = <1202>; trips { cpu6_alert0: trip-point0 { @@ -3719,6 +3726,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 10>; + sustainable-power = <1202>; trips { cpu7_alert0: trip-point0 { @@ -3759,6 +3767,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 11>; + sustainable-power = <1202>; trips { cpu8_alert0: trip-point0 { @@ -3799,6 +3808,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 12>; + sustainable-power = <1202>; trips { cpu9_alert0: trip-point0 { -- cgit v1.2.3 From fa8da06628626531cda3a008223d99109cbd1f02 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Mon, 17 Aug 2020 12:11:04 +0530 Subject: arm64: dts: qcom: sc7180: Add bandwidth votes for eMMC and SDcard Add the bandwidth domain supporting performance state and the corresponding OPP tables for the sdhc device on sc7180. Signed-off-by: Pradeep P V K Signed-off-by: Shaik Sajida Bhanu Link: https://lore.kernel.org/r/1597646464-1863-1-git-send-email-sbhanu@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a43f8fe9b472..e7c4762449df 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -691,6 +691,9 @@ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; + interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&sdhc1_opp_table>; @@ -711,11 +714,15 @@ opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <100000 100000>; + opp-avg-kBps = <100000 50000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <600000 900000>; + opp-avg-kBps = <261438 300000>; }; }; }; @@ -2516,6 +2523,10 @@ clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; clock-names = "core", "iface"; + + interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&sdhc2_opp_table>; @@ -2529,11 +2540,15 @@ opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <80000 50000>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <100000 60000>; }; }; }; -- cgit v1.2.3 From 0a4fd091cf11203c3f0415be85c70daf8db0bd4f Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 16 Jul 2020 17:05:33 +0530 Subject: arm64: dts: sc7180: add bus clock to mdp node for sc7180 target Move the bus clock to mdp device node,in order to facilitate bus band width scaling on sc7180 target. The parent device MDSS will not vote for bus bw, instead the vote will be triggered by mdp device node. Since a minimum vote is required to turn on bus clock, move the clock node to mdp device from where the votes are requested. This patch has dependency on the below series https://patchwork.kernel.org/patch/11468783/ Reviewed-by: Rob Clark Signed-off-by: Krishna Manikandan Link: https://lore.kernel.org/r/1594899334-19772-2-git-send-email-kalyan_t@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e7c4762449df..12fede0532a3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2800,10 +2800,9 @@ power-domains = <&dispcc MDSS_GDSC>; clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "ahb", "core"; + clock-names = "iface", "ahb", "core"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; assigned-clock-rates = <300000000>; @@ -2829,12 +2828,13 @@ <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "rot", "lut", "core", + clock-names = "bus", "iface", "rot", "lut", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, -- cgit v1.2.3 From e89570584d2bcf188af4baaebacfb6998e6326dc Mon Sep 17 00:00:00 2001 From: Ben Pai Date: Wed, 9 Sep 2020 17:08:18 +0800 Subject: ARM: dts: aspeed: Add Mowgli BMC platform The Mowgli BMC is an ASPEED ast2500 based BMC that is part of an OpenPower Power9 server. Signed-off-by: Ben Pai Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200909090818.24021-1-ben_pai@wistron.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts | 662 ++++++++++++++++++++++++++++ 2 files changed, 663 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e252cfff1830..f0062f991744 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1382,6 +1382,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mihawk.dtb \ + aspeed-bmc-opp-mowgli.dtb \ aspeed-bmc-opp-nicole.dtb \ aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts new file mode 100644 index 000000000000..b648e468e9db --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts @@ -0,0 +1,662 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Mowgli BMC"; + compatible = "ibm,mowgli-bmc", "aspeed,ast2500"; + + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + air-water { + label = "air-water"; + gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + id-button { + label = "id-button"; + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + fan4-presence { + label = "fan4-presence"; + gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + }; + + leds { + compatible = "gpio-leds"; + + front-fault { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; + }; + + power-button { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; + }; + + front-id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; + }; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; + }; + + fan4 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon-12v { + compatible = "iio-hwmon"; + io-channels = <&adc 0>; + }; + + iio-hwmon-5v { + compatible = "iio-hwmon"; + io-channels = <&adc 1>; + }; + + iio-hwmon-3v { + compatible = "iio-hwmon"; + io-channels = <&adc 2>; + }; + + iio-hwmon-vdd { + compatible = "iio-hwmon"; + io-channels = <&adc 3>; + }; + + iio-hwmon-vcs { + compatible = "iio-hwmon"; + io-channels = <&adc 5>; + }; + + iio-hwmon-vdn { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; + + iio-hwmon-vio { + compatible = "iio-hwmon"; + io-channels = <&adc 9>; + }; + + iio-hwmon-vddra { + compatible = "iio-hwmon"; + io-channels = <&adc 11>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + + iio-hwmon-vddrb { + compatible = "iio-hwmon"; + io-channels = <&adc 13>; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "obmc-ubi"; + }; + }; + }; + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "alt-u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "alt-u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "alt-obmc-ubi"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* APSS */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + /* CPU MFG CONN */ + +}; + +&i2c3 { + status = "okay"; + + /* APSS */ + /* CPLD */ + + /* PCA9516 (repeater) -> + * CLK Buffer 9FGS9092 + * Power Supply 0 + * Power Supply 1 + * PCA 9552 LED + */ + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + gpio@1 { + reg = <1>; + type = ; + }; + gpio@2 { + reg = <2>; + type = ; + }; + gpio@3 { + reg = <3>; + type = ; + }; + gpio@4 { + reg = <4>; + type = ; + }; + gpio@5 { + reg = <5>; + type = ; + }; + gpio@6 { + reg = <6>; + type = ; + }; + gpio@7 { + reg = <7>; + type = ; + }; + gpio@8 { + reg = <8>; + type = ; + }; + gpio@9 { + reg = <9>; + type = ; + }; + gpio@10 { + reg = <10>; + type = ; + }; + gpio@11 { + reg = <11>; + type = ; + }; + gpio@12 { + reg = <12>; + type = ; + }; + gpio@13 { + reg = <13>; + type = ; + }; + gpio@14 { + reg = <14>; + type = ; + }; + gpio@15 { + reg = <15>; + type = ; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + /* CP0 VDD & VCS : IR35221 */ + /* CP0 VDN & VIO : IR35221 */ + /* CP0 VDDR : IR35221 */ + + ir35221@28 { + compatible = "infineon,ir35221"; + reg = <0x28>; + }; + + ir35221@29 { + compatible = "infineon,ir35221"; + reg = <0x29>; + }; + + ir35221@2d { + compatible = "infineon,ir35221"; + reg = <0x2d>; + }; + +}; + +&i2c5 { + status = "disabled"; +}; + +&i2c6 { + status = "disabled"; +}; + +&i2c7 { + status = "disabled"; +}; + +&i2c8 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c9 { + status = "okay"; + + /* PCIe G3 x16 slot */ +}; + +&i2c10 { + status = "disabled"; +}; + +&i2c11 { + status = "okay"; + + /* CPLD */ + /* TPM */ + /* RTC RX8900CE */ + /* TMP275A */ + /* TMP275A */ + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + +}; + +&i2c12 { + status = "disabled"; +}; + +&i2c13 { + status = "disabled"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + aspeed,alt-boot; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" -- cgit v1.2.3 From d9fd7ff595a89f7c975c96f78a0cedfe6d0828fb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:23:51 +0200 Subject: ARM: dts: renesas: Fix pin controller node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20200821112351.5518-1-geert+renesas@glider.be --- arch/arm/boot/dts/emev2.dtsi | 2 +- arch/arm/boot/dts/r7s72100.dtsi | 2 +- arch/arm/boot/dts/r7s9210.dtsi | 2 +- arch/arm/boot/dts/r8a73a4.dtsi | 2 +- arch/arm/boot/dts/r8a7740.dtsi | 2 +- arch/arm/boot/dts/r8a7742.dtsi | 2 +- arch/arm/boot/dts/r8a7743.dtsi | 2 +- arch/arm/boot/dts/r8a7744.dtsi | 2 +- arch/arm/boot/dts/r8a7745.dtsi | 2 +- arch/arm/boot/dts/r8a77470.dtsi | 2 +- arch/arm/boot/dts/r8a7778.dtsi | 2 +- arch/arm/boot/dts/r8a7779.dtsi | 2 +- arch/arm/boot/dts/r8a7790.dtsi | 2 +- arch/arm/boot/dts/r8a7791.dtsi | 2 +- arch/arm/boot/dts/r8a7792.dtsi | 2 +- arch/arm/boot/dts/r8a7793.dtsi | 2 +- arch/arm/boot/dts/r8a7794.dtsi | 2 +- arch/arm/boot/dts/r9a06g032.dtsi | 2 +- arch/arm/boot/dts/sh73a0.dtsi | 2 +- 19 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 96678ddbb4e6..ecfaa0b7523e 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -195,7 +195,7 @@ clock-names = "sclk"; }; - pfc: pin-controller@e0140200 { + pfc: pinctrl@e0140200 { compatible = "renesas,pfc-emev2"; reg = <0xe0140200 0x100>; }; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index b9b138888048..45cf75b5824c 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -499,7 +499,7 @@ clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; }; - pinctrl: pin-controller@fcfe3000 { + pinctrl: pinctrl@fcfe3000 { compatible = "renesas,r7s72100-ports"; reg = <0xfcfe3000 0x4230>; diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index 838920aef992..85c0399b1339 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -489,7 +489,7 @@ interrupt-map-mask = <7 0>; }; - pinctrl: pin-controller@fcffe000 { + pinctrl: pinctrl@fcffe000 { compatible = "renesas,r7s9210-pinctrl"; reg = <0xfcffe000 0x1000>; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index b92e72579836..e5fb1ce261f7 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -221,7 +221,7 @@ power-domains = <&pd_c4>; }; - pfc: pin-controller@e6050000 { + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a73a4"; reg = <0 0xe6050000 0 0x9000>; gpio-controller; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 8048303037ee..1b2cf5fa322b 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -311,7 +311,7 @@ status = "disabled"; }; - pfc: pin-controller@e6050000 { + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a7740"; reg = <0xe6050000 0x8000>, <0xe605800c 0x20>; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 24647cf13c2b..170f159d6613 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -338,7 +338,7 @@ resets = <&cpg 907>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7742"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 896916a00b84..f444e418f408 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -265,7 +265,7 @@ resets = <&cpg 904>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7743"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 6b56aa286337..0442aad4f9db 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -265,7 +265,7 @@ resets = <&cpg 904>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7744"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 636248f370e0..0f14ac22921d 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -230,7 +230,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7745"; reg = <0 0xe6060000 0 0x11c>; }; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 6baa126b6590..691b1a131c87 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -187,7 +187,7 @@ resets = <&cpg 907>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77470"; reg = <0 0xe6060000 0 0x118>; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 1612b003fb55..c9f8735860bf 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -142,7 +142,7 @@ interrupt-controller; }; - pfc: pin-controller@fffc0000 { + pfc: pinctrl@fffc0000 { compatible = "renesas,pfc-r8a7778"; reg = <0xfffc0000 0x118>; }; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index c5634daef96f..74d7e9084eab 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -321,7 +321,7 @@ status = "disabled"; }; - pfc: pin-controller@fffc0000 { + pfc: pinctrl@fffc0000 { compatible = "renesas,pfc-r8a7779"; reg = <0xfffc0000 0x23c>; }; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 769ba2a33d39..b0569b4ea5c8 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -363,7 +363,7 @@ resets = <&cpg 907>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 499cf388735f..87f0d6dc3e5a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -286,7 +286,7 @@ resets = <&cpg 904>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 597848ad4dfa..f5b299bfcb23 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -296,7 +296,7 @@ resets = <&cpg 913>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7792"; reg = <0 0xe6060000 0 0x144>; }; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 6d507091b163..f930f69f7bcc 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -271,7 +271,7 @@ resets = <&cpg 904>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7793"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 5f340397ab64..cd5e2904068a 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -238,7 +238,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7794"; reg = <0 0xe6060000 0 0x11c>; }; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index ee59cc84f212..c47896e4ab58 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -165,7 +165,7 @@ status = "disabled"; }; - pinctrl: pin-controller@40067000 { + pinctrl: pinctrl@40067000 { compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; reg = <0x40067000 0x1000>, <0x51000000 0x480>; clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index a4d63125ac56..30c67acc4e35 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -448,7 +448,7 @@ status = "disabled"; }; - pfc: pin-controller@e6050000 { + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-sh73a0"; reg = <0xe6050000 0x8000>, <0xe605801c 0x1c>; -- cgit v1.2.3 From a2053990f3275e715d69c208d8c0040cac0df593 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:24:33 +0200 Subject: arm64: dts: renesas: Fix pin controller node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20200821112433.5652-1-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 8f4820c6ce6b..c15f1c571eb0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -408,7 +408,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774a1"; reg = <0 0xe6060000 0 0x50c>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index b078782119a1..39a1a26ffb54 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -282,7 +282,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774b1"; reg = <0 0xe6060000 0 0x50c>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 10e79f2c0c4e..0e1266ff5dc5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -256,7 +256,7 @@ resets = <&cpg 906>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774c0"; reg = <0 0xe6060000 0 0x508>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 574ef623ae9b..9cbf963aa068 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -457,7 +457,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774e1"; reg = <0 0xe6060000 0 0x50c>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 9beb8e76d923..18ce0face72b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -490,7 +490,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7795"; reg = <0 0xe6060000 0 0x50c>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 4dfb7f076787..f379c8d1511d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -459,7 +459,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 23e6d6529e58..7c8bce9cfdfe 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -448,7 +448,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77961"; reg = <0 0xe6060000 0 0x50c>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index fe4dc12e2bdf..c355460e5f7f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -329,7 +329,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77965"; reg = <0 0xe6060000 0 0x50c>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 2b9124a5ca86..baf8cc821564 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -204,7 +204,7 @@ resets = <&cpg 907>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77970"; reg = <0 0xe6060000 0 0x504>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 59f5bbd72161..d6cae90d7fd9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -234,7 +234,7 @@ resets = <&cpg 907>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77980"; reg = <0 0xe6060000 0 0x50c>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 1991bdc36792..6bf2eb19c6a2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -282,7 +282,7 @@ resets = <&cpg 906>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 2c2272f5f5b5..cd7ca9774196 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -188,7 +188,7 @@ resets = <&cpg 906>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77995"; reg = <0 0xe6060000 0 0x508>; }; -- cgit v1.2.3 From 9ab847043f24f6e83eb905230d050a754e790759 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 8 Sep 2020 09:34:50 +0900 Subject: arm64: dts: renesas: r8a77961: Add FCP device nodes This patch adds FCP device nodes for R-Car M3-W+ (r8a77961) SoC. This patch was tested on R-Car M3-W+ Salvator-XS board. Signed-off-by: Kuninori Morimoto Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/87h7s9rtvl.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 52 +++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 7c8bce9cfdfe..206a4043b5b3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1932,6 +1932,58 @@ status = "disabled"; }; + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A77961_PD_A3VC>; + resets = <&cpg 615>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A77961_PD_A3VC>; + resets = <&cpg 607>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A77961_PD_A3VC>; + resets = <&cpg 611>; + iommus = <&ipmmu_vc0 19>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 601>; + iommus = <&ipmmu_vi0 10>; + }; + csi20: csi2@fea80000 { reg = <0 0xfea80000 0 0x10000>; /* placeholder */ -- cgit v1.2.3 From 298b0c8b2a5fb98bab2dc7846adf0f5e3e3f3d8a Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 8 Sep 2020 09:34:59 +0900 Subject: arm64: dts: renesas: r8a77961: Add VSP device nodes This patch adds VSP device nodes for R-Car M3-W+ (r8a77961) SoC. This patch was tested on R-Car M3-W+ Salvator-XS board. Signed-off-by: Kuninori Morimoto Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/87lfhm70s6.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 55 +++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 206a4043b5b3..a0b85a73dc67 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1984,6 +1984,61 @@ iommus = <&ipmmu_vi0 10>; }; + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A77961_PD_A3VC>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A77961_PD_A3VC>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + csi20: csi2@fea80000 { reg = <0 0xfea80000 0 0x10000>; /* placeholder */ -- cgit v1.2.3 From d56896a40247ae47799e56f8651ce653535909bc Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 8 Sep 2020 09:35:10 +0900 Subject: arm64: dts: renesas: r8a77961: Add DU device nodes This patch adds DU device nodes for R-Car M3-W+ (r8a77961) SoC. This patch was tested on R-Car M3-W+ Salvator-XS board. Signed-off-by: Kuninori Morimoto Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/87eendrtv1.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index a0b85a73dc67..148228a2c0ad 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2093,8 +2093,19 @@ }; du: display@feb00000 { + compatible = "renesas,du-r8a77961"; reg = <0 0xfeb00000 0 0x70000>; - /* placeholder */ + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; + + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; + status = "disabled"; ports { #address-cells = <1>; -- cgit v1.2.3 From 0ecbe08bb43df56591ca88d5becd1eab361bdb62 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 8 Sep 2020 09:35:15 +0900 Subject: arm64: dts: renesas: r8a77961: Add HDMI device nodes This patch adds HDMI device nodes for R-Car M3-W+ (r8a77961) SoC. This patch was tested on R-Car M3-W+ Salvator-XS board. Signed-off-by: Kuninori Morimoto Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/87d02xrtux.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 148228a2c0ad..1ba30313c8b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2073,14 +2073,23 @@ }; hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; }; port@1 { reg = <1>; @@ -2119,6 +2128,7 @@ port@1 { reg = <1>; du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; }; }; port@2 { -- cgit v1.2.3 From 58b1b1ddfcc13900a1bead0e487bbb001ca520ee Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 8 Sep 2020 09:35:20 +0900 Subject: arm64: dts: renesas: r8a77961: salvator-xs: Add HDMI Display support This patch enables HDMI Display on R-Car M3-W+ Salvator-XS board. Signed-off-by: Kuninori Morimoto Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/87blihrtus.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a77961-salvator-xs.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts index 2ffc7e31dd58..ca21a702db54 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts @@ -29,3 +29,31 @@ reg = <0x6 0x00000000 0x1 0x00000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock6 1>, + <&x21_clk>, + <&versaclock6 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; +}; + +&hdmi0_con { + remote-endpoint = <&rcar_dw_hdmi0_out>; +}; -- cgit v1.2.3 From 3137852c13c01abd442b021e6e6af057387988d0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 8 Sep 2020 09:35:25 +0900 Subject: arm64: dts: renesas: r8a77961: salvator-xs: Add HDMI Sound support This patch enables HDMI Sound on R-Car M3-W+ Salvator-XS board. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87a6y1rtun.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a77961-salvator-xs.dts | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts index ca21a702db54..1e7603365106 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts @@ -51,9 +51,38 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; &hdmi0_con { remote-endpoint = <&rcar_dw_hdmi0_out>; }; + +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + reg = <1>; + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + }; +}; + +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1>; /* HDMI0 */ +}; -- cgit v1.2.3 From 28ab4caccd17d7b84fd8aa36b13af5e735870bad Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:03 +0200 Subject: ARM: dts: s5pv210: correct ethernet unit address in SMDKV210 The SROM bank 5 is at address 0xa8000000, just like the one put in "reg" property of ethernet node. Fix the unit address of ethernet node. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-2-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 1e1570d66d89..7459e41e8ef1 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -39,7 +39,7 @@ clock-frequency = <32768>; }; - ethernet@18000000 { + ethernet@a8000000 { compatible = "davicom,dm9000"; reg = <0xA8000000 0x2 0xA8000002 0x2>; interrupt-parent = <&gph1>; -- cgit v1.2.3 From 8b81a8decea77bf2ca3c718732184d4aaf949096 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:04 +0200 Subject: ARM: dts: s3c6410: move fixed clocks under root node in Mini6410 The fixed clocks are kept under dedicated 'clocks' node but this causes multiple dtschema warnings: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' clocks: #size-cells:0:0: 0 is not one of [1, 2] clocks: oscillator@0:reg:0: [0] is too short clocks: oscillator@1:reg:0: [1] is too short clocks: 'ranges' is a required property oscillator@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-3-krzk@kernel.org --- arch/arm/boot/dts/s3c6410-mini6410.dts | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 1aeac33b0d34..75067dbcf7e8 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -28,26 +28,18 @@ bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; + fin_pll: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; }; srom-cs1@18000000 { -- cgit v1.2.3 From c298c89ace615e023c05905b6ec8bfc161488b16 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:05 +0200 Subject: ARM: dts: s3c6410: move fixed clocks under root node in SMDK6410 The fixed clocks are kept under dedicated 'clocks' node but this causes multiple dtschema warnings: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' clocks: #size-cells:0:0: 0 is not one of [1, 2] clocks: oscillator@0:reg:0: [0] is too short clocks: oscillator@1:reg:0: [1] is too short clocks: 'ranges' is a required property oscillator@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-4-krzk@kernel.org --- arch/arm/boot/dts/s3c6410-smdk6410.dts | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts index 96267f5f02a8..74379061a11a 100644 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts @@ -28,26 +28,18 @@ bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; + fin_pll: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; }; srom-cs1@18000000 { -- cgit v1.2.3 From 5911622eff5134c4bf1e16e4e1e2fd18c4f24889 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:06 +0200 Subject: ARM: dts: s3c6410: align node SROM bus node name with dtschema in Mini6410 The SROM controller is modeled with a bus so align the device node name with dtschema to fix warning: srom-cs1@18000000: $nodename:0: 'srom-cs1@18000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-5-krzk@kernel.org --- arch/arm/boot/dts/s3c6410-mini6410.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 75067dbcf7e8..285555b9ed94 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -42,7 +42,7 @@ #clock-cells = <0>; }; - srom-cs1@18000000 { + srom-cs1-bus@18000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From e9da51094a3a8ced023c8b6293319c58ce7c82f9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:07 +0200 Subject: ARM: dts: s3c6410: align node SROM bus node name with dtschema in SMDK6410 The SROM controller is modeled with a bus so align the device node name with dtschema to fix warning: srom-cs1@18000000: $nodename:0: 'srom-cs1@18000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-6-krzk@kernel.org --- arch/arm/boot/dts/s3c6410-smdk6410.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts index 74379061a11a..69c9ec4cf381 100644 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts @@ -42,7 +42,7 @@ #clock-cells = <0>; }; - srom-cs1@18000000 { + srom-cs1-bus@18000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From a904023f7ad404269234387f7a1fab92680ea207 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:08 +0200 Subject: ARM: dts: s3c6410: remove additional CPU compatible Only the specific compatible (arm,arm1176jzf-s) is allowed by dtschema: cpu@0: compatible: ['arm,arm1176jzf-s', 'arm,arm1176'] is too long cpu@0: compatible: Additional items are not allowed ('arm,arm1176' was unexpected) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-7-krzk@kernel.org --- arch/arm/boot/dts/s3c64xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index 2e611df37911..cb11a87dbc42 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -34,7 +34,7 @@ cpu@0 { device_type = "cpu"; - compatible = "arm,arm1176jzf-s", "arm,arm1176"; + compatible = "arm,arm1176jzf-s"; reg = <0x0>; }; }; -- cgit v1.2.3 From 83c968058d5da609f7e584d1262c6e177b9b5fd2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:09 +0200 Subject: ARM: dts: s3c24xx: fix number of PWM cells The PWM has only three cells, not four, as pointed out by dtschema: timer@51000000: #pwm-cells:0:0: 3 was expected Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-8-krzk@kernel.org --- arch/arm/boot/dts/s3c24xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi index 6d8dd3cdd3c0..0d49d7680e72 100644 --- a/arch/arm/boot/dts/s3c24xx.dtsi +++ b/arch/arm/boot/dts/s3c24xx.dtsi @@ -43,7 +43,7 @@ compatible = "samsung,s3c2410-pwm"; reg = <0x51000000 0x1000>; interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; - #pwm-cells = <4>; + #pwm-cells = <3>; }; uart0: serial@50000000 { -- cgit v1.2.3 From 9166c9f8aa12f9a939f97ef8dd0e489b8888273a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:10 +0200 Subject: ARM: dts: s3c24xx: override nodes by label Using full paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-9-krzk@kernel.org --- arch/arm/boot/dts/s3c2416.dtsi | 104 ++++++++++++++++++++--------------------- arch/arm/boot/dts/s3c24xx.dtsi | 22 ++++----- 2 files changed, 63 insertions(+), 63 deletions(-) diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index 6adf64ea3ff2..d1dec9f52f69 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -23,49 +23,12 @@ }; }; - interrupt-controller@4a000000 { - compatible = "samsung,s3c2416-irq"; - }; - clocks: clock-controller@4c000000 { compatible = "samsung,s3c2416-clock"; reg = <0x4c000000 0x40>; #clock-cells = <1>; }; - pinctrl@56000000 { - compatible = "samsung,s3c2416-pinctrl"; - }; - - timer@51000000 { - clocks = <&clocks PCLK_PWM>; - clock-names = "timers"; - }; - - uart_0: serial@50000000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; - - uart_1: serial@50004000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - }; - - uart_2: serial@50008000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - }; - uart_3: serial@5000c000 { compatible = "samsung,s3c2440-uart"; reg = <0x5000C000 0x4000>; @@ -98,22 +61,59 @@ <&clocks MUX_HSMMC1>; status = "disabled"; }; +}; - watchdog: watchdog@53000000 { - interrupts = <1 9 27 3>; - clocks = <&clocks PCLK_WDT>; - clock-names = "watchdog"; - }; +&i2c { + compatible = "samsung,s3c2440-i2c"; + clocks = <&clocks PCLK_I2C0>; + clock-names = "i2c"; +}; - rtc: rtc@57000000 { - compatible = "samsung,s3c2416-rtc"; - clocks = <&clocks PCLK_RTC>; - clock-names = "rtc"; - }; +&intc { + compatible = "samsung,s3c2416-irq"; +}; - i2c@54000000 { - compatible = "samsung,s3c2440-i2c"; - clocks = <&clocks PCLK_I2C0>; - clock-names = "i2c"; - }; +&pinctrl_0 { + compatible = "samsung,s3c2416-pinctrl"; +}; + +&rtc { + compatible = "samsung,s3c2416-rtc"; + clocks = <&clocks PCLK_RTC>; + clock-names = "rtc"; +}; + +&timer { + clocks = <&clocks PCLK_PWM>; + clock-names = "timers"; +}; + +&uart_0 { + compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, + <&clocks SCLK_UART>; +}; + +&uart_1 { + compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, + <&clocks SCLK_UART>; +}; + +&uart_2 { + compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, + <&clocks SCLK_UART>; +}; + +&watchdog { + interrupts = <1 9 27 3>; + clocks = <&clocks PCLK_WDT>; + clock-names = "watchdog"; }; diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi index 0d49d7680e72..80d4ce79be55 100644 --- a/arch/arm/boot/dts/s3c24xx.dtsi +++ b/arch/arm/boot/dts/s3c24xx.dtsi @@ -13,12 +13,12 @@ aliases { pinctrl0 = &pinctrl_0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; + serial0 = &uart_0; + serial1 = &uart_1; + serial2 = &uart_2; }; - intc:interrupt-controller@4a000000 { + intc: interrupt-controller@4a000000 { compatible = "samsung,s3c2410-irq"; reg = <0x4a000000 0x100>; interrupt-controller; @@ -39,49 +39,49 @@ }; }; - timer@51000000 { + timer: timer@51000000 { compatible = "samsung,s3c2410-pwm"; reg = <0x51000000 0x1000>; interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; #pwm-cells = <3>; }; - uart0: serial@50000000 { + uart_0: serial@50000000 { compatible = "samsung,s3c2410-uart"; reg = <0x50000000 0x4000>; interrupts = <1 28 0 4>, <1 28 1 4>; status = "disabled"; }; - uart1: serial@50004000 { + uart_1: serial@50004000 { compatible = "samsung,s3c2410-uart"; reg = <0x50004000 0x4000>; interrupts = <1 23 3 4>, <1 23 4 4>; status = "disabled"; }; - uart2: serial@50008000 { + uart_2: serial@50008000 { compatible = "samsung,s3c2410-uart"; reg = <0x50008000 0x4000>; interrupts = <1 15 6 4>, <1 15 7 4>; status = "disabled"; }; - watchdog@53000000 { + watchdog: watchdog@53000000 { compatible = "samsung,s3c2410-wdt"; reg = <0x53000000 0x100>; interrupts = <0 0 9 3>; status = "disabled"; }; - rtc@57000000 { + rtc: rtc@57000000 { compatible = "samsung,s3c2410-rtc"; reg = <0x57000000 0x100>; interrupts = <0 0 30 3>, <0 0 8 3>; status = "disabled"; }; - i2c@54000000 { + i2c: i2c@54000000 { compatible = "samsung,s3c2410-i2c"; reg = <0x54000000 0x100>; interrupts = <0 0 27 3>; -- cgit v1.2.3 From 17281a3c7f5c4e43ec61efe62c24ff593eb57cf5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:11 +0200 Subject: ARM: dts: s3c24xx: align PWM/timer node name with dtschema Although PWM is used on S3C24xx as clocksource/timer, the dtschema expects the node to be named in certain format: timer@51000000: $nodename:0: 'timer@51000000' does not match '^pwm(@.*|-[0-9a-f])*$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-10-krzk@kernel.org --- arch/arm/boot/dts/s3c24xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi index 80d4ce79be55..06f82c7e458e 100644 --- a/arch/arm/boot/dts/s3c24xx.dtsi +++ b/arch/arm/boot/dts/s3c24xx.dtsi @@ -39,7 +39,7 @@ }; }; - timer: timer@51000000 { + timer: pwm@51000000 { compatible = "samsung,s3c2410-pwm"; reg = <0x51000000 0x1000>; interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; -- cgit v1.2.3 From 2436a7e38f9caa8cc93856015d2c132b44c1c0e8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:12 +0200 Subject: ARM: dts: s3c24xx: add address to CPU node The CPU nodes should be described as children of "cpus" bus node with appropriate "reg" properties: cpus: '#address-cells' is a required property cpus: '#size-cells' is a required property cpu: 'device_type' is a required property cpu: 'reg' is a required property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-11-krzk@kernel.org --- arch/arm/boot/dts/s3c2416.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index d1dec9f52f69..4f084f4fe44f 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -18,8 +18,13 @@ }; cpus { - cpu { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; compatible = "arm,arm926ej-s"; + reg = <0x0>; }; }; -- cgit v1.2.3 From 30b904632eae15c9685552e1e2e2cbe04e6318e9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:13 +0200 Subject: ARM: dts: s3c24xx: move fixed clocks under root node in SMDK2416 The fixed clocks are kept under dedicated 'clocks' node but this causes multiple dtschema warnings: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' clocks: #size-cells:0:0: 0 is not one of [1, 2] clocks: xti@0:reg:0: [0] is too short clocks: 'ranges' is a required property xti@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-12-krzk@kernel.org --- arch/arm/boot/dts/s3c2416-smdk2416.dts | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 811bfdef4e9b..47626ede6fdd 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -17,18 +17,11 @@ reg = <0x30000000 0x4000000>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - xti: xti@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "xti"; - #clock-cells = <0>; - }; + xti: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "xti"; + #clock-cells = <0>; }; }; -- cgit v1.2.3 From edbf3cbe2a173ee7d68854666acf5b05225a75cf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 3 Sep 2020 22:32:49 +0200 Subject: arm64: dts: exynos: Remove undocumented i2s properties in Exynos5433 Few I2S device node properties were not documented and not used by any of the drivers. Remove them to fix dtbs_check warning: arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: i2s@14d60000: Additional properties are not allowed ('samsung,supports-rstclr', 'samsung,supports-tdm', 'samsung,supports-6ch', 'samsung,supports-low-rfs' were unexpected) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200903203250.19830-3-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index b2eebdd88c3c..3933d806a9f6 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1460,10 +1460,6 @@ <&cmu_peric CLK_SCLK_I2S1>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; #clock-cells = <1>; - samsung,supports-6ch; - samsung,supports-rstclr; - samsung,supports-tdm; - samsung,supports-low-rfs; #sound-dai-cells = <1>; status = "disabled"; }; -- cgit v1.2.3 From f9e8785da5a6fb1da11e7233d8720254ef1995a5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 6 Sep 2020 16:21:44 +0200 Subject: ARM: dts: exynos: add input clock to CMU in Exynos3250 Commit 52005dece527 ("ARM: dts: Add assigned clock parents to CMU node for exynos3250") added assigned clocks under Clock Management Unit to fix hangs when accessing ISP registers. However the dtschema expects "clocks" property if "assigned-clocks" are used. Add reference to input clock to silence the dtschema warnings: arch/arm/boot/dts/exynos3250-artik5-eval.dt.yaml: clock-controller@10030000: 'clocks' is a dependency of 'assigned-clocks' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200906142146.21266-1-krzk@kernel.org --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 4 ++++ arch/arm/boot/dts/exynos3250-monk.dts | 4 ++++ arch/arm/boot/dts/exynos3250-rinato.dts | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 6c2f320be2f4..12887b3924af 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -55,6 +55,10 @@ assigned-clock-rates = <6000000>; }; +&cmu { + clocks = <&xusbxti>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 9d77a73bc92b..c1a68e612037 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -164,6 +164,10 @@ status = "okay"; }; +&cmu { + clocks = <&xusbxti>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 3df003af0d15..b55afaaa691e 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -205,6 +205,10 @@ status = "okay"; }; +&cmu { + clocks = <&xusbxti>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; -- cgit v1.2.3 From eaf2d2f6895d676dda6c95a652b58594f2887720 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 6 Sep 2020 16:21:45 +0200 Subject: ARM: dts: exynos: add input clock to CMU in Exynos4412 Odroid Commit 68605101460e ("ARM: dts: exynos: Add support for audio over HDMI for Odroid X/X2/U3") added assigned clocks under Clock Management Unit. However the dtschema expects "clocks" property if "assigned-clocks" are used. Add reference to input clock to silence the dtschema warnings: arch/arm/boot/dts/exynos4412-odroidu3.dt.yaml: clock-controller@10030000: 'clocks' is a dependency of 'assigned-clocks' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200906142146.21266-2-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 2983e91bc7dd..ab291cec650a 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -122,6 +122,7 @@ }; &clock { + clocks = <&clock CLK_XUSBXTI>; assigned-clocks = <&clock CLK_FOUT_EPLL>; assigned-clock-rates = <45158401>; }; -- cgit v1.2.3 From 4afb06afd76855932a2d19c983c013105f1cfb9a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 6 Sep 2020 16:21:46 +0200 Subject: ARM: dts: exynos: move assigned-clock* properties to i2s0 node in Odroid XU4 The purpose of those assigned-clock-* properties is to configure clock for the I2S device so move them to respective node. This silences the dtschema warnings like: 'clocks' is a dependency of 'assigned-clocks' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200906142146.21266-3-krzk@kernel.org --- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 60 ++++++++++++++---------------- 1 file changed, 27 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 892d389d6d09..ddd55d3bcadd 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -35,30 +35,6 @@ samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; - assigned-clocks = <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MOUT_USER_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, - <0>, - <0>, - <0>, - <0>, - <196608001>, - <(196608002 / 2)>, - <196608000>; - cpu { sound-dai = <&i2s0 0>, <&i2s0 1>; }; @@ -69,17 +45,35 @@ }; }; -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, - <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <(196608000 / 256)>, - <196608000>; -}; - &i2s0 { status = "okay"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; + + assigned-clocks = <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MOUT_USER_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&i2s0 CLK_I2S_RCLK_SRC>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_SCLK_I2S>; + + assigned-clock-rates = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <196608001>, + <(196608002 / 2)>, + <196608000>; }; &pwm { -- cgit v1.2.3 From b2b72b00795a397730e606b6c168458e8068682c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 29 Jun 2020 09:02:23 +0200 Subject: arm64: dts: alpine: Align GIC nodename with dtschema Fix dtschema validator warnings like: gic@f0100000: $nodename:0: 'gic@f0100000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index d5e7e2bb4e6c..de2eaf77b1ff 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -113,7 +113,7 @@ ; }; - gic: gic@f0100000 { + gic: interrupt-controller@f0100000 { compatible = "arm,gic-v3"; reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ <0x0 0xf0280000 0x0 0x200000>, /* GICR */ -- cgit v1.2.3 From 5024f03c09e4410db880a900f46fac413cd39855 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 29 Jun 2020 09:24:12 +0200 Subject: arm64: dts: alpine: Fix GIC unit address Node unit address should be the same as first address appearing in "reg" property. Fixes DTC warning: arch/arm64/boot/dts/al/alpine-v2.dtsi:116.38-126.5: Warning (simple_bus_reg): /soc/interrupt-controller@f0100000: simple-bus unit address format error, expected "f0200000" Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index de2eaf77b1ff..4eb2cd14e00b 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -113,7 +113,7 @@ ; }; - gic: interrupt-controller@f0100000 { + gic: interrupt-controller@f0200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ <0x0 0xf0280000 0x0 0x200000>, /* GICR */ -- cgit v1.2.3 From 53486d937cb5090eb6cabb4caf2b0e052136134d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 26 Jun 2020 09:52:31 +0200 Subject: ARM: dts: prima: Align L2 cache-controller nodename with dtschema Fix dtschema validator warnings like: l2-cache-controller@80040000: $nodename:0: 'l2-cache-controller@80040000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski Acked-by: Barry Song --- arch/arm/boot/dts/prima2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 9c7b46b90c3c..7d3d93c22ed9 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -50,7 +50,7 @@ #size-cells = <1>; ranges = <0x40000000 0x40000000 0x80000000>; - l2-cache-controller@80040000 { + cache-controller@80040000 { compatible = "arm,pl310-cache"; reg = <0x80040000 0x1000>; interrupts = <59>; -- cgit v1.2.3 From dcc339affb95ae9f2762164ada3a2f417a854491 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 26 Jun 2020 09:52:58 +0200 Subject: ARM: dts: qcom: Align L2 cache-controller nodename with dtschema Fix dtschema validator warnings like: l2-cache@2040000: $nodename:0: 'l2-cache@2040000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 347b4f7d7889..dda2ceec6591 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -98,7 +98,7 @@ ranges; compatible = "simple-bus"; - L2: l2-cache@2040000 { + L2: cache-controller@2040000 { compatible = "arm,pl310-cache"; reg = <0x02040000 0x1000>; arm,data-latency = <2 2 0>; -- cgit v1.2.3 From 1fbd0475a59f10da047fce3a7c504bc01bb80a45 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 26 Jun 2020 09:53:57 +0200 Subject: ARM: dts: spear: Align L2 cache-controller nodename with dtschema Fix dtschema validator warnings like: l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski Acked-by: Viresh Kumar --- arch/arm/boot/dts/spear13xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index f187da4485f4..c87b881b2c8b 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -43,7 +43,7 @@ 0 7 0x04>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xed000000 0x1000>; cache-unified; -- cgit v1.2.3 From 55d3db1103c47d8b66377b5180f0c27b3d97d5b5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 26 Jun 2020 09:54:52 +0200 Subject: ARM: dts: tango: Align L2 cache-controller nodename with dtschema Fix dtschema validator warnings like: l2-cache-controller@20100000: $nodename:0: 'l2-cache-controller@20100000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski Acked-by: Mans Rullgard --- arch/arm/boot/dts/tango4-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi index 54fd522badfc..d584da314500 100644 --- a/arch/arm/boot/dts/tango4-common.dtsi +++ b/arch/arm/boot/dts/tango4-common.dtsi @@ -51,7 +51,7 @@ }; }; - l2cc: l2-cache-controller@20100000 { + l2cc: cache-controller@20100000 { compatible = "arm,pl310-cache"; reg = <0x20100000 0x1000>; cache-level = <2>; -- cgit v1.2.3 From 14ed3139e10b5f3648988d844a47ae7e9650408e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 26 Jun 2020 09:56:10 +0200 Subject: ARM: dts: zx: Align L2 cache-controller nodename with dtschema Fix dtschema validator warnings like: l2-cache-controller@c00000: $nodename:0: 'l2-cache-controller@c00000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jun Nie --- arch/arm/boot/dts/zx296702.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi index afd98de029be..f378c661b3bf 100644 --- a/arch/arm/boot/dts/zx296702.dtsi +++ b/arch/arm/boot/dts/zx296702.dtsi @@ -58,7 +58,7 @@ clocks = <&topclk ZX296702_A9_PERIPHCLK>; }; - l2cc: l2-cache-controller@c00000 { + l2cc: cache-controller@c00000 { compatible = "arm,pl310-cache"; reg = <0x00c00000 0x1000>; cache-unified; -- cgit v1.2.3 From 48d5732cdf57b82ff32d198f7e696386979f8b08 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 29 Jun 2020 08:56:29 +0200 Subject: ARM: dts: alpine: Align GIC nodename with dtschema Fix dtschema validator warnings like: gic@fb001000: $nodename:0: 'gic@fb001000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/alpine.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index d3036ea823d1..3b0675a1c460 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -91,7 +91,7 @@ }; /* Interrupt Controller */ - gic: gic@fb001000 { + gic: interrupt-controller@fb001000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; #size-cells = <0>; -- cgit v1.2.3 From 77809cf74a8c8ab21b02cc16f2bdc0dc1ed36421 Mon Sep 17 00:00:00 2001 From: Amit Pundir Date: Fri, 11 Sep 2020 21:45:40 +0530 Subject: arm64: dts: qcom: Add support for Xiaomi Poco F1 (Beryllium) Add initial dts support for Xiaomi Poco F1 (Beryllium). This initial support is based on upstream Dragonboard 845c (sdm845) device. With this dts, Beryllium boots AOSP up to ADB shell over USB-C. Supported functionality includes UFS, USB-C (peripheral), microSD card and Vol+/Vol-/power keys. Bluetooth should work too but couldn't be verified from adb command line, it is verified when enabled from UI with few WIP display patches. Just like initial db845c support, initializing the SMMU is clearing the mapping used for the splash screen framebuffer, which causes the device to hang during boot and recovery needs a hard power reset. This can be worked around using: fastboot oem select-display-panel none To switch ON the display back run: fastboot oem select-display-panel But this only works on Beryllium devices running bootloader version BOOT.XF.2.0-00369-SDM845LZB-1 that shipped with Android-9 based release. Newer bootloader version do not support switching OFF the display panel at all. Reviewed-by: Konrad Dybcio Signed-off-by: Amit Pundir Link: https://lore.kernel.org/r/1599840940-18144-1-git-send-email-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 380 +++++++++++++++++++++ 2 files changed, 381 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 359811894eac..e0a1d4769586 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts new file mode 100644 index 000000000000..86cbae63eaf7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include +#include +#include +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/* + * Delete following upstream (sdm845.dtsi) reserved + * memory mappings which are different in this device. + */ +/delete-node/ &tz_mem; +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &rmtfs_mem; + +/ { + model = "Xiaomi Pocophone F1"; + compatible = "xiaomi,beryllium", "qcom,sdm845"; + + /* required for bootloader to select correct board */ + qcom,board-id = <69 0>; + qcom,msm-id = <321 0x20001>; + + aliases { + hsuart0 = &uart6; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin_a>; + + vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + }; + }; + + /* Reserved memory changes from downstream */ + reserved-memory { + tz_mem: memory@86200000 { + reg = <0 0x86200000 0 0x4900000>; + no-map; + }; + + adsp_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1e00000>; + no-map; + }; + + wlan_msa_mem: memory@8e300000 { + reg = <0 0x8e300000 0 0x100000>; + no-map; + }; + + mpss_region: memory@8e400000 { + reg = <0 0x8e400000 0 0x7800000>; + no-map; + }; + + venus_mem: memory@95c00000 { + reg = <0 0x95c00000 0 0x500000>; + no-map; + }; + + cdsp_mem: memory@96100000 { + reg = <0 0x96100000 0 0x800000>; + no-map; + }; + + mba_region: memory@96900000 { + reg = <0 0x96900000 0 0x200000>; + no-map; + }; + + slpi_mem: memory@96b00000 { + reg = <0 0x96b00000 0 0x1400000>; + no-map; + }; + + spss_mem: memory@97f00000 { + reg = <0 0x97f00000 0 0x100000>; + no-map; + }; + + rmtfs_mem: memory@f6301000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf6301000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + }; + + vreg_s4a_1p8: vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&adsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/adsp.mdt"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = ; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; +}; + +&cdsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/cdsp.mdt"; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/a630_zap.mbn"; + }; +}; + +&mss_pil { + status = "okay"; + firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mdt"; +}; + +&pm8998_gpio { + vol_up_pin_a: vol-up-active { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + }; +}; + +&pm8998_pon { + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + bus-width = <4>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + sdc2_default_state: sdc2-default { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_card_det_n: sd-card-det-n { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + cts { + pins = "gpio45"; + bias-disable; + }; + + rts-tx { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio48"; + bias-pull-up; + }; +}; -- cgit v1.2.3 From 0f4c40f10242463400950ef8b3ecd45c95bbefca Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Sep 2020 16:53:07 +0200 Subject: arm64: dts: imx8mm-var-som-symphony: Use newer interrupts property The int-gpios was deprecated in favor of generic interrupts property. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 0bca737964d5..fe3abd9d002f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -113,7 +113,7 @@ extcon_usbotg1: typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; - int-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + interrupts = <&gpio1 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; status = "okay"; -- cgit v1.2.3 From 7124b34fab911c53563f0a8f0c8f7d87222f4e5e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Sep 2020 16:53:08 +0200 Subject: arm64: dts: imx8mp-evk: Align pin configuration group names with schema Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... 'usdhc3grp-100mhz', 'usdhc3grp-200mhz' do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 3d535f1b3440..ad66f1286d95 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -157,7 +157,7 @@ >; }; - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 >; @@ -182,7 +182,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 @@ -194,7 +194,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 @@ -206,7 +206,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grp-gpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 >; @@ -228,7 +228,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 @@ -244,7 +244,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 -- cgit v1.2.3 From 791619f66843a213784efb2f171be98933bad991 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Sep 2020 16:53:09 +0200 Subject: arm64: dts: imx8mq: Add missing interrupts to GPC The i.MX General Power Controller v2 device node was missing interrupts property necessary to route its interrupt to GIC. This also fixes the dbts_check warnings like: arch/arm64/boot/dts/freescale/imx8mq-evk.dt.yaml: gpc@303a0000: {'compatible': ... '$nodename': ['gpc@303a0000']} is not valid under any of the given schemas arch/arm64/boot/dts/freescale/imx8mq-evk.dt.yaml: gpc@303a0000: 'interrupts' is a required property Fixes: fdbcc04da246 ("arm64: dts: imx8mq: add GPC power domains") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 4c7d2146bce2..515b6d79c3a5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -623,6 +623,7 @@ gpc: gpc@303a0000 { compatible = "fsl,imx8mq-gpc"; reg = <0x303a0000 0x10000>; + interrupts = ; interrupt-parent = <&gic>; interrupt-controller; #interrupt-cells = <3>; -- cgit v1.2.3 From 0188e9947c82c0e409420d389c9b103b33f50520 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Sep 2020 16:53:10 +0200 Subject: arm64: dts: imx8mq-librem5: Align regulator names with schema Device tree schema expects regulator names to be lowercase. This fixes dtbs_check warnings like: pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-7]$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 30 +++++++++++------------ 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index c3e290703fe8..4e50cb62654d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -645,7 +645,7 @@ regulators { buck1_reg: BUCK1 { - regulator-name = "BUCK1"; + regulator-name = "buck1"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-ramp-delay = <1250>; @@ -656,7 +656,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "BUCK2"; + regulator-name = "buck2"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-ramp-delay = <1250>; @@ -666,7 +666,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "BUCK3"; + regulator-name = "buck3"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; rohm,dvs-run-voltage = <900000>; @@ -674,42 +674,42 @@ }; buck4_reg: BUCK4 { - regulator-name = "BUCK4"; + regulator-name = "buck4"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; rohm,dvs-run-voltage = <1000000>; }; buck5_reg: BUCK5 { - regulator-name = "BUCK5"; + regulator-name = "buck5"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; regulator-always-on; }; buck6_reg: BUCK6 { - regulator-name = "BUCK6"; + regulator-name = "buck6"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; buck7_reg: BUCK7 { - regulator-name = "BUCK7"; + regulator-name = "buck7"; regulator-min-microvolt = <1605000>; regulator-max-microvolt = <1995000>; regulator-always-on; }; buck8_reg: BUCK8 { - regulator-name = "BUCK8"; + regulator-name = "buck8"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-always-on; }; ldo1_reg: LDO1 { - regulator-name = "LDO1"; + regulator-name = "ldo1"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; /* leave on for snvs power button */ @@ -717,7 +717,7 @@ }; ldo2_reg: LDO2 { - regulator-name = "LDO2"; + regulator-name = "ldo2"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; /* leave on for snvs power button */ @@ -725,14 +725,14 @@ }; ldo3_reg: LDO3 { - regulator-name = "LDO3"; + regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; ldo4_reg: LDO4 { - regulator-name = "LDO4"; + regulator-name = "ldo4"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -740,7 +740,7 @@ ldo5_reg: LDO5 { /* VDD_PHY_0V9 - MIPI and HDMI domains */ - regulator-name = "LDO5"; + regulator-name = "ldo5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -748,7 +748,7 @@ ldo6_reg: LDO6 { /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ - regulator-name = "LDO6"; + regulator-name = "ldo6"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -756,7 +756,7 @@ ldo7_reg: LDO7 { /* VDD_PHY_3V3 - USB domain */ - regulator-name = "LDO7"; + regulator-name = "ldo7"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; -- cgit v1.2.3 From 67daa514553b6bd315f8c23138e1486668939fb0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Sep 2020 16:53:11 +0200 Subject: arm64: dts: imx8mq-librem5: Drop interrupt-names in PMIC The 'interrupt-names' property is not described in dtschema, not used by the driver and does not really make sense as its value is simple 'irq'. Drop it to fix dtbs_check warnings like: arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dt.yaml: pmic@4b: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 1 - arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 10f30ff85fd3..cce1b595e2d6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -289,7 +289,6 @@ clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; interrupts = <3 GPIO_ACTIVE_LOW>; - interrupt-names = "irq"; rohm,reset-snvs-powered; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 4e50cb62654d..a78584086fa9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -640,7 +640,6 @@ clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; interrupts = <7 GPIO_ACTIVE_LOW>; - interrupt-names = "irq"; rohm,reset-snvs-powered; regulators { -- cgit v1.2.3 From dd429a462128cb12dc4b55f6812fcab46b3c0395 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Sep 2020 16:53:12 +0200 Subject: arm64: dts: imx8mq-librem5: Add interrupt-names to ti,tps6598x The ti,tps6598x binding requires interrupt-names property. The driver does not really use it but the hardware could have more interrupt lines connected. This fixes dtbs_check warning: arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dt.yaml: usb-pd@3f: 'interrupt-names' is a required property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index a78584086fa9..56295dd2fa8f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -605,6 +605,7 @@ pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; interrupt-parent = <&gpio1>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; connector { ports { -- cgit v1.2.3 From afe617cb5fce7c37d9721008cf0ea89a587d3749 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 7 Sep 2020 10:04:27 +0200 Subject: ARM: dts: imx6qdl-tqma6: fix indentation The PMIC configuration is indented one level too deep. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tqma6.dtsi | 188 +++++++++++++++++------------------ 1 file changed, 94 insertions(+), 94 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi index 29bcce20f5f3..9513020ddd1a 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi @@ -83,101 +83,101 @@ }; &pmic { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_vddcore: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_vddsoc: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_gen_3v3: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_ddr_1v5a: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_1v5b: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5v_600mA: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-always-on; - }; - - reg_snvs_3v: vsnvs { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - reg_vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1_1v5: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - /* not used */ - }; - - reg_vgen2_1v2_eth: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - reg_vgen3_2v8: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen4_1v8: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5_1v8_eth: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6_3v3: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vddcore: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-always-on; + }; + + reg_snvs_3v: vsnvs { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vgen2_1v2_eth: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen4_1v8: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_1v8_eth: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; }; /* eMMC */ -- cgit v1.2.3 From 1b61fa93179a88caeb7ed77ff66468f48805bed7 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 7 Sep 2020 10:04:28 +0200 Subject: ARM: dts: imx6qdl-tqma6: remove obsolete fsl,spi-num-chipselects This property is unneeded and not supported by the spi-imx driver. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tqma6.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi index 9513020ddd1a..b18b83ac6aee 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi @@ -20,7 +20,6 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; status = "okay"; -- cgit v1.2.3 From 888bb3d2ccfbdc33dc947623e4a37841f6d8c0d4 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 7 Sep 2020 10:04:29 +0200 Subject: ARM: dts: imx6qdl-tqma6: fix LM75 compatible string Specify the National LM75 sensor including its vendor name, as mandated by the binding docs. Fixes: cac849e9bbc8 ("ARM: dts: imx6qdl: add TQMa6{S,Q,QP} SoM") Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tqma6a.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-tqma6b.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi index c18a06cf7929..b679bec78e6c 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi @@ -16,7 +16,7 @@ }; sensor@48 { - compatible = "lm75"; + compatible = "national,lm75"; reg = <0x48>; }; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi index a7460075f517..49c472285c06 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi @@ -16,7 +16,7 @@ }; sensor@48 { - compatible = "lm75"; + compatible = "national,lm75"; reg = <0x48>; }; -- cgit v1.2.3 From 955c69f75eba1fcb0bcc78cf49533c9a3bb381ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Sep 2020 17:02:41 +0200 Subject: arm64: dts: imx8mm-var-som-symphony: Drop unused gpioledgrp The gpioledgrp in iomux is not used, so it can be dropped. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index fe3abd9d002f..84a59be209f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -193,12 +193,6 @@ >; }; - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 -- cgit v1.2.3 From 76bd127e6ca51e4fc257f3d82813c92a322e13d2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 14 Sep 2020 01:51:35 +0300 Subject: arm64: dts: qcom: sm8250: add bi_tcxo_ao to gcc clocks Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20200913225135.30366-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c9021685e03d..0d3a954e477f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -394,8 +394,12 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; }; ipcc: mailbox@408000 { -- cgit v1.2.3 From c0011172f9417b414f51c4ff351519dc8244c925 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 14 Sep 2020 01:47:38 +0300 Subject: arm64: dts: qcom: sm8250-mtp: add i2c device tree nodes Add device tree nodes describing used i2c busses according to the dts found in msm-4.19 tree. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20200913224738.30046-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 6e2f7ae1d621..fd194ed7fbc8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -358,10 +358,38 @@ firmware-name = "qcom/sm8250/cdsp.mbn"; }; +&i2c1 { + status = "okay"; + clock-frequency = <1000000>; + + /* NQ NFC chip @28 */ +}; + +&i2c13 { + status = "okay"; + + /* st,stmfts @ 49 */ +}; + +&i2c15 { + status = "okay"; + + /* smb1390 @ 10 */ + /* rtc6226 @ 64 */ +}; + +&qupv3_id_0 { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8250/slpi.mbn"; -- cgit v1.2.3 From 135db20655ca73ca328b9379fd181e5c87ab6429 Mon Sep 17 00:00:00 2001 From: Venkata Lakshmi Narayana Gubba Date: Thu, 10 Sep 2020 16:19:40 +0530 Subject: arm64: dts: qcom: sc7180: Remove clock for bluetooth on SC7180 IDP board Removed voting for RPMH_RF_CLK2 which is not required as it is getting managed by BT SoC through SW_CTRL line. Signed-off-by: Venkata Lakshmi Narayana Gubba Link: https://lore.kernel.org/r/1599734980-22580-1-git-send-email-gubbaven@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index d8b550723b32..d033b3aad54e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -353,7 +353,6 @@ vddrf-supply = <&vreg_l2c_1p3>; vddch0-supply = <&vreg_l10c_3p3>; max-speed = <3200000>; - clocks = <&rpmhcc RPMH_RF_CLK2>; }; }; -- cgit v1.2.3 From bcd86d327a65b5aa7dc4e42f4c65810b1b071263 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 8 Sep 2020 13:31:17 -0700 Subject: arm64: dts: qcom: Add sc7180-lazor sku2 Add a new SKU variant. This is a pick from the downstream tree that is the current source of truth for this platform. Link: https://crrev.com/c/2386997 Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20200908133037.1.Ia98a6b938453254e360c4a9fa253d2d6807dff3f@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e0a1d4769586..7d71a51ca4ea 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts new file mode 100644 index 000000000000..c3f426c3c30a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +#include "sc7180-trogdor-lazor-r1.dts" + +/ { + model = "Google Lazor (rev1+) with KB Backlight"; + compatible = "google,lazor-sku2", "qcom,sc7180"; +}; + +&keyboard_backlight { + status = "okay"; +}; -- cgit v1.2.3 From 9ff8b0591fcfdb455ae3797c2b592fa20a57726b Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Thu, 3 Sep 2020 17:59:23 -0400 Subject: arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk Downstream has this clock as 32000 rate, but testing shows it is close to 32768. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200903215923.14314-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 0d3a954e477f..18b6e4ddae62 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -73,7 +73,7 @@ sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32768>; #clock-cells = <0>; }; }; -- cgit v1.2.3 From 949766e0a32aa9671e4a9a2d4bc1491a42f9743a Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 31 Aug 2020 13:57:08 +0530 Subject: arm64: dts: ipq8074: enable watchdog support Enable watchdog support for the IPQ8074 SoCs. Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/1598862428-13996-1-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 96a5ec89b5f0..74a474300314 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -498,6 +498,14 @@ ; }; + watchdog: watchdog@b017000 { + compatible = "qcom,kpss-wdt"; + reg = <0xb017000 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + timeout-sec = <30>; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 7a1dcc9d022f180ef95cc966dfbbfc22dc6efa1c Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 22:08:45 +0200 Subject: arm64: dts: qcom: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Link: https://lore.kernel.org/r/20200830200845.1771-1-freifunk@adrianschmutzler.de Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 6 ++--- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 34 ++++++++++++++-------------- arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 2 +- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 +++++----- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- 6 files changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 194343510dcb..8665d3464e9b 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -585,7 +585,7 @@ }; &camss { - status = "ok"; + status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; @@ -602,7 +602,7 @@ }; &cci { - status = "ok"; + status = "okay"; }; &cci_i2c0 { diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index b31117a93995..e8eaa958c199 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -26,18 +26,18 @@ &blsp1_uart3 { pinctrl-0 = <&serial_3_pins>; pinctrl-names = "default"; - status = "ok"; + status = "okay"; }; &i2c_1 { pinctrl-0 = <&i2c_1_pins>; pinctrl-names = "default"; - status = "ok"; + status = "okay"; }; &spi_0 { cs-select = <0>; - status = "ok"; + status = "okay"; m25p80@0 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index f4a76162ab5f..e8c37a1693d3 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -27,11 +27,11 @@ }; &blsp1_i2c2 { - status = "ok"; + status = "okay"; }; &blsp1_spi1 { - status = "ok"; + status = "okay"; m25p80@0 { #address-cells = <1>; @@ -43,37 +43,37 @@ }; &blsp1_uart3 { - status = "ok"; + status = "okay"; }; &blsp1_uart5 { - status = "ok"; + status = "okay"; }; &pcie0 { - status = "ok"; + status = "okay"; perst-gpio = <&tlmm 61 0x1>; }; &pcie1 { - status = "ok"; + status = "okay"; perst-gpio = <&tlmm 58 0x1>; }; &pcie_phy0 { - status = "ok"; + status = "okay"; }; &pcie_phy1 { - status = "ok"; + status = "okay"; }; &qpic_bam { - status = "ok"; + status = "okay"; }; &qpic_nand { - status = "ok"; + status = "okay"; nand@0 { reg = <0>; @@ -84,29 +84,29 @@ }; &sdhc_1 { - status = "ok"; + status = "okay"; }; &qusb_phy_0 { - status = "ok"; + status = "okay"; }; &qusb_phy_1 { - status = "ok"; + status = "okay"; }; &ssphy_0 { - status = "ok"; + status = "okay"; }; &ssphy_1 { - status = "ok"; + status = "okay"; }; &usb_0 { - status = "ok"; + status = "okay"; }; &usb_1 { - status = "ok"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts index 479ad3ac6c28..08d5d51221cf 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -13,7 +13,7 @@ }; ðernet { - status = "ok"; + status = "okay"; snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; snps,reset-active-low; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 6422cf9d5855..a80c578484ba 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -97,7 +97,7 @@ }; &pcie { - status = "ok"; + status = "okay"; perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; @@ -106,22 +106,22 @@ }; &pcie_phy { - status = "ok"; + status = "okay"; vdda-vp-supply = <&vreg_l3_1p05>; vdda-vph-supply = <&vreg_l5_1p8>; }; &remoteproc_adsp { - status = "ok"; + status = "okay"; }; &remoteproc_cdsp { - status = "ok"; + status = "okay"; }; &remoteproc_wcss { - status = "ok"; + status = "okay"; }; &rpm_requests { @@ -215,7 +215,7 @@ }; &sdcc1 { - status = "ok"; + status = "okay"; supports-cqe; mmc-ddr-1_8v; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 99d33955270e..7cc236575ee2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1103,7 +1103,7 @@ }; &cci { - status = "ok"; + status = "okay"; }; &cci_i2c0 { -- cgit v1.2.3 From 5a8c1669f3de2181745b5e9bb9c6758dae301a04 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 17 Aug 2020 12:48:39 +0530 Subject: dt-bindings: mailbox: add compatible for the IPQ6018 SoC Add the mailbox compatible for the IPQ6018 SoC. Acked-by: Rob Herring Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/1597648720-13649-2-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 8f810fc5c183..ffd09b664ff5 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -16,6 +16,7 @@ maintainers: properties: compatible: enum: + - qcom,ipq6018-apcs-apps-global - qcom,ipq8074-apcs-apps-global - qcom,msm8916-apcs-kpss-global - qcom,msm8994-apcs-kpss-global -- cgit v1.2.3 From 36f91e63160856344a25f8b814a65765756a2141 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 17 Aug 2020 12:48:40 +0530 Subject: arm64: dts: ipq6018: enable DVFS support Add A53 PLL, APCS clock, RPM Glink, RPM message RAM, cpu-opp-table, SMPA2 regulator to enable the cpu frequency on IPQ6018. Co-developed-by: Sivaprakash Murugesan Signed-off-by: Sivaprakash Murugesan Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/1597648720-13649-3-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 96 +++++++++++++++++++++++++++++++++-- 1 file changed, 93 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 1aa8d8579463..a94dac76bf3f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { #address-cells = <2>; @@ -38,6 +39,10 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; }; CPU1: cpu@1 { @@ -46,6 +51,10 @@ enable-method = "psci"; reg = <0x1>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; }; CPU2: cpu@2 { @@ -54,6 +63,10 @@ enable-method = "psci"; reg = <0x2>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; }; CPU3: cpu@3 { @@ -62,6 +75,10 @@ enable-method = "psci"; reg = <0x3>; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; }; L2_0: l2-cache { @@ -70,6 +87,42 @@ }; }; + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <725000>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <787500>; + clock-latency-ns = <200000>; + }; + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <862500>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm"; @@ -98,6 +151,11 @@ #size-cells = <2>; ranges; + rpm_msg_ram: memory@0x60000 { + reg = <0x0 0x60000 0x0 0x6000>; + no-map; + }; + tz: tz@48500000 { reg = <0x0 0x48500000 0x0 0x00200000>; no-map; @@ -294,12 +352,22 @@ }; apcs_glb: mailbox@b111000 { - compatible = "qcom,ipq8074-apcs-apps-global"; - reg = <0x0b111000 0xc>; - + compatible = "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + clocks = <&a53pll>, <&xo>; + clock-names = "pll", "xo"; #mbox-cells = <1>; }; + a53pll: clock@b116000 { + compatible = "qcom,ipq6018-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo>; + clock-names = "xo"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -440,4 +508,26 @@ #interrupt-cells = <2>; }; }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: glink-channel { + compatible = "qcom,rpm-ipq6018"; + qcom,glink-channels = "rpm_requests"; + + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; + }; + }; }; -- cgit v1.2.3 From 292b18741eb2a24a2c92fae1e9fde05a6b212ea6 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 17 Aug 2020 10:58:36 +0530 Subject: arm64: dts: ipq8074: Use the A53 PMU compatible IPQ8074 has A53 cores, so lets use the corresponding PMU compatible. Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/1597642116-15902-1-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 74a474300314..829e37ac82f6 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -67,7 +67,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = ; }; -- cgit v1.2.3 From 5f854f096f1979865816a4f51d84e2a0f1095a0f Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Thu, 6 Aug 2020 15:02:10 +0530 Subject: dt-bindings: qcom: Add ipq8074 bindings Document the new device-tree bindings for boards HK10-C1 and HK10-C2 based on ipq8074 SoC. Acked-by: Rob Herring Signed-off-by: Gokul Sriram Palanisamy Link: https://lore.kernel.org/r/1596706332-12957-2-git-send-email-gokulsri@codeaurora.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1adc8a33a3e4..e26b1845004f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -48,6 +48,8 @@ description: | cp01-c1 dragonboard hk01 + hk10-c1 + hk10-c2 idp liquid mtp @@ -149,6 +151,8 @@ properties: - items: - enum: - qcom,ipq8074-hk01 + - qcom,ipq8074-hk10-c1 + - qcom,ipq8074-hk10-c2 - const: qcom,ipq8074 - items: -- cgit v1.2.3 From 51e9874d382e089f664b3ce12773bbbaece5f369 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 11 Aug 2020 12:25:03 -0700 Subject: arm64: dts: qcom: sc7180: Drop flags on mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two where the second cell is the irq flags. Drop the second cell to match the binding. Cc: Kalyan Thota Cc: Harigovindan P Link: https://lore.kernel.org/r/20200811192503.1811462-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 12fede0532a3..ac909249886a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2848,7 +2848,7 @@ power-domains = <&rpmhpd SC7180_CX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; status = "disabled"; @@ -2896,7 +2896,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, -- cgit v1.2.3 From b1c0da47cc1797fce8e426f697139ab84170aee7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Patron?= Date: Sat, 25 Jul 2020 10:24:17 +0200 Subject: arm64: dts: qcom: pm660: Fix missing pound sign in interrupt-cells MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also add a space after '=' while at it. Tested-by: Konrad Dybcio Signed-off-by: Łukasz Patron Link: https://lore.kernel.org/r/20200725082417.8507-1-priv.luk@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index ea0e9558d0f2..2e6a6f6c3b66 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -44,7 +44,7 @@ gpio-ranges = <&pm660_gpios 0 0 13>; #gpio-cells = <2>; interrupt-controller; - interrupt-cells =<2>; + #interrupt-cells = <2>; }; }; }; -- cgit v1.2.3 From 64ea21e0173778c5dde08394418cfd5e8cf54641 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 22:05:51 +0200 Subject: arm64: dts: hisilicon: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 6 +++--- arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts | 2 +- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 18 +++++++++--------- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 6 +++--- arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 18 +++++++++--------- arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 20 ++++++++++---------- 7 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index c1b614dabb8e..963300eede17 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -530,7 +530,7 @@ rt1711h: rt1711h@4e { compatible = "richtek,rt1711h"; reg = <0x4e>; - status = "ok"; + status = "okay"; interrupt-parent = <&gpio27>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; @@ -570,7 +570,7 @@ }; adv7533: adv7533@39 { - status = "ok"; + status = "okay"; compatible = "adi,adv7533"; reg = <0x39>; adi,dsi-lanes = <4>; @@ -656,7 +656,7 @@ &sdio_cfg_func>; /* WL_EN */ vmmc-supply = <&wlan_en>; - status = "ok"; + status = "okay"; wlcore: wlcore@2 { compatible = "ti,wl1837"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index 7dac33d4fd5c..7f9f9886c349 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -418,7 +418,7 @@ &sdio_cfg_func>; /* WL_EN */ vmmc-supply = <&wlan_en>; - status = "ok"; + status = "okay"; wlcore: wlcore@2 { compatible = "ti,wl1837"; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 533ed523888d..91d08673c02e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -267,7 +267,7 @@ &uart1 { assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>; assigned-clock-rates = <150000000>; - status = "ok"; + status = "okay"; bluetooth { compatible = "ti,wl1835-st"; @@ -278,21 +278,21 @@ }; &uart2 { - status = "ok"; + status = "okay"; label = "LS-UART0"; }; &uart3 { - status = "ok"; + status = "okay"; label = "LS-UART1"; }; &ade { - status = "ok"; + status = "okay"; }; &dsi { - status = "ok"; + status = "okay"; ports { /* 1 for output port */ @@ -489,17 +489,17 @@ &i2c0 { - status = "ok"; + status = "okay"; }; &i2c1 { - status = "ok"; + status = "okay"; }; &i2c2 { #address-cells = <1>; #size-cells = <0>; - status = "ok"; + status = "okay"; adv7533: adv7533@39 { compatible = "adi,adv7533"; @@ -541,5 +541,5 @@ }; &spi0 { - status = "ok"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3d189d9f0d24..3bab4bc6ff99 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -371,7 +371,7 @@ clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; dma-no-cci; dma-type = "hi6220_dma"; - status = "ok"; + status = "okay"; }; dual_timer0: timer@f8008000 { diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index e93c65ede06c..369b69b17b91 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -42,15 +42,15 @@ }; &uart0 { - status = "ok"; + status = "okay"; }; &peri_gpio0 { - status = "ok"; + status = "okay"; }; &lbc { - status = "ok"; + status = "okay"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x0 0x90000000 0x08000000>, diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts index 677862beebef..9f4a930e734d 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts +++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts @@ -22,37 +22,37 @@ }; &ipmi0 { - status = "ok"; + status = "okay"; }; &uart0 { - status = "ok"; + status = "okay"; }; ð0 { - status = "ok"; + status = "okay"; }; ð1 { - status = "ok"; + status = "okay"; }; ð2 { - status = "ok"; + status = "okay"; }; ð3 { - status = "ok"; + status = "okay"; }; &sas1 { - status = "ok"; + status = "okay"; }; &usb_ohci { - status = "ok"; + status = "okay"; }; &usb_ehci { - status = "ok"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts index fcbdffe0868b..81a2312c8a26 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts @@ -50,41 +50,41 @@ }; &uart0 { - status = "ok"; + status = "okay"; }; &ipmi0 { - status = "ok"; + status = "okay"; }; &usb_ohci { - status = "ok"; + status = "okay"; }; &usb_ehci { - status = "ok"; + status = "okay"; }; ð0 { - status = "ok"; + status = "okay"; }; ð1 { - status = "ok"; + status = "okay"; }; ð2 { - status = "ok"; + status = "okay"; }; ð3 { - status = "ok"; + status = "okay"; }; &sas1 { - status = "ok"; + status = "okay"; }; &p0_pcie2_a { - status = "ok"; + status = "okay"; }; -- cgit v1.2.3 From a665b2c1d28403e385054447cc319095527bedde Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 7 Sep 2020 13:18:29 +0100 Subject: arm64: dts: hisilicon: Fix SP805 clocks The SP805 DT binding requires two clocks to be specified, but Hisilicon platform DTs currently only specify one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++++++---- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 5 +++-- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index d25aac5e0bf8..994140fbc916 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1089,16 +1089,18 @@ compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xe8a06000 0x0 0x1000>; interrupts = ; - clocks = <&crg_ctrl HI3660_OSC32K>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "wdog_clk", "apb_pclk"; }; watchdog1: watchdog@e8a07000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xe8a07000 0x0 0x1000>; interrupts = ; - clocks = <&crg_ctrl HI3660_OSC32K>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "wdog_clk", "apb_pclk"; }; tsensor: tsensor@fff30000 { diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3bab4bc6ff99..014735a9bc73 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -843,8 +843,9 @@ compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xf8005000 0x0 0x1000>; interrupts = ; - clocks = <&ao_ctrl HI6220_WDT0_PCLK>; - clock-names = "apb_pclk"; + clocks = <&ao_ctrl HI6220_WDT0_PCLK>, + <&ao_ctrl HI6220_WDT0_PCLK>; + clock-names = "wdog_clk", "apb_pclk"; }; tsensor: tsensor@0,f7030700 { -- cgit v1.2.3 From c26979a7acf20ab093513d8c09e371b212e02ded Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 7 Sep 2020 13:18:26 +0100 Subject: ARM: dts: hisilicon: Fix SP804 users The SP804 binding only specifies one or three clocks, but does not allow just two clocks. The HiSi 3620 .dtsi specified two clocks for the two timers, plus gave one "apb_pclk" clock-name to appease the primecell bus driver. Extend the clocks by duplicating the first clock to the end of the clock list, and add two dummy clock-names to make the primecell driver happy. I don't know what the real APB clock for the IP is, but with the current DT the first timer clock was used for that, so this change keeps the current status. Signed-off-by: Andre Przywara Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3620.dtsi | 30 ++++++++++++++++++++---------- arch/arm/boot/dts/hip04.dtsi | 4 ++-- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index f0af1bf2b4d8..355175b25fd6 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -111,8 +111,10 @@ reg = <0x800000 0x1000>; /* timer00 & timer01 */ interrupts = <0 0 4>, <0 1 4>; - clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER0_MUX>, + <&clock HI3620_TIMER1_MUX>, + <&clock HI3620_TIMER0_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -121,8 +123,10 @@ reg = <0x801000 0x1000>; /* timer10 & timer11 */ interrupts = <0 2 4>, <0 3 4>; - clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER2_MUX>, + <&clock HI3620_TIMER3_MUX>, + <&clock HI3620_TIMER2_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -131,8 +135,10 @@ reg = <0xa01000 0x1000>; /* timer20 & timer21 */ interrupts = <0 4 4>, <0 5 4>; - clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER4_MUX>, + <&clock HI3620_TIMER5_MUX>, + <&clock HI3620_TIMER4_MUX>; + clock-names = "timer0lck", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -141,8 +147,10 @@ reg = <0xa02000 0x1000>; /* timer30 & timer31 */ interrupts = <0 6 4>, <0 7 4>; - clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER6_MUX>, + <&clock HI3620_TIMER7_MUX>, + <&clock HI3620_TIMER6_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -151,8 +159,10 @@ reg = <0xa03000 0x1000>; /* timer40 & timer41 */ interrupts = <0 96 4>, <0 97 4>; - clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER8_MUX>, + <&clock HI3620_TIMER9_MUX>, + <&clock HI3620_TIMER8_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 4263a9339c2e..f5871b1d1ec4 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -226,8 +226,8 @@ compatible = "arm,sp804", "arm,primecell"; reg = <0x3000000 0x1000>; interrupts = <0 224 4>; - clocks = <&clk_50m>, <&clk_50m>; - clock-names = "apb_pclk"; + clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; }; arm-pmu { -- cgit v1.2.3 From 3328c656663f59382879992419859d73f359ac59 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 7 Sep 2020 13:18:31 +0100 Subject: ARM: dts: hisilicon: Fix SP805 clocks The SP805 DT binding requires two clocks to be specified, but Hisilicon platform DTs currently only specify one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara Signed-off-by: Wei Xu --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 3ee7967c202d..e2dbf1d8a67b 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -370,8 +370,9 @@ arm,primecell-periphid = <0x00141805>; reg = <0xa2c000 0x1000>; interrupts = <0 29 4>; - clocks = <&clock HIX5HD2_WDG0_RST>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_WDG0_RST>, + <&clock HIX5HD2_WDG0_RST>; + clock-names = "wdog_clk", "apb_pclk"; }; }; -- cgit v1.2.3 From 80c2145fa5e7ced8c95f17a1a60866951627f43c Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 28 Aug 2020 17:44:35 +0200 Subject: arm64: dts: meson: vim3l: remove sound card definition The sound card definition should have been removed when the common definition was added to the vim3 dtsi but this slips through. Remove it now. Fixes: 7c9c06246cea ("arm64: dts: meson: vim3: make sound card common to all variants") Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200828154435.419561-1-jbrunet@baylibre.com --- .../boot/dts/amlogic/meson-sm1-khadas-vim3l.dts | 86 ---------------------- 1 file changed, 86 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index 0da56c051a0e..4b517ca72059 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -32,69 +32,6 @@ regulator-boot-on; regulator-always-on; }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "SM1-KHADAS-VIM3L"; - audio-aux-devs = <&tdmout_a>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; }; &cpu0 { @@ -125,18 +62,6 @@ clock-latency = <50000>; }; -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; @@ -174,14 +99,3 @@ }; */ -&tdmif_a { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; -- cgit v1.2.3 From 7c6d828e90082bdbf00cbb816d4cd1b30c4109e0 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 14 Sep 2020 16:22:18 -0700 Subject: arm64: dts: qcom: trogdor: Add labels for type-c ports Some trogdor board variants only have one USB port, so add a couple labels to these ports so we can modify them later. Reviewed-by: Douglas Anderson Cc: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20200914232218.658664-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index a6b9beb29be9..f46d331bab47 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -544,7 +544,7 @@ #address-cells = <1>; #size-cells = <0>; - connector@0 { + usb_c0: connector@0 { compatible = "usb-c-connector"; reg = <0>; label = "left"; @@ -553,7 +553,7 @@ try-power-role = "source"; }; - connector@1 { + usb_c1: connector@1 { compatible = "usb-c-connector"; reg = <1>; label = "right"; -- cgit v1.2.3 From ff11a79878a8b43394b296c06557033efd17b1ee Mon Sep 17 00:00:00 2001 From: satya priya Date: Mon, 14 Sep 2020 19:28:34 +0530 Subject: arm64: dts: qcom: sc7180: Improve the uart3 pin config for sc7180-idp Remove output-high from CTS and TX as this is not really required. During bringup to fix transfer failures this was added to match with console uart settings. Probably some boot loader config was missing then. As it is working fine now, remove it. Signed-off-by: satya priya Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/1600091917-7464-2-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index d033b3aad54e..cd8e6fa3301d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -473,32 +473,30 @@ &qup_uart3_default { pinconf-cts { /* - * Configure a pull-down on 38 (CTS) to match the pull of + * Configure a pull-down on CTS to match the pull of * the Bluetooth module. */ pins = "gpio38"; bias-pull-down; - output-high; }; pinconf-rts { - /* We'll drive 39 (RTS), so no pull */ + /* We'll drive RTS, so no pull */ pins = "gpio39"; drive-strength = <2>; bias-disable; }; pinconf-tx { - /* We'll drive 40 (TX), so no pull */ + /* We'll drive TX, so no pull */ pins = "gpio40"; drive-strength = <2>; bias-disable; - output-high; }; pinconf-rx { /* - * Configure a pull-up on 41 (RX). This is needed to avoid + * Configure a pull-up on RX. This is needed to avoid * garbage data when the TX pin of the Bluetooth module is * in tri-state (module powered off or not driving the * signal yet). -- cgit v1.2.3 From 9a36c6fd09952e1018cca734871ff43d850dd971 Mon Sep 17 00:00:00 2001 From: satya priya Date: Mon, 14 Sep 2020 19:28:35 +0530 Subject: arm64: dts: qcom: sc7180: Add wakeup support for BT UART on sc7180-idp Add the necessary pinctrl, interrupt property and a suitable sleep config to support Bluetooth wakeup feature. GPIO mode is configured in sleep state to drive the RTS/RFR line low. If QUP function is selected in sleep state, UART RTS/RFR is pulled high during suspend and BT SoC not able to send wakeup bytes. Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: satya priya Link: https://lore.kernel.org/r/1600091917-7464-3-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 55 +++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index cd8e6fa3301d..e77a7926034a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -346,6 +346,13 @@ &uart3 { status = "okay"; + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart3_sleep>; + bluetooth: wcn3990-bt { compatible = "qcom,wcn3990-bt"; vddio-supply = <&vreg_l10a_1p8>; @@ -544,3 +551,51 @@ }; }; +&tlmm { + qup_uart3_sleep: qup-uart3-sleep { + pinmux { + pins = "gpio38", "gpio39", + "gpio40", "gpio41"; + function = "gpio"; + }; + + pinconf-cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + bias-pull-down; + }; + + pinconf-rts { + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + pins = "gpio39"; + bias-pull-down; + }; + + pinconf-tx { + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + pins = "gpio40"; + bias-pull-up; + }; + + pinconf-rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + pins = "gpio41"; + bias-pull-up; + }; + }; +}; -- cgit v1.2.3 From 4e0a3e04e46865357008c1b60395d4f07d236d4f Mon Sep 17 00:00:00 2001 From: satya priya Date: Mon, 14 Sep 2020 19:28:36 +0530 Subject: arm64: dts: qcom: sc7180-trogdor: Add wakeup support for BT UART Add the necessary pinctrl, interrupt property and a suitable sleep config to support Bluetooth wakeup feature. GPIO mode is configured in sleep state to drive the RTS/RFR line low. If QUP function is selected in sleep state, UART RTS/RFR is pulled high during suspend and BT SoC not able to send wakeup bytes. Tested-by: Matthias Kaehlcke Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: satya priya Link: https://lore.kernel.org/r/1600091917-7464-4-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 54 ++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index f46d331bab47..bf875589d364 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -794,6 +794,13 @@ ap_spi_fp: &spi10 { &uart3 { status = "okay"; + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart3_sleep>; + bluetooth: bluetooth { compatible = "qcom,wcn3991-bt"; vddio-supply = <&pp1800_l10a>; @@ -1307,6 +1314,53 @@ ap_spi_fp: &spi10 { }; }; + qup_uart3_sleep: qup-uart3-sleep { + pinmux { + pins = "gpio38", "gpio39", + "gpio40", "gpio41"; + function = "gpio"; + }; + + pinconf-cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + bias-pull-down; + }; + + pinconf-rts { + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + pins = "gpio39"; + bias-pull-down; + }; + + pinconf-tx { + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + pins = "gpio40"; + bias-pull-up; + }; + + pinconf-rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + pins = "gpio41"; + bias-pull-up; + }; + }; + trackpad_int_1v8_odl: trackpad-int-1v8-odl { pinmux { pins = "gpio58"; -- cgit v1.2.3 From 08a9ae2d255eca73a9ae7ebf2d24f1e206eb3b14 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 9 Sep 2020 13:32:37 +0300 Subject: arch64: dts: qcom: sm8250: add uart nodes Currently sm8250.dtsi only defines default debug uart. Port rest uart nodes from the downstream dtsi file. Acked-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20200909103238.149761-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 74 ++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 18b6e4ddae62..c989bc1370ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -526,6 +526,17 @@ status = "disabled"; }; + uart17: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart17_default>; + interrupts = ; + status = "disabled"; + }; + i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; @@ -552,6 +563,17 @@ status = "disabled"; }; + uart18: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart18_default>; + interrupts = ; + status = "disabled"; + }; + i2c19: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; @@ -668,6 +690,17 @@ status = "disabled"; }; + uart2: serial@988000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart2_default>; + interrupts = ; + status = "disabled"; + }; + i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0098c000 0 0x4000>; @@ -772,6 +805,17 @@ status = "disabled"; }; + uart6: serial@998000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_default>; + interrupts = ; + status = "disabled"; + }; + i2c7: i2c@99c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0099c000 0 0x4000>; @@ -1888,12 +1932,42 @@ }; }; + qup_uart2_default: qup-uart2-default { + mux { + pins = "gpio117", "gpio118"; + function = "qup2"; + }; + }; + + qup_uart6_default: qup-uart6-default { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "qup6"; + }; + }; + qup_uart12_default: qup-uart12-default { mux { pins = "gpio34", "gpio35"; function = "qup12"; }; }; + + qup_uart17_default: qup-uart17-default { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup17"; + }; + }; + + qup_uart18_default: qup-uart18-default { + mux { + pins = "gpio58", "gpio59"; + function = "qup18"; + }; + }; }; adsp: remoteproc@17300000 { -- cgit v1.2.3 From 4134b8ef08329f5994797f7aaa20d54d69016adb Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:53:57 +0200 Subject: arm64: dts: qcom: apq8016-sbc: Remove properties that are already default apq8016-sbc.dtsi overrides several properties that are already the default in msm8916.dtsi. Remove these to simplify the device tree a bit. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 8665d3464e9b..cb9c70a1532a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -387,7 +387,6 @@ adp-disable; hnp-disable; srp-disable; - dr_mode = "otg"; pinctrl-names = "default", "device"; pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; @@ -405,15 +404,7 @@ }; mdss@1a00000 { - status = "okay"; - - mdp@1a01000 { - status = "okay"; - }; - dsi@1a98000 { - status = "okay"; - vdda-supply = <&pm8916_l2>; vddio-supply = <&pm8916_l6>; @@ -428,16 +419,10 @@ }; dsi-phy@1a98300 { - status = "okay"; - vddio-supply = <&pm8916_l6>; }; }; - lpass_codec: codec{ - status = "okay"; - }; - /* Internal Codec playback - Primary MI2S @@ -587,8 +572,6 @@ &camss { status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; port@0 { reg = <0>; csiphy0_ep: endpoint { @@ -651,7 +634,6 @@ }; &wcd_codec { - status = "okay"; clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "mclk"; qcom,mbhc-vthreshold-low = <75 150 237 450 500>; -- cgit v1.2.3 From 974dc2f3959dba54663f0972a8683e28a2f39e24 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:53:58 +0200 Subject: arm64: dts: qcom: msm8916: Declare sound node in msm8916.dtsi The "sound" node in apq8016-sbc.dtsi references memory regions provided by the SoC and should be therefore declared in msm8916.dtsi. Additionally, the machine driver used for the "qcom,apq8016-sbc-sndcard" compatible also works on other MSM8916 devices (provided that audio routing is set up properly). It is not really specific to apq8016-sbc. Simplify setting up sound on other boards by moving the common part to msm8916.dtsi. This also allows referencing the node by the label, so that we can eventually drop the "soc" node entirely from the board-specific device tree part and use labels exclusively. Cc: Srinivas Kandagatla Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 6 +----- arch/arm64/boot/dts/qcom/msm8916.dtsi | 7 +++++++ 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index cb9c70a1532a..bfc5859726ae 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -438,11 +438,7 @@ */ - sound: sound { - compatible = "qcom,apq8016-sbc-sndcard"; - reg = <0x07702000 0x4>, <0x07702004 0x4>; - reg-names = "mic-iomux", "spkr-iomux"; - + sound: sound@7702000 { status = "okay"; pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 67cae5f9e47e..8b12961f3269 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -704,6 +704,13 @@ status = "disabled"; }; + sound: sound@7702000 { + status = "disabled"; + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + }; + lpass: lpass@7708000 { status = "disabled"; compatible = "qcom,lpass-cpu-apq8016"; -- cgit v1.2.3 From 48faf07941a5099fab7b37ee3cf0e54c6cf4a1de Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:53:59 +0200 Subject: arm64: dts: qcom: apq8016-sbc: Define leds outside of soc node The leds node does not use any memory regions of the SoC and should therefore be declared outside the "soc" node. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 104 +++++++++++++++--------------- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index bfc5859726ae..f590063d5665 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -307,58 +307,6 @@ status = "okay"; }; - leds { - pinctrl-names = "default"; - pinctrl-0 = <&msmgpio_leds>, - <&pm8916_gpios_leds>, - <&pm8916_mpps_leds>; - - compatible = "gpio-leds"; - - led@1 { - label = "apq8016-sbc:green:user1"; - gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led@2 { - label = "apq8016-sbc:green:user2"; - gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led@3 { - label = "apq8016-sbc:green:user3"; - gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led@4 { - label = "apq8016-sbc:green:user4"; - gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - panic-indicator; - default-state = "off"; - }; - - led@5 { - label = "apq8016-sbc:yellow:wlan"; - gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led@6 { - label = "apq8016-sbc:blue:bt"; - gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; - sdhci@7824000 { vmmc-supply = <&pm8916_l8>; vqmmc-supply = <&pm8916_l5>; @@ -563,6 +511,58 @@ gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; }; }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&msmgpio_leds>, + <&pm8916_gpios_leds>, + <&pm8916_mpps_leds>; + + compatible = "gpio-leds"; + + led@1 { + label = "apq8016-sbc:green:user1"; + gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@2 { + label = "apq8016-sbc:green:user2"; + gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@3 { + label = "apq8016-sbc:green:user3"; + gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led@4 { + label = "apq8016-sbc:green:user4"; + gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + panic-indicator; + default-state = "off"; + }; + + led@5 { + label = "apq8016-sbc:yellow:wlan"; + gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led@6 { + label = "apq8016-sbc:blue:bt"; + gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; }; &camss { -- cgit v1.2.3 From 2329e5fb54d76fc28a952678e426eb7d3888631c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:54:00 +0200 Subject: arm64: dts: qcom: msm8916: Add more labels Add a few more labels to device nodes declared in msm8916.dtsi so that we can set all needed properties using labels in the board-specific device tree part. Also rename the "otg" label to "usb" to allow grouping it with the USB PHY (usb_hs_phy) node when ordering referenced labels alphabetically. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 40 +++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8b12961f3269..acbaed23bbdd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -781,7 +781,7 @@ status = "disabled"; }; - otg: usb@78d9000 { + usb: usb@78d9000 { compatible = "qcom,ci-hdrc"; reg = <0x78d9000 0x200>, <0x78d9200 0x200>; @@ -809,7 +809,7 @@ #phy-cells = <0>; clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; reset-names = "phy", "por"; qcom,init-seq = /bits/ 8 <0x0 0x44 0x1 0x6b 0x2 0x24 0x3 0x13>; @@ -1151,7 +1151,7 @@ }; - hexagon@4080000 { + mpss: hexagon@4080000 { compatible = "qcom,q6v5-pil"; reg = <0x04080000 0x100>, <0x04020000 0x040>; @@ -1289,7 +1289,7 @@ }; }; - tpiu@820000 { + tpiu: tpiu@820000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0x820000 0x1000>; @@ -1307,7 +1307,7 @@ }; }; - funnel@821000 { + funnel0: funnel@821000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x821000 0x1000>; @@ -1348,7 +1348,7 @@ }; }; - replicator@824000 { + replicator: replicator@824000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0x824000 0x1000>; @@ -1384,7 +1384,7 @@ }; }; - etf@825000 { + etf: etf@825000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x825000 0x1000>; @@ -1410,7 +1410,7 @@ }; }; - etr@826000 { + etr: etr@826000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x826000 0x1000>; @@ -1428,7 +1428,7 @@ }; }; - funnel@841000 { /* APSS funnel only 4 inputs are used */ + funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x841000 0x1000>; @@ -1476,7 +1476,7 @@ }; }; - debug@850000 { + debug0: debug@850000 { compatible = "arm,coresight-cpu-debug","arm,primecell"; reg = <0x850000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; @@ -1485,7 +1485,7 @@ status = "disabled"; }; - debug@852000 { + debug1: debug@852000 { compatible = "arm,coresight-cpu-debug","arm,primecell"; reg = <0x852000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; @@ -1494,7 +1494,7 @@ status = "disabled"; }; - debug@854000 { + debug2: debug@854000 { compatible = "arm,coresight-cpu-debug","arm,primecell"; reg = <0x854000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; @@ -1503,7 +1503,7 @@ status = "disabled"; }; - debug@856000 { + debug3: debug@856000 { compatible = "arm,coresight-cpu-debug","arm,primecell"; reg = <0x856000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; @@ -1598,7 +1598,7 @@ /* System CTIs */ /* CTI 0 - TMC connections */ - cti@810000 { + cti0: cti@810000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x810000 0x1000>; @@ -1609,7 +1609,7 @@ }; /* CTI 1 - TPIU connections */ - cti@811000 { + cti1: cti@811000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x811000 0x1000>; @@ -1623,7 +1623,7 @@ /* Core CTIs; CTIs 12-15 */ /* CTI - CPU-0 */ - cti@858000 { + cti12: cti@858000 { compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", "arm,primecell"; reg = <0x858000 0x1000>; @@ -1638,7 +1638,7 @@ }; /* CTI - CPU-1 */ - cti@859000 { + cti13: cti@859000 { compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", "arm,primecell"; reg = <0x859000 0x1000>; @@ -1653,7 +1653,7 @@ }; /* CTI - CPU-2 */ - cti@85a000 { + cti14: cti@85a000 { compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", "arm,primecell"; reg = <0x85a000 0x1000>; @@ -1668,7 +1668,7 @@ }; /* CTI - CPU-3 */ - cti@85b000 { + cti15: cti@85b000 { compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", "arm,primecell"; reg = <0x85b000 0x1000>; @@ -1821,7 +1821,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm-requests { + rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8916"; qcom,smd-channels = "rpm_requests"; -- cgit v1.2.3 From e2f6482aff1a362f2246091f8227e8b7d9485005 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:54:01 +0200 Subject: arm64: dts: qcom: msm8916: Use labels in board device trees Device trees for newer SoCs avoid replicating the entire device hierarchy in the board-specific device tree part. Instead, they set additional properties only by referencing labels, sorted alphabetically. Now that we have labels for all relevant nodes, convert the MSM8916 board device trees to use the same style and remove the "soc" node entirely. Note: There is a large block of coresight nodes in apq8016-sbc.dtsi, which are enabled by setting status = "okay". I kept them grouped together (not alphabetically sorted with everything else), since that would be just unnecessarily verbose and hard to see. This commit only moves all existing properties to nodes that reference the respective label. The resulting binary DTBs are exactly the same. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-6-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 800 ++++++++++----------- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 107 ++- arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 14 +- .../dts/qcom/msm8916-samsung-a2015-common.dtsi | 139 ++-- 4 files changed, 514 insertions(+), 546 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index f590063d5665..5552773f633e 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -11,30 +11,6 @@ #include #include -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from the schematic "DragonBoard410c" - * dated monday, august 31, 2015. Page 5 in particular. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ - / { aliases { serial0 = &blsp1_uart2; @@ -76,7 +52,7 @@ }; reserved-memory { - ramoops@bff00000{ + ramoops@bff00000 { compatible = "ramoops"; reg = <0x0 0xbff00000 0x0 0x100000>; @@ -86,392 +62,6 @@ }; }; - soc { - pinctrl@1000000 { - gpio-line-names = - "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ - "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ - "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */ - "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */ - "[UART1_TX]", /* GPIO_4, LSEC pin 11 */ - "[UART1_RX]", /* GPIO_5, LSEC pin 13 */ - "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */ - "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */ - "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */ - "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */ - "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */ - "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */ - "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */ - "[I2C3_SDA]", /* HSEC pin 38 */ - "[I2C3_SCL]", /* HSEC pin 36 */ - "[SPI0_MOSI]", /* LSEC pin 14 */ - "[SPI0_MISO]", /* LSEC pin 10 */ - "[SPI0_CS_N]", /* LSEC pin 12 */ - "[SPI0_CLK]", /* LSEC pin 8 */ - "HDMI_HPD_N", /* GPIO 20 */ - "USR_LED_1_CTRL", - "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */ - "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */ - "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */ - "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */ - "[CSI0_MCLK]", /* HSEC pin 15 */ - "[CSI1_MCLK]", /* HSEC pin 17 */ - "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */ - "[I2C2_SDA]", /* HSEC pin 34 */ - "[I2C2_SCL]", /* HSEC pin 32 */ - "DSI2HDMI_INT_N", - "DSI_SW_SEL_APQ", - "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */ - "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */ - "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */ - "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */ - "FORCED_USB_BOOT", - "SD_CARD_DET_N", - "[WCSS_BT_SSBI]", - "[WCSS_WLAN_DATA_2]", /* GPIO 40 */ - "[WCSS_WLAN_DATA_1]", - "[WCSS_WLAN_DATA_0]", - "[WCSS_WLAN_SET]", - "[WCSS_WLAN_CLK]", - "[WCSS_FM_SSBI]", - "[WCSS_FM_SDI]", - "[WCSS_BT_DAT_CTL]", - "[WCSS_BT_DAT_STB]", - "NC", - "NC", /* GPIO 50 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", /* GPIO 60 */ - "NC", - "NC", - "[CDC_PDM0_CLK]", - "[CDC_PDM0_SYNC]", - "[CDC_PDM0_TX0]", - "[CDC_PDM0_RX0]", - "[CDC_PDM0_RX1]", - "[CDC_PDM0_RX2]", - "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */ - "NC", /* GPIO 70 */ - "NC", - "NC", - "NC", - "NC", /* GPIO 74 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "BOOT_CONFIG_0", /* GPIO 80 */ - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_3", - "NC", - "NC", - "BOOT_CONFIG_5", - "NC", - "NC", - "NC", - "NC", /* GPIO 90 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", /* GPIO 100 */ - "NC", - "NC", - "NC", - "SSBI_GPS", - "NC", - "NC", - "KEY_VOLP_N", - "NC", - "NC", - "[LS_EXP_MI2S_WS]", /* GPIO 110 */ - "NC", - "NC", - "[LS_EXP_MI2S_SCK]", - "[LS_EXP_MI2S_DATA0]", - "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */ - "NC", - "[DSI2HDMI_MI2S_WS]", - "[DSI2HDMI_MI2S_SCK]", - "[DSI2HDMI_MI2S_DATA0]", - "USR_LED_2_CTRL", /* GPIO 120 */ - "SB_HS_ID"; - }; - - dma@7884000 { - status = "okay"; - }; - - serial@78af000 { - label = "LS-UART0"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; - }; - - serial@78b0000 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - - i2c@78b6000 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; - }; - - i2c@78b8000 { - /* On High speed expansion */ - label = "HS-I2C2"; - status = "okay"; - - adv_bridge: bridge@39 { - status = "okay"; - - compatible = "adi,adv7533"; - reg = <0x39>; - - interrupt-parent = <&msmgpio>; - interrupts = <31 2>; - - adi,dsi-lanes = <4>; - clocks = <&rpmcc RPM_SMD_BB_CLK2>; - clock-names = "cec"; - - pd-gpios = <&msmgpio 32 0>; - - avdd-supply = <&pm8916_l6>; - v1p2-supply = <&pm8916_l6>; - v3p3-supply = <&pm8916_l17>; - - pinctrl-names = "default","sleep"; - pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; - pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; - #sound-dai-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7533_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7533_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - }; - - i2c@78ba000 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; - }; - - spi@78b7000 { - /* On High speed expansion */ - label = "HS-SPI1"; - status = "okay"; - }; - - spi@78b9000 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; - }; - - sdhci@7824000 { - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - status = "okay"; - }; - - sdhci@7864000 { - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&msmgpio 38 0x1>; - status = "okay"; - }; - - usb@78d9000 { - extcon = <&usb_id>, <&usb_id>; - status = "okay"; - adp-disable; - hnp-disable; - srp-disable; - pinctrl-names = "default", "device"; - pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; - pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; - ulpi { - phy { - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; - extcon = <&usb_id>; - }; - }; - }; - - lpass@7708000 { - status = "okay"; - }; - - mdss@1a00000 { - dsi@1a98000 { - vdda-supply = <&pm8916_l2>; - vddio-supply = <&pm8916_l6>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7533_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - }; - - dsi-phy@1a98300 { - vddio-supply = <&pm8916_l6>; - }; - }; - - /* - Internal Codec - playback - Primary MI2S - capture - Ter MI2S - - External Primary: - playback - secondary MI2S - capture - Quat MI2S - - External Secondary: - playback - Quat MI2S - capture - Quat MI2S - - */ - - sound: sound@7702000 { - status = "okay"; - pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; - pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; - pinctrl-names = "default", "sleep"; - qcom,model = "DB410c"; - qcom,audio-routing = - "AMIC2", "MIC BIAS Internal2", - "AMIC3", "MIC BIAS External1"; - - external-dai-link@0 { - link-name = "ADV7533"; - cpu { - sound-dai = <&lpass MI2S_QUATERNARY>; - }; - codec { - sound-dai = <&adv_bridge 0>; - }; - }; - - internal-codec-playback-dai-link@0 { - link-name = "WCD"; - cpu { - sound-dai = <&lpass MI2S_PRIMARY>; - }; - codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; - }; - }; - - internal-codec-capture-dai-link@0 { - link-name = "WCD-Capture"; - cpu { - sound-dai = <&lpass MI2S_TERTIARY>; - }; - codec { - sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; - }; - }; - }; - - spmi@200f000 { - pm8916@0 { - gpios@c000 { - gpio-line-names = - "USR_LED_3_CTRL", - "USR_LED_4_CTRL", - "USB_HUB_RESET_N_PM", - "USB_SW_SEL_PM"; - }; - mpps@a000 { - gpio-line-names = - "VDD_PX_BIAS", - "WLAN_LED_CTRL", - "BT_LED_CTRL", - "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */ - }; - }; - }; - - wcnss@a21b000 { - status = "okay"; - }; - - tpiu@820000 { status = "okay"; }; - funnel@821000 { status = "okay"; }; - replicator@824000 { status = "okay"; }; - etf@825000 { status = "okay"; }; - etr@826000 { status = "okay"; }; - funnel@841000 { status = "okay"; }; - debug@850000 { status = "okay"; }; - debug@852000 { status = "okay"; }; - debug@854000 { status = "okay"; }; - debug@856000 { status = "okay"; }; - etm@85c000 { status = "okay"; }; - etm@85d000 { status = "okay"; }; - etm@85e000 { status = "okay"; }; - etm@85f000 { status = "okay"; }; - cti@810000 { status = "okay"; }; - cti@811000 { status = "okay"; }; - cti@858000 { status = "okay"; }; - cti@859000 { status = "okay"; }; - cti@85a000 { status = "okay"; }; - cti@85b000 { status = "okay"; }; - }; - usb2513 { compatible = "smsc,usb3503"; reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>; @@ -565,6 +155,102 @@ }; }; +&blsp_dma { + status = "okay"; +}; + +&blsp_i2c2 { + /* On Low speed expansion */ + status = "okay"; + label = "LS-I2C0"; +}; + +&blsp_i2c4 { + /* On High speed expansion */ + status = "okay"; + label = "HS-I2C2"; + + adv_bridge: bridge@39 { + status = "okay"; + + compatible = "adi,adv7533"; + reg = <0x39>; + + interrupt-parent = <&msmgpio>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + + adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + + pd-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp_i2c6 { + /* On Low speed expansion */ + status = "okay"; + label = "LS-I2C1"; +}; + +&blsp_spi3 { + /* On High speed expansion */ + status = "okay"; + label = "HS-SPI1"; +}; + +&blsp_spi5 { + /* On Low speed expansion */ + status = "okay"; + label = "LS-SPI0"; +}; + +&blsp1_uart1 { + status = "okay"; + label = "LS-UART0"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; +}; + +&blsp1_uart2 { + status = "okay"; + label = "LS-UART1"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; +}; + &camss { status = "okay"; ports { @@ -615,6 +301,98 @@ }; }; +&dsi0 { + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&adv7533_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi_phy0 { + vddio-supply = <&pm8916_l6>; +}; + +&lpass { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +}; + +&sound { + status = "okay"; + + pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; + pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; + pinctrl-names = "default", "sleep"; + qcom,model = "DB410c"; + qcom,audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + + external-dai-link@0 { + link-name = "ADV7533"; + cpu { + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; + + internal-codec-playback-dai-link@0 { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + }; + }; + + internal-codec-capture-dai-link@0 { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + }; + }; +}; + &spmi_bus { pm8916_0: pm8916@0 { pon@800 { @@ -629,6 +407,24 @@ }; }; +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; + adp-disable; + hnp-disable; + srp-disable; + + pinctrl-names = "default", "device"; + pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; + pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; +}; + +&usb_hs_phy { + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; + extcon = <&usb_id>; +}; + &wcd_codec { clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "mclk"; @@ -636,6 +432,28 @@ qcom,mbhc-vthreshold-high = <75 150 237 450 500>; }; +/* Enable CoreSight */ +&cti0 { status = "okay"; }; +&cti1 { status = "okay"; }; +&cti12 { status = "okay"; }; +&cti13 { status = "okay"; }; +&cti14 { status = "okay"; }; +&cti15 { status = "okay"; }; +&debug0 { status = "okay"; }; +&debug1 { status = "okay"; }; +&debug2 { status = "okay"; }; +&debug3 { status = "okay"; }; +&etf { status = "okay"; }; +&etm0 { status = "okay"; }; +&etm1 { status = "okay"; }; +&etm2 { status = "okay"; }; +&etm3 { status = "okay"; }; +&etr { status = "okay"; }; +&funnel0 { status = "okay"; }; +&funnel1 { status = "okay"; }; +&replicator { status = "okay"; }; +&tpiu { status = "okay"; }; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; @@ -773,7 +591,155 @@ drive-strength = <16>; }; +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from the schematic "DragonBoard410c" + * dated monday, august 31, 2015. Page 5 in particular. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + &msmgpio { + gpio-line-names = + "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ + "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ + "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */ + "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */ + "[UART1_TX]", /* GPIO_4, LSEC pin 11 */ + "[UART1_RX]", /* GPIO_5, LSEC pin 13 */ + "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */ + "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */ + "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */ + "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */ + "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */ + "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */ + "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */ + "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */ + "[I2C3_SDA]", /* HSEC pin 38 */ + "[I2C3_SCL]", /* HSEC pin 36 */ + "[SPI0_MOSI]", /* LSEC pin 14 */ + "[SPI0_MISO]", /* LSEC pin 10 */ + "[SPI0_CS_N]", /* LSEC pin 12 */ + "[SPI0_CLK]", /* LSEC pin 8 */ + "HDMI_HPD_N", /* GPIO 20 */ + "USR_LED_1_CTRL", + "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */ + "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */ + "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */ + "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */ + "[CSI0_MCLK]", /* HSEC pin 15 */ + "[CSI1_MCLK]", /* HSEC pin 17 */ + "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */ + "[I2C2_SDA]", /* HSEC pin 34 */ + "[I2C2_SCL]", /* HSEC pin 32 */ + "DSI2HDMI_INT_N", + "DSI_SW_SEL_APQ", + "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */ + "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */ + "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */ + "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */ + "FORCED_USB_BOOT", + "SD_CARD_DET_N", + "[WCSS_BT_SSBI]", + "[WCSS_WLAN_DATA_2]", /* GPIO 40 */ + "[WCSS_WLAN_DATA_1]", + "[WCSS_WLAN_DATA_0]", + "[WCSS_WLAN_SET]", + "[WCSS_WLAN_CLK]", + "[WCSS_FM_SSBI]", + "[WCSS_FM_SDI]", + "[WCSS_BT_DAT_CTL]", + "[WCSS_BT_DAT_STB]", + "NC", + "NC", /* GPIO 50 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO 60 */ + "NC", + "NC", + "[CDC_PDM0_CLK]", + "[CDC_PDM0_SYNC]", + "[CDC_PDM0_TX0]", + "[CDC_PDM0_RX0]", + "[CDC_PDM0_RX1]", + "[CDC_PDM0_RX2]", + "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */ + "NC", /* GPIO 70 */ + "NC", + "NC", + "NC", + "NC", /* GPIO 74 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "BOOT_CONFIG_0", /* GPIO 80 */ + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_3", + "NC", + "NC", + "BOOT_CONFIG_5", + "NC", + "NC", + "NC", + "NC", /* GPIO 90 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO 100 */ + "NC", + "NC", + "NC", + "SSBI_GPS", + "NC", + "NC", + "KEY_VOLP_N", + "NC", + "NC", + "[LS_EXP_MI2S_WS]", /* GPIO 110 */ + "NC", + "NC", + "[LS_EXP_MI2S_SCK]", + "[LS_EXP_MI2S_DATA0]", + "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */ + "NC", + "[DSI2HDMI_MI2S_WS]", + "[DSI2HDMI_MI2S_SCK]", + "[DSI2HDMI_MI2S_DATA0]", + "USR_LED_2_CTRL", /* GPIO 120 */ + "SB_HS_ID"; + msmgpio_leds: msmgpio-leds { pins = "gpio21", "gpio120"; function = "gpio"; @@ -833,6 +799,12 @@ }; &pm8916_gpios { + gpio-line-names = + "USR_LED_3_CTRL", + "USR_LED_4_CTRL", + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM"; + usb_hub_reset_pm: usb-hub-reset-pm { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; @@ -875,6 +847,12 @@ }; &pm8916_mpps { + gpio-line-names = + "VDD_PX_BIAS", + "WLAN_LED_CTRL", + "BT_LED_CTRL", + "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */ + pinctrl-names = "default"; pinctrl-0 = <&ls_exp_gpio_f>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 9f2c8e94fd26..68d89a8acbcf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -29,61 +29,6 @@ }; }; - soc { - sdhci@7824000 { - status = "okay"; - - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - }; - - sdhci@7864000 { - status = "okay"; - - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - - non-removable; - }; - - serial@78b0000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - - usb@78d9000 { - status = "okay"; - dr_mode = "peripheral"; - extcon = <&usb_vbus>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy { - extcon = <&usb_vbus>; - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; - }; - }; - }; - - wcnss@a21b000 { - status = "okay"; - }; - }; - // FIXME: Use extcon device provided by charger driver when available usb_vbus: usb-vbus { compatible = "linux,extcon-usb-gpio"; @@ -108,6 +53,42 @@ }; }; +&blsp1_uart2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + non-removable; +}; + &spmi_bus { pm8916@0 { pon@800 { @@ -121,6 +102,22 @@ }; }; +&usb { + status = "okay"; + dr_mode = "peripheral"; + extcon = <&usb_vbus>; + + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs_phy { + extcon = <&usb_vbus>; + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi index 0c6e81fb8c01..453e6acb5203 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi @@ -15,13 +15,11 @@ chosen { stdout-path = "serial0"; }; +}; - soc { - serial@78b0000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; +&blsp1_uart2 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index a0c00d9d62c4..89b1418eeeb4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -23,78 +23,6 @@ }; }; - soc { - sdhci@7824000 { - status = "okay"; - - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - }; - - sdhci@7864000 { - status = "okay"; - - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; - }; - - serial@78b0000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - - usb@78d9000 { - status = "okay"; - extcon = <&muic>, <&muic>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy { - extcon = <&muic>; - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; - }; - }; - }; - - mdss@1a00000 { - dsi@1a98000 { - #address-cells = <1>; - #size-cells = <0>; - - vdda-supply = <&pm8916_l2>; - vddio-supply = <&pm8916_l6>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mdss_default>; - pinctrl-1 = <&mdss_sleep>; - }; - - dsi-phy@1a98300 { - vddio-supply = <&pm8916_l6>; - }; - }; - - wcnss@a21b000 { - status = "okay"; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -186,6 +114,58 @@ }; }; +&blsp1_uart2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_default>; + pinctrl-1 = <&mdss_sleep>; +}; + +&dsi_phy0 { + vddio-supply = <&pm8916_l6>; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +}; + &spmi_bus { pm8916@0 { pon@800 { @@ -199,6 +179,21 @@ }; }; +&usb { + status = "okay"; + extcon = <&muic>, <&muic>; + + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs_phy { + extcon = <&muic>; + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; -- cgit v1.2.3 From 4eb7b63d4fbb4efa3d033ac3f3f7bef29c596f1b Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:54:02 +0200 Subject: arm64: dts: qcom: pm8916: Add resin node Right now we define the entire pm8916 resin node separately in the board-specific device tree part, including the interrupt that belongs to PM8916. As a feature of the PMIC it should be declared in pm8916.dtsi, disabled by default. Like all other optional components it can then by enabled and configured in the board-specific device tree part. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-7-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 19 +++++-------------- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 18 +++++------------- .../boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 18 +++++------------- arch/arm64/boot/dts/qcom/pm8916.dtsi | 8 ++++++++ 4 files changed, 23 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 5552773f633e..3e42ba9cca94 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -323,6 +323,11 @@ status = "okay"; }; +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + &pronto { status = "okay"; }; @@ -393,20 +398,6 @@ }; }; -&spmi_bus { - pm8916_0: pm8916@0 { - pon@800 { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; - &usb { status = "okay"; extcon = <&usb_id>, <&usb_id>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 68d89a8acbcf..90ce0f96eda4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -61,6 +61,11 @@ pinctrl-1 = <&blsp1_uart2_sleep>; }; +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + &pronto { status = "okay"; }; @@ -89,19 +94,6 @@ non-removable; }; -&spmi_bus { - pm8916@0 { - pon@800 { - volume-down { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; - &usb { status = "okay"; dr_mode = "peripheral"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 89b1418eeeb4..c6eb0b0cd849 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -138,6 +138,11 @@ vddio-supply = <&pm8916_l6>; }; +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + &pronto { status = "okay"; }; @@ -166,19 +171,6 @@ cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; }; -&spmi_bus { - pm8916@0 { - pon@800 { - volume-down { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; - &usb { status = "okay"; extcon = <&muic>, <&muic>; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 0bcdf0471107..c3f62090aff7 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -33,6 +33,14 @@ linux,code = ; }; + pm8916_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + watchdog { compatible = "qcom,pm8916-wdt"; interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; -- cgit v1.2.3 From bfe9d754257cdf026ecf7ccac7180e79b5714303 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:54:03 +0200 Subject: arm64: dts: qcom: msm8916: Move PM8916-specific parts to msm8916-pm8916.dtsi Device trees for newer SoCs avoid defining the regulator nodes directly in the SoC device tree (here: msm8916.dtsi). The reason for this is that theoretically it is possible to combine the SoC with a different PMIC, or to use all the regulators in a board-specific way. Therefore let's remove those from the SoC include (msm8916.dtsi). In practice, pretty much all MSM8916 boards were combined with PM8916, and use the regulators in similar ways. After looking at many different MSM8916 boards (mostly smartphones and tablets), I haven't seen a single device that isn't using the same regulators for components integrated into the SoC. If all boards end up defining all regulators and supplies in the same way then it is useful to have an include for that, so we can avoid duplicating it everywhere. If there is really a super special board that does it differently it could just override some properties or avoid using the include altogether. This patch moves the regulator and common supply definitions to a new include called "msm8916-pm8916.dtsi". This is also going to be useful when introducing CPR (Core Power Reduction) later because we can configure the CPU regulator (pm8916_spmi_s2) for all devices in this common include. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-8-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 3 +- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 3 +- arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 3 +- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 55 ++++++++++++++++++++++ .../dts/qcom/msm8916-samsung-a2015-common.dtsi | 3 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 40 ---------------- 6 files changed, 59 insertions(+), 48 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 3e42ba9cca94..267b61755e1a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -3,8 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ -#include "msm8916.dtsi" -#include "pm8916.dtsi" +#include "msm8916-pm8916.dtsi" #include #include #include diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 90ce0f96eda4..0b72da1bb6ca 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -2,8 +2,7 @@ /dts-v1/; -#include "msm8916.dtsi" -#include "pm8916.dtsi" +#include "msm8916-pm8916.dtsi" #include #include diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi index 453e6acb5203..9c4926326f21 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi @@ -3,8 +3,7 @@ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. */ -#include "msm8916.dtsi" -#include "pm8916.dtsi" +#include "msm8916-pm8916.dtsi" / { aliases { diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi new file mode 100644 index 000000000000..d416fe354f82 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916.dtsi" +#include "pm8916.dtsi" + +&camss { + vdda-supply = <&pm8916_l2>; +}; + +&mpss { + cx-supply = <&pm8916_s1>; + mx-supply = <&pm8916_l3>; + pll-supply = <&pm8916_l7>; +}; + +&pronto { + vddmx-supply = <&pm8916_l3>; + vddpx-supply = <&pm8916_l7>; + + iris { + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; + }; +}; + +&rpm_requests { + smd_rpm_regulators: pm8916-regulators { + compatible = "qcom,rpm-pm8916-regulators"; + + pm8916_s1: s1 {}; + pm8916_s3: s3 {}; + pm8916_s4: s4 {}; + + pm8916_l1: l1 {}; + pm8916_l2: l2 {}; + pm8916_l3: l3 {}; + pm8916_l4: l4 {}; + pm8916_l5: l5 {}; + pm8916_l6: l6 {}; + pm8916_l7: l7 {}; + pm8916_l8: l8 {}; + pm8916_l9: l9 {}; + pm8916_l10: l10 {}; + pm8916_l11: l11 {}; + pm8916_l12: l12 {}; + pm8916_l13: l13 {}; + pm8916_l14: l14 {}; + pm8916_l15: l15 {}; + pm8916_l16: l16 {}; + pm8916_l17: l17 {}; + pm8916_l18: l18 {}; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index c6eb0b0cd849..64e9c73953bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -#include "msm8916.dtsi" -#include "pm8916.dtsi" +#include "msm8916-pm8916.dtsi" #include #include #include diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index acbaed23bbdd..141348a92788 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1178,10 +1178,6 @@ resets = <&scm 0>; reset-names = "mss_restart"; - cx-supply = <&pm8916_s1>; - mx-supply = <&pm8916_l3>; - pll-supply = <&pm8916_l7>; - qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; status = "disabled"; @@ -1233,9 +1229,6 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - vddmx-supply = <&pm8916_l3>; - vddpx-supply = <&pm8916_l7>; - qcom,state = <&wcnss_smp2p_out 0>; qcom,state-names = "stop"; @@ -1249,11 +1242,6 @@ clocks = <&rpmcc RPM_SMD_RF_CLK2>; clock-names = "xo"; - - vddxo-supply = <&pm8916_l7>; - vddrfa-supply = <&pm8916_s3>; - vddpa-supply = <&pm8916_l9>; - vdddig-supply = <&pm8916_l5>; }; smd-edge { @@ -1776,7 +1764,6 @@ "csi_vfe0", "vfe_ahb", "vfe_axi"; - vdda-supply = <&pm8916_l2>; iommus = <&apps_iommu 3>; status = "disabled"; ports { @@ -1829,33 +1816,6 @@ compatible = "qcom,rpmcc-msm8916"; #clock-cells = <1>; }; - - smd_rpm_regulators: pm8916-regulators { - compatible = "qcom,rpm-pm8916-regulators"; - - pm8916_s1: s1 {}; - pm8916_s3: s3 {}; - pm8916_s4: s4 {}; - - pm8916_l1: l1 {}; - pm8916_l2: l2 {}; - pm8916_l3: l3 {}; - pm8916_l4: l4 {}; - pm8916_l5: l5 {}; - pm8916_l6: l6 {}; - pm8916_l7: l7 {}; - pm8916_l8: l8 {}; - pm8916_l9: l9 {}; - pm8916_l10: l10 {}; - pm8916_l11: l11 {}; - pm8916_l12: l12 {}; - pm8916_l13: l13 {}; - pm8916_l14: l14 {}; - pm8916_l15: l15 {}; - pm8916_l16: l16 {}; - pm8916_l17: l17 {}; - pm8916_l18: l18 {}; - }; }; }; }; -- cgit v1.2.3 From cc99dd61b7f8e05cbccad4b231f347bd363d8985 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:54:04 +0200 Subject: arm64: dts: qcom: msm8916: Move more supplies to msm8916-pm8916.dtsi So far we had some supplies defined for all boards in msm8916.dtsi, while others were duplicated into every board-specific device tree. Now that we have msm8916-pm8916.dtsi as a common include for all standard MSM8916 devices using PM8916, move the remaining common supplies to msm8916-pm8916.dtsi to reduce duplication a bit. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-9-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 15 -------------- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 8 -------- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 24 ++++++++++++++++++++++ .../dts/qcom/msm8916-samsung-a2015-common.dtsi | 15 -------------- 4 files changed, 24 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 267b61755e1a..75d5667cda31 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -301,9 +301,6 @@ }; &dsi0 { - vdda-supply = <&pm8916_l2>; - vddio-supply = <&pm8916_l6>; - ports { port@1 { endpoint { @@ -314,10 +311,6 @@ }; }; -&dsi_phy0 { - vddio-supply = <&pm8916_l6>; -}; - &lpass { status = "okay"; }; @@ -334,9 +327,6 @@ &sdhc_1 { status = "okay"; - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -345,9 +335,6 @@ &sdhc_2 { status = "okay"; - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; @@ -410,8 +397,6 @@ }; &usb_hs_phy { - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; extcon = <&usb_id>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 0b72da1bb6ca..8a6a9cd4a3fe 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -72,9 +72,6 @@ &sdhc_1 { status = "okay"; - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -83,9 +80,6 @@ &sdhc_2 { status = "okay"; - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; @@ -105,8 +99,6 @@ &usb_hs_phy { extcon = <&usb_vbus>; - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; }; &smd_rpm_regulators { diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index d416fe354f82..cd626e7db599 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -7,6 +7,15 @@ vdda-supply = <&pm8916_l2>; }; +&dsi0 { + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; +}; + +&dsi_phy0 { + vddio-supply = <&pm8916_l6>; +}; + &mpss { cx-supply = <&pm8916_s1>; mx-supply = <&pm8916_l3>; @@ -25,6 +34,21 @@ }; }; +&sdhc_1 { + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; +}; + +&sdhc_2 { + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; +}; + +&usb_hs_phy { + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; +}; + &rpm_requests { smd_rpm_regulators: pm8916-regulators { compatible = "qcom,rpm-pm8916-regulators"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 64e9c73953bb..f1ddb23ac3c3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -125,18 +125,11 @@ #address-cells = <1>; #size-cells = <0>; - vdda-supply = <&pm8916_l2>; - vddio-supply = <&pm8916_l6>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&mdss_default>; pinctrl-1 = <&mdss_sleep>; }; -&dsi_phy0 { - vddio-supply = <&pm8916_l6>; -}; - &pm8916_resin { status = "okay"; linux,code = ; @@ -149,9 +142,6 @@ &sdhc_1 { status = "okay"; - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -160,9 +150,6 @@ &sdhc_2 { status = "okay"; - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; @@ -181,8 +168,6 @@ &usb_hs_phy { extcon = <&muic>; - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; }; &smd_rpm_regulators { -- cgit v1.2.3 From b0d330c29ef3c55a712da5d0eb37de2b107b324b Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:54:05 +0200 Subject: arm64: dts: qcom: msm8916: Set default pinctrl for blsp1_uart1/2 Right now some device nodes set default pinctrl within msm8916.dtsi (e.g. I2C, SPI), but for others it needs to be explicitly set in the board-specific device tree (e.g. UART). While it is theoretically possible that some super special board needs different pinctrl for these, in practice pretty much every board ends up using the common pinctrl definitions. Make this consistent by also defining the common pinctrl properties for blsp1_uart1 and blsp1_uart2 so we don't need to copy this for every board. If there is really such a super special board it could just override these properties with custom pinctrl or make minor modifications to the common pinctrl configurations provided by msm8916-pins.dtsi. Also move #address-cells/#size-cells for &dsi0 to msm8916.dtsi since this is specific to the DSI node, not the board. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-10-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 8 -------- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 4 ---- arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 3 --- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 7 ------- arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++++++++ 5 files changed, 9 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 75d5667cda31..d9513f779bce 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -235,19 +235,11 @@ &blsp1_uart1 { status = "okay"; label = "LS-UART0"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; }; &blsp1_uart2 { status = "okay"; label = "LS-UART1"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; }; &camss { diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 8a6a9cd4a3fe..dec5e3ba7df4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -54,10 +54,6 @@ &blsp1_uart2 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; }; &pm8916_resin { diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi index 9c4926326f21..1bd05046cdeb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi @@ -18,7 +18,4 @@ &blsp1_uart2 { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index f1ddb23ac3c3..eb667f4b0e05 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -115,16 +115,9 @@ &blsp1_uart2 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; }; &dsi0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&mdss_default>; pinctrl-1 = <&mdss_sleep>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 141348a92788..273faffab369 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -487,6 +487,9 @@ clock-names = "core", "iface"; dmas = <&blsp_dma 1>, <&blsp_dma 0>; dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; status = "disabled"; }; @@ -513,6 +516,9 @@ clock-names = "core", "iface"; dmas = <&blsp_dma 3>, <&blsp_dma 2>; dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; status = "disabled"; }; @@ -1113,6 +1119,9 @@ phys = <&dsi_phy0>; phy-names = "dsi-phy"; + #address-cells = <1>; + #size-cells = <0>; + ports { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From bfd5d21abcd5c7941ad79b594f5f42e27496eb28 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 20 Jul 2020 10:54:06 +0200 Subject: arm64: dts: qcom: msm8916: Move common USB properties to msm8916.dtsi Right now we define "hnp-disable", "srp-disable", "adp-disable" separately for every MSM8916 board that has USB working. They are needed for USB to work properly if CONFIG_USB_OTG_FSM is enabled. This is because the chipidea OTG FSM code waits for interrupts regarding the VBUS state (AVVIS). Those never happen on MSM8916 because VBUS is always connected to the PMIC instead of the USB controller. There was a patch [1] to work around this but ultimately it was decided that it's easier to disable the OTG FSM altogether using these properties. This works fine for most use cases, because the OTG FSM isn't needed for simple dual role host/gadget operation. Given that these properties are needed for every MSM8916 device, move them to msm8916.dtsi so we can avoid some more duplication. [1]: https://lore.kernel.org/lkml/20160707222114.1673-10-stephen.boyd@linaro.org/ Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200720085406.6716-11-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 3 --- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 4 ---- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 4 ---- arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 +++ 4 files changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index d9513f779bce..d9af1a3785d8 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -379,9 +379,6 @@ &usb { status = "okay"; extcon = <&usb_id>, <&usb_id>; - adp-disable; - hnp-disable; - srp-disable; pinctrl-names = "default", "device"; pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index dec5e3ba7df4..b9d3c5d98dd0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -87,10 +87,6 @@ status = "okay"; dr_mode = "peripheral"; extcon = <&usb_vbus>; - - hnp-disable; - srp-disable; - adp-disable; }; &usb_hs_phy { diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index eb667f4b0e05..2ba649bffd4e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -153,10 +153,6 @@ &usb { status = "okay"; extcon = <&muic>, <&muic>; - - hnp-disable; - srp-disable; - adp-disable; }; &usb_hs_phy { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 273faffab369..d6a5b60846d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -802,6 +802,9 @@ reset-names = "core"; phy_type = "ulpi"; dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; ahb-burst-config = <0>; phy-names = "usb-phy"; phys = <&usb_hs_phy>; -- cgit v1.2.3 From c3d91c82c21f7443c828248819593866a6b8becc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 19 Aug 2020 14:39:10 +0200 Subject: arm64: dts: renesas: Drop superfluous pin configuration containers As the pin configuration child nodes for EtherAVB on the Draak and Ebisu boards contain only a single configuration, there is no need to wrap them in additional grandchild containers. Hence remove the superfluous level. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200819123910.19606-1-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 6 ++---- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 7402cfa8d4e4..e0ccca2222d2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -520,10 +520,8 @@ &pfc { avb_pins: avb { - mux { - groups = "avb_link", "avb_mii"; - function = "avb"; - }; + groups = "avb_link", "avb_mii"; + function = "avb"; }; canfd0_pins: canfd0 { diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 79c73a99d2fe..8f471881b7a3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -393,10 +393,8 @@ &pfc { avb0_pins: avb { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_mii"; - function = "avb0"; - }; + groups = "avb0_link", "avb0_mdio", "avb0_mii"; + function = "avb0"; }; can0_pins: can0 { -- cgit v1.2.3 From a937909702e00d98eac5b91b31a7f2ae112f47bf Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 11 Sep 2020 09:09:29 +0100 Subject: ARM: dts: r8a7742: Add VSP support Add VSP support to R8A7742 (RZ/G1H) SoC dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200911080929.15058-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 170f159d6613..6a78c813057b 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -1686,6 +1686,42 @@ status = "disabled"; }; + vsp@fe920000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 130>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 130>; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7742"; reg = <0 0xfeb00000 0 0x70000>; -- cgit v1.2.3 From 9d8827b27b758ecb4fda3da812c77c316b3a5548 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 11 Sep 2020 09:36:15 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add can0 support to camera DB This patch enables CAN0 interface exposed through connector J4 on the camera DB. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200911083615.17377-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 1479ced50873..961c0f2eeefb 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -27,6 +27,12 @@ status = "disabled"; }; +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + ðer { pinctrl-0 = <ðer_pins>; pinctrl-names = "default"; @@ -49,6 +55,11 @@ }; &pfc { + can0_pins: can0 { + groups = "can0_data_d"; + function = "can0"; + }; + ether_pins: ether { groups = "eth_mdio", "eth_rmii"; function = "eth"; -- cgit v1.2.3 From 1ada85b6201dfaf0c5b40ceaa31789d8605b086f Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 11 Sep 2020 13:12:59 +0100 Subject: arm64: dts: renesas: r8a77990: Add DRIF support Add the DRIF controller nodes for the r8a77990 (a.k.a. R-Car E3). Please note that R-Car E3 has register BITCTR located at offset 0x80 (this register is not available on the r8a77960 and r8a77951, whose support has already been upstreamed), and even though it is not dealt with just yet within the driver, we have to keep that into account with our device tree nodes. Also, please note that while testing it has emerged that the HW User Manual has the wrong DMA details for DRIF2 and DRIF3 on E3, as they are only allowed SYS-DMAC0 rather than SYS-DMAC1 and SYS-DMAC2. An errata addressing this issue will be available soon. Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200911121259.5669-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 120 ++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 6bf2eb19c6a2..5eb4e116db09 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1288,6 +1288,126 @@ }; }; + drif00: rif@e6f40000 { + compatible = "renesas,r8a77990-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; + status = "disabled"; + }; + + drif01: rif@e6f50000 { + compatible = "renesas,r8a77990-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; + status = "disabled"; + }; + + drif10: rif@e6f60000 { + compatible = "renesas,r8a77990-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; + status = "disabled"; + }; + + drif11: rif@e6f70000 { + compatible = "renesas,r8a77990-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; + status = "disabled"; + }; + + drif20: rif@e6f80000 { + compatible = "renesas,r8a77990-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac0 0x28>; + dma-names = "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; + status = "disabled"; + }; + + drif21: rif@e6f90000 { + compatible = "renesas,r8a77990-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac0 0x2a>; + dma-names = "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; + status = "disabled"; + }; + + drif30: rif@e6fa0000 { + compatible = "renesas,r8a77990-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac0 0x2c>; + dma-names = "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; + status = "disabled"; + }; + + drif31: rif@e6fb0000 { + compatible = "renesas,r8a77990-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac0 0x2e>; + dma-names = "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required -- cgit v1.2.3 From 43bb8074000c9c597e13bbd35c56db7e25579f6f Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 15 Sep 2020 16:23:16 +0200 Subject: arm64: dts: qcom: msm8996: Add VFE1_GDSC power domain to camss node As the MSM8996 has two VFE IP-blocks, and each has a power domain, both of them have to be enabled. Previously only the power domain of VFE0 was enabled, but not the domain for VFE1. This patch adds the VFE1_GDSC power domain to the camss device tree node of the MSM8996 soc. Signed-off-by: Robert Foss Link: https://lore.kernel.org/r/20200915142316.147208-1-robert.foss@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 9951286db775..fd6ae5464dea 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1009,7 +1009,8 @@ "ispif", "vfe0", "vfe1"; - power-domains = <&mmcc VFE0_GDSC>; + power-domains = <&mmcc VFE0_GDSC>, + <&mmcc VFE1_GDSC>; clocks = <&mmcc CAMSS_TOP_AHB_CLK>, <&mmcc CAMSS_ISPIF_AHB_CLK>, <&mmcc CAMSS_CSI0PHYTIMER_CLK>, -- cgit v1.2.3 From 01e869cc0db9ab0d87818cb926ee97629e2a3f98 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Sep 2020 15:02:03 +0300 Subject: arm64: dts: sm8250: Add OPP table for all qup devices qup has a requirement to vote on the performance state of the CX domain in sm8250 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Acked-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20200915120203.290295-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 69 ++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c989bc1370ab..6cd45a667ba9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -411,6 +411,25 @@ #mbox-cells = <2>; }; + qup_opp_table: qup-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -445,6 +464,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -471,6 +492,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -497,6 +520,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -523,6 +548,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -534,6 +561,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart17_default>; interrupts = ; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -560,6 +589,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -571,6 +602,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart18_default>; interrupts = ; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -597,6 +630,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; @@ -635,6 +670,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -661,6 +698,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -687,6 +726,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -698,6 +739,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = ; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -724,6 +767,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -750,6 +795,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -776,6 +823,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -802,6 +851,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -813,6 +864,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -839,6 +892,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; @@ -877,6 +932,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -903,6 +960,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -929,6 +988,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -955,6 +1016,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -981,6 +1044,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -992,6 +1057,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart12_default>; interrupts = ; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1018,6 +1085,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; -- cgit v1.2.3 From b2106c670e8644335eb528b5f5e298e5be8d28a1 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:08 +0200 Subject: arm64: dts: qcom: msm8916: Configure DSI port with labels &dsi0 -> ports -> port@1 -> endpoint already has the "dsi0_out" label, so we can use it for configuring instead of replicating the entire node hierarchy. Looks like I missed that when converting the boards. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 12 +++--------- arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 12 ++++-------- 2 files changed, 7 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index d9af1a3785d8..3c7f97539390 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -292,15 +292,9 @@ }; }; -&dsi0 { - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7533_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; }; &lpass { diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 410c7d199f96..086f07ead5cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -44,15 +44,11 @@ }; }; }; +}; - ports { - port@1 { - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1>; - }; - }; - }; +&dsi0_out { + data-lanes = <0 1>; + remote-endpoint = <&panel_in>; }; &msmgpio { -- cgit v1.2.3 From e6859ae8603c5946b8f3ecbd9b4f02b72955b9d0 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:09 +0200 Subject: arm64: dts: qcom: msm8916: Remove one more thermal trip point unit name Commit fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points") removed the unit names for most of the thermal trip points defined in msm8916.dtsi, but missed to update the one for cpu0_1-thermal. So why wasn't this spotted by "make dtbs_check"? Apparently, the name of the thermal zone is already invalid: thermal-zones.yaml specifies a regex of ^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$, so it is not allowed to contain underscores. Therefore the thermal zone was never verified using the DTB schema. After replacing the underscore in the thermal zone name, the warning shows up: apq8016-sbc.dt.yaml: thermal-zones: cpu0-1-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' Fix up the thermal zone names and remove the unit name for the trip point. Cc: Amit Kucheria Fixes: fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d6a5b60846d9..d84118fb4403 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -229,14 +229,14 @@ }; thermal-zones { - cpu0_1-thermal { + cpu0-1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 5>; trips { - cpu0_1_alert0: trip-point@0 { + cpu0_1_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -259,7 +259,7 @@ }; }; - cpu2_3-thermal { + cpu2-3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; -- cgit v1.2.3 From c2f0cbb57dbac6da3d38b47b5b96de0fe4e23884 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:10 +0200 Subject: arm64: dts: qcom: pm8916: Remove invalid reg size from wcd_codec Tha parent node of "wcd_codec" specifies #address-cells = <1> and #size-cells = <0>, which means that each resource should be described by one cell for the address and size omitted. However, wcd_codec currently lists 0x200 as second cell (probably the size of the resource). When parsing this would be treated like another memory resource - which is entirely wrong. To quote the device tree specification [1]: "If the parent node specifies a value of 0 for #size-cells, the length field in the value of reg shall be omitted." [1]: https://www.devicetree.org/specifications/ Fixes: 5582fcb3829f ("arm64: dts: apq8016-sbc: add analog audio support with multicodec") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index c3f62090aff7..636ef9db9a14 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -127,7 +127,7 @@ wcd_codec: codec@f000 { compatible = "qcom,pm8916-wcd-analog-codec"; - reg = <0xf000 0x200>; + reg = <0xf000>; reg-names = "pmic-codec-core"; clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "mclk"; -- cgit v1.2.3 From 027cca9eb5b450c3f6bb916ba999144c2ec23cb7 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:11 +0200 Subject: arm64: dts: qcom: msm8916: Fix MDP/DSI interrupts The mdss node sets #interrupt-cells = <1>, so its interrupts should be referenced using a single cell (in this case: only the interrupt number). However, right now the mdp/dsi node both have two interrupt cells set, e.g. interrupts = <4 0>. The 0 is probably meant to say IRQ_TYPE_NONE (= 0), but with #interrupt-cells = <1> this is actually interpreted as a second interrupt line. Remove the IRQ flags from both interrupts to fix this. Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d84118fb4403..1f9a24a2464e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1068,7 +1068,7 @@ reg-names = "mdp_phys"; interrupt-parent = <&mdss>; - interrupts = <0 0>; + interrupts = <0>; clocks = <&gcc GCC_MDSS_AHB_CLK>, <&gcc GCC_MDSS_AXI_CLK>, @@ -1100,7 +1100,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 0>; + interrupts = <4>; assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; -- cgit v1.2.3 From dd5f6c73240756abb0dd457d7c885564167e9f0a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:12 +0200 Subject: arm64: dts: qcom: msm8916: Use IRQ defines, add IRQ types dt-bindings/interrupt-controller/arm-gic.h has a GIC_SPI define that allows specifying interrupts more clearly, but right now only some device nodes in msm8916.dtsi make use of it. Convert all others to use it. The same applies to the IRQ_TYPE_* defines in dt-bindings/interrupt-controller/irq.h. Some interrupts were defined with raw numbers, or even with IRQ_TYPE_NONE (0). Convert all these to use appropriate IRQ types. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-6-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 38 ++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 1f9a24a2464e..003451ccf3ee 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -737,7 +737,7 @@ "mi2s-bit-clk3"; #sound-dai-cells = <1>; - interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; interrupt-names = "lpass-irq-lpaif"; reg = <0x07708000 0x10000>; reg-names = "lpass-lpaif"; @@ -760,7 +760,8 @@ reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, @@ -777,7 +778,8 @@ reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>, @@ -1053,7 +1055,7 @@ "bus", "vsync"; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -1170,11 +1172,11 @@ reg-names = "qdsp6", "rmb"; - interrupts-extended = <&intc 0 24 1>, - <&hexagon_smp2p_in 0 0>, - <&hexagon_smp2p_in 1 0>, - <&hexagon_smp2p_in 2 0>, - <&hexagon_smp2p_in 3 0>; + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; @@ -1203,7 +1205,7 @@ }; smd-edge { - interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; + interrupts = ; qcom,smd-edge = <0>; qcom,ipc = <&apcs 8 12>; @@ -1234,7 +1236,7 @@ memory-region = <&wcnss_mem>; - interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -1257,7 +1259,7 @@ }; smd-edge { - interrupts = <0 142 1>; + interrupts = ; qcom,ipc = <&apcs 8 17>; qcom,smd-edge = <6>; @@ -1278,8 +1280,8 @@ wifi { compatible = "qcom,wcnss-wlan"; - interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>, - <0 146 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "tx", "rx"; qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; @@ -1836,7 +1838,7 @@ compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; - interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; + interrupts = ; qcom,ipc = <&apcs 8 14>; @@ -1861,7 +1863,7 @@ compatible = "qcom,smp2p"; qcom,smem = <451>, <431>; - interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; + interrupts = ; qcom,ipc = <&apcs 8 18>; @@ -1899,7 +1901,7 @@ hexagon_smsm: hexagon@1 { reg = <1>; - interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; @@ -1907,7 +1909,7 @@ wcnss_smsm: wcnss@6 { reg = <6>; - interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; -- cgit v1.2.3 From 5342f1df8f50df3cec6e015beefc4eca79eb858d Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:13 +0200 Subject: arm64: dts: qcom: msm8916: Drop qcom,tcsr-mutex syscon The hwlock device node does not (directly) use memory resources of the SoC, so we should move it outside the "soc" node. However, as of commit 7a1e6fb1c606 ("hwspinlock: qcom: Allow mmio usage in addition to syscon") we can now assign the memory region directly to the hwlock device node. This works because the register space used by it is actually separate and not used by any other components. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-7-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 003451ccf3ee..10e177988555 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -458,9 +458,10 @@ reg = <0x1800000 0x80000>; }; - tcsr_mutex_regs: syscon@1905000 { - compatible = "syscon"; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; reg = <0x1905000 0x20000>; + #hwlock-cells = <1>; }; tcsr: syscon@1937000 { @@ -468,12 +469,6 @@ reg = <0x1937000 0x30000>; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - rpm_msg_ram: memory@60000 { compatible = "qcom,rpm-msg-ram"; reg = <0x60000 0x8000>; -- cgit v1.2.3 From 1b1bd497000ef58c83b9430f8e46758febb5416f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:14 +0200 Subject: arm64: dts: qcom: msm8916: Minor style fixes Fix usages of spaces for indentation, break a long line and remove duplicate new lines. Add some spaces where appropriate. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-8-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 10e177988555..eca3cd94d3d5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -151,8 +151,8 @@ }; L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; + compatible = "cache"; + cache-level = <2>; }; idle-states { @@ -225,7 +225,7 @@ pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; thermal-zones { @@ -393,7 +393,9 @@ firmware { scm: scm { compatible = "qcom,scm"; - clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; clock-names = "core", "bus", "iface"; #reset-cells = <1>; @@ -741,14 +743,14 @@ #size-cells = <0>; }; - lpass_codec: codec{ + lpass_codec: codec@771c000 { compatible = "qcom,msm8916-wcd-digital-codec"; reg = <0x0771c000 0x400>; clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "ahbix-clk", "mclk"; #sound-dai-cells = <1>; - }; + }; sdhc_1: sdhci@7824000 { compatible = "qcom,sdhci-msm-v4"; @@ -1159,7 +1161,6 @@ }; }; - mpss: hexagon@4080000 { compatible = "qcom,q6v5-pil"; reg = <0x04080000 0x100>, @@ -1216,7 +1217,7 @@ #address-cells = <1>; #size-cells = <0>; - cb@1{ + cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; }; @@ -1474,7 +1475,7 @@ }; debug0: debug@850000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; + compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x850000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1483,7 +1484,7 @@ }; debug1: debug@852000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; + compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x852000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1492,7 +1493,7 @@ }; debug2: debug@854000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; + compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x854000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1501,7 +1502,7 @@ }; debug3: debug@856000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; + compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x856000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1679,7 +1680,6 @@ status = "disabled"; }; - venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>; -- cgit v1.2.3 From 60a05ed059a0993cd5501e9e7e07aacb135a35e4 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:15 +0200 Subject: arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS Over the time, the SCM and MSS driver were refactored to use SoC-specific compatibles. While the generic compatibles still work correctly, add the MSM8916-specific compatibles so they are actually used somewhere. For SCM this will ensure that we actually manage to obtain all three of the specified clocks, since those are required on MSM8916. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-9-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index eca3cd94d3d5..b2669643a12d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -392,7 +392,7 @@ firmware { scm: scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-msm8916", "qcom,scm"; clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; @@ -1162,7 +1162,7 @@ }; mpss: hexagon@4080000 { - compatible = "qcom,q6v5-pil"; + compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; reg = <0x04080000 0x100>, <0x04020000 0x040>; -- cgit v1.2.3 From 6300095b0bc7d70d5d2133769355442688c44c6f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:16 +0200 Subject: arm64: dts: qcom: msm8916: Use more generic node names Now that all MSM8916 boards are referencing nodes by label instead of name, we can easily make some more nodes use more generic names (as recommended in the device tree specification or the binding documentation). Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-10-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8916-samsung-a2015-common.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 +++++----- arch/arm64/boot/dts/qcom/pm8916.dtsi | 22 +++++++++++----------- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 2ba649bffd4e..b18d21e42f59 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -81,7 +81,7 @@ #address-cells = <1>; #size-cells = <0>; - muic: sm5502@25 { + muic: extcon@25 { compatible = "siliconmitus,sm5502-muic"; reg = <0x25>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index b2669643a12d..4444d068343c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -714,7 +714,7 @@ reg-names = "mic-iomux", "spkr-iomux"; }; - lpass: lpass@7708000 { + lpass: audio-controller@7708000 { status = "disabled"; compatible = "qcom,lpass-cpu-apq8016"; clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, @@ -743,7 +743,7 @@ #size-cells = <0>; }; - lpass_codec: codec@771c000 { + lpass_codec: audio-codec@771c000 { compatible = "qcom,msm8916-wcd-digital-codec"; reg = <0x0771c000 0x400>; clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, @@ -1161,7 +1161,7 @@ }; }; - mpss: hexagon@4080000 { + mpss: remoteproc@4080000 { compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; reg = <0x04080000 0x100>, <0x04020000 0x040>; @@ -1225,7 +1225,7 @@ }; }; - pronto: wcnss@a21b000 { + pronto: remoteproc@a21b000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; @@ -1821,7 +1821,7 @@ compatible = "qcom,rpm-msm8916"; qcom,smd-channels = "rpm_requests"; - rpmcc: qcom,rpmcc { + rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8916"; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 636ef9db9a14..c7b22ac81452 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -6,7 +6,7 @@ &spmi_bus { - pm8916_0: pm8916@0 { + pm8916_0: pmic@0 { compatible = "qcom,pm8916", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <1>; @@ -79,7 +79,7 @@ #thermal-sensor-cells = <0>; }; - pm8916_vadc: vadc@3100 { + pm8916_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; @@ -87,33 +87,33 @@ #size-cells = <0>; #io-channel-cells = <1>; - usb_in { + adc-chan@0 { reg = ; qcom,pre-scaling = <1 10>; }; - vph_pwr { + adc-chan@7 { reg = ; qcom,pre-scaling = <1 3>; }; - die_temp { + adc-chan@8 { reg = ; }; - ref_625mv { + adc-chan@9 { reg = ; }; - ref_1250v { + adc-chan@a { reg = ; }; - ref_gnd { + adc-chan@e { reg = ; }; - ref_vdd { + adc-chan@f { reg = ; }; }; }; - pm8916_1: pm8916@1 { + pm8916_1: pmic@1 { compatible = "qcom,pm8916", "qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; #address-cells = <1>; @@ -125,7 +125,7 @@ status = "disabled"; }; - wcd_codec: codec@f000 { + wcd_codec: audio-codec@f000 { compatible = "qcom,pm8916-wcd-analog-codec"; reg = <0xf000>; reg-names = "pmic-codec-core"; -- cgit v1.2.3 From cdbb391676fa07606994243cc670dd496a9d37db Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:17 +0200 Subject: arm64: dts: qcom: msm8916: Rename "x-smp2p" to "smp2p-x" This allows grouping them together when sorting nodes alphabetically. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-11-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4444d068343c..47f01e206255 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1829,7 +1829,7 @@ }; }; - hexagon-smp2p { + smp2p-hexagon { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -1854,7 +1854,7 @@ }; }; - wcnss-smp2p { + smp2p-wcnss { compatible = "qcom,smp2p"; qcom,smem = <451>, <431>; -- cgit v1.2.3 From 2e04aa29ac8782143779e16dac33a691d2f7df67 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:18 +0200 Subject: arm64: dts: qcom: msm8916: Pad addresses Just like in commit 86f6d6225e5e ("arm64: dts: qcom: msm8996: Pad addresses"), pad all addresses to 8 digits to make it easier to see the correct order of the nodes. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-12-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 138 +++++++++++++++++----------------- 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 47f01e206255..9af528b9979b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -420,7 +420,7 @@ restart@4ab000 { compatible = "qcom,pshold"; - reg = <0x4ab000 0x4>; + reg = <0x004ab000 0x4>; }; pcnoc: interconnect@500000 { @@ -443,7 +443,7 @@ msmgpio: pinctrl@1000000 { compatible = "qcom,msm8916-pinctrl"; - reg = <0x1000000 0x300000>; + reg = <0x01000000 0x300000>; interrupts = ; gpio-controller; gpio-ranges = <&msmgpio 0 0 122>; @@ -457,28 +457,28 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - reg = <0x1800000 0x80000>; + reg = <0x01800000 0x80000>; }; tcsr_mutex: hwlock@1905000 { compatible = "qcom,tcsr-mutex"; - reg = <0x1905000 0x20000>; + reg = <0x01905000 0x20000>; #hwlock-cells = <1>; }; tcsr: syscon@1937000 { compatible = "qcom,tcsr-msm8916", "syscon"; - reg = <0x1937000 0x30000>; + reg = <0x01937000 0x30000>; }; rpm_msg_ram: memory@60000 { compatible = "qcom,rpm-msg-ram"; - reg = <0x60000 0x8000>; + reg = <0x00060000 0x8000>; }; blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; + reg = <0x078af000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -492,13 +492,13 @@ a53pll: clock@b016000 { compatible = "qcom,msm8916-a53pll"; - reg = <0xb016000 0x40>; + reg = <0x0b016000 0x40>; #clock-cells = <0>; }; apcs: mailbox@b011000 { compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; - reg = <0xb011000 0x1000>; + reg = <0x0b011000 0x1000>; #mbox-cells = <1>; clocks = <&a53pll>, <&gcc GPLL0_VOTE>; clock-names = "pll", "aux"; @@ -507,7 +507,7 @@ blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b0000 0x200>; + reg = <0x078b0000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -788,8 +788,8 @@ usb: usb@78d9000 { compatible = "qcom,ci-hdrc"; - reg = <0x78d9000 0x200>, - <0x78d9200 0x200>; + reg = <0x078d9000 0x200>, + <0x078d9200 0x200>; interrupts = , ; clocks = <&gcc GCC_USB_HS_AHB_CLK>, @@ -837,67 +837,67 @@ #size-cells = <1>; ranges; compatible = "arm,armv7-timer-mem"; - reg = <0xb020000 0x1000>; + reg = <0x0b020000 0x1000>; clock-frequency = <19200000>; frame@b021000 { frame-number = <0>; interrupts = , ; - reg = <0xb021000 0x1000>, - <0xb022000 0x1000>; + reg = <0x0b021000 0x1000>, + <0x0b022000 0x1000>; }; frame@b023000 { frame-number = <1>; interrupts = ; - reg = <0xb023000 0x1000>; + reg = <0x0b023000 0x1000>; status = "disabled"; }; frame@b024000 { frame-number = <2>; interrupts = ; - reg = <0xb024000 0x1000>; + reg = <0x0b024000 0x1000>; status = "disabled"; }; frame@b025000 { frame-number = <3>; interrupts = ; - reg = <0xb025000 0x1000>; + reg = <0x0b025000 0x1000>; status = "disabled"; }; frame@b026000 { frame-number = <4>; interrupts = ; - reg = <0xb026000 0x1000>; + reg = <0x0b026000 0x1000>; status = "disabled"; }; frame@b027000 { frame-number = <5>; interrupts = ; - reg = <0xb027000 0x1000>; + reg = <0x0b027000 0x1000>; status = "disabled"; }; frame@b028000 { frame-number = <6>; interrupts = ; - reg = <0xb028000 0x1000>; + reg = <0x0b028000 0x1000>; status = "disabled"; }; }; spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x200f000 0x001000>, - <0x2400000 0x400000>, - <0x2c00000 0x400000>, - <0x3800000 0x200000>, - <0x200a000 0x002100>; + reg = <0x0200f000 0x001000>, + <0x02400000 0x400000>, + <0x02c00000 0x400000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; @@ -918,7 +918,7 @@ qfprom: qfprom@5c000 { compatible = "qcom,qfprom"; - reg = <0x5c000 0x1000>; + reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; tsens_caldata: caldata@d0 { @@ -931,8 +931,8 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; - reg = <0x4a9000 0x1000>, /* TM */ - <0x4a8000 0x1000>; /* SROT */ + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; #qcom,sensors = <5>; @@ -946,8 +946,8 @@ #size-cells = <1>; #iommu-cells = <1>; compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1e20000 0x40000>; - reg = <0x1ef0000 0x3000>; + ranges = <0 0x01e20000 0x40000>; + reg = <0x01ef0000 0x3000>; clocks = <&gcc GCC_SMMU_CFG_CLK>, <&gcc GCC_APSS_TCU_CLK>; clock-names = "iface", "bus"; @@ -980,7 +980,7 @@ #size-cells = <1>; #iommu-cells = <1>; compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1f08000 0x10000>; + ranges = <0 0x01f08000 0x10000>; clocks = <&gcc GCC_SMMU_CFG_CLK>, <&gcc GCC_GFX_TCU_CLK>; clock-names = "iface", "bus"; @@ -1039,8 +1039,8 @@ mdss: mdss@1a00000 { compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, - <0x1ac8000 0x3000>; + reg = <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; reg-names = "mdss_phys", "vbif_phys"; power-domains = <&gcc MDSS_GDSC>; @@ -1063,7 +1063,7 @@ mdp: mdp@1a01000 { compatible = "qcom,mdp5"; - reg = <0x1a01000 0x89000>; + reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; interrupt-parent = <&mdss>; @@ -1095,7 +1095,7 @@ dsi0: dsi@1a98000 { compatible = "qcom,mdss-dsi-ctrl"; - reg = <0x1a98000 0x25c>; + reg = <0x01a98000 0x25c>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -1145,9 +1145,9 @@ dsi_phy0: dsi-phy@1a98300 { compatible = "qcom,dsi-phy-28nm-lp"; - reg = <0x1a98300 0xd4>, - <0x1a98500 0x280>, - <0x1a98780 0x30>; + reg = <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; @@ -1289,7 +1289,7 @@ tpiu: tpiu@820000 { compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x820000 0x1000>; + reg = <0x00820000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1307,7 +1307,7 @@ funnel0: funnel@821000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x821000 0x1000>; + reg = <0x00821000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1348,7 +1348,7 @@ replicator: replicator@824000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x824000 0x1000>; + reg = <0x00824000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1384,7 +1384,7 @@ etf: etf@825000 { compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x825000 0x1000>; + reg = <0x00825000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1410,7 +1410,7 @@ etr: etr@826000 { compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x826000 0x1000>; + reg = <0x00826000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1428,7 +1428,7 @@ funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x841000 0x1000>; + reg = <0x00841000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1476,7 +1476,7 @@ debug0: debug@850000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x850000 0x1000>; + reg = <0x00850000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU0>; @@ -1485,7 +1485,7 @@ debug1: debug@852000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x852000 0x1000>; + reg = <0x00852000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU1>; @@ -1494,7 +1494,7 @@ debug2: debug@854000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x854000 0x1000>; + reg = <0x00854000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU2>; @@ -1503,7 +1503,7 @@ debug3: debug@856000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x856000 0x1000>; + reg = <0x00856000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU3>; @@ -1512,7 +1512,7 @@ etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x85c000 0x1000>; + reg = <0x0085c000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1533,7 +1533,7 @@ etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x85d000 0x1000>; + reg = <0x0085d000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1554,7 +1554,7 @@ etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x85e000 0x1000>; + reg = <0x0085e000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1575,7 +1575,7 @@ etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x85f000 0x1000>; + reg = <0x0085f000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; @@ -1598,7 +1598,7 @@ /* CTI 0 - TMC connections */ cti0: cti@810000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x810000 0x1000>; + reg = <0x00810000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1609,7 +1609,7 @@ /* CTI 1 - TPIU connections */ cti1: cti@811000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x811000 0x1000>; + reg = <0x00811000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1624,7 +1624,7 @@ cti12: cti@858000 { compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", "arm,primecell"; - reg = <0x858000 0x1000>; + reg = <0x00858000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1639,7 +1639,7 @@ cti13: cti@859000 { compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", "arm,primecell"; - reg = <0x859000 0x1000>; + reg = <0x00859000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1654,7 +1654,7 @@ cti14: cti@85a000 { compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", "arm,primecell"; - reg = <0x85a000 0x1000>; + reg = <0x0085a000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1669,7 +1669,7 @@ cti15: cti@85b000 { compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", "arm,primecell"; - reg = <0x85b000 0x1000>; + reg = <0x0085b000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1704,15 +1704,15 @@ camss: camss@1b00000 { compatible = "qcom,msm8916-camss"; - reg = <0x1b0ac00 0x200>, - <0x1b00030 0x4>, - <0x1b0b000 0x200>, - <0x1b00038 0x4>, - <0x1b08000 0x100>, - <0x1b08400 0x100>, - <0x1b0a000 0x500>, - <0x1b00020 0x10>, - <0x1b10000 0x1000>; + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>; reg-names = "csiphy0", "csiphy0_clk_mux", "csiphy1", @@ -1785,7 +1785,7 @@ compatible = "qcom,msm8916-cci"; #address-cells = <1>; #size-cells = <0>; - reg = <0x1b0c000 0x1000>; + reg = <0x01b0c000 0x1000>; interrupts = ; clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_AHB_CLK>, -- cgit v1.2.3 From 327c0f5f25100fbd04181b0196b89fff785bf1c9 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:19 +0200 Subject: arm64: dts: qcom: msm8916: Sort nodes Just like in commit 50aa72ccb30b ("arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsi"), sort all the nodes by unit address, then alphabetically by their name. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-13-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2540 ++++++++++++++++----------------- 1 file changed, 1270 insertions(+), 1270 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 9af528b9979b..aaa21899f1a6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -4,11 +4,11 @@ */ #include +#include +#include #include #include -#include #include -#include #include / { @@ -94,6 +94,20 @@ }; }; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -189,6 +203,42 @@ }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + }; + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8916", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -223,183 +273,114 @@ }; }; - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - thermal-zones { - cpu0-1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + smd { + compatible = "qcom,smd"; - thermal-sensors = <&tsens 5>; + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; - trips { - cpu0_1_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; - cooling-maps { - map0 { - trip = <&cpu0_1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8916"; + #clock-cells = <1>; }; }; }; + }; - cpu2-3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; + smem { + compatible = "qcom,smem"; - trips { - cpu2_3_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; - cooling-maps { - map0 { - trip = <&cpu2_3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; + hwlocks = <&tcsr_mutex 3>; + }; - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + smp2p-hexagon { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; - thermal-sensors = <&tsens 2>; + interrupts = ; - trips { - gpu_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; + qcom,ipc = <&apcs 8 14>; - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; - thermal-sensors = <&tsens 1>; + hexagon_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; - trips { - cam_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "hot"; - }; - }; + #qcom,smem-state-cells = <1>; }; - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 0>; + hexagon_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; - trips { - modem_alert0: trip-point0 { - temperature = <85000>; - hysteresis = <2000>; - type = "hot"; - }; - }; + interrupt-controller; + #interrupt-cells = <2>; }; - }; - cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2"; - opp-shared; + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - }; - opp-998400000 { - opp-hz = /bits/ 64 <998400000>; - }; - }; + interrupts = ; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; + qcom,ipc = <&apcs 8 18>; - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; }; - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; }; }; - smem { - compatible = "qcom,smem"; + smsm { + compatible = "qcom,smsm"; - memory-region = <&smem_mem>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; + #address-cells = <1>; + #size-cells = <0>; - hwlocks = <&tcsr_mutex 3>; - }; + qcom,ipc-1 = <&apcs 8 13>; + qcom,ipc-3 = <&apcs 8 19>; - firmware { - scm: scm { - compatible = "qcom,scm-msm8916", "qcom,scm"; - clocks = <&gcc GCC_CRYPTO_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "core", "bus", "iface"; - #reset-cells = <1>; + apps_smsm: apps@0 { + reg = <0>; - qcom,dload-mode = <&tcsr 0x6100>; + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; }; }; @@ -409,6 +390,36 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x004ab000 0x4>; + }; + + qfprom: qfprom@5c000 { + compatible = "qcom,qfprom"; + reg = <0x0005c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0xd0 0x8>; + }; + tsens_calsel: calsel@ec { + reg = <0xec 0x4>; + }; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + bimc: interconnect@400000 { compatible = "qcom,msm8916-bimc"; reg = <0x00400000 0x62000>; @@ -418,9 +429,16 @@ <&rpmcc RPM_SMD_BIMC_A_CLK>; }; - restart@4ab000 { - compatible = "qcom,pshold"; - reg = <0x004ab000 0x4>; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; + nvmem-cell-names = "calib", "calib_sel"; + #qcom,sensors = <5>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; }; pcnoc: interconnect@500000 { @@ -441,602 +459,429 @@ <&rpmcc RPM_SMD_SNOC_A_CLK>; }; - msmgpio: pinctrl@1000000 { - compatible = "qcom,msm8916-pinctrl"; - reg = <0x01000000 0x300000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 122>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti0: cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x00810000 0x1000>; - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-msm8916"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x01800000 0x80000>; - }; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; - tcsr_mutex: hwlock@1905000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01905000 0x20000>; - #hwlock-cells = <1>; + status = "disabled"; }; - tcsr: syscon@1937000 { - compatible = "qcom,tcsr-msm8916", "syscon"; - reg = <0x01937000 0x30000>; - }; + /* CTI 1 - TPIU connections */ + cti1: cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x00811000 0x1000>; - rpm_msg_ram: memory@60000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00060000 0x8000>; - }; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; status = "disabled"; }; - a53pll: clock@b016000 { - compatible = "qcom,msm8916-a53pll"; - reg = <0x0b016000 0x40>; - #clock-cells = <0>; - }; + /* CTIs 2-11 - no information - not instantiated */ - apcs: mailbox@b011000 { - compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; - reg = <0x0b011000 0x1000>; - #mbox-cells = <1>; - clocks = <&a53pll>, <&gcc GPLL0_VOTE>; - clock-names = "pll", "aux"; - #clock-cells = <0>; - }; + tpiu: tpiu@820000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x00820000 0x1000>; - blsp1_uart2: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b0000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - status = "disabled"; - }; + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x23000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; status = "disabled"; - }; - blsp_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b5000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = <&replicator_out1>; + }; + }; + }; }; - blsp_spi2: spi@78b6000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b6000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + funnel0: funnel@821000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x00821000 0x1000>; - blsp_spi3: spi@78b7000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b7000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; - blsp_spi4: spi@78b8000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b8000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; - }; - blsp_spi5: spi@78b9000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b9000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 13>, <&blsp_dma 12>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + in-ports { + #address-cells = <1>; + #size-cells = <0>; - blsp_spi6: spi@78ba000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078ba000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi6_default>; - pinctrl-1 = <&spi6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + /* + * Not described input ports: + * 0 - connected to Resource and Power Manger CPU ETM + * 1 - not-connected + * 2 - connected to Modem CPU ETM + * 3 - not-connected + * 5 - not-connected + * 6 - connected trought funnel to Wireless CPU ETM + * 7 - connected to STM component + */ - blsp_i2c1: i2c@78b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b5000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + port@4 { + reg = <4>; + funnel0_in4: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + }; - blsp_i2c2: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b6000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; }; - blsp_i2c4: i2c@78b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b8000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_default>; - pinctrl-1 = <&i2c4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + replicator: replicator@824000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x00824000 0x1000>; - blsp_i2c5: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b9000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; - blsp_i2c6: i2c@78ba000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078ba000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; - }; - sound: sound@7702000 { - status = "disabled"; - compatible = "qcom,apq8016-sbc-sndcard"; - reg = <0x07702000 0x4>, <0x07702004 0x4>; - reg-names = "mic-iomux", "spkr-iomux"; + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; }; - lpass: audio-controller@7708000 { - status = "disabled"; - compatible = "qcom,lpass-cpu-apq8016"; - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; + etf: etf@825000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x00825000 0x1000>; - clock-names = "ahbix-clk", - "pcnoc-mport-clk", - "pcnoc-sway-clk", - "mi2s-bit-clk0", - "mi2s-bit-clk1", - "mi2s-bit-clk2", - "mi2s-bit-clk3"; - #sound-dai-cells = <1>; + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; - interrupts = ; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x07708000 0x10000>; - reg-names = "lpass-lpaif"; + status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + }; - lpass_codec: audio-codec@771c000 { - compatible = "qcom,msm8916-wcd-digital-codec"; - reg = <0x0771c000 0x400>; - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "ahbix-clk", "mclk"; - #sound-dai-cells = <1>; + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; }; - sdhc_1: sdhci@7824000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names = "hc_mem", "core_mem"; + etr: etr@826000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x00826000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - mmc-ddr-1_8v; - bus-width = <8>; - non-removable; status = "disabled"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out0>; + }; + }; + }; }; - sdhc_2: sdhci@7864000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names = "hc_mem", "core_mem"; + funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x00841000 0x1000>; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - bus-width = <4>; - status = "disabled"; - }; + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; - usb: usb@78d9000 { - compatible = "qcom,ci-hdrc"; - reg = <0x078d9000 0x200>, - <0x078d9200 0x200>; - interrupts = , - ; - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <80000000>; - resets = <&gcc GCC_USB_HS_BCR>; - reset-names = "core"; - phy_type = "ulpi"; - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - ahb-burst-config = <0>; - phy-names = "usb-phy"; - phys = <&usb_hs_phy>; status = "disabled"; - #reset-cells = <1>; - ulpi { - usb_hs_phy: phy { - compatible = "qcom,usb-hs-phy-msm8916", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; - reset-names = "phy", "por"; - qcom,init-seq = /bits/ 8 <0x0 0x44 - 0x1 0x6b 0x2 0x24 0x3 0x13>; + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel1_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + funnel1_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + port@2 { + reg = <2>; + funnel1_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + port@3 { + reg = <3>; + funnel1_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; }; }; - }; - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&funnel0_in4>; + }; + }; + }; }; - timer@b020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0b020000 0x1000>; - clock-frequency = <19200000>; + debug0: debug@850000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x00850000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU0>; + status = "disabled"; + }; - frame@b021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0b021000 0x1000>, - <0x0b022000 0x1000>; - }; + debug1: debug@852000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x00852000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU1>; + status = "disabled"; + }; - frame@b023000 { - frame-number = <1>; - interrupts = ; - reg = <0x0b023000 0x1000>; - status = "disabled"; - }; + debug2: debug@854000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x00854000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU2>; + status = "disabled"; + }; - frame@b024000 { - frame-number = <2>; - interrupts = ; - reg = <0x0b024000 0x1000>; - status = "disabled"; - }; + debug3: debug@856000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x00856000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU3>; + status = "disabled"; + }; - frame@b025000 { - frame-number = <3>; - interrupts = ; - reg = <0x0b025000 0x1000>; - status = "disabled"; - }; + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti12: cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x00858000 0x1000>; - frame@b026000 { - frame-number = <4>; - interrupts = ; - reg = <0x0b026000 0x1000>; - status = "disabled"; - }; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; - frame@b027000 { - frame-number = <5>; - interrupts = ; - reg = <0x0b027000 0x1000>; - status = "disabled"; - }; + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; - frame@b028000 { - frame-number = <6>; - interrupts = ; - reg = <0x0b028000 0x1000>; - status = "disabled"; - }; + status = "disabled"; }; - spmi_bus: spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0200f000 0x001000>, - <0x02400000 0x400000>, - <0x02c00000 0x400000>, - <0x03800000 0x200000>, - <0x0200a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; + /* CTI - CPU-1 */ + cti13: cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x00859000 0x1000>; - rng@22000 { - compatible = "qcom,prng"; - reg = <0x00022000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; - qfprom: qfprom@5c000 { - compatible = "qcom,qfprom"; - reg = <0x0005c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; - }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; - }; - }; + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; - tsens: thermal-sensor@4a9000 { - compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; - #qcom,sensors = <5>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; + status = "disabled"; }; - apps_iommu: iommu@1ef0000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x01e20000 0x40000>; - reg = <0x01ef0000 0x3000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_APSS_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <17>; + /* CTI - CPU-2 */ + cti14: cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x0085a000 0x1000>; - // vfe: - iommu-ctx@3000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x3000 0x1000>; - interrupts = ; - }; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; - // mdp_0: - iommu-ctx@4000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x4000 0x1000>; - interrupts = ; - }; + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; - // venus_ns: - iommu-ctx@5000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x5000 0x1000>; - interrupts = ; - }; + status = "disabled"; }; - gpu_iommu: iommu@1f08000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x01f08000 0x10000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_GFX_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <18>; + /* CTI - CPU-3 */ + cti15: cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x0085b000 0x1000>; - // gfx3d_user: - iommu-ctx@1000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x1000 0x1000>; - interrupts = ; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + + status = "disabled"; + }; + + etm0: etm@85c000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0085c000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU0>; + + status = "disabled"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel1_in0>; + }; + }; }; + }; - // gfx3d_priv: - iommu-ctx@2000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x2000 0x1000>; - interrupts = ; + etm1: etm@85d000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0085d000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU1>; + + status = "disabled"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel1_in1>; + }; + }; }; }; - gpu@1c00000 { - compatible = "qcom,adreno-306.0", "qcom,adreno"; - reg = <0x01c00000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - clock-names = - "core", - "iface", - "mem", - "mem_iface", - "alt_mem_iface", - "gfx3d"; - clocks = - <&gcc GCC_OXILI_GFX3D_CLK>, - <&gcc GCC_OXILI_AHB_CLK>, - <&gcc GCC_OXILI_GMEM_CLK>, - <&gcc GCC_BIMC_GFX_CLK>, - <&gcc GCC_BIMC_GPU_CLK>, - <&gcc GFX3D_CLK_SRC>; - power-domains = <&gcc OXILI_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + etm2: etm@85e000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0085e000 0x1000>; - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,coresight-loses-context-with-cpu; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; + cpu = <&CPU2>; + + status = "disabled"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel1_in2>; + }; }; - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; + }; + }; + + etm3: etm@85f000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0085f000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU3>; + + status = "disabled"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel1_in3>; + }; }; }; }; + msmgpio: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 122>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8916"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x01800000 0x80000>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x01937000 0x30000>; + }; + mdss: mdss@1a00000 { compatible = "qcom,mdss"; reg = <0x01a00000 0x1000>, @@ -1161,42 +1006,284 @@ }; }; - mpss: remoteproc@4080000 { - compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; - reg = <0x04080000 0x100>, - <0x04020000 0x040>; - - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - qcom,smem-states = <&hexagon_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&scm 0>; - reset-names = "mss_restart"; - - qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; - + camss: camss@1b00000 { + compatible = "qcom,msm8916-camss"; + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "ispif", + "csi_clk_mux", + "vfe0"; + interrupts = , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "ispif", + "vfe0"; + power-domains = <&gcc VFE_GDSC>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>; + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi"; + iommus = <&apps_iommu 3>; status = "disabled"; - - mba { - memory-region = <&mba_mem>; + ports { + #address-cells = <1>; + #size-cells = <0>; }; + }; - mpss { + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x01b0c000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", "cci_ahb", + "cci", "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <19200000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gpu@1c00000 { + compatible = "qcom,adreno-306.0", "qcom,adreno"; + reg = <0x01c00000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d"; + clocks = + <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + power-domains = <&gcc OXILI_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; + }; + + venus: video-codec@1d00000 { + compatible = "qcom,msm8916-venus"; + reg = <0x01d00000 0xff000>; + interrupts = ; + power-domains = <&gcc VENUS_GDSC>; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>; + clock-names = "core", "iface", "bus"; + iommus = <&apps_iommu 5>; + memory-region = <&venus_mem>; + status = "okay"; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + }; + + apps_iommu: iommu@1ef0000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x01e20000 0x40000>; + reg = <0x01ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + // vfe: + iommu-ctx@3000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + + // mdp_0: + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + + // venus_ns: + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x01f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <18>; + + // gfx3d_user: + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + // gfx3d_priv: + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x400000>, + <0x02c00000 0x400000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + mpss: remoteproc@4080000 { + compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; + reg = <0x04080000 0x100>, + <0x04020000 0x040>; + + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&scm 0>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { memory-region = <&mpss_mem>; }; @@ -1225,690 +1312,603 @@ }; }; - pronto: remoteproc@a21b000 { - compatible = "qcom,pronto-v2-pil", "qcom,pronto"; - reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - memory-region = <&wcnss_mem>; - - interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - qcom,state = <&wcnss_smp2p_out 0>; - qcom,state-names = "stop"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; + sound: sound@7702000 { + status = "disabled"; + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + }; + lpass: audio-controller@7708000 { status = "disabled"; + compatible = "qcom,lpass-cpu-apq8016"; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; - iris { - compatible = "qcom,wcn3620"; + clock-names = "ahbix-clk", + "pcnoc-mport-clk", + "pcnoc-sway-clk", + "mi2s-bit-clk0", + "mi2s-bit-clk1", + "mi2s-bit-clk2", + "mi2s-bit-clk3"; + #sound-dai-cells = <1>; - clocks = <&rpmcc RPM_SMD_RF_CLK2>; - clock-names = "xo"; - }; + interrupts = ; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x07708000 0x10000>; + reg-names = "lpass-lpaif"; - smd-edge { - interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - qcom,remote-pid = <4>; - - label = "pronto"; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - }; - - wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = , - ; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; - }; - - tpiu: tpiu@820000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x00820000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel0: funnel@821000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x00821000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - connected to Resource and Power Manger CPU ETM - * 1 - not-connected - * 2 - connected to Modem CPU ETM - * 3 - not-connected - * 5 - not-connected - * 6 - connected trought funnel to Wireless CPU ETM - * 7 - connected to STM component - */ - - port@4 { - reg = <4>; - funnel0_in4: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; + lpass_codec: audio-codec@771c000 { + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; }; - replicator: replicator@824000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x00824000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; + sdhc_1: sdhci@7824000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x11c>, <0x07824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; status = "disabled"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; }; - etf: etf@825000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x00825000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; + sdhc_2: sdhci@7864000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + bus-width = <4>; status = "disabled"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; }; - etr: etr@826000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x00826000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; status = "disabled"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; }; - funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x00841000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 1>, <&blsp_dma 0>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; status = "disabled"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel1_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - funnel1_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@2 { - reg = <2>; - funnel1_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@3 { - reg = <3>; - funnel1_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&funnel0_in4>; - }; - }; - }; }; - debug0: debug@850000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00850000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU0>; + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 3>, <&blsp_dma 2>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; status = "disabled"; }; - debug1: debug@852000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00852000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU1>; + blsp_i2c1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - debug2: debug@854000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00854000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU2>; + blsp_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 5>, <&blsp_dma 4>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - debug3: debug@856000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00856000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU3>; + blsp_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - etm0: etm@85c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085c000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU0>; - + blsp_spi2: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 7>, <&blsp_dma 6>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&funnel1_in0>; - }; - }; - }; }; - etm1: etm@85d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085d000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU1>; - + blsp_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 9>, <&blsp_dma 8>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&funnel1_in1>; - }; - }; - }; }; - etm2: etm@85e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085e000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU2>; - + blsp_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_default>; + pinctrl-1 = <&i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&funnel1_in2>; - }; - }; - }; }; - etm3: etm@85f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085f000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU3>; - + blsp_spi4: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 11>, <&blsp_dma 10>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&funnel1_in3>; - }; - }; - }; }; - /* System CTIs */ - /* CTI 0 - TMC connections */ - cti0: cti@810000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x00810000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - + blsp_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - /* CTI 1 - TPIU connections */ - cti1: cti@811000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x00811000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - + blsp_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 13>, <&blsp_dma 12>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_default>; + pinctrl-1 = <&spi5_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - /* CTIs 2-11 - no information - not instantiated */ - - /* Core CTIs; CTIs 12-15 */ - /* CTI - CPU-0 */ - cti12: cti@858000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x00858000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU0>; - arm,cs-dev-assoc = <&etm0>; - + blsp_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_default>; + pinctrl-1 = <&i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - /* CTI - CPU-1 */ - cti13: cti@859000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x00859000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - arm,cs-dev-assoc = <&etm1>; - + blsp_spi6: spi@78ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 15>, <&blsp_dma 14>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi6_default>; + pinctrl-1 = <&spi6_sleep>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - /* CTI - CPU-2 */ - cti14: cti@85a000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x0085a000 0x1000>; + usb: usb@78d9000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078d9000 0x200>, + <0x078d9200 0x200>; + interrupts = , + ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8916", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + qcom,init-seq = /bits/ 8 <0x0 0x44 + 0x1 0x6b 0x2 0x24 0x3 0x13>; + }; + }; + }; - cpu = <&CPU2>; - arm,cs-dev-assoc = <&etm2>; + pronto: remoteproc@a21b000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; - status = "disabled"; - }; + memory-region = <&wcnss_mem>; - /* CTI - CPU-3 */ - cti15: cti@85b000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x0085b000 0x1000>; + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; + qcom,state = <&wcnss_smp2p_out 0>; + qcom,state-names = "stop"; - cpu = <&CPU3>; - arm,cs-dev-assoc = <&etm3>; + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; status = "disabled"; - }; - venus: video-codec@1d00000 { - compatible = "qcom,msm8916-venus"; - reg = <0x01d00000 0xff000>; - interrupts = ; - power-domains = <&gcc VENUS_GDSC>; - clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, - <&gcc GCC_VENUS0_AHB_CLK>, - <&gcc GCC_VENUS0_AXI_CLK>; - clock-names = "core", "iface", "bus"; - iommus = <&apps_iommu 5>; - memory-region = <&venus_mem>; - status = "okay"; + iris { + compatible = "qcom,wcn3620"; - video-decoder { - compatible = "venus-decoder"; + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; }; - video-encoder { - compatible = "venus-encoder"; - }; - }; + smd-edge { + interrupts = ; - camss: camss@1b00000 { - compatible = "qcom,msm8916-camss"; - reg = <0x01b0ac00 0x200>, - <0x01b00030 0x4>, - <0x01b0b000 0x200>, - <0x01b00038 0x4>, - <0x01b08000 0x100>, - <0x01b08400 0x100>, - <0x01b0a000 0x500>, - <0x01b00020 0x10>, - <0x01b10000 0x1000>; - reg-names = "csiphy0", - "csiphy0_clk_mux", - "csiphy1", - "csiphy1_clk_mux", - "csid0", - "csid1", - "ispif", - "csi_clk_mux", - "vfe0"; - interrupts = , - , - , - , - , - ; - interrupt-names = "csiphy0", - "csiphy1", - "csid0", - "csid1", - "ispif", - "vfe0"; - power-domains = <&gcc VFE_GDSC>; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI0_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0_CLK>, - <&gcc GCC_CAMSS_CSI0PHY_CLK>, - <&gcc GCC_CAMSS_CSI0PIX_CLK>, - <&gcc GCC_CAMSS_CSI0RDI_CLK>, - <&gcc GCC_CAMSS_CSI1_AHB_CLK>, - <&gcc GCC_CAMSS_CSI1_CLK>, - <&gcc GCC_CAMSS_CSI1PHY_CLK>, - <&gcc GCC_CAMSS_CSI1PIX_CLK>, - <&gcc GCC_CAMSS_CSI1RDI_CLK>, - <&gcc GCC_CAMSS_AHB_CLK>, - <&gcc GCC_CAMSS_VFE0_CLK>, - <&gcc GCC_CAMSS_CSI_VFE0_CLK>, - <&gcc GCC_CAMSS_VFE_AHB_CLK>, - <&gcc GCC_CAMSS_VFE_AXI_CLK>; - clock-names = "top_ahb", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe_ahb", - "vfe_axi"; - iommus = <&apps_iommu 3>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; - cci: cci@1b0c000 { - compatible = "qcom,msm8916-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01b0c000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_CLK>, - <&gcc GCC_CAMSS_AHB_CLK>; - clock-names = "camss_top_ahb", "cci_ahb", - "cci", "camss_ahb"; - assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_CLK>; - assigned-clock-rates = <80000000>, <19200000>; - pinctrl-names = "default"; - pinctrl-0 = <&cci0_default>; - status = "disabled"; + label = "pronto"; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; + qcom,mmio = <&pronto>; - smd { - compatible = "qcom,smd"; + bt { + compatible = "qcom,wcnss-bt"; + }; - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; + wifi { + compatible = "qcom,wcnss-wlan"; - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8916"; - qcom,smd-channels = "rpm_requests"; + interrupts = , + ; + interrupt-names = "tx", "rx"; - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8916"; - #clock-cells = <1>; + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; }; }; }; - }; - smp2p-hexagon { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + }; - interrupts = ; + apcs: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&a53pll>, <&gcc GPLL0_VOTE>; + clock-names = "pll", "aux"; + #clock-cells = <0>; + }; - qcom,ipc = <&apcs 8 14>; + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0x0b016000 0x40>; + #clock-cells = <0>; + }; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; + timer@b020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b020000 0x1000>; + clock-frequency = <19200000>; - hexagon_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; + frame@b021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0b021000 0x1000>, + <0x0b022000 0x1000>; + }; - #qcom,smem-state-cells = <1>; - }; + frame@b023000 { + frame-number = <1>; + interrupts = ; + reg = <0x0b023000 0x1000>; + status = "disabled"; + }; - hexagon_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; + frame@b024000 { + frame-number = <2>; + interrupts = ; + reg = <0x0b024000 0x1000>; + status = "disabled"; + }; - interrupt-controller; - #interrupt-cells = <2>; + frame@b025000 { + frame-number = <3>; + interrupts = ; + reg = <0x0b025000 0x1000>; + status = "disabled"; + }; + + frame@b026000 { + frame-number = <4>; + interrupts = ; + reg = <0x0b026000 0x1000>; + status = "disabled"; + }; + + frame@b027000 { + frame-number = <5>; + interrupts = ; + reg = <0x0b027000 0x1000>; + status = "disabled"; + }; + + frame@b028000 { + frame-number = <6>; + interrupts = ; + reg = <0x0b028000 0x1000>; + status = "disabled"; + }; }; }; - smp2p-wcnss { - compatible = "qcom,smp2p"; - qcom,smem = <451>, <431>; + thermal-zones { + cpu0-1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; - interrupts = ; + thermal-sensors = <&tsens 5>; - qcom,ipc = <&apcs 8 18>; + trips { + cpu0_1_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_1_crit: cpu_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; - qcom,local-pid = <0>; - qcom,remote-pid = <4>; + cooling-maps { + map0 { + trip = <&cpu0_1_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; + cpu2-3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; - #qcom,smem-state-cells = <1>; - }; + thermal-sensors = <&tsens 4>; - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; + trips { + cpu2_3_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_3_crit: cpu_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; - interrupt-controller; - #interrupt-cells = <2>; + cooling-maps { + map0 { + trip = <&cpu2_3_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; - }; - smsm { - compatible = "qcom,smsm"; + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; - #address-cells = <1>; - #size-cells = <0>; + thermal-sensors = <&tsens 2>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-3 = <&apcs 8 19>; + trips { + gpu_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; - apps_smsm: apps@0 { - reg = <0>; + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; - #qcom,smem-state-cells = <1>; + thermal-sensors = <&tsens 1>; + + trips { + cam_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; }; - hexagon_smsm: hexagon@1 { - reg = <1>; - interrupts = ; + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; - interrupt-controller; - #interrupt-cells = <2>; + thermal-sensors = <&tsens 0>; + + trips { + modem_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + }; }; - wcnss_smsm: wcnss@6 { - reg = <6>; - interrupts = ; + }; - interrupt-controller; - #interrupt-cells = <2>; - }; + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; }; }; -- cgit v1.2.3 From 09a587a06724164ff6e11651feb5f98ead24ac4c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:20 +0200 Subject: arm64: dts: qcom: pm8916: Sort nodes Sort nodes by unit address so we have a consistent order in pm8916.dtsi. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-14-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 60 ++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index c7b22ac81452..f931cb0de231 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include -#include #include +#include #include &spmi_bus { @@ -12,13 +12,6 @@ #address-cells = <1>; #size-cells = <0>; - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x800>; @@ -48,28 +41,6 @@ }; }; - pm8916_gpios: gpios@c000 { - compatible = "qcom,pm8916-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>; - }; - - pm8916_mpps: mpps@a000 { - compatible = "qcom,pm8916-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>; - }; - pm8916_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; @@ -111,6 +82,35 @@ reg = ; }; }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm8916_mpps: mpps@a000 { + compatible = "qcom,pm8916-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>; + }; + + pm8916_gpios: gpios@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>; + }; }; pm8916_1: pmic@1 { -- cgit v1.2.3 From a9118250462529ffee0f758b2e55da0658cd1f22 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 15 Sep 2020 09:12:21 +0200 Subject: arm64: dts: qcom: Makefile: Sort lines The Makefile is in a bit of a weird order at the moment. It's almost sorted alphabetically, but not entirely. Also, one element uses a space before the += instead of a tab. Fix this up and sort the lines alphabetically so we have a consistent order in the Makefile. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200915071221.72895-15-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7d71a51ca4ea..fb4631f898fd 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb @@ -18,6 +18,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb @@ -40,6 +43,3 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb -- cgit v1.2.3 From 7901c2bc3ffc70764bf00f7862edeacb083ecd5c Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 3 Sep 2020 16:31:32 +0300 Subject: arm64: dts: qcom: sdm845: Increase the number of interconnect cells Increase the number of interconnect-cells, as now we can include the tag information. The consumers can specify the path tag as an additional argument to the endpoints. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Reviewed-by: Matthias Kaehlcke Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20200903133134.17201-6-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 48 ++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 86457d9bc229..b4062063d74a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -200,7 +200,7 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; next-level-cache = <&L2_0>; @@ -225,7 +225,7 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; next-level-cache = <&L2_100>; @@ -247,7 +247,7 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; next-level-cache = <&L2_200>; @@ -269,7 +269,7 @@ dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; next-level-cache = <&L2_300>; @@ -291,7 +291,7 @@ dynamic-power-coefficient = <396>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; next-level-cache = <&L2_400>; @@ -313,7 +313,7 @@ dynamic-power-coefficient = <396>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; next-level-cache = <&L2_500>; @@ -335,7 +335,7 @@ dynamic-power-coefficient = <396>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; next-level-cache = <&L2_600>; @@ -357,7 +357,7 @@ dynamic-power-coefficient = <396>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; next-level-cache = <&L2_700>; @@ -2011,49 +2011,49 @@ mem_noc: interconnect@1380000 { compatible = "qcom,sdm845-mem-noc"; reg = <0 0x01380000 0 0x27200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; dc_noc: interconnect@14e0000 { compatible = "qcom,sdm845-dc-noc"; reg = <0 0x014e0000 0 0x400>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; config_noc: interconnect@1500000 { compatible = "qcom,sdm845-config-noc"; reg = <0 0x01500000 0 0x5080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sdm845-system-noc"; reg = <0 0x01620000 0 0x18080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sdm845-aggre1-noc"; reg = <0 0x016e0000 0 0x15080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sdm845-aggre2-noc"; reg = <0 0x01700000 0 0x1f300>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sdm845-mmss-noc"; reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -2156,9 +2156,9 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>, - <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, - <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names = "memory", "imem", "config"; @@ -3569,8 +3569,8 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; - interconnects = <&aggre2_noc MASTER_USB3_0 &mem_noc SLAVE_EBI1>, - <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_1_dwc3: dwc3@a600000 { @@ -3617,8 +3617,8 @@ resets = <&gcc GCC_USB30_SEC_BCR>; - interconnects = <&aggre2_noc MASTER_USB3_1 &mem_noc SLAVE_EBI1>, - <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_2_dwc3: dwc3@a800000 { @@ -4043,7 +4043,7 @@ qcom,gmu = <&gmu>; - interconnects = <&mem_noc MASTER_GFX3D &mem_noc SLAVE_EBI1>; + interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; gpu_opp_table: opp-table { @@ -4360,7 +4360,7 @@ gladiator_noc: interconnect@17900000 { compatible = "qcom,sdm845-gladiator-noc"; reg = <0 0x17900000 0 0xd080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; -- cgit v1.2.3 From e23b1220a24600c7b165f4da4eff3519c2eb8167 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 3 Sep 2020 16:31:34 +0300 Subject: arm64: dts: qcom: sc7180: Increase the number of interconnect cells Increase the number of interconnect-cells, as now we can include the tag information. The consumers can specify the path tag as an additional argument to the endpoints. Signed-off-by: Sibi Sankar Tested-by: Matthias Kaehlcke Reviewed-by: Matthias Kaehlcke Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20200903133134.17201-8-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 218 +++++++++++++++++------------------ 1 file changed, 109 insertions(+), 109 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ac909249886a..6678f1e8e395 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -133,7 +133,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; next-level-cache = <&L2_0>; #cooling-cells = <2>; @@ -159,7 +159,7 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -181,7 +181,7 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -203,7 +203,7 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -225,7 +225,7 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -247,7 +247,7 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -269,7 +269,7 @@ dynamic-power-coefficient = <405>; next-level-cache = <&L2_600>; operating-points-v2 = <&cpu6_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -291,7 +291,7 @@ dynamic-power-coefficient = <405>; next-level-cache = <&L2_700>; operating-points-v2 = <&cpu6_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -756,7 +756,7 @@ #size-cells = <2>; ranges; iommus = <&apps_smmu 0x43 0x0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; interconnect-names = "qup-core"; status = "disabled"; @@ -770,9 +770,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, - <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -790,8 +790,8 @@ #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -806,8 +806,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -822,9 +822,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, - <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -842,8 +842,8 @@ #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -858,8 +858,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -874,9 +874,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, - <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -892,8 +892,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -908,9 +908,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, - <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -928,8 +928,8 @@ #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -944,8 +944,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -960,9 +960,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, - <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -978,8 +978,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -994,9 +994,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, - <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -1014,8 +1014,8 @@ #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1030,8 +1030,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1047,7 +1047,7 @@ #size-cells = <2>; ranges; iommus = <&apps_smmu 0x4c3 0x0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; status = "disabled"; @@ -1061,9 +1061,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, - <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -1081,8 +1081,8 @@ #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1097,8 +1097,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1113,9 +1113,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, - <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -1131,8 +1131,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1147,9 +1147,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, - <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -1167,8 +1167,8 @@ #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1183,8 +1183,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1199,9 +1199,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, - <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -1217,8 +1217,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1233,9 +1233,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, - <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -1253,8 +1253,8 @@ #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1269,8 +1269,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1285,9 +1285,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, - <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; @@ -1305,8 +1305,8 @@ #size-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1321,8 +1321,8 @@ interrupts = ; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1331,63 +1331,63 @@ config_noc: interconnect@1500000 { compatible = "qcom,sc7180-config-noc"; reg = <0 0x01500000 0 0x28000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sc7180-system-noc"; reg = <0 0x01620000 0 0x17080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@1638000 { compatible = "qcom,sc7180-mc-virt"; reg = <0 0x01638000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; qup_virt: interconnect@1650000 { compatible = "qcom,sc7180-qup-virt"; reg = <0 0x01650000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sc7180-aggre1-noc"; reg = <0 0x016e0000 0 0x15080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1705000 { compatible = "qcom,sc7180-aggre2-noc"; reg = <0 0x01705000 0 0x9000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; compute_noc: interconnect@170e000 { compatible = "qcom,sc7180-compute-noc"; reg = <0 0x0170e000 0 0x6000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sc7180-mmss-noc"; reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; ipa_virt: interconnect@1e00000 { compatible = "qcom,sc7180-ipa-virt"; reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1414,9 +1414,9 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, - <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names = "memory", "imem", "config"; @@ -1907,7 +1907,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; - interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; gpu_opp_table: opp-table { @@ -2581,8 +2581,8 @@ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; - interconnects = <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_QSPI_0>; + interconnects = <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QSPI_0 0>; interconnect-names = "qspi-config"; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qspi_opp_table>; @@ -2641,7 +2641,7 @@ dc_noc: interconnect@9160000 { compatible = "qcom,sc7180-dc-noc"; reg = <0 0x09160000 0 0x03200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -2655,14 +2655,14 @@ gem_noc: interconnect@9680000 { compatible = "qcom,sc7180-gem-noc"; reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; npu_noc: interconnect@9990000 { compatible = "qcom,sc7180-npu-noc"; reg = <0 0x09990000 0 0x1600>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -2698,8 +2698,8 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; - interconnects = <&aggre2_noc MASTER_USB3 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>; + interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_1_dwc3: dwc3@a600000 { @@ -2733,8 +2733,8 @@ "vcodec0_core", "vcodec0_bus"; iommus = <&apps_smmu 0x0c00 0x60>; memory-region = <&venus_mem>; - interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; + interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; interconnect-names = "video-mem", "cpu-cfg"; video-decoder { @@ -2788,7 +2788,7 @@ camnoc_virt: interconnect@ac00000 { compatible = "qcom,sc7180-camnoc-virt"; reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; -- cgit v1.2.3 From 71a2fc6e7b30a0234d3895fa0d91be754dc06905 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 27 Jul 2020 22:38:05 -0400 Subject: arm64: dts: qcom: sm8150: add interconnect nodes Add the interconnect dts nodes for sm8150. Reviewed-by: Sibi Sankar Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200728023811.5607-7-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 81 ++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 62d49e81483e..8f26df1651cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -440,6 +440,55 @@ }; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sm8150-config-noc"; + reg = <0 0x01500000 0 0x7400>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm8150-system-noc"; + reg = <0 0x01620000 0 0x19400>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@163a000 { + compatible = "qcom,sm8150-mc-virt"; + reg = <0 0x0163a000 0 0x1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8150-aggre1-noc"; + reg = <0 0x016e0000 0 0xd080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm8150-aggre2-noc"; + reg = <0 0x01700000 0 0x20000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + compute_noc: interconnect@1720000 { + compatible = "qcom,sm8150-compute-noc"; + reg = <0 0x01720000 0 0x7000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sm8150-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -508,6 +557,13 @@ }; }; + ipa_virt: interconnect@1e00000 { + compatible = "qcom,sm8150-ipa-virt"; + reg = <0 0x01e00000 0 0x1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -814,6 +870,20 @@ }; }; + dc_noc: interconnect@9160000 { + compatible = "qcom,sm8150-dc-noc"; + reg = <0 0x09160000 0 0x3200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + compatible = "qcom,sm8150-gem-noc"; + reg = <0 0x09680000 0 0x3e200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; @@ -858,6 +928,13 @@ }; }; + camnoc_virt: interconnect@ac00000 { + compatible = "qcom,sm8150-camnoc-virt"; + reg = <0 0x0ac00000 0 0x1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8150-aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x100000>; @@ -1100,6 +1177,10 @@ }; }; }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; }; cpufreq_hw: cpufreq@18323000 { -- cgit v1.2.3 From e7e41a207a3e37fe29a799fc0940b3a540237a49 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 27 Jul 2020 22:38:06 -0400 Subject: arm64: dts: qcom: sm8250: add interconnect nodes Add the interconnect dts nodes for sm8250. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200728023811.5607-8-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 81 ++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 6cd45a667ba9..92f40b6d04e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1091,6 +1091,55 @@ }; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sm8250-config-noc"; + reg = <0 0x01500000 0 0xa580>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm8250-system-noc"; + reg = <0 0x01620000 0 0x1c200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@163d000 { + compatible = "qcom,sm8250-mc-virt"; + reg = <0 0x0163d000 0 0x1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8250-aggre1-noc"; + reg = <0 0x016e0000 0 0x1f180>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm8250-aggre2-noc"; + reg = <0 0x01700000 0 0x33000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + compute_noc: interconnect@1733000 { + compatible = "qcom,sm8250-compute-noc"; + reg = <0 0x01733000 0 0xa180>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sm8250-mmss-noc"; + reg = <0 0x01740000 0 0x1f080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -1161,6 +1210,13 @@ }; }; + ipa_virt: interconnect@1e00000 { + compatible = "qcom,sm8250-ipa-virt"; + reg = <0 0x01e00000 0 0x1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -1386,6 +1442,27 @@ }; }; + dc_noc: interconnect@90c0000 { + compatible = "qcom,sm8250-dc-noc"; + reg = <0 0x090c0000 0 0x4200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible = "qcom,sm8250-gem-noc"; + reg = <0 0x09100000 0 0xb4000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + npu_noc: interconnect@9990000 { + compatible = "qcom,sm8250-npu-noc"; + reg = <0 0x09990000 0 0x1600>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; @@ -2223,6 +2300,10 @@ }; }; }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; }; }; -- cgit v1.2.3 From a6d435c1a6aec3d86b2857204473176ac6eced1f Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Sat, 1 Aug 2020 18:00:48 +0530 Subject: arm64: dts: qcom: sm8150: Add OSM L3 interconnect provider Add Operation State Manager (OSM) L3 interconnect provider node on SM8150 SoCs. Acked-by: Georgi Djakov Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20200801123049.32398-7-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8f26df1651cd..f0a872e02686 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include / { @@ -1183,6 +1184,16 @@ }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sm8150-osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, -- cgit v1.2.3 From 79a595bb92ea4b6bc33a704ad4db584c07c949ff Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Sat, 1 Aug 2020 18:00:49 +0530 Subject: arm64: dts: qcom: sm8250: Add EPSS L3 interconnect provider Add Epoch Subsystem (EPSS) L3 interconnect provider node on SM8250 SoCs. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20200801123049.32398-8-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 92f40b6d04e9..f49a4a1651e2 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -2305,6 +2306,16 @@ compatible = "qcom,bcm-voter"; }; }; + + epss_l3: interconnect@18591000 { + compatible = "qcom,sm8250-epss-l3"; + reg = <0 0x18590000 0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; }; timer { -- cgit v1.2.3 From c8c61c09e38b894e68e1d9c6c3c1bfcae3cbf8cf Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 16 Sep 2020 00:45:11 +0300 Subject: arm64: dts: qcom: sdm845: Add interconnects property for display Add the interconnect paths that are used by the display (MDSS). This will allow the driver to request the needed bandwidth and prevent display flickering. Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20200915214511.786-1-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b4062063d74a..d3737ffbf824 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3813,6 +3813,10 @@ interrupt-controller; #interrupt-cells = <1>; + interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + iommus = <&apps_smmu 0x880 0x8>, <&apps_smmu 0xc80 0x8>; -- cgit v1.2.3 From 45145406f30c693564904335d216c3b18c0e1e8b Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Tue, 28 Apr 2020 14:40:23 +0200 Subject: arm64: dts: sparx5: Add Sparx5 eMMC support This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200825081357.32354-4-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 24 ++++++++++++++++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 23 +++++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 23 +++++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 23 +++++++++++++++++++++ 4 files changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index cf712e80615d..d477fcb57e64 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { compatible = "microchip,sparx5"; @@ -151,6 +152,20 @@ interrupts = ; }; + sdhci0: mmc@600800000 { + compatible = "microchip,dw-sparx5-sdhci"; + status = "disabled"; + reg = <0x6 0x00800000 0x1000>; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + clocks = <&clks CLK_ID_AUX1>; + clock-names = "core"; + assigned-clocks = <&clks CLK_ID_AUX1>; + assigned-clock-rates = <800000000>; + interrupts = ; + bus-width = <8>; + }; + gpio: pinctrl@6110101e0 { compatible = "microchip,sparx5-pinctrl"; reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; @@ -180,6 +195,15 @@ pins = "GPIO_28", "GPIO_29"; function = "twi2"; }; + + emmc_pins: emmc-pins { + pins = "GPIO_34", "GPIO_35", "GPIO_36", + "GPIO_37", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + function = "emmc"; + }; }; i2c0: i2c@600101000 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 91ee5b6cfc37..573309fe4582 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -16,6 +16,29 @@ }; }; +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + bus-width = <8>; + non-removable; + pinctrl-0 = <&emmc_pins>; + max-frequency = <8000000>; + microchip,clock-delay = <10>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts index 10081a66961b..bbb9852c1f15 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts @@ -15,3 +15,26 @@ reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; + microchip,clock-delay = <10>; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts index 741f0e12260e..f82266fe2ad4 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts @@ -15,3 +15,26 @@ reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; + microchip,clock-delay = <10>; +}; -- cgit v1.2.3 From d14f6a1ae07f034921741c631ba83ceb97fe6734 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Tue, 28 Apr 2020 16:50:42 +0200 Subject: arm64: dts: sparx5: Add hwmon temperature sensor This adds a hwmon temperature node sensor to the Sparx5 SoC. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200618135951.25441-3-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index d477fcb57e64..a84ffd3069d4 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -233,5 +233,12 @@ clock-frequency = <100000>; clocks = <&ahb_clk>; }; + + tmon0: tmon@610508110 { + compatible = "microchip,sparx5-temp"; + reg = <0x6 0x10508110 0xc>; + #thermal-sensor-cells = <0>; + clocks = <&ahb_clk>; + }; }; }; -- cgit v1.2.3 From b17400c9dec40d5f263cfe692452e70ec978066a Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 14 Sep 2020 10:27:04 +0200 Subject: MAINTAINERS: Add git tree for Sparx5 This adds a git tree for maintaining the Sparx5 SoC from. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200914083257.11080-1-lars.povlsen@microchip.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index deaafb617361..eda3c051b13c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2136,6 +2136,7 @@ M: Steen Hegelund M: Microchip Linux Driver Support L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported +T: git git://github.com/microchip-ung/linux-upstream.git F: arch/arm64/boot/dts/microchip/ N: sparx5 -- cgit v1.2.3 From 08ee16e95492f41d69df3b7fbd942d35dfece6a9 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 24 Aug 2020 22:30:07 +0200 Subject: arm64: dts: sparx5: Add SPI controller and associated mmio-mux This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for a given SPI device. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index a84ffd3069d4..b7a38557fb77 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -14,6 +14,7 @@ #size-cells = <1>; aliases { + spi0 = &spi0; serial0 = &uart0; serial1 = &uart1; }; @@ -118,6 +119,22 @@ interrupts = ; }; + cpu_ctrl: syscon@600000000 { + compatible = "microchip,sparx5-cpu-syscon", "syscon", + "simple-mfd"; + reg = <0x6 0x00000000 0xd0>; + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <0>; + /* + * SI_OWNER and SI2_OWNER in GENERAL_CTRL + * SPI: value 9 - (SIMC,SIBM) = 0b1001 + * SPI2: value 6 - (SIBM,SIMC) = 0b0110 + */ + mux-reg-masks = <0x88 0xf0>; + }; + }; + uart0: serial@600100000 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default"; @@ -144,6 +161,19 @@ status = "disabled"; }; + spi0: spi@600104000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-spi"; + reg = <0x6 0x00104000 0x40>; + num-cs = <16>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + timer1: timer@600105000 { compatible = "snps,dw-apb-timer"; reg = <0x6 0x00105000 0x1000>; -- cgit v1.2.3 From b0d0c3bba90b913ec7762187b64607d43cb855fb Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 31 Aug 2020 19:11:26 +0200 Subject: ARM: dts: at91: move mmc pinctrl-names property to board dts Having the pinctrl-names property in the dtsi leads to dtbs_check warnings when the board dts doesn't define pinctrl-0. Instead, move the property to the board dts actually using the mmc node. Signed-off-by: Alexandre Belloni Reviewed-by: Nicolas Ferre Link: https://lore.kernel.org/r/20200831171129.3886857-5-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/animeo_ip.dts | 1 + arch/arm/boot/dts/at91-ariag25.dts | 1 + arch/arm/boot/dts/at91-ariettag25.dts | 1 + arch/arm/boot/dts/at91-cosino.dtsi | 1 + arch/arm/boot/dts/at91-cosino_mega2560.dts | 1 + arch/arm/boot/dts/at91-foxg20.dts | 1 + arch/arm/boot/dts/at91-qil_a9260.dts | 1 + arch/arm/boot/dts/at91-sam9_l9260.dts | 1 + arch/arm/boot/dts/at91-wb45n.dtsi | 1 + arch/arm/boot/dts/at91rm9200.dtsi | 1 - arch/arm/boot/dts/at91sam9260.dtsi | 1 - arch/arm/boot/dts/at91sam9260ek.dts | 1 + arch/arm/boot/dts/at91sam9263.dtsi | 2 -- arch/arm/boot/dts/at91sam9263ek.dts | 1 + arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 1 + arch/arm/boot/dts/at91sam9g45.dtsi | 2 -- arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 ++ arch/arm/boot/dts/at91sam9x5.dtsi | 2 -- arch/arm/boot/dts/at91sam9x5ek.dtsi | 2 ++ arch/arm/boot/dts/pm9g45.dts | 1 + 20 files changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index c36d28c295d6..6d7fc9c6c6e0 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -81,6 +81,7 @@ pinctrl-0 = <&pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index dbfefef2869d..2ef39ecbda18 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -93,6 +93,7 @@ pinctrl-0 = < &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/at91-ariettag25.dts index 0267e72c074a..2eb494f49078 100644 --- a/arch/arm/boot/dts/at91-ariettag25.dts +++ b/arch/arm/boot/dts/at91-ariettag25.dts @@ -48,6 +48,7 @@ pinctrl-0 = < &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi index feebd54f670e..91e386d4872f 100644 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -112,6 +112,7 @@ &pinctrl_board_mmc0 &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts index 73e88d1ba4ed..04cb7bee937d 100644 --- a/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts @@ -34,6 +34,7 @@ pinctrl-0 = < &pinctrl_mmc1_slot0_clk_cmd_dat0 &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index 683b9e37f9c5..c0509c4e5138 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -55,6 +55,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index a50b7fd2149f..ee8525d5a5da 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -52,6 +52,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot0_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts index 954404ed8158..f475c0b0f1de 100644 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -49,6 +49,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/at91-wb45n.dtsi index ebe61a25ca96..e3d98306ee3a 100644 --- a/arch/arm/boot/dts/at91-wb45n.dtsi +++ b/arch/arm/boot/dts/at91-wb45n.dtsi @@ -145,6 +145,7 @@ }; &mmc0 { + pinctrl-names = "default"; pinctrl-0 = < &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 1724e14d9994..0ea0aff2a024 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -173,7 +173,6 @@ clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index f6ac5346f910..b07578ff214c 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -654,7 +654,6 @@ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "mci_clk"; status = "disabled"; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index 81f808a10931..657dc3a420d6 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -55,6 +55,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { reg = <1>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index a321c68be64f..aea70a32511c 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -654,7 +654,6 @@ compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; @@ -666,7 +665,6 @@ compatible = "atmel,hsmci"; reg = <0xfff84000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 62d218542a48..bf89cb2bbdd9 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -72,6 +72,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot0_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index bda22700110c..c65651549692 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -93,6 +93,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { reg = <1>; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 984b5292a129..1e1b7490ee0a 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -875,7 +875,6 @@ compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; #address-cells = <1>; @@ -889,7 +888,6 @@ compatible = "atmel,hsmci"; reg = <0xfffd0000 0x600>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; dma-names = "rxtx"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index a3a5c82d9f29..09b29126f60d 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -99,6 +99,7 @@ &pinctrl_board_mmc0 &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; @@ -112,6 +113,7 @@ &pinctrl_board_mmc1 &pinctrl_mmc1_slot0_clk_cmd_dat0 &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index a5a1838c2524..79076e4ed1e0 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -651,7 +651,6 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; - pinctrl-names = "default"; clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "mci_clk"; #address-cells = <1>; @@ -665,7 +664,6 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; - pinctrl-names = "default"; clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; clock-names = "mci_clk"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index c934928742b0..6d1264de6060 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -56,6 +56,7 @@ &pinctrl_board_mmc0 &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { @@ -70,6 +71,7 @@ &pinctrl_board_mmc1 &pinctrl_mmc1_slot0_clk_cmd_dat0 &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 4dfe0f15d7bd..f52f5eea430a 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -68,6 +68,7 @@ &pinctrl_board_mmc &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; -- cgit v1.2.3 From 996710a8956e43227399d140ef54c72da6532443 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 31 Aug 2020 19:11:28 +0200 Subject: ARM: dts: at91: add unit-address to memory node The memory node requires a unit-address, add it. Signed-off-by: Alexandre Belloni Reviewed-by: Nicolas Ferre Link: https://lore.kernel.org/r/20200831171129.3886857-7-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/animeo_ip.dts | 2 +- arch/arm/boot/dts/at91-ariag25.dts | 2 +- arch/arm/boot/dts/at91-ariettag25.dts | 2 +- arch/arm/boot/dts/at91-cosino.dtsi | 2 +- arch/arm/boot/dts/at91-foxg20.dts | 2 +- arch/arm/boot/dts/at91-kizbox.dts | 2 +- arch/arm/boot/dts/at91-kizbox2-common.dtsi | 2 +- arch/arm/boot/dts/at91-kizboxmini-common.dtsi | 2 +- arch/arm/boot/dts/at91-linea.dtsi | 2 +- arch/arm/boot/dts/at91-qil_a9260.dts | 2 +- arch/arm/boot/dts/at91-sam9_l9260.dts | 2 +- arch/arm/boot/dts/at91-sama5d3_xplained.dts | 2 +- arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi | 2 +- arch/arm/boot/dts/at91-sama5d4_xplained.dts | 2 +- arch/arm/boot/dts/at91-sama5d4ek.dts | 2 +- arch/arm/boot/dts/at91-som60.dtsi | 2 +- arch/arm/boot/dts/at91-vinco.dts | 2 +- arch/arm/boot/dts/at91-wb45n.dtsi | 2 +- arch/arm/boot/dts/at91-wb50n.dtsi | 2 +- arch/arm/boot/dts/at91rm9200.dtsi | 2 +- arch/arm/boot/dts/at91rm9200ek.dts | 2 +- arch/arm/boot/dts/at91sam9260.dtsi | 2 +- arch/arm/boot/dts/at91sam9260ek.dts | 2 +- arch/arm/boot/dts/at91sam9261.dtsi | 2 +- arch/arm/boot/dts/at91sam9261ek.dts | 2 +- arch/arm/boot/dts/at91sam9263.dtsi | 2 +- arch/arm/boot/dts/at91sam9263ek.dts | 2 +- arch/arm/boot/dts/at91sam9g20.dtsi | 2 +- arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 2 +- arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 +- arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- arch/arm/boot/dts/at91sam9n12ek.dts | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/at91sam9rlek.dts | 2 +- arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- arch/arm/boot/dts/at91sam9x5cm.dtsi | 2 +- arch/arm/boot/dts/ethernut5.dts | 2 +- arch/arm/boot/dts/mpa1600.dts | 2 +- arch/arm/boot/dts/pm9g45.dts | 2 +- arch/arm/boot/dts/sam9x60.dtsi | 2 +- arch/arm/boot/dts/sama5d2.dtsi | 2 +- arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d3xcm.dtsi | 2 +- arch/arm/boot/dts/sama5d3xcm_cmp.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- arch/arm/boot/dts/tny_a9260_common.dtsi | 2 +- arch/arm/boot/dts/tny_a9263.dts | 2 +- arch/arm/boot/dts/usb_a9260.dts | 2 +- arch/arm/boot/dts/usb_a9263.dts | 2 +- arch/arm/boot/dts/usb_a9g20_common.dtsi | 2 +- 51 files changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 6d7fc9c6c6e0..7da718abbd85 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -26,7 +26,7 @@ stdout-path = &usart2; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index 2ef39ecbda18..713d18f80356 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -22,7 +22,7 @@ bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; }; - memory { + memory@20000000 { /* 128 MB, change this for 256 MB revision */ reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/at91-ariettag25.dts index 2eb494f49078..2c52a71752c2 100644 --- a/arch/arm/boot/dts/at91-ariettag25.dts +++ b/arch/arm/boot/dts/at91-ariettag25.dts @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi index 91e386d4872f..ee0f5da6d819 100644 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -20,7 +20,7 @@ bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index c0509c4e5138..7edf057047f8 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -17,7 +17,7 @@ bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 7d938ccf71b0..7add151f6250 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -18,7 +18,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi index af38253a6e7a..25f761065106 100644 --- a/arch/arm/boot/dts/at91-kizbox2-common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox2-common.dtsi @@ -17,7 +17,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi index fddf267b2d17..d37724c10695 100644 --- a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi +++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi @@ -16,7 +16,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi index 41f163955b1e..533a440d5583 100644 --- a/arch/arm/boot/dts/at91-linea.dtsi +++ b/arch/arm/boot/dts/at91-linea.dtsi @@ -13,7 +13,7 @@ compatible = "axentia,linea", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; }; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index ee8525d5a5da..969d990767fc 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -14,7 +14,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts index f475c0b0f1de..1e2a28c2f365 100644 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 7abf555cd2fe..cf13632edd44 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index 0be184a870eb..710cb72bda5a 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -9,7 +9,7 @@ model = "Aries/DENX MA5D4"; compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; - memory { + memory@20000000 { reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index 924d9491780d..e5974a17374c 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 0cc1cff13e46..fe432b6b7e95 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/at91-som60.dtsi b/arch/arm/boot/dts/at91-som60.dtsi index 241682a207c5..39474a112b16 100644 --- a/arch/arm/boot/dts/at91-som60.dtsi +++ b/arch/arm/boot/dts/at91-som60.dtsi @@ -16,7 +16,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts index 15050fdd479d..a51a3372afa1 100644 --- a/arch/arm/boot/dts/at91-vinco.dts +++ b/arch/arm/boot/dts/at91-vinco.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/at91-wb45n.dtsi index e3d98306ee3a..430c75358086 100644 --- a/arch/arm/boot/dts/at91-wb45n.dtsi +++ b/arch/arm/boot/dts/at91-wb45n.dtsi @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi index 1487b893cfa7..74b249bb6351 100644 --- a/arch/arm/boot/dts/at91-wb50n.dtsi +++ b/arch/arm/boot/dts/at91-wb50n.dtsi @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; }; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 0ea0aff2a024..d1181ead18e5 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -49,7 +49,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index 1e0bf5afa913..e1ef4e44e663 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index b07578ff214c..82c5d7fd9811 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -46,7 +46,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index 657dc3a420d6..d3446e42b598 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -16,7 +16,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 980cc308fec5..7adc36ca8a46 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -43,7 +43,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index c4ef74fea97c..beed819609e8 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index aea70a32511c..fe45d96239c9 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -45,7 +45,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index bf89cb2bbdd9..71f60576761a 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 86b4e943089a..708e1646b7f4 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -11,7 +11,7 @@ model = "Atmel AT91SAM9G20 family SoC"; compatible = "atmel,at91sam9g20"; - memory { + memory@20000000 { reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index c65651549692..6e6e672c0b86 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -13,7 +13,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 1e1b7490ee0a..19fc748a87c5 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -51,7 +51,7 @@ }; }; - memory { + memory@70000000 { device_type = "memory"; reg = <0x70000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 09b29126f60d..9734667abbfc 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@70000000 { reg = <0x70000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 5c27ead05284..0785389f5507 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -47,7 +47,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 870b83ff6b97..2bc4e6e0a923 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index eb5bea473bc8..5653e70c84b4 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -48,7 +48,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 0de75d3c4f18..1590862f16f2 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 79076e4ed1e0..4cdb05079cc7 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -49,7 +49,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 75d2f7fd314f..cdd37f67280b 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -7,7 +7,7 @@ */ / { - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 052a52f947ce..ad7a0850252a 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -15,7 +15,7 @@ bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; }; - memory { + memory@20000000 { reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index a5c91c240db9..005c2758e229 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -11,7 +11,7 @@ model = "Phontech MPA 1600"; compatible = "phontech,mpa1600", "atmel,at91rm9200"; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index f52f5eea430a..c349fd3758a6 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -15,7 +15,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@70000000 { reg = <0x70000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 3e85c2a0d198..04ad6b956471 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -42,7 +42,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index ddd7f9b05aa2..c4aecfa4a2be 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -72,7 +72,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 4f9001188511..86137f8d2b45 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -55,7 +55,7 @@ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 65566e4b78d8..384335635792 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -14,7 +14,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi index 9d2563602cbe..5579c955f141 100644 --- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi @@ -12,7 +12,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 1aca4b462f52..04f24cf752d3 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -53,7 +53,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi index dd6957b20772..70e5635c78ed 100644 --- a/arch/arm/boot/dts/tny_a9260_common.dtsi +++ b/arch/arm/boot/dts/tny_a9260_common.dtsi @@ -10,7 +10,7 @@ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index 2820635952e3..62b7d9f9a926 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -15,7 +15,7 @@ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts index ec8cd86b260d..6cfa83921ac2 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/usb_a9260.dts @@ -16,7 +16,7 @@ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index e7a705fddda9..8a0cfbfd0c45 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -15,7 +15,7 @@ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi index adbe75024739..7d10b36db1ee 100644 --- a/arch/arm/boot/dts/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi @@ -14,7 +14,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; -- cgit v1.2.3 From 860b6d803f3d5feab4b67d500b060168a77f9a04 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 31 Aug 2020 19:11:29 +0200 Subject: ARM: dts: at91: sama5d2: add missing flexcom spi node properties SPI nodes require #address-cells and #size-cells add those properties in the flexcom spi nodes. Signed-off-by: Alexandre Belloni Reviewed-by: Nicolas Ferre Link: https://lore.kernel.org/r/20200831171129.3886857-8-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/sama5d2.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index c4aecfa4a2be..2ddc85dff8ce 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -542,6 +542,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; clock-names = "spi_clk"; dmas = <&dma0 @@ -610,6 +612,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "spi_clk"; dmas = <&dma0 @@ -817,6 +821,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "spi_clk"; dmas = <&dma0 @@ -885,6 +891,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "spi_clk"; dmas = <&dma0 @@ -954,6 +962,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "spi_clk"; dmas = <&dma0 -- cgit v1.2.3 From ba4d1c074fd7e5f5d1a5b025b510fd542fc04da5 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 24 Aug 2020 22:30:09 +0200 Subject: arm64: dts: sparx5: Add spi-nor support This add spi-nor device nodes to the Sparx5 reference boards. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200824203010.2033-6-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 16 +++++++++++ .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 32 ++++++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 32 ++++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 573309fe4582..c1eb1d661174 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -39,6 +39,22 @@ microchip,clock-delay = <10>; }; +&spi0 { + status = "okay"; + spi@0 { + compatible = "spi-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* CS0 */ + spi-flash@9 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 18a535a04368..f37b478d6534 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -38,6 +38,38 @@ }; }; +&spi0 { + status = "okay"; + spi@0 { + compatible = "spi-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* CS0 */ + spi-flash@9 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; +}; + +&spi0 { + status = "okay"; + spi@0 { + compatible = "spi-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* CS0 */ + spi-flash@9 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index d71f11a10b3d..b02b8c8ce44d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -51,6 +51,38 @@ }; }; +&spi0 { + status = "okay"; + spi@0 { + compatible = "spi-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* CS0 */ + spi-flash@9 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; +}; + +&spi0 { + status = "okay"; + spi@0 { + compatible = "spi-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* CS0 */ + spi-flash@9 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl"; -- cgit v1.2.3 From 5df50128050d01d300f28d9bca4dd89d6d24de3d Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 24 Aug 2020 22:30:10 +0200 Subject: arm64: dts: sparx5: Add spi-nand devices This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++++++ arch/arm64/boot/dts/microchip/sparx5_nand.dtsi | 31 +++++++++++++++++++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 14 +++++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb134.dts | 1 + arch/arm64/boot/dts/microchip/sparx5_pcb135.dts | 1 + 5 files changed, 67 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/sparx5_nand.dtsi diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index b7a38557fb77..3cb01c39c3c8 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -206,6 +206,26 @@ interrupts = ; #interrupt-cells = <2>; + cs1_pins: cs1-pins { + pins = "GPIO_16"; + function = "si"; + }; + + cs2_pins: cs2-pins { + pins = "GPIO_17"; + function = "si"; + }; + + cs3_pins: cs3-pins { + pins = "GPIO_18"; + function = "si"; + }; + + si2_pins: si2-pins { + pins = "GPIO_39", "GPIO_40", "GPIO_41"; + function = "si2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi new file mode 100644 index 000000000000..03f107e427d7 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +&gpio { + cs14_pins: cs14-pins { + pins = "GPIO_44"; + function = "si"; + }; +}; + +&spi0 { + pinctrl-0 = <&si2_pins>; + pinctrl-names = "default"; + spi@e { + compatible = "spi-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + reg = <14>; /* CS14 */ + spi-flash@6 { + compatible = "spi-nand"; + pinctrl-0 = <&cs14_pins>; + pinctrl-names = "default"; + reg = <0x6>; /* SPI2 */ + spi-max-frequency = <42000000>; + rx-sample-delay-ns = <7>; /* Tune for speed */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index c1eb1d661174..6b2da7c7520c 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -53,6 +53,20 @@ reg = <0x9>; /* SPI */ }; }; + spi@1 { + compatible = "spi-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* CS1 */ + spi-flash@9 { + compatible = "spi-nand"; + pinctrl-0 = <&cs1_pins>; + pinctrl-names = "default"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; }; &i2c1 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts index feee4e99ff57..45ca1af7e850 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "sparx5_pcb134_board.dtsi" +#include "sparx5_nand.dtsi" / { model = "Sparx5 PCB134 Reference Board (NAND)"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts index 20e409a9be19..647cdb38b113 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "sparx5_pcb135_board.dtsi" +#include "sparx5_nand.dtsi" / { model = "Sparx5 PCB135 Reference Board (NAND)"; -- cgit v1.2.3 From 3a3a5a59ee622e7062a9b05ebed83b4dfc46f406 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 3 Sep 2020 21:14:37 +0200 Subject: ARM: dts: exynos: Align OPP table name with dt-schema Device tree nodes should have hyphens instead of underscores. This is also expected by the bindings. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200903191438.12781-5-krzk@kernel.org --- arch/arm/boot/dts/exynos4412.dtsi | 16 ++++++++-------- arch/arm/boot/dts/exynos5250.dtsi | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index c74b1be12671..e76881dc0014 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -76,7 +76,7 @@ }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table0 { compatible = "operating-points-v2"; opp-shared; @@ -402,7 +402,7 @@ status = "disabled"; }; - bus_dmc_opp_table: opp_table1 { + bus_dmc_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-shared; @@ -429,7 +429,7 @@ }; }; - bus_acp_opp_table: opp_table2 { + bus_acp_opp_table: opp-table2 { compatible = "operating-points-v2"; opp-shared; @@ -495,7 +495,7 @@ status = "disabled"; }; - bus_leftbus_opp_table: opp_table3 { + bus_leftbus_opp_table: opp-table3 { compatible = "operating-points-v2"; opp-shared; @@ -518,7 +518,7 @@ }; }; - bus_display_opp_table: opp_table4 { + bus_display_opp_table: opp-table4 { compatible = "operating-points-v2"; opp-shared; @@ -530,7 +530,7 @@ }; }; - bus_fsys_opp_table: opp_table5 { + bus_fsys_opp_table: opp-table5 { compatible = "operating-points-v2"; opp-shared; @@ -542,7 +542,7 @@ }; }; - bus_peri_opp_table: opp_table6 { + bus_peri_opp_table: opp-table6 { compatible = "operating-points-v2"; opp-shared; @@ -734,7 +734,7 @@ "pmu"; operating-points-v2 = <&gpu_opp_table>; - gpu_opp_table: opp_table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index e09db3cecbff..bd2d8835dd36 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -330,7 +330,7 @@ power-domains = <&pd_g3d>; status = "disabled"; - gpu_opp_table: gpu-opp-table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { -- cgit v1.2.3 From fceeb3f69e5d04353758b03d94da4bec99ffaff9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 3 Sep 2020 21:14:38 +0200 Subject: arm64: dts: exynos: Align OPP table name with dt-schema Device tree nodes should have hyphens instead of underscores. This is also expected by the bindings. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200903191438.12781-6-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 3933d806a9f6..8eb4576da8f3 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1087,7 +1087,7 @@ operating-points-v2 = <&gpu_opp_table>; status = "disabled"; - gpu_opp_table: opp_table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { -- cgit v1.2.3 From bb4e9860686b23e86427d1adbeec8703a19e0c04 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:36 +0200 Subject: ARM: dts: s5pv210: move fixed regulators under root node in Aquila The fixed regulators are kept under dedicated "regulators" node but this causes multiple dtschema warnings: regulators: $nodename:0: 'regulators' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' regulators: #size-cells:0:0: 0 is not one of [1, 2] regulators: fixed-regulator@0:reg:0: [0] is too short regulators: fixed-regulator@1:reg:0: [1] is too short regulators: fixed-regulator@2:reg:0: [2] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-21-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aquila.dts | 47 +++++++++++++++--------------------- 1 file changed, 19 insertions(+), 28 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 25d4ab4a52c5..28e9e81bb2d1 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -40,36 +40,27 @@ clock-frequency = <32768>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vtf_reg: fixed-regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vtf_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "V_TF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - pda_reg: fixed-regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - reg = <1>; - }; + pda_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - bat_reg: fixed-regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - reg = <2>; - }; + bat_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "V_BAT"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; }; i2c_pmic: i2c-pmic { -- cgit v1.2.3 From 8fbc73dc57e13e5733b4a555b0c7d9dbb1a1fcd7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:37 +0200 Subject: ARM: dts: s5pv210: move fixed regulators under root node in Goni The fixed regulators are kept under dedicated "regulators" node but this causes multiple dtschema warnings: regulators: $nodename:0: 'regulators' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' regulators: #size-cells:0:0: 0 is not one of [1, 2] regulators: fixed-regulator@0:reg:0: [0] is too short regulators: fixed-regulator@1:reg:0: [1] is too short regulators: fixed-regulator@2:reg:0: [2] is too short regulators: fixed-regulator@3:reg:0: [3] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-22-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-goni.dts | 64 ++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index 20f1c2773805..eec6531e6ef8 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -42,46 +42,36 @@ clock-frequency = <32768>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vtf_reg: fixed-regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - reg = <0>; - gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vtf_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "V_TF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - pda_reg: fixed-regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - reg = <1>; - }; + pda_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - bat_reg: fixed-regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - reg = <2>; - }; + bat_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "V_BAT"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; - tsp_reg: fixed-regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "TSP_VDD"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - reg = <3>; - gpio = <&gpj1 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + tsp_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "TSP_VDD"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpj1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; }; i2c_pmic: i2c-pmic { -- cgit v1.2.3 From ddeb5e7d3da885246d1f27e6ed03e4d38eacdb51 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:38 +0200 Subject: ARM: dts: s5pv210: replace deprecated "gpios" i2c-gpio property in Aquila "gpios" property is deprecated. Update the Aquila DTS to fix dtbs_checks warnings like: i2c-pmic: 'sda-gpios' is a required property i2c-pmic: 'scl-gpios' is a required property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-23-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aquila.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 28e9e81bb2d1..8e57e5a1f0c5 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -65,8 +65,8 @@ i2c_pmic: i2c-pmic { compatible = "i2c-gpio"; - gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpj4 3 GPIO_ACTIVE_HIGH>; /* scl */ + sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 6995a4c46331e39646e1bbe4418acf5cf00ef536 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:39 +0200 Subject: ARM: dts: s5pv210: replace deprecated "gpios" i2c-gpio property in Goni "gpios" property is deprecated. Update the Goni DTS to fix dtbs_checks warnings like: i2c-pmic: 'sda-gpios' is a required property i2c-pmic: 'scl-gpios' is a required property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-24-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-goni.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index eec6531e6ef8..ad8d5d2fa32d 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -76,8 +76,8 @@ i2c_pmic: i2c-pmic { compatible = "i2c-gpio"; - gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpj4 3 GPIO_ACTIVE_HIGH>; /* scl */ + sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 02ae4a0ed14d94709a707dfb02b0a4a4dfcced59 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 15 Sep 2020 12:54:20 +0530 Subject: arm64: dts: qcom: sm8250: Add cpufreq hw node Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8250 SoCs. Signed-off-by: Bjorn Andersson Signed-off-by: Manivannan Sadhasivam Acked-by: Viresh Kumar Reviewed-by: Amit Kucheria Link: https://lore.kernel.org/r/20200915072423.18437-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f49a4a1651e2..357e4bfba70c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -89,6 +89,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -104,6 +105,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -116,6 +118,7 @@ reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -128,6 +131,7 @@ reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -140,6 +144,7 @@ reg = <0x0 0x400>; enable-method = "psci"; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -152,6 +157,7 @@ reg = <0x0 0x500>; enable-method = "psci"; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -165,6 +171,7 @@ reg = <0x0 0x600>; enable-method = "psci"; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -177,6 +184,7 @@ reg = <0x0 0x700>; enable-method = "psci"; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -2316,6 +2324,20 @@ #interconnect-cells = <1>; }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>, + <0 0x18593000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", + "freq-domain2"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; timer { -- cgit v1.2.3 From a4387f2973a0562c9432e79f3b7eb33de59ee045 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 16 Sep 2020 10:49:51 +0100 Subject: arm64: tegra: Add label properties for EEPROMs Populate the label property for the AT24 EEPROMs on the various Jetson platforms. Note that the name 'module' is used to identify the EEPROM on the processor module board and the name 'system' is used to identify the EEPROM on the main base board (which is sometimes referred to as the carrier board). Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 1 + arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 1 + arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 1 + arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 ++ 7 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 802b8c52489a..381a84912ba8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -222,6 +222,7 @@ compatible = "atmel,24c02"; reg = <0x57>; + label = "system"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 53d92fdd7f06..fd9177447711 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -173,6 +173,7 @@ compatible = "atmel,24c02"; reg = <0x50>; + label = "module"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 0ea0bd83cb8e..d71b7a1140fe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -64,6 +64,7 @@ compatible = "atmel,24c02"; reg = <0x50>; + label = "module"; vcc-supply = <&vdd_1v8ls>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 4d8a0e10250f..54d057beec59 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -28,6 +28,7 @@ compatible = "atmel,24c02"; reg = <0x56>; + label = "system"; vcc-supply = <&vdd_1v8ls>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 85ee7e6b71ac..6077d572d828 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -273,6 +273,7 @@ compatible = "atmel,24c02"; reg = <0x50>; + label = "module"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 56adf287a82c..4c9c2a054642 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -86,6 +86,7 @@ compatible = "atmel,24c02"; reg = <0x57>; + label = "system"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index ba892cd4b5a9..859241db4b4d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -144,6 +144,7 @@ compatible = "atmel,24c02"; reg = <0x50>; + label = "module"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; @@ -155,6 +156,7 @@ compatible = "atmel,24c02"; reg = <0x57>; + label = "system"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; -- cgit v1.2.3 From 2b9ee384b450d4b8b7a44806f382e43f61a47a4c Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 16 Sep 2020 10:49:52 +0100 Subject: arm64: tegra: Populate EEPROMs for Jetson Xavier NX Populate the EEPROMs that are present on the Jetson Xavier NX developer platform. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts | 14 ++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi | 16 ++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts index c1c589805d6b..7f97b34216a0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts @@ -27,6 +27,20 @@ status = "okay"; }; + i2c@3160000 { + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + + label = "system"; + vcc-supply = <&vdd_1v8>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + hda@3510000 { nvidia,model = "jetson-xavier-nx-hda"; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi index 10cb836aea7e..a2893be80507 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi @@ -58,6 +58,22 @@ status = "okay"; }; + i2c@3160000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + label = "module"; + vcc-supply = <&vdd_1v8ls>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + /* SDMMC1 (SD/MMC) */ mmc@3400000 { status = "okay"; -- cgit v1.2.3 From f5ddee15086be2efaaa218aa5731f5afebf05835 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:39 +0200 Subject: dt-bindings: misc: tegra-apbmisc: Add missing compatible strings The compatible string for the Tegra210 APBMISC block was missing from the bindings. Add it and while at it, rewrite the description of the compatible string to make it clearer. Signed-off-by: Thierry Reding --- .../devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index 4556359c5876..83f6a251ba3e 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -1,10 +1,13 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block +NVIDIA Tegra APBMISC block Required properties: -- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30, - must be "nvidia,tegra30-apbmisc". Otherwise, must contain - "nvidia,-apbmisc", plus one of the above, where is tegra114, - tegra124, tegra132. +- compatible: Must be: + - Tegra20: "nvidia,tegra20-apbmisc" + - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc" + - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc" + - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" + - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" + - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc" - reg: Should contain 2 entries: the first entry gives the physical address and length of the registers which contain revision and debug features. The second entry gives the physical address and length of the -- cgit v1.2.3 From 24989476352599c68e91eb601a6751fd250a458f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:40 +0200 Subject: dt-bindings: misc: tegra186-misc: Add missing compatible string Add the missing compatible string for the Tegra194 MISC block. Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt index 892ba4384abc..111dfac70ea7 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt @@ -1,11 +1,12 @@ -NVIDIA Tegra186 MISC register block +NVIDIA Tegra186 (and later) MISC register block -The MISC register block found on Tegra186 SoCs contains registers that can be -used to identify a given chip and various strapping options. +The MISC register block found on Tegra186 and later SoCs contains registers +that can be used to identify a given chip and various strapping options. Required properties: - compatible: Must be: - Tegra186: "nvidia,tegra186-misc" + - Tegra194: "nvidia,tegra194-misc" - reg: Should contain 2 entries: The first entry gives the physical address and length of the register region which contains revision and debug features. The second entry specifies the physical address and length -- cgit v1.2.3 From 2778aca0b429dff1925c882da6ec4170ff25e971 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:41 +0200 Subject: dt-bindings: misc: tegra186-misc: Add Tegra234 support The MISC block found on Tegra234 is mostly similar to the one on Tegra194 but supports slightly different register sets that make it incompatible. Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt index 111dfac70ea7..43d777ed8316 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt @@ -7,6 +7,7 @@ Required properties: - compatible: Must be: - Tegra186: "nvidia,tegra186-misc" - Tegra194: "nvidia,tegra194-misc" + - Tegra234: "nvidia,tegra234-misc" - reg: Should contain 2 entries: The first entry gives the physical address and length of the register region which contains revision and debug features. The second entry specifies the physical address and length -- cgit v1.2.3 From 97cb586ad2437a540c730d710391468368dc14c3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:42 +0200 Subject: dt-bindings: tegra: Add Tegra234 VDK compatible The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index e0b3debaee9e..85006ca503a7 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -119,3 +119,7 @@ properties: items: - const: nvidia,p3509-0000+p3668-0000 - const: nvidia,tegra194 + - items: + - enum: + - nvidia,tegra234-vdk + - const: nvidia,tegra234 -- cgit v1.2.3 From ba81973044b4cb1fd299be3651e4f6b323e22e71 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:43 +0200 Subject: dt-bindings: fuse: tegra: Add Tegra234 support The Tegra234 FUSE block is very similar to that on prior chips but not completely compatible. Document the new compatible string. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt index 2aaf661c04ee..b109911669e4 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt @@ -7,6 +7,7 @@ Required properties: For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". + For Tegra234 must contain "nvidia,tegra234-efuse". Details: nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data due to a hardware bug. Tegra20 also lacks certain information which is -- cgit v1.2.3 From ac82240510b319d7d85a4da34816a2a14c530507 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:44 +0200 Subject: dt-bindings: tegra: pmc: Add Tegra234 support The PMC found on Tegra234 is mostly similar to the one on Tegra194 but supports slightly different I/O pads and wake events. Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt index 2d89cdc39eb0..576462fae27f 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Should contain one of the following: - "nvidia,tegra186-pmc": for Tegra186 - "nvidia,tegra194-pmc": for Tegra194 + - "nvidia,tegra234-pmc": for Tegra234 - reg: Must contain an (offset, length) pair of the register set for each entry in reg-names. - reg-names: Must include the following entries: @@ -11,7 +12,7 @@ Required properties: - "wake" - "aotag" - "scratch" - - "misc" (Only for Tegra194) + - "misc" (Only for Tegra194 and later) Optional properties: - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. -- cgit v1.2.3 From e9b641030d916b60bfbca8fd081820a8757bfc16 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 14 Aug 2020 00:34:01 +0300 Subject: dt-bindings: power: supply: Add device-tree binding for Summit SMB3xx Summit SMB3xx series is a Programmable Switching Li+ Battery Charger. This patch adds device-tree binding for Summit SMB345, SMB347 and SMB358 chargers. Signed-off-by: David Heidelberg Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../power/supply/summit,smb347-charger.yaml | 152 +++++++++++++++++++++ include/dt-bindings/power/summit,smb347-charger.h | 19 +++ 2 files changed, 171 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml create mode 100644 include/dt-bindings/power/summit,smb347-charger.h diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml new file mode 100644 index 000000000000..193a23af2007 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/supply/summit,smb347-charger.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Battery charger driver for SMB345, SMB347 and SMB358 + +maintainers: + - David Heidelberg + - Dmitry Osipenko + +properties: + compatible: + enum: + - summit,smb345 + - summit,smb347 + - summit,smb358 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + monitored-battery: + description: phandle to the battery node + $ref: /schemas/types.yaml#/definitions/phandle + + summit,enable-usb-charging: + type: boolean + description: Enable charging through USB. + + summit,enable-otg-charging: + type: boolean + description: Provide power for USB OTG + + summit,enable-mains-charging: + type: boolean + description: Enable charging through mains + + summit,enable-charge-control: + description: Enable charging control + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_CHG_ENABLE_SW SW (I2C interface) + - 1 # SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW Pin control (Active Low) + - 2 # SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH Pin control (Active High) + + summit,fast-voltage-threshold-microvolt: + description: Voltage threshold to transit to fast charge mode (in uV) + minimum: 2400000 + maximum: 3000000 + + summit,mains-current-limit-microamp: + description: Maximum input current from AC/DC input (in uA) + + summit,usb-current-limit-microamp: + description: Maximum input current from USB input (in uA) + + summit,charge-current-compensation-microamp: + description: Charge current compensation (in uA) + + summit,chip-temperature-threshold-celsius: + description: Chip temperature for thermal regulation in °C. + enum: [100, 110, 120, 130] + + summit,soft-compensation-method: + description: Soft temperature limit compensation method + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_SOFT_TEMP_COMPENSATE_NONE Compensation none + - 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation + - 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation + +allOf: + - if: + properties: + compatible: + enum: + - summit,smb345 + - summit,smb358 + + then: + properties: + summit,mains-current-limit-microamp: + enum: [ 300000, 500000, 700000, 1000000, + 1500000, 1800000, 2000000] + + summit,usb-current-limit-microamp: + enum: [ 300000, 500000, 700000, 1000000, + 1500000, 1800000, 2000000] + + summit,charge-current-compensation-microamp: + enum: [200000, 450000, 600000, 900000] + + else: + properties: + summit,mains-current-limit-microamp: + enum: [ 300000, 500000, 700000, 900000, 1200000, + 1500000, 1800000, 2000000, 2200000, 2500000] + + summit,usb-current-limit-microamp: + enum: [ 300000, 500000, 700000, 900000, 1200000, + 1500000, 1800000, 2000000, 2200000, 2500000] + + summit,charge-current-compensation-microamp: + enum: [250000, 700000, 900000, 1200000] + +required: + - compatible + - reg + +anyOf: + - required: + - summit,enable-usb-charging + - required: + - summit,enable-otg-charging + - required: + - summit,enable-mains-charging + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@7f { + compatible = "summit,smb347"; + reg = <0x7f>; + + summit,enable-charge-control = ; + summit,chip-temperature-threshold-celsius = <110>; + summit,mains-current-limit-microamp = <2000000>; + summit,usb-current-limit-microamp = <500000>; + summit,enable-usb-charging; + summit,enable-mains-charging; + + monitored-battery = <&battery>; + }; + }; + + battery: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <1800000>; + operating-range-celsius = <0 45>; + alert-celsius = <3 42>; + }; diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h new file mode 100644 index 000000000000..d918bf321a71 --- /dev/null +++ b/include/dt-bindings/power/summit,smb347-charger.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later or MIT) */ +/* + * Author: David Heidelberg + */ + +#ifndef _DT_BINDINGS_SMB347_CHARGER_H +#define _DT_BINDINGS_SMB347_CHARGER_H + +/* Charging compensation method */ +#define SMB3XX_SOFT_TEMP_COMPENSATE_NONE 0 +#define SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT 1 +#define SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE 2 + +/* Charging enable control */ +#define SMB3XX_CHG_ENABLE_SW 0 +#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1 +#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2 + +#endif -- cgit v1.2.3 From 110a5803424255b876e25b28093cd13d86d0ccd2 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 6 Sep 2020 22:00:06 +0300 Subject: ARM: tegra: nexus7: Add aliases for MMC MMC core now supports binding to a specific ID, which is very handy for embedded devices, like Nexus 7, because MMC ID may change depending on kernel version or configuration which affects MMC driver probe order. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 3922517145e7..9999e1afd465 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -10,6 +10,9 @@ / { aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* WiFi */ + rtc0 = &pmic; rtc1 = "/rtc@7000e000"; @@ -936,7 +939,7 @@ power-off-delay-us = <300>; }; - mmc@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; #address-cells = <1>; @@ -960,7 +963,7 @@ }; }; - mmc@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; vmmc-supply = <&vcore_emmc>; -- cgit v1.2.3 From 21806bb0a1dc742c5d2b19edcd7b3410d67ec895 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 6 Sep 2020 22:00:07 +0300 Subject: ARM: tegra: acer-a500: Add aliases for MMC MMC core now supports binding to a specific ID, which is very handy for embedded devices, like Acer A500, because MMC ID may change depending on kernel version or configuration which affects MMC driver probe order. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2d683c9a1a5d..fc930c93981d 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -14,6 +14,10 @@ compatible = "acer,picasso", "nvidia,tegra20"; aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + mmc2 = &sdmmc1; /* WiFi */ + rtc0 = &pmic; rtc1 = "/rtc@7000e000"; @@ -720,7 +724,7 @@ power-off-delay-us = <300>; }; - mmc@c8000000 { + sdmmc1: mmc@c8000000 { status = "okay"; #address-cells = <1>; @@ -745,7 +749,7 @@ }; }; - mmc@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -754,7 +758,7 @@ vqmmc-supply = <&vdd_3v3_sys>; }; - mmc@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; vmmc-supply = <&vcore_emmc>; -- cgit v1.2.3 From 878fd50925f9e88b620d4a4a173647a487adcb42 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 6 Sep 2020 22:00:08 +0300 Subject: ARM: tegra: acer-a500: Remove atmel,cfg_name property This property was supposed to be upstreamed, but it was NAKed recently in a favor to a better approach of firmware loading. It also turned out that the firmware loading isn't really necessary because it's stored in a non-volatile memory inside of the touchscreen controller and previously the FW loading was needed in order to get touchscreen working, but it actually was a TS driver problem which is resolved now. Hence remove the unsupported property. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index fc930c93981d..d380ae1f9437 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -435,8 +435,6 @@ compatible = "atmel,maxtouch"; reg = <0x4c>; - atmel,cfg_name = "maxtouch-acer-iconia-tab-a500.cfg"; - interrupt-parent = <&gpio>; interrupts = ; -- cgit v1.2.3 From eb885f5ef73b1716d34f872ca37ac0b1a6e8cf2e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 23 Aug 2020 17:47:22 +0300 Subject: ARM: tegra: acer-a500: Correct PINCTRL configuration The low-power-mode drive was set to DIV_4 for some of PINCTRL groups, while these groups should use DIV_1. This patch fixes the wrong PINCTRL configurations and adds a full drive-setup for the changed configs, just for completeness since the added values match the default configuration. Now WiFi SDIO communication works properly using legacy signaling mode if SDIO BUS clocked at 50MHz, which is a maximum SDIO clock rate on Tegra20. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index d380ae1f9437..bc7c1d082828 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -318,16 +318,24 @@ nvidia,pins = "drive_ddc", "drive_vi1", "drive_sdio1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; nvidia,schmitt = ; - nvidia,low-power-mode = ; + nvidia,high-speed-mode = ; + nvidia,low-power-mode = ; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; }; drive_dbg { nvidia,pins = "drive_dbg", "drive_vi2", "drive_at1", "drive_ao1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; nvidia,schmitt = ; - nvidia,low-power-mode = ; + nvidia,high-speed-mode = ; + nvidia,low-power-mode = ; nvidia,slew-rate-rising = ; nvidia,slew-rate-falling = ; }; -- cgit v1.2.3 From a252efadf3e7ffa8f5793cb431f35bb95bdc4795 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 23 Aug 2020 17:47:23 +0300 Subject: ARM: tegra: acer-a500: Set WiFi MMC clock rate to 50 MHz Previously 50MHz clock rate didn't work because of the wrong PINCTRL configuration used for SDIO pins. Now the PINCTRL config is corrected and the MMC clock rate could be bumped safely to 50MHz, increasing WiFi TX throughput by 20 Mbit/s and allowing to hit the maximum 40 Mbit/s. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index bc7c1d082828..9489eedcf0c9 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -736,7 +736,7 @@ #address-cells = <1>; #size-cells = <0>; - max-frequency = <25000000>; + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>; non-removable; -- cgit v1.2.3 From 98e710a01738cc99fce0830e4949710bb10fd4ee Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 23 Aug 2020 17:47:24 +0300 Subject: ARM: tegra: acer-a500: Use PLLC for WiFi MMC clock parent The default parent for all MMCs is PLLP, which is running at 216 MHz on Tegra20 and 50 MHz clock can't be derived from PLLP. The maximum SDIO clock rate is 50 MHz, but this rate isn't achievable using PLLP. Let's switch the WiFi MMC clock parent to PLLC in order to get true 50 MHz. This patch doesn't fix any problems, it's just a minor improvement. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 9489eedcf0c9..a0b829738e8f 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -736,6 +736,10 @@ #address-cells = <1>; #size-cells = <0>; + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>; -- cgit v1.2.3 From 17110cbbef701b56136aabaaab5652b9ea4618a0 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 23 Aug 2020 17:47:25 +0300 Subject: ARM: tegra: nexus7: Use PLLC for WiFi MMC clock parent The default parent for all MMCs is PLLP, which is running at 408 MHz on Tegra30 and 50 MHz clock can't be derived from PLLP. The maximum SDIO clock rate is 50 MHz, but this rate isn't achievable using PLLP. Let's switch the WiFi MMC clock parent to PLLC in order to get true 50 MHz. This patch doesn't fix any problems, it's just a minor improvement. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 9999e1afd465..bca77ee33c74 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -945,6 +945,11 @@ #address-cells = <1>; #size-cells = <0>; + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>; non-removable; -- cgit v1.2.3 From c82ef94b3a2105482deebc37156d682f194d067e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Fri, 14 Aug 2020 03:21:38 +0300 Subject: ARM: tegra: nexus7: Add touchscreen Nexus 7 2012 has Elantech EKTF3624 touchscreen, this patch adds TS node to the device-tree. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index bca77ee33c74..a84b8e3f71f2 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -839,6 +839,24 @@ i2c@7000c400 { clock-frequency = <400000>; status = "okay"; + + touchscreen@10 { + compatible ="elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vcc_3v3_ts>; + vccio-supply = <&vcc_3v3_ts>; + + touchscreen-size-x = <2112>; + touchscreen-size-y = <1280>; + touchscreen-swapped-x-y; + touchscreen-inverted-x; + }; }; i2c@7000c500 { -- cgit v1.2.3 From c2ef3aa464a70f73f4fc763e6f54f689c2ee6d6a Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 14 Aug 2020 00:34:09 +0300 Subject: ARM: tegra: nexus7: Add SMB347 battery charger SMB347 is a battery charger controller which is found on the Nexus 7 device. Signed-off-by: David Heidelberg Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../dts/tegra30-asus-nexus7-grouper-common.dtsi | 24 +++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index a84b8e3f71f2..88ca03f57b3b 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include #include "tegra30.dtsi" @@ -922,9 +923,24 @@ #thermal-sensor-cells = <1>; }; - battery@55 { + fuel-gauge@55 { compatible = "ti,bq27541"; reg = <0x55>; + power-supplies = <&power_supply>; + monitored-battery = <&battery_cell>; + }; + + power_supply: charger@6a { + compatible = "summit,smb347"; + reg = <0x6a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + summit,enable-charge-control = ; + summit,enable-usb-charging; + + monitored-battery = <&battery_cell>; }; }; @@ -1019,6 +1035,12 @@ default-brightness-level = <15>; }; + battery_cell: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <1800000>; + operating-range-celsius = <0 45>; + }; + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ clk32k_in: clock@0 { compatible = "fixed-clock"; -- cgit v1.2.3 From a770df83d85eca56c7e842e9ecbdc5fe91701958 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 25 Aug 2020 19:35:23 +0200 Subject: ARM: dts: sun8i: r40: Add video engine node Allwinner R40 SoC has a video engine. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200825173523.1289379-6-jernej.skrabec@siol.net --- arch/arm/boot/dts/sun8i-r40.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 0c7526365896..7907569e7b5c 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -273,6 +273,17 @@ status = "disabled"; }; + video-codec@1c0e000 { + compatible = "allwinner,sun8i-r40-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-r40-mmc", "allwinner,sun50i-a64-mmc"; -- cgit v1.2.3 From 44967e8182e6265158d769f56993870aa08e800d Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 25 Jul 2020 20:25:55 -0500 Subject: ARM: dts: sun8i: a33: Update codec widget names The sun8i-codec driver introduced a new set of DAPM widgets that more accurately describe the hardware topology. Update the various device trees to use the new widget names. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200726012557.38282-6-samuel@sholland.org --- arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 4 ++-- arch/arm/boot/dts/sun8i-a33.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts index 3d78169cdeed..a1953b2872d0 100644 --- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -194,8 +194,8 @@ "Headphone", "Headphone Jack"; /* Board level routing. First 2 routes copied from SoC level */ simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", + "Left DAC", "DACL", + "Right DAC", "DACR", "HP", "HPCOM", "Headphone Jack", "HP", "MIC1", "Microphone Jack", diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index cfd3858afb3e..c458f5fb124f 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -189,8 +189,8 @@ simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right"; + "Left DAC", "DACL", + "Right DAC", "DACR"; status = "disabled"; simple-audio-card,cpu { -- cgit v1.2.3 From 631e6a353060981675cc15d71417e3379fb414e2 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 25 Jul 2020 20:25:56 -0500 Subject: arm64: dts: allwinner: a64: Update codec widget names The sun8i-codec driver introduced a new set of DAPM widgets that more accurately describe the hardware topology. Update the various device trees to use the new widget names. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200726012557.38282-7-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++---- 9 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 883f217efb81..3ea5182ca489 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -331,10 +331,10 @@ "Microphone", "Microphone Jack", "Microphone", "Onboard Microphone"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "Left DAC", "DACL", + "Right DAC", "DACR", + "ADCL", "Left ADC", + "ADCR", "Right ADC", "Headphone Jack", "HP", "MIC2", "Microphone Jack", "Onboard Microphone", "MBIAS", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index fde9c7a99b17..d894ec5fa8a1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -330,10 +330,10 @@ "Microphone", "Microphone Jack", "Microphone", "Onboard Microphone"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "Left DAC", "DACL", + "Right DAC", "DACR", + "ADCL", "Left ADC", + "ADCR", "Right ADC", "Headphone Jack", "HP", "MIC2", "Microphone Jack", "Onboard Microphone", "MBIAS", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 2165f238af13..329cf276561e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -261,11 +261,11 @@ simple-audio-card,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", + "Left DAC", "DACL", + "Right DAC", "DACR", "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "ADCL", "Left ADC", + "ADCR", "Right ADC", "MIC2", "Microphone Jack"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 64b1c54f87c0..896f34fd9fc3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -374,15 +374,15 @@ "Headphone", "Headphone Jack", "Speaker", "Internal Speaker"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", + "Left DAC", "DACL", + "Right DAC", "DACR", "Speaker Amp INL", "LINEOUT", "Speaker Amp INR", "LINEOUT", "Internal Speaker", "Speaker Amp OUTL", "Internal Speaker", "Speaker Amp OUTR", "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "ADCL", "Left ADC", + "ADCR", "Right ADC", "Internal Microphone Left", "MBIAS", "MIC1", "Internal Microphone Left", "Internal Microphone Right", "HBIAS", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 25150aba749d..5780713b0dba 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -392,10 +392,10 @@ "Internal Speaker", "Speaker Amp OUTR", "Speaker Amp INL", "LINEOUT", "Speaker Amp INR", "LINEOUT", - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "Left DAC", "DACL", + "Right DAC", "DACR", + "ADCL", "Left ADC", + "ADCR", "Right ADC", "Internal Microphone", "MBIAS", "MIC1", "Internal Microphone", "Headset Microphone", "HBIAS", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index dc4ab6b434f9..3ab0f0347bc9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -421,15 +421,15 @@ "Headphone", "Headphone Jack", "Speaker", "Internal Speaker"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", + "Left DAC", "DACL", + "Right DAC", "DACR", "Speaker Amp INL", "LINEOUT", "Speaker Amp INR", "LINEOUT", "Internal Speaker", "Speaker Amp OUTL", "Internal Speaker", "Speaker Amp OUTR", "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "ADCL", "Left ADC", + "ADCR", "Right ADC", "Internal Microphone Left", "MBIAS", "MIC1", "Internal Microphone Left", "Internal Microphone Right", "HBIAS", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 2f6ea9f3f6a2..9ebb9e07fae3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -159,11 +159,11 @@ simple-audio-card,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", + "Left DAC", "DACL", + "Right DAC", "DACR", "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "ADCL", "Left ADC", + "ADCR", "Right ADC", "MIC2", "Microphone Jack"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index f5df5f705b72..a1864a89fb89 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -340,10 +340,10 @@ "Microphone", "Internal Microphone", "Speaker", "Internal Speaker"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "Left DAC", "DACL", + "Right DAC", "DACR", + "ADCL", "Left ADC", + "ADCR", "Right ADC", "Headphone Jack", "HP", "Speaker Amp INL", "LINEOUT", "Speaker Amp INR", "LINEOUT", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index cf379e38b3a0..88758af18369 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -139,10 +139,10 @@ simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC"; + "Left DAC", "DACL", + "Right DAC", "DACR", + "ADCL", "Left ADC", + "ADCR", "Right ADC"; status = "disabled"; cpudai: simple-audio-card,cpu { -- cgit v1.2.3 From db9c6ad2e88603f5c58d53894ffefcabd55ce3d2 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 25 Jul 2020 20:25:57 -0500 Subject: arm64: dts: allwinner: a64: Update the audio codec compatible The audio codec in the A64 has some differences from the A33 codec, so it needs its own compatible. Since the two codecs are similar, the A33 codec compatible is kept as a fallback. Using the correct compatible fixes a channel inversion issue and cleans up some DAPM widgets that are no longer used. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200726012557.38282-8-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 88758af18369..dc238814013c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -861,7 +861,8 @@ codec: codec@1c22e00 { #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a33-codec"; + compatible = "allwinner,sun50i-a64-codec", + "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x600>; interrupts = ; clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; -- cgit v1.2.3 From 884d1a334ae8130fabede56f59b224619ad6bca4 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Mon, 7 Sep 2020 19:54:37 +0200 Subject: dt-bindings: crypto: Specify that allwinner, sun8i-a33-crypto needs reset When adding allwinner,sun8i-a33-crypto, I forgot to add that it needs reset. Furthermore, there are no need to use items to list only one compatible in compatible list. Fixes: f81547ba7a98 ("dt-bindings: crypto: add new compatible for A33 SS") Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200907175437.4464-1-clabbe.montjoie@gmail.com --- .../devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml index fc823572bcff..90c6d039b91b 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -23,8 +23,7 @@ properties: - items: - const: allwinner,sun7i-a20-crypto - const: allwinner,sun4i-a10-crypto - - items: - - const: allwinner,sun8i-a33-crypto + - const: allwinner,sun8i-a33-crypto reg: maxItems: 1 @@ -59,7 +58,9 @@ if: properties: compatible: contains: - const: allwinner,sun6i-a31-crypto + enum: + - allwinner,sun6i-a31-crypto + - allwinner,sun8i-a33-crypto then: required: -- cgit v1.2.3 From b7158866c3b8aaff16fbea1a35cbbb4ab068ea3e Mon Sep 17 00:00:00 2001 From: Martin Cerveny Date: Mon, 7 Sep 2020 18:24:57 +0200 Subject: dt-bindings: crypto: Add compatible for V3s Allwinner V3s has crypto engine similar to that in A33. So add compatible. Signed-off-by: Martin Cerveny Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200907162458.23730-2-m.cerveny@computer.org --- .../devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml index 90c6d039b91b..0429fb774f10 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -24,6 +24,9 @@ properties: - const: allwinner,sun7i-a20-crypto - const: allwinner,sun4i-a10-crypto - const: allwinner,sun8i-a33-crypto + - items: + - const: allwinner,sun8i-v3s-crypto + - const: allwinner,sun8i-a33-crypto reg: maxItems: 1 -- cgit v1.2.3 From 96820e359e25c7a61c4c8b994745aaa9d9db6a5e Mon Sep 17 00:00:00 2001 From: Martin Cerveny Date: Mon, 7 Sep 2020 18:24:58 +0200 Subject: ARM: dts: sun8i: v3s: Enable crypto engine V3s contains crypto engine that is compatible with A33. Add device tree node. Signed-off-by: Martin Cerveny Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200907162458.23730-3-m.cerveny@computer.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index e5312869c0d2..6eb9c39aa93f 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -234,6 +234,17 @@ #size-cells = <0>; }; + crypto@1c15000 { + compatible = "allwinner,sun8i-v3s-crypto", + "allwinner,sun8i-a33-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_CE>; + reset-names = "ahb"; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x0400>; -- cgit v1.2.3 From 453802c463abd003a7c38ffbc90b67ba162335b6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 17 Sep 2020 15:21:16 +0200 Subject: arm64: dts: renesas: r8a77990: Fix MSIOF1 DMA channels According to Technical Update TN-RCT-S0352A/E, MSIOF1 DMA can only be used with SYS-DMAC0 on R-Car E3. Fixes: 8517042060b55a37 ("arm64: dts: renesas: r8a77990: Add DMA properties to MSIOF nodes") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200917132117.8515-2-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 5eb4e116db09..33d7e657bd9c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1192,9 +1192,8 @@ reg = <0 0xe6ea0000 0 0x0064>; interrupts = ; clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x43>, <&dmac0 0x42>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 210>; #address-cells = <1>; -- cgit v1.2.3 From c91dfc9818df5f43c10c727f1cecaebdb5e2fa92 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 17 Sep 2020 15:21:17 +0200 Subject: arm64: dts: renesas: r8a774c0: Fix MSIOF1 DMA channels According to Technical Update TN-RCT-S0352A/E, MSIOF1 DMA can only be used with SYS-DMAC0 on R-Car E3. Fixes: 62c0056f1c3eb15d ("arm64: dts: renesas: r8a774c0: Add MSIOF nodes") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200917132117.8515-3-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 0e1266ff5dc5..f27d9b2eb996 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1214,9 +1214,8 @@ reg = <0 0xe6ea0000 0 0x0064>; interrupts = ; clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x43>, <&dmac0 0x42>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 210>; #address-cells = <1>; -- cgit v1.2.3 From 54cc33a3a44fc7f7d6743f7cfabc5de086a0e056 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:39 +0200 Subject: dt-bindings: misc: tegra-apbmisc: Add missing compatible strings The compatible string for the Tegra210 APBMISC block was missing from the bindings. Add it and while at it, rewrite the description of the compatible string to make it clearer. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- .../devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index 4556359c5876..83f6a251ba3e 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -1,10 +1,13 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block +NVIDIA Tegra APBMISC block Required properties: -- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30, - must be "nvidia,tegra30-apbmisc". Otherwise, must contain - "nvidia,-apbmisc", plus one of the above, where is tegra114, - tegra124, tegra132. +- compatible: Must be: + - Tegra20: "nvidia,tegra20-apbmisc" + - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc" + - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc" + - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" + - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" + - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc" - reg: Should contain 2 entries: the first entry gives the physical address and length of the registers which contain revision and debug features. The second entry gives the physical address and length of the -- cgit v1.2.3 From c8f413b930058726ad0bb59ac35d9241a375e905 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:40 +0200 Subject: dt-bindings: misc: tegra186-misc: Add missing compatible string Add the missing compatible string for the Tegra194 MISC block. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt index 892ba4384abc..111dfac70ea7 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt @@ -1,11 +1,12 @@ -NVIDIA Tegra186 MISC register block +NVIDIA Tegra186 (and later) MISC register block -The MISC register block found on Tegra186 SoCs contains registers that can be -used to identify a given chip and various strapping options. +The MISC register block found on Tegra186 and later SoCs contains registers +that can be used to identify a given chip and various strapping options. Required properties: - compatible: Must be: - Tegra186: "nvidia,tegra186-misc" + - Tegra194: "nvidia,tegra194-misc" - reg: Should contain 2 entries: The first entry gives the physical address and length of the register region which contains revision and debug features. The second entry specifies the physical address and length -- cgit v1.2.3 From c9e43d13f02785c5dc53ff62c6c94d6df8c6f978 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:41 +0200 Subject: dt-bindings: misc: tegra186-misc: Add Tegra234 support The MISC block found on Tegra234 is mostly similar to the one on Tegra194 but supports slightly different register sets that make it incompatible. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt index 111dfac70ea7..43d777ed8316 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt @@ -7,6 +7,7 @@ Required properties: - compatible: Must be: - Tegra186: "nvidia,tegra186-misc" - Tegra194: "nvidia,tegra194-misc" + - Tegra234: "nvidia,tegra234-misc" - reg: Should contain 2 entries: The first entry gives the physical address and length of the register region which contains revision and debug features. The second entry specifies the physical address and length -- cgit v1.2.3 From b0e0423cfabc1eb407baee52cabbd9df2830feb0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:42 +0200 Subject: dt-bindings: tegra: Add Tegra234 VDK compatible The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index e0b3debaee9e..85006ca503a7 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -119,3 +119,7 @@ properties: items: - const: nvidia,p3509-0000+p3668-0000 - const: nvidia,tegra194 + - items: + - enum: + - nvidia,tegra234-vdk + - const: nvidia,tegra234 -- cgit v1.2.3 From e4fb9a715f75efb28e7d92a573bd6216ca5355ac Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:43 +0200 Subject: dt-bindings: fuse: tegra: Add Tegra234 support The Tegra234 FUSE block is very similar to that on prior chips but not completely compatible. Document the new compatible string. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt index 2aaf661c04ee..b109911669e4 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt @@ -7,6 +7,7 @@ Required properties: For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". + For Tegra234 must contain "nvidia,tegra234-efuse". Details: nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data due to a hardware bug. Tegra20 also lacks certain information which is -- cgit v1.2.3 From b198a6ed02562b1a5aaae4f22598706b912c026a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:44 +0200 Subject: dt-bindings: tegra: pmc: Add Tegra234 support The PMC found on Tegra234 is mostly similar to the one on Tegra194 but supports slightly different I/O pads and wake events. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt index 2d89cdc39eb0..576462fae27f 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Should contain one of the following: - "nvidia,tegra186-pmc": for Tegra186 - "nvidia,tegra194-pmc": for Tegra194 + - "nvidia,tegra234-pmc": for Tegra234 - reg: Must contain an (offset, length) pair of the register set for each entry in reg-names. - reg-names: Must include the following entries: @@ -11,7 +12,7 @@ Required properties: - "wake" - "aotag" - "scratch" - - "misc" (Only for Tegra194) + - "misc" (Only for Tegra194 and later) Optional properties: - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. -- cgit v1.2.3 From 2312c291f6ac340af88eee0867fdfdfa2299ffc3 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 14 Aug 2020 00:34:01 +0300 Subject: dt-bindings: power: supply: Add device-tree binding for Summit SMB3xx Summit SMB3xx series is a Programmable Switching Li+ Battery Charger. This patch adds device-tree binding for Summit SMB345, SMB347 and SMB358 chargers. Signed-off-by: David Heidelberg Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../power/supply/summit,smb347-charger.yaml | 152 +++++++++++++++++++++ include/dt-bindings/power/summit,smb347-charger.h | 19 +++ 2 files changed, 171 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml create mode 100644 include/dt-bindings/power/summit,smb347-charger.h diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml new file mode 100644 index 000000000000..193a23af2007 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/supply/summit,smb347-charger.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Battery charger driver for SMB345, SMB347 and SMB358 + +maintainers: + - David Heidelberg + - Dmitry Osipenko + +properties: + compatible: + enum: + - summit,smb345 + - summit,smb347 + - summit,smb358 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + monitored-battery: + description: phandle to the battery node + $ref: /schemas/types.yaml#/definitions/phandle + + summit,enable-usb-charging: + type: boolean + description: Enable charging through USB. + + summit,enable-otg-charging: + type: boolean + description: Provide power for USB OTG + + summit,enable-mains-charging: + type: boolean + description: Enable charging through mains + + summit,enable-charge-control: + description: Enable charging control + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_CHG_ENABLE_SW SW (I2C interface) + - 1 # SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW Pin control (Active Low) + - 2 # SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH Pin control (Active High) + + summit,fast-voltage-threshold-microvolt: + description: Voltage threshold to transit to fast charge mode (in uV) + minimum: 2400000 + maximum: 3000000 + + summit,mains-current-limit-microamp: + description: Maximum input current from AC/DC input (in uA) + + summit,usb-current-limit-microamp: + description: Maximum input current from USB input (in uA) + + summit,charge-current-compensation-microamp: + description: Charge current compensation (in uA) + + summit,chip-temperature-threshold-celsius: + description: Chip temperature for thermal regulation in °C. + enum: [100, 110, 120, 130] + + summit,soft-compensation-method: + description: Soft temperature limit compensation method + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_SOFT_TEMP_COMPENSATE_NONE Compensation none + - 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation + - 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation + +allOf: + - if: + properties: + compatible: + enum: + - summit,smb345 + - summit,smb358 + + then: + properties: + summit,mains-current-limit-microamp: + enum: [ 300000, 500000, 700000, 1000000, + 1500000, 1800000, 2000000] + + summit,usb-current-limit-microamp: + enum: [ 300000, 500000, 700000, 1000000, + 1500000, 1800000, 2000000] + + summit,charge-current-compensation-microamp: + enum: [200000, 450000, 600000, 900000] + + else: + properties: + summit,mains-current-limit-microamp: + enum: [ 300000, 500000, 700000, 900000, 1200000, + 1500000, 1800000, 2000000, 2200000, 2500000] + + summit,usb-current-limit-microamp: + enum: [ 300000, 500000, 700000, 900000, 1200000, + 1500000, 1800000, 2000000, 2200000, 2500000] + + summit,charge-current-compensation-microamp: + enum: [250000, 700000, 900000, 1200000] + +required: + - compatible + - reg + +anyOf: + - required: + - summit,enable-usb-charging + - required: + - summit,enable-otg-charging + - required: + - summit,enable-mains-charging + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@7f { + compatible = "summit,smb347"; + reg = <0x7f>; + + summit,enable-charge-control = ; + summit,chip-temperature-threshold-celsius = <110>; + summit,mains-current-limit-microamp = <2000000>; + summit,usb-current-limit-microamp = <500000>; + summit,enable-usb-charging; + summit,enable-mains-charging; + + monitored-battery = <&battery>; + }; + }; + + battery: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <1800000>; + operating-range-celsius = <0 45>; + alert-celsius = <3 42>; + }; diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h new file mode 100644 index 000000000000..d918bf321a71 --- /dev/null +++ b/include/dt-bindings/power/summit,smb347-charger.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later or MIT) */ +/* + * Author: David Heidelberg + */ + +#ifndef _DT_BINDINGS_SMB347_CHARGER_H +#define _DT_BINDINGS_SMB347_CHARGER_H + +/* Charging compensation method */ +#define SMB3XX_SOFT_TEMP_COMPENSATE_NONE 0 +#define SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT 1 +#define SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE 2 + +/* Charging enable control */ +#define SMB3XX_CHG_ENABLE_SW 0 +#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1 +#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2 + +#endif -- cgit v1.2.3 From 639448912ba17a9af9e759efbab37d36c6e29dea Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:52 +0200 Subject: arm64: tegra: Initial Tegra234 VDK support The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 1 + arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts | 40 +++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 189 ++++++++++++++++++++++++ drivers/soc/tegra/Kconfig | 10 ++ include/dt-bindings/clock/tegra234-clock.h | 14 ++ include/dt-bindings/reset/tegra234-reset.h | 10 ++ 6 files changed, 264 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra234.dtsi create mode 100644 include/dt-bindings/clock/tegra234-clock.h create mode 100644 include/dt-bindings/reset/tegra234-reset.h diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 2273fc5db19c..9296d12d11e9 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -9,3 +9,4 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts new file mode 100644 index 000000000000..f6e6a24829af --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra234.dtsi" + +/ { + model = "NVIDIA Tegra234 VDK"; + compatible = "nvidia,tegra234-vdk", "nvidia,tegra234"; + + aliases { + sdhci3 = "/cbb@0/sdhci@3460000"; + serial0 = &uarta; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x03100000"; + stdout-path = "serial0:115200n8"; + }; + + cbb@0 { + serial@3100000 { + status = "okay"; + }; + + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + only-1-8-v; + }; + + rtc@c2a0000 { + status = "okay"; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi new file mode 100644 index 000000000000..f0efb3a62804 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include + +/ { + compatible = "nvidia,tegra234"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + bus@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x0 0x40000000>; + + misc@100000 { + compatible = "nvidia,tegra234-misc"; + reg = <0x00100000 0xf000>, + <0x0010f000 0x1000>; + status = "okay"; + }; + + uarta: serial@3100000 { + compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; + reg = <0x03100000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_UARTA>; + clock-names = "serial"; + resets = <&bpmp TEGRA234_RESET_UARTA>; + reset-names = "serial"; + status = "disabled"; + }; + + mmc@3460000 { + compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; + reg = <0x03460000 0x20000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_SDMMC4>; + clock-names = "sdhci"; + resets = <&bpmp TEGRA234_RESET_SDMMC4>; + reset-names = "sdhci"; + dma-coherent; + status = "disabled"; + }; + + fuse@3810000 { + compatible = "nvidia,tegra234-efuse"; + reg = <0x03810000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_FUSE>; + clock-names = "fuse"; + }; + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell", "shared0", "shared1", "shared2", + "shared3", "shared4", "shared5", "shared6", + "shared7"; + #mbox-cells = <2>; + }; + + hsp_aon: hsp@c150000 { + compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; + reg = <0x0c150000 0x90000>; + interrupts = , + , + , + ; + /* + * Shared interrupt 0 is routed only to AON/SPE, so + * we only have 4 shared interrupts for the CCPLEX. + */ + interrupt-names = "shared1", "shared2", "shared3", "shared4"; + #mbox-cells = <2>; + }; + + rtc@c2a0000 { + compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; + reg = <0x0c2a0000 0x10000>; + interrupt-parent = <&pmc>; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pmc: pmc@c360000 { + compatible = "nvidia,tegra234-pmc"; + reg = <0x0c360000 0x10000>, + <0x0c370000 0x10000>, + <0x0c380000 0x10000>, + <0x0c390000 0x10000>, + <0x0c3a0000 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch", "misc"; + + #interrupt-cells = <2>; + interrupt-controller; + }; + + gic: interrupt-controller@f400000 { + compatible = "arm,gic-v3"; + reg = <0x0f400000 0x010000>, /* GICD */ + <0x0f440000 0x200000>; /* GICR */ + interrupt-parent = <&gic>; + interrupts = ; + + #redistributor-regions = <1>; + #interrupt-cells = <3>; + interrupt-controller; + }; + }; + + sysram@40000000 { + compatible = "nvidia,tegra234-sysram", "mmio-sram"; + reg = <0x0 0x40000000 0x0 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40000000 0x50000>; + + cpu_bpmp_tx: shmem@4e000 { + reg = <0x4e000 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: shmem@4f000 { + reg = <0x4f000 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + bpmp_i2c: i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + reg = <0x000>; + + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + status = "okay"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + always-on; + }; +}; diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 6bc603d0b9d9..976dee036470 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -119,6 +119,16 @@ config ARCH_TEGRA_194_SOC help Enable support for the NVIDIA Tegra194 SoC. +config ARCH_TEGRA_234_SOC + bool "NVIDIA Tegra234 SoC" + select MAILBOX + select TEGRA_BPMP + select TEGRA_HSP_MBOX + select TEGRA_IVC + select SOC_TEGRA_PMC + help + Enable support for the NVIDIA Tegra234 SoC. + endif endif diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h new file mode 100644 index 000000000000..2c82072950ee --- /dev/null +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H +#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H + +/** @brief output of gate CLK_ENB_FUSE */ +#define TEGRA234_CLK_FUSE 40 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ +#define TEGRA234_CLK_SDMMC4 123 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ +#define TEGRA234_CLK_UARTA 155 + +#endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h new file mode 100644 index 000000000000..b3c63be06d2d --- /dev/null +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H +#define DT_BINDINGS_RESET_TEGRA234_RESET_H + +#define TEGRA234_RESET_SDMMC4 85 +#define TEGRA234_RESET_UARTA 100 + +#endif -- cgit v1.2.3 From ef599f5f3e10bf1979d8ece29fd7fa511fedd59d Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 15 Sep 2020 17:24:30 +0200 Subject: arm64: dts: meson: convert ODROID-N2 to dtsi Convert the current ODROID-N2 dts into a common dtsi in preparation for adding ODROID-N2+ support. Signed-off-by: Christian Hewitt Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Acked-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20200915152432.30616-2-narmstrong@baylibre.com --- .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 618 +------------------- .../boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 625 +++++++++++++++++++++ 2 files changed, 626 insertions(+), 617 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts index 34fffa6d859d..a198a91259ec 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts @@ -7,625 +7,9 @@ /dts-v1/; #include "meson-g12b-s922x.dtsi" -#include -#include -#include -#include +#include "meson-g12b-odroid-n2.dtsi" / { compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b"; model = "Hardkernel ODROID-N2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - dioo2133: audio-amplifier-0 { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - VCC-supply = <&vcc_5v>; - sound-name-prefix = "U19"; - status = "okay"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "n2:blue"; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8120B1ABC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-ODROID-N2"; - audio-widgets = "Line", "Lineout"; - audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, - <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, - <&dioo2133>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_LB IN 1", "TDM_B Loopback", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 5", "TDM_C Loopback", - "TDMIN_LB IN 2", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT", - "U19 INL", "ACODEC LOLP", - "U19 INR", "ACODEC LORP", - "Lineout", "U19 OUTL", - "Lineout", "U19 OUTR"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_B>; - }; - }; - - /* i2s jack output interface */ - dai-link-7 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_C>; - }; - }; - - /* hdmi glue */ - dai-link-8 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - - /* acodec glue */ - dai-link-9 { - sound-dai = <&toacodec TOACODEC_OUT>; - - codec { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddao_1v8>; - status = "okay"; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&gpio { - /* - * WARNING: The USB Hub on the Odroid-N2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - usb-hub { - gpio-hog; - gpios = ; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-odroid"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; - -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -/* - * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins - * and eMMC Data 4 to 7 pins. - * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, - * and change bus-width to 4 then spifc can be enabled. - * The SW1 slide should also be set to the correct position. - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - mx25u64: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmif_c { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmin_lb { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&toacodec { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi new file mode 100644 index 000000000000..6982632ae646 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include +#include +#include +#include + +/ { + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + dioo2133: audio-amplifier-0 { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + VCC-supply = <&vcc_5v>; + sound-name-prefix = "U19"; + status = "okay"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "n2:blue"; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + tflash_vdd: regulator-tflash_vdd { + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0>, + <1800000 1>; + }; + + flash_1v8: regulator-flash_1v8 { + compatible = "regulator-fixed"; + regulator-name = "FLASH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&main_12v>; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + /* FIXME: actually controlled by VDDCPU_B_EN */ + }; + + vddcpu_a: regulator-vddcpu-a { + /* + * MP8756GD Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_A"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_ab 0 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddcpu_b: regulator-vddcpu-b { + /* + * Silergy SY8120B1ABC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_B"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + hub_5v: regulator-hub_5v { + compatible = "regulator-fixed"; + regulator-name = "HUB_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the Hub CHIPENABLE, LOW sets low power state */ + gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_pwr_en: regulator-usb_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the microUSB port power enable */ + gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "G12B-ODROID-N2"; + audio-widgets = "Line", "Lineout"; + audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, + <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, + <&dioo2133>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "TDMOUT_C IN 0", "FRDDR_A OUT 2", + "TDMOUT_C IN 1", "FRDDR_B OUT 2", + "TDMOUT_C IN 2", "FRDDR_C OUT 2", + "TDM_C Playback", "TDMOUT_C OUT", + "TDMIN_A IN 4", "TDM_B Loopback", + "TDMIN_B IN 4", "TDM_B Loopback", + "TDMIN_C IN 4", "TDM_B Loopback", + "TDMIN_LB IN 1", "TDM_B Loopback", + "TDMIN_A IN 5", "TDM_C Loopback", + "TDMIN_B IN 5", "TDM_C Loopback", + "TDMIN_C IN 5", "TDM_C Loopback", + "TDMIN_LB IN 2", "TDM_C Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT", + "TODDR_A IN 2", "TDMIN_C OUT", + "TODDR_B IN 2", "TDMIN_C OUT", + "TODDR_C IN 2", "TDMIN_C OUT", + "TODDR_A IN 6", "TDMIN_LB OUT", + "TODDR_B IN 6", "TDMIN_LB OUT", + "TODDR_C IN 6", "TDMIN_LB OUT", + "U19 INL", "ACODEC LOLP", + "U19 INR", "ACODEC LORP", + "Lineout", "U19 OUTL", + "Lineout", "U19 OUTR"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + dai-link-3 { + sound-dai = <&toddr_a>; + }; + + dai-link-4 { + sound-dai = <&toddr_b>; + }; + + dai-link-5 { + sound-dai = <&toddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-6 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + + codec-1 { + sound-dai = <&toacodec TOACODEC_IN_B>; + }; + }; + + /* i2s jack output interface */ + dai-link-7 { + sound-dai = <&tdmif_c>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; + }; + + codec-1 { + sound-dai = <&toacodec TOACODEC_IN_C>; + }; + }; + + /* hdmi glue */ + dai-link-8 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + + /* acodec glue */ + dai-link-9 { + sound-dai = <&toacodec TOACODEC_OUT>; + + codec { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddao_1v8>; + status = "okay"; +}; + +&arb { + status = "okay"; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&clkc_audio { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu100 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu101 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu102 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu103 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&gpio { + /* + * WARNING: The USB Hub on the Odroid-N2 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = ; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; + linux,rc-map-name = "rc-odroid"; +}; + +&pwm_ab { + pinctrl-0 = <&pwm_a_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; + status = "okay"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; + +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + +/* + * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins + * and eMMC Data 4 to 7 pins. + * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, + * and change bus-width to 4 then spifc can be enabled. + * The SW1 slide should also be set to the correct position. + */ +&spifc { + status = "disabled"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + mx25u64: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + }; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmif_c { + status = "okay"; +}; + +&tdmin_a { + status = "okay"; +}; + +&tdmin_b { + status = "okay"; +}; + +&tdmin_c { + status = "okay"; +}; + +&tdmin_lb { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tdmout_c { + status = "okay"; +}; + +&toacodec { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_pwr_en>; +}; + +&usb2_phy0 { + phy-supply = <&vcc_5v>; +}; + +&usb2_phy1 { + /* Enable the hub which is connected to this port */ + phy-supply = <&hub_5v>; +}; -- cgit v1.2.3 From 88ba71cdc5497390350c87e68ce35688e88be3e8 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 15 Sep 2020 17:24:31 +0200 Subject: dt-bindings: arm: amlogic: add support for the ODROID-N2+ HardKernel ODROID-N2+ uses a revised Amlogic S922X v2 chip that supports higher cpu clock speeds than the original ODROID-N2. Signed-off-by: Christian Hewitt Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Acked-by: Rob Herring Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20200915152432.30616-3-narmstrong@baylibre.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 5eba9f48823e..12ba8d074370 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -153,6 +153,7 @@ properties: - azw,gtking - azw,gtking-pro - hardkernel,odroid-n2 + - hardkernel,odroid-n2-plus - khadas,vim3 - ugoos,am6 - const: amlogic,s922x -- cgit v1.2.3 From 98d24896ee117b1f0969405476c943e9307e30d4 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 15 Sep 2020 17:24:32 +0200 Subject: arm64: dts: meson: add support for the ODROID-N2+ HardKernel ODROID-N2+ uses an Amlogic S922X rev. C chip capable of higher clock speeds than the original ODROID-N2. The rev. C support a slighly higher VDDCPU_A & VDDCPU_B voltages and supports the same OPPs as the Amlogic A311D SoC from the same G12B family. Suggested-by: Dongjin Kim Signed-off-by: Christian Hewitt Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20200915152432.30616-4-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts | 31 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 4e2239ffcaa5..b0b3d6791499 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts new file mode 100644 index 000000000000..5de2815ba99d --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +/dts-v1/; + +/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */ +#include "meson-g12b-a311d.dtsi" +#include "meson-g12b-odroid-n2.dtsi" + +/ { + compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b"; + model = "Hardkernel ODROID-N2Plus"; +}; + +&vddcpu_a { + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1040000>; + + pwms = <&pwm_AO_cd 1 1500 0>; +}; + +&vddcpu_b { + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1040000>; + + pwms = <&pwm_AO_cd 1 1500 0>; +}; + -- cgit v1.2.3 From 0748c77fc8dc6bb20f9af395872ea35d8ac85998 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 15 Sep 2020 16:19:20 +0200 Subject: dt-bindings: arm: amlogic: add support for libretch s905x cc v2 Add support for the 2nd version of the libretch aml-s905x-cc. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200915141921.57258-2-jbrunet@baylibre.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 12ba8d074370..0ee7c5b7b3f6 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -96,6 +96,7 @@ properties: - hwacom,amazetv - khadas,vim - libretech,aml-s905x-cc + - libretech,aml-s905x-cc-v2 - nexbox,a95x - const: amlogic,s905x - const: amlogic,meson-gxl -- cgit v1.2.3 From 63fafc5a046b1e21756de691b48f0c70c25e1426 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 15 Sep 2020 16:19:21 +0200 Subject: arm64: dts: meson: initial support for aml-s905x-cc v2 Add initial support for the libretech aml-s905x-cc (Le Potato) v2 Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200915141921.57258-3-jbrunet@baylibre.com --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../amlogic/meson-gxl-s905x-libretech-cc-v2.dts | 318 +++++++++++++++++++++ 2 files changed, 319 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index b0b3d6791499..ced03946314f 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts new file mode 100644 index 000000000000..675eaa87963e --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Jerome Brunet + */ + +/dts-v1/; + +#include +#include +#include + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x", + "amlogic,meson-gxl"; + model = "Libre Computer AML-S905X-CC V2"; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + spi0 = &spifc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + panic-indicator; + }; + + led-green { + color = ; + function = LED_FUNCTION_DISK_ACTIVITY; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ao_5v: regulator-ao_5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + dc_in: regulator-dc_in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + + vcck: regulator-vcck { + compatible = "regulator-fixed"; + regulator-name = "VCCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ao_5v>; + regulator-always-on; + }; + + vcc_card: regulator-vcc_card { + compatible = "regulator-fixed"; + regulator-name = "VCC_CARD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddio_ao3v3>; + + gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc5v: regulator-vcc5v { + compatible = "regulator-fixed"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ao_5v>; + + gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; + }; + + vddio_ao3v3: regulator-vddio_ao3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ao_5v>; + regulator-always-on; + }; + + + vddio_card: regulator-vddio-card { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0>, + <1800000 1>; + + regulator-settling-time-up-us = <200>; + regulator-settling-time-down-us = <50000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddio_ao3v3>; + regulator-always-on; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC 1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddio_ao3v3>; + regulator-always-on; + }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-LIBRETECH-S905X-CC-V2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + + +&aiu { + status = "okay"; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + + +ðmac { + status = "okay"; +}; + +&internal_phy { + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + hdmi-supply = <&vcc5v>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* SD card */ +&sd_emmc_b { + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vcc_card>; + vqmmc-supply = <&vddio_card>; + + status = "okay"; +}; + +/* eMMC */ +&sd_emmc_c { + pinctrl-0 = <&emmc_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddio_ao3v3>; + vqmmc-supply = <&vcc_1v8>; + + status = "okay"; +}; + +&spifc { + status = "okay"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + nor_4u1: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <3000000>; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy0 { + pinctrl-names = "default"; + phy-supply = <&vcc5v>; +}; + +&usb2_phy1 { + phy-supply = <&vcc5v>; +}; -- cgit v1.2.3 From fa7a98eb47f4d0aa431994dfd5cf2d621771ebe5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:50:52 +0200 Subject: arm64: dts: zynqmp-zcu100-revC: correct interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200917185052.5084-1-krzk@kernel.org Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index d60110ad8367..c9460693f4e9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -186,7 +186,7 @@ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; - interrupts = <77 GPIO_ACTIVE_LOW>; + interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; -- cgit v1.2.3 From e2a8fa1e0faa5000c89a5af33d6c357e55c86014 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 10 Sep 2020 19:57:21 +0200 Subject: arm64: dts: mediatek: fix tca6416 reset GPIOs in pumpkin Correct the property for reset GPIOs of tca6416 GPIO expander. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200910175733.11046-4-krzk@kernel.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index dfceffe6950a..29d8cf6df46b 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -56,7 +56,7 @@ tca6416: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; - rst-gpio = <&pio 65 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 65 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&tca6416_pins>; -- cgit v1.2.3 From 36f0a5fc5284838c544218666c63ee8cfa46a9c3 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Mon, 7 Sep 2020 09:05:17 +0200 Subject: arm: dts: mt7623: add missing pause for switchport port6 of mt7530 switch (= cpu port 0) on bananapi-r2 misses pause option which causes rx drops on running iperf. Fixes: f4ff257cd160 ("arm: dts: mt7623: add support for Bananapi R2 (BPI-R2) board") Signed-off-by: Frank Wunderlich Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200907070517.51715-1-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 826912545ef1..e96aa0ed1ebd 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -235,6 +235,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; -- cgit v1.2.3 From 1276be23fd53e1c4e752966d0eab42aa54a343da Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Mon, 27 Jul 2020 15:41:24 +0800 Subject: arm64: dts: mt8173: elm: Fix nor_flash node property bus-width and non-removable is not used by the driver. max-frequency should be spi-max-frequency for flash node. Fixes: 689b937bedde ("arm64: dts: mediatek: add mt8173 elm and hana board") Reported-by: Nicolas Boichat Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20200727074124.3779237-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index bdec719a6b62..44a0346133cd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -433,12 +433,11 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nor_gpio1_pins>; - bus-width = <8>; - max-frequency = <50000000>; - non-removable; + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; + spi-max-frequency = <50000000>; }; }; -- cgit v1.2.3 From 31026c72f9f29644d130d740e7060f431247085a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Sep 2020 16:53:02 +0200 Subject: dt-bindings: arm: fsl: Fix matching Purism Librem5 phones All Purism Librem5 phones have three compatibles so they need their own entry to fix dbts_check warnings like: arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dt.yaml: /: compatible: ['purism,librem5r2', 'purism,librem5', 'fsl,imx8mq'] is not valid under any of the given schemas arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dt.yaml: /: compatible: ['purism,librem5r2', 'purism,librem5', 'fsl,imx8mq'] is too long Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 71acf14da715..93d82641d15c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -379,12 +379,18 @@ properties: - fsl,imx8mq-evk # i.MX8MQ EVK Board - google,imx8mq-phanbell # Google Coral Edge TPU - purism,librem5-devkit # Purism Librem5 devkit - - purism,librem5r2 # Purism Librem5 phone "Chestnut" - - purism,librem5r3 # Purism Librem5 phone "Dogwood" - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk - const: fsl,imx8mq + - description: Purism Librem5 phones + items: + - enum: + - purism,librem5r2 # Purism Librem5 phone "Chestnut" + - purism,librem5r3 # Purism Librem5 phone "Dogwood" + - const: purism,librem5 + - const: fsl,imx8mq + - description: Zodiac Inflight Innovations Ultra Boards items: - enum: -- cgit v1.2.3 From f866c471542e6dddca2ab971a85ebc54fd3713a4 Mon Sep 17 00:00:00 2001 From: Crystal Guo Date: Mon, 3 Aug 2020 15:14:58 +0800 Subject: arm64: dts: mt8183: update watchdog device node The watchdog driver for MT8183 relies on DT data, so the fallback compatible MT6589 won't work, need to update watchdog device node to sync with watchdog dt-binding document. Signed-off-by: Crystal Guo Acked-by: Guenter Roeck Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index f9b60e3d085c..9cfd961c45eb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -317,8 +317,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt8183-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8183-wdt"; reg = <0 0x10007000 0 0x100>; #reset-cells = <1>; }; -- cgit v1.2.3 From 510ed6749fa62f9013d73e1b74ae942704904e71 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 9 Sep 2020 17:17:53 +0200 Subject: arm64: dts: imx8mm-var-som-symphony: Remove unneeded i2c3 properties The i2c3 clock frequency and pin configuration are already set by imx8mm-var-som.dtsi. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 84a59be209f1..4e811a7971fe 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -121,11 +121,6 @@ }; &i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - /* Capacitive touch controller */ ft5x06_ts: touchscreen@38 { compatible = "edt,edt-ft5406"; -- cgit v1.2.3 From 12cdf9d2c9f8b846ebca210c523fa6c3c5db0ac0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 9 Sep 2020 17:17:54 +0200 Subject: arm64: dts: imx8mm-var-som-symphony: Adjust ethernet pin configuration The Symphony board uses GPIO from expander as Ethernet PHY reset pin, not the GPIO1_IO9. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-var-som-symphony.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 4e811a7971fe..daaed1a525a9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -181,6 +181,26 @@ status = "disabled"; }; +&pinctrl_fec1 { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ + >; +}; + &iomuxc { pinctrl_captouch: captouchgrp { fsl,pins = < -- cgit v1.2.3 From c48cf8e5d88bcbeaeb3c3e779cebd58d1e5e7653 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 22 Sep 2020 09:46:48 +0800 Subject: arm64: dts: imx8mn-ddr4-evk: Remove unneeded PMIC pin configuration The pin configuration for PMIC interrupt is already set by imx8mn-evk.dtsi with exactly the same values. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 8f7155716c84..68fa943ea8d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -153,11 +153,3 @@ }; }; }; - -&iomuxc { - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; -}; -- cgit v1.2.3 From dcdd4f2e829e707c6cf4f6f6554252bb31f7b98a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:15 +0200 Subject: ARM: dts: imx6q: align GPIO hog names with dtschema dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. While touching the hogs, fix indentation (spaces -> tabs). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-b450v3.dts | 14 +++++++------- arch/arm/boot/dts/imx6q-b650v3.dts | 12 ++++++------ arch/arm/boot/dts/imx6q-b850v3.dts | 4 ++-- arch/arm/boot/dts/imx6q-bx50v3.dtsi | 12 ++++++------ 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts index fb0980190aa0..604f2420370f 100644 --- a/arch/arm/boot/dts/imx6q-b450v3.dts +++ b/arch/arm/boot/dts/imx6q-b450v3.dts @@ -84,19 +84,19 @@ }; &pca9539 { - P04 { + P04-hog { gpio-hog; gpios = <4 0>; output-low; line-name = "PCA9539-P04"; }; - P07 { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; + P07-hog { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; }; &pci_root { diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts index 8f762d9c5ae9..56d2aeb1900c 100644 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/imx6q-b650v3.dts @@ -84,12 +84,12 @@ }; &pca9539 { - P07 { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; + P07-hog { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; }; &usbphy1 { diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index 1ea64ecf4291..3d6b757bf325 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -199,14 +199,14 @@ }; &pca9539 { - P10 { + P10-hog { gpio-hog; gpios = <8 0>; output-low; line-name = "PCA9539-P10"; }; - P11 { + P11-hog { gpio-hog; gpios = <9 0>; output-low; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 02812e6cb302..2a98cc657595 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -248,42 +248,42 @@ interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - P12 { + P12-hog { gpio-hog; gpios = <10 0>; output-low; line-name = "PCA9539-P12"; }; - P13 { + P13-hog { gpio-hog; gpios = <11 0>; output-low; line-name = "PCA9539-P13"; }; - P14 { + P14-hog { gpio-hog; gpios = <12 0>; output-low; line-name = "PCA9539-P14"; }; - P15 { + P15-hog { gpio-hog; gpios = <13 0>; output-low; line-name = "PCA9539-P15"; }; - P16 { + P16-hog { gpio-hog; gpios = <14 0>; output-low; line-name = "PCA9539-P16"; }; - P17 { + P17-hog { gpio-hog; gpios = <15 0>; output-low; -- cgit v1.2.3 From 928b960fe5aff659de33a3f04ace1ba7d379d5fa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Sep 2020 13:29:11 -0300 Subject: dt-bindings: arm: fsl: Add an entry for the i.MX6 LogicPD board Add an entry for the i.MX6 LogicPD board. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 93d82641d15c..671f809a42b7 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -120,6 +120,7 @@ properties: - fsl,imx6q-sabrelite - fsl,imx6q-sabresd - kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module + - logicpd,imx6q-logicpd - prt,prti6q # Protonic PRTI6Q board - prt,prtwd2 # Protonic WD2 board - technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf -- cgit v1.2.3 From 9249d286984cb0dec97aeef4cea2a680cbe58724 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Sep 2020 13:29:10 -0300 Subject: ARM: dts: imx6q-logicpd: Add a specific board compatible string It is standard practice to have a specific board compatible string, so pass "logicpd,imx6q-logicpd". Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-logicpd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts index 7a3d1d3e54a9..0a211b216a27 100644 --- a/arch/arm/boot/dts/imx6q-logicpd.dts +++ b/arch/arm/boot/dts/imx6q-logicpd.dts @@ -9,7 +9,7 @@ / { model = "Logic PD i.MX6QD SOM-M3"; - compatible = "fsl,imx6q"; + compatible = "logicpd,imx6q-logicpd", "fsl,imx6q"; backlight: backlight-lvds { compatible = "pwm-backlight"; -- cgit v1.2.3 From dd1d4def682048cae8aafad0453c1e65e6596183 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Sep 2020 13:29:12 -0300 Subject: ARM: dts: imx: Add an entry for imx6q-logicpd.dtb Add an entry for imx6q-logicpd.dtb so that it can be built by default. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 245cdc445bc0..8a861fe73e42 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -532,6 +532,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-icore-ofcap12.dtb \ imx6q-icore-rqs.dtb \ imx6q-kp-tpc.dtb \ + imx6q-logicpd.dtb \ imx6q-marsboard.dtb \ imx6q-mccmon6.dtb \ imx6q-nitrogen6x.dtb \ -- cgit v1.2.3 From 55df2079eb6faa048a0d65306556e6d7423a5029 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Sep 2020 13:29:13 -0300 Subject: ARM: dts: imx6q-logicpd: Use GPIO chipselect Using the native SPI chipselect on i.MX6 is known to be problematic. Doing it on a imx6q-sabresd causes the SPI NOR probe to fail: [ 5.388704] spi-nor spi0.0: unrecognized JEDEC id bytes: 00 00 00 00 00 00 Use the GPIO chipselect to avoid such problem. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi index 9e027b9a5f91..665d63765cdc 100644 --- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi +++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi @@ -212,6 +212,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -383,7 +384,7 @@ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 >; }; -- cgit v1.2.3 From 7b0bb204ee705c3b46d8e48f1893979ea6af4753 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 17 Sep 2020 10:30:02 +0200 Subject: dt-bindings: arm: fsl: Add PHYTEC i.MX6 UL/ULL devicetree bindings Add devicetree bindings for i.MX6 UL/ULL based phyCORE-i.MX6 UL/ULL and phyBOARD-Segin. Signed-off-by: Stefan Riedmueller Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 671f809a42b7..eb0db8dd91ca 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -249,6 +249,15 @@ properties: - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi - const: fsl,imx6ul + - description: i.MX6UL PHYTEC phyBOARD-Segin + items: + - enum: + - phytec,imx6ul-pbacd10-emmc + - phytec,imx6ul-pbacd10-nand + - const: phytec,imx6ul-pbacd10 # PHYTEC phyBOARD-Segin with i.MX6 UL + - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL + - const: fsl,imx6ul + - description: Kontron N6310 S Board items: - const: kontron,imx6ul-n6310-s @@ -280,6 +289,15 @@ properties: - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin + items: + - enum: + - phytec,imx6ull-pbacd10-emmc + - phytec,imx6ull-pbacd10-nand + - const: phytec,imx6ull-pbacd10 # PHYTEC phyBOARD-Segin with i.MX6 ULL + - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL + - const: fsl,imx6ull + - description: Kontron N6411 S Board items: - const: kontron,imx6ull-n6411-s -- cgit v1.2.3 From e8c677195cae38175ca45e4ded5b369278a38fec Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 17 Sep 2020 10:30:03 +0200 Subject: dt-bindings: arm: fsl: Add PHYTEC i.MX6 devicetree bindings Add devicetree bindings for i.MX6 based phyCORE-i.MX6, phyBOARD-Mira and phyFLEX-i.MX6. Signed-off-by: Stefan Riedmueller Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index eb0db8dd91ca..14b85166d3bb 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -157,6 +157,21 @@ properties: - const: gw,ventana - const: fsl,imx6q + - description: i.MX6Q PHYTEC phyBOARD-Mira + items: + - enum: + - phytec,imx6q-pbac06-emmc # PHYTEC phyBOARD-Mira eMMC RDK + - phytec,imx6q-pbac06-nand # PHYTEC phyBOARD-Mira NAND RDK + - const: phytec,imx6q-pbac06 # PHYTEC phyBOARD-Mira + - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 + - const: fsl,imx6q + + - description: i.MX6Q PHYTEC phyFLEX-i.MX6 + items: + - const: phytec,imx6q-pbab01 # PHYTEC phyFLEX carrier board + - const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad + - const: fsl,imx6q + - description: i.MX6QP based Boards items: - enum: @@ -164,6 +179,13 @@ properties: - fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board - const: fsl,imx6qp + - description: i.MX6QP PHYTEC phyBOARD-Mira + items: + - const: phytec,imx6qp-pbac06-nand + - const: phytec,imx6qp-pbac06 # PHYTEC phyBOARD-Mira + - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 + - const: fsl,imx6qp + - description: i.MX6DL based Boards items: - enum: @@ -213,6 +235,21 @@ properties: - const: gw,ventana - const: fsl,imx6dl + - description: i.MX6DL PHYTEC phyBOARD-Mira + items: + - enum: + - phytec,imx6dl-pbac06-emmc # PHYTEC phyBOARD-Mira eMMC RDK + - phytec,imx6dl-pbac06-nand # PHYTEC phyBOARD-Mira NAND RDK + - const: phytec,imx6dl-pbac06 # PHYTEC phyBOARD-Mira + - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 + - const: fsl,imx6dl + + - description: i.MX6DL PHYTEC phyFLEX-i.MX6 + items: + - const: phytec,imx6dl-pbab01 # PHYTEC phyFLEX carrier board + - const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad + - const: fsl,imx6dl + - description: i.MX6SL based Boards items: - enum: -- cgit v1.2.3 From 05b0852ec99d45cc95d8f587561239a9095c2949 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:54:46 +0200 Subject: ARM: dts: imx6qdl-gw5xxx: correct interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW Signed-off-by: Krzysztof Kozlowski Acked-By: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw5903.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw5907.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-gw5913.dtsi | 3 ++- 14 files changed, 28 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 7705285d9e3c..e98935974b5d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -154,7 +155,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index f6182a9d201c..736074f1c3ef 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -217,7 +218,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index a28e79463d0c..8072ed47c6bb 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -210,7 +211,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 55f368e192c0..8c9bcdd39830 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include / { @@ -247,7 +248,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 1516e2b0bcde..e5d803d023c8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -48,6 +48,7 @@ #include #include #include +#include #include / { @@ -219,7 +220,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 0da6e6f7482b..290a607fede9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -144,7 +145,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi index faf9a3ba61b2..c15b9cc63bf8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi @@ -47,6 +47,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -180,7 +181,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi index f68f9dada5b0..093a219a77ae 100644 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -47,6 +47,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -294,7 +295,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi index fbe6c32bd756..e1c8dd233cab 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi @@ -47,6 +47,7 @@ #include #include +#include / { chosen { @@ -235,7 +236,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi index 23c6e4047621..3cd2e717c1da 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi @@ -47,6 +47,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -257,7 +258,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi index b1ff7c859c4d..21c68a55bcb9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -154,7 +155,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index 6c943a517ad7..ed4e22259959 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -163,7 +164,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi index 441d8ce97aa4..797f160249f7 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -158,7 +159,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi index d62a8da49367..4cd7d290f5b2 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -139,7 +140,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 4bb1eb3cd4bd6241d5e5f99bbfd801ea5a007b6c Mon Sep 17 00:00:00 2001 From: Amit Singh Tomar Date: Sun, 19 Jul 2020 23:12:02 +0530 Subject: arm64: dts: actions: limit address range for pinctrl node After commit 7cdf8446ed1d ("arm64: dts: actions: Add pinctrl node for Actions Semi S700") following error has been observed while booting Linux on Cubieboard7-lite(based on S700 SoC). [ 0.257415] pinctrl-s700 e01b0000.pinctrl: can't request region for resource [mem 0xe01b0000-0xe01b0fff] [ 0.266902] pinctrl-s700: probe of e01b0000.pinctrl failed with error -16 This is due to the fact that memory range for "sps" power domain controller clashes with pinctrl. One way to fix it, is to limit pinctrl address range which is safe to do as current pinctrl driver uses address range only up to 0x100. This commit limits the pinctrl address range to 0x100 so that it doesn't conflict with sps range. Fixes: 7cdf8446ed1d ("arm64: dts: actions: Add pinctrl node for Actions Semi S700") Reviewed-by: Manivannan Sadhasivam Suggested-by: Andre Przywara Signed-off-by: Amit Singh Tomar Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s700.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi index 2006ad5424fa..f8eb72bb4125 100644 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ b/arch/arm64/boot/dts/actions/s700.dtsi @@ -231,7 +231,7 @@ pinctrl: pinctrl@e01b0000 { compatible = "actions,s700-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; + reg = <0x0 0xe01b0000 0x0 0x100>; clocks = <&cmu CLK_GPIO>; gpio-controller; gpio-ranges = <&pinctrl 0 0 136>; -- cgit v1.2.3 From 13441281bde0b63c6a4767182adbb0c5c1313321 Mon Sep 17 00:00:00 2001 From: Amit Singh Tomar Date: Sun, 19 Jul 2020 23:12:03 +0530 Subject: arm64: dts: actions: Add DMA Controller for S700 This commit adds DMA controller present on Actions S700, it differs from S900 in terms of number of dma channels and requests. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Amit Singh Tomar Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s700.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi index f8eb72bb4125..2c78caebf515 100644 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ b/arch/arm64/boot/dts/actions/s700.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include / { @@ -244,5 +245,19 @@ , ; }; + + dma: dma-controller@e0230000 { + compatible = "actions,s700-dma"; + reg = <0x0 0xe0230000 0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <10>; + dma-requests = <44>; + clocks = <&cmu CLK_DMAC>; + power-domains = <&sps S700_PD_DMA>; + }; }; }; -- cgit v1.2.3 From 874a36f057647e1d9e6c17c15c5c0f5e60fe93a3 Mon Sep 17 00:00:00 2001 From: Matheus Castello Date: Mon, 21 Sep 2020 23:43:01 -0300 Subject: ARM: dts: Add Caninos Loucos Labrador v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Device Trees for Caninos Loucos Labrador CoM Core v2 and base board M v1. Based on the work of Andreas Färber on Lemaker Guitar device tree. Signed-off-by: Matheus Castello Reviewed-by: Manivannan Sadhasivam Reviewed-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/owl-s500-labrador-base-m.dts | 35 ++++++++++++++++++++++++++ arch/arm/boot/dts/owl-s500-labrador-v2.dtsi | 22 ++++++++++++++++ 3 files changed, 58 insertions(+) create mode 100644 arch/arm/boot/dts/owl-s500-labrador-base-m.dts create mode 100644 arch/arm/boot/dts/owl-s500-labrador-v2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..5d5e370af290 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_ACTIONS) += \ owl-s500-cubieboard6.dtb \ owl-s500-guitar-bb-rev-b.dtb \ + owl-s500-labrador-base-m.dtb \ owl-s500-sparky.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts new file mode 100644 index 000000000000..c92f8bdcb331 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Caninos Labrador Base Board + * + * Copyright (c) 2019-2020 Matheus Castello + */ + +/dts-v1/; + +#include "owl-s500-labrador-v2.dtsi" + +/ { + model = "Caninos Labrador Core v2 on Labrador Base-M v1"; + compatible = "caninos,labrador-base-m", + "caninos,labrador-v2", "actions,s500"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + uart3_clk: uart3-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&uart3 { + status = "okay"; + clocks = <&uart3_clk>; +}; diff --git a/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi b/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi new file mode 100644 index 000000000000..883ff2f9886d --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Caninos Labrador SoM V2 + * + * Copyright (c) 2019-2020 Matheus Castello + */ + +#include "owl-s500.dtsi" + +/ { + model = "Caninos Labrador Core V2.1"; + compatible = "caninos,labrador-v2", "actions,s500"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; +}; + +&timer { + clocks = <&hosc>; +}; -- cgit v1.2.3 From 55f6c9931f7c32f19cf221211f099dfd8dab3af9 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 28 Aug 2020 16:53:17 +0300 Subject: ARM: dts: owl-s500: Fix incorrect PPI interrupt specifiers The PPI interrupts for cortex-a9 were incorrectly specified, fix them. Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar") Signed-off-by: Cristian Ciocaltea Reviewed-by: Peter Korsgaard Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5ceb6cc4451d..1dbe4e8b38ac 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -84,21 +84,21 @@ global_timer: timer@b0020200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xb0020200 0x100>; - interrupts = ; + interrupts = ; status = "disabled"; }; twd_timer: timer@b0020600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xb0020600 0x20>; - interrupts = ; + interrupts = ; status = "disabled"; }; twd_wdt: wdt@b0020620 { compatible = "arm,cortex-a9-twd-wdt"; reg = <0xb0020620 0xe0>; - interrupts = ; + interrupts = ; status = "disabled"; }; -- cgit v1.2.3 From 47be1cdee7ac71cec6ab71be654b3204496a8325 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 28 Aug 2020 16:53:20 +0300 Subject: ARM: dts: owl-s500: Add RoseapplePi Add a Device Tree for the RoseapplePi SBC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Peter Korsgaard Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 ++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5d5e370af290..b7854859e6b4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -869,6 +869,7 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \ owl-s500-cubieboard6.dtb \ owl-s500-guitar-bb-rev-b.dtb \ owl-s500-labrador-base-m.dtb \ + owl-s500-roseapplepi.dtb \ owl-s500-sparky.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts new file mode 100644 index 000000000000..a2087e617cb2 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Roseapple Pi + * + * Copyright (C) 2020 Cristian Ciocaltea + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "roseapplepi,roseapplepi", "actions,s500"; + model = "Roseapple Pi"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; + + uart2_clk: uart2-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&twd_timer { + status = "okay"; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart2_clk>; +}; -- cgit v1.2.3 From d684ad5a4c3d85f16a7c72731914de95281a250b Mon Sep 17 00:00:00 2001 From: Matheus Castello Date: Mon, 21 Sep 2020 23:42:59 -0300 Subject: dt-bindings: Add vendor prefix for Caninos Loucos MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Caninos Loucos Program develops Single Board Computers with an open structure. The Program wants to form a community of developers to use IoT technologies and disseminate the learning of embedded systems in Brazil. It is an initiative of the Technological Integrated Systems Laboratory (LSI-TEC) with the support of Polytechnic School of the University of São Paulo (Poli-USP) and Jon "Maddog" Hall. Signed-off-by: Matheus Castello Acked-by: Rob Herring Reviewed-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2baee2c817c1..750aa03f63cc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -179,6 +179,8 @@ patternProperties: description: CALAO Systems SAS "^calxeda,.*": description: Calxeda + "^caninos,.*": + description: Caninos Loucos Program "^capella,.*": description: Capella Microsystems, Inc "^cascoda,.*": -- cgit v1.2.3 From ccc3b1ac4ac65870c02087f0727ea70ba02e3e6b Mon Sep 17 00:00:00 2001 From: Matheus Castello Date: Mon, 21 Sep 2020 23:43:00 -0300 Subject: dt-bindings: arm: actions: Document Caninos Loucos Labrador Update the documentation to add the Caninos Loucos Labrador. Labrador project consists of the computer on module Core v2 based on the Actions Semi S500, computer on module Core v3 based on the Actions Semi S700 and the Labrador base boards. Signed-off-by: Matheus Castello Acked-by: Rob Herring Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/actions.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/actions.yaml b/Documentation/devicetree/bindings/arm/actions.yaml index ace3fdaa8396..1cc66803ce2a 100644 --- a/Documentation/devicetree/bindings/arm/actions.yaml +++ b/Documentation/devicetree/bindings/arm/actions.yaml @@ -19,6 +19,11 @@ properties: - allo,sparky # Allo.com Sparky - cubietech,cubieboard6 # Cubietech CubieBoard6 - const: actions,s500 + - items: + - enum: + - caninos,labrador-base-m # Labrador Base Board M v1 + - const: caninos,labrador-v2 # Labrador Core v2 + - const: actions,s500 - items: - enum: - lemaker,guitar-bb-rev-b # LeMaker Guitar Base Board rev. B @@ -26,6 +31,11 @@ properties: - const: actions,s500 # The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC. + - items: + - enum: + - caninos,labrador-base-m2 # Labrador Base Board M v2 + - const: caninos,labrador-v3 # Labrador Core v3 + - const: actions,s700 - items: - enum: - cubietech,cubieboard7 # Cubietech CubieBoard7 -- cgit v1.2.3 From dde8a1e4426d0c2816162602eb4c9ebba26398ec Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 28 Aug 2020 16:53:18 +0300 Subject: dt-bindings: Add vendor prefix for RoseapplePi.org Add devicetree vendor prefix for RoseapplePi.org Foundation. Website: http://roseapplepi.org/ Signed-off-by: Cristian Ciocaltea Acked-by: Rob Herring Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 750aa03f63cc..8c6832e95103 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -896,6 +896,8 @@ patternProperties: description: Ronbo Electronics "^roofull,.*": description: Shenzhen Roofull Technology Co, Ltd + "^roseapplepi,.*": + description: RoseapplePi.org "^samsung,.*": description: Samsung Semiconductor "^samtec,.*": -- cgit v1.2.3 From 494eebdc7e9089021192d1642d7c6d542dbc8ec8 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 28 Aug 2020 16:53:19 +0300 Subject: dt-bindings: arm: actions: Document RoseapplePi Define compatible strings for RoseapplePi, a SBC manufactured in Taiwan, based on Actions Semi S500 reference design. Signed-off-by: Cristian Ciocaltea Reviewed-by: Rob Herring Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/actions.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/actions.yaml b/Documentation/devicetree/bindings/arm/actions.yaml index 1cc66803ce2a..9dd6bd067f4a 100644 --- a/Documentation/devicetree/bindings/arm/actions.yaml +++ b/Documentation/devicetree/bindings/arm/actions.yaml @@ -18,6 +18,7 @@ properties: - enum: - allo,sparky # Allo.com Sparky - cubietech,cubieboard6 # Cubietech CubieBoard6 + - roseapplepi,roseapplepi # RoseapplePi.org RoseapplePi - const: actions,s500 - items: - enum: -- cgit v1.2.3 From 8e5910d2dc391b9e8e3e5831b3524f32c419ef18 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 19 Sep 2020 16:13:30 +0200 Subject: dt-bindings: arm: fsl: Add binding for Variscite Symphony board with VAR-SOM-MX8MN Add a binding for the Variscite Symphony evaluation kit board with VAR-SOM-MX8MN System on Module. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 14b85166d3bb..1ca9dfa8ce9a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -421,6 +421,12 @@ properties: - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - const: fsl,imx8mn + - description: Variscite VAR-SOM-MX8MN based boards + items: + - const: variscite,var-som-mx8mn-symphony + - const: variscite,var-som-mx8mn + - const: fsl,imx8mn + - description: i.MX8MP based Boards items: - enum: -- cgit v1.2.3 From ade0176dd8a0daf4448a817a718263b64913c37c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 19 Sep 2020 16:13:31 +0200 Subject: arm64: dts: imx8mn-var-som: Add Variscite VAR-SOM-MX8MN System on Module Add DTSI of Variscite VAR-SOM-MX8MN (Nano) System on Module in a basic version, delivered with Variscite Symphony Evaluation kit. This version comes with: - 1 GB of RAM, - 16 GB eMMC, - Gigabit Ethernet PHY, - 802.11 ac/a/b/g/n WiFi with 4.2 Bluetooth, - CAN bus, - Audio codec (not yet configured in DTSI). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 551 ++++++++++++++++++++++ 1 file changed, 551 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi new file mode 100644 index 000000000000..a2d0190921e4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -0,0 +1,551 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2019-2020 Variscite Ltd. + * Copyright (C) 2020 Krzysztof Kozlowski + */ + +#include "imx8mn.dtsi" + +/ { + model = "Variscite VAR-SOM-MX8MN module"; + compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; + + chosen { + stdout-path = &uart4; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x40000000>; + }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth_phy>; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, + <&gpio1 0 GPIO_ACTIVE_LOW>; + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + /* Resistive touch controller */ + touchscreen@0 { + reg = <0>; + compatible = "ti,ads7846"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + + ti,x-min = /bits/ 16 <125>; + touchscreen-size-x = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + touchscreen-size-y = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + touchscreen-max-pressure = /bits/ 16 <255>; + touchscreen-average-samples = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + phy-supply = <®_eth_phy>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + /* + * The interrupt is not correct. It should be level low, + * however with internal pull up this causes IRQ storm. + */ + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /* TODO: configure audio, as of now just put a placeholder */ + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + status = "disabled"; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* Bluetooth */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MN_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; +}; + +/* WIFI */ +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD */ +&usdhc2 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 + MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 + MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_fec1_sleep: fec1sleepgrp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 + MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 + MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 + MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 + MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 + MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 + MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 + MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 + MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 + MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 + MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 + MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 + MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 + MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x101 + >; + }; + + pinctrl_reg_eth_phy: regethphygrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- cgit v1.2.3 From 7358e05bddca16ec230596d218df62f998e310ae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 19 Sep 2020 16:13:32 +0200 Subject: arm64: dts: imx8mn-var-som-symphony: Add Variscite Symphony board with VAR-SOM-MX8MN Add a basic DTS for Variscite Symphony evaluation kit with VAR-SOM-MX8MN (i.MX 8M Nano) System on Module. This brings up the board with basic functionalities although still few issues remain (e.g. I2C3 and USB OTG port, although it might not be the problem of DTS). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mn-var-som-symphony.dts | 240 +++++++++++++++++++++ 2 files changed, 241 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 54b7a345d0e4..c7890b622587 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts new file mode 100644 index 000000000000..f61c48776cf3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019-2020 Variscite Ltd. + * Copyright (C) 2020 Krzysztof Kozlowski + */ + +/dts-v1/; + +#include "imx8mn-var-som.dtsi" + +/ { + model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; + compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn"; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + back { + label = "Back"; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + menu { + label = "Menu"; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "Heartbeat"; + gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +ðphy { + reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + wakeup-source; + + /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ + usb3-sata-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "usb3_sata_sel"; + }; + + som-vselect-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "som_vselect"; + }; + + enet-sel-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "enet_sel"; + }; + }; + + extcon_usbotg1: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + status = "okay"; + }; +}; + +&i2c3 { + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +/* Header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; +}; + +&pinctrl_fec1 { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ + >; +}; + +&pinctrl_fec1_sleep { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 + MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 + MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 + MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 + MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 + MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 + MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 + MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 + MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 + MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 + MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 + MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 + MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 + MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 + /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ + >; +}; + +&iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 + >; + }; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; +}; -- cgit v1.2.3 From f7d48ffcfc6efc6dc35ef34f4415b311a08d0840 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Sun, 13 Sep 2020 10:51:16 +0530 Subject: arm64: dts: layerscape: Add label to pcie nodes Add label to pcie nodes so that they are easy to refer. Signed-off-by: Wasim Khan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 5 +++-- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++---- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 12 ++++++------ 7 files changed, 30 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts index 9927b096d343..242f4b0cb344 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts @@ -87,7 +87,7 @@ status = "okay"; }; -&pcie { +&pcie1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ff19ec415b60..6a2c09199047 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -1,8 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree Include file for Freescale Layerscape-1012A family SoC. + * Device Tree Include file for NXP Layerscape-1012A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019-2020 NXP * */ @@ -489,7 +490,7 @@ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; }; - pcie: pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls1012a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 13c0163939ad..73e4f9466887 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Include file for NXP Layerscape-1028A family SoC. * - * Copyright 2018 NXP + * Copyright 2018-2020 NXP * * Harninder Rai * @@ -553,7 +553,7 @@ status = "disabled"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls1028a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -580,7 +580,7 @@ status = "disabled"; }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls1028a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 5c2e370f6316..0464b8aa4bc4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -1,9 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * Device Tree Include file for NXP Layerscape-1043A family SoC. * * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * * Mingkai Hu */ @@ -814,7 +814,7 @@ interrupts = <0 160 0x4>; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls1043a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -840,7 +840,7 @@ status = "disabled"; }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls1043a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -866,7 +866,7 @@ status = "disabled"; }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls1043a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 0246d975a206..1fa39bacff4b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -1,9 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * Device Tree Include file for NXP Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * * Mingkai Hu */ @@ -718,7 +718,7 @@ ; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls1046a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -744,7 +744,7 @@ status = "disabled"; }; - pcie_ep@3400000 { + pcie_ep1: pcie_ep@3400000 { compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; reg = <0x00 0x03400000 0x0 0x00100000 0x40 0x00000000 0x8 0x00000000>; @@ -754,7 +754,7 @@ status = "disabled"; }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls1046a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -780,7 +780,7 @@ status = "disabled"; }; - pcie_ep@3500000 { + pcie_ep2: pcie_ep@3500000 { compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; reg = <0x00 0x03500000 0x0 0x00100000 0x48 0x00000000 0x8 0x00000000>; @@ -790,7 +790,7 @@ status = "disabled"; }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls1046a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -816,7 +816,7 @@ status = "disabled"; }; - pcie_ep@3600000 { + pcie_ep3: pcie_ep@3600000 { compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; reg = <0x00 0x03600000 0x0 0x00100000 0x50 0x00000000 0x8 0x00000000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index c909ad12cfec..28f44ac96ca7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Include file for NXP Layerscape-1088A family SoC. * - * Copyright 2017 NXP + * Copyright 2017-2020 NXP * * Harninder Rai * @@ -491,7 +491,7 @@ }; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -517,7 +517,7 @@ status = "disabled"; }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -543,7 +543,7 @@ status = "disabled"; }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index d247e4228d60..83072da6f6c6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1011,7 +1011,7 @@ status = "disabled"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -1039,7 +1039,7 @@ status = "disabled"; }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -1067,7 +1067,7 @@ status = "disabled"; }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -1095,7 +1095,7 @@ status = "disabled"; }; - pcie@3700000 { + pcie4: pcie@3700000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -1123,7 +1123,7 @@ status = "disabled"; }; - pcie@3800000 { + pcie5: pcie@3800000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -1151,7 +1151,7 @@ status = "disabled"; }; - pcie@3900000 { + pcie6: pcie@3900000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ -- cgit v1.2.3 From d367e7d3351edc526133e4bd258dac2dd0b4ef4f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 14 Sep 2020 11:38:46 -0300 Subject: arm64: dts: imx8mq-evk: Add MIPI DSI support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit imx8mq-evk has a MIPI DSI port that can be used to connect a Raydium RM67191 panel. Add support for it. Signed-off-by: Fabio Estevam Acked-by: Guido Günther Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 7c6808814856..2418cca00bc5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -132,6 +132,10 @@ }; }; +&dphy { + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -255,6 +259,40 @@ }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + pinctrl-0 = <&pinctrl_mipi_dsi>; + pinctrl-names = "default"; + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; @@ -388,6 +426,12 @@ >; }; + pinctrl_mipi_dsi: mipidsigrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 -- cgit v1.2.3 From c86e4202fde491e5fa578a3bf3bcfd056441e18d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 14 Sep 2020 23:43:37 +0200 Subject: arm64: dts: freescale: sl28: enable sl28cpld Add the board management controller node. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../dts/freescale/fsl-ls1028a-kontron-sl28.dts | 102 +++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 852dad8d70ab..5fdf4ec8b39f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "fsl-ls1028a.dtsi" +#include / { model = "Kontron SMARC-sAL28"; @@ -166,6 +167,107 @@ reg = <0x32>; }; + sl28cpld@4a { + compatible = "kontron,sl28cpld"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + + watchdog@4 { + compatible = "kontron,sl28cpld-wdt"; + reg = <0x4>; + kontron,assert-wdt-timeout-pin; + }; + + hwmon@b { + compatible = "kontron,sl28cpld-fan"; + reg = <0xb>; + }; + + sl28cpld_pwm0: pwm@c { + compatible = "kontron,sl28cpld-pwm"; + reg = <0xc>; + #pwm-cells = <2>; + }; + + sl28cpld_pwm1: pwm@e { + compatible = "kontron,sl28cpld-pwm"; + reg = <0xe>; + #pwm-cells = <2>; + }; + + sl28cpld_gpio0: gpio@10 { + compatible = "kontron,sl28cpld-gpio"; + reg = <0x10>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N", + "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N", + "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT", + "GPIO6_TACHIN", "GPIO7"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sl28cpld_gpio1: gpio@15 { + compatible = "kontron,sl28cpld-gpio"; + reg = <0x15>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GPIO8", "GPIO9", "GPIO10", "GPIO11", + "", "", "", ""; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sl28cpld_gpio2: gpio@1a { + compatible = "kontron,sl28cpld-gpo"; + reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "LCD0 voltage enable", + "LCD0 backlight enable", + "eMMC reset", "LVDS bridge reset", + "LVDS bridge power-down", + "SDIO power enable", + "", ""; + }; + + sl28cpld_gpio3: gpio@1b { + compatible = "kontron,sl28cpld-gpi"; + reg = <0x1b>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "Power button", "Force recovery", "Sleep", + "Battery low", "Lid state", "Charging", + "Charger present", ""; + }; + + sl28cpld_intc: interrupt-controller@1c { + compatible = "kontron,sl28cpld-intc"; + reg = <0x1c>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; -- cgit v1.2.3 From 945710bbdbdf6c44f467b705c327556efee67b04 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 14 Sep 2020 23:43:38 +0200 Subject: arm64: dts: freescale: sl28: map GPIOs to input events Now that we have support for GPIO lines of the SMARC connector, map the sleep, power and lid switch signals to the corresponding keys using the gpio-keys and gpio-keys-polled drivers. The power and sleep signals have dedicated interrupts, thus we use these ones. The lid switch is just mapped to a GPIO input and needs polling. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../dts/freescale/fsl-ls1028a-kontron-sl28.dts | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 5fdf4ec8b39f..f46eb47cfa4d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -9,6 +9,8 @@ /dts-v1/; #include "fsl-ls1028a.dtsi" #include +#include +#include / { model = "Kontron SMARC-sAL28"; @@ -23,6 +25,36 @@ spi1 = &dspi2; }; + buttons0 { + compatible = "gpio-keys"; + + power-button { + interrupts-extended = <&sl28cpld_intc + 4 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "Power"; + }; + + sleep-button { + interrupts-extended = <&sl28cpld_intc + 5 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "Sleep"; + }; + }; + + buttons1 { + compatible = "gpio-keys-polled"; + poll-interval = <200>; + + lid-switch { + linux,input-type = ; + linux,code = ; + gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>; + label = "Lid"; + }; + }; + chosen { stdout-path = "serial0:115200n8"; }; -- cgit v1.2.3 From 3672d6fa6eae5c09345a32163516df51b9f78dff Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 14 Sep 2020 23:43:39 +0200 Subject: arm64: dts: freescale: sl28: enable LED support Now that we have support for GPIO lines of the SMARC connector, enable LED support on the KBox A-230-LS. There are two LEDs without fixed functions, one is yellow and one is green. Unfortunately, it is just one multi-color LED, thus while it is possible to enable both at the same time it is hard to tell the difference between "yellow only" and "yellow and green". Signed-off-by: Michael Walle Acked-by: Pavel Machek Signed-off-by: Shawn Guo --- .../freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts index 4b4cc6a1573d..d66d8b2c3d1a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts @@ -11,11 +11,29 @@ /dts-v1/; #include "fsl-ls1028a-kontron-sl28-var4.dts" +#include / { model = "Kontron KBox A-230-LS"; compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; + + leds { + compatible = "gpio-leds"; + + alarm-led { + function = LED_FUNCTION_ALARM; + color = ; + gpios = <&sl28cpld_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + power-led { + linux,default-trigger = "default-on"; + function = LED_FUNCTION_POWER; + color = ; + gpios = <&sl28cpld_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + }; }; &enetc_mdio_pf3 { -- cgit v1.2.3 From 499b7678758637ce47fa270fcb36d2c8e1c9fbc1 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 14 Sep 2020 23:43:40 +0200 Subject: arm64: dts: freescale: sl28: enable fan support Add a pwm-fan mapped to the PWM channel 0 which is connected to the fan connector of the carrier. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts index 0973a6a45217..c45d7b40e374 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts @@ -15,6 +15,15 @@ compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a"; + pwm-fan { + compatible = "pwm-fan"; + cooling-min-state = <0>; + cooling-max-state = <3>; + #cooling-cells = <2>; + pwms = <&sl28cpld_pwm0 0 4000000>; + cooling-levels = <1 128 192 255>; + }; + sound { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From f3cbcbbb4b38eb73917591b9c4fea014b167db98 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Tue, 22 Sep 2020 11:31:46 +0800 Subject: arm64: dts: layerscape: correct watchdog clocks for LS1088A On LS1088A, watchdog clk are divided by 16, correct it in dts. Signed-off-by: Zhao Qiang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 28f44ac96ca7..ff5805206a28 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -675,56 +675,56 @@ cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: wdt@c010000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core2_watchdog: wdt@c020000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc020000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core3_watchdog: wdt@c030000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc030000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core0_watchdog: wdt@c100000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core1_watchdog: wdt@c110000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core2_watchdog: wdt@c120000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc120000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core3_watchdog: wdt@c130000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc130000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; clock-names = "wdog_clk", "apb_pclk"; }; -- cgit v1.2.3 From 1d93b292af67e1848a87991c59be6929187cba23 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:41:31 +0200 Subject: arm64: dts: imx8mm-var-som-symphony: fix ptn5150 interrupts Conversion of int-gpios into interrupts property requires also interrupt-parent and uses different flags. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index daaed1a525a9..6f998d57aafa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -113,7 +113,8 @@ extcon_usbotg1: typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; - interrupts = <&gpio1 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; status = "okay"; -- cgit v1.2.3 From 5f67317bd967bbdde945ce3a586d3841f8a5bf65 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:54:47 +0200 Subject: arm64: dts: imx8mm: correct interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW ACTIVE_HIGH => IRQ_TYPE_LEVEL_HIGH In case of level low interrupts, enable also internal pull up. It is required at least on imx8mm-evk, according to schematics. The schematics for Variscite imx8mm-var-som are not available and I was unable to get proper configuration from Variscite. Signed-off-by: Krzysztof Kozlowski Acked-By: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 6 +++++- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 502faf6144b0..6de86a4f0ec4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -74,7 +74,7 @@ reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { @@ -292,7 +292,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index f572b7d207f4..f305a530ff6f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -123,7 +123,7 @@ reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; #clock-cells = <0>; @@ -392,7 +392,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 6f998d57aafa..5313dd7b8ded 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -129,7 +129,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_captouch>; interrupt-parent = <&gpio5>; - interrupts = <4 GPIO_ACTIVE_HIGH>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; touchscreen-size-x = <800>; touchscreen-size-y = <480>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 9c6e91243ba0..4107fe914d08 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -137,7 +137,11 @@ reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio2>; - interrupts = <8 GPIO_ACTIVE_LOW>; + /* + * The interrupt is not correct. It should be level low, + * however with internal pull up this causes IRQ storm. + */ + interrupts = <8 IRQ_TYPE_EDGE_RISING>; rohm,reset-snvs-powered; #clock-cells = <0>; -- cgit v1.2.3 From 4153f7811a9b2b6f65f9ba5470d4f3e020ad1b7c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:54:48 +0200 Subject: arm64: dts: imx8mn: correct interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW For level low interrupts, enable also internal pull up. It is required at least on imx8mm-evk, according to schematics. Signed-off-by: Krzysztof Kozlowski Acked-By: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 3 ++- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 68fa943ea8d8..46e76cf32b2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -55,7 +55,7 @@ reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index b846526a8d8b..707d8486b4d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -7,6 +7,7 @@ #include "imx8mn.dtsi" #include "imx8mn-evk.dtsi" +#include / { model = "NXP i.MX8MNano EVK board"; @@ -19,7 +20,7 @@ reg = <0x25>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; regulators { buck1: BUCK1{ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 7f4b904e9982..4aa0dbd578df 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -225,7 +225,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; -- cgit v1.2.3 From d8fa4792dad3abc723644d5dd9dd94853593d072 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:54:49 +0200 Subject: arm64: dts: imx8mq: correct interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW Signed-off-by: Krzysztof Kozlowski Acked-By: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 5 +++-- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 3 ++- arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 3 ++- arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts | 3 ++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index cce1b595e2d6..af139b283daf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "dt-bindings/input/input.h" +#include #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/usb/pd.h" #include "imx8mq.dtsi" @@ -60,7 +61,7 @@ label = "WWAN_WAKE"; gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; - interrupts = <8 GPIO_ACTIVE_LOW>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; wakeup-source; linux,code = ; }; @@ -288,7 +289,7 @@ #clock-cells = <0>; clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 56295dd2fa8f..0c13b70192af 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include "dt-bindings/input/input.h" +#include #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/usb/pd.h" #include "imx8mq.dtsi" @@ -640,7 +641,7 @@ clock-names = "osc"; clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; - interrupts = <7 GPIO_ACTIVE_LOW>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts index d6d3a3d5abc3..a3b9d615a3b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx8mq.dtsi" +#include / { model = "Google i.MX8MQ Phanbell"; @@ -125,7 +126,7 @@ clocks = <&pmic_osc>; clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; regulators { buck1: BUCK1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts index f4d5748a7bd6..89cbec5c41b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "imx8mq.dtsi" +#include / { model = "TechNexion PICO-PI-8M"; @@ -70,7 +71,7 @@ clock-names = "osc"; clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; regulators { -- cgit v1.2.3 From ac938aa9aec46db5914b089a8d3f018f2b37ec79 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 19 Sep 2020 16:06:47 +0200 Subject: arm64: dts: imx8mm-var-som-symphony: Drop wake-up source from RTC The RTC on Symphony board does not have its interrupt pin connected to the SoC, therefore it is not capable of waking up. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 5313dd7b8ded..ac1fe1530ac7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -140,7 +140,6 @@ rtc@68 { compatible = "dallas,ds1337"; reg = <0x68>; - wakeup-source; }; }; -- cgit v1.2.3 From 912a6e2ef6dd895929e910e1c4025a0f34b743b6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 20 Sep 2020 21:57:47 +0200 Subject: arm64: dts: imx8mq-librem5: correct GPIO hog property Correct the name of property for GPIO specifier in GPIO hog. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 0c13b70192af..e3c6d1272198 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -252,7 +252,7 @@ pmic-5v { gpio-hog; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; input; }; }; -- cgit v1.2.3 From 4e5833884f6656042eb100e9bcd68072e3338b25 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Sep 2020 20:51:14 +0530 Subject: arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes Add PCIe device tree nodes (both RC and EP) for the four PCIe instances here. Also add the missing translations required in the "ranges" DT property of cbass_main to access all the four PCIe instances. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200914152115.1788-2-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 232 +++++++++++++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- 2 files changed, 235 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index ea57d07777ba..824ccd7a414d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -28,7 +28,39 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - serdes_ln_ctrl: serdes-ln-ctrl@4080 { + pcie0_ctrl: syscon@4070 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004070 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4070 0x4070 0x4>; + }; + + pcie1_ctrl: syscon@4074 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4074 0x4074 0x4>; + }; + + pcie2_ctrl: syscon@4078 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004078 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4078 0x4078 0x4>; + }; + + pcie3_ctrl: syscon@407c { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x0000407c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x407c 0x407c 0x4>; + }; + + serdes_ln_ctrl: mux@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; #mux-control-cells = <1>; @@ -576,6 +608,204 @@ }; }; + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie2_rc: pcie@2920000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x20000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie2_ep: pcie-ep@2920000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie3_rc: pcie@2930000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x30000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie3_ep: pcie-ep@2930000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + #address-cells = <2>; + #size-cells = <2>; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 1bb8235d9ffb..cc483f7344af 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -132,9 +132,12 @@ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ -- cgit v1.2.3 From 66db854b1f62dbee48ec7373f149fa30e4b3dd4e Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Sep 2020 20:51:15 +0530 Subject: arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances J721E Common Processor Board has PCIe connectors for the 1st three PCIe instances. Configure the three PCIe instances in RC mode and disable the 4th PCIe instance. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200914152115.1788-3-kishon@ti.com --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 648267284582..f35a5d5b1cd8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -558,3 +558,83 @@ status = "okay"; }; + +&serdes0 { + serdes0_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&serdes2 { + serdes2_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie2_rc { + reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; + phys = <&serdes2_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; + +&pcie1_ep { + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; + +&pcie2_ep { + phys = <&serdes2_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; + +&pcie3_rc { + status = "disabled"; +}; + +&pcie3_ep { + status = "disabled"; +}; -- cgit v1.2.3 From 8cfcf3279419acbf2d2c471262bfb18d9e175fc9 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sun, 20 Sep 2020 17:45:27 +0200 Subject: dt-bindings: Add doc for FriendlyARM NanoPi R2S Add devicetree binding documentation for the FriendlyARM NanoPi R2S. Signed-off-by: David Bauer Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200920154528.88185-1-mail@david-bauer.net Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 251c3ca22e1b..65b4cc2c63f7 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -104,6 +104,11 @@ properties: - firefly,roc-rk3399-pc-mezzanine - const: rockchip,rk3399 + - description: FriendlyElec NanoPi R2S + items: + - const: friendlyarm,nanopi-r2s + - const: rockchip,rk3328 + - description: FriendlyElec NanoPi4 series boards items: - enum: -- cgit v1.2.3 From f1ec83f880dbeaceb10d33c40c47aa1769b787e8 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sun, 20 Sep 2020 17:45:28 +0200 Subject: arm64: dts: rockchip: Add support for FriendlyARM NanoPi R2S This adds support for the NanoPi R2S from FriendlyARM. Rockchip RK3328 SoC 1GB DDR4 RAM Gigabit Ethernet (WAN) Gigabit Ethernet (USB3) (LAN) USB 2.0 Host Port MicroSD slot Reset button WAN - LAN - SYS LED Signed-off-by: David Bauer Link: https://lore.kernel.org/r/20200920154528.88185-2-mail@david-bauer.net [adapted from sdmmc0m1_gpio to renamed sdmmc0m1_pin] Reported-by: kernel test robot Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 368 +++++++++++++++++++++ 2 files changed, 369 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d53efdf4cb5a..26661c7b736b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts new file mode 100644 index 000000000000..be7a31d81632 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 David Bauer + */ + +/dts-v1/; + +#include +#include +#include "rk3328.dtsi" + +/ { + model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clk"; + #clock-cells = <0>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&reset_button_pin>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; + + lan_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:lan"; + }; + + sys_led: led-1 { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:red:sys"; + }; + + wan_led: led-2 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:wan"; + }; + }; + + vcc_io_sdio: sdmmcio-regulator { + compatible = "regulator-gpio"; + enable-active-high; + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdio_vcc_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_io_sdio"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-settling-time-us = <5000>; + regulator-type = "voltage"; + startup-delay-us = <2000>; + states = <1800000 0x1 + 3300000 0x0>; + vin-supply = <&vcc_io_33>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io_33>; + }; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; + phy-supply = <&vcc_io_33>; + pinctrl-0 = <&rgmiim1_pins>; + pinctrl-names = "default"; + rx_delay = <0x18>; + snps,aal; + tx_delay = <0x24>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pmic_int_l>; + pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vdd_5v>; + vcc2-supply = <&vdd_5v>; + vcc3-supply = <&vdd_5v>; + vcc4-supply = <&vdd_5v>; + vcc5-supply = <&vcc_io_33>; + vcc6-supply = <&vdd_5v>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io_33: DCDC_REG4 { + regulator-name = "vcc_io_33"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + pmuio-supply = <&vcc_io_33>; + vccio1-supply = <&vcc_io_33>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io_sdio>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io_33>; + vccio6-supply = <&vcc_io_33>; + status = "okay"; +}; + +&pinctrl { + button { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet-phy { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sd { + sdio_vcc_pin: sdio-vcc-pin { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_io_sdio>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; -- cgit v1.2.3 From b3ff08bc9ba6a2047d7a5812e89a5187cf3e4aa4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 27 Apr 2020 09:10:40 +0900 Subject: dt-bindings: arm: toshiba: add Toshiba Visconti ARM SoCs Add device tree bindings for the Toshiba Visconti ARM SoCs. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/toshiba.yaml | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/toshiba.yaml diff --git a/Documentation/devicetree/bindings/arm/toshiba.yaml b/Documentation/devicetree/bindings/arm/toshiba.yaml new file mode 100644 index 000000000000..efd3f4859669 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/toshiba.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/toshiba.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti Platform Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Visconti5 TMPV7708 + items: + - const: toshiba,tmpv7708 +... -- cgit v1.2.3 From a1fd0c367be3a7fd3c19f08aed4126d7cda1ba11 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Wed, 22 Jul 2020 10:50:46 +0900 Subject: dt-bindings: arm: toshiba: Add the TMPV7708 RM main board Add an entry for the Toshiba Visconti TMPV7708 RM main board (tmpv7708-rm-mbrc) to the board/SoC bindings. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/toshiba.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/toshiba.yaml b/Documentation/devicetree/bindings/arm/toshiba.yaml index efd3f4859669..0e066290238e 100644 --- a/Documentation/devicetree/bindings/arm/toshiba.yaml +++ b/Documentation/devicetree/bindings/arm/toshiba.yaml @@ -16,5 +16,7 @@ properties: oneOf: - description: Visconti5 TMPV7708 items: + - enum: + - toshiba,tmpv7708-rm-mbrc # TMPV7708 RM main board - const: toshiba,tmpv7708 ... -- cgit v1.2.3 From 0aa56c7eba9ab7b7661b165f3b7dc4e73a4fb1ef Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 28 Apr 2020 05:58:48 +0900 Subject: arm64: visconti: Add initial support for Toshiba Visconti platform Add the initial device tree files for Toshiba Visconti platform. For starters, the only SoC supported will be Visconti5 TMPV7708. https://toshiba.semicon-storage.com/ap-en/semiconductor/product/image-recognition-processors-visconti.html Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal --- arch/arm64/Kconfig.platforms | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index cd58f8495c45..dce74d34d18a 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -300,6 +300,13 @@ config ARCH_VEXPRESS This enables support for the ARMv8 software model (Versatile Express). +config ARCH_VISCONTI + bool "Toshiba Visconti SoC Family" + select PINCTRL + select PINCTRL_VISCONTI + help + This enables support for Toshiba Visconti SoCs Family. + config ARCH_VULCAN def_bool n -- cgit v1.2.3 From 48dea9a700c8728cc31a1dd44588b97578de86ee Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 28 Apr 2020 05:59:12 +0900 Subject: arm64: dts: visconti: Add device tree for TMPV7708 RM main board Add basic support for the Visconti TMPV7708 SoC peripherals - - CPU - CA53 x 4 and 2 cluster. - not support PSCI, currently only spin-table is supported. - Interrupt controller (ARM Generic Interrupt Controller) - Timer (ARM architected timer) - UART (ARM PL011 UART controller) - SPI (ARM PL022 SPI controller) - I2C (Synopsys DesignWare APB I2C Controller) - Pin control (Visconti specific) Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/toshiba/Makefile | 2 + arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 43 +++ arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 390 +++++++++++++++++++++++ arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 93 ++++++ 5 files changed, 529 insertions(+) create mode 100644 arch/arm64/boot/dts/toshiba/Makefile create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 270e8aabbac8..9b1170658d60 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -27,5 +27,6 @@ subdir-y += socionext subdir-y += sprd subdir-y += synaptics subdir-y += ti +subdir-y += toshiba subdir-y += xilinx subdir-y += zte diff --git a/arch/arm64/boot/dts/toshiba/Makefile b/arch/arm64/boot/dts/toshiba/Makefile new file mode 100644 index 000000000000..8cd460d5b68e --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts new file mode 100644 index 000000000000..ed0bf7f13f54 --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree File for TMPV7708 RM main board + * + * (C) Copyright 2020, Toshiba Corporation. + * (C) Copyright 2020, Nobuhiro Iwamatsu + */ + +/dts-v1/; + +#include "tmpv7708.dtsi" + +/ { + model = "Toshiba TMPV7708 RM main board"; + compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* 768MB memory */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x30000000>; + }; +}; + +&uart0 { + status = "okay"; + clocks = <&uart_clk>; + clock-names = "apb_pclk"; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; + clock-names = "apb_pclk"; +}; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi new file mode 100644 index 000000000000..242f25f4e12a --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for the TMPV7708 + * + * (C) Copyright 2018 - 2020, Toshiba Corporation. + * (C) Copyright 2020, Nobuhiro Iwamatsu + * + */ + +#include +#include + +/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ + +/ { + compatible = "toshiba,tmpv7708"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x00>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x01>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x02>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x03>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x100>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x101>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x102>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x81100000>; + reg = <0x103>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = + , + , + , + ; + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + gic: interrupt-controller@24001000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + reg = <0 0x24001000 0 0x1000>, + <0 0x24002000 0 0x2000>, + <0 0x24004000 0 0x2000>, + <0 0x24006000 0 0x2000>; + }; + + pmux: pmux@24190000 { + compatible = "toshiba,tmpv7708-pinctrl"; + reg = <0 0x24190000 0 0x10000>; + }; + + uart0: serial@28200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28200000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "disabled"; + }; + + uart1: serial@28201000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28201000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; + }; + + uart2: serial@28202000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28202000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; + }; + + uart3: serial@28203000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x28203000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; + }; + + i2c0: i2c@28030000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28030000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@28031000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28031000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@28032000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28032000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@28033000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28033000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@28034000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28034000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@28035000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28035000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@28036000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28036000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@28037000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28037000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@28038000 { + compatible = "snps,designware-i2c"; + reg = <0 0x28038000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_pins>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@28140000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28140000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@28141000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28141000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@28142000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28142000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@28143000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28143000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@28144000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28144000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@28145000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28145000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@28146000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0 0x28146000 0 0x1000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi6_pins>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; + +#include "tmpv7708_pins.dtsi" diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi new file mode 100644 index 000000000000..34de00015a7f --- /dev/null +++ b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&pmux { + spi0_pins: spi0-pins { + function = "spi0"; + groups = "spi0_grp"; + }; + spi1_pins: spi1-pins { + function = "spi1"; + groups = "spi1_grp"; + }; + spi2_pins: spi2-pins { + function = "spi2"; + groups = "spi2_grp"; + }; + spi3_pins: spi3-pins { + function = "spi3"; + groups = "spi3_grp"; + }; + spi4_pins: spi4-pins { + function = "spi4"; + groups = "spi4_grp"; + }; + spi5_pins: spi5-pins { + function = "spi5"; + groups = "spi5_grp"; + }; + spi6_pins: spi6-pins { + function = "spi6"; + groups = "spi6_grp"; + }; + uart0_pins: uart0-pins { + function = "uart0"; + groups = "uart0_grp"; + }; + uart1_pins: uart1-pins { + function = "uart1"; + groups = "uart1_grp"; + }; + uart2_pins: uart2-pins { + function = "uart2"; + groups = "uart2_grp"; + }; + uart3_pins: uart3-pins { + function = "uart3"; + groups = "uart3_grp"; + }; + i2c0_pins: i2c0-pins { + function = "i2c0"; + groups = "i2c0_grp"; + bias-pull-up; + }; + i2c1_pins: i2c1-pins { + function = "i2c1"; + groups = "i2c1_grp"; + bias-pull-up; + }; + i2c2_pins: i2c2-pins { + function = "i2c2"; + groups = "i2c2_grp"; + bias-pull-up; + }; + i2c3_pins: i2c3-pins { + function = "i2c3"; + groups = "i2c3_grp"; + bias-pull-up; + }; + i2c4_pins: i2c4-pins { + function = "i2c4"; + groups = "i2c4_grp"; + bias-pull-up; + }; + i2c5_pins: i2c5-pins { + function = "i2c5"; + groups = "i2c5_grp"; + bias-pull-up; + }; + i2c6_pins: i2c6-pins { + function = "i2c6"; + groups = "i2c6_grp"; + bias-pull-up; + }; + i2c7_pins: i2c7-pins { + function = "i2c7"; + groups = "i2c7_grp"; + bias-pull-up; + }; + i2c8_pins: i2c8-pins { + function = "i2c8"; + groups = "i2c8_grp"; + bias-pull-up; + }; +}; -- cgit v1.2.3 From 836863a08c99dec42337fde0d4f4620fcac69f20 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 27 Apr 2020 10:36:01 +0900 Subject: MAINTAINERS: Add information for Toshiba Visconti ARM SoCs Add information about Toshiba Visconti ARM SoCs to MAINTAINERS. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal --- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f0068bceeb61..cbc445ab2cc4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2651,6 +2651,17 @@ M: Dmitry Eremin-Solenikov M: Dirk Opfer S: Maintained +ARM/TOSHIBA VISCONTI ARCHITECTURE +M: Nobuhiro Iwamatsu +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git +F: Documentation/devicetree/bindings/arm/toshiba.yaml +F: Documentation/devicetree/bindings/pinctrl/toshiba,tmpv7700-pinctrl.yaml +F: arch/arm64/boot/dts/toshiba/ +F: drivers/pinctrl/visconti/ +N: visconti + ARM/UNIPHIER ARCHITECTURE M: Masahiro Yamada L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- cgit v1.2.3 From c29900d50f4445e25a8e70dbd794bcc51d531639 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 28 Apr 2020 06:47:04 +0900 Subject: arm64: defconfig: Enable configs for Toshiba Visconti Enable support for the Toshiba Visconti SoCs. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e0f33826819f..8faadd68f859 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -57,6 +57,7 @@ CONFIG_ARCH_THUNDER=y CONFIG_ARCH_THUNDER2=y CONFIG_ARCH_UNIPHIER=y CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_VISCONTI=y CONFIG_ARCH_XGENE=y CONFIG_ARCH_ZX=y CONFIG_ARCH_ZYNQMP=y -- cgit v1.2.3 From 5d71f44569941386b419398463166fdf1785f4e2 Mon Sep 17 00:00:00 2001 From: Artem Lapkin Date: Wed, 23 Sep 2020 21:08:22 +0800 Subject: arm64: dts: rockchip: add spiflash node to rk3399-khadas-edge The Khadas Edge Boards uses winbond - w25q128 spi flash with 104Mhz Signed-off-by: Artem Lapkin Link: https://lore.kernel.org/r/20200923130823.1612533-2-art@khadas.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi index e36837c04dc7..c67420578fac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -690,6 +690,16 @@ status = "okay"; }; +&spi1 { + status = "okay"; + + spiflash: flash@0 { + compatible = "winbond,w25q128fw", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + }; +}; + &tcphy0 { status = "okay"; }; -- cgit v1.2.3 From 30a9a8c16865d37bfc0f1859a398ba1b24eec569 Mon Sep 17 00:00:00 2001 From: Artem Lapkin Date: Wed, 23 Sep 2020 21:08:23 +0800 Subject: arm64: dts: rockchip: add ir-receiver node to rk3399-khadas-edge add missed ir-receiver and ir_rx pinctl nodes to rk3399-khadas-edge Khadas Edge board uses gpio-ir-receiver on RK_PB6 gpio Signed-off-by: Artem Lapkin Link: https://lore.kernel.org/r/20200923130823.1612533-3-art@khadas.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi index c67420578fac..635afdd99122 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -138,6 +138,14 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + linux,rc-map-name = "rc-khadas"; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -585,6 +593,12 @@ }; }; + ir { + ir_rx: ir-rx { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { sys_led_pin: sys-led-pin { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -- cgit v1.2.3 From 21bb8c83c94923f1f996e1cb57c4744ea1163eed Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 14 Sep 2020 21:52:27 +0530 Subject: arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs To allow lesser dependency and better maintainability use CONFIG_ARCH_K3 for building dtbs for all K3 based devices. This is as per the discussion in [0]. [0] https://lore.kernel.org/linux-arm-kernel/20200908112534.t5bgrjf7y3a6l2ss@akan/ Signed-off-by: Lokesh Vutla Signed-off-by: Nishanth Menon Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200914162231.2535-2-lokeshvutla@ti.com --- arch/arm64/boot/dts/ti/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 05c0bebf65d4..7f28be62b8da 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -3,9 +3,9 @@ # Make file to build device tree binaries for boards based on # Texas Instruments Inc processors # -# Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ # -dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb -dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb -- cgit v1.2.3 From 66e06509aa37bcf089ce341ec9c027922f105155 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 14 Sep 2020 21:52:28 +0530 Subject: dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema Convert TI K3 Board/SoC bindings to DT schema format. Signed-off-by: Lokesh Vutla Signed-off-by: Nishanth Menon Reviewed-by: Grygorii Strashko Reviewed-by: Rob Herring Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200914162231.2535-3-lokeshvutla@ti.com --- Documentation/devicetree/bindings/arm/ti/k3.txt | 26 -------------------- Documentation/devicetree/bindings/arm/ti/k3.yaml | 31 ++++++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 32 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt deleted file mode 100644 index 333e7256126a..000000000000 --- a/Documentation/devicetree/bindings/arm/ti/k3.txt +++ /dev/null @@ -1,26 +0,0 @@ -Texas Instruments K3 Multicore SoC architecture device tree bindings --------------------------------------------------------------------- - -Platforms based on Texas Instruments K3 Multicore SoC architecture -shall follow the following scheme: - -SoCs ----- - -Each device tree root node must specify which exact SoC in K3 Multicore SoC -architecture it uses, using one of the following compatible values: - -- AM654 - compatible = "ti,am654"; - -- J721E - compatible = "ti,j721e"; - -Boards ------- - -In addition, each device tree root node must specify which one or more -of the following board-specific compatible values: - -- AM654 EVM - compatible = "ti,am654-evm", "ti,am654"; diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml new file mode 100644 index 000000000000..c5e3e4aeda8e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/k3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 Multicore SoC architecture device tree bindings + +maintainers: + - Nishanth Menon + +description: | + Platforms based on Texas Instruments K3 Multicore SoC architecture + shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: K3 AM654 SoC + items: + - enum: + - ti,am654-evm + - const: ti,am654 + + - description: K3 J721E SoC + items: + - const: ti,j721e +... diff --git a/MAINTAINERS b/MAINTAINERS index e4647c84c987..076fae9aa75b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2636,7 +2636,7 @@ M: Tero Kristo M: Nishanth Menon L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported -F: Documentation/devicetree/bindings/arm/ti/k3.txt +F: Documentation/devicetree/bindings/arm/ti/k3.yaml F: arch/arm64/boot/dts/ti/Makefile F: arch/arm64/boot/dts/ti/k3-* F: include/dt-bindings/pinctrl/k3.h -- cgit v1.2.3 From 214b0eb35e55d9d726ad02ffec62f087c09864fb Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 14 Sep 2020 21:52:29 +0530 Subject: dt-bindings: arm: ti: Add bindings for J7200 SoC The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Lokesh Vutla Signed-off-by: Nishanth Menon Reviewed-by: Grygorii Strashko Reviewed-by: Rob Herring Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200914162231.2535-4-lokeshvutla@ti.com --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index c5e3e4aeda8e..829751209543 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -28,4 +28,8 @@ properties: - description: K3 J721E SoC items: - const: ti,j721e + + - description: K3 J7200 SoC + items: + - const: ti,j7200 ... -- cgit v1.2.3 From d361ed88455feae5f7e555828b0d8104588cc53d Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 14 Sep 2020 21:52:30 +0530 Subject: arm64: dts: ti: Add support for J7200 SoC The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Lokesh Vutla Signed-off-by: Nishanth Menon Reviewed-by: Grygorii Strashko Reviewed-by: Suman Anna Reviewed-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20200914162231.2535-5-lokeshvutla@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 236 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 95 ++++++++++ arch/arm64/boot/dts/ti/k3-j7200.dtsi | 172 +++++++++++++++++ 3 files changed, 503 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi new file mode 100644 index 000000000000..3df49577b06a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J7200 SoC Family Main Domain peripherals + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x70000000 0x100000>; + + atf-sram@0 { + reg = <0x00 0x20000>; + }; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01900000 0x00 0x100000>; /* GICR */ + + /* vcpumntirq: virtual CPU interface maintenance interrupt */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_gpio_intr: interrupt-controller0 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <131>; + ti,interrupt-ranges = <8 392 56>; + }; + + main_navss: bus@30000000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + ti,sci-dev-id = <199>; + + main_navss_intr: interrupt-controller1 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <213>; + ti,interrupt-ranges = <0 64 64>, + <64 448 64>, + <128 672 64>; + }; + + main_udmass_inta: msi-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x33d00000 0x00 0x100000>; + interrupt-controller; + #interrupt-cells = <0>; + interrupt-parent = <&main_navss_intr>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <209>; + ti,interrupt-ranges = <0 0 256>; + }; + + secure_proxy_main: mailbox@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x32c00000 0x00 0x100000>, + <0x00 0x32400000 0x00 0x100000>, + <0x00 0x32800000 0x00 0x100000>; + interrupt-names = "rx_011"; + interrupts = ; + }; + }; + + main_pmx0: pinctrl@11c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x11c000 0x00 0x2b4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 2>; + clock-names = "fclk"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 278 2>; + clock-names = "fclk"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 279 2>; + clock-names = "fclk"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 280 2>; + clock-names = "fclk"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 281 2>; + clock-names = "fclk"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 282 2>; + clock-names = "fclk"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 283 2>; + clock-names = "fclk"; + }; + + main_uart7: serial@2870000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02870000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 284 2>; + clock-names = "fclk"; + }; + + main_uart8: serial@2880000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02880000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 285 2>; + clock-names = "fclk"; + }; + + main_uart9: serial@2890000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02890000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 286 2>; + clock-names = "fclk"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi new file mode 100644 index 000000000000..ec2745e0768e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu_wakeup { + dmsc: dmsc@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + + reg-names = "debug_messages"; + reg = <0x00 0x44083000 0x00 0x1000>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clocks { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + chipid@43000014 { + compatible = "ti,am654-chipid"; + reg = <0x00 0x43000014 0x00 0x4>; + }; + + wkup_pmx0: pinctrl@4301c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c000 0x00 0x178>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + mcu_ram: sram@41c00000 { + compatible = "mmio-sram"; + reg = <0x00 0x41c00000 0x00 0x100000>; + ranges = <0x00 0x00 0x41c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wkup_uart0: serial@42300000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x42300000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 287 2>; + clock-names = "fclk"; + }; + + mcu_uart0: serial@40a00000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <96000000>; + current-speed = <115200>; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 2>; + clock-names = "fclk"; + }; + + wkup_gpio_intr: interrupt-controller2 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <137>; + ti,interrupt-ranges = <16 960 16>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi new file mode 100644 index 000000000000..66169bcf7c9a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J7200 SoC Family + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +/ { + model = "Texas Instruments K3 J7200 SoC"; + compatible = "ti,j7200"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial5 = &main_uart3; + serial6 = &main_uart4; + serial7 = &main_uart5; + serial8 = &main_uart6; + serial9 = &main_uart7; + serial10 = &main_uart8; + serial11 = &main_uart9; + }; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a72_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + cbass_main: bus@100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ + + /* MCUSS_WKUP Range */ + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + cbass_mcu_wakeup: bus@28380000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-j7200-main.dtsi" +#include "k3-j7200-mcu-wakeup.dtsi" -- cgit v1.2.3 From 26bd3f312c2ece0e8860c80fc64a112df5a620c6 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 14 Sep 2020 21:52:31 +0530 Subject: arm64: dts: ti: Add support for J7200 Common Processor Board Add support for J7200 Common Processor Board. The EVM architecture is very similar to J721E as follows: +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that has most of the actual connectors, power supply etc. A SOM (System on Module) is plugged on to the common processor board and this contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Note: * The minimum configuration required to boot up the board is System On Module(SOM) + Common Processor Board. * Since there is just a single SOM and Common Processor Board, we are maintaining common processor board as the base dts and SOM as the dtsi that we include. In the future as more SOM's appear, we should move common processor board as a dtsi and include configurations as dts. * All daughter cards beyond the basic boards shall be maintained as overlays. Signed-off-by: Lokesh Vutla Signed-off-by: Peter Ujfalusi Signed-off-by: Nishanth Menon Reviewed-by: Grygorii Strashko Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200914162231.2535-6-lokeshvutla@ti.com --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-j7200-common-proc-board.dts | 65 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 ++++++++++ 3 files changed, 96 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 7f28be62b8da..65506f21ba30 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,3 +9,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb + +dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts new file mode 100644 index 000000000000..d257d23e27f5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j7200-som-p0.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; +}; + +&wkup_uart0 { + /* Wakeup UART is used by System firmware */ + status = "disabled"; +}; + +&main_uart0 { + /* Shared with ATF on this platform */ + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +}; + +&main_uart2 { + /* MAIN UART 2 is used by R5F firmware */ + status = "disabled"; +}; + +&main_uart3 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart4 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart5 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart6 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart7 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart8 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart9 { + /* UART not brought out */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi new file mode 100644 index 000000000000..f7e271c442a0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j7200.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x00 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + }; +}; -- cgit v1.2.3 From b0a07f609600b6fa4c30f783db50c38456804485 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Jul 2020 18:51:40 +0200 Subject: ARM: dts: stm32: Move ethernet PHY into DH SoM DT The PHY and the VIO regulator is populated on the SoM, move it into the SoM DT. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 33 ------------------------ arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 36 +++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 7c4bd615b311..9cf6d90fbf69 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -11,7 +11,6 @@ serial0 = &uart4; serial1 = &usart3; serial2 = &uart8; - ethernet0 = ðernet0; }; chosen { @@ -33,16 +32,6 @@ status = "okay"; }; - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #size-cells = <0>; @@ -141,28 +130,6 @@ status = "okay"; }; -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - &i2c2 { /* Header X22 */ pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index ba905196fb54..d30a3c60da9b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -9,6 +9,10 @@ #include / { + aliases { + ethernet0 = ðernet0; + }; + memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; @@ -55,6 +59,16 @@ no-map; }; }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; }; &adc { @@ -94,6 +108,28 @@ status = "okay"; }; +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; -- cgit v1.2.3 From fde180f06d7bc71c457879615cfc070a66a76ce0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Jul 2020 18:51:41 +0200 Subject: ARM: dts: stm32: Add DHSOM based DRC02 board Add DT for DH DRC02 unit, which is a universal controller device. The system has two ethernet ports, two CANs, RS485 and RS232, USB, capacitive buttons and an OLED display. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts | 35 ++++++ arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 4 +- arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi | 157 +++++++++++++++++++++++++ 4 files changed, 195 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..8cdcf7316ca2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1047,6 +1047,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ + stm32mp153c-dhcom-drc02.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ diff --git a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts new file mode 100644 index 000000000000..02a39132958e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2 + * DHCOM PCB number: 587-200 or newer + * DRC02 PCB number: 568-100 or newer + */ +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-drc02.dtsi" + +/ { + model = "DH electronics STM32MP153C DHCOM DRC02"; + compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som", + "st,stm32mp153"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts index 197aa98d49e2..d3b81382f97c 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -4,7 +4,7 @@ * * DHCOM STM32MP1 variant: * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 - * DHCOR PCB number: 587-200 or newer + * DHCOM PCB number: 587-200 or newer * PDK2 PCB number: 516-400 or newer */ /dts-v1/; @@ -15,7 +15,7 @@ #include "stm32mp15xx-dhcom-pdk2.dtsi" / { - model = "DH Electronics STM32MP157C DHCOM Premium Developer Kit (2)"; + model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)"; compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", "st,stm32mp157"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi new file mode 100644 index 000000000000..62ab23824a3e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpiob { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the STM32 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485-rx-en"; + }; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "Out1", + "Out2", "", "", ""; +}; + +&gpioi { + gpio-line-names = "In1", "", "", "", + "", "", "", "", + "In2", "", "", "", + "", "", "", ""; + + /* + * NOTE: The USB Hub on the DRC02 needs a reset signal to be + * pulled high in order to be detected by the USB Controller. + * This signal should be handled by USB power sequencing in + * order to reset the Hub when USB bus is powered down, but + * so far there is no such functionality. + */ + usb-hub { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c5 { /* TP7/TP8 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc3 { + /* + * On DRC02, the SoM does not have SDIO WiFi. The pins + * are used for on-board microSD slot instead. + */ + /delete-property/broken-cd; + cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + /* Use PIO for the display */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; /* Enable once there is display driver */ + /* + * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are + * also connected to the display board connector. + */ +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +/* + * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), + * however the STM32MP1 pinmux cannot map them to UART4 . + */ + +&uart8 { /* RS485 */ + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; -- cgit v1.2.3 From 1ad6e36ec266cedb0d274aa13253ff1fb2eed4ba Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 31 Jul 2020 01:27:57 +0200 Subject: ARM: dts: stm32: Fix sdmmc2 pins on AV96 The AV96 uses sdmmc2_d47_pins_c and sdmmc2_d47_sleep_pins_c, which differ from sdmmc2_d47_pins_b and sdmmc2_d47_sleep_pins_b in one pin, SDMMC2_D5, which is PA15 in the former and PA9 in the later. The PA15 is correct on AV96, so fix this. This error is likely a result of rebasing across the stm32mp1 DT pinctrl rework. Fixes: 611325f68102 ("ARM: dts: stm32: Add eMMC attached to SDMMC2 on AV96") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 930202742a3f..905cd7bb98cf 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -295,9 +295,9 @@ &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; bus-width = <8>; mmc-ddr-1_8v; no-sd; -- cgit v1.2.3 From 4e0ec51f8b9ec3802330a431357e955f552a3f99 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Aug 2020 12:22:54 +0200 Subject: ARM: dts: stm32: Add USB OTG support to DH PDK2 The DH PDK2 board is capable of USB OTG on the X14 USB Mini-AB connector, fill in the missing bits to make USB OTG possible instead of peripheral. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 9cf6d90fbf69..9e93f0a0d293 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -281,9 +281,12 @@ }; &usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; status = "okay"; }; -- cgit v1.2.3 From 42a31ac6698681363363d48335559d212a26a7ca Mon Sep 17 00:00:00 2001 From: Holger Assmann Date: Fri, 7 Aug 2020 17:03:56 +0200 Subject: ARM: dts: stm32: lxa-mc1: Fix kernel warning about PHY delays The KSZ9031 PHY skew timings for rxc/txc, originally set to achieve the desired phase shift between clock- and data-signal, now trigger a kernel warning when used in rgmii-id mode: *-skew-ps values should be used only with phy-mode = "rgmii" This is because commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY") now configures own timings when phy-mode = "rgmii-id". Device trees wanting to set their own delays should use phy-mode "rgmii" instead as the warning prescribes. The "standard" timings now used with "rgmii-id" work fine on this board, so drop the explicit timings in the device tree and thereby silence the warning. Fixes: 666b5ca85cd3 ("ARM: dts: stm32: add STM32MP1-based Linux Automation MC-1 board") Signed-off-by: Holger Assmann Acked-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 5700e6b700d3..b85025d00943 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -121,8 +121,6 @@ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ interrupt-parent = <&gpioa>; interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ - rxc-skew-ps = <1860>; - txc-skew-ps = <1860>; reset-assert-us = <10000>; reset-deassert-us = <300>; micrel,force-master; -- cgit v1.2.3 From f3a622297b045e03d07a2e1a6661134505fa8a8d Mon Sep 17 00:00:00 2001 From: Marcin Sloniewski Date: Sun, 9 Aug 2020 18:44:48 +0200 Subject: dt-bindings: vendor-prefixes: add Seeed Studio Add the "seeed" vendor prefix for Seeed Technology Co., Ltd Website: https://www.seeedstudio.com/ Signed-off-by: Marcin Sloniewski Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2baee2c817c1..70cfac65dc55 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -910,6 +910,8 @@ patternProperties: description: Schindler "^seagate,.*": description: Seagate Technology PLC + "^seeed,.*": + description: Seeed Technology Co., Ltd "^seirobotics,.*": description: Shenzhen SEI Robotics Co., Ltd "^semtech,.*": -- cgit v1.2.3 From 0e2807579a344dff804b4e111c8ccddb0e2e1feb Mon Sep 17 00:00:00 2001 From: Marcin Sloniewski Date: Sun, 9 Aug 2020 18:44:49 +0200 Subject: dt-bindings: arm: stm32: document Odyssey compatible Document device tree bindings of Seeed SoM and carrier board. Signed-off-by: Marcin Sloniewski Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 790e6dd48e34..3b318fe15194 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -50,4 +50,10 @@ properties: - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: Odyssey STM32MP1 SoM based Boards + items: + - enum: + - seeed,stm32mp157c-odyssey + - const: seeed,stm32mp157c-odyssey-som + - const: st,stm32mp157 ... -- cgit v1.2.3 From be78ab4f632c9f24a58b5bb91c5fb9286ae978c3 Mon Sep 17 00:00:00 2001 From: Marcin Sloniewski Date: Sun, 9 Aug 2020 18:44:50 +0200 Subject: ARM: dts: stm32: add initial support for stm32mp157-odyssey board Add support for Seeed Studio's stm32mp157c odyssey board. Board consists of SoM with stm32mp157c with 4GB eMMC and 512 MB DDR3 RAM and carrier board with USB and ETH interfaces, SD card connector, wifi and BT chip AP6236. In this patch only basic kernel boot is supported and interfacing SD card and on-board eMMC. Signed-off-by: Marcin Sloniewski Reviewed-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 18 ++ arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 276 +++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-odyssey.dts | 80 +++++++ 4 files changed, 376 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi create mode 100644 arch/arm/boot/dts/stm32mp157c-odyssey.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8cdcf7316ca2..d7653839deb9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1057,7 +1057,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ - stm32mp157c-lxa-mc1.dtb + stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-odyssey.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index b5a66429670c..a47eaecbde42 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1437,6 +1437,24 @@ }; }; + sdmmc2_d47_pins_d: sdmmc2-d47-3 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi new file mode 100644 index 000000000000..6cf49a0a9e69 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski . + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Seeed Studio Odyssey-STM32MP157C SOM"; + compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved: gpu@d4000000 { + reg = <0xd4000000 0x4000000>; + no-map; + }; + }; + + led { + compatible = "gpio-leds"; + led-blue { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts new file mode 100644 index 000000000000..a7ffec8f1516 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski . + */ + +/dts-v1/; + +#include "stm32mp157c-odyssey-som.dtsi" + +/ { + model = "Seeed Studio Odyssey-STM32MP157C Board"; + compatible = "seeed,stm32mp157c-odyssey", + "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */ + st,eth-clk-sel; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@7 { /* KSZ9031RN */ + reg = <7>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + -- cgit v1.2.3 From 9e8f500af7c59d3057fb784d6c0c5b5cd1f9430f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Aug 2020 14:36:27 +0200 Subject: ARM: dts: stm32: Add STM32MP1 UART8 RTS/CTS pinmux Add extra RTS/CTS line pinmux for STM32MP1 UART8. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index a47eaecbde42..d84686e00370 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1718,6 +1718,14 @@ }; }; + uart8_rtscts_pins_a: uart8rtscts-0 { + pins { + pinmux = , /* UART8_RTS */ + ; /* UART8_CTS */ + bias-disable; + }; + }; + spi4_pins_a: spi4-0 { pins { pinmux = , /* SPI4_SCK */ -- cgit v1.2.3 From 30e9af4ba3e11cd80f1b5063085f2b37aeecaf62 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Aug 2020 14:36:28 +0200 Subject: ARM: dts: stm32: Drop QSPI CS2 pinmux on DHCOM The QSPI CS2 is not used on DHCOM, remove the pinmux settings. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index d30a3c60da9b..60e3d6687f63 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -321,8 +321,8 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From d0ce6f1be3d38de41369692449766dad86d21644 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Aug 2020 14:36:29 +0200 Subject: ARM: dts: stm32: Enable RTS/CTS for DH PDK2 UART8 The DH PDK2 has RTS/CTS lines available on UART8, describe them in DT. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 9e93f0a0d293..f8ac065d4597 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -271,7 +271,8 @@ &uart8 { pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; status = "okay"; }; -- cgit v1.2.3 From 9fc37291831fd85e579cacccb3d887c4f240f2e8 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Sat, 15 Aug 2020 00:50:07 +0200 Subject: ARM: dts: stm32: add display controller node to stm32h743 Declare LTDC (display controller) on stm32h743. Signed-off-by: Tobias Schramm Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 69e2f1e78ed6..2ac6e17c7035 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -329,6 +329,16 @@ status = "disabled"; }; + ltdc: display-controller@50001000 { + compatible = "st,stm32-ltdc"; + reg = <0x50001000 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32H7_APB3_RESET(LTDC)>; + clocks = <&rcc LTDC_CK>; + clock-names = "lcd"; + status = "disabled"; + }; + mdma1: dma-controller@52000000 { compatible = "st,stm32h7-mdma"; reg = <0x52000000 0x1000>; -- cgit v1.2.3 From 33aa48808619393d70f103da85db03847f29b90f Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Sat, 15 Aug 2020 00:35:43 +0200 Subject: ARM: dts: stm32: add resets property to spi device nodes on stm32h743 The stm32 spi driver tries to determine the fifo size of spi devices dynamically. However, if the spi was already configured by the bootloader the fifo size check can become an endless loop, because the driver expects the spi to be in its initial "after device reset" state. The driver does already support resetting the spi device at probe, thus this patch adds only the required device tree properties Signed-off-by: Tobias Schramm Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 2ac6e17c7035..59995720c270 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -110,6 +110,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40003800 0x400>; interrupts = <36>; + resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; clocks = <&rcc SPI2_CK>; status = "disabled"; @@ -121,6 +122,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40003c00 0x400>; interrupts = <51>; + resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; clocks = <&rcc SPI3_CK>; status = "disabled"; }; @@ -207,6 +209,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40013000 0x400>; interrupts = <35>; + resets = <&rcc STM32H7_APB2_RESET(SPI1)>; clocks = <&rcc SPI1_CK>; status = "disabled"; }; @@ -217,6 +220,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40013400 0x400>; interrupts = <84>; + resets = <&rcc STM32H7_APB2_RESET(SPI4)>; clocks = <&rcc SPI4_CK>; status = "disabled"; }; @@ -227,6 +231,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40015000 0x400>; interrupts = <85>; + resets = <&rcc STM32H7_APB2_RESET(SPI5)>; clocks = <&rcc SPI5_CK>; status = "disabled"; }; @@ -382,6 +387,7 @@ compatible = "st,stm32h7-spi"; reg = <0x58001400 0x400>; interrupts = <86>; + resets = <&rcc STM32H7_APB4_RESET(SPI6)>; clocks = <&rcc SPI6_CK>; status = "disabled"; }; -- cgit v1.2.3 From 862f5c7ebc88e72990dd70c4d687b571ce999473 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 Aug 2020 20:11:25 +0200 Subject: ARM: dts: stm32: use stm32h7 usart compatible string for stm32h743 Previously the FIFO on the stm32h743 usart was not utilized, because the stm32f7 compatible configures it without FIFO support. Signed-off-by: Tobias Schramm Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 59995720c270..7febe19e780d 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -128,7 +128,7 @@ }; usart2: serial@40004400 { - compatible = "st,stm32f7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; @@ -196,7 +196,7 @@ }; usart1: serial@40011000 { - compatible = "st,stm32f7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; -- cgit v1.2.3 From 9ad98319e95263469d8ca2cb543c37c5a2f40980 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 28 Aug 2020 14:14:12 +0200 Subject: ARM: dts: stm32: Swap PHY reset GPIO and TSC2004 IRQ on DHCOM SOM On the production revision of the SoM, 587-200, the PHY reset GPIO and touchscreen IRQs are swapped to prevent collision between EXTi IRQs, reflect that in DT. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 60e3d6687f63..b4b52cf634af 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -117,7 +117,7 @@ max-speed = <100>; phy-handle = <&phy0>; st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; mdio0 { #address-cells = <1>; @@ -285,7 +285,7 @@ compatible = "ti,tsc2004"; reg = <0x49>; vio-supply = <&v3v3>; - interrupts-extended = <&gpioh 3 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; }; eeprom@50 { -- cgit v1.2.3 From 3c5c0eee95ece9a73969a94832093be8892cd4c1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:34:25 +0200 Subject: ARM: dts: stm32: Enable RTS/CTS for DH AV96 UART7 The DH AV96 has RTS/CTS lines available on UART7, describe them in DT. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 905cd7bb98cf..ec02cee1dd9b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -351,6 +351,7 @@ label = "LS-UART0"; pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; status = "okay"; }; -- cgit v1.2.3 From 57592d2a98dbc3bde3ddc062e91a8486bdcb211e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:32:55 +0200 Subject: ARM: dts: stm32: Fix DH PDK2 display PWM channel The display PWM channel is number 3 (PWM2 CH4), make it so. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index f8ac065d4597..5dff24e39af8 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -25,7 +25,7 @@ display_bl: display-bl { compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; default-brightness-level = <8>; enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3 From bae2b7f6774b2db44f9001bee7465d4dadd1ede8 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Fri, 28 Aug 2020 15:00:02 +0200 Subject: ARM: dts: stm32: lxa-mc1: enable DDR50 mode on eMMC The "eMMC high-speed DDR mode (3.3V I/O)" at 50MHz is supported on the eMMC-interface of the lxa-mc1. Set it in the device tree to benefit from the speed improvement. Signed-off-by: Ahmad Fatoum Signed-off-by: Holger Assmann Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index b85025d00943..1e5333fd437f 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -212,6 +212,7 @@ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; bus-width = <8>; + mmc-ddr-3_3v; no-1-8-v; no-sd; no-sdio; -- cgit v1.2.3 From fdcf9ea31c33fe9c54dc0b99ca4f744813ba6840 Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Fri, 4 Sep 2020 15:20:43 +0200 Subject: ARM: dts: stm32: add FMC2 EBI support for stm32mp157c This patch adds FMC2 External Bus Interface support on stm32mp157c. Signed-off-by: Christophe Kerello Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 43 +++++++++++++++++++++++------------ arch/arm/boot/dts/stm32mp157c-ev1.dts | 16 +++++++------ 2 files changed, 38 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index bfe29023fbd5..4fd757237b98 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1302,23 +1302,38 @@ dma-requests = <48>; }; - fmc: nand-controller@58002000 { - compatible = "st,stm32mp15-fmc2"; - reg = <0x58002000 0x1000>, - <0x80000000 0x1000>, - <0x88010000 0x1000>, - <0x88020000 0x1000>, - <0x81000000 0x1000>, - <0x89010000 0x1000>, - <0x89020000 0x1000>; - interrupts = ; - dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>, - <&mdma1 20 0x10 0x12000a08 0x0 0x0>, - <&mdma1 21 0x10 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = ; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; }; qspi: spi@58003000 { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 85628e16d2d5..a55e80ce2602 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -158,14 +158,16 @@ pinctrl-0 = <&fmc_pins_a>; pinctrl-1 = <&fmc_sleep_pins_a>; status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; -- cgit v1.2.3 From 71593c519f162b5f54bafed085cdddc7a883894d Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 17 Sep 2020 05:00:35 +0200 Subject: ARM: dts: stm32: add arm-pmu node on stm32mp15 Add arm-pmu node on stm32mp15. Signed-off-by: Alexandre Torgue Signed-off-by: Marek Vasut # update to linux-next Tested-by: Marek Vasut # on DH PDK2 and Avenger96 Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 7 +++++++ arch/arm/boot/dts/stm32mp153.dtsi | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 4fd757237b98..84757901cd8d 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -23,6 +23,13 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi index 6d9ab08667fc..1c1889b194cf 100644 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -16,6 +16,12 @@ }; }; + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can"; -- cgit v1.2.3 From bac12f2569d1e2378d8de59eefbaa1d0ef5101dc Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 10 Sep 2020 15:44:30 +0530 Subject: arm64: dts: qcom: sm8250: Add thermal zones and throttling support sm8250 has 24 thermal sensors split across two tsens controllers. Add the thermal zones to expose them and wireup the cpus to throttle on crossing passive temperature thresholds. Signed-off-by: Amit Kucheria Link: https://lore.kernel.org/r/89b83b3caa4e32db08fe402cfa510feb25232aa0.1599732068.git.amitk@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 766 +++++++++++++++++++++++++++++++++++ 1 file changed, 766 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 357e4bfba70c..d057d85a19fb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -90,6 +91,7 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -106,6 +108,7 @@ enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -119,6 +122,7 @@ enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -132,6 +136,7 @@ enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -145,6 +150,7 @@ enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -158,6 +164,7 @@ enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -172,6 +179,7 @@ enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -185,6 +193,7 @@ enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; + #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -1482,6 +1491,28 @@ interrupt-controller; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <9>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: qmp@c300000 { compatible = "qcom,sm8250-aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; @@ -2351,4 +2382,739 @@ ; }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu4_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_top_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_top_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu5_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_top_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_top_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_top_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_top_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_top_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_top_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu4_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_bottom_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_bottom_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu5_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_bottom_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_bottom_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 13>; + + trips { + cpu6_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_bottom_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_bottom_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 14>; + + trips { + cpu7_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_bottom_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_bottom_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cluster0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster0_crit: cluster0_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 6>; + + trips { + cluster1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster1_crit: cluster1_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal-top { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 15>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + wlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + mem_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6_hvx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + compute-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + compute_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 7>; + + trips { + npu_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-bottom { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 8>; + + trips { + gpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; }; -- cgit v1.2.3 From 463742644e964037d015b1200e2084fd54508007 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 24 Sep 2020 01:09:35 +0300 Subject: arm64: dts: ti: k3-j7200: add DMA support Add the ringacc and udmap nodes for Main and MCU NAVSS. Signed-off-by: Peter Ujfalusi Signed-off-by: Grygorii Strashko Signed-off-by: Nishanth Menon Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200923220938.30788-2-grygorii.strashko@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 36 ++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 44 +++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 3df49577b06a..a44c3388c1a8 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -93,6 +93,42 @@ interrupt-names = "rx_011"; interrupts = ; }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x00 0x3c000000 0x00 0x400000>, + <0x00 0x38000000 0x00 0x400000>, + <0x00 0x31120000 0x00 0x100>, + <0x00 0x33000000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <211>; + msi-parent = <&main_udmass_inta>; + }; + + main_udmap: dma-controller@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x00 0x31150000 0x00 0x100>, + <0x00 0x34000000 0x00 0x100000>, + <0x00 0x35000000 0x00 0x100000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <212>; + ti,ringacc = <&main_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; }; main_pmx0: pinctrl@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index ec2745e0768e..334c2fb2c082 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -92,4 +92,48 @@ ti,sci-dev-id = <137>; ti,interrupt-ranges = <16 960 16>; }; + + mcu_navss: bus@28380000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + dma-coherent; + dma-ranges; + ti,sci-dev-id = <232>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x00 0x2b800000 0x00 0x400000>, + <0x00 0x2b000000 0x00 0x400000>, + <0x00 0x28590000 0x00 0x100>, + <0x00 0x2a500000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <235>; + msi-parent = <&main_udmass_inta>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x00 0x285c0000 0x00 0x100>, + <0x00 0x2a800000 0x00 0x40000>, + <0x00 0x2aa00000 0x00 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <236>; + ti,ringacc = <&mcu_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; }; -- cgit v1.2.3 From c5d73d8d49f62bddbce0251e0033cd2c919a039f Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Thu, 24 Sep 2020 01:09:36 +0300 Subject: arm64: dts: ti: k3-j7200-main: add main navss cpts node Add DT node for Main NAVSS CPTS module. Signed-off-by: Grygorii Strashko Signed-off-by: Nishanth Menon Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200923220938.30788-3-grygorii.strashko@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index a44c3388c1a8..c2a986affb0e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -129,6 +129,18 @@ <0x0c>; /* RX_UHCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + + cpts@310d0000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x310d0000 0x00 0x400>; + reg-names = "cpts"; + clocks = <&k3_clks 201 1>; + clock-names = "cpts"; + interrupts-extended = <&main_navss_intr 391>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; }; main_pmx0: pinctrl@11c000 { -- cgit v1.2.3 From a323da4b43fd1a9fbbe490375cc090d0b8feb59a Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Thu, 24 Sep 2020 01:09:37 +0300 Subject: arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node Add DT node for The TI J7200 MCU SoC Gigabit Ethernet two ports Switch subsystem (MCU CPSW NUSS). Signed-off-by: Grygorii Strashko Signed-off-by: Nishanth Menon Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200923220938.30788-4-grygorii.strashko@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 74 +++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 334c2fb2c082..c168171da429 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,20 @@ }; }; + mcu_conf: syscon@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x40f00000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; + }; + chipid@43000014 { compatible = "ti,am654-chipid"; reg = <0x00 0x43000014 0x00 0x4>; @@ -136,4 +150,64 @@ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x46000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; + dma-coherent; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 18 2>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; }; -- cgit v1.2.3 From fc3b15506d8f22cf1f74fa60b9e4d524e5fe3430 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Thu, 24 Sep 2020 01:09:38 +0300 Subject: arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI J7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko Signed-off-by: Nishanth Menon Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20200923220938.30788-5-grygorii.strashko@ti.com --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index d257d23e27f5..b8000dfb791c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include / { chosen { @@ -14,6 +15,32 @@ }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; @@ -63,3 +90,21 @@ /* UART not brought out */ status = "disabled"; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; -- cgit v1.2.3 From 03bfeb528772d2521abe14b2e24c9b5645dcb26f Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 23 Sep 2020 21:23:59 +0530 Subject: arm64: dts: ti: k3-j7200: Add I2C nodes J7200 has 7 I2Cs in main domain, 2 I2Cs in MCU and 1 in wakeup domain. Add DT nodes for the same. Signed-off-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Sekhar Nori Reviewed-by: Faiz Abbas Link: https://lore.kernel.org/r/20200923155400.13757-2-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 77 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33 +++++++++++ 2 files changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index c2a986affb0e..a65ca56fbc59 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -281,4 +281,81 @@ clocks = <&k3_clks 286 2>; clock-names = "fclk"; }; + + main_i2c0: i2c@2000000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 187 1>; + power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; + }; + + main_i2c1: i2c@2010000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 188 1>; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c2: i2c@2020000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 189 1>; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c3: i2c@2030000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 190 1>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c4: i2c@2040000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2040000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 191 1>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c5: i2c@2050000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2050000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 192 1>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c6: i2c@2060000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2060000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 193 1>; + power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index c168171da429..b67b33c9bda6 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -210,4 +210,37 @@ ti,cpts-periodic-outputs = <2>; }; }; + + mcu_i2c0: i2c@40b00000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x40b00000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 194 1>; + power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_i2c1: i2c@40b10000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x40b10000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 195 1>; + power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; + }; + + wkup_i2c0: i2c@42120000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x42120000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 197 1>; + power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; + }; }; -- cgit v1.2.3 From e25889f8f5db5e3c4edb428611329c105bfdf7cf Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 23 Sep 2020 21:24:00 +0530 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and also add the pinmux corresponding to these I2C instances. Signed-off-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Sekhar Nori Reviewed-by: Faiz Abbas Link: https://lore.kernel.org/r/20200923155400.13757-3-vigneshr@ti.com --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index b8000dfb791c..c71b8ec1d55e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -41,6 +41,22 @@ }; }; +&main_pmx0 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ + J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ + J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; @@ -108,3 +124,36 @@ phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; }; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + exp2: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; -- cgit v1.2.3 From 1b77265626a44f38d5583256247195bba2c1934c Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 23 Sep 2020 22:01:49 +0530 Subject: arm64: dts: ti: k3-j7200-mcu-wakeup: Add HyperBus node J7200 has a Flash SubSystem that has one OSPI and one HyperBus.. Add DT nodes for HyperBus controller for now. Signed-off-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Sekhar Nori Link: https://lore.kernel.org/r/20200923163150.16973-2-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index b67b33c9bda6..eb2a78a53512 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -243,4 +243,31 @@ clocks = <&k3_clks 197 1>; power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; }; + + fss: syscon@47000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x47000000 0x00 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hbmc_mux: hbmc-mux { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x2>; /* HBMC select */ + }; + + hbmc: hyperbus@47034000 { + compatible = "ti,am654-hbmc"; + reg = <0x00 0x47034000 0x00 0x100>, + <0x05 0x00000000 0x01 0x0000000>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 0>; + assigned-clocks = <&k3_clks 102 5>; + assigned-clock-rates = <333333333>; + #address-cells = <2>; + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + }; + }; }; -- cgit v1.2.3 From 0bf331496ae0a49758fd1082d7886e7dd90da41d Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 23 Sep 2020 22:01:50 +0530 Subject: arm64: dts: ti: k3-j7200-som-p0: Add HyperFlash node J7200 SoM has a HyperFlash connected to HyperBus memory controller. But HyperBus is muxed with OSPI, therefore keep HyperBus node disabled. Bootloader will detect the mux and enable the node as required. Signed-off-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Sekhar Nori Link: https://lore.kernel.org/r/20200923163150.16973-3-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index f7e271c442a0..6a98ba499bc2 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -27,3 +27,39 @@ }; }; }; + +&wkup_pmx0 { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; +}; + +&hbmc { + /* OSPI and HBMC are muxed inside FSS, Bootloader will enable + * appropriate node based on board detection + */ + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x00 0x00 0x4000000>; + }; +}; -- cgit v1.2.3 From 7cd03dc78b290400875b6b54e257ba5ea4e810c3 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Thu, 24 Sep 2020 16:56:43 +0530 Subject: arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodes Add support for MMC/SD controller nodes present on TI's j7200 SoCs. There are two nodes: 1. sdhci0 (8 bit bus width, 200 MHz, HS200, 200 MBps) 2. sdhci1 (4 bit bus width, 50 MHz, HS, 25 MBps) Signed-off-by: Faiz Abbas Signed-off-by: Nishanth Menon Tested-by: Vignesh Raghavendra Reviewed-by: Sekhar Nori Link: https://lore.kernel.org/r/20200924112644.11076-2-faiz_abbas@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 37 +++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index a65ca56fbc59..4a4fcd24f852 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -358,4 +358,41 @@ clocks = <&k3_clks 193 1>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; }; + + main_sdhci0: mmc@4f80000 { + compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; + reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x0>; + ti,strobe-sel = <0x77>; + ti,trm-icp = <0x8>; + bus-width = <8>; + mmc-ddr-1_8v; + dma-coherent; + }; + + main_sdhci1: mmc@4fb0000 { + compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; + reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-ddr50 = <0xc>; + no-1-8-v; + dma-coherent; + }; }; -- cgit v1.2.3 From a2178b83ae8f61b2a9fae2aa9a4d4ed2511690a4 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Thu, 24 Sep 2020 16:56:44 +0530 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card Add support for the eMMC and SD card connected on the common processor board sdhci0 is connected to an eMMC while sdhci1 is connected to the micro SD slot. Signed-off-by: Faiz Abbas Signed-off-by: Nishanth Menon Tested-by: Vignesh Raghavendra Reviewed-by: Sekhar Nori Link: https://lore.kernel.org/r/20200924112644.11076-3-faiz_abbas@ti.com --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index c71b8ec1d55e..1541311cecb4 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -55,6 +55,19 @@ J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ >; }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ + J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ + J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ + J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ + J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ + J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ + J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ + >; + }; }; &wkup_uart0 { @@ -157,3 +170,18 @@ #gpio-cells = <2>; }; }; + +&main_sdhci0 { + /* eMMC */ + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci1 { + /* SD card */ + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + ti,driver-strength-ohm = <50>; + disable-wp; +}; -- cgit v1.2.3 From 7bf8f37aea8212d795dd5c821fa0a622b143000c Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Fri, 11 Sep 2020 01:25:16 +0300 Subject: ARM: dts: am437x-l4: add dt node for new cpsw switchdev driver Add DT node for the new cpsw switchdev based driver. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 3d393fe252c6..e702e9576115 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -571,6 +571,60 @@ phys = <&phy_gmii_sel 2 0>; }; }; + + mac_sw: switch@0 { + compatible = "ti,am4372-cpsw","ti,cpsw-switch"; + reg = <0x0 0x4000>; + ranges = <0 0 0x4000>; + clocks = <&cpsw_125mhz_gclk>, <&dpll_clksel_mac_clk>; + clock-names = "fck", "50mclk"; + assigned-clocks = <&dpll_clksel_mac_clk>; + assigned-clock-rates = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + syscon = <&scm_conf>; + status = "disabled"; + + interrupts = ; + interrupt-names = "rx_thresh", "rx", "tx", "misc"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + label = "port1"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; + }; + + cpsw_port2: port@2 { + reg = <2>; + label = "port2"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; + }; + }; + + davinci_mdio_sw: mdio@1000 { + compatible = "ti,am4372-mdio", "ti,cpsw-mdio","ti,davinci_mdio"; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x1000 0x100>; + }; + + cpts { + clocks = <&cpsw_cpts_rft_clk>; + clock-names = "cpts"; + }; + }; }; target-module@200000 { /* 0x4a200000, ap 7 02.0 */ -- cgit v1.2.3 From aff7e5038c8558b68383b992e33486045cf5734a Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Fri, 11 Sep 2020 01:25:17 +0300 Subject: ARM: dts: am437x: switch to new cpsw switch drv The dual_mac mode has been preserved the same way between legacy and new driver, and one port devices works the same as 1 dual_mac port - it's safe to switch drivers. So, Switch all am437x boards to use new cpsw switch driver. Those boards have or 2 Ext. port wired and configured in dual_mac mode by default, or only 1 Ext. port. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 4 ++-- arch/arm/boot/dts/am437x-cm-t43.dts | 14 ++++++-------- arch/arm/boot/dts/am437x-gp-evm.dts | 13 ++++++++----- arch/arm/boot/dts/am437x-idk-evm.dts | 13 ++++++++----- arch/arm/boot/dts/am437x-sk-evm.dts | 14 ++++++-------- arch/arm/boot/dts/am43x-epos-evm.dts | 13 ++++++++----- 6 files changed, 38 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 14314046256c..38a7dd64f8df 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -35,8 +35,8 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; spi0 = &qspi; }; diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index a6b4fca8626a..a83f46ed0c9a 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -325,17 +325,15 @@ }; }; -&mac { +&mac_sw { pinctrl-names = "default"; pinctrl-0 = <&cpsw_default>; - dual_emac = <1>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default"; pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; @@ -346,16 +344,16 @@ }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; &dwc3_1 { diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 7c1ee35e6a1c..6e4d05d649e9 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -906,28 +906,31 @@ status = "okay"; }; -&mac { - slaves = <1>; +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; &elm { diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 8b986c45f09d..2dc525512266 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -483,28 +483,31 @@ }; }; -&mac { - slaves = <1>; +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; &rtc { diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 5fffdce853b1..496ed34f7755 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -792,19 +792,17 @@ }; }; -&mac { +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@4 { reg = <4>; @@ -815,16 +813,16 @@ }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; &elm { diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 76f48ff051e8..b19c2fb2a388 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -550,29 +550,32 @@ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; -&mac { +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; - slaves = <1>; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@16 { reg = <16>; }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rmii"; phys = <&phy_gmii_sel 1 1>; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; &i2c0 { -- cgit v1.2.3 From 8cbe7afc92d0ed0078ac00de5fc48c202bbb67f9 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Fri, 11 Sep 2020 01:25:18 +0300 Subject: ARM: dts: am437x-l4: drop legacy cpsw dt node All am437x boards have been converted to use new driver, so drop legacy cpsw dt node. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 51 ---------------------------------------- 1 file changed, 51 deletions(-) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index e702e9576115..d82a6eeaf1b3 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -521,57 +521,6 @@ #size-cells = <1>; ranges = <0x0 0x100000 0x8000>; - mac: ethernet@0 { - compatible = "ti,am4372-cpsw","ti,cpsw"; - reg = <0x0 0x800 - 0x1200 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, - <&dpll_clksel_mac_clk>; - clock-names = "fck", "cpts", "50mclk"; - assigned-clocks = <&dpll_clksel_mac_clk>; - assigned-clock-rates = <50000000>; - status = "disabled"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - ranges = <0 0 0x8000>; - syscon = <&scm_conf>; - - davinci_mdio: mdio@1000 { - compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x1000 0x100>; - clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1 0>; - }; - - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2 0>; - }; - }; - mac_sw: switch@0 { compatible = "ti,am4372-cpsw","ti,cpsw-switch"; reg = <0x0 0x4000>; -- cgit v1.2.3 From 97b16ed1038b1cd40114d6486c0e67029bfcd8db Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:08 +0200 Subject: ARM: dts: am335x: lxm: fix PCA9539 GPIO expander properties The PCA9539 GPIO expander requires GPIO controller properties to operate properly. Signed-off-by: Krzysztof Kozlowski Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-lxm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index cd55f11260ea..0f078465297a 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -160,11 +160,15 @@ serial_config1: serial_config1@20 { compatible = "nxp,pca9539"; reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; }; serial_config2: serial_config2@21 { compatible = "nxp,pca9539"; reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; }; tps: tps@2d { -- cgit v1.2.3 From ccd73f07e05d0adc99d164cc919293799cca510c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:09 +0200 Subject: ARM: dts: am335x: t335: align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sbc-t335.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/am335x-sbc-t335.dts index a3f6bc4072d9..81e4453687ba 100644 --- a/arch/arm/boot/dts/am335x-sbc-t335.dts +++ b/arch/arm/boot/dts/am335x-sbc-t335.dts @@ -155,13 +155,13 @@ gpio-controller; #gpio-cells = <2>; reg = <0x26>; - dvi_ena { + dvi-ena-hog { gpio-hog; gpios = <13 GPIO_ACTIVE_HIGH>; output-high; line-name = "dvi-enable"; }; - lcd_ena { + lcd-ena-hog { gpio-hog; gpios = <11 GPIO_ACTIVE_HIGH>; output-high; -- cgit v1.2.3 From 5e7998b8017f83d421fcf41421c562f63ed125cc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:10 +0200 Subject: ARM: dts: am3874: iceboard: fix GPIO expander reset GPIOs Correct the property for reset GPIOs of the GPIO expander. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3874-iceboard.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index 1bb57019d082..9423e9feaa10 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -195,7 +195,7 @@ "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; }; u42: pca9575@21 { @@ -208,7 +208,7 @@ "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; }; u48: pca9575@22 { @@ -227,7 +227,7 @@ "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; }; u59: pca9575@23 { @@ -240,7 +240,7 @@ "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; }; tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; -- cgit v1.2.3 From 197bbae9ed8b45aa5c6cacddbcacc3d67e53de3a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:06 +0200 Subject: arm64: dts: ti: k3-j721e-common-proc-board: align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200916155715.21009-7-krzk@kernel.org --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index f35a5d5b1cd8..917421ed3f79 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -407,7 +407,7 @@ gpio-controller; #gpio-cells = <2>; - p09 { + p09-hog { /* P11 - MCASP/TRACE_MUX_S0 */ gpio-hog; gpios = <9 GPIO_ACTIVE_HIGH>; @@ -415,7 +415,7 @@ line-name = "MCASP/TRACE_MUX_S0"; }; - p10 { + p10-hog { /* P12 - MCASP/TRACE_MUX_S1 */ gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3 From e89c32fe22e431f09bafa63cf61c76c9551d56cf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 18:39:57 +0200 Subject: ARM: dts: picoxcell: build DTBs with make dtbs Add ARCH_PICOXCELL entries to Makefil so the DTBs get built with `make dtbs`. Link: https://lore.kernel.org/r/20200917163957.21895-1-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Olof Johansson --- arch/arm/boot/dts/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 98149f9c949c..6987db026f69 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -871,6 +871,9 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \ owl-s500-cubieboard6.dtb \ owl-s500-guitar-bb-rev-b.dtb \ owl-s500-sparky.dtb +dtb-$(CONFIG_ARCH_PICOXCELL) += \ + picoxcell-pc7302-pc3x2.dtb \ + picoxcell-pc7302-pc3x3.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_PXA) += \ -- cgit v1.2.3 From 088a2644de6a16c49cf44d9edfc9490229865c18 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 18:49:09 +0200 Subject: ARM: dts: picoxcell: drop unused reg-io-width from DW APB GPIO controller The Synopsys DesignWare APB GPIO controller driver does not parse reg-io-width and dtschema does not allow it so drop it to fix dtschema warnings like: arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dt.yaml: gpio@20000: 'reg-io-width' does not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20200917164909.22490-1-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski Acked-by: Jamie Iles Signed-off-by: Olof Johansson --- arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 1 - arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi index 5ae860788339..c4c6c7e9e37b 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi @@ -160,7 +160,6 @@ reg = <0x20000 0x1000>; #address-cells = <1>; #size-cells = <0>; - reg-io-width = <4>; banka: gpio-controller@0 { compatible = "snps,dw-apb-gpio-bank"; diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi index fa93155fadb7..0e85bb6bd150 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi @@ -243,7 +243,6 @@ reg = <0x20000 0x1000>; #address-cells = <1>; #size-cells = <0>; - reg-io-width = <4>; banka: gpio-controller@0 { compatible = "snps,dw-apb-gpio-bank"; -- cgit v1.2.3 From 61163895f3e0474b2e668439d2c79708c4122265 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 18:50:39 +0200 Subject: arm64: dts: apm: drop unused reg-io-width from DW APB GPIO controller The Synopsys DesignWare APB GPIO controller driver does not parse reg-io-width and dtschema does not allow it so drop it to fix dtschema warnings like: arch/arm64/boot/dts/apm/apm-mustang.dt.yaml: gpio@1c024000: 'reg-io-width' does not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20200917165040.22908-1-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 1 - arch/arm64/boot/dts/apm/apm-storm.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 3feb1881bbc2..2da5b8a0cd35 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -709,7 +709,6 @@ dwgpio: gpio@1c024000 { compatible = "snps,dw-apb-gpio"; reg = <0x0 0x1c024000 0x0 0x1000>; - reg-io-width = <4>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 8c802d87e751..560b2a6f2082 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -825,7 +825,6 @@ dwgpio: gpio@1c024000 { compatible = "snps,dw-apb-gpio"; reg = <0x0 0x1c024000 0x0 0x1000>; - reg-io-width = <4>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From e90ac411dcbdef4baaf2a1ce244bbe7bab176d4c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 18:50:40 +0200 Subject: arm64: dts: apm: add required gpio-cells to DW APB GPIO controller port The Synopsys DesignWare APB GPIO controller port must have gpio-cells property, as pointed by dtschema: arch/arm64/boot/dts/apm/apm-mustang.dt.yaml: gpio@1c024000: gpio-controller@0: '#gpio-cells' is a required property Link: https://lore.kernel.org/r/20200917165040.22908-2-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 1 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 2da5b8a0cd35..a83c82c50e29 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -715,6 +715,7 @@ porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; + #gpio-cells = <2>; snps,nr-gpios = <32>; reg = <0>; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 560b2a6f2082..0f37e77f5459 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -831,6 +831,7 @@ porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; + #gpio-cells = <2>; snps,nr-gpios = <32>; reg = <0>; }; -- cgit v1.2.3 From 02ed6bb83ec3f99806b0f3471c7ee1a02525e236 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 23 Sep 2020 08:57:03 +0800 Subject: ARM: dts: sun8i: V3/V3s/S3/S3L: add Ethernet support The Allwinner V3/V3s/S3L/SoChip S3 Ethernet MAC and internal PHY is quite similar to the ones on Allwinner H3, except for V3s the external MII is not wired out. Add ethernet support to V3/V3s/S3/S3L. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200923005709.147966-2-icenowy@aosc.io --- arch/arm/boot/dts/sun8i-v3.dtsi | 13 ++++++++++ arch/arm/boot/dts/sun8i-v3s.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index 6ae8645ade50..ca4672ed2e02 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -9,6 +9,19 @@ compatible = "allwinner,sun8i-v3-ccu"; }; +&emac { + /delete-property/ phy-handle; + /delete-property/ phy-mode; +}; + +&mdio_mux { + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + &pio { compatible = "allwinner,sun8i-v3-pinctrl"; }; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 6eb9c39aa93f..7d40897dab09 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -138,6 +138,15 @@ }; }; + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-v3s-system-control", + "allwinner,sun8i-h3-system-control"; + reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-v3s-tcon"; reg = <0x01c0c000 0x1000>; @@ -415,6 +424,49 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-v3s-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio_mux: mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + }; + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; -- cgit v1.2.3 From c0dcfbe29edcc90d90da6b84e7d45ef39e67a726 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 23 Sep 2020 08:58:53 +0800 Subject: ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for UART2 RX/TX The UART2 RX/TX pins on Allwinner V3 series is at PB0/1, which is used as debugging UART on some boards. Add pinctrl node for them. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200923005858.148261-1-icenowy@aosc.io --- arch/arm/boot/dts/sun8i-v3s.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 7d40897dab09..4cfdf193cf88 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -322,6 +322,11 @@ function = "uart0"; }; + uart2_pins: uart2-pins { + pins = "PB0", "PB1"; + function = "uart2"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -397,6 +402,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; status = "disabled"; }; -- cgit v1.2.3 From 90e048101fa192e6e1ea48192fa22d8c684a0bf1 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 23 Sep 2020 08:58:54 +0800 Subject: ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI. Add the device tree node of it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200923005858.148261-2-icenowy@aosc.io --- arch/arm/boot/dts/sun8i-v3s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 4cfdf193cf88..3e079973672d 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -488,6 +488,18 @@ #size-cells = <0>; }; + csi1: camera@1cb4000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb4000 0x3000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, -- cgit v1.2.3 From e174afa66e09e0f836c581c082fbdd73e8875209 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 23 Sep 2020 09:01:21 +0800 Subject: ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for 8-bit parallel CSI The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI. As we're going to add support for Pine64 SCC board, which uses 8-bit parallel CSI (and the MCLK output), add the pinctrl node of 8-bit CSI and MCLK to the DTSI file. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200923010122.148661-1-icenowy@aosc.io --- arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 3e079973672d..19fba1a9115b 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -312,6 +312,20 @@ interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + csi1_8bit_pins: csi1-8bit-pins { + pins = "PE0", "PE2", "PE3", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi1_mclk_pin: csi1-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + i2c0_pins: i2c0-pins { pins = "PB6", "PB7"; function = "i2c0"; -- cgit v1.2.3 From b5a2221c077a54886cc3161c95ae5c3511049299 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 23 Sep 2020 09:00:12 +0800 Subject: ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for I2C1 at PE bank I2C1 controller is available at PE bank, usually used for connecting an I2C-controlled camera sensor. Add pinctrl node for it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200923010014.148482-2-icenowy@aosc.io --- arch/arm/boot/dts/sun8i-v3s.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 19fba1a9115b..bae8fa9e356a 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -331,6 +331,12 @@ function = "i2c0"; }; + /omit-if-no-ref/ + i2c1_pe_pins: i2c1-pe-pins { + pins = "PE21", "PE22"; + function = "i2c1"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB8", "PB9"; function = "uart0"; -- cgit v1.2.3 From 61f4bc990b378d10ee2964c764f92363e1fd6ed4 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 23 Sep 2020 09:02:14 +0800 Subject: dt-bindings: arm: sunxi: add Pine64 PineCube binding Document board compatible names for Pine64 PineCube IP camera. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200923010215.148819-1-icenowy@aosc.io --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 5957a22c2e95..afa00268c7db 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -631,6 +631,11 @@ properties: - const: pine64,pine64-plus - const: allwinner,sun50i-a64 + - description: Pine64 PineCube + items: + - const: pine64,pinecube + - const: allwinner,sun8i-s3 + - description: Pine64 PineH64 model A items: - const: pine64,pine-h64 -- cgit v1.2.3 From bbcf293d838b81b77e12ce7859715eac80ff11a6 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 23 Sep 2020 09:02:15 +0800 Subject: ARM: dts: sun8i: s3l: add support for Pine64 PineCube IP camera The Pine64 PineCube IP camera is an IP camera with SoChip S3 SoC. It comes with a main board, an expansion board and a camera. The main board features a Micro-USB power-only jack, a USB Type-A port, an Ethernet port connected to the internal PHY of the SoC and a Realtek RTL8189ES SDIO Wi-Fi module. A RGB LCD connector is reserved on the board. The expansion board features a TF slot, a microphone, a speaker connector with on-board amplifier and a few IR LEDs. Add support for the kit, with features on the main board and the expansion board now. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200923010215.148819-2-icenowy@aosc.io --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-s3-pinecube.dts | 235 ++++++++++++++++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-pinecube.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..4363ba564bb4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1194,6 +1194,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts new file mode 100644 index 000000000000..9bab6b7f4014 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2019 Icenowy Zheng + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" +#include +#include + +/ { + model = "PineCube IP Camera"; + compatible = "pine64,pinecube", "allwinner,sun8i-s3"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "pine64:ir:led1"; + gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ + }; + + led2 { + label = "pine64:ir:led2"; + gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_wifi: vcc-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ + vin-supply = <®_dcdc3>; + startup-delay-us = <200000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ + post-power-on-delay-ms = <200>; + }; +}; + +&csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_8bit_pins>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp203", + "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pe_pins>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi1_mclk_pin>; + clocks = <&ccu CLK_CSI1_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_ldo3>; + DOVDD-supply = <®_ldo3>; + DVDD-supply = <®_ldo4>; + reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ + powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Setup"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc_wifi>; + vqmmc-supply = <®_dcdc3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pio { + vcc-pd-supply = <®_dcdc3>; + vcc-pe-supply = <®_ldo3>; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-sys-cpu-ephy"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-dovdd-2v8-csi"; + regulator-soft-start; + regulator-ramp-delay = <1600>; +}; + +®_ldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-1v8-csi"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; -- cgit v1.2.3 From 2bd5298af55cfd725f13ff853adcee4d117532cd Mon Sep 17 00:00:00 2001 From: Martin Cerveny Date: Wed, 16 Sep 2020 19:59:41 +0200 Subject: ARM: dts: sun8i: v3s: Add simple-framebuffer Add support for "allwinner,simple-framebuffer" with "mixer0-lcd0" pipeline from boot loader (u-boot). It depends on boot loader implementation of DE2/TCON0 setup with LCD. Signed-off-by: Martin Cerveny Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200916175941.8448-1-m.cerveny@computer.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index bae8fa9e356a..0c7341676921 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -43,12 +43,28 @@ #include #include #include +#include / { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0"; + clocks = <&display_clocks CLK_MIXER0>, + <&ccu CLK_TCON0>; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From cbf5a878aea9ccd0236c99f028080e099365c65d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:07 +0200 Subject: arm64: dts: xilinx: align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200916155715.21009-8-krzk@kernel.org Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 4f801721564f..f1255f635dfd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -203,25 +203,25 @@ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ -- cgit v1.2.3 From dfff9066e60ee8670424cfedf4269d3b51c5100f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Aug 2020 12:05:42 +0200 Subject: arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml Rename amba-apu and amba to AXI. Based on Xilinx ZynqMP TRM (Chapter 15) chip is "using the advanced eXtensible interface (AXI) point-to-point channels for communicating addresses, data, and response transactions between master and slave clients." Issues are reported as: ...: amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: .../dt-schema/dtschema/schemas/simple-bus.yaml ...: amba-apu@0: $nodename:0: 'amba-apu@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: .../dt-schema/dtschema/schemas/simple-bus.yaml Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/68f20a2b2bb0feee80bc3348619c2ee98aa69963.1598263539.git.michal.simek@xilinx.com Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 3ec99f13c259..8e35b9daf4a3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -183,7 +183,7 @@ ranges; }; - amba_apu: amba-apu@0 { + amba_apu: axi@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; @@ -202,7 +202,7 @@ }; }; - amba: amba { + amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From 35292518cb0a626fcdcabf739aed75060a018ab5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Aug 2020 10:59:14 +0200 Subject: arm64: dts: zynqmp: Remove additional compatible string for i2c IPs DT binding permits only one compatible string which was decribed in past by commit 63cab195bf49 ("i2c: removed work arounds in i2c driver for Zynq Ultrascale+ MPSoC"). The commit aea37006e183 ("dt-bindings: i2c: cadence: Migrate i2c-cadence documentation to YAML") has converted binding to yaml and the following issues is reported: ...: i2c@ff030000: compatible: Additional items are not allowed ('cdns,i2c-r1p10' was unexpected) From schema: .../Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml fds ...: i2c@ff030000: compatible: ['cdns,i2c-r1p14', 'cdns,i2c-r1p10'] is too long The commit c415f9e8304a ("ARM64: zynqmp: Fix i2c node's compatible string") has added the second compatible string but without removing origin one. The patch is only keeping one compatible string "cdns,i2c-r1p14". Fixes: c415f9e8304a ("ARM64: zynqmp: Fix i2c node's compatible string") Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/cc294ae1a79ef845af6809ddb4049f0c0f5bb87a.1598259551.git.michal.simek@xilinx.com Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 8e35b9daf4a3..f1b338e09a67 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -501,7 +501,7 @@ }; i2c0: i2c@ff020000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; @@ -512,7 +512,7 @@ }; i2c1: i2c@ff030000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; -- cgit v1.2.3 From db7691f9587cb01f4c9bde096f6e7ffd9f1297c0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Aug 2020 10:28:45 +0200 Subject: arm64: dts: zynqmp: Remove undocumented u-boot properties u-boot, DT properties are not documented anywhere in Linux DT binding that's why remove them. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8ba339425b9c9f319bdedce7741367055a30713c.1598257720.git.michal.simek@xilinx.com Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 5 ----- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 1 - 2 files changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 9868ca15dfc5..c94c3bb67edc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -10,35 +10,30 @@ #include / { pss_ref_clk: pss_ref_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index f1b338e09a67..771f60e0346d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -131,7 +131,6 @@ }; zynqmp_clk: clock-controller { - u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, -- cgit v1.2.3 From 9a19a39ee48b73a5dc84b3e102cda2219dfd5b0f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Aug 2020 12:28:39 +0200 Subject: arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 Fix the leds subnode names to match (^led-[0-9a-f]$|led). Similar change has been also done by commit 08dc0e5dd9aa ("arm64: dts: meson: fix leds subnodes name"). The patch is fixing this warning: avnet-ultra96-rev1.dt.yaml: leds: 'ds2', 'ds3', 'ds4', 'ds5' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/1a69c3fa0291f991ffcf113ea222c713ba4d4ff0.1598264917.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index c9460693f4e9..68ecd0f7b2f2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -56,27 +56,27 @@ leds { compatible = "gpio-leds"; - ds2 { + led-ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - ds3 { + led-ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; - ds4 { + led-ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; - ds5 { + led-ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; -- cgit v1.2.3 From 227afa0488c4cb8adb474e30eb3f4527fe85eb13 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Tue, 29 Sep 2020 22:14:46 +0800 Subject: ARM: dts: hisilicon: fix the system controller compatible nodes The DT binding for Hisilicon system controllers require to have a "syscon" compatible string. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3620.dtsi | 2 +- arch/arm/boot/dts/hip04.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 355175b25fd6..f683440ee569 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -89,7 +89,7 @@ }; sysctrl: system-controller@802000 { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x802000 0x1000>; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index f5871b1d1ec4..555bc6b6720f 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -213,7 +213,7 @@ }; sysctrl: sysctrl { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; reg = <0x3e00000 0x00100000>; }; -- cgit v1.2.3 From a332f5f96b2724a436d3a75b0bbf053d0a002c02 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Tue, 29 Sep 2020 22:14:45 +0800 Subject: ARM: dts: hisilicon: add SD5203 dts Add sd5203.dts for Hisilicon SD5203 SoC platform. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm/boot/dts/sd5203.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..1d1262df5c55 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000..3cc9a23910be --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "H836ASDJ", "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +}; -- cgit v1.2.3 From ba90e0c92666979298a2c42ca396ac56d00cf33e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 30 Sep 2020 15:20:27 +0300 Subject: dt-bindings: ti-serdes-mux: Add defines for J7200 SoC There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by: Roger Quadros Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Acked-by: Rob Herring Acked-by: Peter Rosin Cc: Peter Rosin Link: https://lore.kernel.org/r/20200930122032.23481-2-rogerq@ti.com --- include/dt-bindings/mux/ti-serdes.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 146d0685a925..9047ec6bd3cf 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -68,4 +68,26 @@ #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 +/* J7200 */ + +#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 +#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 +#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 +#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 +#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J7200_SERDES0_LANE3_USB 0x2 +#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */ -- cgit v1.2.3 From 1509295295c03c570bd65c3e393b334c188218cd Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 30 Sep 2020 15:20:28 +0300 Subject: arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux The SERDES lane control mux registers are present in the CTRLMMR space. Signed-off-by: Roger Quadros Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20200930122032.23481-3-rogerq@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 4a4fcd24f852..8997276158ca 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -18,6 +18,21 @@ }; }; + scm_conf: scm-conf@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: serdes-ln-ctrl@4080 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; -- cgit v1.2.3 From 9a09e6e9cfcf5424e78636e9b9585de5c07407bc Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 30 Sep 2020 15:20:29 +0300 Subject: arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX The USB controller can be connected to one of the 2 lanes of SERDES0 using a MUX. Add a MUX controller node for that. Signed-off-by: Roger Quadros Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20200930122032.23481-4-rogerq@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 8997276158ca..c638c3d8c0f2 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -31,6 +31,12 @@ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ }; + + usb_serdes_mux: mux-controller@4000 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; }; gic500: interrupt-controller@1800000 { -- cgit v1.2.3 From 6197d7139d128d3391a94bfad467ffe349a869a6 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 30 Sep 2020 15:20:30 +0300 Subject: arm64: dts: ti: k3-j7200-main: Add USB controller j7200 has on USB controller instance. Add that. Signed-off-by: Roger Quadros Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20200930122032.23481-5-rogerq@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index c638c3d8c0f2..72d6496e88dd 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -416,4 +416,34 @@ no-1-8-v; dma-coherent; }; + + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; + dma-coherent; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; }; -- cgit v1.2.3 From e38a45b0192c4562e610c9c81e4c742b48fa69f0 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 30 Sep 2020 15:20:31 +0300 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function First two lanes of SERDES is connected to PCIe, third lane is connected to QSGMII and the last lane is connected to USB. However, Cadence torrent SERDES doesn't support more than 2 protocols at the same time. Configure it only for PCIe and QSGMII. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Roger Quadros Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 1541311cecb4..ddbc2163e698 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -7,6 +7,7 @@ #include "k3-j7200-som-p0.dtsi" #include +#include / { chosen { @@ -185,3 +186,8 @@ ti,driver-strength-ohm = <50>; disable-wp; }; + +&serdes_ln_ctrl { + idle-states = , , + , ; +}; -- cgit v1.2.3 From bbcb0522ae0cea0f2561e7dad243f8a3d5ab5559 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 30 Sep 2020 15:20:32 +0300 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Add USB support The board uses lane 3 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, QSGMII and USB super-speed. It has been chosen to use PCI2 and QSGMII as default. So restrict USB0 to high-speed mode. Signed-off-by: Roger Quadros Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20200930122032.23481-7-rogerq@ti.com --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ddbc2163e698..ef03e7636b66 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -69,6 +69,12 @@ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ + >; + }; }; &wkup_uart0 { @@ -191,3 +197,19 @@ idle-states = , , , ; }; + +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; -- cgit v1.2.3 From 737e7610b545cc901a9696083c1824a7104b8d1b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 15 Aug 2020 20:19:57 +0200 Subject: ARM: dts: meson8: remove two invalid interrupt lines from the GPU node The 3.10 vendor kernel defines the following GPU 20 interrupt lines: #define INT_MALI_GP AM_IRQ(160) #define INT_MALI_GP_MMU AM_IRQ(161) #define INT_MALI_PP AM_IRQ(162) #define INT_MALI_PMU AM_IRQ(163) #define INT_MALI_PP0 AM_IRQ(164) #define INT_MALI_PP0_MMU AM_IRQ(165) #define INT_MALI_PP1 AM_IRQ(166) #define INT_MALI_PP1_MMU AM_IRQ(167) #define INT_MALI_PP2 AM_IRQ(168) #define INT_MALI_PP2_MMU AM_IRQ(169) #define INT_MALI_PP3 AM_IRQ(170) #define INT_MALI_PP3_MMU AM_IRQ(171) #define INT_MALI_PP4 AM_IRQ(172) #define INT_MALI_PP4_MMU AM_IRQ(173) #define INT_MALI_PP5 AM_IRQ(174) #define INT_MALI_PP5_MMU AM_IRQ(175) #define INT_MALI_PP6 AM_IRQ(176) #define INT_MALI_PP6_MMU AM_IRQ(177) #define INT_MALI_PP7 AM_IRQ(178) #define INT_MALI_PP7_MMU AM_IRQ(179) However, the driver from the 3.10 vendor kernel does not use the following four interrupt lines: - INT_MALI_PP3 - INT_MALI_PP3_MMU - INT_MALI_PP7 - INT_MALI_PP7_MMU Drop the "pp3" and "ppmmu3" interrupt lines. This is also important because there is no matching entry in interrupt-names for it (meaning the "pp2" interrupt is actually assigned to the "pp3" interrupt line). Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU") Reported-by: Thomas Graichen Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Tested-by: thomas graichen Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20200815181957.408649-1-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 277c0bb10453..04688e8abce2 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -240,8 +240,6 @@ , , , - , - , , , , -- cgit v1.2.3 From 925595f77f8bcf0159d9ff97141eeb1fed506888 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 2 Oct 2020 22:34:15 +0900 Subject: ARM: mstar: Add interrupt controller to base dtsi Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7 dtsi. All of the known SoCs have both and at the same place with their common IPs using the same interrupt lines. Link: https://lore.kernel.org/r/20201002133418.2250277-3-daniel@0x0f.com Signed-off-by: Daniel Palmer Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mstar-v7.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b7b9b793736..aec841b52ca4 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -85,6 +85,25 @@ mask = <0x79>; }; + intc_fiq: interrupt-controller@201310 { + compatible = "mstar,mst-intc"; + reg = <0x201310 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <96 127>; + }; + + intc_irq: interrupt-controller@201350 { + compatible = "mstar,mst-intc"; + reg = <0x201350 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <32 95>; + mstar,intc-no-eoi; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>; -- cgit v1.2.3 From 0434460442a7f234b99d9361ca397e0bbb48fa60 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 2 Oct 2020 22:34:16 +0900 Subject: ARM: mstar: Add interrupt to pm_uart Since we now have support for the interrupt controller pm_uart's interrupt is routed through it make sense to wire up it's interrupt in the device tree. The interrupt is the same for all known chips so it goes in the base dtsi. Link: https://lore.kernel.org/r/20201002133418.2250277-4-daniel@0x0f.com Signed-off-by: Daniel Palmer Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mstar-v7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index aec841b52ca4..f07880561e11 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -113,6 +113,7 @@ compatible = "ns16550a"; reg = <0x221000 0x100>; reg-shift = <3>; + interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <172000000>; status = "disabled"; }; -- cgit v1.2.3 From f1ef5b78a76224ee741925abad0a4b3af482d57f Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 2 Oct 2020 22:34:17 +0900 Subject: ARM: mstar: Add mstar prefix to all of the dtsi/dts files Based on Arnd's comment[0] all of the MStar dtsi/dts files should have had a prefix. This moves the files, fixes the Makefile that generates dtbs and fixes up the MAINTAINERS entry. Fixing up some includes in the files themselves is left for a later commit as rolling it into this commit resulted in a confusing diff. 0 - https://lore.kernel.org/linux-arm-kernel/CAK8P3a0maQhfaerwG4KgFZOrUPwueKOp2+MOeG9C=+8ZNzc2Kg@mail.gmail.com/ Link: https://lore.kernel.org/r/20201002133418.2250277-5-daniel@0x0f.com Signed-off-by: Daniel Palmer Signed-off-by: Olof Johansson --- MAINTAINERS | 4 +--- arch/arm/boot/dts/Makefile | 6 +++--- .../boot/dts/infinity-msc313-breadbee_crust.dts | 25 ---------------------- arch/arm/boot/dts/infinity-msc313.dtsi | 14 ------------ arch/arm/boot/dts/infinity.dtsi | 11 ---------- arch/arm/boot/dts/infinity3-msc313e-breadbee.dts | 25 ---------------------- arch/arm/boot/dts/infinity3-msc313e.dtsi | 14 ------------ arch/arm/boot/dts/infinity3.dtsi | 11 ---------- arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts | 25 ---------------------- arch/arm/boot/dts/mercury5-ssc8336n.dtsi | 14 ------------ arch/arm/boot/dts/mercury5.dtsi | 11 ---------- .../dts/mstar-infinity-msc313-breadbee_crust.dts | 25 ++++++++++++++++++++++ arch/arm/boot/dts/mstar-infinity-msc313.dtsi | 14 ++++++++++++ arch/arm/boot/dts/mstar-infinity.dtsi | 11 ++++++++++ .../boot/dts/mstar-infinity3-msc313e-breadbee.dts | 25 ++++++++++++++++++++++ arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi | 14 ++++++++++++ arch/arm/boot/dts/mstar-infinity3.dtsi | 11 ++++++++++ .../dts/mstar-mercury5-ssc8336n-midrived08.dts | 25 ++++++++++++++++++++++ arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi | 14 ++++++++++++ arch/arm/boot/dts/mstar-mercury5.dtsi | 11 ++++++++++ 20 files changed, 154 insertions(+), 156 deletions(-) delete mode 100644 arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts delete mode 100644 arch/arm/boot/dts/infinity-msc313.dtsi delete mode 100644 arch/arm/boot/dts/infinity.dtsi delete mode 100644 arch/arm/boot/dts/infinity3-msc313e-breadbee.dts delete mode 100644 arch/arm/boot/dts/infinity3-msc313e.dtsi delete mode 100644 arch/arm/boot/dts/infinity3.dtsi delete mode 100644 arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts delete mode 100644 arch/arm/boot/dts/mercury5-ssc8336n.dtsi delete mode 100644 arch/arm/boot/dts/mercury5.dtsi create mode 100644 arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts create mode 100644 arch/arm/boot/dts/mstar-infinity-msc313.dtsi create mode 100644 arch/arm/boot/dts/mstar-infinity.dtsi create mode 100644 arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts create mode 100644 arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi create mode 100644 arch/arm/boot/dts/mstar-infinity3.dtsi create mode 100644 arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts create mode 100644 arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi create mode 100644 arch/arm/boot/dts/mstar-mercury5.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 86bfe2421483..b5de0502d94c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2152,9 +2152,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar/* -F: arch/arm/boot/dts/infinity*.dtsi -F: arch/arm/boot/dts/mercury*.dtsi -F: arch/arm/boot/dts/mstar-v7.dtsi +F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a457dca8af40..ce66ffd5a1bb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1371,9 +1371,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8135-evbp1.dtb dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ - infinity-msc313-breadbee_crust.dtb \ - infinity3-msc313e-breadbee.dtb \ - mercury5-ssc8336n-midrived08.dtb + mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity3-msc313e-breadbee.dtb \ + mstar-mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts deleted file mode 100644 index f24c5580d3e4..000000000000 --- a/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "infinity-msc313.dtsi" - -/ { - model = "BreadBee Crust"; - compatible = "thingyjp,breadbee-crust", "mstar,infinity"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/infinity-msc313.dtsi b/arch/arm/boot/dts/infinity-msc313.dtsi deleted file mode 100644 index 42f2b5552c77..000000000000 --- a/arch/arm/boot/dts/infinity-msc313.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "infinity.dtsi" - -/ { - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x4000000>; - }; -}; diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/infinity.dtsi deleted file mode 100644 index cd911adef014..000000000000 --- a/arch/arm/boot/dts/infinity.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-v7.dtsi" - -&imi { - reg = <0xa0000000 0x16000>; -}; diff --git a/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts deleted file mode 100644 index 1f93401c8530..000000000000 --- a/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "infinity3-msc313e.dtsi" - -/ { - model = "BreadBee"; - compatible = "thingyjp,breadbee", "mstar,infinity3"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/infinity3-msc313e.dtsi b/arch/arm/boot/dts/infinity3-msc313e.dtsi deleted file mode 100644 index 4e7239afd823..000000000000 --- a/arch/arm/boot/dts/infinity3-msc313e.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "infinity3.dtsi" - -/ { - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x4000000>; - }; -}; diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/infinity3.dtsi deleted file mode 100644 index 9b918c802654..000000000000 --- a/arch/arm/boot/dts/infinity3.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "infinity.dtsi" - -&imi { - reg = <0xa0000000 0x20000>; -}; diff --git a/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts deleted file mode 100644 index f24bd8cb8e60..000000000000 --- a/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -/dts-v1/; -#include "mercury5-ssc8336n.dtsi" - -/ { - model = "70mai Midrive D08"; - compatible = "70mai,midrived08", "mstar,mercury5"; - - aliases { - serial0 = &pm_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pm_uart { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mercury5-ssc8336n.dtsi deleted file mode 100644 index 7d4a4630c25c..000000000000 --- a/arch/arm/boot/dts/mercury5-ssc8336n.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mercury5.dtsi" - -/ { - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x4000000>; - }; -}; diff --git a/arch/arm/boot/dts/mercury5.dtsi b/arch/arm/boot/dts/mercury5.dtsi deleted file mode 100644 index a7d0dd9d6132..000000000000 --- a/arch/arm/boot/dts/mercury5.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2020 thingy.jp. - * Author: Daniel Palmer - */ - -#include "mstar-v7.dtsi" - -&imi { - reg = <0xa0000000 0x20000>; -}; diff --git a/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts new file mode 100644 index 000000000000..f24c5580d3e4 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "infinity-msc313.dtsi" + +/ { + model = "BreadBee Crust"; + compatible = "thingyjp,breadbee-crust", "mstar,infinity"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity-msc313.dtsi b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi new file mode 100644 index 000000000000..42f2b5552c77 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi new file mode 100644 index 000000000000..cd911adef014 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-v7.dtsi" + +&imi { + reg = <0xa0000000 0x16000>; +}; diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts new file mode 100644 index 000000000000..1f93401c8530 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "infinity3-msc313e.dtsi" + +/ { + model = "BreadBee"; + compatible = "thingyjp,breadbee", "mstar,infinity3"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi new file mode 100644 index 000000000000..4e7239afd823 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity3.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi new file mode 100644 index 000000000000..9b918c802654 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity.dtsi" + +&imi { + reg = <0xa0000000 0x20000>; +}; diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts new file mode 100644 index 000000000000..f24bd8cb8e60 --- /dev/null +++ b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mercury5-ssc8336n.dtsi" + +/ { + model = "70mai Midrive D08"; + compatible = "70mai,midrived08", "mstar,mercury5"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi new file mode 100644 index 000000000000..7d4a4630c25c --- /dev/null +++ b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mercury5.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/mstar-mercury5.dtsi new file mode 100644 index 000000000000..a7d0dd9d6132 --- /dev/null +++ b/arch/arm/boot/dts/mstar-mercury5.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-v7.dtsi" + +&imi { + reg = <0xa0000000 0x20000>; +}; -- cgit v1.2.3 From f6320e326f401e077bf7a042db0740c441ca0c8e Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 2 Oct 2020 22:34:18 +0900 Subject: ARM: mstar: Fix up the fallout from moving the dts/dtsi files Since the dtsi/dts files have been moved some includes are now broken so this fixes up the includes so the dtbs build again. Link: https://lore.kernel.org/r/20201002133418.2250277-6-daniel@0x0f.com Signed-off-by: Daniel Palmer Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts | 2 +- arch/arm/boot/dts/mstar-infinity-msc313.dtsi | 2 +- arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts | 2 +- arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi | 2 +- arch/arm/boot/dts/mstar-infinity3.dtsi | 2 +- arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts | 2 +- arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts index f24c5580d3e4..f9db2ff86f2d 100644 --- a/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts +++ b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include "infinity-msc313.dtsi" +#include "mstar-infinity-msc313.dtsi" / { model = "BreadBee Crust"; diff --git a/arch/arm/boot/dts/mstar-infinity-msc313.dtsi b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi index 42f2b5552c77..3499fde263be 100644 --- a/arch/arm/boot/dts/mstar-infinity-msc313.dtsi +++ b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi @@ -4,7 +4,7 @@ * Author: Daniel Palmer */ -#include "infinity.dtsi" +#include "mstar-infinity.dtsi" / { memory@20000000 { diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts index 1f93401c8530..f0eda80a95cc 100644 --- a/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts +++ b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include "infinity3-msc313e.dtsi" +#include "mstar-infinity3-msc313e.dtsi" / { model = "BreadBee"; diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi index 4e7239afd823..f581b6f89555 100644 --- a/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi @@ -4,7 +4,7 @@ * Author: Daniel Palmer */ -#include "infinity3.dtsi" +#include "mstar-infinity3.dtsi" / { memory@20000000 { diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi index 9b918c802654..9857e2a9934d 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -4,7 +4,7 @@ * Author: Daniel Palmer */ -#include "infinity.dtsi" +#include "mstar-infinity.dtsi" &imi { reg = <0xa0000000 0x20000>; diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts index f24bd8cb8e60..7306b737d9c4 100644 --- a/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts +++ b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include "mercury5-ssc8336n.dtsi" +#include "mstar-mercury5-ssc8336n.dtsi" / { model = "70mai Midrive D08"; diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi index 7d4a4630c25c..3f5a4c029744 100644 --- a/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi +++ b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi @@ -4,7 +4,7 @@ * Author: Daniel Palmer */ -#include "mercury5.dtsi" +#include "mstar-mercury5.dtsi" / { memory@20000000 { -- cgit v1.2.3 From fc772314a3683ab3f19aa68a660a0f70a8e836a4 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 7 Sep 2020 13:18:30 +0100 Subject: arm64: dts: lg: Fix SP805 clocks The SP805 DT binding requires two clocks to be specified, but the two LG platform DTs currently only specify one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux (and U-Boot) SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Link: https://lore.kernel.org/r/20200907121831.242281-6-andre.przywara@arm.com Signed-off-by: Andre Przywara Acked-by: Chanho Min Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/lg/lg1312.dtsi | 4 ++-- arch/arm64/boot/dts/lg/lg1313.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 64f3b135068d..587103eb9536 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -141,8 +141,8 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xfd200000 0x1000>; interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "wdog_clk", "apb_pclk"; }; uart0: serial@fe000000 { compatible = "arm,pl011", "arm,primecell"; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index ac23592ab011..2cea5b18aac7 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -141,8 +141,8 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xfd200000 0x1000>; interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "wdog_clk", "apb_pclk"; }; uart0: serial@fe000000 { compatible = "arm,pl011", "arm,primecell"; -- cgit v1.2.3 From c9794866ac30d9440b327e96b4ecc97d8f0055f6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 7 Sep 2020 13:18:28 +0100 Subject: arm64: dts: lg: Fix SP804 users Even though the SP804 binding allows to specify only one clock, the primecell driver requires a named clock to activate the bus clock. Specify the one clock three times and provide some clock-names, to make the DT match the SP804 and primecell binding. Also add the missing arm,primecell compatible string. Link: https://lore.kernel.org/r/20200907121831.242281-4-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/lg/lg1312.dtsi | 6 +++--- arch/arm64/boot/dts/lg/lg1313.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 587103eb9536..081fe7a9f605 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -131,11 +131,11 @@ ranges; timers: timer@fd100000 { - compatible = "arm,sp804"; + compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xfd100000 0x1000>; interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; }; wdog: watchdog@fd200000 { compatible = "arm,sp805", "arm,primecell"; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 2cea5b18aac7..604bb6975337 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -131,11 +131,11 @@ ranges; timers: timer@fd100000 { - compatible = "arm,sp804"; + compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xfd100000 0x1000>; interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; }; wdog: watchdog@fd200000 { compatible = "arm,sp805", "arm,primecell"; -- cgit v1.2.3 From e916bfacf558ee835c480d2c2dad9d144baf9e1c Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 7 Sep 2020 13:18:27 +0100 Subject: ARM: dts: nspire: Fix SP804 users Even though the SP804 binding allows to specify only one clock, the primecell driver requires a named clock to activate the bus clock. Specify the one clock three times and provide some clock-names, to make the DT match the SP804 and primecell binding. Link: https://lore.kernel.org/r/20200907121831.242281-3-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Olof Johansson --- arch/arm/boot/dts/nspire.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index d9a0fd7524dc..90e033d9141f 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -145,15 +145,19 @@ timer0: timer@900C0000 { reg = <0x900C0000 0x1000>; - - clocks = <&timer_clk>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; }; timer1: timer@900D0000 { reg = <0x900D0000 0x1000>; interrupts = <19>; - - clocks = <&timer_clk>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; }; watchdog: watchdog@90060000 { -- cgit v1.2.3