From e807acbc6fd1d5ff115f9a8eae0c1af6cf1c46c6 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Sat, 16 Jul 2011 10:49:47 +0900 Subject: ARM: GIC: move gic_chip_data structure declaration to header Since Samsung EXYNOS4210 cannot support register banking in GIC, so needs to update CPU interface base address. The 'gic_chip_data' is used for it, this patch moves gic_chip_data structure declaraton to arch/arm/include/asm/hardware/gic.h to use it. Cc: Russell King Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/common/gic.c | 6 ------ arch/arm/include/asm/hardware/gic.h | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4ddd0a6ac7ff..23564edbd849 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock); /* Address of GIC 0 CPU interface */ void __iomem *gic_cpu_base_addr __read_mostly; -struct gic_chip_data { - unsigned int irq_offset; - void __iomem *dist_base; - void __iomem *cpu_base; -}; - /* * Supported arch specific GIC irq extension. * Default make them NULL. diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 0691f9dcc500..435d3f86c708 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); void gic_enable_ppi(unsigned int); + +struct gic_chip_data { + unsigned int irq_offset; + void __iomem *dist_base; + void __iomem *cpu_base; +}; #endif #endif -- cgit v1.2.3