From 7917d14129a5a7241289f06d2c5299c5d03ed529 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 18 Mar 2015 11:24:01 +0800 Subject: ARM: sun8i: Add SMP support for the Allwinner A23 The A23 is a dual Cortex-A7. Add the logic to use the IPs used to control the CPU configuration and the CPU power so that we can bring up secondary CPUs at boot. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 6aa331d11c5e..d6b794cef0b8 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -188,6 +188,7 @@ nodes to be present and contain the properties described below. # On ARM 32-bit systems this property is optional and can be one of: "allwinner,sun6i-a31" + "allwinner,sun8i-a23" "arm,psci" "brcm,brahma-b15" "marvell,armada-375-smp" -- cgit v1.2.3 From 9b799b78372c925d3204567741e3ff8fe0cc1c7d Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Sat, 9 May 2015 09:53:54 +0200 Subject: ARM: Add STM32 family machine STMicrolectronics's STM32 series is a family of Cortex-M microcontrollers. It is used in various applications, and proposes a wide range of peripherals. Tested-by: Chanwoo Choi Signed-off-by: Maxime Coquelin Signed-off-by: Arnd Bergmann --- Documentation/arm/stm32/overview.txt | 32 ++++++++++++++++++++++++++ Documentation/arm/stm32/stm32f429-overview.txt | 22 ++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 Documentation/arm/stm32/overview.txt create mode 100644 Documentation/arm/stm32/stm32f429-overview.txt (limited to 'Documentation') diff --git a/Documentation/arm/stm32/overview.txt b/Documentation/arm/stm32/overview.txt new file mode 100644 index 000000000000..09aed5588d7c --- /dev/null +++ b/Documentation/arm/stm32/overview.txt @@ -0,0 +1,32 @@ + STM32 ARM Linux Overview + ======================== + +Introduction +------------ + + The STMicroelectronics family of Cortex-M based MCUs are supported by the + 'STM32' platform of ARM Linux. Currently only the STM32F429 is supported. + + +Configuration +------------- + + A generic configuration is provided for STM32 family, and can be used as the + default by + make stm32_defconfig + +Layout +------ + + All the files for multiple machine families are located in the platform code + contained in arch/arm/mach-stm32 + + There is a generic board board-dt.c in the mach folder which support + Flattened Device Tree, which means, it works with any compatible board with + Device Trees. + + +Document Author +--------------- + + Maxime Coquelin diff --git a/Documentation/arm/stm32/stm32f429-overview.txt b/Documentation/arm/stm32/stm32f429-overview.txt new file mode 100644 index 000000000000..5206822bd8ef --- /dev/null +++ b/Documentation/arm/stm32/stm32f429-overview.txt @@ -0,0 +1,22 @@ + STM32F429 Overview + ================== + + Introduction + ------------ + The STM32F429 is a Cortex-M4 MCU aimed at various applications. + It features: + - ARM Cortex-M4 up to 180MHz with FPU + - 2MB internal Flash Memory + - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND) + - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers + - LCD controller & Camera interface + - Cryptographic processor + + Resources + --------- + Datasheet and reference manual are publicly available on ST website: + - http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013 + + Document Author + --------------- + Maxime Coquelin -- cgit v1.2.3 From 8064887e02fd684fa0576cbbcdbc29ceab125c4c Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 20 May 2015 00:03:52 +0200 Subject: ARM: vf610: enable Cortex-M4 configuration on Vybrid SoC This patch allows to build the Kernel for Vybrid (VF6xx) SoC when ARMv7-M CPU is selected. The resulting image runs on the secondary Cortex-M4 core. This core has equally access to all peripherals as the main Cortex-A5 core. However, there is no resource control mechanism, hence when both cores are used simultaneously, orthogonal device tree's are required. The boot CPU is dependent on the SoC variant. The available boards use mostly variants where the Cortex-A5 is the primary and hence the boot CPU. Booting the secondary Cortex-M4 CPU needs SoC specific registers written. There is no in kernel support for this right now, a external userspace utility called "m4boot" can be used to boot the kernel: m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb Signed-off-by: Stefan Agner Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/fsl.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index a5462b6b3c30..2a3ba73f0c5c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -81,12 +81,15 @@ Freescale Vybrid Platform Device Tree Bindings For the Vybrid SoC familiy all variants with DDR controller are supported, which is the VF5xx and VF6xx series. Out of historical reasons, in most places the kernel uses vf610 to refer to the whole familiy. +The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 +core support. Required root node compatible property (one of them): - compatible = "fsl,vf500"; - compatible = "fsl,vf510"; - compatible = "fsl,vf600"; - compatible = "fsl,vf610"; + - compatible = "fsl,vf610m4"; Freescale LS1021A Platform Device Tree Bindings ------------------------------------------------ -- cgit v1.2.3 From 29e5eea06bc19114b1df668f85b605914766a899 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 3 Apr 2015 11:25:54 +0200 Subject: ARM: EXYNOS: Get current parent clock for power domain on/off Using a fixed (by DTS) parent for clocks when turning on the power domain may introduce issues in other drivers. For example when such driver changes the parent during runtime and expects that he is the only place of such change. Do not rely on DTS providing the fixed parent for such clocks. Instead before switching domain off, grab a current parent of a clock with clk_get_parent(). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 5da38c5ed476..e151057d92f0 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -19,9 +19,10 @@ Optional Properties: domains. - clock-names: The following clocks can be specified: - oscclk: Oscillator clock. - - pclkN, clkN: Pairs of parent of input clock and input clock to the - devices in this power domain. Maximum of 4 pairs (N = 0 to 3) - are supported currently. + - clkN: Input clocks to the devices in this power domain. These clocks + will be reparented to oscclk before swithing power domain off. + Their original parent will be brought back after turning on + the domain. Maximum of 4 clocks (N = 0 to 3) are supported. - asbN: Clocks required by asynchronous bridges (ASB) present in the power domain. These clock should be enabled during power domain on/off operations. -- cgit v1.2.3 From d5553cb05a041d7c31e4e70950ecbb4ee52049cb Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Thu, 4 Jun 2015 11:21:02 +0800 Subject: ARM: dts: zx: add an initial zx296702 dts and doc Add initial dts file and document for ZX296702 and board ZX296702-AD1. More peripherals will be added later. Signed-off-by: Jun Nie Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/zte.txt | 15 ++++++++++ .../devicetree/bindings/clock/zx296702-clk.txt | 35 ++++++++++++++++++++++ Documentation/devicetree/bindings/serial/pl011.txt | 2 +- .../devicetree/bindings/vendor-prefixes.txt | 1 + 4 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/zte.txt create mode 100644 Documentation/devicetree/bindings/clock/zx296702-clk.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt new file mode 100644 index 000000000000..3ff5c9e85c1c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.txt @@ -0,0 +1,15 @@ +ZTE platforms device tree bindings +--------------------------------------- + +- ZX296702 board: + Required root node properties: + - compatible = "zte,zx296702-ad1", "zte,zx296702" + +System management required properties: + - compatible = "zte,sysctrl" + +Low power management required properties: + - compatible = "zte,zx296702-pcu" + +Bus matrix required properties: + - compatible = "zte,zx-bus-matrix" diff --git a/Documentation/devicetree/bindings/clock/zx296702-clk.txt b/Documentation/devicetree/bindings/clock/zx296702-clk.txt new file mode 100644 index 000000000000..750442b65505 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zx296702-clk.txt @@ -0,0 +1,35 @@ +Device Tree Clock bindings for ZTE zx296702 + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "zte,zx296702-topcrm-clk": + zx296702 top clock selection, divider and gating + + "zte,zx296702-lsp0crpm-clk" and + "zte,zx296702-lsp1crpm-clk": + zx296702 device level clock selection and gating + +- reg: Address and length of the register set + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h +for the full list of zx296702 clock IDs. + + +topclk: topcrm@0x09800000 { + compatible = "zte,zx296702-topcrm-clk"; + reg = <0x09800000 0x1000>; + #clock-cells = <1>; +}; + +uart0: serial@0x09405000 { + compatible = "zte,zx296702-uart"; + reg = <0x09405000 0x1000>; + interrupts = ; + clocks = <&lsp1clk ZX296702_UART0_PCLK>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index ba3ecb8cb5a1..cbae3d9a0278 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -1,7 +1,7 @@ * ARM AMBA Primecell PL011 serial UART Required properties: -- compatible: must be "arm,primecell", "arm,pl011" +- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart" - reg: exactly one register range with length 0x1000 - interrupts: exactly one interrupt specifier diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..717ffd5a3563 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -211,3 +211,4 @@ xillybus Xillybus Ltd. xlnx Xilinx zyxel ZyXEL Communications Corp. zarlink Zarlink Semiconductor +zte ZTE Corp. -- cgit v1.2.3