From 75efba81513133fdd2f9c1ac9213bf86cc622f62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Tue, 4 Mar 2014 11:50:35 +0100 Subject: CNS3xxx: Fix a WARN() related to IRQ allocation. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit WARNING: at drivers/irqchip/irq-gic.c:952 gic_init_bases+0xe4/0x2b8() Cannot allocate irq_descs @ IRQ16, assuming pre-allocated Backtrace: gic_init_bases from cns3xxx_init_irq+0x24/0x34 cns3xxx_init_irq from init_IRQ+0x24/0x2c init_IRQ from start_kernel+0x1a8/0x338 start_kernel from 0x2000806c The problem is that 64 CNS3xxx CPU interrupts, starting at 32, are allocated by the ARM platform-independent code (as requested by machine_desc->nr_irqs = 96), and then the GIC code tries to allocate them again. Tested on Gateworks Laguna board, masqueraded as CNS3420VB. Signed-off-by: Krzysztof Hałasa Signed-off-by: Arnd Bergmann --- arch/arm/mach-cns3xxx/cns3420vb.c | 1 - arch/arm/mach-cns3xxx/core.c | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm/mach-cns3xxx') diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index ce096d678aa4..d863d8729edc 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -246,7 +246,6 @@ static void __init cns3420_map_io(void) MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .atag_offset = 0x100, - .nr_irqs = NR_IRQS_CNS3XXX, .map_io = cns3420_map_io, .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index e38b279f402c..0aaeb8c19c9c 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -368,7 +368,6 @@ static const char *cns3xxx_dt_compat[] __initdata = { DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") .dt_compat = cns3xxx_dt_compat, - .nr_irqs = NR_IRQS_CNS3XXX, .map_io = cns3xxx_map_io, .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, -- cgit v1.2.3