From dfbdd3d55403ebd29a355e907e53576ce57c6d96 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 19 Mar 2014 12:07:34 +0000 Subject: ARM: l2c: exynos: remove cache size override The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King --- arch/arm/mach-exynos/exynos.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index e6828fb46034..a51bf25e7523 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -32,9 +32,6 @@ #include "mfc.h" #include "regs-pmu.h" -#define L2_AUX_VAL 0x3c470001 -#define L2_AUX_MASK 0xc200ffff - static struct map_desc exynos4_iodesc[] __initdata = { { .virtual = (unsigned long)S3C_VA_SYS, @@ -323,7 +320,7 @@ static int __init exynos4_l2x0_cache_init(void) { int ret; - ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); + ret = l2x0_of_init(0x3c400001, 0xc20fffff); if (ret) return ret; -- cgit v1.2.3