From 460d4117a4714f3e9ae600974df03632139728ec Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Dec 2016 11:39:37 +0100 Subject: ARM: shmobile: apmu: Add more register documentation Signed-off-by: Geert Uytterhoeven Tested-by: Hiep Cao Minh Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/platsmp-apmu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-shmobile') diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 0c6bb458b7a4..933f9b902405 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -31,9 +31,15 @@ static struct { int bit; } apmu_cpus[NR_CPUS]; -#define WUPCR_OFFS 0x10 -#define PSTR_OFFS 0x40 -#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) +#define WUPCR_OFFS 0x10 /* Wake Up Control Register */ +#define PSTR_OFFS 0x40 /* Power Status Register */ +#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) + /* CPUn Power Status Control Register */ + +/* Power Status Register */ +#define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */ +#define CPUST_RUN 0 /* Run Mode */ +#define CPUST_STANDBY 3 /* CoreStandby Mode */ static int __maybe_unused apmu_power_on(void __iomem *p, int bit) { @@ -59,7 +65,7 @@ static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit) int k; for (k = 0; k < 1000; k++) { - if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) + if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY) return 1; mdelay(1); -- cgit v1.2.3 From 10f778a97845e8b10af8878af99c9cfe6c31baf9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Dec 2016 11:39:38 +0100 Subject: ARM: shmobile: apmu: Add debug resource reset for secondary CPU boot In debug mode (MD21=1), reset requests derived from power-shutoff to the AP-system CPU cores must be enabled before the AP-system CPU cores resume from power-shutoff for the first time. Else resume may fail, causing the system to hang during boot. As setting these bits is a no-op in normal mode, there's no need to check the actual state of MD21 first. Inspired by CPU-specific patches in the BSP by Hisashi Nakamura . Signed-off-by: Geert Uytterhoeven Tested-by: Hiep Cao Minh Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/platsmp-apmu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/mach-shmobile') diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 933f9b902405..7e4ca6788be5 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -35,12 +35,18 @@ static struct { #define PSTR_OFFS 0x40 /* Power Status Register */ #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) /* CPUn Power Status Control Register */ +#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */ /* Power Status Register */ #define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */ #define CPUST_RUN 0 /* Run Mode */ #define CPUST_STANDBY 3 /* CoreStandby Mode */ +/* Debug Resource Reset Control Register */ +#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */ +#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */ +#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */ + static int __maybe_unused apmu_power_on(void __iomem *p, int bit) { /* request power on */ @@ -84,6 +90,8 @@ static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu) #ifdef CONFIG_SMP static void apmu_init_cpu(struct resource *res, int cpu, int bit) { + u32 x; + if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem) return; @@ -91,6 +99,11 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit) apmu_cpus[cpu].bit = bit; pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res); + + /* Setup for debug mode */ + x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS); + x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN; + writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS); } static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit), -- cgit v1.2.3 From d03c8f78d03af2a46127537dd1daa67164e53c09 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Dec 2016 11:39:39 +0100 Subject: ARM: shmobile: apmu: Allow booting secondary CPU cores in debug mode Now debug resource reset is handled properly, allow booting secondary CPU cores when hardware debug mode is enabled (MD21=1) on SoCs using the "renesas,apmu" enable method. Signed-off-by: Geert Uytterhoeven Tested-by: Hiep Cao Minh Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/platsmp-apmu.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'arch/arm/mach-shmobile') diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 7e4ca6788be5..e19266844e16 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -216,21 +216,9 @@ static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus) rcar_gen2_pm_init(); } -static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu, - struct task_struct *idle) -{ - /* Error out when hardware debug mode is enabled */ - if (rcar_gen2_read_mode_pins() & BIT(21)) { - pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu); - return -ENOTSUPP; - } - - return shmobile_smp_apmu_boot_secondary(cpu, idle); -} - static struct smp_operations apmu_smp_ops __initdata = { .smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt, - .smp_boot_secondary = shmobile_smp_apmu_boot_secondary_md21, + .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_can_disable = shmobile_smp_cpu_can_disable, .cpu_die = shmobile_smp_apmu_cpu_die, -- cgit v1.2.3 From 367ed998fa3e04d8bde42f431e880cd3e5922095 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Dec 2016 11:39:40 +0100 Subject: ARM: shmobile: r8a7791: Allow booting secondary CPU cores in debug mode Now debug resource reset is handled properly, allow booting secondary CPU cores when hardware debug mode is enabled (MD21=1, SW8-4=OFF on koelsch) on legacy r8a7791. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7791.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'arch/arm/mach-shmobile') diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c index 2d6417af73b5..2948c22cfc53 100644 --- a/arch/arm/mach-shmobile/smp-r8a7791.c +++ b/arch/arm/mach-shmobile/smp-r8a7791.c @@ -42,21 +42,9 @@ static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus) rcar_gen2_pm_init(); } -static int r8a7791_smp_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - /* Error out when hardware debug mode is enabled */ - if (rcar_gen2_read_mode_pins() & BIT(21)) { - pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu); - return -ENOTSUPP; - } - - return shmobile_smp_apmu_boot_secondary(cpu, idle); -} - const struct smp_operations r8a7791_smp_ops __initconst = { .smp_prepare_cpus = r8a7791_smp_prepare_cpus, - .smp_boot_secondary = r8a7791_smp_boot_secondary, + .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_can_disable = shmobile_smp_cpu_can_disable, .cpu_die = shmobile_smp_apmu_cpu_die, -- cgit v1.2.3 From 70def3e53694a65c5583fb5f411491a5074bab18 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Dec 2016 11:39:41 +0100 Subject: ARM: shmobile: rcar-gen2: Remove unused rcar_gen2_read_mode_pins() After 1. commit 9f5ce39ddb8f68b3 ("ARM: shmobile: rcar-gen2: Obtain extal frequency from DT"), 2. commit 80951f04c3f92533 ("ARM: shmobile: rcar-gen2: Stop passing mode pins state to clock driver"), 3. and handling of debug resource reset, there are no more users of rcar_gen2_read_mode_pins() left. Remove the function and its support definitions. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/rcar-gen2.h | 2 -- arch/arm/mach-shmobile/setup-rcar-gen2.c | 18 ------------------ 2 files changed, 20 deletions(-) (limited to 'arch/arm/mach-shmobile') diff --git a/arch/arm/mach-shmobile/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h index 8a66b4aae035..6792e249cf56 100644 --- a/arch/arm/mach-shmobile/rcar-gen2.h +++ b/arch/arm/mach-shmobile/rcar-gen2.h @@ -2,8 +2,6 @@ #define __ASM_RCAR_GEN2_H__ void rcar_gen2_timer_init(void); -#define MD(nr) BIT(nr) -u32 rcar_gen2_read_mode_pins(void); void rcar_gen2_reserve(void); void rcar_gen2_pm_init(void); diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index ac63fa407b64..52d466b75973 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -29,24 +29,6 @@ #include "common.h" #include "rcar-gen2.h" -#define MODEMR 0xe6160060 - -u32 rcar_gen2_read_mode_pins(void) -{ - static u32 mode; - static bool mode_valid; - - if (!mode_valid) { - void __iomem *modemr = ioremap_nocache(MODEMR, 4); - BUG_ON(!modemr); - mode = ioread32(modemr); - iounmap(modemr); - mode_valid = true; - } - - return mode; -} - static unsigned int __init get_extal_freq(void) { struct device_node *cpg, *extal; -- cgit v1.2.3 From aa7f39d51e33555fc45645c08bc74a74e22b166f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 25 Jan 2017 10:02:13 +0100 Subject: ARM: shmobile: rcar-gen2: Add more register documentation Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-shmobile') diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c index dd9ac366868f..0178da7ace82 100644 --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c @@ -20,14 +20,30 @@ /* RST */ #define RST 0xe6160000 -#define CA15BAR 0x0020 -#define CA7BAR 0x0030 -#define CA15RESCNT 0x0040 -#define CA7RESCNT 0x0044 + +#define CA15BAR 0x0020 /* CA15 Boot Address Register */ +#define CA7BAR 0x0030 /* CA7 Boot Address Register */ +#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */ +#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */ + +/* SYS Boot Address Register */ +#define SBAR_BAREN BIT(4) /* SBAR is valid */ + +/* Reset Control Registers */ +#define CA15RESCNT_CODE 0xa5a50000 +#define CA15RESCNT_CPUS 0xf /* CPU0-3 */ +#define CA7RESCNT_CODE 0x5a5a0000 +#define CA7RESCNT_CPUS 0xf /* CPU0-3 */ + /* On-chip RAM */ #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */ +static inline u32 phys_to_sbar(phys_addr_t addr) +{ + return (addr >> 8) & 0xfffffc00; +} + /* SYSC */ #define SYSCIER 0x0c #define SYSCIMR 0x10 @@ -82,22 +98,24 @@ void __init rcar_gen2_pm_init(void) /* setup reset vectors */ p = ioremap_nocache(RST, 0x63); - bar = (boot_vector_addr >> 8) & 0xfffffc00; + bar = phys_to_sbar(boot_vector_addr); if (has_a15) { writel_relaxed(bar, p + CA15BAR); - writel_relaxed(bar | 0x10, p + CA15BAR); + writel_relaxed(bar | SBAR_BAREN, p + CA15BAR); /* de-assert reset for CA15 CPUs */ - writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | - 0xa5a50000, p + CA15RESCNT); + writel_relaxed((readl_relaxed(p + CA15RESCNT) & + ~CA15RESCNT_CPUS) | CA15RESCNT_CODE, + p + CA15RESCNT); } if (has_a7) { writel_relaxed(bar, p + CA7BAR); - writel_relaxed(bar | 0x10, p + CA7BAR); + writel_relaxed(bar | SBAR_BAREN, p + CA7BAR); /* de-assert reset for CA7 CPUs */ - writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | - 0x5a5a0000, p + CA7RESCNT); + writel_relaxed((readl_relaxed(p + CA7RESCNT) & + ~CA7RESCNT_CPUS) | CA7RESCNT_CODE, + p + CA7RESCNT); } iounmap(p); -- cgit v1.2.3