From 30da66eafc015cd7e952829eaf8f86d8680f86d9 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 9 Jan 2013 17:39:51 -0800 Subject: ARM: SAMSUNG: Export MIPI CSIS/DSIM PHY control functions The s5p_csis_phy_enable/s5p_dsim_phy_enable functions are now used directly by corresponding drivers and thus need to be exported so the drivers can be built as modules. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/setup-mipiphy.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c index 147459327601..66df315990a7 100644 --- a/arch/arm/plat-samsung/setup-mipiphy.c +++ b/arch/arm/plat-samsung/setup-mipiphy.c @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -50,8 +51,10 @@ int s5p_csis_phy_enable(int id, bool on) { return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); } +EXPORT_SYMBOL(s5p_csis_phy_enable); int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) { return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); } +EXPORT_SYMBOL(s5p_dsim_phy_enable); -- cgit v1.2.3 From d9cdeb814fd6bb1b5eaa49c5848f10ba7acf992a Mon Sep 17 00:00:00 2001 From: Inderpal Singh Date: Thu, 4 Apr 2013 16:01:15 +0900 Subject: ARM: SAMSUNG: check processor type before cache restoration in resume Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check the same before restoring the cache in resume. This is needed for single kernel image. Signed-off-by: Inderpal Singh Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/s5p-sleep.S | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dadf8790..a030e7301da8 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S @@ -25,6 +25,9 @@ #include #include +#define CPU_MASK 0xff0ffff0 +#define CPU_CORTEX_A9 0x410fc090 + /* * The following code is located into the .data section. This is to * allow l2x0_regs_phys to be accessed with a relative load while we @@ -51,6 +54,12 @@ ENTRY(s3c_cpu_resume) #ifdef CONFIG_CACHE_L2X0 + mrc p15, 0, r0, c0, c0, 0 + ldr r1, =CPU_MASK + and r0, r0, r1 + ldr r1, =CPU_CORTEX_A9 + cmp r0, r1 + bne resume_l2on adr r0, l2x0_regs_phys ldr r0, [r0] ldr r1, [r0, #L2X0_R_PHY_BASE] -- cgit v1.2.3