From 721cabf6c6600dbe689ee2782bc087270e97e652 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 17 Feb 2017 20:02:44 +0100 Subject: soc: imx: move PGC handling to a new GPC driver This is an almost complete re-write of the previous GPC power gating control code found in the IMX architecture code. It supports both the old and the new DT binding, allowing more domains to be added later and generally makes the driver easier to extend, while keeping compatibility with existing DTBs. As the result, all functionality regarding the power gating controller gets removed from the IMX architecture GPC driver. It keeps only the IRQ controller code in the architecture, as this is closely coupled to the CPU idle implementation. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/mach-imx/gpc.c | 217 ------------------------------------------------ 1 file changed, 217 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 1dc2a34b9dbd..93f584ba0130 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -10,26 +10,17 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include -#include #include #include #include #include #include #include -#include -#include -#include #include #include "common.h" #include "hardware.h" -#define GPC_CNTR 0x000 #define GPC_IMR1 0x008 -#define GPC_PGC_GPU_PDN 0x260 -#define GPC_PGC_GPU_PUPSCR 0x264 -#define GPC_PGC_GPU_PDNSCR 0x268 #define GPC_PGC_CPU_PDN 0x2a0 #define GPC_PGC_CPU_PUPSCR 0x2a4 #define GPC_PGC_CPU_PDNSCR 0x2a8 @@ -39,18 +30,6 @@ #define IMR_NUM 4 #define GPC_MAX_IRQS (IMR_NUM * 32) -#define GPU_VPU_PUP_REQ BIT(1) -#define GPU_VPU_PDN_REQ BIT(0) - -#define GPC_CLK_MAX 6 - -struct pu_domain { - struct generic_pm_domain base; - struct regulator *reg; - struct clk *clk[GPC_CLK_MAX]; - int num_clks; -}; - static void __iomem *gpc_base; static u32 gpc_wake_irqs[IMR_NUM]; static u32 gpc_saved_imrs[IMR_NUM]; @@ -296,199 +275,3 @@ void __init imx_gpc_check_dt(void) gpc_base = of_iomap(np, 0); } } - -static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) -{ - int iso, iso2sw; - u32 val; - - /* Read ISO and ISO2SW power down delays */ - val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR); - iso = val & 0x3f; - iso2sw = (val >> 8) & 0x3f; - - /* Gate off PU domain when GPU/VPU when powered down */ - writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); - - /* Request GPC to power down GPU/VPU */ - val = readl_relaxed(gpc_base + GPC_CNTR); - val |= GPU_VPU_PDN_REQ; - writel_relaxed(val, gpc_base + GPC_CNTR); - - /* Wait ISO + ISO2SW IPG clock cycles */ - ndelay((iso + iso2sw) * 1000 / 66); -} - -static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) -{ - struct pu_domain *pu = container_of(genpd, struct pu_domain, base); - - _imx6q_pm_pu_power_off(genpd); - - if (pu->reg) - regulator_disable(pu->reg); - - return 0; -} - -static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) -{ - struct pu_domain *pu = container_of(genpd, struct pu_domain, base); - int i, ret, sw, sw2iso; - u32 val; - - if (pu->reg) - ret = regulator_enable(pu->reg); - if (pu->reg && ret) { - pr_err("%s: failed to enable regulator: %d\n", __func__, ret); - return ret; - } - - /* Enable reset clocks for all devices in the PU domain */ - for (i = 0; i < pu->num_clks; i++) - clk_prepare_enable(pu->clk[i]); - - /* Gate off PU domain when GPU/VPU when powered down */ - writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); - - /* Read ISO and ISO2SW power down delays */ - val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR); - sw = val & 0x3f; - sw2iso = (val >> 8) & 0x3f; - - /* Request GPC to power up GPU/VPU */ - val = readl_relaxed(gpc_base + GPC_CNTR); - val |= GPU_VPU_PUP_REQ; - writel_relaxed(val, gpc_base + GPC_CNTR); - - /* Wait ISO + ISO2SW IPG clock cycles */ - ndelay((sw + sw2iso) * 1000 / 66); - - /* Disable reset clocks for all devices in the PU domain */ - for (i = 0; i < pu->num_clks; i++) - clk_disable_unprepare(pu->clk[i]); - - return 0; -} - -static struct generic_pm_domain imx6q_arm_domain = { - .name = "ARM", -}; - -static struct pu_domain imx6q_pu_domain = { - .base = { - .name = "PU", - .power_off = imx6q_pm_pu_power_off, - .power_on = imx6q_pm_pu_power_on, - }, -}; - -static struct generic_pm_domain imx6sl_display_domain = { - .name = "DISPLAY", -}; - -static struct generic_pm_domain *imx_gpc_domains[] = { - &imx6q_arm_domain, - &imx6q_pu_domain.base, - &imx6sl_display_domain, -}; - -static struct genpd_onecell_data imx_gpc_onecell_data = { - .domains = imx_gpc_domains, - .num_domains = ARRAY_SIZE(imx_gpc_domains), -}; - -static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) -{ - struct clk *clk; - int i, ret; - - imx6q_pu_domain.reg = pu_reg; - - for (i = 0; ; i++) { - clk = of_clk_get(dev->of_node, i); - if (IS_ERR(clk)) - break; - if (i >= GPC_CLK_MAX) { - dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX); - goto clk_err; - } - imx6q_pu_domain.clk[i] = clk; - } - imx6q_pu_domain.num_clks = i; - - /* Enable power always in case bootloader disabled it. */ - imx6q_pm_pu_power_on(&imx6q_pu_domain.base); - - if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) - return 0; - - imx6q_pu_domain.base.states = devm_kzalloc(dev, - sizeof(*imx6q_pu_domain.base.states), - GFP_KERNEL); - if (!imx6q_pu_domain.base.states) - return -ENOMEM; - - imx6q_pu_domain.base.states[0].power_off_latency_ns = 25000; - imx6q_pu_domain.base.states[0].power_on_latency_ns = 2000000; - imx6q_pu_domain.base.state_count = 1; - - for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++) - pm_genpd_init(imx_gpc_domains[i], NULL, false); - - ret = of_genpd_add_provider_onecell(dev->of_node, - &imx_gpc_onecell_data); - if (ret) - goto power_off; - - return 0; - -power_off: - imx6q_pm_pu_power_off(&imx6q_pu_domain.base); -clk_err: - while (i--) - clk_put(imx6q_pu_domain.clk[i]); - imx6q_pu_domain.reg = NULL; - return -EINVAL; -} - -static int imx_gpc_probe(struct platform_device *pdev) -{ - struct regulator *pu_reg; - int ret; - - /* bail out if DT too old and doesn't provide the necessary info */ - if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells")) - return 0; - - pu_reg = devm_regulator_get_optional(&pdev->dev, "pu"); - if (PTR_ERR(pu_reg) == -ENODEV) - pu_reg = NULL; - if (IS_ERR(pu_reg)) { - ret = PTR_ERR(pu_reg); - dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret); - return ret; - } - - return imx_gpc_genpd_init(&pdev->dev, pu_reg); -} - -static const struct of_device_id imx_gpc_dt_ids[] = { - { .compatible = "fsl,imx6q-gpc" }, - { .compatible = "fsl,imx6sl-gpc" }, - { } -}; - -static struct platform_driver imx_gpc_driver = { - .driver = { - .name = "imx-gpc", - .of_match_table = imx_gpc_dt_ids, - }, - .probe = imx_gpc_probe, -}; - -static int __init imx_pgc_init(void) -{ - return platform_driver_register(&imx_gpc_driver); -} -subsys_initcall(imx_pgc_init); -- cgit v1.2.3 From 07d76e953b5ec616f3d4c2d807e911e37312dc72 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 28 Mar 2017 13:42:53 +0100 Subject: ARM: tegra: Remove unnecessary inclusion of flowctrl header The Tegra flowctrl.h header is included unnecessarily by the Tegra sleep.S source file. Remove this unnecessary inclusion. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep.S | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index f024a5109e8e..5e3496753df1 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -30,8 +30,6 @@ #include #include "iomap.h" - -#include "flowctrl.h" #include "sleep.h" #define CLK_RESET_CCLK_BURST 0x20 -- cgit v1.2.3 From 7e10cf743634a6b0f3cf63046c49294b38254fe9 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 28 Mar 2017 13:42:54 +0100 Subject: soc/tegra: Move Tegra flowctrl driver The flowctrl driver is required for both ARM and ARM64 Tegra devices and in order to enable support for it for ARM64, move the Tegra flowctrl driver into drivers/soc/tegra. By moving the flowctrl driver, tegra_flowctrl_init() is now called by via an early initcall and to prevent this function from attempting to mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()' is also added. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Makefile | 1 - arch/arm/mach-tegra/cpuidle-tegra20.c | 3 +- arch/arm/mach-tegra/flowctrl.c | 171 ---------------------------------- arch/arm/mach-tegra/flowctrl.h | 66 ------------- arch/arm/mach-tegra/platsmp.c | 2 +- arch/arm/mach-tegra/pm.c | 2 +- arch/arm/mach-tegra/reset-handler.S | 2 +- arch/arm/mach-tegra/sleep-tegra20.S | 3 +- arch/arm/mach-tegra/sleep-tegra30.S | 2 +- arch/arm/mach-tegra/tegra.c | 2 - 10 files changed, 8 insertions(+), 246 deletions(-) delete mode 100644 arch/arm/mach-tegra/flowctrl.c delete mode 100644 arch/arm/mach-tegra/flowctrl.h (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index fffad2426ee4..3b33f0bb78ae 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -2,7 +2,6 @@ asflags-y += -march=armv7-a obj-y += io.o obj-y += irq.o -obj-y += flowctrl.o obj-y += pm.o obj-y += reset.o obj-y += reset-handler.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index afcee04f2616..76e4c83cd5c8 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -26,12 +26,13 @@ #include #include +#include + #include #include #include #include "cpuidle.h" -#include "flowctrl.h" #include "iomap.h" #include "irq.h" #include "pm.h" diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c deleted file mode 100644 index 475e783992fd..000000000000 --- a/arch/arm/mach-tegra/flowctrl.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * arch/arm/mach-tegra/flowctrl.c - * - * functions and macros to control the flowcontroller - * - * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "flowctrl.h" - -static u8 flowctrl_offset_halt_cpu[] = { - FLOW_CTRL_HALT_CPU0_EVENTS, - FLOW_CTRL_HALT_CPU1_EVENTS, - FLOW_CTRL_HALT_CPU1_EVENTS + 8, - FLOW_CTRL_HALT_CPU1_EVENTS + 16, -}; - -static u8 flowctrl_offset_cpu_csr[] = { - FLOW_CTRL_CPU0_CSR, - FLOW_CTRL_CPU1_CSR, - FLOW_CTRL_CPU1_CSR + 8, - FLOW_CTRL_CPU1_CSR + 16, -}; - -static void __iomem *tegra_flowctrl_base; - -static void flowctrl_update(u8 offset, u32 value) -{ - writel(value, tegra_flowctrl_base + offset); - - /* ensure the update has reached the flow controller */ - wmb(); - readl_relaxed(tegra_flowctrl_base + offset); -} - -u32 flowctrl_read_cpu_csr(unsigned int cpuid) -{ - u8 offset = flowctrl_offset_cpu_csr[cpuid]; - - return readl(tegra_flowctrl_base + offset); -} - -void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) -{ - return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); -} - -void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) -{ - return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); -} - -void flowctrl_cpu_suspend_enter(unsigned int cpuid) -{ - unsigned int reg; - int i; - - reg = flowctrl_read_cpu_csr(cpuid); - switch (tegra_get_chip_id()) { - case TEGRA20: - /* clear wfe bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; - /* pwr gating on wfe */ - reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; - break; - case TEGRA30: - case TEGRA114: - case TEGRA124: - /* clear wfe bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; - /* pwr gating on wfi */ - reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; - break; - } - reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ - reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ - reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ - flowctrl_write_cpu_csr(cpuid, reg); - - for (i = 0; i < num_possible_cpus(); i++) { - if (i == cpuid) - continue; - reg = flowctrl_read_cpu_csr(i); - reg |= FLOW_CTRL_CSR_EVENT_FLAG; - reg |= FLOW_CTRL_CSR_INTR_FLAG; - flowctrl_write_cpu_csr(i, reg); - } -} - -void flowctrl_cpu_suspend_exit(unsigned int cpuid) -{ - unsigned int reg; - - /* Disable powergating via flow controller for CPU0 */ - reg = flowctrl_read_cpu_csr(cpuid); - switch (tegra_get_chip_id()) { - case TEGRA20: - /* clear wfe bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; - break; - case TEGRA30: - case TEGRA114: - case TEGRA124: - /* clear wfe bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; - break; - } - reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ - reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ - reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ - flowctrl_write_cpu_csr(cpuid, reg); -} - -static const struct of_device_id matches[] __initconst = { - { .compatible = "nvidia,tegra124-flowctrl" }, - { .compatible = "nvidia,tegra114-flowctrl" }, - { .compatible = "nvidia,tegra30-flowctrl" }, - { .compatible = "nvidia,tegra20-flowctrl" }, - { } -}; - -void __init tegra_flowctrl_init(void) -{ - /* hardcoded fallback if device tree node is missing */ - unsigned long base = 0x60007000; - unsigned long size = SZ_4K; - struct device_node *np; - - np = of_find_matching_node(NULL, matches); - if (np) { - struct resource res; - - if (of_address_to_resource(np, 0, &res) == 0) { - size = resource_size(&res); - base = res.start; - } - - of_node_put(np); - } - - tegra_flowctrl_base = ioremap_nocache(base, size); -} diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h deleted file mode 100644 index 73a9c5016c1a..000000000000 --- a/arch/arm/mach-tegra/flowctrl.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * arch/arm/mach-tegra/flowctrl.h - * - * functions and macros to control the flowcontroller - * - * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __MACH_TEGRA_FLOWCTRL_H -#define __MACH_TEGRA_FLOWCTRL_H - -#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 -#define FLOW_CTRL_WAITEVENT (2 << 29) -#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) -#define FLOW_CTRL_JTAG_RESUME (1 << 28) -#define FLOW_CTRL_SCLK_RESUME (1 << 27) -#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) -#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) -#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) -#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) -#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) -#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) -#define FLOW_CTRL_CPU0_CSR 0x8 -#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) -#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) -#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) -#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) -#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ - FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ - FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) -#define FLOW_CTRL_CSR_ENABLE (1 << 0) -#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 -#define FLOW_CTRL_CPU1_CSR 0x18 - -#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) -#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) -#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 - -#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) -#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) -#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) - -#ifndef __ASSEMBLY__ -u32 flowctrl_read_cpu_csr(unsigned int cpuid); -void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value); -void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); - -void flowctrl_cpu_suspend_enter(unsigned int cpuid); -void flowctrl_cpu_suspend_exit(unsigned int cpuid); - -void tegra_flowctrl_init(void); -#endif - -#endif diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 75620ae73913..b5a2afe99101 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -30,7 +31,6 @@ #include #include "common.h" -#include "flowctrl.h" #include "iomap.h" #include "reset.h" diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index b0f48a3946fa..1ad5719779b0 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -38,7 +39,6 @@ #include #include -#include "flowctrl.h" #include "iomap.h" #include "pm.h" #include "reset.h" diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index e3070fdab80b..805f306fa6f7 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -17,12 +17,12 @@ #include #include +#include #include #include #include -#include "flowctrl.h" #include "iomap.h" #include "reset.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index f5d19667484e..5c8e638ee51a 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -20,6 +20,8 @@ #include +#include + #include #include #include @@ -27,7 +29,6 @@ #include "irammap.h" #include "sleep.h" -#include "flowctrl.h" #define EMC_CFG 0xc #define EMC_ADR_CFG 0x10 diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 16e5ff03383c..dd4a67dabd91 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -16,13 +16,13 @@ #include +#include #include #include #include #include -#include "flowctrl.h" #include "irammap.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e01cbca196b5..649e9e8c7bcc 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -48,7 +48,6 @@ #include "board.h" #include "common.h" #include "cpuidle.h" -#include "flowctrl.h" #include "iomap.h" #include "irq.h" #include "pm.h" @@ -75,7 +74,6 @@ static void __init tegra_init_early(void) { of_register_trusted_foundations(); tegra_cpu_reset_handler_init(); - tegra_flowctrl_init(); } static void __init tegra_dt_init_irq(void) -- cgit v1.2.3 From 52835d59fc6cc7f3c3cfdb4a194ddc9ebd6c0c31 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 4 Apr 2017 08:59:27 -0700 Subject: soc: ti: Add ti_sci_pm_domains driver Introduce a ti_sci_pm_domains driver to act as a generic pm domain provider to allow each device to attach and associate it's ti-sci-id so that it can be controlled through the TI SCI protocol. This driver implements a simple genpd where each device node has a phandle to the power domain node and also must provide an index which represents the ID to be passed with TI SCI representing the device using a single phandle cell. The driver manually parses the phandle to get the cell value. Through this interface the genpd dev_ops start and stop hooks will use TI SCI to turn on and off each device as determined by pm_runtime usage. Reviewed-by: Kevin Hilman Acked-by: Santosh Shilimkar Reviewed-by: Ulf Hansson Signed-off-by: Keerthy Signed-off-by: Nishanth Menon Signed-off-by: Dave Gerlach Signed-off-by: Santosh Shilimkar --- arch/arm/mach-keystone/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 554357035f30..db122356b410 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -10,6 +10,7 @@ config ARCH_KEYSTONE select ARCH_SUPPORTS_BIG_ENDIAN select ZONE_DMA if ARM_LPAE select PINCTRL + select PM_GENERIC_DOMAINS if PM help Support for boards based on the Texas Instruments Keystone family of SoCs. -- cgit v1.2.3 From ae3874cc931b760c08bd6617a45fec1ba97d87f8 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 4 Apr 2017 08:59:28 -0700 Subject: ARM: keystone: Drop PM domain support for k2g K2G will use a different power domain driver than the rest of the keystone family in order to make use of the TI SCI protocol so prevent the standard keystone pm_domain code from registering itself in preparation for a new driver. Acked-by: Santosh Shilimkar Signed-off-by: Lokesh Vutla Signed-off-by: Dave Gerlach Signed-off-by: Santosh Shilimkar --- arch/arm/mach-keystone/pm_domain.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c index 8cbb35765a19..fe57e2692629 100644 --- a/arch/arm/mach-keystone/pm_domain.c +++ b/arch/arm/mach-keystone/pm_domain.c @@ -32,7 +32,9 @@ static struct pm_clk_notifier_block platform_domain_notifier = { }; static const struct of_device_id of_keystone_table[] = { - {.compatible = "ti,keystone"}, + {.compatible = "ti,k2hk"}, + {.compatible = "ti,k2e"}, + {.compatible = "ti,k2l"}, { /* end of list */ }, }; -- cgit v1.2.3 From b6acb2e4d934afffafb318a5c342243a482b25f1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 1 Feb 2017 10:34:41 +0100 Subject: ARM: plat-versatile: remove stale clock header All the Versatile platforms (Integrator, Versatile, RealView Versatile Express) have been migrated to use the drivers/clk subsystem. Clean out this header that is not referenced anywhere anymore. Acked-by: Stephen Boyd Signed-off-by: Linus Walleij --- arch/arm/plat-versatile/include/plat/clock.h | 15 --------------- 1 file changed, 15 deletions(-) delete mode 100644 arch/arm/plat-versatile/include/plat/clock.h (limited to 'arch/arm') diff --git a/arch/arm/plat-versatile/include/plat/clock.h b/arch/arm/plat-versatile/include/plat/clock.h deleted file mode 100644 index 3cfb024ccd70..000000000000 --- a/arch/arm/plat-versatile/include/plat/clock.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef PLAT_CLOCK_H -#define PLAT_CLOCK_H - -#include - -struct clk_ops { - long (*round)(struct clk *, unsigned long); - int (*set)(struct clk *, unsigned long); - void (*setvco)(struct clk *, struct icst_vco); -}; - -int icst_clk_set(struct clk *, unsigned long); -long icst_clk_round(struct clk *, unsigned long); - -#endif -- cgit v1.2.3 From ba3fae06c7a4e80ab9d48a8a045b352da97cf23d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 1 Feb 2017 10:41:43 +0100 Subject: ARM/clk: move the ICST library to drivers/clk This moves the ICST clock divider helper library from arch/arm/common to drivers/clk/versatile so it is maintained with the other clock drivers. We keep the structure as a helper library intact and do not fuse it with the clk-icst.c Versatile ICST clock driver: there may be other users out there that need to use this library for their clocking, and then it will be helpful to keep the library contained. (The icst.[c|h] files could just be moved to drivers/clk/lib or a similar location to share the library.) Acked-by: Stephen Boyd Signed-off-by: Linus Walleij --- arch/arm/common/Kconfig | 3 - arch/arm/common/Makefile | 1 - arch/arm/common/icst.c | 105 ----------------------------------- arch/arm/include/asm/hardware/icst.h | 59 -------------------- 4 files changed, 168 deletions(-) delete mode 100644 arch/arm/common/icst.c delete mode 100644 arch/arm/include/asm/hardware/icst.h (limited to 'arch/arm') diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 9353184d730d..1181053e3ade 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -1,6 +1,3 @@ -config ICST - bool - config SA1111 bool select DMABOUNCE if !ARCH_PXA diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 27f23b15b1ea..29fdf6a3601d 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -4,7 +4,6 @@ obj-y += firmware.o -obj-$(CONFIG_ICST) += icst.o obj-$(CONFIG_SA1111) += sa1111.o obj-$(CONFIG_DMABOUNCE) += dmabounce.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o diff --git a/arch/arm/common/icst.c b/arch/arm/common/icst.c deleted file mode 100644 index d7ed252708c5..000000000000 --- a/arch/arm/common/icst.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * linux/arch/arm/common/icst307.c - * - * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Support functions for calculating clocks/divisors for the ICST307 - * clock generators. See http://www.idt.com/ for more information - * on these devices. - * - * This is an almost identical implementation to the ICST525 clock generator. - * The s2div and idx2s files are different - */ -#include -#include -#include -#include - -/* - * Divisors for each OD setting. - */ -const unsigned char icst307_s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 }; -const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 }; -EXPORT_SYMBOL(icst307_s2div); -EXPORT_SYMBOL(icst525_s2div); - -unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) -{ - u64 dividend = p->ref * 2 * (u64)(vco.v + 8); - u32 divisor = (vco.r + 2) * p->s2div[vco.s]; - - do_div(dividend, divisor); - return (unsigned long)dividend; -} - -EXPORT_SYMBOL(icst_hz); - -/* - * Ascending divisor S values. - */ -const unsigned char icst307_idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 }; -const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 }; -EXPORT_SYMBOL(icst307_idx2s); -EXPORT_SYMBOL(icst525_idx2s); - -struct icst_vco -icst_hz_to_vco(const struct icst_params *p, unsigned long freq) -{ - struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; - unsigned long f; - unsigned int i = 0, rd, best = (unsigned int)-1; - - /* - * First, find the PLL output divisor such - * that the PLL output is within spec. - */ - do { - f = freq * p->s2div[p->idx2s[i]]; - - if (f > p->vco_min && f <= p->vco_max) - break; - i++; - } while (i < 8); - - if (i >= 8) - return vco; - - vco.s = p->idx2s[i]; - - /* - * Now find the closest divisor combination - * which gives a PLL output of 'f'. - */ - for (rd = p->rd_min; rd <= p->rd_max; rd++) { - unsigned long fref_div, f_pll; - unsigned int vd; - int f_diff; - - fref_div = (2 * p->ref) / rd; - - vd = (f + fref_div / 2) / fref_div; - if (vd < p->vd_min || vd > p->vd_max) - continue; - - f_pll = fref_div * vd; - f_diff = f_pll - f; - if (f_diff < 0) - f_diff = -f_diff; - - if ((unsigned)f_diff < best) { - vco.v = vd - 8; - vco.r = rd - 2; - if (f_diff == 0) - break; - best = f_diff; - } - } - - return vco; -} - -EXPORT_SYMBOL(icst_hz_to_vco); diff --git a/arch/arm/include/asm/hardware/icst.h b/arch/arm/include/asm/hardware/icst.h deleted file mode 100644 index 794220b087d2..000000000000 --- a/arch/arm/include/asm/hardware/icst.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * arch/arm/include/asm/hardware/icst.h - * - * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Support functions for calculating clocks/divisors for the ICST - * clock generators. See http://www.idt.com/ for more information - * on these devices. - */ -#ifndef ASMARM_HARDWARE_ICST_H -#define ASMARM_HARDWARE_ICST_H - -struct icst_params { - unsigned long ref; - unsigned long vco_max; /* inclusive */ - unsigned long vco_min; /* exclusive */ - unsigned short vd_min; /* inclusive */ - unsigned short vd_max; /* inclusive */ - unsigned char rd_min; /* inclusive */ - unsigned char rd_max; /* inclusive */ - const unsigned char *s2div; /* chip specific s2div array */ - const unsigned char *idx2s; /* chip specific idx2s array */ -}; - -struct icst_vco { - unsigned short v; - unsigned char r; - unsigned char s; -}; - -unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco); -struct icst_vco icst_hz_to_vco(const struct icst_params *p, unsigned long freq); - -/* - * ICST307 VCO frequency must be between 6MHz and 200MHz (3.3 or 5V). - * This frequency is pre-output divider. - */ -#define ICST307_VCO_MIN 6000000 -#define ICST307_VCO_MAX 200000000 - -extern const unsigned char icst307_s2div[]; -extern const unsigned char icst307_idx2s[]; - -/* - * ICST525 VCO frequency must be between 10MHz and 200MHz (3V) or 320MHz (5V). - * This frequency is pre-output divider. - */ -#define ICST525_VCO_MIN 10000000 -#define ICST525_VCO_MAX_3V 200000000 -#define ICST525_VCO_MAX_5V 320000000 - -extern const unsigned char icst525_s2div[]; -extern const unsigned char icst525_idx2s[]; - -#endif -- cgit v1.2.3