From b2ab4f08e84d4031f82255447180c559bd076bbf Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Thu, 13 Sep 2012 16:47:58 -0500 Subject: MIPS: Add base architecture support for RI and XI. Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill Acked-by: David Daney --- arch/mips/include/asm/cpu-features.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/include/asm/cpu-features.h') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7c3f59..3af9aca65ab5 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -95,6 +95,9 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif +#ifndef cpu_has_rixi +#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +#endif #ifndef kernel_uses_smartmips_rixi #define kernel_uses_smartmips_rixi 0 #endif -- cgit v1.2.3