From 720e34ab3e57e19dba70c384e30494f047999c43 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 16 May 2022 09:05:51 +0200 Subject: clk: stm32mp13: add stm32 divider clock Just to introduce management of a stm32 divider clock Signed-off-by: Gabriel Fernandez Link: https://lore.kernel.org/r/20220516070600.7692-6-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd --- drivers/clk/stm32/clk-stm32mp13.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/clk/stm32/clk-stm32mp13.c') diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 55326d4d34dd..d93d92b5fe82 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -415,9 +415,16 @@ static struct clk_stm32_gate eth1ck_k = { .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0), }; +static struct clk_stm32_div eth1ptp_k = { + .div_id = DIV_ETH1PTP, + .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops, + CLK_SET_RATE_NO_REPARENT), +}; + static const struct clock_config stm32mp13_clock_cfg[] = { STM32_MUX_CFG(NO_ID, ck_ker_eth1), STM32_GATE_CFG(ETH1CK_K, eth1ck_k), + STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k), }; static u16 stm32mp13_cpt_gate[GATE_NB]; -- cgit v1.2.3