From 8fa7ff4fc01d7f43cd03143e4ec58323865bfacf Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:45 +0300 Subject: dmaengine: edma: Simplify and optimize the edma_execute path The code path in edma_execute() and edma_callback() can be simplified and make it more optimal. There is not need to call in to edma_execute() when the transfer has been finished for example. Also the handling of missed/first or next batch of paRAMs can be done in a more optimal way. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 76 +++++++++++++++++++++--------------------------------- 1 file changed, 29 insertions(+), 47 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 3e5d4f193005..19fa49d6f555 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -154,15 +154,11 @@ static void edma_execute(struct edma_chan *echan) struct device *dev = echan->vchan.chan.device->dev; int i, j, left, nslots; - /* If either we processed all psets or we're still not started */ - if (!echan->edesc || - echan->edesc->pset_nr == echan->edesc->processed) { - /* Get next vdesc */ + if (!echan->edesc) { + /* Setup is needed for the first transfer */ vdesc = vchan_next_desc(&echan->vchan); - if (!vdesc) { - echan->edesc = NULL; + if (!vdesc) return; - } list_del(&vdesc->node); echan->edesc = to_edma_desc(&vdesc->tx); } @@ -220,28 +216,26 @@ static void edma_execute(struct edma_chan *echan) echan->ecc->dummy_slot); } - if (edesc->processed <= MAX_NR_SG) { - dev_dbg(dev, "first transfer starting on channel %d\n", - echan->ch_num); - edma_start(echan->ch_num); - } else { - dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", - echan->ch_num, edesc->processed); - edma_resume(echan->ch_num); - } - - /* - * This happens due to setup times between intermediate transfers - * in long SG lists which have to be broken up into transfers of - * MAX_NR_SG - */ if (echan->missed) { + /* + * This happens due to setup times between intermediate + * transfers in long SG lists which have to be broken up into + * transfers of MAX_NR_SG + */ dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); edma_clean_channel(echan->ch_num); edma_stop(echan->ch_num); edma_start(echan->ch_num); edma_trigger_channel(echan->ch_num); echan->missed = 0; + } else if (edesc->processed <= MAX_NR_SG) { + dev_dbg(dev, "first transfer starting on channel %d\n", + echan->ch_num); + edma_start(echan->ch_num); + } else { + dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", + echan->ch_num, edesc->processed); + edma_resume(echan->ch_num); } } @@ -259,20 +253,17 @@ static int edma_terminate_all(struct dma_chan *chan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { - int cyclic = echan->edesc->cyclic; - + edma_stop(echan->ch_num); + /* Move the cyclic channel back to default queue */ + if (echan->edesc->cyclic) + edma_assign_channel_eventq(echan->ch_num, + EVENTQ_DEFAULT); /* * free the running request descriptor * since it is not in any of the vdesc lists */ edma_desc_free(&echan->edesc->vdesc); - echan->edesc = NULL; - edma_stop(echan->ch_num); - /* Move the cyclic channel back to default queue */ - if (cyclic) - edma_assign_channel_eventq(echan->ch_num, - EVENTQ_DEFAULT); } vchan_get_all_descriptors(&echan->vchan, &head); @@ -725,41 +716,33 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) edesc = echan->edesc; - /* Pause the channel for non-cyclic */ - if (!edesc || (edesc && !edesc->cyclic)) - edma_pause(echan->ch_num); - + spin_lock(&echan->vchan.lock); switch (ch_status) { case EDMA_DMA_COMPLETE: - spin_lock(&echan->vchan.lock); - if (edesc) { if (edesc->cyclic) { vchan_cyclic_callback(&edesc->vdesc); + goto out; } else if (edesc->processed == edesc->pset_nr) { dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); edesc->residue = 0; edma_stop(echan->ch_num); vchan_cookie_complete(&edesc->vdesc); - edma_execute(echan); + echan->edesc = NULL; } else { dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); + edma_pause(echan->ch_num); + /* Update statistics for tx_status */ edesc->residue -= edesc->sg_len; edesc->residue_stat = edesc->residue; edesc->processed_stat = edesc->processed; - - edma_execute(echan); } + edma_execute(echan); } - - spin_unlock(&echan->vchan.lock); - break; case EDMA_DMA_CC_ERROR: - spin_lock(&echan->vchan.lock); - edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); /* @@ -788,13 +771,12 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) edma_start(echan->ch_num); edma_trigger_channel(echan->ch_num); } - - spin_unlock(&echan->vchan.lock); - break; default: break; } +out: + spin_unlock(&echan->vchan.lock); } /* Alloc channel resources */ -- cgit v1.2.3 From dc9b60552f6a6a56b1defb88aa9f7f1498fcc045 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:47 +0300 Subject: ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driver If the of_dma_controller is registered in the non dmaengine driver we could have race condition: the of_dma_controller has been registered, but the dmaengine driver is not yet probed. Drivers requesting DMA channels during this window will fail since we do not yet have dmaengine drivers registered. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 19fa49d6f555..fcb4680efed7 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -25,6 +25,7 @@ #include #include #include +#include #include @@ -987,9 +988,14 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, INIT_LIST_HEAD(&dma->channels); } +static struct of_dma_filter_info edma_filter_info = { + .filter_fn = edma_filter_fn, +}; + static int edma_probe(struct platform_device *pdev) { struct edma_cc *ecc; + struct device_node *parent_node = pdev->dev.parent->of_node; int ret; ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); @@ -1024,6 +1030,13 @@ static int edma_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ecc); + if (parent_node) { + dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); + dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap); + of_dma_controller_register(parent_node, of_dma_simple_xlate, + &edma_filter_info); + } + dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); return 0; @@ -1037,7 +1050,10 @@ static int edma_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct edma_cc *ecc = dev_get_drvdata(dev); + struct device_node *parent_node = pdev->dev.parent->of_node; + if (parent_node) + of_dma_controller_free(parent_node); dma_async_device_unregister(&ecc->dma_slave); edma_free_slot(ecc->dummy_slot); -- cgit v1.2.3 From ca304fa9bb762f091e851d48de43f623c975d47a Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:49 +0300 Subject: ARM/dmaengine: edma: Public API to use private struct pointer Instead of relying on indexes pointing to edma private date in the global pointer array, pass the private data pointer via the public API. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 79 +++++++++++++++++++++++++++++------------------------- 1 file changed, 43 insertions(+), 36 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index fcb4680efed7..53d48b2a700d 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -119,6 +119,7 @@ struct edma_chan { }; struct edma_cc { + struct edma *cc; int ctlr; struct dma_device dma_slave; struct edma_chan slave_chans[EDMA_CHANS]; @@ -150,6 +151,7 @@ static void edma_desc_free(struct virt_dma_desc *vdesc) /* Dispatch a queued descriptor to the controller (caller holds lock) */ static void edma_execute(struct edma_chan *echan) { + struct edma *cc = echan->ecc->cc; struct virt_dma_desc *vdesc; struct edma_desc *edesc; struct device *dev = echan->vchan.chan.device->dev; @@ -174,7 +176,7 @@ static void edma_execute(struct edma_chan *echan) /* Write descriptor PaRAM set(s) */ for (i = 0; i < nslots; i++) { j = i + edesc->processed; - edma_write_slot(echan->slot[i], &edesc->pset[j].param); + edma_write_slot(cc, echan->slot[i], &edesc->pset[j].param); edesc->sg_len += edesc->pset[j].len; dev_vdbg(echan->vchan.chan.device->dev, "\n pset[%d]:\n" @@ -199,7 +201,7 @@ static void edma_execute(struct edma_chan *echan) edesc->pset[j].param.link_bcntrld); /* Link to the previous slot if not the last set */ if (i != (nslots - 1)) - edma_link(echan->slot[i], echan->slot[i+1]); + edma_link(cc, echan->slot[i], echan->slot[i+1]); } edesc->processed += nslots; @@ -211,9 +213,9 @@ static void edma_execute(struct edma_chan *echan) */ if (edesc->processed == edesc->pset_nr) { if (edesc->cyclic) - edma_link(echan->slot[nslots-1], echan->slot[1]); + edma_link(cc, echan->slot[nslots-1], echan->slot[1]); else - edma_link(echan->slot[nslots-1], + edma_link(cc, echan->slot[nslots-1], echan->ecc->dummy_slot); } @@ -224,19 +226,19 @@ static void edma_execute(struct edma_chan *echan) * transfers of MAX_NR_SG */ dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); - edma_clean_channel(echan->ch_num); - edma_stop(echan->ch_num); - edma_start(echan->ch_num); - edma_trigger_channel(echan->ch_num); + edma_clean_channel(cc, echan->ch_num); + edma_stop(cc, echan->ch_num); + edma_start(cc, echan->ch_num); + edma_trigger_channel(cc, echan->ch_num); echan->missed = 0; } else if (edesc->processed <= MAX_NR_SG) { dev_dbg(dev, "first transfer starting on channel %d\n", echan->ch_num); - edma_start(echan->ch_num); + edma_start(cc, echan->ch_num); } else { dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", echan->ch_num, edesc->processed); - edma_resume(echan->ch_num); + edma_resume(cc, echan->ch_num); } } @@ -254,10 +256,11 @@ static int edma_terminate_all(struct dma_chan *chan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { - edma_stop(echan->ch_num); + edma_stop(echan->ecc->cc, echan->ch_num); /* Move the cyclic channel back to default queue */ if (echan->edesc->cyclic) - edma_assign_channel_eventq(echan->ch_num, + edma_assign_channel_eventq(echan->ecc->cc, + echan->ch_num, EVENTQ_DEFAULT); /* * free the running request descriptor @@ -295,7 +298,7 @@ static int edma_dma_pause(struct dma_chan *chan) if (!echan->edesc) return -EINVAL; - edma_pause(echan->ch_num); + edma_pause(echan->ecc->cc, echan->ch_num); return 0; } @@ -303,7 +306,7 @@ static int edma_dma_resume(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - edma_resume(echan->ch_num); + edma_resume(echan->ecc->cc, echan->ch_num); return 0; } @@ -485,8 +488,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg( for (i = 0; i < nslots; i++) { if (echan->slot[i] < 0) { echan->slot[i] = - edma_alloc_slot(EDMA_CTLR(echan->ch_num), - EDMA_SLOT_ANY); + edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY); if (echan->slot[i] < 0) { kfree(edesc); dev_err(dev, "%s: Failed to allocate slot\n", @@ -641,8 +643,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( /* Allocate a PaRAM slot, if needed */ if (echan->slot[i] < 0) { echan->slot[i] = - edma_alloc_slot(EDMA_CTLR(echan->ch_num), - EDMA_SLOT_ANY); + edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY); if (echan->slot[i] < 0) { kfree(edesc); dev_err(dev, "%s: Failed to allocate slot\n", @@ -703,7 +704,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( } /* Place the cyclic channel to highest priority queue */ - edma_assign_channel_eventq(echan->ch_num, EVENTQ_0); + edma_assign_channel_eventq(echan->ecc->cc, echan->ch_num, EVENTQ_0); return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } @@ -711,6 +712,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( static void edma_callback(unsigned ch_num, u16 ch_status, void *data) { struct edma_chan *echan = data; + struct edma *cc = echan->ecc->cc; struct device *dev = echan->vchan.chan.device->dev; struct edma_desc *edesc; struct edmacc_param p; @@ -727,13 +729,13 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) } else if (edesc->processed == edesc->pset_nr) { dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); edesc->residue = 0; - edma_stop(echan->ch_num); + edma_stop(cc, echan->ch_num); vchan_cookie_complete(&edesc->vdesc); echan->edesc = NULL; } else { dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); - edma_pause(echan->ch_num); + edma_pause(cc, echan->ch_num); /* Update statistics for tx_status */ edesc->residue -= edesc->sg_len; @@ -744,7 +746,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) } break; case EDMA_DMA_CC_ERROR: - edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); + edma_read_slot(cc, echan->slot[0], &p); /* * Issue later based on missed flag which will be sure @@ -767,10 +769,10 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) * missed, so its safe to issue it here. */ dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); - edma_clean_channel(echan->ch_num); - edma_stop(echan->ch_num); - edma_start(echan->ch_num); - edma_trigger_channel(echan->ch_num); + edma_clean_channel(cc, echan->ch_num); + edma_stop(cc, echan->ch_num); + edma_start(cc, echan->ch_num); + edma_trigger_channel(cc, echan->ch_num); } break; default: @@ -789,8 +791,8 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) int a_ch_num; LIST_HEAD(descs); - a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback, - echan, EVENTQ_DEFAULT); + a_ch_num = edma_alloc_channel(echan->ecc->cc, echan->ch_num, + edma_callback, echan, EVENTQ_DEFAULT); if (a_ch_num < 0) { ret = -ENODEV; @@ -814,7 +816,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) return 0; err_wrong_chan: - edma_free_channel(a_ch_num); + edma_free_channel(echan->ecc->cc, a_ch_num); err_no_chan: return ret; } @@ -827,21 +829,21 @@ static void edma_free_chan_resources(struct dma_chan *chan) int i; /* Terminate transfers */ - edma_stop(echan->ch_num); + edma_stop(echan->ecc->cc, echan->ch_num); vchan_free_chan_resources(&echan->vchan); /* Free EDMA PaRAM slots */ for (i = 1; i < EDMA_MAX_SLOTS; i++) { if (echan->slot[i] >= 0) { - edma_free_slot(echan->slot[i]); + edma_free_slot(echan->ecc->cc, echan->slot[i]); echan->slot[i] = -1; } } /* Free EDMA channel */ if (echan->alloced) { - edma_free_channel(echan->ch_num); + edma_free_channel(echan->ecc->cc, echan->ch_num); echan->alloced = false; } @@ -871,7 +873,8 @@ static u32 edma_residue(struct edma_desc *edesc) * We always read the dst/src position from the first RamPar * pset. That's the one which is active now. */ - pos = edma_get_position(edesc->echan->slot[0], dst); + pos = edma_get_position(edesc->echan->ecc->cc, edesc->echan->slot[0], + dst); /* * Cyclic is simple. Just subtract pset[0].addr from pos. @@ -1008,8 +1011,12 @@ static int edma_probe(struct platform_device *pdev) return -ENOMEM; } + ecc->cc = edma_get_data(pdev->dev.parent); + if (!ecc->cc) + return -ENODEV; + ecc->ctlr = pdev->id; - ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY); + ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY); if (ecc->dummy_slot < 0) { dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); return ecc->dummy_slot; @@ -1042,7 +1049,7 @@ static int edma_probe(struct platform_device *pdev) return 0; err_reg1: - edma_free_slot(ecc->dummy_slot); + edma_free_slot(ecc->cc, ecc->dummy_slot); return ret; } @@ -1055,7 +1062,7 @@ static int edma_remove(struct platform_device *pdev) if (parent_node) of_dma_controller_free(parent_node); dma_async_device_unregister(&ecc->dma_slave); - edma_free_slot(ecc->dummy_slot); + edma_free_slot(ecc->cc, ecc->dummy_slot); return 0; } -- cgit v1.2.3 From b2c843a196b8f5aca74ebabd16c60d59480d6721 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:50 +0300 Subject: ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers Since the driver stack no longer depends on lookup with id number in a global array of pointers, the limitation for the number of eDMAs are no longer needed. We can handle as many eDMAs in legacy and DT boot as we have memory for them to allocate the needed structures. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 53d48b2a700d..fc91ab9dd1bb 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -991,14 +991,12 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, INIT_LIST_HEAD(&dma->channels); } -static struct of_dma_filter_info edma_filter_info = { - .filter_fn = edma_filter_fn, -}; - static int edma_probe(struct platform_device *pdev) { struct edma_cc *ecc; struct device_node *parent_node = pdev->dev.parent->of_node; + struct platform_device *parent_pdev = + to_platform_device(pdev->dev.parent); int ret; ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); @@ -1015,7 +1013,10 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->cc) return -ENODEV; - ecc->ctlr = pdev->id; + ecc->ctlr = parent_pdev->id; + if (ecc->ctlr < 0) + ecc->ctlr = 0; + ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY); if (ecc->dummy_slot < 0) { dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); @@ -1038,10 +1039,8 @@ static int edma_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ecc); if (parent_node) { - dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); - dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap); - of_dma_controller_register(parent_node, of_dma_simple_xlate, - &edma_filter_info); + of_dma_controller_register(parent_node, of_dma_xlate_by_chan_id, + &ecc->dma_slave); } dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); -- cgit v1.2.3 From 2b6b3b7420190888793c49e97276e1e73bd7eaed Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:53 +0300 Subject: ARM/dmaengine: edma: Merge the two drivers under drivers/dma/ Move the code out from arch/arm/common and merge it inside of the dmaengine driver. This change is done with as minimal (if eny) functional change to the code as possible to avoid introducing regression. Signed-off-by: Peter Ujfalusi Acked-by: Tony Lindgren Signed-off-by: Vinod Koul --- drivers/dma/Kconfig | 1 - drivers/dma/edma.c | 1506 ++++++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 1431 insertions(+), 76 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index b4584757dae0..992efc8e465e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -486,7 +486,6 @@ config TI_EDMA depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE select DMA_ENGINE select DMA_VIRTUAL_CHANNELS - select TI_PRIV_EDMA default n help Enable support for the TI EDMA controller. This DMA diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index fc91ab9dd1bb..aeb67e0cc523 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -26,12 +26,92 @@ #include #include #include +#include +#include +#include +#include #include #include "dmaengine.h" #include "virt-dma.h" +/* Offsets matching "struct edmacc_param" */ +#define PARM_OPT 0x00 +#define PARM_SRC 0x04 +#define PARM_A_B_CNT 0x08 +#define PARM_DST 0x0c +#define PARM_SRC_DST_BIDX 0x10 +#define PARM_LINK_BCNTRLD 0x14 +#define PARM_SRC_DST_CIDX 0x18 +#define PARM_CCNT 0x1c + +#define PARM_SIZE 0x20 + +/* Offsets for EDMA CC global channel registers and their shadows */ +#define SH_ER 0x00 /* 64 bits */ +#define SH_ECR 0x08 /* 64 bits */ +#define SH_ESR 0x10 /* 64 bits */ +#define SH_CER 0x18 /* 64 bits */ +#define SH_EER 0x20 /* 64 bits */ +#define SH_EECR 0x28 /* 64 bits */ +#define SH_EESR 0x30 /* 64 bits */ +#define SH_SER 0x38 /* 64 bits */ +#define SH_SECR 0x40 /* 64 bits */ +#define SH_IER 0x50 /* 64 bits */ +#define SH_IECR 0x58 /* 64 bits */ +#define SH_IESR 0x60 /* 64 bits */ +#define SH_IPR 0x68 /* 64 bits */ +#define SH_ICR 0x70 /* 64 bits */ +#define SH_IEVAL 0x78 +#define SH_QER 0x80 +#define SH_QEER 0x84 +#define SH_QEECR 0x88 +#define SH_QEESR 0x8c +#define SH_QSER 0x90 +#define SH_QSECR 0x94 +#define SH_SIZE 0x200 + +/* Offsets for EDMA CC global registers */ +#define EDMA_REV 0x0000 +#define EDMA_CCCFG 0x0004 +#define EDMA_QCHMAP 0x0200 /* 8 registers */ +#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ +#define EDMA_QDMAQNUM 0x0260 +#define EDMA_QUETCMAP 0x0280 +#define EDMA_QUEPRI 0x0284 +#define EDMA_EMR 0x0300 /* 64 bits */ +#define EDMA_EMCR 0x0308 /* 64 bits */ +#define EDMA_QEMR 0x0310 +#define EDMA_QEMCR 0x0314 +#define EDMA_CCERR 0x0318 +#define EDMA_CCERRCLR 0x031c +#define EDMA_EEVAL 0x0320 +#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ +#define EDMA_QRAE 0x0380 /* 4 registers */ +#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ +#define EDMA_QSTAT 0x0600 /* 2 registers */ +#define EDMA_QWMTHRA 0x0620 +#define EDMA_QWMTHRB 0x0624 +#define EDMA_CCSTAT 0x0640 + +#define EDMA_M 0x1000 /* global channel registers */ +#define EDMA_ECR 0x1008 +#define EDMA_ECRH 0x100C +#define EDMA_SHADOW0 0x2000 /* 4 shadow regions */ +#define EDMA_PARM 0x4000 /* PaRAM entries */ + +#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) + +#define EDMA_DCHMAP 0x0100 /* 64 registers */ + +/* CCCFG register */ +#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ +#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ +#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ +#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ +#define CHMAP_EXIST BIT(24) + /* * This will go away when the private EDMA API is folded * into this driver and the platform device(s) are @@ -60,6 +140,47 @@ #define EDMA_MAX_SLOTS MAX_NR_SG #define EDMA_DESCRIPTORS 16 +#define EDMA_MAX_PARAMENTRY 512 + +#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ +#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ +#define EDMA_CONT_PARAMS_ANY 1001 +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 +#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 + +#define EDMA_MAX_CC 2 + +/* PaRAM slots are laid out like this */ +struct edmacc_param { + u32 opt; + u32 src; + u32 a_b_cnt; + u32 dst; + u32 src_dst_bidx; + u32 link_bcntrld; + u32 src_dst_cidx; + u32 ccnt; +} __packed; + +/* fields in edmacc_param.opt */ +#define SAM BIT(0) +#define DAM BIT(1) +#define SYNCDIM BIT(2) +#define STATIC BIT(3) +#define EDMA_FWID (0x07 << 8) +#define TCCMODE BIT(11) +#define EDMA_TCC(t) ((t) << 12) +#define TCINTEN BIT(20) +#define ITCINTEN BIT(21) +#define TCCHEN BIT(22) +#define ITCCHEN BIT(23) + +/*ch_status parameter of callback function possible values*/ +#define EDMA_DMA_COMPLETE 1 +#define EDMA_DMA_CC_ERROR 2 +#define EDMA_DMA_TC1_ERROR 3 +#define EDMA_DMA_TC2_ERROR 4 + struct edma_pset { u32 len; dma_addr_t addr; @@ -119,14 +240,929 @@ struct edma_chan { }; struct edma_cc { - struct edma *cc; - int ctlr; + struct device *dev; + struct edma_soc_info *info; + void __iomem *base; + int id; + + /* eDMA3 resource information */ + unsigned num_channels; + unsigned num_region; + unsigned num_slots; + unsigned num_tc; + enum dma_event_q default_queue; + + bool unused_chan_list_done; + /* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ + DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + + /* The edma_unused bit for each channel is clear unless + * it is not being used on this platform. It uses a bit + * of SOC-specific initialization code. + */ + DECLARE_BITMAP(edma_unused, EDMA_CHANS); + + struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; + } intr_data[EDMA_CHANS]; + struct dma_device dma_slave; struct edma_chan slave_chans[EDMA_CHANS]; - int num_slave_chans; int dummy_slot; }; +/* dummy param set used to (re)initialize parameter RAM slots */ +static const struct edmacc_param dummy_paramset = { + .link_bcntrld = 0xffff, + .ccnt = 1, +}; + +static const struct of_device_id edma_of_ids[] = { + { .compatible = "ti,edma3", }, + {} +}; + +static inline unsigned int edma_read(struct edma_cc *ecc, int offset) +{ + return (unsigned int)__raw_readl(ecc->base + offset); +} + +static inline void edma_write(struct edma_cc *ecc, int offset, int val) +{ + __raw_writel(val, ecc->base + offset); +} + +static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, + unsigned or) +{ + unsigned val = edma_read(ecc, offset); + + val &= and; + val |= or; + edma_write(ecc, offset, val); +} + +static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) +{ + unsigned val = edma_read(ecc, offset); + + val &= and; + edma_write(ecc, offset, val); +} + +static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) +{ + unsigned val = edma_read(ecc, offset); + + val |= or; + edma_write(ecc, offset, val); +} + +static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, + int i) +{ + return edma_read(ecc, offset + (i << 2)); +} + +static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, + unsigned val) +{ + edma_write(ecc, offset + (i << 2), val); +} + +static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, + unsigned and, unsigned or) +{ + edma_modify(ecc, offset + (i << 2), and, or); +} + +static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, + unsigned or) +{ + edma_or(ecc, offset + (i << 2), or); +} + +static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, + unsigned or) +{ + edma_or(ecc, offset + ((i * 2 + j) << 2), or); +} + +static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, + int j, unsigned val) +{ + edma_write(ecc, offset + ((i * 2 + j) << 2), val); +} + +static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset) +{ + return edma_read(ecc, EDMA_SHADOW0 + offset); +} + +static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, + int offset, int i) +{ + return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); +} + +static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, + unsigned val) +{ + edma_write(ecc, EDMA_SHADOW0 + offset, val); +} + +static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, + int i, unsigned val) +{ + edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); +} + +static inline unsigned int edma_parm_read(struct edma_cc *ecc, int offset, + int param_no) +{ + return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); +} + +static inline void edma_parm_write(struct edma_cc *ecc, int offset, + int param_no, unsigned val) +{ + edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); +} + +static inline void edma_parm_modify(struct edma_cc *ecc, int offset, + int param_no, unsigned and, unsigned or) +{ + edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); +} + +static inline void edma_parm_and(struct edma_cc *ecc, int offset, int param_no, + unsigned and) +{ + edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); +} + +static inline void edma_parm_or(struct edma_cc *ecc, int offset, int param_no, + unsigned or) +{ + edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); +} + +static inline void set_bits(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + set_bit(offset + (len - 1), p); +} + +static inline void clear_bits(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + clear_bit(offset + (len - 1), p); +} + +static void edma_map_dmach_to_queue(struct edma_cc *ecc, unsigned ch_no, + enum dma_event_q queue_no) +{ + int bit = (ch_no & 0x7) * 4; + + /* default to low priority queue */ + if (queue_no == EVENTQ_DEFAULT) + queue_no = ecc->default_queue; + + queue_no &= 7; + edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit), + queue_no << bit); +} + +static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, + int priority) +{ + int bit = queue_no * 4; + + edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); +} + +static void edma_direct_dmach_to_param_mapping(struct edma_cc *ecc) +{ + int i; + + for (i = 0; i < ecc->num_channels; i++) + edma_write_array(ecc, EDMA_DCHMAP, i, (i << 5)); +} + +static int prepare_unused_channel_list(struct device *dev, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct edma_cc *ecc = data; + int i, count; + struct of_phandle_args dma_spec; + + if (dev->of_node) { + struct platform_device *dma_pdev; + + count = of_property_count_strings(dev->of_node, "dma-names"); + if (count < 0) + return 0; + for (i = 0; i < count; i++) { + if (of_parse_phandle_with_args(dev->of_node, "dmas", + "#dma-cells", i, + &dma_spec)) + continue; + + if (!of_match_node(edma_of_ids, dma_spec.np)) { + of_node_put(dma_spec.np); + continue; + } + + dma_pdev = of_find_device_by_node(dma_spec.np); + if (&dma_pdev->dev != ecc->dev) + continue; + + clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), + ecc->edma_unused); + of_node_put(dma_spec.np); + } + return 0; + } + + /* For non-OF case */ + for (i = 0; i < pdev->num_resources; i++) { + struct resource *res = &pdev->resource[i]; + + if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) { + clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), + ecc->edma_unused); + } + } + + return 0; +} + +static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data) +{ + lch = EDMA_CHAN_SLOT(lch); + + if (!callback) + edma_shadow0_write_array(ecc, SH_IECR, lch >> 5, + BIT(lch & 0x1f)); + + ecc->intr_data[lch].callback = callback; + ecc->intr_data[lch].data = data; + + if (callback) { + edma_shadow0_write_array(ecc, SH_ICR, lch >> 5, + BIT(lch & 0x1f)); + edma_shadow0_write_array(ecc, SH_IESR, lch >> 5, + BIT(lch & 0x1f)); + } +} + +/* + * paRAM management functions + */ + +/** + * edma_write_slot - write parameter RAM data for slot + * @ecc: pointer to edma_cc struct + * @slot: number of parameter RAM slot being modified + * @param: data to be written into parameter RAM slot + * + * Use this to assign all parameters of a transfer at once. This + * allows more efficient setup of transfers than issuing multiple + * calls to set up those parameters in small pieces, and provides + * complete control over all transfer options. + */ +static void edma_write_slot(struct edma_cc *ecc, unsigned slot, + const struct edmacc_param *param) +{ + slot = EDMA_CHAN_SLOT(slot); + if (slot >= ecc->num_slots) + return; + memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); +} + +/** + * edma_read_slot - read parameter RAM data from slot + * @ecc: pointer to edma_cc struct + * @slot: number of parameter RAM slot being copied + * @param: where to store copy of parameter RAM data + * + * Use this to read data from a parameter RAM slot, perhaps to + * save them as a template for later reuse. + */ +static void edma_read_slot(struct edma_cc *ecc, unsigned slot, + struct edmacc_param *param) +{ + slot = EDMA_CHAN_SLOT(slot); + if (slot >= ecc->num_slots) + return; + memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); +} + +/** + * edma_alloc_slot - allocate DMA parameter RAM + * @ecc: pointer to edma_cc struct + * @slot: specific slot to allocate; negative for "any unused slot" + * + * This allocates a parameter RAM slot, initializing it to hold a + * dummy transfer. Slots allocated using this routine have not been + * mapped to a hardware DMA channel, and will normally be used by + * linking to them from a slot associated with a DMA channel. + * + * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific + * slots may be allocated on behalf of DSP firmware. + * + * Returns the number of the slot, else negative errno. + */ +static int edma_alloc_slot(struct edma_cc *ecc, int slot) +{ + if (slot > 0) + slot = EDMA_CHAN_SLOT(slot); + if (slot < 0) { + slot = ecc->num_channels; + for (;;) { + slot = find_next_zero_bit(ecc->edma_inuse, + ecc->num_slots, + slot); + if (slot == ecc->num_slots) + return -ENOMEM; + if (!test_and_set_bit(slot, ecc->edma_inuse)) + break; + } + } else if (slot < ecc->num_channels || slot >= ecc->num_slots) { + return -EINVAL; + } else if (test_and_set_bit(slot, ecc->edma_inuse)) { + return -EBUSY; + } + + edma_write_slot(ecc, slot, &dummy_paramset); + + return EDMA_CTLR_CHAN(ecc->id, slot); +} + +/** + * edma_free_slot - deallocate DMA parameter RAM + * @ecc: pointer to edma_cc struct + * @slot: parameter RAM slot returned from edma_alloc_slot() + * + * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). + * Callers are responsible for ensuring the slot is inactive, and will + * not be activated. + */ +static void edma_free_slot(struct edma_cc *ecc, unsigned slot) +{ + slot = EDMA_CHAN_SLOT(slot); + if (slot < ecc->num_channels || slot >= ecc->num_slots) + return; + + edma_write_slot(ecc, slot, &dummy_paramset); + clear_bit(slot, ecc->edma_inuse); +} + +/** + * edma_link - link one parameter RAM slot to another + * @ecc: pointer to edma_cc struct + * @from: parameter RAM slot originating the link + * @to: parameter RAM slot which is the link target + * + * The originating slot should not be part of any active DMA transfer. + */ +static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) +{ + from = EDMA_CHAN_SLOT(from); + to = EDMA_CHAN_SLOT(to); + if (from >= ecc->num_slots || to >= ecc->num_slots) + return; + + edma_parm_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); +} + +/** + * edma_get_position - returns the current transfer point + * @ecc: pointer to edma_cc struct + * @slot: parameter RAM slot being examined + * @dst: true selects the dest position, false the source + * + * Returns the position of the current active slot + */ +static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, + bool dst) +{ + u32 offs; + + slot = EDMA_CHAN_SLOT(slot); + offs = PARM_OFFSET(slot); + offs += dst ? PARM_DST : PARM_SRC; + + return edma_read(ecc, offs); +} + +/*-----------------------------------------------------------------------*/ +/** + * edma_start - start dma on a channel + * @ecc: pointer to edma_cc struct + * @channel: channel being activated + * + * Channels with event associations will be triggered by their hardware + * events, and channels without such associations will be triggered by + * software. (At this writing there is no interface for using software + * triggers except with channels that don't support hardware triggers.) + * + * Returns zero on success, else negative errno. + */ +static int edma_start(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return -EINVAL; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); + + /* EDMA channels without event association */ + if (test_bit(channel, ecc->edma_unused)) { + pr_debug("EDMA: ESR%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ESR, j)); + edma_shadow0_write_array(ecc, SH_ESR, j, mask); + return 0; + } + + /* EDMA channel with event association */ + pr_debug("EDMA: ER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ER, j)); + /* Clear any pending event or error */ + edma_write_array(ecc, EDMA_ECR, j, mask); + edma_write_array(ecc, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_shadow0_write_array(ecc, SH_EESR, j, mask); + pr_debug("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); + return 0; + } + + return -EINVAL; +} + +/** + * edma_stop - stops dma on the channel passed + * @ecc: pointer to edma_cc struct + * @channel: channel being deactivated + * + * When @lch is a channel, any active transfer is paused and + * all pending hardware events are cleared. The current transfer + * may not be resumed, and the channel's Parameter RAM should be + * reinitialized before being reused. + */ +static void edma_stop(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); + + edma_shadow0_write_array(ecc, SH_EECR, j, mask); + edma_shadow0_write_array(ecc, SH_ECR, j, mask); + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_write_array(ecc, EDMA_EMCR, j, mask); + + /* clear possibly pending completion interrupt */ + edma_shadow0_write_array(ecc, SH_ICR, j, mask); + + pr_debug("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); + + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ + } +} + +/** + * edma_pause - pause dma on a channel + * @ecc: pointer to edma_cc struct + * @channel: on which edma_start() has been called + * + * This temporarily disables EDMA hardware events on the specified channel, + * preventing them from triggering new transfers on its behalf + */ +static void edma_pause(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + unsigned int mask = BIT(channel & 0x1f); + + edma_shadow0_write_array(ecc, SH_EECR, channel >> 5, mask); + } +} + +/** + * edma_resume - resumes dma on a paused channel + * @ecc: pointer to edma_cc struct + * @channel: on which edma_pause() has been called + * + * This re-enables EDMA hardware events on the specified channel. + */ +static void edma_resume(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + unsigned int mask = BIT(channel & 0x1f); + + edma_shadow0_write_array(ecc, SH_EESR, channel >> 5, mask); + } +} + +static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) +{ + unsigned int mask; + + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return -EINVAL; + } + channel = EDMA_CHAN_SLOT(channel); + mask = BIT(channel & 0x1f); + + edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); + + pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), + edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); + return 0; +} + +/****************************************************************************** + * + * It cleans ParamEntry qand bring back EDMA to initial state if media has + * been removed before EDMA has finished.It is usedful for removable media. + * Arguments: + * ch_no - channel no + * + * Return: zero on success, or corresponding error no on failure + * + * FIXME this should not be needed ... edma_stop() should suffice. + * + *****************************************************************************/ + +static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); + + pr_debug("EDMA: EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); + edma_shadow0_write_array(ecc, SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); + } +} + +/** + * edma_alloc_channel - allocate DMA channel and paired parameter RAM + * @ecc: pointer to edma_cc struct + * @channel: specific channel to allocate; negative for "any unmapped channel" + * @callback: optional; to be issued on DMA completion or errors + * @data: passed to callback + * @eventq_no: an EVENTQ_* constant, used to choose which Transfer + * Controller (TC) executes requests using this channel. Use + * EVENTQ_DEFAULT unless you really need a high priority queue. + * + * This allocates a DMA channel and its associated parameter RAM slot. + * The parameter RAM is initialized to hold a dummy transfer. + * + * Normal use is to pass a specific channel number as @channel, to make + * use of hardware events mapped to that channel. When the channel will + * be used only for software triggering or event chaining, channels not + * mapped to hardware events (or mapped to unused events) are preferable. + * + * DMA transfers start from a channel using edma_start(), or by + * chaining. When the transfer described in that channel's parameter RAM + * slot completes, that slot's data may be reloaded through a link. + * + * DMA errors are only reported to the @callback associated with the + * channel driving that transfer, but transfer completion callbacks can + * be sent to another channel under control of the TCC field in + * the option word of the transfer's parameter RAM set. Drivers must not + * use DMA transfer completion callbacks for channels they did not allocate. + * (The same applies to TCC codes used in transfer chaining.) + * + * Returns the number of the channel, else negative errno. + */ +static int edma_alloc_channel(struct edma_cc *ecc, int channel, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data, + enum dma_event_q eventq_no) +{ + unsigned done = 0; + int ret = 0; + + if (!ecc->unused_chan_list_done) { + /* + * Scan all the platform devices to find out the EDMA channels + * used and clear them in the unused list, making the rest + * available for ARM usage. + */ + ret = bus_for_each_dev(&platform_bus_type, NULL, ecc, + prepare_unused_channel_list); + if (ret < 0) + return ret; + + ecc->unused_chan_list_done = true; + } + + if (channel >= 0) { + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", + __func__, ecc->id, EDMA_CTLR(channel)); + return -EINVAL; + } + channel = EDMA_CHAN_SLOT(channel); + } + + if (channel < 0) { + channel = 0; + for (;;) { + channel = find_next_bit(ecc->edma_unused, + ecc->num_channels, channel); + if (channel == ecc->num_channels) + break; + if (!test_and_set_bit(channel, ecc->edma_inuse)) { + done = 1; + break; + } + channel++; + } + if (!done) + return -ENOMEM; + } else if (channel >= ecc->num_channels) { + return -EINVAL; + } else if (test_and_set_bit(channel, ecc->edma_inuse)) { + return -EBUSY; + } + + /* ensure access through shadow region 0 */ + edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); + + /* ensure no events are pending */ + edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel)); + edma_write_slot(ecc, channel, &dummy_paramset); + + if (callback) + edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), + callback, data); + + edma_map_dmach_to_queue(ecc, channel, eventq_no); + + return EDMA_CTLR_CHAN(ecc->id, channel); +} + +/** + * edma_free_channel - deallocate DMA channel + * @ecc: pointer to edma_cc struct + * @channel: dma channel returned from edma_alloc_channel() + * + * This deallocates the DMA channel and associated parameter RAM slot + * allocated by edma_alloc_channel(). + * + * Callers are responsible for ensuring the channel is inactive, and + * will not be reactivated by linking, chaining, or software calls to + * edma_start(). + */ +static void edma_free_channel(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel >= ecc->num_channels) + return; + + edma_setup_interrupt(ecc, channel, NULL, NULL); + /* REVISIT should probably take out of shadow region 0 */ + + memcpy_toio(ecc->base + PARM_OFFSET(channel), &dummy_paramset, + PARM_SIZE); + clear_bit(channel, ecc->edma_inuse); +} + +/* + * edma_assign_channel_eventq - move given channel to desired eventq + * Arguments: + * channel - channel number + * eventq_no - queue to move the channel + * + * Can be used to move a channel to a selected event queue. + */ +static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, + enum dma_event_q eventq_no) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel >= ecc->num_channels) + return; + + /* default to low priority queue */ + if (eventq_no == EVENTQ_DEFAULT) + eventq_no = ecc->default_queue; + if (eventq_no >= ecc->num_tc) + return; + + edma_map_dmach_to_queue(ecc, channel, eventq_no); +} + +static irqreturn_t dma_irq_handler(int irq, void *data) +{ + struct edma_cc *ecc = data; + int ctlr; + u32 sh_ier; + u32 sh_ipr; + u32 bank; + + ctlr = ecc->id; + if (ctlr < 0) + return IRQ_NONE; + + dev_dbg(ecc->dev, "dma_irq_handler\n"); + + sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); + if (!sh_ipr) { + sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); + if (!sh_ipr) + return IRQ_NONE; + sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); + bank = 1; + } else { + sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); + bank = 0; + } + + do { + u32 slot; + u32 channel; + + dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr); + + slot = __ffs(sh_ipr); + sh_ipr &= ~(BIT(slot)); + + if (sh_ier & BIT(slot)) { + channel = (bank << 5) | slot; + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); + if (ecc->intr_data[channel].callback) + ecc->intr_data[channel].callback( + EDMA_CTLR_CHAN(ctlr, channel), + EDMA_DMA_COMPLETE, + ecc->intr_data[channel].data); + } + } while (sh_ipr); + + edma_shadow0_write(ecc, SH_IEVAL, 1); + return IRQ_HANDLED; +} + +/****************************************************************************** + * + * DMA error interrupt handler + * + *****************************************************************************/ +static irqreturn_t dma_ccerr_handler(int irq, void *data) +{ + struct edma_cc *ecc = data; + int i; + int ctlr; + unsigned int cnt = 0; + + ctlr = ecc->id; + if (ctlr < 0) + return IRQ_NONE; + + dev_dbg(ecc->dev, "dma_ccerr_handler\n"); + + if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && + (edma_read_array(ecc, EDMA_EMR, 1) == 0) && + (edma_read(ecc, EDMA_QEMR) == 0) && + (edma_read(ecc, EDMA_CCERR) == 0)) + return IRQ_NONE; + + while (1) { + int j = -1; + + if (edma_read_array(ecc, EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(ecc, EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + dev_dbg(ecc->dev, "EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + + if (edma_read_array(ecc, EDMA_EMR, j) & + BIT(i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, + BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, + j, BIT(i)); + if (ecc->intr_data[k].callback) { + ecc->intr_data[k].callback( + EDMA_CTLR_CHAN(ctlr, k), + EDMA_DMA_CC_ERROR, + ecc->intr_data[k].data); + } + } + } + } else if (edma_read(ecc, EDMA_QEMR)) { + dev_dbg(ecc->dev, "QEMR %02x\n", + edma_read(ecc, EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ecc, EDMA_QEMCR, BIT(i)); + edma_shadow0_write(ecc, SH_QSECR, + BIT(i)); + + /* NOTE: not reported!! */ + } + } + } else if (edma_read(ecc, EDMA_CCERR)) { + dev_dbg(ecc->dev, "CCERR %08x\n", + edma_read(ecc, EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... + */ + for (i = 0; i < 8; i++) { + if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ecc, EDMA_CCERRCLR, BIT(i)); + + /* NOTE: not reported!! */ + } + } + } + if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && + (edma_read_array(ecc, EDMA_EMR, 1) == 0) && + (edma_read(ecc, EDMA_QEMR) == 0) && + (edma_read(ecc, EDMA_CCERR) == 0)) + break; + cnt++; + if (cnt > 10) + break; + } + edma_write(ecc, EDMA_EEVAL, 1); + return IRQ_HANDLED; +} + static inline struct edma_cc *to_edma_cc(struct dma_device *d) { return container_of(d, struct edma_cc, dma_slave); @@ -137,8 +1173,7 @@ static inline struct edma_chan *to_edma_chan(struct dma_chan *c) return container_of(c, struct edma_chan, vchan.chan); } -static inline struct edma_desc -*to_edma_desc(struct dma_async_tx_descriptor *tx) +static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx) { return container_of(tx, struct edma_desc, vdesc.tx); } @@ -151,7 +1186,7 @@ static void edma_desc_free(struct virt_dma_desc *vdesc) /* Dispatch a queued descriptor to the controller (caller holds lock) */ static void edma_execute(struct edma_chan *echan) { - struct edma *cc = echan->ecc->cc; + struct edma_cc *ecc = echan->ecc; struct virt_dma_desc *vdesc; struct edma_desc *edesc; struct device *dev = echan->vchan.chan.device->dev; @@ -176,7 +1211,7 @@ static void edma_execute(struct edma_chan *echan) /* Write descriptor PaRAM set(s) */ for (i = 0; i < nslots; i++) { j = i + edesc->processed; - edma_write_slot(cc, echan->slot[i], &edesc->pset[j].param); + edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); edesc->sg_len += edesc->pset[j].len; dev_vdbg(echan->vchan.chan.device->dev, "\n pset[%d]:\n" @@ -201,7 +1236,7 @@ static void edma_execute(struct edma_chan *echan) edesc->pset[j].param.link_bcntrld); /* Link to the previous slot if not the last set */ if (i != (nslots - 1)) - edma_link(cc, echan->slot[i], echan->slot[i+1]); + edma_link(ecc, echan->slot[i], echan->slot[i + 1]); } edesc->processed += nslots; @@ -213,9 +1248,9 @@ static void edma_execute(struct edma_chan *echan) */ if (edesc->processed == edesc->pset_nr) { if (edesc->cyclic) - edma_link(cc, echan->slot[nslots-1], echan->slot[1]); + edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); else - edma_link(cc, echan->slot[nslots-1], + edma_link(ecc, echan->slot[nslots - 1], echan->ecc->dummy_slot); } @@ -226,19 +1261,19 @@ static void edma_execute(struct edma_chan *echan) * transfers of MAX_NR_SG */ dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); - edma_clean_channel(cc, echan->ch_num); - edma_stop(cc, echan->ch_num); - edma_start(cc, echan->ch_num); - edma_trigger_channel(cc, echan->ch_num); + edma_clean_channel(ecc, echan->ch_num); + edma_stop(ecc, echan->ch_num); + edma_start(ecc, echan->ch_num); + edma_trigger_channel(ecc, echan->ch_num); echan->missed = 0; } else if (edesc->processed <= MAX_NR_SG) { dev_dbg(dev, "first transfer starting on channel %d\n", echan->ch_num); - edma_start(cc, echan->ch_num); + edma_start(ecc, echan->ch_num); } else { dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", echan->ch_num, edesc->processed); - edma_resume(cc, echan->ch_num); + edma_resume(ecc, echan->ch_num); } } @@ -256,11 +1291,10 @@ static int edma_terminate_all(struct dma_chan *chan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { - edma_stop(echan->ecc->cc, echan->ch_num); + edma_stop(echan->ecc, echan->ch_num); /* Move the cyclic channel back to default queue */ if (echan->edesc->cyclic) - edma_assign_channel_eventq(echan->ecc->cc, - echan->ch_num, + edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_DEFAULT); /* * free the running request descriptor @@ -298,7 +1332,7 @@ static int edma_dma_pause(struct dma_chan *chan) if (!echan->edesc) return -EINVAL; - edma_pause(echan->ecc->cc, echan->ch_num); + edma_pause(echan->ecc, echan->ch_num); return 0; } @@ -306,7 +1340,7 @@ static int edma_dma_resume(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - edma_resume(echan->ecc->cc, echan->ch_num); + edma_resume(echan->ecc, echan->ch_num); return 0; } @@ -322,9 +1356,10 @@ static int edma_dma_resume(struct dma_chan *chan) * @direction: Direction of the transfer */ static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, - dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, - enum dma_slave_buswidth dev_width, unsigned int dma_length, - enum dma_transfer_direction direction) + dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, + enum dma_slave_buswidth dev_width, + unsigned int dma_length, + enum dma_transfer_direction direction) { struct edma_chan *echan = to_edma_chan(chan); struct device *dev = chan->device->dev; @@ -470,8 +1505,8 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg( return NULL; } - edesc = kzalloc(sizeof(*edesc) + sg_len * - sizeof(edesc->pset[0]), GFP_ATOMIC); + edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]), + GFP_ATOMIC); if (!edesc) { dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); return NULL; @@ -488,7 +1523,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg( for (i = 0; i < nslots; i++) { if (echan->slot[i] < 0) { echan->slot[i] = - edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY); + edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); if (echan->slot[i] < 0) { kfree(edesc); dev_err(dev, "%s: Failed to allocate slot\n", @@ -623,8 +1658,8 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( if (nslots > MAX_NR_SG) return NULL; - edesc = kzalloc(sizeof(*edesc) + nslots * - sizeof(edesc->pset[0]), GFP_ATOMIC); + edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), + GFP_ATOMIC); if (!edesc) { dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); return NULL; @@ -643,7 +1678,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( /* Allocate a PaRAM slot, if needed */ if (echan->slot[i] < 0) { echan->slot[i] = - edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY); + edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); if (echan->slot[i] < 0) { kfree(edesc); dev_err(dev, "%s: Failed to allocate slot\n", @@ -704,7 +1739,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( } /* Place the cyclic channel to highest priority queue */ - edma_assign_channel_eventq(echan->ecc->cc, echan->ch_num, EVENTQ_0); + edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_0); return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } @@ -712,7 +1747,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( static void edma_callback(unsigned ch_num, u16 ch_status, void *data) { struct edma_chan *echan = data; - struct edma *cc = echan->ecc->cc; + struct edma_cc *ecc = echan->ecc; struct device *dev = echan->vchan.chan.device->dev; struct edma_desc *edesc; struct edmacc_param p; @@ -727,15 +1762,19 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) vchan_cyclic_callback(&edesc->vdesc); goto out; } else if (edesc->processed == edesc->pset_nr) { - dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); + dev_dbg(dev, + "Transfer completed on channel %d\n", + ch_num); edesc->residue = 0; - edma_stop(cc, echan->ch_num); + edma_stop(ecc, echan->ch_num); vchan_cookie_complete(&edesc->vdesc); echan->edesc = NULL; } else { - dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); + dev_dbg(dev, + "Sub transfer completed on channel %d\n", + ch_num); - edma_pause(cc, echan->ch_num); + edma_pause(ecc, echan->ch_num); /* Update statistics for tx_status */ edesc->residue -= edesc->sg_len; @@ -746,7 +1785,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) } break; case EDMA_DMA_CC_ERROR: - edma_read_slot(cc, echan->slot[0], &p); + edma_read_slot(ecc, echan->slot[0], &p); /* * Issue later based on missed flag which will be sure @@ -761,18 +1800,18 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) * slot. So we avoid doing so and set the missed flag. */ if (p.a_b_cnt == 0 && p.ccnt == 0) { - dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n"); + dev_dbg(dev, "Error on null slot, setting miss\n"); echan->missed = 1; } else { /* * The slot is already programmed but the event got * missed, so its safe to issue it here. */ - dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); - edma_clean_channel(cc, echan->ch_num); - edma_stop(cc, echan->ch_num); - edma_start(cc, echan->ch_num); - edma_trigger_channel(cc, echan->ch_num); + dev_dbg(dev, "Missed event, TRIGGERING\n"); + edma_clean_channel(ecc, echan->ch_num); + edma_stop(ecc, echan->ch_num); + edma_start(ecc, echan->ch_num); + edma_trigger_channel(ecc, echan->ch_num); } break; default: @@ -791,7 +1830,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) int a_ch_num; LIST_HEAD(descs); - a_ch_num = edma_alloc_channel(echan->ecc->cc, echan->ch_num, + a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, edma_callback, echan, EVENTQ_DEFAULT); if (a_ch_num < 0) { @@ -816,7 +1855,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) return 0; err_wrong_chan: - edma_free_channel(echan->ecc->cc, a_ch_num); + edma_free_channel(echan->ecc, a_ch_num); err_no_chan: return ret; } @@ -829,21 +1868,21 @@ static void edma_free_chan_resources(struct dma_chan *chan) int i; /* Terminate transfers */ - edma_stop(echan->ecc->cc, echan->ch_num); + edma_stop(echan->ecc, echan->ch_num); vchan_free_chan_resources(&echan->vchan); /* Free EDMA PaRAM slots */ for (i = 1; i < EDMA_MAX_SLOTS; i++) { if (echan->slot[i] >= 0) { - edma_free_slot(echan->ecc->cc, echan->slot[i]); + edma_free_slot(echan->ecc, echan->slot[i]); echan->slot[i] = -1; } } /* Free EDMA channel */ if (echan->alloced) { - edma_free_channel(echan->ecc->cc, echan->ch_num); + edma_free_channel(echan->ecc, echan->ch_num); echan->alloced = false; } @@ -873,8 +1912,7 @@ static u32 edma_residue(struct edma_desc *edesc) * We always read the dst/src position from the first RamPar * pset. That's the one which is active now. */ - pos = edma_get_position(edesc->echan->ecc->cc, edesc->echan->slot[0], - dst); + pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst); /* * Cyclic is simple. Just subtract pset[0].addr from pos. @@ -935,15 +1973,14 @@ static enum dma_status edma_tx_status(struct dma_chan *chan, return ret; } -static void __init edma_chan_init(struct edma_cc *ecc, - struct dma_device *dma, +static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma, struct edma_chan *echans) { int i, j; for (i = 0; i < EDMA_CHANS; i++) { struct edma_chan *echan = &echans[i]; - echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); + echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); echan->ecc = ecc; echan->vchan.desc_free = edma_desc_free; @@ -991,14 +2028,189 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, INIT_LIST_HEAD(&dma->channels); } +static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, + struct edma_cc *ecc) +{ + int i; + u32 value, cccfg; + s8 (*queue_priority_map)[2]; + + /* Decode the eDMA3 configuration from CCCFG register */ + cccfg = edma_read(ecc, EDMA_CCCFG); + + value = GET_NUM_REGN(cccfg); + ecc->num_region = BIT(value); + + value = GET_NUM_DMACH(cccfg); + ecc->num_channels = BIT(value + 1); + + value = GET_NUM_PAENTRY(cccfg); + ecc->num_slots = BIT(value + 4); + + value = GET_NUM_EVQUE(cccfg); + ecc->num_tc = value + 1; + + dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); + dev_dbg(dev, "num_region: %u\n", ecc->num_region); + dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); + dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); + dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); + + /* Nothing need to be done if queue priority is provided */ + if (pdata->queue_priority_mapping) + return 0; + + /* + * Configure TC/queue priority as follows: + * Q0 - priority 0 + * Q1 - priority 1 + * Q2 - priority 2 + * ... + * The meaning of priority numbers: 0 highest priority, 7 lowest + * priority. So Q0 is the highest priority queue and the last queue has + * the lowest priority. + */ + queue_priority_map = devm_kzalloc(dev, (ecc->num_tc + 1) * sizeof(s8), + GFP_KERNEL); + if (!queue_priority_map) + return -ENOMEM; + + for (i = 0; i < ecc->num_tc; i++) { + queue_priority_map[i][0] = i; + queue_priority_map[i][1] = i; + } + queue_priority_map[i][0] = -1; + queue_priority_map[i][1] = -1; + + pdata->queue_priority_mapping = queue_priority_map; + /* Default queue has the lowest priority */ + pdata->default_queue = i - 1; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, + size_t sz) +{ + const char pname[] = "ti,edma-xbar-event-map"; + struct resource res; + void __iomem *xbar; + s16 (*xbar_chans)[2]; + size_t nelm = sz / sizeof(s16); + u32 shift, offset, mux; + int ret, i; + + xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL); + if (!xbar_chans) + return -ENOMEM; + + ret = of_address_to_resource(dev->of_node, 1, &res); + if (ret) + return -ENOMEM; + + xbar = devm_ioremap(dev, res.start, resource_size(&res)); + if (!xbar) + return -ENOMEM; + + ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans, + nelm); + if (ret) + return -EIO; + + /* Invalidate last entry for the other user of this mess */ + nelm >>= 1; + xbar_chans[nelm][0] = -1; + xbar_chans[nelm][1] = -1; + + for (i = 0; i < nelm; i++) { + shift = (xbar_chans[i][1] & 0x03) << 3; + offset = xbar_chans[i][1] & 0xfffffffc; + mux = readl(xbar + offset); + mux &= ~(0xff << shift); + mux |= xbar_chans[i][0] << shift; + writel(mux, (xbar + offset)); + } + + pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; + return 0; +} + +static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata) +{ + int ret = 0; + struct property *prop; + size_t sz; + struct edma_rsv_info *rsv_info; + + rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); + if (!rsv_info) + return -ENOMEM; + pdata->rsv = rsv_info; + + prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); + if (prop) + ret = edma_xbar_event_map(dev, pdata, sz); + + return ret; +} + +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) +{ + struct edma_soc_info *info; + int ret; + + info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); + if (!info) + return ERR_PTR(-ENOMEM); + + ret = edma_of_parse_dt(dev, info); + if (ret) + return ERR_PTR(ret); + + return info; +} +#else +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) +{ + return ERR_PTR(-EINVAL); +} +#endif + static int edma_probe(struct platform_device *pdev) { - struct edma_cc *ecc; - struct device_node *parent_node = pdev->dev.parent->of_node; - struct platform_device *parent_pdev = - to_platform_device(pdev->dev.parent); + struct edma_soc_info *info = pdev->dev.platform_data; + s8 (*queue_priority_mapping)[2]; + int i, off, ln; + const s16 (*rsv_chans)[2]; + const s16 (*rsv_slots)[2]; + const s16 (*xbar_chans)[2]; + int irq; + char *irq_name; + struct resource *mem; + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct edma_cc *ecc; int ret; + if (node) { + info = edma_setup_info_from_dt(dev); + if (IS_ERR(info)) { + dev_err(dev, "failed to get DT data\n"); + return PTR_ERR(info); + } + } + + if (!info) + return -ENODEV; + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync() failed\n"); + return ret; + } + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); if (ret) return ret; @@ -1009,15 +2221,123 @@ static int edma_probe(struct platform_device *pdev) return -ENOMEM; } - ecc->cc = edma_get_data(pdev->dev.parent); - if (!ecc->cc) - return -ENODEV; + ecc->dev = dev; + ecc->id = pdev->id; + /* When booting with DT the pdev->id is -1 */ + if (ecc->id < 0) + ecc->id = 0; + + mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc"); + if (!mem) { + dev_dbg(dev, "mem resource not found, using index 0\n"); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(dev, "no mem resource?\n"); + return -ENODEV; + } + } + ecc->base = devm_ioremap_resource(dev, mem); + if (IS_ERR(ecc->base)) + return PTR_ERR(ecc->base); + + platform_set_drvdata(pdev, ecc); + + /* Get eDMA3 configuration from IP */ + ret = edma_setup_from_hw(dev, info, ecc); + if (ret) + return ret; + + ecc->default_queue = info->default_queue; + + for (i = 0; i < ecc->num_slots; i++) + edma_write_slot(ecc, i, &dummy_paramset); + + /* Mark all channels as unused */ + memset(ecc->edma_unused, 0xff, sizeof(ecc->edma_unused)); + + if (info->rsv) { + /* Clear the reserved channels in unused list */ + rsv_chans = info->rsv->rsv_chans; + if (rsv_chans) { + for (i = 0; rsv_chans[i][0] != -1; i++) { + off = rsv_chans[i][0]; + ln = rsv_chans[i][1]; + clear_bits(off, ln, ecc->edma_unused); + } + } + + /* Set the reserved slots in inuse list */ + rsv_slots = info->rsv->rsv_slots; + if (rsv_slots) { + for (i = 0; rsv_slots[i][0] != -1; i++) { + off = rsv_slots[i][0]; + ln = rsv_slots[i][1]; + set_bits(off, ln, ecc->edma_inuse); + } + } + } + + /* Clear the xbar mapped channels in unused list */ + xbar_chans = info->xbar_chans; + if (xbar_chans) { + for (i = 0; xbar_chans[i][1] != -1; i++) { + off = xbar_chans[i][1]; + clear_bits(off, 1, ecc->edma_unused); + } + } + + irq = platform_get_irq_byname(pdev, "edma3_ccint"); + if (irq < 0 && node) + irq = irq_of_parse_and_map(node, 0); + + if (irq >= 0) { + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", + dev_name(dev)); + ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, + ecc); + if (ret) { + dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); + return ret; + } + } + + irq = platform_get_irq_byname(pdev, "edma3_ccerrint"); + if (irq < 0 && node) + irq = irq_of_parse_and_map(node, 2); + + if (irq >= 0) { + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", + dev_name(dev)); + ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, + ecc); + if (ret) { + dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); + return ret; + } + } + + for (i = 0; i < ecc->num_channels; i++) + edma_map_dmach_to_queue(ecc, i, info->default_queue); + + queue_priority_mapping = info->queue_priority_mapping; + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); - ecc->ctlr = parent_pdev->id; - if (ecc->ctlr < 0) - ecc->ctlr = 0; + /* Map the channel to param entry if channel mapping logic exist */ + if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + edma_direct_dmach_to_param_mapping(ecc); - ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY); + for (i = 0; i < ecc->num_region; i++) { + edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); + edma_write_array(ecc, EDMA_QRAE, i, 0x0); + } + ecc->info = info; + + ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); if (ecc->dummy_slot < 0) { dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); return ecc->dummy_slot; @@ -1036,19 +2356,16 @@ static int edma_probe(struct platform_device *pdev) if (ret) goto err_reg1; - platform_set_drvdata(pdev, ecc); - - if (parent_node) { - of_dma_controller_register(parent_node, of_dma_xlate_by_chan_id, + if (node) + of_dma_controller_register(node, of_dma_xlate_by_chan_id, &ecc->dma_slave); - } dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); return 0; err_reg1: - edma_free_slot(ecc->cc, ecc->dummy_slot); + edma_free_slot(ecc, ecc->dummy_slot); return ret; } @@ -1056,21 +2373,60 @@ static int edma_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct edma_cc *ecc = dev_get_drvdata(dev); - struct device_node *parent_node = pdev->dev.parent->of_node; - if (parent_node) - of_dma_controller_free(parent_node); + if (pdev->dev.of_node) + of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&ecc->dma_slave); - edma_free_slot(ecc->cc, ecc->dummy_slot); + edma_free_slot(ecc, ecc->dummy_slot); return 0; } +#ifdef CONFIG_PM_SLEEP +static int edma_pm_resume(struct device *dev) +{ + struct edma_cc *ecc = dev_get_drvdata(dev); + int i; + s8 (*queue_priority_mapping)[2]; + + queue_priority_mapping = ecc->info->queue_priority_mapping; + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + /* Map the channel to param entry if channel mapping logic */ + if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + edma_direct_dmach_to_param_mapping(ecc); + + for (i = 0; i < ecc->num_channels; i++) { + if (test_bit(i, ecc->edma_inuse)) { + /* ensure access through shadow region 0 */ + edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, + BIT(i & 0x1f)); + + edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i), + ecc->intr_data[i].callback, + ecc->intr_data[i].data); + } + } + + return 0; +} +#endif + +static const struct dev_pm_ops edma_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume) +}; + static struct platform_driver edma_driver = { .probe = edma_probe, .remove = edma_remove, .driver = { - .name = "edma-dma-engine", + .name = "edma", + .pm = &edma_pm_ops, + .of_match_table = edma_of_ids, }, }; -- cgit v1.2.3 From cb78205955d4a2c26c18984896b81cc63b416f63 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:54 +0300 Subject: dmaengine: edma: Allocate memory dynamically for bitmaps and structures Instead of using defines to specify the size of different arrays and bitmaps, allocate the memory for them based on the information we get from the HW itself. Since these defines are set based on the worst case, there are devices where they are not valid. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 62 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 28 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index aeb67e0cc523..d5a76c67f83f 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -112,23 +112,6 @@ #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ #define CHMAP_EXIST BIT(24) -/* - * This will go away when the private EDMA API is folded - * into this driver and the platform device(s) are - * instantiated in the arch code. We can only get away - * with this simplification because DA8XX may not be built - * in the same kernel image with other DaVinci parts. This - * avoids having to sprinkle dmaengine driver platform devices - * and data throughout all the existing board files. - */ -#ifdef CONFIG_ARCH_DAVINCI_DA8XX -#define EDMA_CTLRS 2 -#define EDMA_CHANS 32 -#else -#define EDMA_CTLRS 1 -#define EDMA_CHANS 64 -#endif /* CONFIG_ARCH_DAVINCI_DA8XX */ - /* * Max of 20 segments per channel to conserve PaRAM slots * Also note that MAX_NR_SG should be atleast the no.of periods @@ -140,16 +123,12 @@ #define EDMA_MAX_SLOTS MAX_NR_SG #define EDMA_DESCRIPTORS 16 -#define EDMA_MAX_PARAMENTRY 512 - #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ #define EDMA_CONT_PARAMS_ANY 1001 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 -#define EDMA_MAX_CC 2 - /* PaRAM slots are laid out like this */ struct edmacc_param { u32 opt; @@ -256,22 +235,22 @@ struct edma_cc { /* The edma_inuse bit for each PaRAM slot is clear unless the * channel is in use ... by ARM or DSP, for QDMA, or whatever. */ - DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + unsigned long *edma_inuse; /* The edma_unused bit for each channel is clear unless * it is not being used on this platform. It uses a bit * of SOC-specific initialization code. */ - DECLARE_BITMAP(edma_unused, EDMA_CHANS); + unsigned long *edma_unused; struct dma_interrupt_data { void (*callback)(unsigned channel, unsigned short ch_status, void *data); void *data; - } intr_data[EDMA_CHANS]; + } *intr_data; struct dma_device dma_slave; - struct edma_chan slave_chans[EDMA_CHANS]; + struct edma_chan *slave_chans; int dummy_slot; }; @@ -457,6 +436,8 @@ static int prepare_unused_channel_list(struct device *dev, void *data) { struct platform_device *pdev = to_platform_device(dev); struct edma_cc *ecc = data; + int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0); + int dma_req_max = dma_req_min + ecc->num_channels; int i, count; struct of_phandle_args dma_spec; @@ -491,11 +472,15 @@ static int prepare_unused_channel_list(struct device *dev, void *data) /* For non-OF case */ for (i = 0; i < pdev->num_resources; i++) { struct resource *res = &pdev->resource[i]; + int dma_req; + + if (!(res->flags & IORESOURCE_DMA)) + continue; - if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) { + dma_req = (int)res->start; + if (dma_req >= dma_req_min && dma_req < dma_req_max) clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), ecc->edma_unused); - } } return 0; @@ -1978,7 +1963,7 @@ static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma, { int i, j; - for (i = 0; i < EDMA_CHANS; i++) { + for (i = 0; i < ecc->num_channels; i++) { struct edma_chan *echan = &echans[i]; echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); echan->ecc = ecc; @@ -2247,6 +2232,27 @@ static int edma_probe(struct platform_device *pdev) if (ret) return ret; + /* Allocate memory based on the information we got from the IP */ + ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, + sizeof(*ecc->slave_chans), GFP_KERNEL); + if (!ecc->slave_chans) + return -ENOMEM; + + ecc->intr_data = devm_kcalloc(dev, ecc->num_channels, + sizeof(*ecc->intr_data), GFP_KERNEL); + if (!ecc->intr_data) + return -ENOMEM; + + ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->edma_unused) + return -ENOMEM; + + ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->edma_inuse) + return -ENOMEM; + ecc->default_queue = info->default_queue; for (i = 0; i < ecc->num_slots; i++) -- cgit v1.2.3 From 547c6e27113b7d0d03db6df0d60f91b8eb232793 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:55 +0300 Subject: dmaengine: edma: Use devm_kcalloc when possible When allocating a memory for number of items it is better (looks better) to use devm_kcalloc. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d5a76c67f83f..95c10373168d 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -2055,7 +2055,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, * priority. So Q0 is the highest priority queue and the last queue has * the lowest priority. */ - queue_priority_map = devm_kzalloc(dev, (ecc->num_tc + 1) * sizeof(s8), + queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), GFP_KERNEL); if (!queue_priority_map) return -ENOMEM; @@ -2086,7 +2086,7 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, u32 shift, offset, mux; int ret, i; - xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL); + xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL); if (!xbar_chans) return -ENOMEM; -- cgit v1.2.3 From 907f74a0b46890da59c4f2caf7e17a89695e8132 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:56 +0300 Subject: dmaengine: edma: Cleanup regarding the use of dev around the code Be consistent and do not mix the use of dev, &pdev->dev, etc in the functions. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 61 +++++++++++++++++++++++++++--------------------------- 1 file changed, 30 insertions(+), 31 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 95c10373168d..a9fe5c92451d 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1198,27 +1198,27 @@ static void edma_execute(struct edma_chan *echan) j = i + edesc->processed; edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); edesc->sg_len += edesc->pset[j].len; - dev_vdbg(echan->vchan.chan.device->dev, - "\n pset[%d]:\n" - " chnum\t%d\n" - " slot\t%d\n" - " opt\t%08x\n" - " src\t%08x\n" - " dst\t%08x\n" - " abcnt\t%08x\n" - " ccnt\t%08x\n" - " bidx\t%08x\n" - " cidx\t%08x\n" - " lkrld\t%08x\n", - j, echan->ch_num, echan->slot[i], - edesc->pset[j].param.opt, - edesc->pset[j].param.src, - edesc->pset[j].param.dst, - edesc->pset[j].param.a_b_cnt, - edesc->pset[j].param.ccnt, - edesc->pset[j].param.src_dst_bidx, - edesc->pset[j].param.src_dst_cidx, - edesc->pset[j].param.link_bcntrld); + dev_vdbg(dev, + "\n pset[%d]:\n" + " chnum\t%d\n" + " slot\t%d\n" + " opt\t%08x\n" + " src\t%08x\n" + " dst\t%08x\n" + " abcnt\t%08x\n" + " ccnt\t%08x\n" + " bidx\t%08x\n" + " cidx\t%08x\n" + " lkrld\t%08x\n", + j, echan->ch_num, echan->slot[i], + edesc->pset[j].param.opt, + edesc->pset[j].param.src, + edesc->pset[j].param.dst, + edesc->pset[j].param.a_b_cnt, + edesc->pset[j].param.ccnt, + edesc->pset[j].param.src_dst_bidx, + edesc->pset[j].param.src_dst_cidx, + edesc->pset[j].param.link_bcntrld); /* Link to the previous slot if not the last set */ if (i != (nslots - 1)) edma_link(ecc, echan->slot[i], echan->slot[i + 1]); @@ -1849,7 +1849,6 @@ err_no_chan: static void edma_free_chan_resources(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - struct device *dev = chan->device->dev; int i; /* Terminate transfers */ @@ -1871,7 +1870,7 @@ static void edma_free_chan_resources(struct dma_chan *chan) echan->alloced = false; } - dev_dbg(dev, "freeing channel for %u\n", echan->ch_num); + dev_dbg(chan->device->dev, "freeing channel for %u\n", echan->ch_num); } /* Send pending descriptor to hardware */ @@ -2196,13 +2195,13 @@ static int edma_probe(struct platform_device *pdev) return ret; } - ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) return ret; - ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL); + ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); if (!ecc) { - dev_err(&pdev->dev, "Can't allocate controller\n"); + dev_err(dev, "Can't allocate controller\n"); return -ENOMEM; } @@ -2345,7 +2344,7 @@ static int edma_probe(struct platform_device *pdev) ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); if (ecc->dummy_slot < 0) { - dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); + dev_err(dev, "Can't allocate PaRAM dummy slot\n"); return ecc->dummy_slot; } @@ -2354,7 +2353,7 @@ static int edma_probe(struct platform_device *pdev) dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask); - edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); + edma_dma_init(ecc, &ecc->dma_slave, dev); edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); @@ -2366,7 +2365,7 @@ static int edma_probe(struct platform_device *pdev) of_dma_controller_register(node, of_dma_xlate_by_chan_id, &ecc->dma_slave); - dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); + dev_info(dev, "TI EDMA DMA engine driver\n"); return 0; @@ -2380,8 +2379,8 @@ static int edma_remove(struct platform_device *pdev) struct device *dev = &pdev->dev; struct edma_cc *ecc = dev_get_drvdata(dev); - if (pdev->dev.of_node) - of_dma_controller_free(pdev->dev.of_node); + if (dev->of_node) + of_dma_controller_free(dev->of_node); dma_async_device_unregister(&ecc->dma_slave); edma_free_slot(ecc, ecc->dummy_slot); -- cgit v1.2.3 From 3287fb4d23fc906edcd5fa8c1632f30946e9c779 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:57 +0300 Subject: dmaengine: edma: Use dev_dbg instead pr_debug We have access to dev, so it is better to use the dev_dbg for debug prints. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index a9fe5c92451d..08f9bd0aa0b3 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -676,23 +676,23 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) /* EDMA channels without event association */ if (test_bit(channel, ecc->edma_unused)) { - pr_debug("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ESR, j)); + dev_dbg(ecc->dev, "ESR%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ESR, j)); edma_shadow0_write_array(ecc, SH_ESR, j, mask); return 0; } /* EDMA channel with event association */ - pr_debug("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ER, j)); + dev_dbg(ecc->dev, "ER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ER, j)); /* Clear any pending event or error */ edma_write_array(ecc, EDMA_ECR, j, mask); edma_write_array(ecc, EDMA_EMCR, j, mask); /* Clear any SER */ edma_shadow0_write_array(ecc, SH_SECR, j, mask); edma_shadow0_write_array(ecc, SH_EESR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); return 0; } @@ -730,8 +730,8 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel) /* clear possibly pending completion interrupt */ edma_shadow0_write_array(ecc, SH_ICR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); /* REVISIT: consider guarding against inappropriate event * chaining by overwriting with dummy_paramset. @@ -800,8 +800,8 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); - pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), - edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); + dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), + edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); return 0; } @@ -831,8 +831,8 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) int j = (channel >> 5); unsigned int mask = BIT(channel & 0x1f); - pr_debug("EDMA: EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); + dev_dbg(ecc->dev, "EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); edma_shadow0_write_array(ecc, SH_ECR, j, mask); /* Clear the corresponding EMR bits */ edma_write_array(ecc, EDMA_EMCR, j, mask); -- cgit v1.2.3 From 96f5ff0e108a497372d86a286e6c264b39c09370 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:58 +0300 Subject: dmaengine: edma: Use the edma_write_slot instead open coded memcpy_toio edma_write_slot() is for writing an entire paRAM slot. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 08f9bd0aa0b3..f6653da0ee16 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -968,8 +968,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) edma_setup_interrupt(ecc, channel, NULL, NULL); /* REVISIT should probably take out of shadow region 0 */ - memcpy_toio(ecc->base + PARM_OFFSET(channel), &dummy_paramset, - PARM_SIZE); + edma_write_slot(ecc, channel, &dummy_paramset); clear_bit(channel, ecc->edma_inuse); } -- cgit v1.2.3 From fc014095da23575297288bb3ab215db7c50af381 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:59 +0300 Subject: dmaengine: edma: Print warning when linking slots from different eDMA Warning message in case of linking between paRAM slots in different eDMA controllers. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index f6653da0ee16..d33ae0b43925 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -619,6 +619,9 @@ static void edma_free_slot(struct edma_cc *ecc, unsigned slot) */ static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) { + if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to))) + dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); + from = EDMA_CHAN_SLOT(from); to = EDMA_CHAN_SLOT(to); if (from >= ecc->num_slots || to >= ecc->num_slots) -- cgit v1.2.3 From 11c157337a3fb0a8bed5272b3a43f2bf482032ee Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:00 +0300 Subject: dmaengine: edma: Consolidate the comments for functions Remove or rewrite the comments for the internal functions. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 86 +++++++----------------------------------------------- 1 file changed, 11 insertions(+), 75 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d33ae0b43925..6bcbdceb3dc2 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -508,19 +508,7 @@ static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, } /* - * paRAM management functions - */ - -/** - * edma_write_slot - write parameter RAM data for slot - * @ecc: pointer to edma_cc struct - * @slot: number of parameter RAM slot being modified - * @param: data to be written into parameter RAM slot - * - * Use this to assign all parameters of a transfer at once. This - * allows more efficient setup of transfers than issuing multiple - * calls to set up those parameters in small pieces, and provides - * complete control over all transfer options. + * paRAM slot management functions */ static void edma_write_slot(struct edma_cc *ecc, unsigned slot, const struct edmacc_param *param) @@ -531,15 +519,6 @@ static void edma_write_slot(struct edma_cc *ecc, unsigned slot, memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); } -/** - * edma_read_slot - read parameter RAM data from slot - * @ecc: pointer to edma_cc struct - * @slot: number of parameter RAM slot being copied - * @param: where to store copy of parameter RAM data - * - * Use this to read data from a parameter RAM slot, perhaps to - * save them as a template for later reuse. - */ static void edma_read_slot(struct edma_cc *ecc, unsigned slot, struct edmacc_param *param) { @@ -590,15 +569,6 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot) return EDMA_CTLR_CHAN(ecc->id, slot); } -/** - * edma_free_slot - deallocate DMA parameter RAM - * @ecc: pointer to edma_cc struct - * @slot: parameter RAM slot returned from edma_alloc_slot() - * - * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). - * Callers are responsible for ensuring the slot is inactive, and will - * not be activated. - */ static void edma_free_slot(struct edma_cc *ecc, unsigned slot) { slot = EDMA_CHAN_SLOT(slot); @@ -707,10 +677,9 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) * @ecc: pointer to edma_cc struct * @channel: channel being deactivated * - * When @lch is a channel, any active transfer is paused and - * all pending hardware events are cleared. The current transfer - * may not be resumed, and the channel's Parameter RAM should be - * reinitialized before being reused. + * Any active transfer is paused and all pending hardware events are cleared. + * The current transfer may not be resumed, and the channel's Parameter RAM + * should be reinitialized before being reused. */ static void edma_stop(struct edma_cc *ecc, unsigned channel) { @@ -742,13 +711,9 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel) } } -/** - * edma_pause - pause dma on a channel - * @ecc: pointer to edma_cc struct - * @channel: on which edma_start() has been called - * - * This temporarily disables EDMA hardware events on the specified channel, - * preventing them from triggering new transfers on its behalf +/* + * Temporarily disable EDMA hardware events on the specified channel, + * preventing them from triggering new transfers */ static void edma_pause(struct edma_cc *ecc, unsigned channel) { @@ -766,13 +731,7 @@ static void edma_pause(struct edma_cc *ecc, unsigned channel) } } -/** - * edma_resume - resumes dma on a paused channel - * @ecc: pointer to edma_cc struct - * @channel: on which edma_pause() has been called - * - * This re-enables EDMA hardware events on the specified channel. - */ +/* Re-enable EDMA hardware events on the specified channel. */ static void edma_resume(struct edma_cc *ecc, unsigned channel) { if (ecc->id != EDMA_CTLR(channel)) { @@ -808,19 +767,6 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) return 0; } -/****************************************************************************** - * - * It cleans ParamEntry qand bring back EDMA to initial state if media has - * been removed before EDMA has finished.It is usedful for removable media. - * Arguments: - * ch_no - channel no - * - * Return: zero on success, or corresponding error no on failure - * - * FIXME this should not be needed ... edma_stop() should suffice. - * - *****************************************************************************/ - static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) { if (ecc->id != EDMA_CTLR(channel)) { @@ -975,14 +921,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) clear_bit(channel, ecc->edma_inuse); } -/* - * edma_assign_channel_eventq - move given channel to desired eventq - * Arguments: - * channel - channel number - * eventq_no - queue to move the channel - * - * Can be used to move a channel to a selected event queue. - */ +/* Move channel to a specific event queue */ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, enum dma_event_q eventq_no) { @@ -1005,6 +944,7 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, edma_map_dmach_to_queue(ecc, channel, eventq_no); } +/* eDMA interrupt handler */ static irqreturn_t dma_irq_handler(int irq, void *data) { struct edma_cc *ecc = data; @@ -1056,11 +996,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) return IRQ_HANDLED; } -/****************************************************************************** - * - * DMA error interrupt handler - * - *****************************************************************************/ +/* eDMA error interrupt handler */ static irqreturn_t dma_ccerr_handler(int irq, void *data) { struct edma_cc *ecc = data; -- cgit v1.2.3 From 79ad2e383d01d03188d9e51e2058545203288bc4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:01 +0300 Subject: dmaengine: edma: Simplify the interrupt handling With the merger of the arch/arm/common/edma.c code into the dmaengine driver, there is no longer need to have per channel callback/data storage for interrupt events. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 450 ++++++++++++++++++++++++----------------------------- 1 file changed, 205 insertions(+), 245 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 6bcbdceb3dc2..daa94a4bbe11 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -154,12 +154,6 @@ struct edmacc_param { #define TCCHEN BIT(22) #define ITCCHEN BIT(23) -/*ch_status parameter of callback function possible values*/ -#define EDMA_DMA_COMPLETE 1 -#define EDMA_DMA_CC_ERROR 2 -#define EDMA_DMA_TC1_ERROR 3 -#define EDMA_DMA_TC2_ERROR 4 - struct edma_pset { u32 len; dma_addr_t addr; @@ -243,12 +237,6 @@ struct edma_cc { */ unsigned long *edma_unused; - struct dma_interrupt_data { - void (*callback)(unsigned channel, unsigned short ch_status, - void *data); - void *data; - } *intr_data; - struct dma_device dma_slave; struct edma_chan *slave_chans; int dummy_slot; @@ -486,24 +474,18 @@ static int prepare_unused_channel_list(struct device *dev, void *data) return 0; } -static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data) +static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, bool enable) { lch = EDMA_CHAN_SLOT(lch); - if (!callback) - edma_shadow0_write_array(ecc, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); - - ecc->intr_data[lch].callback = callback; - ecc->intr_data[lch].data = data; - - if (callback) { + if (enable) { edma_shadow0_write_array(ecc, SH_ICR, lch >> 5, BIT(lch & 0x1f)); edma_shadow0_write_array(ecc, SH_IESR, lch >> 5, BIT(lch & 0x1f)); + } else { + edma_shadow0_write_array(ecc, SH_IECR, lch >> 5, + BIT(lch & 0x1f)); } } @@ -795,8 +777,6 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) * edma_alloc_channel - allocate DMA channel and paired parameter RAM * @ecc: pointer to edma_cc struct * @channel: specific channel to allocate; negative for "any unmapped channel" - * @callback: optional; to be issued on DMA completion or errors - * @data: passed to callback * @eventq_no: an EVENTQ_* constant, used to choose which Transfer * Controller (TC) executes requests using this channel. Use * EVENTQ_DEFAULT unless you really need a high priority queue. @@ -823,9 +803,7 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) * Returns the number of the channel, else negative errno. */ static int edma_alloc_channel(struct edma_cc *ecc, int channel, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data, - enum dma_event_q eventq_no) + enum dma_event_q eventq_no) { unsigned done = 0; int ret = 0; @@ -881,9 +859,7 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel)); edma_write_slot(ecc, channel, &dummy_paramset); - if (callback) - edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), - callback, data); + edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true); edma_map_dmach_to_queue(ecc, channel, eventq_no); @@ -914,7 +890,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) if (channel >= ecc->num_channels) return; - edma_setup_interrupt(ecc, channel, NULL, NULL); + edma_setup_interrupt(ecc, channel, false); /* REVISIT should probably take out of shadow region 0 */ edma_write_slot(ecc, channel, &dummy_paramset); @@ -944,148 +920,6 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, edma_map_dmach_to_queue(ecc, channel, eventq_no); } -/* eDMA interrupt handler */ -static irqreturn_t dma_irq_handler(int irq, void *data) -{ - struct edma_cc *ecc = data; - int ctlr; - u32 sh_ier; - u32 sh_ipr; - u32 bank; - - ctlr = ecc->id; - if (ctlr < 0) - return IRQ_NONE; - - dev_dbg(ecc->dev, "dma_irq_handler\n"); - - sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); - if (!sh_ipr) { - sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); - if (!sh_ipr) - return IRQ_NONE; - sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); - bank = 1; - } else { - sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); - bank = 0; - } - - do { - u32 slot; - u32 channel; - - dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr); - - slot = __ffs(sh_ipr); - sh_ipr &= ~(BIT(slot)); - - if (sh_ier & BIT(slot)) { - channel = (bank << 5) | slot; - /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); - if (ecc->intr_data[channel].callback) - ecc->intr_data[channel].callback( - EDMA_CTLR_CHAN(ctlr, channel), - EDMA_DMA_COMPLETE, - ecc->intr_data[channel].data); - } - } while (sh_ipr); - - edma_shadow0_write(ecc, SH_IEVAL, 1); - return IRQ_HANDLED; -} - -/* eDMA error interrupt handler */ -static irqreturn_t dma_ccerr_handler(int irq, void *data) -{ - struct edma_cc *ecc = data; - int i; - int ctlr; - unsigned int cnt = 0; - - ctlr = ecc->id; - if (ctlr < 0) - return IRQ_NONE; - - dev_dbg(ecc->dev, "dma_ccerr_handler\n"); - - if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && - (edma_read_array(ecc, EDMA_EMR, 1) == 0) && - (edma_read(ecc, EDMA_QEMR) == 0) && - (edma_read(ecc, EDMA_CCERR) == 0)) - return IRQ_NONE; - - while (1) { - int j = -1; - - if (edma_read_array(ecc, EDMA_EMR, 0)) - j = 0; - else if (edma_read_array(ecc, EDMA_EMR, 1)) - j = 1; - if (j >= 0) { - dev_dbg(ecc->dev, "EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - - if (edma_read_array(ecc, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(ecc, EDMA_EMCR, j, - BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(ecc, SH_SECR, - j, BIT(i)); - if (ecc->intr_data[k].callback) { - ecc->intr_data[k].callback( - EDMA_CTLR_CHAN(ctlr, k), - EDMA_DMA_CC_ERROR, - ecc->intr_data[k].data); - } - } - } - } else if (edma_read(ecc, EDMA_QEMR)) { - dev_dbg(ecc->dev, "QEMR %02x\n", - edma_read(ecc, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ecc, SH_QSECR, - BIT(i)); - - /* NOTE: not reported!! */ - } - } - } else if (edma_read(ecc, EDMA_CCERR)) { - dev_dbg(ecc->dev, "CCERR %08x\n", - edma_read(ecc, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_CCERRCLR, BIT(i)); - - /* NOTE: not reported!! */ - } - } - } - if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && - (edma_read_array(ecc, EDMA_EMR, 1) == 0) && - (edma_read(ecc, EDMA_QEMR) == 0) && - (edma_read(ecc, EDMA_CCERR) == 0)) - break; - cnt++; - if (cnt > 10) - break; - } - edma_write(ecc, EDMA_EEVAL, 1); - return IRQ_HANDLED; -} - static inline struct edma_cc *to_edma_cc(struct dma_device *d) { return container_of(d, struct edma_cc, dma_slave); @@ -1667,81 +1501,214 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } -static void edma_callback(unsigned ch_num, u16 ch_status, void *data) +static void edma_completion_handler(struct edma_chan *echan) { - struct edma_chan *echan = data; struct edma_cc *ecc = echan->ecc; struct device *dev = echan->vchan.chan.device->dev; - struct edma_desc *edesc; - struct edmacc_param p; + struct edma_desc *edesc = echan->edesc; - edesc = echan->edesc; + if (!edesc) + return; spin_lock(&echan->vchan.lock); - switch (ch_status) { - case EDMA_DMA_COMPLETE: - if (edesc) { - if (edesc->cyclic) { - vchan_cyclic_callback(&edesc->vdesc); - goto out; - } else if (edesc->processed == edesc->pset_nr) { - dev_dbg(dev, - "Transfer completed on channel %d\n", - ch_num); - edesc->residue = 0; - edma_stop(ecc, echan->ch_num); - vchan_cookie_complete(&edesc->vdesc); - echan->edesc = NULL; - } else { - dev_dbg(dev, - "Sub transfer completed on channel %d\n", - ch_num); - - edma_pause(ecc, echan->ch_num); - - /* Update statistics for tx_status */ - edesc->residue -= edesc->sg_len; - edesc->residue_stat = edesc->residue; - edesc->processed_stat = edesc->processed; - } - edma_execute(echan); + if (edesc->cyclic) { + vchan_cyclic_callback(&edesc->vdesc); + spin_unlock(&echan->vchan.lock); + return; + } else if (edesc->processed == edesc->pset_nr) { + edesc->residue = 0; + edma_stop(ecc, echan->ch_num); + vchan_cookie_complete(&edesc->vdesc); + echan->edesc = NULL; + + dev_dbg(dev, "Transfer completed on channel %d\n", + echan->ch_num); + } else { + dev_dbg(dev, "Sub transfer completed on channel %d\n", + echan->ch_num); + + edma_pause(ecc, echan->ch_num); + + /* Update statistics for tx_status */ + edesc->residue -= edesc->sg_len; + edesc->residue_stat = edesc->residue; + edesc->processed_stat = edesc->processed; + } + edma_execute(echan); + + spin_unlock(&echan->vchan.lock); +} + +/* eDMA interrupt handler */ +static irqreturn_t dma_irq_handler(int irq, void *data) +{ + struct edma_cc *ecc = data; + int ctlr; + u32 sh_ier; + u32 sh_ipr; + u32 bank; + + ctlr = ecc->id; + if (ctlr < 0) + return IRQ_NONE; + + dev_vdbg(ecc->dev, "dma_irq_handler\n"); + + sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); + if (!sh_ipr) { + sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); + if (!sh_ipr) + return IRQ_NONE; + sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); + bank = 1; + } else { + sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); + bank = 0; + } + + do { + u32 slot; + u32 channel; + + slot = __ffs(sh_ipr); + sh_ipr &= ~(BIT(slot)); + + if (sh_ier & BIT(slot)) { + channel = (bank << 5) | slot; + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); + edma_completion_handler(&ecc->slave_chans[channel]); } - break; - case EDMA_DMA_CC_ERROR: - edma_read_slot(ecc, echan->slot[0], &p); + } while (sh_ipr); + + edma_shadow0_write(ecc, SH_IEVAL, 1); + return IRQ_HANDLED; +} + +static void edma_error_handler(struct edma_chan *echan) +{ + struct edma_cc *ecc = echan->ecc; + struct device *dev = echan->vchan.chan.device->dev; + struct edmacc_param p; + + if (!echan->edesc) + return; + + spin_lock(&echan->vchan.lock); + edma_read_slot(ecc, echan->slot[0], &p); + /* + * Issue later based on missed flag which will be sure + * to happen as: + * (1) we finished transmitting an intermediate slot and + * edma_execute is coming up. + * (2) or we finished current transfer and issue will + * call edma_execute. + * + * Important note: issuing can be dangerous here and + * lead to some nasty recursion when we are in a NULL + * slot. So we avoid doing so and set the missed flag. + */ + if (p.a_b_cnt == 0 && p.ccnt == 0) { + dev_dbg(dev, "Error on null slot, setting miss\n"); + echan->missed = 1; + } else { /* - * Issue later based on missed flag which will be sure - * to happen as: - * (1) we finished transmitting an intermediate slot and - * edma_execute is coming up. - * (2) or we finished current transfer and issue will - * call edma_execute. - * - * Important note: issuing can be dangerous here and - * lead to some nasty recursion when we are in a NULL - * slot. So we avoid doing so and set the missed flag. + * The slot is already programmed but the event got + * missed, so its safe to issue it here. */ - if (p.a_b_cnt == 0 && p.ccnt == 0) { - dev_dbg(dev, "Error on null slot, setting miss\n"); - echan->missed = 1; - } else { - /* - * The slot is already programmed but the event got - * missed, so its safe to issue it here. + dev_dbg(dev, "Missed event, TRIGGERING\n"); + edma_clean_channel(ecc, echan->ch_num); + edma_stop(ecc, echan->ch_num); + edma_start(ecc, echan->ch_num); + edma_trigger_channel(ecc, echan->ch_num); + } + spin_unlock(&echan->vchan.lock); +} + +/* eDMA error interrupt handler */ +static irqreturn_t dma_ccerr_handler(int irq, void *data) +{ + struct edma_cc *ecc = data; + int i; + int ctlr; + unsigned int cnt = 0; + + ctlr = ecc->id; + if (ctlr < 0) + return IRQ_NONE; + + dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); + + if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && + (edma_read_array(ecc, EDMA_EMR, 1) == 0) && + (edma_read(ecc, EDMA_QEMR) == 0) && + (edma_read(ecc, EDMA_CCERR) == 0)) + return IRQ_NONE; + + while (1) { + int j = -1; + + if (edma_read_array(ecc, EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(ecc, EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + dev_dbg(ecc->dev, "EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + + if (edma_read_array(ecc, EDMA_EMR, j) & + BIT(i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, + BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, + j, BIT(i)); + edma_error_handler(&ecc->slave_chans[k]); + } + } + } else if (edma_read(ecc, EDMA_QEMR)) { + dev_dbg(ecc->dev, "QEMR %02x\n", + edma_read(ecc, EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ecc, EDMA_QEMCR, BIT(i)); + edma_shadow0_write(ecc, SH_QSECR, + BIT(i)); + + /* NOTE: not reported!! */ + } + } + } else if (edma_read(ecc, EDMA_CCERR)) { + dev_dbg(ecc->dev, "CCERR %08x\n", + edma_read(ecc, EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... */ - dev_dbg(dev, "Missed event, TRIGGERING\n"); - edma_clean_channel(ecc, echan->ch_num); - edma_stop(ecc, echan->ch_num); - edma_start(ecc, echan->ch_num); - edma_trigger_channel(ecc, echan->ch_num); + for (i = 0; i < 8; i++) { + if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ecc, EDMA_CCERRCLR, BIT(i)); + + /* NOTE: not reported!! */ + } + } } - break; - default: - break; + if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && + (edma_read_array(ecc, EDMA_EMR, 1) == 0) && + (edma_read(ecc, EDMA_QEMR) == 0) && + (edma_read(ecc, EDMA_CCERR) == 0)) + break; + cnt++; + if (cnt > 10) + break; } -out: - spin_unlock(&echan->vchan.lock); + edma_write(ecc, EDMA_EEVAL, 1); + return IRQ_HANDLED; } /* Alloc channel resources */ @@ -1753,8 +1720,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) int a_ch_num; LIST_HEAD(descs); - a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, - edma_callback, echan, EVENTQ_DEFAULT); + a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, EVENTQ_DEFAULT); if (a_ch_num < 0) { ret = -ENODEV; @@ -2175,11 +2141,6 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slave_chans) return -ENOMEM; - ecc->intr_data = devm_kcalloc(dev, ecc->num_channels, - sizeof(*ecc->intr_data), GFP_KERNEL); - if (!ecc->intr_data) - return -ENOMEM; - ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels), sizeof(unsigned long), GFP_KERNEL); if (!ecc->edma_unused) @@ -2350,8 +2311,7 @@ static int edma_pm_resume(struct device *dev) BIT(i & 0x1f)); edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i), - ecc->intr_data[i].callback, - ecc->intr_data[i].data); + true); } } -- cgit v1.2.3 From 7c3b8b3d2608bb4b1a97749c607440785b60ef7f Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:02 +0300 Subject: dmaengine: edma: Move the pending error check into helper function In the ccerr interrupt handler the code checks for pending errors in the error status registers in two different places. Move the check out to a helper function. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index daa94a4bbe11..84b98a01993a 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1626,6 +1626,16 @@ static void edma_error_handler(struct edma_chan *echan) spin_unlock(&echan->vchan.lock); } +static inline bool edma_error_pending(struct edma_cc *ecc) +{ + if (edma_read_array(ecc, EDMA_EMR, 0) || + edma_read_array(ecc, EDMA_EMR, 1) || + edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) + return true; + + return false; +} + /* eDMA error interrupt handler */ static irqreturn_t dma_ccerr_handler(int irq, void *data) { @@ -1640,10 +1650,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); - if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && - (edma_read_array(ecc, EDMA_EMR, 1) == 0) && - (edma_read(ecc, EDMA_QEMR) == 0) && - (edma_read(ecc, EDMA_CCERR) == 0)) + if (!edma_error_pending(ecc)) return IRQ_NONE; while (1) { @@ -1698,10 +1705,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) } } } - if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && - (edma_read_array(ecc, EDMA_EMR, 1) == 0) && - (edma_read(ecc, EDMA_QEMR) == 0) && - (edma_read(ecc, EDMA_CCERR) == 0)) + if (!edma_error_pending(ecc)) break; cnt++; if (cnt > 10) -- cgit v1.2.3 From e4402a129faca71ddd160d89ef7750da0ce2d6c4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:03 +0300 Subject: dmaengine: edma: Simplify and optimize ccerr interrupt handler No need to run through the bits in QEMR and CCERR events since they will not trigger any action, so just clearing the errors there is fine. In case of the missed event the loop can be optimized so we spend less time to handle the event. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 82 +++++++++++++++++++++++------------------------------- 1 file changed, 35 insertions(+), 47 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 84b98a01993a..d105d1ae0f13 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1640,9 +1640,10 @@ static inline bool edma_error_pending(struct edma_cc *ecc) static irqreturn_t dma_ccerr_handler(int irq, void *data) { struct edma_cc *ecc = data; - int i; + int i, j; int ctlr; unsigned int cnt = 0; + unsigned int val; ctlr = ecc->id; if (ctlr < 0) @@ -1654,57 +1655,44 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) return IRQ_NONE; while (1) { - int j = -1; - - if (edma_read_array(ecc, EDMA_EMR, 0)) - j = 0; - else if (edma_read_array(ecc, EDMA_EMR, 1)) - j = 1; - if (j >= 0) { - dev_dbg(ecc->dev, "EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { + /* Event missed register(s) */ + for (j = 0; j < 2; j++) { + unsigned long emr; + + val = edma_read_array(ecc, EDMA_EMR, j); + if (!val) + continue; + + dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); + emr = val; + for (i = find_next_bit(&emr, 32, 0); i < 32; + i = find_next_bit(&emr, 32, i + 1)) { int k = (j << 5) + i; - if (edma_read_array(ecc, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(ecc, EDMA_EMCR, j, + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(ecc, SH_SECR, - j, BIT(i)); - edma_error_handler(&ecc->slave_chans[k]); - } - } - } else if (edma_read(ecc, EDMA_QEMR)) { - dev_dbg(ecc->dev, "QEMR %02x\n", - edma_read(ecc, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ecc, SH_QSECR, - BIT(i)); - - /* NOTE: not reported!! */ - } - } - } else if (edma_read(ecc, EDMA_CCERR)) { - dev_dbg(ecc->dev, "CCERR %08x\n", - edma_read(ecc, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_CCERRCLR, BIT(i)); - - /* NOTE: not reported!! */ - } + edma_error_handler(&ecc->slave_chans[k]); } } + + val = edma_read(ecc, EDMA_QEMR); + if (val) { + dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); + /* Not reported, just clear the interrupt reason. */ + edma_write(ecc, EDMA_QEMCR, val); + edma_shadow0_write(ecc, SH_QSECR, val); + } + + val = edma_read(ecc, EDMA_CCERR); + if (val) { + dev_warn(ecc->dev, "CCERR 0x%08x\n", val); + /* Not reported, just clear the interrupt reason. */ + edma_write(ecc, EDMA_CCERRCLR, val); + } + if (!edma_error_pending(ecc)) break; cnt++; -- cgit v1.2.3 From 4ab54f696dc5299d7db9d924f28f408dc0404f1b Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:04 +0300 Subject: dmaengine: edma: Read channel mapping support only once from HW Instead of directly reading it from CCCFG register take the information out once when we set up the configuration from the HW. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d105d1ae0f13..4b2ccc9de0ad 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -223,6 +223,7 @@ struct edma_cc { unsigned num_region; unsigned num_slots; unsigned num_tc; + bool chmap_exist; enum dma_event_q default_queue; bool unused_chan_list_done; @@ -1930,11 +1931,14 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, value = GET_NUM_EVQUE(cccfg); ecc->num_tc = value + 1; + ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; + dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); dev_dbg(dev, "num_region: %u\n", ecc->num_region); dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); + dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); /* Nothing need to be done if queue priority is provided */ if (pdata->queue_priority_mapping) @@ -2223,7 +2227,7 @@ static int edma_probe(struct platform_device *pdev) queue_priority_mapping[i][1]); /* Map the channel to param entry if channel mapping logic exist */ - if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + if (ecc->chmap_exist) edma_direct_dmach_to_param_mapping(ecc); for (i = 0; i < ecc->num_region; i++) { @@ -2293,7 +2297,7 @@ static int edma_pm_resume(struct device *dev) queue_priority_mapping[i][1]); /* Map the channel to param entry if channel mapping logic */ - if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + if (ecc->chmap_exist) edma_direct_dmach_to_param_mapping(ecc); for (i = 0; i < ecc->num_channels; i++) { -- cgit v1.2.3 From 7a73b135cdb33f78acab118dd72782416d5281b2 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:05 +0300 Subject: dmaengine: edma: Rename bitfields for slot and channel usage tracking The names chosen for the bitfields were quite confusing and given no real information on what they are used for... edma_inuse -> slot_inuse: tracks the slot usage/availability edma_unused -> channel_unused: tracks the channel usage/availability Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 51 ++++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 25 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 4b2ccc9de0ad..8d9169b7f208 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -227,16 +227,16 @@ struct edma_cc { enum dma_event_q default_queue; bool unused_chan_list_done; - /* The edma_inuse bit for each PaRAM slot is clear unless the + /* The slot_inuse bit for each PaRAM slot is clear unless the * channel is in use ... by ARM or DSP, for QDMA, or whatever. */ - unsigned long *edma_inuse; + unsigned long *slot_inuse; - /* The edma_unused bit for each channel is clear unless + /* The channel_unused bit for each channel is clear unless * it is not being used on this platform. It uses a bit * of SOC-specific initialization code. */ - unsigned long *edma_unused; + unsigned long *channel_unused; struct dma_device dma_slave; struct edma_chan *slave_chans; @@ -452,7 +452,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data) continue; clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), - ecc->edma_unused); + ecc->channel_unused); of_node_put(dma_spec.np); } return 0; @@ -469,7 +469,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data) dma_req = (int)res->start; if (dma_req >= dma_req_min && dma_req < dma_req_max) clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - ecc->edma_unused); + ecc->channel_unused); } return 0; @@ -533,17 +533,17 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot) if (slot < 0) { slot = ecc->num_channels; for (;;) { - slot = find_next_zero_bit(ecc->edma_inuse, + slot = find_next_zero_bit(ecc->slot_inuse, ecc->num_slots, slot); if (slot == ecc->num_slots) return -ENOMEM; - if (!test_and_set_bit(slot, ecc->edma_inuse)) + if (!test_and_set_bit(slot, ecc->slot_inuse)) break; } } else if (slot < ecc->num_channels || slot >= ecc->num_slots) { return -EINVAL; - } else if (test_and_set_bit(slot, ecc->edma_inuse)) { + } else if (test_and_set_bit(slot, ecc->slot_inuse)) { return -EBUSY; } @@ -559,7 +559,7 @@ static void edma_free_slot(struct edma_cc *ecc, unsigned slot) return; edma_write_slot(ecc, slot, &dummy_paramset); - clear_bit(slot, ecc->edma_inuse); + clear_bit(slot, ecc->slot_inuse); } /** @@ -631,7 +631,7 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) unsigned int mask = BIT(channel & 0x1f); /* EDMA channels without event association */ - if (test_bit(channel, ecc->edma_unused)) { + if (test_bit(channel, ecc->channel_unused)) { dev_dbg(ecc->dev, "ESR%d %08x\n", j, edma_shadow0_read_array(ecc, SH_ESR, j)); edma_shadow0_write_array(ecc, SH_ESR, j, mask); @@ -835,11 +835,11 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, if (channel < 0) { channel = 0; for (;;) { - channel = find_next_bit(ecc->edma_unused, + channel = find_next_bit(ecc->channel_unused, ecc->num_channels, channel); if (channel == ecc->num_channels) break; - if (!test_and_set_bit(channel, ecc->edma_inuse)) { + if (!test_and_set_bit(channel, ecc->slot_inuse)) { done = 1; break; } @@ -849,7 +849,7 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, return -ENOMEM; } else if (channel >= ecc->num_channels) { return -EINVAL; - } else if (test_and_set_bit(channel, ecc->edma_inuse)) { + } else if (test_and_set_bit(channel, ecc->slot_inuse)) { return -EBUSY; } @@ -895,7 +895,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) /* REVISIT should probably take out of shadow region 0 */ edma_write_slot(ecc, channel, &dummy_paramset); - clear_bit(channel, ecc->edma_inuse); + clear_bit(channel, ecc->slot_inuse); } /* Move channel to a specific event queue */ @@ -2137,14 +2137,15 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slave_chans) return -ENOMEM; - ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels), - sizeof(unsigned long), GFP_KERNEL); - if (!ecc->edma_unused) + ecc->channel_unused = devm_kcalloc(dev, + BITS_TO_LONGS(ecc->num_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->channel_unused) return -ENOMEM; - ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), + ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), sizeof(unsigned long), GFP_KERNEL); - if (!ecc->edma_inuse) + if (!ecc->slot_inuse) return -ENOMEM; ecc->default_queue = info->default_queue; @@ -2153,7 +2154,7 @@ static int edma_probe(struct platform_device *pdev) edma_write_slot(ecc, i, &dummy_paramset); /* Mark all channels as unused */ - memset(ecc->edma_unused, 0xff, sizeof(ecc->edma_unused)); + memset(ecc->channel_unused, 0xff, sizeof(ecc->channel_unused)); if (info->rsv) { /* Clear the reserved channels in unused list */ @@ -2162,7 +2163,7 @@ static int edma_probe(struct platform_device *pdev) for (i = 0; rsv_chans[i][0] != -1; i++) { off = rsv_chans[i][0]; ln = rsv_chans[i][1]; - clear_bits(off, ln, ecc->edma_unused); + clear_bits(off, ln, ecc->channel_unused); } } @@ -2172,7 +2173,7 @@ static int edma_probe(struct platform_device *pdev) for (i = 0; rsv_slots[i][0] != -1; i++) { off = rsv_slots[i][0]; ln = rsv_slots[i][1]; - set_bits(off, ln, ecc->edma_inuse); + set_bits(off, ln, ecc->slot_inuse); } } } @@ -2182,7 +2183,7 @@ static int edma_probe(struct platform_device *pdev) if (xbar_chans) { for (i = 0; xbar_chans[i][1] != -1; i++) { off = xbar_chans[i][1]; - clear_bits(off, 1, ecc->edma_unused); + clear_bits(off, 1, ecc->channel_unused); } } @@ -2301,7 +2302,7 @@ static int edma_pm_resume(struct device *dev) edma_direct_dmach_to_param_mapping(ecc); for (i = 0; i < ecc->num_channels; i++) { - if (test_bit(i, ecc->edma_inuse)) { + if (test_bit(i, ecc->slot_inuse)) { /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f)); -- cgit v1.2.3 From e4e886c6b1e2a1ef9654d26dad1c3baca8139b3c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:06 +0300 Subject: dmaengine: edma: Dynamic paRAM slot handling if HW supports it If the eDMA3 has support for channel paRAM slot mapping we can utilize it to allocate slots on demand and save precious slots for real transfers. On am335x the eDMA has 64 channels which means we can unlock 64 paRAM slots out from the available 256. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 101 +++++++++++++++++++++++++++-------------------------- 1 file changed, 52 insertions(+), 49 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 8d9169b7f208..7eefbf1e1c94 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -413,12 +413,13 @@ static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); } -static void edma_direct_dmach_to_param_mapping(struct edma_cc *ecc) +static void edma_set_chmap(struct edma_cc *ecc, int channel, int slot) { - int i; - - for (i = 0; i < ecc->num_channels; i++) - edma_write_array(ecc, EDMA_DCHMAP, i, (i << 5)); + if (ecc->chmap_exist) { + channel = EDMA_CHAN_SLOT(channel); + slot = EDMA_CHAN_SLOT(slot); + edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); + } } static int prepare_unused_channel_list(struct device *dev, void *data) @@ -528,10 +529,18 @@ static void edma_read_slot(struct edma_cc *ecc, unsigned slot, */ static int edma_alloc_slot(struct edma_cc *ecc, int slot) { - if (slot > 0) + if (slot > 0) { slot = EDMA_CHAN_SLOT(slot); + /* Requesting entry paRAM slot for a HW triggered channel. */ + if (ecc->chmap_exist && slot < ecc->num_channels) + slot = EDMA_SLOT_ANY; + } + if (slot < 0) { - slot = ecc->num_channels; + if (ecc->chmap_exist) + slot = 0; + else + slot = ecc->num_channels; for (;;) { slot = find_next_zero_bit(ecc->slot_inuse, ecc->num_slots, @@ -541,7 +550,7 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot) if (!test_and_set_bit(slot, ecc->slot_inuse)) break; } - } else if (slot < ecc->num_channels || slot >= ecc->num_slots) { + } else if (slot >= ecc->num_slots) { return -EINVAL; } else if (test_and_set_bit(slot, ecc->slot_inuse)) { return -EBUSY; @@ -555,7 +564,7 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot) static void edma_free_slot(struct edma_cc *ecc, unsigned slot) { slot = EDMA_CHAN_SLOT(slot); - if (slot < ecc->num_channels || slot >= ecc->num_slots) + if (slot >= ecc->num_slots) return; edma_write_slot(ecc, slot, &dummy_paramset); @@ -806,7 +815,6 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) static int edma_alloc_channel(struct edma_cc *ecc, int channel, enum dma_event_q eventq_no) { - unsigned done = 0; int ret = 0; if (!ecc->unused_chan_list_done) { @@ -833,24 +841,12 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, } if (channel < 0) { - channel = 0; - for (;;) { - channel = find_next_bit(ecc->channel_unused, - ecc->num_channels, channel); - if (channel == ecc->num_channels) - break; - if (!test_and_set_bit(channel, ecc->slot_inuse)) { - done = 1; - break; - } - channel++; - } - if (!done) - return -ENOMEM; + channel = find_next_bit(ecc->channel_unused, ecc->num_channels, + 0); + if (channel == ecc->num_channels) + return -EBUSY; } else if (channel >= ecc->num_channels) { return -EINVAL; - } else if (test_and_set_bit(channel, ecc->slot_inuse)) { - return -EBUSY; } /* ensure access through shadow region 0 */ @@ -858,7 +854,6 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, /* ensure no events are pending */ edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel)); - edma_write_slot(ecc, channel, &dummy_paramset); edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true); @@ -891,11 +886,8 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) if (channel >= ecc->num_channels) return; - edma_setup_interrupt(ecc, channel, false); /* REVISIT should probably take out of shadow region 0 */ - - edma_write_slot(ecc, channel, &dummy_paramset); - clear_bit(channel, ecc->slot_inuse); + edma_setup_interrupt(ecc, channel, false); } /* Move channel to a specific event queue */ @@ -1729,7 +1721,15 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) } echan->alloced = true; - echan->slot[0] = echan->ch_num; + echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num); + if (echan->slot[0] < 0) { + dev_err(dev, "Entry slot allocation failed for channel %u\n", + EDMA_CHAN_SLOT(echan->ch_num)); + goto err_wrong_chan; + } + + /* Set up channel -> slot mapping for the entry slot */ + edma_set_chmap(echan->ecc, echan->ch_num, echan->slot[0]); dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); @@ -1754,13 +1754,16 @@ static void edma_free_chan_resources(struct dma_chan *chan) vchan_free_chan_resources(&echan->vchan); /* Free EDMA PaRAM slots */ - for (i = 1; i < EDMA_MAX_SLOTS; i++) { + for (i = 0; i < EDMA_MAX_SLOTS; i++) { if (echan->slot[i] >= 0) { edma_free_slot(echan->ecc, echan->slot[i]); echan->slot[i] = -1; } } + /* Set entry slot to the dummy slot */ + edma_set_chmap(echan->ecc, echan->ch_num, echan->ecc->dummy_slot); + /* Free EDMA channel */ if (echan->alloced) { edma_free_channel(echan->ecc, echan->ch_num); @@ -2217,8 +2220,18 @@ static int edma_probe(struct platform_device *pdev) } } - for (i = 0; i < ecc->num_channels; i++) + ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); + if (ecc->dummy_slot < 0) { + dev_err(dev, "Can't allocate PaRAM dummy slot\n"); + return ecc->dummy_slot; + } + + for (i = 0; i < ecc->num_channels; i++) { + /* Assign all channels to the default queue */ edma_map_dmach_to_queue(ecc, i, info->default_queue); + /* Set entry slot to the dummy slot */ + edma_set_chmap(ecc, i, ecc->dummy_slot); + } queue_priority_mapping = info->queue_priority_mapping; @@ -2227,10 +2240,6 @@ static int edma_probe(struct platform_device *pdev) edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], queue_priority_mapping[i][1]); - /* Map the channel to param entry if channel mapping logic exist */ - if (ecc->chmap_exist) - edma_direct_dmach_to_param_mapping(ecc); - for (i = 0; i < ecc->num_region; i++) { edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); @@ -2238,12 +2247,6 @@ static int edma_probe(struct platform_device *pdev) } ecc->info = info; - ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); - if (ecc->dummy_slot < 0) { - dev_err(dev, "Can't allocate PaRAM dummy slot\n"); - return ecc->dummy_slot; - } - dma_cap_zero(ecc->dma_slave.cap_mask); dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); @@ -2287,6 +2290,7 @@ static int edma_remove(struct platform_device *pdev) static int edma_pm_resume(struct device *dev) { struct edma_cc *ecc = dev_get_drvdata(dev); + struct edma_chan *echan = ecc->slave_chans; int i; s8 (*queue_priority_mapping)[2]; @@ -2297,18 +2301,17 @@ static int edma_pm_resume(struct device *dev) edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], queue_priority_mapping[i][1]); - /* Map the channel to param entry if channel mapping logic */ - if (ecc->chmap_exist) - edma_direct_dmach_to_param_mapping(ecc); - for (i = 0; i < ecc->num_channels; i++) { - if (test_bit(i, ecc->slot_inuse)) { + if (echan[i].alloced) { /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f)); edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i), true); + + /* Set up channel -> slot mapping for the entry slot */ + edma_set_chmap(ecc, echan[i].ch_num, echan[i].slot[0]); } } -- cgit v1.2.3 From 21a31846a7736a88709fe6fe2e73857d884de89c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:17:59 +0300 Subject: dmaengine: edma: Remove alignment constraint for memcpy Despite the claim by the original commit adding the memcpy support, eDMA does not have constraint on the alignment of src, dst or length in increment mode. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 7eefbf1e1c94..b36dfa5458cb 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1324,6 +1324,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( struct edma_desc *edesc; struct device *dev = chan->device->dev; struct edma_chan *echan = to_edma_chan(chan); + unsigned int width; if (unlikely(!echan || !len)) return NULL; @@ -1336,8 +1337,12 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( edesc->pset_nr = 1; + width = 1 << __ffs((src | dest | len)); + if (width > DMA_SLAVE_BUSWIDTH_64_BYTES) + width = DMA_SLAVE_BUSWIDTH_64_BYTES; + ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, - DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM); + width, len, DMA_MEM_TO_MEM); if (ret < 0) return NULL; @@ -1903,12 +1908,6 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, dma->dev = dev; - /* - * code using dma memcpy must make sure alignment of - * length is at dma->copy_align boundary. - */ - dma->copy_align = DMAENGINE_ALIGN_4_BYTES; - INIT_LIST_HEAD(&dma->channels); } -- cgit v1.2.3 From df6694f80365a72700d4c68fcf61ef068f5b3c25 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:00 +0300 Subject: dmaengine: edma: Optimize memcpy operation If the transfer is shorted then 64K we can complete it with one ACNT burst by configuring ACNT to the length of the copy, this require one paRAM slot. Otherwise we use two paRAM slots for the copy: slot1: will copy (length / 32767) number of 32767 byte long blocks slot2: will be configured to copy the remaining data. According to tests this patch increases the throughput of memcpy from ~3MB/s to 15MB/s Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 96 ++++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 75 insertions(+), 21 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index b36dfa5458cb..c0165e3d3396 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1107,19 +1107,16 @@ static int edma_dma_resume(struct dma_chan *chan) */ static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, - enum dma_slave_buswidth dev_width, - unsigned int dma_length, + unsigned int acnt, unsigned int dma_length, enum dma_transfer_direction direction) { struct edma_chan *echan = to_edma_chan(chan); struct device *dev = chan->device->dev; struct edmacc_param *param = &epset->param; - int acnt, bcnt, ccnt, cidx; + int bcnt, ccnt, cidx; int src_bidx, dst_bidx, src_cidx, dst_cidx; int absync; - acnt = dev_width; - /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ if (!burst) burst = 1; @@ -1320,41 +1317,98 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long tx_flags) { - int ret; + int ret, nslots; struct edma_desc *edesc; struct device *dev = chan->device->dev; struct edma_chan *echan = to_edma_chan(chan); - unsigned int width; + unsigned int width, pset_len; if (unlikely(!echan || !len)) return NULL; - edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC); + if (len < SZ_64K) { + /* + * Transfer size less than 64K can be handled with one paRAM + * slot and with one burst. + * ACNT = length + */ + width = len; + pset_len = len; + nslots = 1; + } else { + /* + * Transfer size bigger than 64K will be handled with maximum of + * two paRAM slots. + * slot1: (full_length / 32767) times 32767 bytes bursts. + * ACNT = 32767, length1: (full_length / 32767) * 32767 + * slot2: the remaining amount of data after slot1. + * ACNT = full_length - length1, length2 = ACNT + * + * When the full_length is multibple of 32767 one slot can be + * used to complete the transfer. + */ + width = SZ_32K - 1; + pset_len = rounddown(len, width); + /* One slot is enough for lengths multiple of (SZ_32K -1) */ + if (unlikely(pset_len == len)) + nslots = 1; + else + nslots = 2; + } + + edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), + GFP_ATOMIC); if (!edesc) { dev_dbg(dev, "Failed to allocate a descriptor\n"); return NULL; } - edesc->pset_nr = 1; - - width = 1 << __ffs((src | dest | len)); - if (width > DMA_SLAVE_BUSWIDTH_64_BYTES) - width = DMA_SLAVE_BUSWIDTH_64_BYTES; + edesc->pset_nr = nslots; + edesc->residue = edesc->residue_stat = len; + edesc->direction = DMA_MEM_TO_MEM; + edesc->echan = echan; ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, - width, len, DMA_MEM_TO_MEM); - if (ret < 0) + width, pset_len, DMA_MEM_TO_MEM); + if (ret < 0) { + kfree(edesc); return NULL; + } edesc->absync = ret; - /* - * Enable intermediate transfer chaining to re-trigger channel - * on completion of every TR, and enable transfer-completion - * interrupt on completion of the whole transfer. - */ edesc->pset[0].param.opt |= ITCCHEN; - edesc->pset[0].param.opt |= TCINTEN; + if (nslots == 1) { + /* Enable transfer complete interrupt */ + edesc->pset[0].param.opt |= TCINTEN; + } else { + /* Enable transfer complete chaining for the first slot */ + edesc->pset[0].param.opt |= TCCHEN; + + if (echan->slot[1] < 0) { + echan->slot[1] = edma_alloc_slot(echan->ecc, + EDMA_SLOT_ANY); + if (echan->slot[1] < 0) { + kfree(edesc); + dev_err(dev, "%s: Failed to allocate slot\n", + __func__); + return NULL; + } + } + dest += pset_len; + src += pset_len; + pset_len = width = len % (SZ_32K - 1); + + ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1, + width, pset_len, DMA_MEM_TO_MEM); + if (ret < 0) { + kfree(edesc); + return NULL; + } + + edesc->pset[1].param.opt |= ITCCHEN; + edesc->pset[1].param.opt |= TCINTEN; + } return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } -- cgit v1.2.3 From 34cf30111cfccd18e1ccf2456f72dff6d42bd853 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:01 +0300 Subject: dmaengine: edma: Simplify function parameter list for channel operations Instead of passing a pointer to struct edma_cc and the channel number, pass only the pointer to the edma_chan structure for the given channel. This struct contains all the information needed by the functions and the use of this makes it obvious that most of the sanity checks can be removed from the driver. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 396 +++++++++++++++++------------------------------------ 1 file changed, 123 insertions(+), 273 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index c0165e3d3396..a64befecf477 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -391,17 +391,19 @@ static inline void clear_bits(int offset, int len, unsigned long *p) clear_bit(offset + (len - 1), p); } -static void edma_map_dmach_to_queue(struct edma_cc *ecc, unsigned ch_no, +static void edma_map_dmach_to_queue(struct edma_chan *echan, enum dma_event_q queue_no) { - int bit = (ch_no & 0x7) * 4; + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int bit = (channel & 0x7) * 4; /* default to low priority queue */ if (queue_no == EVENTQ_DEFAULT) queue_no = ecc->default_queue; queue_no &= 7; - edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit), + edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), queue_no << bit); } @@ -413,10 +415,12 @@ static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); } -static void edma_set_chmap(struct edma_cc *ecc, int channel, int slot) +static void edma_set_chmap(struct edma_chan *echan, int slot) { + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + if (ecc->chmap_exist) { - channel = EDMA_CHAN_SLOT(channel); slot = EDMA_CHAN_SLOT(slot); edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); } @@ -476,18 +480,19 @@ static int prepare_unused_channel_list(struct device *dev, void *data) return 0; } -static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, bool enable) +static void edma_setup_interrupt(struct edma_chan *echan, bool enable) { - lch = EDMA_CHAN_SLOT(lch); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); if (enable) { - edma_shadow0_write_array(ecc, SH_ICR, lch >> 5, - BIT(lch & 0x1f)); - edma_shadow0_write_array(ecc, SH_IESR, lch >> 5, - BIT(lch & 0x1f)); + edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, + BIT(channel & 0x1f)); + edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, + BIT(channel & 0x1f)); } else { - edma_shadow0_write_array(ecc, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); + edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, + BIT(channel & 0x1f)); } } @@ -613,40 +618,25 @@ static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, return edma_read(ecc, offs); } -/*-----------------------------------------------------------------------*/ -/** - * edma_start - start dma on a channel - * @ecc: pointer to edma_cc struct - * @channel: channel being activated - * +/* * Channels with event associations will be triggered by their hardware * events, and channels without such associations will be triggered by * software. (At this writing there is no interface for using software * triggers except with channels that don't support hardware triggers.) - * - * Returns zero on success, else negative errno. */ -static int edma_start(struct edma_cc *ecc, unsigned channel) +static void edma_start(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < ecc->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); + if (test_bit(channel, ecc->channel_unused)) { /* EDMA channels without event association */ - if (test_bit(channel, ecc->channel_unused)) { - dev_dbg(ecc->dev, "ESR%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ESR, j)); - edma_shadow0_write_array(ecc, SH_ESR, j, mask); - return 0; - } - + dev_dbg(ecc->dev, "ESR%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ESR, j)); + edma_shadow0_write_array(ecc, SH_ESR, j, mask); + } else { /* EDMA channel with event association */ dev_dbg(ecc->dev, "ER%d %08x\n", j, edma_shadow0_read_array(ecc, SH_ER, j)); @@ -658,164 +648,86 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) edma_shadow0_write_array(ecc, SH_EESR, j, mask); dev_dbg(ecc->dev, "EER%d %08x\n", j, edma_shadow0_read_array(ecc, SH_EER, j)); - return 0; } - - return -EINVAL; } -/** - * edma_stop - stops dma on the channel passed - * @ecc: pointer to edma_cc struct - * @channel: channel being deactivated - * - * Any active transfer is paused and all pending hardware events are cleared. - * The current transfer may not be resumed, and the channel's Parameter RAM - * should be reinitialized before being reused. - */ -static void edma_stop(struct edma_cc *ecc, unsigned channel) +static void edma_stop(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); - if (channel < ecc->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + edma_shadow0_write_array(ecc, SH_EECR, j, mask); + edma_shadow0_write_array(ecc, SH_ECR, j, mask); + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_write_array(ecc, EDMA_EMCR, j, mask); - edma_shadow0_write_array(ecc, SH_EECR, j, mask); - edma_shadow0_write_array(ecc, SH_ECR, j, mask); - edma_shadow0_write_array(ecc, SH_SECR, j, mask); - edma_write_array(ecc, EDMA_EMCR, j, mask); + /* clear possibly pending completion interrupt */ + edma_shadow0_write_array(ecc, SH_ICR, j, mask); - /* clear possibly pending completion interrupt */ - edma_shadow0_write_array(ecc, SH_ICR, j, mask); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); - dev_dbg(ecc->dev, "EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); - - /* REVISIT: consider guarding against inappropriate event - * chaining by overwriting with dummy_paramset. - */ - } + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ } /* * Temporarily disable EDMA hardware events on the specified channel, * preventing them from triggering new transfers */ -static void edma_pause(struct edma_cc *ecc, unsigned channel) +static void edma_pause(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < ecc->num_channels) { - unsigned int mask = BIT(channel & 0x1f); + int channel = EDMA_CHAN_SLOT(echan->ch_num); + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ecc, SH_EECR, channel >> 5, mask); - } + edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); } /* Re-enable EDMA hardware events on the specified channel. */ -static void edma_resume(struct edma_cc *ecc, unsigned channel) +static void edma_resume(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < ecc->num_channels) { - unsigned int mask = BIT(channel & 0x1f); + int channel = EDMA_CHAN_SLOT(echan->ch_num); + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ecc, SH_EESR, channel >> 5, mask); - } + edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); } -static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) +static void edma_trigger_channel(struct edma_chan *echan) { - unsigned int mask; - - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - mask = BIT(channel & 0x1f); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + unsigned int mask = BIT(channel & 0x1f); edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); - return 0; } -static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) +static void edma_clean_channel(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < ecc->num_channels) { - int j = (channel >> 5); - unsigned int mask = BIT(channel & 0x1f); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); - dev_dbg(ecc->dev, "EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); - edma_shadow0_write_array(ecc, SH_ECR, j, mask); - /* Clear the corresponding EMR bits */ - edma_write_array(ecc, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(ecc, SH_SECR, j, mask); - edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); - } + dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j)); + edma_shadow0_write_array(ecc, SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); } -/** - * edma_alloc_channel - allocate DMA channel and paired parameter RAM - * @ecc: pointer to edma_cc struct - * @channel: specific channel to allocate; negative for "any unmapped channel" - * @eventq_no: an EVENTQ_* constant, used to choose which Transfer - * Controller (TC) executes requests using this channel. Use - * EVENTQ_DEFAULT unless you really need a high priority queue. - * - * This allocates a DMA channel and its associated parameter RAM slot. - * The parameter RAM is initialized to hold a dummy transfer. - * - * Normal use is to pass a specific channel number as @channel, to make - * use of hardware events mapped to that channel. When the channel will - * be used only for software triggering or event chaining, channels not - * mapped to hardware events (or mapped to unused events) are preferable. - * - * DMA transfers start from a channel using edma_start(), or by - * chaining. When the transfer described in that channel's parameter RAM - * slot completes, that slot's data may be reloaded through a link. - * - * DMA errors are only reported to the @callback associated with the - * channel driving that transfer, but transfer completion callbacks can - * be sent to another channel under control of the TCC field in - * the option word of the transfer's parameter RAM set. Drivers must not - * use DMA transfer completion callbacks for channels they did not allocate. - * (The same applies to TCC codes used in transfer chaining.) - * - * Returns the number of the channel, else negative errno. - */ -static int edma_alloc_channel(struct edma_cc *ecc, int channel, +static int edma_alloc_channel(struct edma_chan *echan, enum dma_event_q eventq_no) { - int ret = 0; + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); if (!ecc->unused_chan_list_done) { /* @@ -823,86 +735,40 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, * used and clear them in the unused list, making the rest * available for ARM usage. */ - ret = bus_for_each_dev(&platform_bus_type, NULL, ecc, - prepare_unused_channel_list); + int ret = bus_for_each_dev(&platform_bus_type, NULL, ecc, + prepare_unused_channel_list); if (ret < 0) return ret; ecc->unused_chan_list_done = true; } - if (channel >= 0) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", - __func__, ecc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - } - - if (channel < 0) { - channel = find_next_bit(ecc->channel_unused, ecc->num_channels, - 0); - if (channel == ecc->num_channels) - return -EBUSY; - } else if (channel >= ecc->num_channels) { - return -EINVAL; - } - /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); /* ensure no events are pending */ - edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel)); + edma_stop(echan); - edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true); + edma_setup_interrupt(echan, true); - edma_map_dmach_to_queue(ecc, channel, eventq_no); + edma_map_dmach_to_queue(echan, eventq_no); - return EDMA_CTLR_CHAN(ecc->id, channel); + return 0; } -/** - * edma_free_channel - deallocate DMA channel - * @ecc: pointer to edma_cc struct - * @channel: dma channel returned from edma_alloc_channel() - * - * This deallocates the DMA channel and associated parameter RAM slot - * allocated by edma_alloc_channel(). - * - * Callers are responsible for ensuring the channel is inactive, and - * will not be reactivated by linking, chaining, or software calls to - * edma_start(). - */ -static void edma_free_channel(struct edma_cc *ecc, unsigned channel) +static void edma_free_channel(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel >= ecc->num_channels) - return; - + /* ensure no events are pending */ + edma_stop(echan); /* REVISIT should probably take out of shadow region 0 */ - edma_setup_interrupt(ecc, channel, false); + edma_setup_interrupt(echan, false); } /* Move channel to a specific event queue */ -static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, +static void edma_assign_channel_eventq(struct edma_chan *echan, enum dma_event_q eventq_no) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel >= ecc->num_channels) - return; + struct edma_cc *ecc = echan->ecc; /* default to low priority queue */ if (eventq_no == EVENTQ_DEFAULT) @@ -910,7 +776,7 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, if (eventq_no >= ecc->num_tc) return; - edma_map_dmach_to_queue(ecc, channel, eventq_no); + edma_map_dmach_to_queue(echan, eventq_no); } static inline struct edma_cc *to_edma_cc(struct dma_device *d) @@ -1011,19 +877,19 @@ static void edma_execute(struct edma_chan *echan) * transfers of MAX_NR_SG */ dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); - edma_clean_channel(ecc, echan->ch_num); - edma_stop(ecc, echan->ch_num); - edma_start(ecc, echan->ch_num); - edma_trigger_channel(ecc, echan->ch_num); + edma_clean_channel(echan); + edma_stop(echan); + edma_start(echan); + edma_trigger_channel(echan); echan->missed = 0; } else if (edesc->processed <= MAX_NR_SG) { dev_dbg(dev, "first transfer starting on channel %d\n", echan->ch_num); - edma_start(ecc, echan->ch_num); + edma_start(echan); } else { dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", echan->ch_num, edesc->processed); - edma_resume(ecc, echan->ch_num); + edma_resume(echan); } } @@ -1041,11 +907,10 @@ static int edma_terminate_all(struct dma_chan *chan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { - edma_stop(echan->ecc, echan->ch_num); + edma_stop(echan); /* Move the cyclic channel back to default queue */ if (echan->edesc->cyclic) - edma_assign_channel_eventq(echan->ecc, echan->ch_num, - EVENTQ_DEFAULT); + edma_assign_channel_eventq(echan, EVENTQ_DEFAULT); /* * free the running request descriptor * since it is not in any of the vdesc lists @@ -1082,7 +947,7 @@ static int edma_dma_pause(struct dma_chan *chan) if (!echan->edesc) return -EINVAL; - edma_pause(echan->ecc, echan->ch_num); + edma_pause(echan); return 0; } @@ -1090,7 +955,7 @@ static int edma_dma_resume(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - edma_resume(echan->ecc, echan->ch_num); + edma_resume(echan); return 0; } @@ -1548,14 +1413,13 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( } /* Place the cyclic channel to highest priority queue */ - edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_0); + edma_assign_channel_eventq(echan, EVENTQ_0); return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } static void edma_completion_handler(struct edma_chan *echan) { - struct edma_cc *ecc = echan->ecc; struct device *dev = echan->vchan.chan.device->dev; struct edma_desc *edesc = echan->edesc; @@ -1569,7 +1433,7 @@ static void edma_completion_handler(struct edma_chan *echan) return; } else if (edesc->processed == edesc->pset_nr) { edesc->residue = 0; - edma_stop(ecc, echan->ch_num); + edma_stop(echan); vchan_cookie_complete(&edesc->vdesc); echan->edesc = NULL; @@ -1579,7 +1443,7 @@ static void edma_completion_handler(struct edma_chan *echan) dev_dbg(dev, "Sub transfer completed on channel %d\n", echan->ch_num); - edma_pause(ecc, echan->ch_num); + edma_pause(echan); /* Update statistics for tx_status */ edesc->residue -= edesc->sg_len; @@ -1670,10 +1534,10 @@ static void edma_error_handler(struct edma_chan *echan) * missed, so its safe to issue it here. */ dev_dbg(dev, "Missed event, TRIGGERING\n"); - edma_clean_channel(ecc, echan->ch_num); - edma_stop(ecc, echan->ch_num); - edma_start(ecc, echan->ch_num); - edma_trigger_channel(ecc, echan->ch_num); + edma_clean_channel(echan); + edma_stop(echan); + edma_start(echan); + edma_trigger_channel(echan); } spin_unlock(&echan->vchan.lock); } @@ -1761,43 +1625,29 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) struct edma_chan *echan = to_edma_chan(chan); struct device *dev = chan->device->dev; int ret; - int a_ch_num; - LIST_HEAD(descs); - - a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, EVENTQ_DEFAULT); - - if (a_ch_num < 0) { - ret = -ENODEV; - goto err_no_chan; - } - if (a_ch_num != echan->ch_num) { - dev_err(dev, "failed to allocate requested channel %u:%u\n", - EDMA_CTLR(echan->ch_num), - EDMA_CHAN_SLOT(echan->ch_num)); - ret = -ENODEV; - goto err_wrong_chan; - } + ret = edma_alloc_channel(echan, EVENTQ_DEFAULT); + if (ret) + return ret; - echan->alloced = true; echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num); if (echan->slot[0] < 0) { dev_err(dev, "Entry slot allocation failed for channel %u\n", EDMA_CHAN_SLOT(echan->ch_num)); - goto err_wrong_chan; + goto err_slot; } /* Set up channel -> slot mapping for the entry slot */ - edma_set_chmap(echan->ecc, echan->ch_num, echan->slot[0]); + edma_set_chmap(echan, echan->slot[0]); + echan->alloced = true; dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); return 0; -err_wrong_chan: - edma_free_channel(echan->ecc, a_ch_num); -err_no_chan: +err_slot: + edma_free_channel(echan); return ret; } @@ -1808,7 +1658,7 @@ static void edma_free_chan_resources(struct dma_chan *chan) int i; /* Terminate transfers */ - edma_stop(echan->ecc, echan->ch_num); + edma_stop(echan); vchan_free_chan_resources(&echan->vchan); @@ -1821,11 +1671,11 @@ static void edma_free_chan_resources(struct dma_chan *chan) } /* Set entry slot to the dummy slot */ - edma_set_chmap(echan->ecc, echan->ch_num, echan->ecc->dummy_slot); + edma_set_chmap(echan, echan->ecc->dummy_slot); /* Free EDMA channel */ if (echan->alloced) { - edma_free_channel(echan->ecc, echan->ch_num); + edma_free_channel(echan); echan->alloced = false; } @@ -2279,13 +2129,6 @@ static int edma_probe(struct platform_device *pdev) return ecc->dummy_slot; } - for (i = 0; i < ecc->num_channels; i++) { - /* Assign all channels to the default queue */ - edma_map_dmach_to_queue(ecc, i, info->default_queue); - /* Set entry slot to the dummy slot */ - edma_set_chmap(ecc, i, ecc->dummy_slot); - } - queue_priority_mapping = info->queue_priority_mapping; /* Event queue priority mapping */ @@ -2309,6 +2152,14 @@ static int edma_probe(struct platform_device *pdev) edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); + for (i = 0; i < ecc->num_channels; i++) { + /* Assign all channels to the default queue */ + edma_map_dmach_to_queue(&ecc->slave_chans[i], + info->default_queue); + /* Set entry slot to the dummy slot */ + edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); + } + ret = dma_async_device_register(&ecc->dma_slave); if (ret) goto err_reg1; @@ -2360,11 +2211,10 @@ static int edma_pm_resume(struct device *dev) edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f)); - edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i), - true); + edma_setup_interrupt(&echan[i], true); /* Set up channel -> slot mapping for the entry slot */ - edma_set_chmap(ecc, echan[i].ch_num, echan[i].slot[0]); + edma_set_chmap(&echan[i], echan[i].slot[0]); } } -- cgit v1.2.3 From d9c345d18a8df5a5427cca80d2b9d981468ef270 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:02 +0300 Subject: dmaengine: edma: Correct PaRAM access function names (_parm_ to _param_) These inline functions are designed to modify parts of the PaRAM in eDMA. Change the names accordingly. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index a64befecf477..051a7c4593d4 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -349,32 +349,32 @@ static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); } -static inline unsigned int edma_parm_read(struct edma_cc *ecc, int offset, - int param_no) +static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset, + int param_no) { return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); } -static inline void edma_parm_write(struct edma_cc *ecc, int offset, - int param_no, unsigned val) +static inline void edma_param_write(struct edma_cc *ecc, int offset, + int param_no, unsigned val) { edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); } -static inline void edma_parm_modify(struct edma_cc *ecc, int offset, - int param_no, unsigned and, unsigned or) +static inline void edma_param_modify(struct edma_cc *ecc, int offset, + int param_no, unsigned and, unsigned or) { edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); } -static inline void edma_parm_and(struct edma_cc *ecc, int offset, int param_no, - unsigned and) +static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no, + unsigned and) { edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); } -static inline void edma_parm_or(struct edma_cc *ecc, int offset, int param_no, - unsigned or) +static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, + unsigned or) { edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); } @@ -594,8 +594,8 @@ static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) if (from >= ecc->num_slots || to >= ecc->num_slots) return; - edma_parm_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, - PARM_OFFSET(to)); + edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); } /** -- cgit v1.2.3 From f9425deb662ac07099ec151ffb4791eef48e9d83 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:03 +0300 Subject: dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventq edma_assign_channel_eventq() is a wrapper around edma_map_dmach_to_queue() We can merge the content of the later so we will have only one function to be used for mapping channels to given eventq Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 56 +++++++++++++++++++++--------------------------------- 1 file changed, 22 insertions(+), 34 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 051a7c4593d4..eaf1f9e4bde0 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -391,22 +391,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p) clear_bit(offset + (len - 1), p); } -static void edma_map_dmach_to_queue(struct edma_chan *echan, - enum dma_event_q queue_no) -{ - struct edma_cc *ecc = echan->ecc; - int channel = EDMA_CHAN_SLOT(echan->ch_num); - int bit = (channel & 0x7) * 4; - - /* default to low priority queue */ - if (queue_no == EVENTQ_DEFAULT) - queue_no = ecc->default_queue; - - queue_no &= 7; - edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), - queue_no << bit); -} - static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, int priority) { @@ -723,6 +707,25 @@ static void edma_clean_channel(struct edma_chan *echan) edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); } +/* Move channel to a specific event queue */ +static void edma_assign_channel_eventq(struct edma_chan *echan, + enum dma_event_q eventq_no) +{ + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int bit = (channel & 0x7) * 4; + + /* default to low priority queue */ + if (eventq_no == EVENTQ_DEFAULT) + eventq_no = ecc->default_queue; + if (eventq_no >= ecc->num_tc) + return; + + eventq_no &= 7; + edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), + eventq_no << bit); +} + static int edma_alloc_channel(struct edma_chan *echan, enum dma_event_q eventq_no) { @@ -751,7 +754,7 @@ static int edma_alloc_channel(struct edma_chan *echan, edma_setup_interrupt(echan, true); - edma_map_dmach_to_queue(echan, eventq_no); + edma_assign_channel_eventq(echan, eventq_no); return 0; } @@ -764,21 +767,6 @@ static void edma_free_channel(struct edma_chan *echan) edma_setup_interrupt(echan, false); } -/* Move channel to a specific event queue */ -static void edma_assign_channel_eventq(struct edma_chan *echan, - enum dma_event_q eventq_no) -{ - struct edma_cc *ecc = echan->ecc; - - /* default to low priority queue */ - if (eventq_no == EVENTQ_DEFAULT) - eventq_no = ecc->default_queue; - if (eventq_no >= ecc->num_tc) - return; - - edma_map_dmach_to_queue(echan, eventq_no); -} - static inline struct edma_cc *to_edma_cc(struct dma_device *d) { return container_of(d, struct edma_cc, dma_slave); @@ -2154,8 +2142,8 @@ static int edma_probe(struct platform_device *pdev) for (i = 0; i < ecc->num_channels; i++) { /* Assign all channels to the default queue */ - edma_map_dmach_to_queue(&ecc->slave_chans[i], - info->default_queue); + edma_assign_channel_eventq(&ecc->slave_chans[i], + info->default_queue); /* Set entry slot to the dummy slot */ edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); } -- cgit v1.2.3 From 633e42b8c5465acf03671be7bd2866c486816596 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:04 +0300 Subject: dmaengine: edma: Get qDMA channel information from HW also Query the number of qDMA channels from CCCFG register. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index eaf1f9e4bde0..ea851ab05c8e 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -107,6 +107,7 @@ /* CCCFG register */ #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ +#define GET_NUM_QDMACH(x) (x & 0x70 >> 4) /* bits 4-6 */ #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ @@ -220,6 +221,7 @@ struct edma_cc { /* eDMA3 resource information */ unsigned num_channels; + unsigned num_qchannels; unsigned num_region; unsigned num_slots; unsigned num_tc; @@ -1819,6 +1821,9 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, value = GET_NUM_DMACH(cccfg); ecc->num_channels = BIT(value + 1); + value = GET_NUM_QDMACH(cccfg); + ecc->num_qchannels = value * 2; + value = GET_NUM_PAENTRY(cccfg); ecc->num_slots = BIT(value + 4); @@ -1830,6 +1835,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); dev_dbg(dev, "num_region: %u\n", ecc->num_region); dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); + dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); -- cgit v1.2.3 From 02f77ef1197bd0acde8c0b7ed2b4dee7da7bcbf6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:05 +0300 Subject: dmaengine: edma: Refactor the dma device and channel struct initialization Move all code under one function to do the dma device and eDMA channel related setup so they are not scattered around the driver. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 79 +++++++++++++++++++++++++----------------------------- 1 file changed, 37 insertions(+), 42 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index ea851ab05c8e..e1b0e6864f27 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1756,18 +1756,49 @@ static enum dma_status edma_tx_status(struct dma_chan *chan, return ret; } -static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma, - struct edma_chan *echans) +#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) + +static void edma_dma_init(struct edma_cc *ecc) { + struct dma_device *ddev = &ecc->dma_slave; int i, j; + dma_cap_zero(ddev->cap_mask); + dma_cap_set(DMA_SLAVE, ddev->cap_mask); + dma_cap_set(DMA_CYCLIC, ddev->cap_mask); + dma_cap_set(DMA_MEMCPY, ddev->cap_mask); + + ddev->device_prep_slave_sg = edma_prep_slave_sg; + ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; + ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; + ddev->device_alloc_chan_resources = edma_alloc_chan_resources; + ddev->device_free_chan_resources = edma_free_chan_resources; + ddev->device_issue_pending = edma_issue_pending; + ddev->device_tx_status = edma_tx_status; + ddev->device_config = edma_slave_config; + ddev->device_pause = edma_dma_pause; + ddev->device_resume = edma_dma_resume; + ddev->device_terminate_all = edma_terminate_all; + + ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; + ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; + ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + + ddev->dev = ecc->dev; + + INIT_LIST_HEAD(&ddev->channels); + for (i = 0; i < ecc->num_channels; i++) { - struct edma_chan *echan = &echans[i]; + struct edma_chan *echan = &ecc->slave_chans[i]; echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); echan->ecc = ecc; echan->vchan.desc_free = edma_desc_free; - vchan_init(&echan->vchan, dma); + vchan_init(&echan->vchan, ddev); INIT_LIST_HEAD(&echan->node); for (j = 0; j < EDMA_MAX_SLOTS; j++) @@ -1775,36 +1806,6 @@ static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma, } } -#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) - -static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, - struct device *dev) -{ - dma->device_prep_slave_sg = edma_prep_slave_sg; - dma->device_prep_dma_cyclic = edma_prep_dma_cyclic; - dma->device_prep_dma_memcpy = edma_prep_dma_memcpy; - dma->device_alloc_chan_resources = edma_alloc_chan_resources; - dma->device_free_chan_resources = edma_free_chan_resources; - dma->device_issue_pending = edma_issue_pending; - dma->device_tx_status = edma_tx_status; - dma->device_config = edma_slave_config; - dma->device_pause = edma_dma_pause; - dma->device_resume = edma_dma_resume; - dma->device_terminate_all = edma_terminate_all; - - dma->src_addr_widths = EDMA_DMA_BUSWIDTHS; - dma->dst_addr_widths = EDMA_DMA_BUSWIDTHS; - dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); - dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; - - dma->dev = dev; - - INIT_LIST_HEAD(&dma->channels); -} - static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, struct edma_cc *ecc) { @@ -2137,14 +2138,8 @@ static int edma_probe(struct platform_device *pdev) } ecc->info = info; - dma_cap_zero(ecc->dma_slave.cap_mask); - dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); - dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); - dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask); - - edma_dma_init(ecc, &ecc->dma_slave, dev); - - edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); + /* Init the dma device and channels */ + edma_dma_init(ecc); for (i = 0; i < ecc->num_channels; i++) { /* Assign all channels to the default queue */ -- cgit v1.2.3 From 56c7b749965947af45efaf8a7021a1f86d4ce4d8 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:06 +0300 Subject: dmaengine: edma: Do not allocate memory for edma_rsv_info in case of DT boot The channel/slot reservation is not supported when booted with DT so there is not need to allocate memory. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index e1b0e6864f27..c1b8bb09c221 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1926,12 +1926,6 @@ static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata) int ret = 0; struct property *prop; size_t sz; - struct edma_rsv_info *rsv_info; - - rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); - if (!rsv_info) - return -ENOMEM; - pdata->rsv = rsv_info; prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); if (prop) -- cgit v1.2.3 From 966a87b5962ed0d058e93809ae310fa542a69c8e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:07 +0300 Subject: dmaengine: edma: Merge the of parsing functions Instead of nesting functions just merge them since the resulting function is still small and readable. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index c1b8bb09c221..d4d71e60da1b 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1921,31 +1921,23 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, return 0; } -static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata) -{ - int ret = 0; - struct property *prop; - size_t sz; - - prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); - if (prop) - ret = edma_xbar_event_map(dev, pdata, sz); - - return ret; -} - static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) { struct edma_soc_info *info; + struct property *prop; + size_t sz; int ret; info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); if (!info) return ERR_PTR(-ENOMEM); - ret = edma_of_parse_dt(dev, info); - if (ret) - return ERR_PTR(ret); + prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); + if (prop) { + ret = edma_xbar_event_map(dev, info, sz); + if (ret) + return ERR_PTR(ret); + } return info; } -- cgit v1.2.3 From 42dbdcc6bf965997c088caff2a8be7f9bf44f701 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:08 +0300 Subject: dmaengine: ti-dma-crossbar: Add support for crossbar on AM33xx/AM43xx The DMA event crossbar on AM33xx/AM43xx is different from the one found in DRA7x family. Instead of a single event crossbar it has 64 identical mux attached to each eDMA event line. When the 0 event mux is selected, the default mapped event is going to be routed to the corresponding eDMA event line. If different mux is selected, then the selected event is going to be routed to the given eDMA event. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/ti-dma-crossbar.c | 251 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 221 insertions(+), 30 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c index 5cce8c9d0026..a415edbe61b1 100644 --- a/drivers/dma/ti-dma-crossbar.c +++ b/drivers/dma/ti-dma-crossbar.c @@ -17,13 +17,184 @@ #include #include -#define TI_XBAR_OUTPUTS 127 -#define TI_XBAR_INPUTS 256 +#define TI_XBAR_DRA7 0 +#define TI_XBAR_AM335X 1 + +static const struct of_device_id ti_dma_xbar_match[] = { + { + .compatible = "ti,dra7-dma-crossbar", + .data = (void *)TI_XBAR_DRA7, + }, + { + .compatible = "ti,am335x-edma-crossbar", + .data = (void *)TI_XBAR_AM335X, + }, + {}, +}; + +/* Crossbar on AM335x/AM437x family */ +#define TI_AM335X_XBAR_LINES 64 + +struct ti_am335x_xbar_data { + void __iomem *iomem; + + struct dma_router dmarouter; + + u32 xbar_events; /* maximum number of events to select in xbar */ + u32 dma_requests; /* number of DMA requests on eDMA */ +}; + +struct ti_am335x_xbar_map { + u16 dma_line; + u16 mux_val; +}; + +static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u16 val) +{ + writeb_relaxed(val & 0x1f, iomem + event); +} + +static void ti_am335x_xbar_free(struct device *dev, void *route_data) +{ + struct ti_am335x_xbar_data *xbar = dev_get_drvdata(dev); + struct ti_am335x_xbar_map *map = route_data; + + dev_dbg(dev, "Unmapping XBAR event %u on channel %u\n", + map->mux_val, map->dma_line); + + ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); + kfree(map); +} + +static void *ti_am335x_xbar_route_allocate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); + struct ti_am335x_xbar_data *xbar = platform_get_drvdata(pdev); + struct ti_am335x_xbar_map *map; + + if (dma_spec->args_count != 3) + return ERR_PTR(-EINVAL); + + if (dma_spec->args[2] >= xbar->xbar_events) { + dev_err(&pdev->dev, "Invalid XBAR event number: %d\n", + dma_spec->args[2]); + return ERR_PTR(-EINVAL); + } + + if (dma_spec->args[0] >= xbar->dma_requests) { + dev_err(&pdev->dev, "Invalid DMA request line number: %d\n", + dma_spec->args[0]); + return ERR_PTR(-EINVAL); + } + + /* The of_node_put() will be done in the core for the node */ + dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0); + if (!dma_spec->np) { + dev_err(&pdev->dev, "Can't get DMA master\n"); + return ERR_PTR(-EINVAL); + } + + map = kzalloc(sizeof(*map), GFP_KERNEL); + if (!map) { + of_node_put(dma_spec->np); + return ERR_PTR(-ENOMEM); + } + + map->dma_line = (u16)dma_spec->args[0]; + map->mux_val = (u16)dma_spec->args[2]; + + dma_spec->args[2] = 0; + dma_spec->args_count = 2; + + dev_dbg(&pdev->dev, "Mapping XBAR event%u to DMA%u\n", + map->mux_val, map->dma_line); + + ti_am335x_xbar_write(xbar->iomem, map->dma_line, map->mux_val); + + return map; +} + +static const struct of_device_id ti_am335x_master_match[] = { + { .compatible = "ti,edma3-tpcc", }, + {}, +}; + +static int ti_am335x_xbar_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + const struct of_device_id *match; + struct device_node *dma_node; + struct ti_am335x_xbar_data *xbar; + struct resource *res; + void __iomem *iomem; + int i, ret; + + if (!node) + return -ENODEV; + + xbar = devm_kzalloc(&pdev->dev, sizeof(*xbar), GFP_KERNEL); + if (!xbar) + return -ENOMEM; + + dma_node = of_parse_phandle(node, "dma-masters", 0); + if (!dma_node) { + dev_err(&pdev->dev, "Can't get DMA master node\n"); + return -ENODEV; + } + + match = of_match_node(ti_am335x_master_match, dma_node); + if (!match) { + dev_err(&pdev->dev, "DMA master is not supported\n"); + return -EINVAL; + } + + if (of_property_read_u32(dma_node, "dma-requests", + &xbar->dma_requests)) { + dev_info(&pdev->dev, + "Missing XBAR output information, using %u.\n", + TI_AM335X_XBAR_LINES); + xbar->dma_requests = TI_AM335X_XBAR_LINES; + } + of_node_put(dma_node); + + if (of_property_read_u32(node, "dma-requests", &xbar->xbar_events)) { + dev_info(&pdev->dev, + "Missing XBAR input information, using %u.\n", + TI_AM335X_XBAR_LINES); + xbar->xbar_events = TI_AM335X_XBAR_LINES; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + iomem = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(iomem)) + return PTR_ERR(iomem); + + xbar->iomem = iomem; + + xbar->dmarouter.dev = &pdev->dev; + xbar->dmarouter.route_free = ti_am335x_xbar_free; + + platform_set_drvdata(pdev, xbar); + + /* Reset the crossbar */ + for (i = 0; i < xbar->dma_requests; i++) + ti_am335x_xbar_write(xbar->iomem, i, 0); + + ret = of_dma_router_register(node, ti_am335x_xbar_route_allocate, + &xbar->dmarouter); + + return ret; +} + +/* Crossbar on DRA7xx family */ +#define TI_DRA7_XBAR_OUTPUTS 127 +#define TI_DRA7_XBAR_INPUTS 256 #define TI_XBAR_EDMA_OFFSET 0 #define TI_XBAR_SDMA_OFFSET 1 -struct ti_dma_xbar_data { +struct ti_dra7_xbar_data { void __iomem *iomem; struct dma_router dmarouter; @@ -35,35 +206,35 @@ struct ti_dma_xbar_data { u32 dma_offset; }; -struct ti_dma_xbar_map { +struct ti_dra7_xbar_map { u16 xbar_in; int xbar_out; }; -static inline void ti_dma_xbar_write(void __iomem *iomem, int xbar, u16 val) +static inline void ti_dra7_xbar_write(void __iomem *iomem, int xbar, u16 val) { writew_relaxed(val, iomem + (xbar * 2)); } -static void ti_dma_xbar_free(struct device *dev, void *route_data) +static void ti_dra7_xbar_free(struct device *dev, void *route_data) { - struct ti_dma_xbar_data *xbar = dev_get_drvdata(dev); - struct ti_dma_xbar_map *map = route_data; + struct ti_dra7_xbar_data *xbar = dev_get_drvdata(dev); + struct ti_dra7_xbar_map *map = route_data; dev_dbg(dev, "Unmapping XBAR%u (was routed to %d)\n", map->xbar_in, map->xbar_out); - ti_dma_xbar_write(xbar->iomem, map->xbar_out, xbar->safe_val); + ti_dra7_xbar_write(xbar->iomem, map->xbar_out, xbar->safe_val); idr_remove(&xbar->map_idr, map->xbar_out); kfree(map); } -static void *ti_dma_xbar_route_allocate(struct of_phandle_args *dma_spec, - struct of_dma *ofdma) +static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) { struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); - struct ti_dma_xbar_data *xbar = platform_get_drvdata(pdev); - struct ti_dma_xbar_map *map; + struct ti_dra7_xbar_data *xbar = platform_get_drvdata(pdev); + struct ti_dra7_xbar_map *map; if (dma_spec->args[0] >= xbar->xbar_requests) { dev_err(&pdev->dev, "Invalid XBAR request number: %d\n", @@ -93,12 +264,12 @@ static void *ti_dma_xbar_route_allocate(struct of_phandle_args *dma_spec, dev_dbg(&pdev->dev, "Mapping XBAR%u to DMA%d\n", map->xbar_in, map->xbar_out); - ti_dma_xbar_write(xbar->iomem, map->xbar_out, map->xbar_in); + ti_dra7_xbar_write(xbar->iomem, map->xbar_out, map->xbar_in); return map; } -static const struct of_device_id ti_dma_master_match[] = { +static const struct of_device_id ti_dra7_master_match[] = { { .compatible = "ti,omap4430-sdma", .data = (void *)TI_XBAR_SDMA_OFFSET, @@ -110,12 +281,12 @@ static const struct of_device_id ti_dma_master_match[] = { {}, }; -static int ti_dma_xbar_probe(struct platform_device *pdev) +static int ti_dra7_xbar_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; const struct of_device_id *match; struct device_node *dma_node; - struct ti_dma_xbar_data *xbar; + struct ti_dra7_xbar_data *xbar; struct resource *res; u32 safe_val; void __iomem *iomem; @@ -136,7 +307,7 @@ static int ti_dma_xbar_probe(struct platform_device *pdev) return -ENODEV; } - match = of_match_node(ti_dma_master_match, dma_node); + match = of_match_node(ti_dra7_master_match, dma_node); if (!match) { dev_err(&pdev->dev, "DMA master is not supported\n"); return -EINVAL; @@ -146,16 +317,16 @@ static int ti_dma_xbar_probe(struct platform_device *pdev) &xbar->dma_requests)) { dev_info(&pdev->dev, "Missing XBAR output information, using %u.\n", - TI_XBAR_OUTPUTS); - xbar->dma_requests = TI_XBAR_OUTPUTS; + TI_DRA7_XBAR_OUTPUTS); + xbar->dma_requests = TI_DRA7_XBAR_OUTPUTS; } of_node_put(dma_node); if (of_property_read_u32(node, "dma-requests", &xbar->xbar_requests)) { dev_info(&pdev->dev, "Missing XBAR input information, using %u.\n", - TI_XBAR_INPUTS); - xbar->xbar_requests = TI_XBAR_INPUTS; + TI_DRA7_XBAR_INPUTS); + xbar->xbar_requests = TI_DRA7_XBAR_INPUTS; } if (!of_property_read_u32(node, "ti,dma-safe-map", &safe_val)) @@ -169,30 +340,50 @@ static int ti_dma_xbar_probe(struct platform_device *pdev) xbar->iomem = iomem; xbar->dmarouter.dev = &pdev->dev; - xbar->dmarouter.route_free = ti_dma_xbar_free; + xbar->dmarouter.route_free = ti_dra7_xbar_free; xbar->dma_offset = (u32)match->data; platform_set_drvdata(pdev, xbar); /* Reset the crossbar */ for (i = 0; i < xbar->dma_requests; i++) - ti_dma_xbar_write(xbar->iomem, i, xbar->safe_val); + ti_dra7_xbar_write(xbar->iomem, i, xbar->safe_val); - ret = of_dma_router_register(node, ti_dma_xbar_route_allocate, + ret = of_dma_router_register(node, ti_dra7_xbar_route_allocate, &xbar->dmarouter); if (ret) { /* Restore the defaults for the crossbar */ for (i = 0; i < xbar->dma_requests; i++) - ti_dma_xbar_write(xbar->iomem, i, i); + ti_dra7_xbar_write(xbar->iomem, i, i); } return ret; } -static const struct of_device_id ti_dma_xbar_match[] = { - { .compatible = "ti,dra7-dma-crossbar" }, - {}, -}; +static int ti_dma_xbar_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + int ret; + + match = of_match_node(ti_dma_xbar_match, pdev->dev.of_node); + if (unlikely(!match)) + return -EINVAL; + + switch ((u32)match->data) { + case TI_XBAR_DRA7: + ret = ti_dra7_xbar_probe(pdev); + break; + case TI_XBAR_AM335X: + ret = ti_am335x_xbar_probe(pdev); + break; + default: + dev_err(&pdev->dev, "Unsupported crossbar\n"); + ret = -ENODEV; + break; + } + + return ret; +} static struct platform_driver ti_dma_xbar_driver = { .driver = { -- cgit v1.2.3 From f7c7cae94832fc09ccff080b4cc2358ac11e2150 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:09 +0300 Subject: dmaengine: Kconfig: edma: Select TI_DMA_CROSSBAR in case of ARCH_OMAP Since the crossbar is needed for eDMA when it is used on OMAP like platforms (am335x/am437x and later DRA7xx), select the crossbar to be built if ARCH_OMAP is set. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/dma') diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 992efc8e465e..6a388a7c6429 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -486,6 +486,7 @@ config TI_EDMA depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE select DMA_ENGINE select DMA_VIRTUAL_CHANNELS + select TI_DMA_CROSSBAR if ARCH_OMAP default n help Enable support for the TI EDMA controller. This DMA -- cgit v1.2.3 From 1be5336bc7ba050ee07d352643bf4c01c513553c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:10 +0300 Subject: dmaengine: edma: New device tree binding With the old binding and driver architecture we had many issues: No way to assign eDMA channels to event queues, thus not able to tune the system by moving specific DMA channels to low/high priority servicing. We moved the cyclic channels to high priority within the code, but that was just a workaround to this issue. Memcopy was fundamentally broken: even if the driver scanned the DT/devices in the booted system for direct DMA users (which is not effective when the events are going through a crossbar) and created a map of 'used' channels, this information was not really usable. Since via dmaengien API the eDMA driver will be called with _some_ channel number, we would try to request this channel when any channel is requested for memcpy. By luck we got channel which is not used by any device most of the time so things worked, but if a device would have been using the given channel, but not requested it, the memcpy channel would have been waiting for HW event. The old code had the am33xx/am43xx DMA event router handling embedded. This should have been done in a separate driver since it is not part of the actual eDMA IP. There were no way to 'lock' PaRAM slots to be used by the DSP for example when booting with DT. In DT boot the edma node used more than one hwmod which is not a good practice and the kernel prints warning because of this. With the new bindings and the changes in the driver we can: - No regression with Legacy binding and non DT boot - DMA channels can be assigned to any TC (to set priority) - PaRAM slots can be reserved for other cores to use - Dynamic power management for CC and TCs, if only TC0 is used all other TC can be powered down for example Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 486 +++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 340 insertions(+), 146 deletions(-) (limited to 'drivers/dma') diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d4d71e60da1b..31722d436a42 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -201,13 +201,20 @@ struct edma_desc { struct edma_cc; +struct edma_tc { + struct device_node *node; + u16 id; +}; + struct edma_chan { struct virt_dma_chan vchan; struct list_head node; struct edma_desc *edesc; struct edma_cc *ecc; + struct edma_tc *tc; int ch_num; bool alloced; + bool hw_triggered; int slot[EDMA_MAX_SLOTS]; int missed; struct dma_slave_config cfg; @@ -218,6 +225,7 @@ struct edma_cc { struct edma_soc_info *info; void __iomem *base; int id; + bool legacy_mode; /* eDMA3 resource information */ unsigned num_channels; @@ -228,20 +236,16 @@ struct edma_cc { bool chmap_exist; enum dma_event_q default_queue; - bool unused_chan_list_done; - /* The slot_inuse bit for each PaRAM slot is clear unless the - * channel is in use ... by ARM or DSP, for QDMA, or whatever. + /* + * The slot_inuse bit for each PaRAM slot is clear unless the slot is + * in use by Linux or if it is allocated to be used by DSP. */ unsigned long *slot_inuse; - /* The channel_unused bit for each channel is clear unless - * it is not being used on this platform. It uses a bit - * of SOC-specific initialization code. - */ - unsigned long *channel_unused; - struct dma_device dma_slave; + struct dma_device *dma_memcpy; struct edma_chan *slave_chans; + struct edma_tc *tc_list; int dummy_slot; }; @@ -251,8 +255,17 @@ static const struct edmacc_param dummy_paramset = { .ccnt = 1, }; +#define EDMA_BINDING_LEGACY 0 +#define EDMA_BINDING_TPCC 1 static const struct of_device_id edma_of_ids[] = { - { .compatible = "ti,edma3", }, + { + .compatible = "ti,edma3", + .data = (void *)EDMA_BINDING_LEGACY, + }, + { + .compatible = "ti,edma3-tpcc", + .data = (void *)EDMA_BINDING_TPCC, + }, {} }; @@ -412,60 +425,6 @@ static void edma_set_chmap(struct edma_chan *echan, int slot) } } -static int prepare_unused_channel_list(struct device *dev, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - struct edma_cc *ecc = data; - int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0); - int dma_req_max = dma_req_min + ecc->num_channels; - int i, count; - struct of_phandle_args dma_spec; - - if (dev->of_node) { - struct platform_device *dma_pdev; - - count = of_property_count_strings(dev->of_node, "dma-names"); - if (count < 0) - return 0; - for (i = 0; i < count; i++) { - if (of_parse_phandle_with_args(dev->of_node, "dmas", - "#dma-cells", i, - &dma_spec)) - continue; - - if (!of_match_node(edma_of_ids, dma_spec.np)) { - of_node_put(dma_spec.np); - continue; - } - - dma_pdev = of_find_device_by_node(dma_spec.np); - if (&dma_pdev->dev != ecc->dev) - continue; - - clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), - ecc->channel_unused); - of_node_put(dma_spec.np); - } - return 0; - } - - /* For non-OF case */ - for (i = 0; i < pdev->num_resources; i++) { - struct resource *res = &pdev->resource[i]; - int dma_req; - - if (!(res->flags & IORESOURCE_DMA)) - continue; - - dma_req = (int)res->start; - if (dma_req >= dma_req_min && dma_req < dma_req_max) - clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - ecc->channel_unused); - } - - return 0; -} - static void edma_setup_interrupt(struct edma_chan *echan, bool enable) { struct edma_cc *ecc = echan->ecc; @@ -617,7 +576,7 @@ static void edma_start(struct edma_chan *echan) int j = (channel >> 5); unsigned int mask = BIT(channel & 0x1f); - if (test_bit(channel, ecc->channel_unused)) { + if (!echan->hw_triggered) { /* EDMA channels without event association */ dev_dbg(ecc->dev, "ESR%d %08x\n", j, edma_shadow0_read_array(ecc, SH_ESR, j)); @@ -734,20 +693,6 @@ static int edma_alloc_channel(struct edma_chan *echan, struct edma_cc *ecc = echan->ecc; int channel = EDMA_CHAN_SLOT(echan->ch_num); - if (!ecc->unused_chan_list_done) { - /* - * Scan all the platform devices to find out the EDMA channels - * used and clear them in the unused list, making the rest - * available for ARM usage. - */ - int ret = bus_for_each_dev(&platform_bus_type, NULL, ecc, - prepare_unused_channel_list); - if (ret < 0) - return ret; - - ecc->unused_chan_list_done = true; - } - /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); @@ -899,7 +844,7 @@ static int edma_terminate_all(struct dma_chan *chan) if (echan->edesc) { edma_stop(echan); /* Move the cyclic channel back to default queue */ - if (echan->edesc->cyclic) + if (!echan->tc && echan->edesc->cyclic) edma_assign_channel_eventq(echan, EVENTQ_DEFAULT); /* * free the running request descriptor @@ -1403,7 +1348,8 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( } /* Place the cyclic channel to highest priority queue */ - edma_assign_channel_eventq(echan, EVENTQ_0); + if (!echan->tc) + edma_assign_channel_eventq(echan, EVENTQ_0); return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } @@ -1609,18 +1555,54 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) return IRQ_HANDLED; } +static void edma_tc_set_pm_state(struct edma_tc *tc, bool enable) +{ + struct platform_device *tc_pdev; + int ret; + + if (!tc) + return; + + tc_pdev = of_find_device_by_node(tc->node); + if (!tc_pdev) { + pr_err("%s: TPTC device is not found\n", __func__); + return; + } + if (!pm_runtime_enabled(&tc_pdev->dev)) + pm_runtime_enable(&tc_pdev->dev); + + if (enable) + ret = pm_runtime_get_sync(&tc_pdev->dev); + else + ret = pm_runtime_put_sync(&tc_pdev->dev); + + if (ret < 0) + pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__, + enable ? "get" : "put", dev_name(&tc_pdev->dev)); +} + /* Alloc channel resources */ static int edma_alloc_chan_resources(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - struct device *dev = chan->device->dev; + struct edma_cc *ecc = echan->ecc; + struct device *dev = ecc->dev; + enum dma_event_q eventq_no = EVENTQ_DEFAULT; int ret; - ret = edma_alloc_channel(echan, EVENTQ_DEFAULT); + if (echan->tc) { + eventq_no = echan->tc->id; + } else if (ecc->tc_list) { + /* memcpy channel */ + echan->tc = &ecc->tc_list[ecc->info->default_queue]; + eventq_no = echan->tc->id; + } + + ret = edma_alloc_channel(echan, eventq_no); if (ret) return ret; - echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num); + echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); if (echan->slot[0] < 0) { dev_err(dev, "Entry slot allocation failed for channel %u\n", EDMA_CHAN_SLOT(echan->ch_num)); @@ -1631,8 +1613,11 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) edma_set_chmap(echan, echan->slot[0]); echan->alloced = true; - dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, - EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); + dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n", + EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id, + echan->hw_triggered ? "HW" : "SW"); + + edma_tc_set_pm_state(echan->tc, true); return 0; @@ -1645,6 +1630,7 @@ err_slot: static void edma_free_chan_resources(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); + struct device *dev = echan->ecc->dev; int i; /* Terminate transfers */ @@ -1669,7 +1655,12 @@ static void edma_free_chan_resources(struct dma_chan *chan) echan->alloced = false; } - dev_dbg(chan->device->dev, "freeing channel for %u\n", echan->ch_num); + edma_tc_set_pm_state(echan->tc, false); + echan->tc = NULL; + echan->hw_triggered = false; + + dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n", + EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id); } /* Send pending descriptor to hardware */ @@ -1756,41 +1747,90 @@ static enum dma_status edma_tx_status(struct dma_chan *chan, return ret; } +static bool edma_is_memcpy_channel(int ch_num, u16 *memcpy_channels) +{ + s16 *memcpy_ch = memcpy_channels; + + if (!memcpy_channels) + return false; + while (*memcpy_ch != -1) { + if (*memcpy_ch == ch_num) + return true; + memcpy_ch++; + } + return false; +} + #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) -static void edma_dma_init(struct edma_cc *ecc) +static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) { - struct dma_device *ddev = &ecc->dma_slave; + struct dma_device *s_ddev = &ecc->dma_slave; + struct dma_device *m_ddev = NULL; + s16 *memcpy_channels = ecc->info->memcpy_channels; int i, j; - dma_cap_zero(ddev->cap_mask); - dma_cap_set(DMA_SLAVE, ddev->cap_mask); - dma_cap_set(DMA_CYCLIC, ddev->cap_mask); - dma_cap_set(DMA_MEMCPY, ddev->cap_mask); + dma_cap_zero(s_ddev->cap_mask); + dma_cap_set(DMA_SLAVE, s_ddev->cap_mask); + dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask); + if (ecc->legacy_mode && !memcpy_channels) { + dev_warn(ecc->dev, + "Legacy memcpy is enabled, things might not work\n"); - ddev->device_prep_slave_sg = edma_prep_slave_sg; - ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; - ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; - ddev->device_alloc_chan_resources = edma_alloc_chan_resources; - ddev->device_free_chan_resources = edma_free_chan_resources; - ddev->device_issue_pending = edma_issue_pending; - ddev->device_tx_status = edma_tx_status; - ddev->device_config = edma_slave_config; - ddev->device_pause = edma_dma_pause; - ddev->device_resume = edma_dma_resume; - ddev->device_terminate_all = edma_terminate_all; - - ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; - ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; - ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); - ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; - - ddev->dev = ecc->dev; + dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask); + s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; + s_ddev->directions = BIT(DMA_MEM_TO_MEM); + } - INIT_LIST_HEAD(&ddev->channels); + s_ddev->device_prep_slave_sg = edma_prep_slave_sg; + s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; + s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; + s_ddev->device_free_chan_resources = edma_free_chan_resources; + s_ddev->device_issue_pending = edma_issue_pending; + s_ddev->device_tx_status = edma_tx_status; + s_ddev->device_config = edma_slave_config; + s_ddev->device_pause = edma_dma_pause; + s_ddev->device_resume = edma_dma_resume; + s_ddev->device_terminate_all = edma_terminate_all; + + s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; + s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; + s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); + s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + + s_ddev->dev = ecc->dev; + INIT_LIST_HEAD(&s_ddev->channels); + + if (memcpy_channels) { + m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); + ecc->dma_memcpy = m_ddev; + + dma_cap_zero(m_ddev->cap_mask); + dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask); + + m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; + m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; + m_ddev->device_free_chan_resources = edma_free_chan_resources; + m_ddev->device_issue_pending = edma_issue_pending; + m_ddev->device_tx_status = edma_tx_status; + m_ddev->device_config = edma_slave_config; + m_ddev->device_pause = edma_dma_pause; + m_ddev->device_resume = edma_dma_resume; + m_ddev->device_terminate_all = edma_terminate_all; + + m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; + m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; + m_ddev->directions = BIT(DMA_MEM_TO_MEM); + m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + + m_ddev->dev = ecc->dev; + INIT_LIST_HEAD(&m_ddev->channels); + } else if (!ecc->legacy_mode) { + dev_info(ecc->dev, "memcpy is disabled\n"); + } for (i = 0; i < ecc->num_channels; i++) { struct edma_chan *echan = &ecc->slave_chans[i]; @@ -1798,7 +1838,10 @@ static void edma_dma_init(struct edma_cc *ecc) echan->ecc = ecc; echan->vchan.desc_free = edma_desc_free; - vchan_init(&echan->vchan, ddev); + if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels)) + vchan_init(&echan->vchan, m_ddev); + else + vchan_init(&echan->vchan, s_ddev); INIT_LIST_HEAD(&echan->node); for (j = 0; j < EDMA_MAX_SLOTS; j++) @@ -1921,7 +1964,8 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, return 0; } -static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, + bool legacy_mode) { struct edma_soc_info *info; struct property *prop; @@ -1932,20 +1976,121 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) if (!info) return ERR_PTR(-ENOMEM); - prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); + if (legacy_mode) { + prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", + &sz); + if (prop) { + ret = edma_xbar_event_map(dev, info, sz); + if (ret) + return ERR_PTR(ret); + } + return info; + } + + /* Get the list of channels allocated to be used for memcpy */ + prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz); + if (prop) { + const char pname[] = "ti,edma-memcpy-channels"; + size_t nelm = sz / sizeof(s16); + s16 *memcpy_ch; + + memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s16), + GFP_KERNEL); + if (!memcpy_ch) + return ERR_PTR(-ENOMEM); + + ret = of_property_read_u16_array(dev->of_node, pname, + (u16 *)memcpy_ch, nelm); + if (ret) + return ERR_PTR(ret); + + memcpy_ch[nelm] = -1; + info->memcpy_channels = memcpy_ch; + } + + prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges", + &sz); if (prop) { - ret = edma_xbar_event_map(dev, info, sz); + const char pname[] = "ti,edma-reserved-slot-ranges"; + s16 (*rsv_slots)[2]; + size_t nelm = sz / sizeof(*rsv_slots); + struct edma_rsv_info *rsv_info; + + if (!nelm) + return info; + + rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL); + if (!rsv_info) + return ERR_PTR(-ENOMEM); + + rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots), + GFP_KERNEL); + if (!rsv_slots) + return ERR_PTR(-ENOMEM); + + ret = of_property_read_u16_array(dev->of_node, pname, + (u16 *)rsv_slots, nelm * 2); if (ret) return ERR_PTR(ret); + + rsv_slots[nelm][0] = -1; + rsv_slots[nelm][1] = -1; + info->rsv = rsv_info; + info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots; } return info; } + +static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct edma_cc *ecc = ofdma->of_dma_data; + struct dma_chan *chan = NULL; + struct edma_chan *echan; + int i; + + if (!ecc || dma_spec->args_count < 1) + return NULL; + + for (i = 0; i < ecc->num_channels; i++) { + echan = &ecc->slave_chans[i]; + if (echan->ch_num == dma_spec->args[0]) { + chan = &echan->vchan.chan; + break; + } + } + + if (!chan) + return NULL; + + if (echan->ecc->legacy_mode && dma_spec->args_count == 1) + goto out; + + if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && + dma_spec->args[1] < echan->ecc->num_tc) { + echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; + goto out; + } + + return NULL; +out: + /* The channel is going to be used as HW synchronized */ + echan->hw_triggered = true; + return dma_get_slave_channel(chan); +} #else -static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, + bool legacy_mode) { return ERR_PTR(-EINVAL); } + +static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + return NULL; +} #endif static int edma_probe(struct platform_device *pdev) @@ -1953,7 +2098,6 @@ static int edma_probe(struct platform_device *pdev) struct edma_soc_info *info = pdev->dev.platform_data; s8 (*queue_priority_mapping)[2]; int i, off, ln; - const s16 (*rsv_chans)[2]; const s16 (*rsv_slots)[2]; const s16 (*xbar_chans)[2]; int irq; @@ -1962,10 +2106,17 @@ static int edma_probe(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; struct device *dev = &pdev->dev; struct edma_cc *ecc; + bool legacy_mode = true; int ret; if (node) { - info = edma_setup_info_from_dt(dev); + const struct of_device_id *match; + + match = of_match_node(edma_of_ids, node); + if (match && (u32)match->data == EDMA_BINDING_TPCC) + legacy_mode = false; + + info = edma_setup_info_from_dt(dev, legacy_mode); if (IS_ERR(info)) { dev_err(dev, "failed to get DT data\n"); return PTR_ERR(info); @@ -1994,6 +2145,7 @@ static int edma_probe(struct platform_device *pdev) ecc->dev = dev; ecc->id = pdev->id; + ecc->legacy_mode = legacy_mode; /* When booting with DT the pdev->id is -1 */ if (ecc->id < 0) ecc->id = 0; @@ -2024,12 +2176,6 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slave_chans) return -ENOMEM; - ecc->channel_unused = devm_kcalloc(dev, - BITS_TO_LONGS(ecc->num_channels), - sizeof(unsigned long), GFP_KERNEL); - if (!ecc->channel_unused) - return -ENOMEM; - ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), sizeof(unsigned long), GFP_KERNEL); if (!ecc->slot_inuse) @@ -2040,20 +2186,7 @@ static int edma_probe(struct platform_device *pdev) for (i = 0; i < ecc->num_slots; i++) edma_write_slot(ecc, i, &dummy_paramset); - /* Mark all channels as unused */ - memset(ecc->channel_unused, 0xff, sizeof(ecc->channel_unused)); - if (info->rsv) { - /* Clear the reserved channels in unused list */ - rsv_chans = info->rsv->rsv_chans; - if (rsv_chans) { - for (i = 0; rsv_chans[i][0] != -1; i++) { - off = rsv_chans[i][0]; - ln = rsv_chans[i][1]; - clear_bits(off, ln, ecc->channel_unused); - } - } - /* Set the reserved slots in inuse list */ rsv_slots = info->rsv->rsv_slots; if (rsv_slots) { @@ -2070,7 +2203,6 @@ static int edma_probe(struct platform_device *pdev) if (xbar_chans) { for (i = 0; xbar_chans[i][1] != -1; i++) { off = xbar_chans[i][1]; - clear_bits(off, 1, ecc->channel_unused); } } @@ -2112,6 +2244,31 @@ static int edma_probe(struct platform_device *pdev) queue_priority_mapping = info->queue_priority_mapping; + if (!ecc->legacy_mode) { + int lowest_priority = 0; + struct of_phandle_args tc_args; + + ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, + sizeof(*ecc->tc_list), GFP_KERNEL); + if (!ecc->tc_list) + return -ENOMEM; + + for (i = 0;; i++) { + ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs", + 1, i, &tc_args); + if (ret || i == ecc->num_tc) + break; + + ecc->tc_list[i].node = tc_args.np; + ecc->tc_list[i].id = i; + queue_priority_mapping[i][1] = tc_args.args[0]; + if (queue_priority_mapping[i][1] > lowest_priority) { + lowest_priority = queue_priority_mapping[i][1]; + info->default_queue = i; + } + } + } + /* Event queue priority mapping */ for (i = 0; queue_priority_mapping[i][0] != -1; i++) edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], @@ -2125,7 +2282,7 @@ static int edma_probe(struct platform_device *pdev) ecc->info = info; /* Init the dma device and channels */ - edma_dma_init(ecc); + edma_dma_init(ecc, legacy_mode); for (i = 0; i < ecc->num_channels; i++) { /* Assign all channels to the default queue */ @@ -2136,12 +2293,23 @@ static int edma_probe(struct platform_device *pdev) } ret = dma_async_device_register(&ecc->dma_slave); - if (ret) + if (ret) { + dev_err(dev, "slave ddev registration failed (%d)\n", ret); goto err_reg1; + } + + if (ecc->dma_memcpy) { + ret = dma_async_device_register(ecc->dma_memcpy); + if (ret) { + dev_err(dev, "memcpy ddev registration failed (%d)\n", + ret); + dma_async_device_unregister(&ecc->dma_slave); + goto err_reg1; + } + } if (node) - of_dma_controller_register(node, of_dma_xlate_by_chan_id, - &ecc->dma_slave); + of_dma_controller_register(node, of_edma_xlate, ecc); dev_info(dev, "TI EDMA DMA engine driver\n"); @@ -2160,12 +2328,30 @@ static int edma_remove(struct platform_device *pdev) if (dev->of_node) of_dma_controller_free(dev->of_node); dma_async_device_unregister(&ecc->dma_slave); + if (ecc->dma_memcpy) + dma_async_device_unregister(ecc->dma_memcpy); edma_free_slot(ecc, ecc->dummy_slot); return 0; } #ifdef CONFIG_PM_SLEEP +static int edma_pm_suspend(struct device *dev) +{ + struct edma_cc *ecc = dev_get_drvdata(dev); + struct edma_chan *echan = ecc->slave_chans; + int i; + + for (i = 0; i < ecc->num_channels; i++) { + if (echan[i].alloced) { + edma_setup_interrupt(&echan[i], false); + edma_tc_set_pm_state(echan[i].tc, false); + } + } + + return 0; +} + static int edma_pm_resume(struct device *dev) { struct edma_cc *ecc = dev_get_drvdata(dev); @@ -2190,6 +2376,8 @@ static int edma_pm_resume(struct device *dev) /* Set up channel -> slot mapping for the entry slot */ edma_set_chmap(&echan[i], echan[i].slot[0]); + + edma_tc_set_pm_state(echan[i].tc, true); } } @@ -2198,7 +2386,7 @@ static int edma_pm_resume(struct device *dev) #endif static const struct dev_pm_ops edma_pm_ops = { - SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume) + SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume) }; static struct platform_driver edma_driver = { @@ -2213,12 +2401,18 @@ static struct platform_driver edma_driver = { bool edma_filter_fn(struct dma_chan *chan, void *param) { + bool match = false; + if (chan->device->dev->driver == &edma_driver.driver) { struct edma_chan *echan = to_edma_chan(chan); unsigned ch_req = *(unsigned *)param; - return ch_req == echan->ch_num; + if (ch_req == echan->ch_num) { + /* The channel is going to be used as HW synchronized */ + echan->hw_triggered = true; + match = true; + } } - return false; + return match; } EXPORT_SYMBOL(edma_filter_fn); -- cgit v1.2.3