From 3e8d74cb128fb1a4d56270ffbecea6056c55739a Mon Sep 17 00:00:00 2001 From: Saaem Rizvi Date: Tue, 9 May 2023 14:41:59 -0400 Subject: drm/amd/display: Trigger DIO FIFO resync on commit streams [WHY] Currently, there is an intermittent issue where a screen can either go blank or be corrupted. [HOW] To resolve the issue we trigger the ramping logic for DIO FIFO so that it goes back up to the correct speed. Reviewed-by: Nicholas Kazlauskas Acked-by: Tom Chung Signed-off-by: Saaem Rizvi Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index 4513544559be..4ca4192c1e12 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -160,6 +160,8 @@ struct hwseq_private_funcs { unsigned int *k1_div, unsigned int *k2_div); void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx); + void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc, + struct dc_state *context); bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx); #endif }; -- cgit v1.2.3