From a046a0daa3c6855d63fdf108919bb9666ba96c82 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Fri, 23 Jul 2021 10:42:34 -0700 Subject: drm/i915/dg2: Add vswing programming for SNPS phys Vswing programming for SNPS PHYs is just a single step -- look up the value that corresponds to the voltage level from a table and program it into the SNPS_PHY_TX_EQ register. Bspec: 53920 Cc: Matt Atwood Signed-off-by: Matt Roper Signed-off-by: Jani Nikula Reviewed-by: Matt Atwood Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-26-matthew.d.roper@intel.com --- drivers/gpu/drm/i915/display/intel_snps_phy.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/i915/display/intel_snps_phy.h') diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index ca4c2a25182b..3ce92d424f66 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -6,6 +6,8 @@ #ifndef __INTEL_SNPS_PHY_H__ #define __INTEL_SNPS_PHY_H__ +#include + struct intel_encoder; struct intel_crtc_state; struct intel_mpllb_state; @@ -21,5 +23,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, const struct intel_mpllb_state *pll_state); int intel_snps_phy_check_hdmi_link_rate(int clock); +void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, + u32 level); #endif /* __INTEL_SNPS_PHY_H__ */ -- cgit v1.2.3