From ebb945a94bba2ce8dff7b0942ff2b3f2a52a0a69 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 20 Jul 2012 08:17:34 +1000 Subject: drm/nouveau: port all engines to new engine module format This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz - fix find/replace bug in license header v3: Ben Skeggs - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 387 +++++++++++++++++++++++++++++++++ 1 file changed, 387 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/nouveau_chan.c (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c new file mode 100644 index 000000000000..3dd5f712b98c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -0,0 +1,387 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "nouveau_drm.h" +#include "nouveau_dma.h" +#include "nouveau_bo.h" +#include "nouveau_chan.h" +#include "nouveau_fence.h" +#include "nouveau_abi16.h" + +MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); +static int nouveau_vram_pushbuf; +module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); + +int +nouveau_channel_idle(struct nouveau_channel *chan) +{ + struct nouveau_drm *drm = chan->drm; + struct nouveau_fence *fence = NULL; + int ret; + + ret = nouveau_fence_new(chan, &fence); + if (!ret) { + ret = nouveau_fence_wait(fence, false, false); + nouveau_fence_unref(&fence); + } + + if (ret) + NV_ERROR(drm, "failed to idle channel 0x%08x\n", chan->handle); + return ret; +} + +void +nouveau_channel_del(struct nouveau_channel **pchan) +{ + struct nouveau_channel *chan = *pchan; + if (chan) { + struct nouveau_object *client = nv_object(chan->cli); + if (chan->fence) { + nouveau_channel_idle(chan); + nouveau_fence(chan->drm)->context_del(chan); + } + nouveau_object_del(client, NVDRM_DEVICE, chan->handle); + nouveau_object_del(client, NVDRM_DEVICE, chan->push.handle); + nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); + nouveau_bo_unmap(chan->push.buffer); + nouveau_bo_ref(NULL, &chan->push.buffer); + kfree(chan); + } + *pchan = NULL; +} + +static int +nouveau_channel_prep(struct nouveau_drm *drm, struct nouveau_cli *cli, + u32 parent, u32 handle, u32 size, + struct nouveau_channel **pchan) +{ + struct nouveau_device *device = nv_device(drm->device); + struct nouveau_instmem *imem = nouveau_instmem(device); + struct nouveau_vmmgr *vmm = nouveau_vmmgr(device); + struct nouveau_fb *pfb = nouveau_fb(device); + struct nouveau_client *client = &cli->base; + struct nv_dma_class args = {}; + struct nouveau_channel *chan; + struct nouveau_object *push; + u32 target; + int ret; + + chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + chan->cli = cli; + chan->drm = drm; + chan->handle = handle; + + /* allocate memory for dma push buffer */ + target = TTM_PL_FLAG_TT; + if (nouveau_vram_pushbuf) + target = TTM_PL_FLAG_VRAM; + + ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, + &chan->push.buffer); + if (ret == 0) { + ret = nouveau_bo_pin(chan->push.buffer, target); + if (ret == 0) + ret = nouveau_bo_map(chan->push.buffer); + } + + if (ret) { + nouveau_channel_del(pchan); + return ret; + } + + /* create dma object covering the *entire* memory space that the + * pushbuf lives in, this is because the GEM code requires that + * we be able to call out to other (indirect) push buffers + */ + chan->push.vma.offset = chan->push.buffer->bo.offset; + chan->push.handle = NVDRM_PUSH | (handle & 0xffff); + + if (device->card_type >= NV_50) { + ret = nouveau_bo_vma_add(chan->push.buffer, client->vm, + &chan->push.vma); + if (ret) { + nouveau_channel_del(pchan); + return ret; + } + + args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; + args.start = 0; + args.limit = client->vm->vmm->limit - 1; + } else + if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { + u64 limit = pfb->ram.size - imem->reserved - 1; + if (device->card_type == NV_04) { + /* nv04 vram pushbuf hack, retarget to its location in + * the framebuffer bar rather than direct vram access.. + * nfi why this exists, it came from the -nv ddx. + */ + args.flags = NV_DMA_TARGET_PCI | NV_DMA_ACCESS_RDWR; + args.start = pci_resource_start(device->pdev, 1); + args.limit = args.start + limit; + } else { + args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR; + args.start = 0; + args.limit = limit; + } + } else { + if (chan->drm->agp.stat == ENABLED) { + args.flags = NV_DMA_TARGET_AGP | NV_DMA_ACCESS_RDWR; + args.start = chan->drm->agp.base; + args.limit = chan->drm->agp.base + + chan->drm->agp.size - 1; + } else { + args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_RDWR; + args.start = 0; + args.limit = vmm->limit - 1; + } + } + + ret = nouveau_object_new(nv_object(chan->cli), parent, + chan->push.handle, 0x0002, + &args, sizeof(args), &push); + if (ret) { + nouveau_channel_del(pchan); + return ret; + } + + return 0; +} + +int +nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, + u32 parent, u32 handle, struct nouveau_channel **pchan) +{ + static const u16 oclasses[] = { 0xa06f, 0x906f, 0x826f, 0x506f, 0 }; + const u16 *oclass = oclasses; + struct nv_channel_ind_class args; + struct nouveau_channel *chan; + int ret; + + /* allocate dma push buffer */ + ret = nouveau_channel_prep(drm, cli, parent, handle, 0x12000, &chan); + *pchan = chan; + if (ret) + return ret; + + /* create channel object */ + args.pushbuf = chan->push.handle; + args.ioffset = 0x10000 + chan->push.vma.offset; + args.ilength = 0x02000; + + do { + ret = nouveau_object_new(nv_object(cli), parent, handle, + *oclass++, &args, sizeof(args), + &chan->object); + if (ret == 0) + return ret; + } while (*oclass); + + nouveau_channel_del(pchan); + return ret; +} + +static int +nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli, + u32 parent, u32 handle, struct nouveau_channel **pchan) +{ + static const u16 oclasses[] = { 0x006e, 0 }; + const u16 *oclass = oclasses; + struct nv_channel_dma_class args; + struct nouveau_channel *chan; + int ret; + + /* allocate dma push buffer */ + ret = nouveau_channel_prep(drm, cli, parent, handle, 0x10000, &chan); + *pchan = chan; + if (ret) + return ret; + + /* create channel object */ + args.pushbuf = chan->push.handle; + args.offset = chan->push.vma.offset; + + do { + ret = nouveau_object_new(nv_object(cli), parent, handle, + *oclass++, &args, sizeof(args), + &chan->object); + if (ret == 0) + return ret; + } while (ret && *oclass); + + nouveau_channel_del(pchan); + return ret; +} + +static int +nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) +{ + struct nouveau_client *client = nv_client(chan->cli); + struct nouveau_device *device = nv_device(chan->drm->device); + struct nouveau_instmem *imem = nouveau_instmem(device); + struct nouveau_vmmgr *vmm = nouveau_vmmgr(device); + struct nouveau_fb *pfb = nouveau_fb(device); + struct nouveau_software_chan *swch; + struct nouveau_object *object; + struct nv_dma_class args; + int ret, i; + + chan->vram = vram; + chan->gart = gart; + + /* allocate dma objects to cover all allowed vram, and gart */ + if (device->card_type < NV_C0) { + if (device->card_type >= NV_50) { + args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; + args.start = 0; + args.limit = client->vm->vmm->limit - 1; + } else { + args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR; + args.start = 0; + args.limit = pfb->ram.size - imem->reserved - 1; + } + + ret = nouveau_object_new(nv_object(client), chan->handle, vram, + 0x003d, &args, sizeof(args), &object); + if (ret) + return ret; + + if (device->card_type >= NV_50) { + args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; + args.start = 0; + args.limit = client->vm->vmm->limit - 1; + } else + if (chan->drm->agp.stat == ENABLED) { + args.flags = NV_DMA_TARGET_AGP | NV_DMA_ACCESS_RDWR; + args.start = chan->drm->agp.base; + args.limit = chan->drm->agp.base + + chan->drm->agp.size - 1; + } else { + args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_RDWR; + args.start = 0; + args.limit = vmm->limit - 1; + } + + ret = nouveau_object_new(nv_object(client), chan->handle, gart, + 0x003d, &args, sizeof(args), &object); + if (ret) + return ret; + } + + /* initialise dma tracking parameters */ + switch (nv_hclass(chan->object) & 0xffff) { + case 0x006e: + chan->user_put = 0x40; + chan->user_get = 0x44; + chan->dma.max = (0x10000 / 4) - 2; + break; + default: + chan->user_put = 0x40; + chan->user_get = 0x44; + chan->user_get_hi = 0x60; + chan->dma.ib_base = 0x10000 / 4; + chan->dma.ib_max = (0x02000 / 8) - 1; + chan->dma.ib_put = 0; + chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; + chan->dma.max = chan->dma.ib_base; + break; + } + + chan->dma.put = 0; + chan->dma.cur = chan->dma.put; + chan->dma.free = chan->dma.max - chan->dma.cur; + + ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); + if (ret) + return ret; + + for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) + OUT_RING(chan, 0x00000000); + + /* allocate software object class (used for fences on <= nv05, and + * to signal flip completion), bind it to a subchannel. + */ + ret = nouveau_object_new(nv_object(client), chan->handle, + NvSw, nouveau_abi16_swclass(chan->drm), + NULL, 0, &object); + if (ret) + return ret; + + swch = (void *)object->parent; + swch->flip = nouveau_flip_complete; + swch->flip_data = chan; + + if (device->card_type < NV_C0) { + ret = RING_SPACE(chan, 2); + if (ret) + return ret; + + BEGIN_NV04(chan, NvSubSw, 0x0000, 1); + OUT_RING (chan, NvSw); + FIRE_RING (chan); + } + + /* initialise synchronisation */ + return nouveau_fence(chan->drm)->context_new(chan); +} + +int +nouveau_channel_new(struct nouveau_drm *drm, struct nouveau_cli *cli, + u32 parent, u32 handle, u32 vram, u32 gart, + struct nouveau_channel **pchan) +{ + int ret; + + ret = nouveau_channel_ind(drm, cli, parent, handle, pchan); + if (ret) { + NV_DEBUG(drm, "ib channel create, %d\n", ret); + ret = nouveau_channel_dma(drm, cli, parent, handle, pchan); + if (ret) { + NV_DEBUG(drm, "dma channel create, %d\n", ret); + return ret; + } + } + + ret = nouveau_channel_init(*pchan, vram, gart); + if (ret) { + NV_ERROR(drm, "channel failed to initialise, %d\n", ret); + nouveau_channel_del(pchan); + return ret; + } + + return 0; +} -- cgit v1.2.3 From dbff2dee9f8561710fcfe7f6623dd272ddca5a27 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2012 18:16:37 +1000 Subject: drm/nve0/fifo: support engine selection when creating fifo channels Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 3dd5f712b98c..b1eea19d99a6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -188,7 +188,7 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, { static const u16 oclasses[] = { 0xa06f, 0x906f, 0x826f, 0x506f, 0 }; const u16 *oclass = oclasses; - struct nv_channel_ind_class args; + struct nve0_channel_ind_class args; struct nouveau_channel *chan; int ret; @@ -202,6 +202,7 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, args.pushbuf = chan->push.handle; args.ioffset = 0x10000 + chan->push.vma.offset; args.ilength = 0x02000; + args.engine = NVE0_CHANNEL_IND_ENGINE_GR; do { ret = nouveau_object_new(nv_object(cli), parent, handle, -- cgit v1.2.3 From 49981046e3dc2f934663548a270d4bf1a4534bb9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2012 19:38:25 +1000 Subject: drm/nve0: use async copy engine for ttm buffer moves if available Kepler PFIFO lost the ability to address multiple engines from a single channel, so we need a separate one for the copy engine. v2: Marcin Slusarz - regression fix: restore hw accelerated buffer copies Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 35 ++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index b1eea19d99a6..62c7edf08e5a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -184,7 +184,8 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nouveau_cli *cli, int nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, - u32 parent, u32 handle, struct nouveau_channel **pchan) + u32 parent, u32 handle, u32 engine, + struct nouveau_channel **pchan) { static const u16 oclasses[] = { 0xa06f, 0x906f, 0x826f, 0x506f, 0 }; const u16 *oclass = oclasses; @@ -202,7 +203,7 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, args.pushbuf = chan->push.handle; args.ioffset = 0x10000 + chan->push.vma.offset; args.ilength = 0x02000; - args.engine = NVE0_CHANNEL_IND_ENGINE_GR; + args.engine = engine; do { ret = nouveau_object_new(nv_object(cli), parent, handle, @@ -261,9 +262,6 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) struct nv_dma_class args; int ret, i; - chan->vram = vram; - chan->gart = gart; - /* allocate dma objects to cover all allowed vram, and gart */ if (device->card_type < NV_C0) { if (device->card_type >= NV_50) { @@ -301,6 +299,9 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 0x003d, &args, sizeof(args), &object); if (ret) return ret; + + chan->vram = vram; + chan->gart = gart; } /* initialise dma tracking parameters */ @@ -336,15 +337,17 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) /* allocate software object class (used for fences on <= nv05, and * to signal flip completion), bind it to a subchannel. */ - ret = nouveau_object_new(nv_object(client), chan->handle, - NvSw, nouveau_abi16_swclass(chan->drm), - NULL, 0, &object); - if (ret) - return ret; + if (chan != chan->drm->cechan) { + ret = nouveau_object_new(nv_object(client), chan->handle, + NvSw, nouveau_abi16_swclass(chan->drm), + NULL, 0, &object); + if (ret) + return ret; - swch = (void *)object->parent; - swch->flip = nouveau_flip_complete; - swch->flip_data = chan; + swch = (void *)object->parent; + swch->flip = nouveau_flip_complete; + swch->flip_data = chan; + } if (device->card_type < NV_C0) { ret = RING_SPACE(chan, 2); @@ -362,12 +365,12 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) int nouveau_channel_new(struct nouveau_drm *drm, struct nouveau_cli *cli, - u32 parent, u32 handle, u32 vram, u32 gart, + u32 parent, u32 handle, u32 arg0, u32 arg1, struct nouveau_channel **pchan) { int ret; - ret = nouveau_channel_ind(drm, cli, parent, handle, pchan); + ret = nouveau_channel_ind(drm, cli, parent, handle, arg0, pchan); if (ret) { NV_DEBUG(drm, "ib channel create, %d\n", ret); ret = nouveau_channel_dma(drm, cli, parent, handle, pchan); @@ -377,7 +380,7 @@ nouveau_channel_new(struct nouveau_drm *drm, struct nouveau_cli *cli, } } - ret = nouveau_channel_init(*pchan, vram, gart); + ret = nouveau_channel_init(*pchan, arg0, arg1); if (ret) { NV_ERROR(drm, "channel failed to initialise, %d\n", ret); nouveau_channel_del(pchan); -- cgit v1.2.3 From 503b0f1cd66c54dd88e644fa1a521ebd764bf54e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 14 Aug 2012 14:53:51 +1000 Subject: drm/nouveau/fifo: separate object classes for dma channels Future code will use the object class rather than chipset checks in order to identify available channel features. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 62c7edf08e5a..cf61dc0226a3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -221,7 +221,7 @@ static int nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli, u32 parent, u32 handle, struct nouveau_channel **pchan) { - static const u16 oclasses[] = { 0x006e, 0 }; + static const u16 oclasses[] = { 0x406e, 0x176e, 0x006e, 0x006b, 0 }; const u16 *oclass = oclasses; struct nv_channel_dma_class args; struct nouveau_channel *chan; @@ -305,7 +305,8 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) } /* initialise dma tracking parameters */ - switch (nv_hclass(chan->object) & 0xffff) { + switch (nv_hclass(chan->object) & 0x00ff) { + case 0x006b: case 0x006e: chan->user_put = 0x40; chan->user_get = 0x44; -- cgit v1.2.3 From a7c6e75eb28d18ed8d53182891330f5c1fa4477c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 14 Aug 2012 15:02:29 +1000 Subject: drm/nouveau/fifo: version the dma channel class struct Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index cf61dc0226a3..e6451847df4a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -223,7 +223,7 @@ nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli, { static const u16 oclasses[] = { 0x406e, 0x176e, 0x006e, 0x006b, 0 }; const u16 *oclass = oclasses; - struct nv_channel_dma_class args; + struct nv03_channel_dma_class args; struct nouveau_channel *chan; int ret; -- cgit v1.2.3 From c97f8c922ea78195aa7d833d639d2963cc11af8e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 19 Aug 2012 16:03:00 +1000 Subject: drm/nouveau/fifo: use defines instead of hardcoded class ids Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index e6451847df4a..55dc51c1b92e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -187,7 +187,11 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, u32 parent, u32 handle, u32 engine, struct nouveau_channel **pchan) { - static const u16 oclasses[] = { 0xa06f, 0x906f, 0x826f, 0x506f, 0 }; + static const u16 oclasses[] = { NVE0_CHANNEL_IND_CLASS, + NVC0_CHANNEL_IND_CLASS, + NV84_CHANNEL_IND_CLASS, + NV50_CHANNEL_IND_CLASS, + 0 }; const u16 *oclass = oclasses; struct nve0_channel_ind_class args; struct nouveau_channel *chan; @@ -221,7 +225,11 @@ static int nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli, u32 parent, u32 handle, struct nouveau_channel **pchan) { - static const u16 oclasses[] = { 0x406e, 0x176e, 0x006e, 0x006b, 0 }; + static const u16 oclasses[] = { NV40_CHANNEL_DMA_CLASS, + NV17_CHANNEL_DMA_CLASS, + NV10_CHANNEL_DMA_CLASS, + NV03_CHANNEL_DMA_CLASS, + 0 }; const u16 *oclass = oclasses; struct nv03_channel_dma_class args; struct nouveau_channel *chan; -- cgit v1.2.3 From 5b8a43aeb9cbf6b965f67f6c850382788076325a Mon Sep 17 00:00:00 2001 From: Marcin Slusarz Date: Sun, 19 Aug 2012 23:00:00 +0200 Subject: drm/nouveau: quiet some static-related sparse noise Signed-off-by: Marcin Slusarz Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 55dc51c1b92e..3b3791453178 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -182,7 +182,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nouveau_cli *cli, return 0; } -int +static int nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, u32 parent, u32 handle, u32 engine, struct nouveau_channel **pchan) -- cgit v1.2.3 From da07e52cf10c9584c7e197ac3d49455e1a4d4756 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 12 Sep 2012 13:40:47 +1000 Subject: drm/nouveau: log channel debug/error messages from client object rather than drm client This will make it more obvious which application caused particular messages. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 3b3791453178..c1d7301c0e9c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -47,7 +47,7 @@ module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); int nouveau_channel_idle(struct nouveau_channel *chan) { - struct nouveau_drm *drm = chan->drm; + struct nouveau_cli *cli = chan->cli; struct nouveau_fence *fence = NULL; int ret; @@ -58,7 +58,7 @@ nouveau_channel_idle(struct nouveau_channel *chan) } if (ret) - NV_ERROR(drm, "failed to idle channel 0x%08x\n", chan->handle); + NV_ERROR(cli, "failed to idle channel 0x%08x\n", chan->handle); return ret; } @@ -381,17 +381,17 @@ nouveau_channel_new(struct nouveau_drm *drm, struct nouveau_cli *cli, ret = nouveau_channel_ind(drm, cli, parent, handle, arg0, pchan); if (ret) { - NV_DEBUG(drm, "ib channel create, %d\n", ret); + NV_DEBUG(cli, "ib channel create, %d\n", ret); ret = nouveau_channel_dma(drm, cli, parent, handle, pchan); if (ret) { - NV_DEBUG(drm, "dma channel create, %d\n", ret); + NV_DEBUG(cli, "dma channel create, %d\n", ret); return ret; } } ret = nouveau_channel_init(*pchan, arg0, arg1); if (ret) { - NV_ERROR(drm, "channel failed to initialise, %d\n", ret); + NV_ERROR(cli, "channel failed to initialise, %d\n", ret); nouveau_channel_del(pchan); return ret; } -- cgit v1.2.3