From 2704cf5fbd248871a745d210733c6319959d2b0c Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 28 Jul 2011 11:52:45 -0700 Subject: drm/i915: flush plane control changes on ILK+ as well After writing to the plane control reg we need to write to the surface reg to trigger the double buffered register latch. On previous chipsets, writing to DSPADDR was enough, but on ILK+ DSPSURF is the reg that triggers the double buffer latch. v2: write DSPADDR too to cover pre-965 chipsets v3: use flush_display_plane instead, that's what it's for v4: send the right patch Signed-off-by: Jesse Barnes Tested-by: Keith Packard Reviewed-by: Keith Packard Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 502efc37b074..a7a7b672c4c2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1323,8 +1323,8 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, static void intel_flush_display_plane(struct drm_i915_private *dev_priv, enum plane plane) { - u32 reg = DSPADDR(plane); - I915_WRITE(reg, I915_READ(reg)); + I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); + I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); } /** -- cgit v1.2.3