From 27ecdd07e3e16684fd996730100637a61d9ac2ee Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 28 Jun 2022 15:22:49 +0300 Subject: phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200 Select the same mac divider for SGMII too as the one being used for QSGMII. Enable full rate divider configuration support for J721E_WIZ_10G for SGMII. Signed-off-by: Siddharth Vadapalli Signed-off-by: Vignesh Raghavendra Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-2-rogerq@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/ti/phy-j721e-wiz.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 70bac931f99a..8c10ee8e2707 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -325,7 +325,8 @@ static int wiz_p_mac_div_sel(struct wiz *wiz) int i; for (i = 0; i < num_lanes; i++) { - if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { + if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || + wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); if (ret) return ret; @@ -1025,12 +1026,18 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) { - if (wiz->type != AM64_WIZ_10G) + switch (wiz->type) { + case AM64_WIZ_10G: + if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); + break; + case J721E_WIZ_10G: + if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); + break; + default: return 0; - - if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) - return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); - + } return 0; } -- cgit v1.2.3 From b64a85fb8f531d201cc43088a23d8b32dc729fc2 Mon Sep 17 00:00:00 2001 From: Tanmay Patil Date: Tue, 28 Jun 2022 15:22:51 +0300 Subject: phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver Changes the wiz_p_mac_div_sel() and wiz_mode_select() to configure serdes for USXGMII. Adds the support to configure mac_src_sel, refclk_sel and rxfclk_sel in the LANECTL register and configures the serdes for usxgmii. [rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code. Signed-off-by: Tanmay Patil Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-4-rogerq@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/ti/phy-j721e-wiz.c | 51 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 8c10ee8e2707..77accea6ec2f 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -129,6 +129,26 @@ static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(3), 22, 23), }; +static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 20, 21), + REG_FIELD(WIZ_LANECTL(1), 20, 21), + REG_FIELD(WIZ_LANECTL(2), 20, 21), + REG_FIELD(WIZ_LANECTL(3), 20, 21), +}; + +static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 6, 7), + REG_FIELD(WIZ_LANECTL(1), 6, 7), + REG_FIELD(WIZ_LANECTL(2), 6, 7), + REG_FIELD(WIZ_LANECTL(3), 6, 7), +}; + +static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 18, 19), + REG_FIELD(WIZ_LANECTL(1), 18, 19), + REG_FIELD(WIZ_LANECTL(2), 18, 19), + REG_FIELD(WIZ_LANECTL(3), 18, 19), +}; static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANEDIV(0), 16, 22), REG_FIELD(WIZ_LANEDIV(1), 16, 22), @@ -280,6 +300,9 @@ struct wiz { struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; + struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; + struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; + struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; struct regmap_field *pma_cmn_refclk_int_mode; struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; @@ -326,7 +349,8 @@ static int wiz_p_mac_div_sel(struct wiz *wiz) for (i = 0; i < num_lanes; i++) { if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || - wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { + wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || + wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); if (ret) return ret; @@ -355,6 +379,13 @@ static int wiz_mode_select(struct wiz *wiz) else continue; + if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { + ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); + ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); + ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); + mode = LANE_MODE_GEN1; + } + ret = regmap_field_write(wiz->p_standard_mode[i], mode); if (ret) return ret; @@ -524,6 +555,24 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->p0_fullrt_div[i]); } + wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); + if (IS_ERR(wiz->p0_mac_src_sel[i])) { + dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); + return PTR_ERR(wiz->p0_mac_src_sel[i]); + } + + wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); + if (IS_ERR(wiz->p0_rxfclk_sel[i])) { + dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); + return PTR_ERR(wiz->p0_rxfclk_sel[i]); + } + + wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); + if (IS_ERR(wiz->p0_refclk_sel[i])) { + dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); + return PTR_ERR(wiz->p0_refclk_sel[i]); + } + wiz->p_mac_div_sel0[i] = devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); if (IS_ERR(wiz->p_mac_div_sel0[i])) { -- cgit v1.2.3 From edd473d4293aa5a1684f4efe0d4e0c0318a92976 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 28 Jun 2022 15:22:54 +0300 Subject: phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g j7200-wiz-10g supports 2 reference clocks. However, the control bits for these clocks is in a separate register that sits in the System Control register space. Handle that register. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-7-rogerq@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/ti/phy-j721e-wiz.c | 138 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 129 insertions(+), 9 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 77accea6ec2f..cc2ab5152f07 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,10 @@ #include #include +/* SCM offsets */ +#define SERDES_SUP_CTRL 0x4400 + +/* SERDES offsets */ #define WIZ_SERDES_CTRL 0x404 #define WIZ_SERDES_TOP_CTRL 0x408 #define WIZ_SERDES_RST 0x40c @@ -85,6 +90,18 @@ static const struct reg_field pma_cmn_refclk_dig_div = REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); static const struct reg_field pma_cmn_refclk1_dig_div = REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); + +static const struct reg_field sup_pll0_refclk_mux_sel = + REG_FIELD(SERDES_SUP_CTRL, 0, 1); +static const struct reg_field sup_pll1_refclk_mux_sel = + REG_FIELD(SERDES_SUP_CTRL, 2, 3); +static const struct reg_field sup_pma_cmn_refclk1_int_mode = + REG_FIELD(SERDES_SUP_CTRL, 4, 5); +static const struct reg_field sup_refclk_dig_sel_10g = + REG_FIELD(SERDES_SUP_CTRL, 6, 7); +static const struct reg_field sup_legacy_clk_override = + REG_FIELD(SERDES_SUP_CTRL, 8, 8); + static const char * const output_clk_names[] = { [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", @@ -248,6 +265,27 @@ static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { }, }; +static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = { + { + .num_parents = 3, + .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table = { 2, 3, 0 }, + .node_name = "pll0-refclk", + }, + { + .num_parents = 3, + .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table = { 2, 3, 0 }, + .node_name = "pll1-refclk", + }, + { + .num_parents = 3, + .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table = { 2, 3, 0 }, + .node_name = "refclk-dig", + }, +}; + static const struct clk_div_table clk_div_table[] = { { .val = 0, .div = 1, }, { .val = 1, .div = 2, }, @@ -269,14 +307,18 @@ static const struct wiz_clk_div_sel clk_div_sel[] = { enum wiz_type { J721E_WIZ_16G, - J721E_WIZ_10G, + J721E_WIZ_10G, /* Also for J7200 SR1.0 */ AM64_WIZ_10G, + J7200_WIZ_10G, /* J7200 SR2.0 */ }; struct wiz_data { enum wiz_type type; + const struct reg_field *pll0_refclk_mux_sel; + const struct reg_field *pll1_refclk_mux_sel; const struct reg_field *refclk_dig_sel; const struct reg_field *pma_cmn_refclk1_dig_div; + const struct reg_field *pma_cmn_refclk1_int_mode; const struct wiz_clk_mux_sel *clk_mux_sel; unsigned int clk_div_sel_num; }; @@ -286,6 +328,7 @@ struct wiz_data { struct wiz { struct regmap *regmap; + struct regmap *scm_regmap; enum wiz_type type; const struct wiz_clk_mux_sel *clk_mux_sel; const struct wiz_clk_div_sel *clk_div_sel; @@ -304,12 +347,14 @@ struct wiz { struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; struct regmap_field *pma_cmn_refclk_int_mode; + struct regmap_field *pma_cmn_refclk1_int_mode; struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; struct regmap_field *pma_cmn_refclk1_dig_div; struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; struct regmap_field *typec_ln10_swap; + struct regmap_field *sup_legacy_clk_override; struct device *dev; u32 num_lanes; @@ -448,6 +493,7 @@ static int wiz_init(struct wiz *wiz) static int wiz_regfield_init(struct wiz *wiz) { struct regmap *regmap = wiz->regmap; + struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */ int num_lanes = wiz->num_lanes; struct device *dev = wiz->dev; const struct wiz_data *data = wiz->data; @@ -497,27 +543,46 @@ static int wiz_regfield_init(struct wiz *wiz) } } + if (wiz->scm_regmap) { + scm_regmap = wiz->scm_regmap; + wiz->sup_legacy_clk_override = + devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override); + if (IS_ERR(wiz->sup_legacy_clk_override)) { + dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n"); + return PTR_ERR(wiz->sup_legacy_clk_override); + } + } + wiz->mux_sel_field[PLL0_REFCLK] = - devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel); + devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); } wiz->mux_sel_field[PLL1_REFCLK] = - devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel); + devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); } - wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap, + wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap, *data->refclk_dig_sel); if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); } + if (data->pma_cmn_refclk1_int_mode) { + wiz->pma_cmn_refclk1_int_mode = + devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode); + if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { + dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n"); + return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); + } + } + for (i = 0; i < num_lanes; i++) { wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, p_enable[i]); @@ -906,9 +971,13 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) struct device_node *clk_node; int i; - if (wiz->type == AM64_WIZ_10G) { + switch (wiz->type) { + case AM64_WIZ_10G: + case J7200_WIZ_10G: of_clk_del_provider(dev->of_node); return; + default: + break; } for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { @@ -935,9 +1004,6 @@ static int wiz_clock_register(struct wiz *wiz) int ret; int i; - if (wiz->type != AM64_WIZ_10G) - return 0; - clk_index = TI_WIZ_PLL0_REFCLK; for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); @@ -987,6 +1053,22 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) else regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); + if (wiz->data->pma_cmn_refclk1_int_mode) { + clk = devm_clk_get(dev, "core_ref1_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "core_ref1_clk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + wiz->input_clks[WIZ_CORE_REFCLK1] = clk; + + rate = clk_get_rate(clk); + if (rate >= 100000000) + regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); + else + regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); + } + clk = devm_clk_get(dev, "ext_ref_clk"); if (IS_ERR(clk)) { dev_err(dev, "ext_ref_clk clock not found\n"); @@ -1001,11 +1083,15 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) else regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); - if (wiz->type == AM64_WIZ_10G) { + switch (wiz->type) { + case AM64_WIZ_10G: + case J7200_WIZ_10G: ret = wiz_clock_register(wiz); if (ret) dev_err(dev, "Failed to register wiz clocks\n"); return ret; + default: + break; } for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { @@ -1081,6 +1167,7 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); break; case J721E_WIZ_10G: + case J7200_WIZ_10G: if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); break; @@ -1139,6 +1226,8 @@ static const struct regmap_config wiz_regmap_config = { static struct wiz_data j721e_16g_data = { .type = J721E_WIZ_16G, + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, .refclk_dig_sel = &refclk_dig_sel_16g, .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, .clk_mux_sel = clk_mux_sel_16g, @@ -1147,6 +1236,8 @@ static struct wiz_data j721e_16g_data = { static struct wiz_data j721e_10g_data = { .type = J721E_WIZ_10G, + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, .refclk_dig_sel = &refclk_dig_sel_10g, .clk_mux_sel = clk_mux_sel_10g, .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, @@ -1154,11 +1245,23 @@ static struct wiz_data j721e_10g_data = { static struct wiz_data am64_10g_data = { .type = AM64_WIZ_10G, + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, .refclk_dig_sel = &refclk_dig_sel_10g, .clk_mux_sel = clk_mux_sel_10g, .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, }; +static struct wiz_data j7200_pg2_10g_data = { + .type = J7200_WIZ_10G, + .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel, + .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel, + .refclk_dig_sel = &sup_refclk_dig_sel_10g, + .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode, + .clk_mux_sel = clk_mux_sel_10g_2_refclk, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, +}; + static const struct of_device_id wiz_id_table[] = { { .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, @@ -1169,6 +1272,9 @@ static const struct of_device_id wiz_id_table[] = { { .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, }, + { + .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, + }, {} }; MODULE_DEVICE_TABLE(of, wiz_id_table); @@ -1266,6 +1372,16 @@ static int wiz_probe(struct platform_device *pdev) goto err_addr_to_resource; } + wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm"); + if (IS_ERR(wiz->scm_regmap)) { + if (wiz->type == J7200_WIZ_10G) { + dev_err(dev, "Couldn't get ti,scm regmap\n"); + return -ENODEV; + } + + wiz->scm_regmap = NULL; + } + ret = of_property_read_u32(node, "num-lanes", &num_lanes); if (ret) { dev_err(dev, "Failed to read num-lanes property\n"); @@ -1327,6 +1443,10 @@ static int wiz_probe(struct platform_device *pdev) goto err_addr_to_resource; } + /* Enable supplemental Control override if available */ + if (wiz->scm_regmap) + regmap_field_write(wiz->sup_legacy_clk_override, 1); + phy_reset_dev = &wiz->wiz_phy_reset_dev; phy_reset_dev->dev = dev; phy_reset_dev->ops = &wiz_phy_reset_ops, -- cgit v1.2.3 From 86d11e225e3fd204d42346effba08a7c465f6a57 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 28 Jun 2022 15:22:55 +0300 Subject: phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/phy') diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index cc2ab5152f07..20af142580ad 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -24,6 +24,11 @@ #include #include +#define REF_CLK_19_2MHZ 19200000 +#define REF_CLK_25MHZ 25000000 +#define REF_CLK_100MHZ 100000000 +#define REF_CLK_156_25MHZ 156250000 + /* SCM offsets */ #define SERDES_SUP_CTRL 0x4400 @@ -1053,6 +1058,25 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) else regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); + switch (wiz->type) { + case AM64_WIZ_10G: + case J7200_WIZ_10G: + switch (rate) { + case REF_CLK_100MHZ: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); + break; + case REF_CLK_156_25MHZ: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); + break; + default: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); + break; + } + break; + default: + break; + } + if (wiz->data->pma_cmn_refclk1_int_mode) { clk = devm_clk_get(dev, "core_ref1_clk"); if (IS_ERR(clk)) { -- cgit v1.2.3 From 317e00bbf950b5dd83f18f6771c3e402485052ea Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 9 Aug 2022 21:07:42 -0700 Subject: phy: qcom: edp: Generate unique clock names With multiple Displayport PHYs the hard coded clock names collides, generate unique clock names based on the device name instead. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810040745.3582985-3-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-edp.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 7e3570789845..41aa28291cea 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -571,21 +571,24 @@ static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np) { struct clk_hw_onecell_data *data; struct clk_init_data init = { }; + char name[64]; int ret; data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL); if (!data) return -ENOMEM; + snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev)); init.ops = &qcom_edp_dp_link_clk_ops; - init.name = "edp_phy_pll_link_clk"; + init.name = name; edp->dp_link_hw.init = &init; ret = devm_clk_hw_register(edp->dev, &edp->dp_link_hw); if (ret) return ret; + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(edp->dev)); init.ops = &qcom_edp_dp_pixel_clk_ops; - init.name = "edp_phy_pll_vco_div_clk"; + init.name = name; edp->dp_pixel_hw.init = &init; ret = devm_clk_hw_register(edp->dev, &edp->dp_pixel_hw); if (ret) -- cgit v1.2.3 From 5894ff12c7ec0bd5960c6f1d91b64674d9ffb9bf Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 9 Aug 2022 21:07:43 -0700 Subject: phy: qcom: edp: Perform lane configuration The TRANSCIEVER_BIAS_EN, HIGHZ_DRVR_EN and PHY_CFG_1 registers are used for lane configuration, with the currently hard coded configuration being a mix of 2 and 4 lane (effectively 2-lane). Properly implement lane configuration for 1, 2 and 4 lanes. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810040745.3582985-4-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-edp.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 41aa28291cea..32614fb838b5 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -315,9 +315,11 @@ static int qcom_edp_set_vco_div(const struct qcom_edp *edp) static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp = phy_get_drvdata(phy); + u32 bias0_en, drvr0_en, bias1_en, drvr1_en; int timeout; int ret; u32 val; + u8 cfg1; writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | @@ -398,11 +400,31 @@ static int qcom_edp_phy_power_on(struct phy *phy) writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL); writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL); - writel(0x4, edp->tx0 + TXn_HIGHZ_DRVR_EN); - writel(0x3, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); - writel(0x4, edp->tx1 + TXn_HIGHZ_DRVR_EN); - writel(0x0, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); - writel(0x3, edp->edp + DP_PHY_CFG_1); + if (edp->dp_opts.lanes == 1) { + bias0_en = 0x01; + bias1_en = 0x00; + drvr0_en = 0x06; + drvr1_en = 0x07; + cfg1 = 0x1; + } else if (edp->dp_opts.lanes == 2) { + bias0_en = 0x03; + bias1_en = 0x00; + drvr0_en = 0x04; + drvr1_en = 0x07; + cfg1 = 0x3; + } else { + bias0_en = 0x03; + bias1_en = 0x03; + drvr0_en = 0x04; + drvr1_en = 0x04; + cfg1 = 0xf; + } + + writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN); + writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); + writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN); + writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); + writel(cfg1, edp->edp + DP_PHY_CFG_1); writel(0x18, edp->edp + DP_PHY_CFG); usleep_range(100, 1000); -- cgit v1.2.3 From 2300d1cb24b3290e1e04b78692446052e911c92f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 9 Aug 2022 21:07:44 -0700 Subject: phy: qcom: edp: Introduce support for DisplayPort The eDP phy can be used to drive either eDP or DP output, with some minor variations in some of the configuration and seemingly a need for implementing swing and pre_emphasis calibration. Introduce a config object, indicating if the phy is operating in eDP or DP mode and swing/pre-emphasis calibration to support this. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810040745.3582985-5-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-edp.c | 80 +++++++++++++++++++++++++++++++++++-- 1 file changed, 76 insertions(+), 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 32614fb838b5..301ac422d2fe 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -70,8 +70,19 @@ #define TXn_TRAN_DRVR_EMP_EN 0x0078 +struct qcom_edp_cfg { + bool is_dp; + + /* DP PHY swing and pre_emphasis tables */ + const u8 (*swing_hbr_rbr)[4][4]; + const u8 (*swing_hbr3_hbr2)[4][4]; + const u8 (*pre_emphasis_hbr_rbr)[4][4]; + const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; +}; + struct qcom_edp { struct device *dev; + const struct qcom_edp_cfg *cfg; struct phy *phy; @@ -92,7 +103,9 @@ struct qcom_edp { static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp = phy_get_drvdata(phy); + const struct qcom_edp_cfg *cfg = edp->cfg; int ret; + u8 cfg8; ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); if (ret) @@ -117,6 +130,13 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); + if (cfg && cfg->is_dp) + cfg8 = 0xb7; + else + cfg8 = 0x37; + + writel(0xfc, edp->edp + DP_PHY_MODE); + writel(0x00, edp->edp + DP_PHY_AUX_CFG0); writel(0x13, edp->edp + DP_PHY_AUX_CFG1); writel(0x24, edp->edp + DP_PHY_AUX_CFG2); @@ -125,7 +145,7 @@ static int qcom_edp_phy_init(struct phy *phy) writel(0x26, edp->edp + DP_PHY_AUX_CFG5); writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); writel(0x03, edp->edp + DP_PHY_AUX_CFG7); - writel(0x37, edp->edp + DP_PHY_AUX_CFG8); + writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); writel(0x03, edp->edp + DP_PHY_AUX_CFG9); writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | @@ -142,14 +162,60 @@ out_disable_supplies: return ret; } +static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts) +{ + const struct qcom_edp_cfg *cfg = edp->cfg; + unsigned int v_level = 0; + unsigned int p_level = 0; + u8 ldo_config; + u8 swing; + u8 emph; + int i; + + if (!cfg) + return 0; + + for (i = 0; i < dp_opts->lanes; i++) { + v_level = max(v_level, dp_opts->voltage[i]); + p_level = max(p_level, dp_opts->pre[i]); + } + + if (dp_opts->link_rate <= 2700) { + swing = (*cfg->swing_hbr_rbr)[v_level][p_level]; + emph = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; + } else { + swing = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; + emph = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; + } + + if (swing == 0xff || emph == 0xff) + return -EINVAL; + + ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(swing, edp->tx0 + TXn_TX_DRV_LVL); + writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); + + writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); + writel(swing, edp->tx1 + TXn_TX_DRV_LVL); + writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); + + return 0; +} + static int qcom_edp_phy_configure(struct phy *phy, union phy_configure_opts *opts) { const struct phy_configure_opts_dp *dp_opts = &opts->dp; struct qcom_edp *edp = phy_get_drvdata(phy); + int ret = 0; memcpy(&edp->dp_opts, dp_opts, sizeof(*dp_opts)); - return 0; + if (dp_opts->set_voltages) + ret = qcom_edp_set_voltages(edp, dp_opts); + + return ret; } static int qcom_edp_configure_ssc(const struct qcom_edp *edp) @@ -315,7 +381,9 @@ static int qcom_edp_set_vco_div(const struct qcom_edp *edp) static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp = phy_get_drvdata(phy); + const struct qcom_edp_cfg *cfg = edp->cfg; u32 bias0_en, drvr0_en, bias1_en, drvr1_en; + u8 ldo_config; int timeout; int ret; u32 val; @@ -332,8 +400,11 @@ static int qcom_edp_phy_power_on(struct phy *phy) if (timeout) return timeout; - writel(0x01, edp->tx0 + TXn_LDO_CONFIG); - writel(0x01, edp->tx1 + TXn_LDO_CONFIG); + + ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); writel(0x00, edp->tx0 + TXn_LANE_MODE_1); writel(0x00, edp->tx1 + TXn_LANE_MODE_1); @@ -635,6 +706,7 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) return -ENOMEM; edp->dev = dev; + edp->cfg = of_device_get_match_data(&pdev->dev); edp->edp = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(edp->edp)) -- cgit v1.2.3 From 3b7267dec4456314794632a94ff2ed30bc35c576 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 9 Aug 2022 21:07:45 -0700 Subject: phy: qcom: edp: Add SC8280XP eDP and DP PHYs The Qualcomm SC8280XP platform has a number of eDP and DP PHY instances, add support for these. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810040745.3582985-6-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-edp.c | 74 +++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 301ac422d2fe..de696108cf6e 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -100,6 +100,78 @@ struct qcom_edp { struct regulator_bulk_data supplies[2]; }; +static const u8 dp_swing_hbr_rbr[4][4] = { + { 0x08, 0x0f, 0x16, 0x1f }, + { 0x11, 0x1e, 0x1f, 0xff }, + { 0x16, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 dp_pre_emp_hbr_rbr[4][4] = { + { 0x00, 0x0d, 0x14, 0x1a }, + { 0x00, 0x0e, 0x15, 0xff }, + { 0x00, 0x0e, 0xff, 0xff }, + { 0x03, 0xff, 0xff, 0xff } +}; + +static const u8 dp_swing_hbr2_hbr3[4][4] = { + { 0x02, 0x12, 0x16, 0x1a }, + { 0x09, 0x19, 0x1f, 0xff }, + { 0x10, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 dp_pre_emp_hbr2_hbr3[4][4] = { + { 0x00, 0x0c, 0x15, 0x1b }, + { 0x02, 0x0e, 0x16, 0xff }, + { 0x02, 0x11, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_cfg dp_phy_cfg = { + .is_dp = true, + .swing_hbr_rbr = &dp_swing_hbr_rbr, + .swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3, +}; + +static const u8 edp_swing_hbr_rbr[4][4] = { + { 0x07, 0x0f, 0x16, 0x1f }, + { 0x0d, 0x16, 0x1e, 0xff }, + { 0x11, 0x1b, 0xff, 0xff }, + { 0x16, 0xff, 0xff, 0xff } +}; + +static const u8 edp_pre_emp_hbr_rbr[4][4] = { + { 0x05, 0x12, 0x17, 0x1d }, + { 0x05, 0x11, 0x18, 0xff }, + { 0x06, 0x11, 0xff, 0xff }, + { 0x00, 0xff, 0xff, 0xff } +}; + +static const u8 edp_swing_hbr2_hbr3[4][4] = { + { 0x0b, 0x11, 0x17, 0x1c }, + { 0x10, 0x19, 0x1f, 0xff }, + { 0x19, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 edp_pre_emp_hbr2_hbr3[4][4] = { + { 0x08, 0x11, 0x17, 0x1b }, + { 0x00, 0x0c, 0x13, 0xff }, + { 0x05, 0x10, 0xff, 0xff }, + { 0x00, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_cfg edp_phy_cfg = { + .is_dp = false, + .swing_hbr_rbr = &edp_swing_hbr_rbr, + .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3, +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp = phy_get_drvdata(phy); @@ -767,6 +839,8 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) static const struct of_device_id qcom_edp_phy_match_table[] = { { .compatible = "qcom,sc7280-edp-phy" }, { .compatible = "qcom,sc8180x-edp-phy" }, + { .compatible = "qcom,sc8280xp-dp-phy", .data = &dp_phy_cfg }, + { .compatible = "qcom,sc8280xp-edp-phy", .data = &edp_phy_cfg }, { } }; MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table); -- cgit v1.2.3 From 533e13305c16c63915f7cc8a36ed7ef717e15378 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 16 Jul 2022 16:54:03 +0200 Subject: phy: tegra: xusb: Only warn once about reset problems in .remove() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The single difference between returning 0 and returning an error code in a platform remove callback is that in the latter case the platform core emits a warning about the error being ignored. If reset_control_assert() fails there is already a warning, so suppress the more generic (and less helpful) by returning 0 in tegra_xusb_padctl_remove(). This is a preparation for making platform remove callbacks return void. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20220716145403.107703-1-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul --- drivers/phy/tegra/xusb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index aa5237eacd29..d04a80c436c3 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -1270,7 +1270,7 @@ static int tegra_xusb_padctl_remove(struct platform_device *pdev) padctl->soc->ops->remove(padctl); - return err; + return 0; } static __maybe_unused int tegra_xusb_padctl_suspend_noirq(struct device *dev) -- cgit v1.2.3 From d88497fb6bbdd19a136a7ac1007c60e3e38bebc4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Aug 2022 22:09:26 -0500 Subject: phy: qualcomm: phy-qcom-qmp: add support for combo USB3+DP phy on SDM845 Define configuration to be used by combo USB3 + DisplayPort phy on SDM845 SoC family. It closely follows sc7180, however like the main USB3 phy it uses the qmp_v3_usb3phy_cfg config. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810030926.2794179-1-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 4b1828976104..e9722d8aae59 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -903,6 +903,43 @@ static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { .dp_cfg = &sc7180_dpphy_cfg, }; +static const struct qmp_phy_cfg sdm845_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = { + .usb_cfg = &sdm845_usb3phy_cfg, + .dp_cfg = &sc7180_dpphy_cfg, +}; + static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -2441,6 +2478,10 @@ static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { .compatible = "qcom,sc7180-qmp-usb3-dp-phy", .data = &sc7180_usb3dpphy_cfg, }, + { + .compatible = "qcom,sdm845-qmp-usb3-dp-phy", + .data = &sdm845_usb3dpphy_cfg, + }, { .compatible = "qcom,sm8250-qmp-usb3-dp-phy", .data = &sm8250_usb3dpphy_cfg, -- cgit v1.2.3 From 712e5dffe9115ba3cf0dc9969b5d8f113f81ebda Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 9 Aug 2022 21:23:01 -0700 Subject: phy: qcom-qmp-combo: Parameterize swing and pre_emphasis tables The swing and pre-emphasis tables differ between different PHY versions, or perhaps between different platforms. In particular in order to introduce SC8280XP these tables needs to be replaced. Make it possible to specify these tables per PHY config. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810042303.3583194-3-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 86 +++++++++++++++++++------------ 1 file changed, 54 insertions(+), 32 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index e9722d8aae59..d7df3270e57c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -618,6 +618,34 @@ static struct qmp_regulator_data qmp_phy_vreg_l[] = { { .name = "vdda-pll", .enable_load = 36000 }, }; +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { + { 0x00, 0x0c, 0x15, 0x1a }, + { 0x02, 0x0e, 0x16, 0xff }, + { 0x02, 0x11, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { + { 0x02, 0x12, 0x16, 0x1a }, + { 0x09, 0x19, 0x1f, 0xff }, + { 0x10, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { + { 0x00, 0x0c, 0x14, 0x19 }, + { 0x00, 0x0b, 0x12, 0xff }, + { 0x00, 0x0b, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { + { 0x08, 0x0f, 0x16, 0x1f }, + { 0x11, 0x1e, 0x1f, 0xff }, + { 0x19, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + struct qmp_phy; /* struct qmp_phy_cfg - per-PHY initialization config */ @@ -649,6 +677,12 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *serdes_tbl_hbr3; int serdes_tbl_hbr3_num; + /* DP PHY swing and pre_emphasis tables */ + const u8 (*swing_hbr_rbr)[4][4]; + const u8 (*swing_hbr3_hbr2)[4][4]; + const u8 (*pre_emphasis_hbr_rbr)[4][4]; + const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; + /* DP PHY callbacks */ int (*configure_dp_phy)(struct qmp_phy *qphy); void (*configure_dp_tx)(struct qmp_phy *qphy); @@ -881,6 +915,11 @@ static const struct qmp_phy_cfg sc7180_dpphy_cfg = { .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), + .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, + .clk_list = qmp_v3_phy_clk_l, .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), .reset_list = sc7180_usb3phy_reset_l, @@ -994,6 +1033,11 @@ static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), + .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, + .clk_list = qmp_v3_phy_clk_l, .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), .reset_list = sc7180_usb3phy_reset_l, @@ -1069,6 +1113,11 @@ static const struct qmp_phy_cfg sm8250_dpphy_cfg = { .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), + .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, + .clk_list = qmp_v4_phy_clk_l, .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), .reset_list = msm8996_usb3phy_reset_l, @@ -1206,38 +1255,11 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); } -static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { - { 0x00, 0x0c, 0x15, 0x1a }, - { 0x02, 0x0e, 0x16, 0xff }, - { 0x02, 0x11, 0xff, 0xff }, - { 0x04, 0xff, 0xff, 0xff } -}; - -static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { - { 0x02, 0x12, 0x16, 0x1a }, - { 0x09, 0x19, 0x1f, 0xff }, - { 0x10, 0x1f, 0xff, 0xff }, - { 0x1f, 0xff, 0xff, 0xff } -}; - -static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { - { 0x00, 0x0c, 0x14, 0x19 }, - { 0x00, 0x0b, 0x12, 0xff }, - { 0x00, 0x0b, 0xff, 0xff }, - { 0x04, 0xff, 0xff, 0xff } -}; - -static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { - { 0x08, 0x0f, 0x16, 0x1f }, - { 0x11, 0x1e, 0x1f, 0xff }, - { 0x19, 0x1f, 0xff, 0xff }, - { 0x1f, 0xff, 0xff, 0xff } -}; - static int qcom_qmp_phy_combo_configure_dp_swing(struct qmp_phy *qphy, unsigned int drv_lvl_reg, unsigned int emp_post_reg) { const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + const struct qmp_phy_cfg *cfg = qphy->cfg; unsigned int v_level = 0, p_level = 0; u8 voltage_swing_cfg, pre_emphasis_cfg; int i; @@ -1248,11 +1270,11 @@ static int qcom_qmp_phy_combo_configure_dp_swing(struct qmp_phy *qphy, } if (dp_opts->link_rate <= 2700) { - voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; - pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; + voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; + pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; } else { - voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; - pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; + voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; + pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; } /* TODO: Move check to config check */ -- cgit v1.2.3 From c0c7769cdae24467b99d45b9d1073940d7a39664 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 9 Aug 2022 21:23:02 -0700 Subject: phy: qcom-qmp: Add SC8280XP USB3 UNI phy The SC8280XP platform has two instances of the 5nm USB3 UNI phy attached to the multi-port USB controller, add definition for these. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810042303.3583194-4-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 12 +++ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 137 +++++++++++++++++++++++++++++ 2 files changed, 149 insertions(+) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h index 61a44519f969..e1f2faa2493d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h @@ -7,11 +7,23 @@ #define QCOM_PHY_QMP_PCS_V5_H_ /* Only for QMP V5 PHY - USB/PCIe PCS registers */ +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4 +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8 +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V5_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_V5_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V5_PCS_EQ_CONFIG1 0x1dc #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 +#define QPHY_V5_PCS_EQ_CONFIG5 0x1ec #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 1d270356a97f..ce0e2acb7094 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1338,6 +1338,111 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; +static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), +}; + +static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), +}; + +static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), +}; + +static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), +}; + struct qmp_phy; /* struct qmp_phy_cfg - per-PHY initialization config */ @@ -1633,6 +1738,35 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .is_dual_lane_phy = true, }; +static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), + .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), + .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), + .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -2594,6 +2728,9 @@ static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = { }, { .compatible = "qcom,sc8180x-qmp-usb3-phy", .data = &sm8150_usb3phy_cfg, + }, { + .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy", + .data = &sc8280xp_usb3_uniphy_cfg, }, { .compatible = "qcom,sdm845-qmp-usb3-phy", .data = &qmp_v3_usb3phy_cfg, -- cgit v1.2.3 From a2e927b0e50d1c181f602f6ab091d8349b08211c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 9 Aug 2022 21:23:03 -0700 Subject: phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys The SC8280P has two copies of an USB/DP compbo PHY, add support for this to the Qualcomm QMP PHY driver. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810042303.3583194-5-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 343 ++++++++++++++++++++- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 1 + .../qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h | 333 ++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 4 files changed, 674 insertions(+), 4 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index d7df3270e57c..d01053c64d82 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -606,6 +606,160 @@ static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), }; +static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), +}; + +static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), +}; + +static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), +}; + +static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), +}; + +static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), +}; + +static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +}; /* list of regulators */ struct qmp_regulator_data { @@ -646,6 +800,34 @@ static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { { 0x1f, 0xff, 0xff, 0xff } }; +static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { + { 0x20, 0x2c, 0x35, 0x3b }, + { 0x22, 0x2e, 0x36, 0xff }, + { 0x22, 0x31, 0xff, 0xff }, + { 0x24, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { + { 0x22, 0x32, 0x36, 0x3a }, + { 0x29, 0x39, 0x3f, 0xff }, + { 0x30, 0x3f, 0xff, 0xff }, + { 0x3f, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { + { 0x20, 0x2d, 0x34, 0x3a }, + { 0x20, 0x2e, 0x35, 0xff }, + { 0x20, 0x2e, 0xff, 0xff }, + { 0x24, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { + { 0x28, 0x2f, 0x36, 0x3f }, + { 0x31, 0x3e, 0x3f, 0xff }, + { 0x36, 0x3f, 0xff, 0xff }, + { 0x3f, 0xff, 0xff, 0xff } +}; + struct qmp_phy; /* struct qmp_phy_cfg - per-PHY initialization config */ @@ -818,6 +1000,8 @@ static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); +static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy); + static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -1060,6 +1244,83 @@ static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { .dp_cfg = &sc8180x_dpphy_cfg, }; +static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), + .tx_tbl = sc8280xp_usb43dp_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), + .rx_tbl = sc8280xp_usb43dp_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), + .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = { + .type = PHY_TYPE_DP, + .nlanes = 1, + + .serdes_tbl = qmp_v5_dp_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), + .tx_tbl = qmp_v5_5nm_dp_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), + + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), + + .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, + + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, + + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, + .configure_dp_phy = qcom_qmp_v5_phy_configure_dp_phy, + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, +}; + +static const struct qmp_phy_combo_cfg sc8280xp_usb43dpphy_combo_cfg = { + .usb_cfg = &sc8280xp_usb43dp_usb_cfg, + .dp_cfg = &sc8280xp_usb43dp_dp_cfg, +}; + static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -1479,18 +1740,16 @@ static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) QSERDES_V4_TX_TX_EMP_POST1_LVL); } -static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) +static int qcom_qmp_v45_phy_configure_dp_phy(struct qmp_phy *qphy) { const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; u32 phy_vco_div, status; unsigned long pixel_freq; - u32 bias0_en, drvr0_en, bias1_en, drvr1_en; - bool reverse; writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); - reverse = qcom_qmp_phy_combo_configure_dp_mode(qphy); + qcom_qmp_phy_combo_configure_dp_mode(qphy); writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); @@ -1568,6 +1827,21 @@ static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) 10000)) return -ETIMEDOUT; + return 0; +} + +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) +{ + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 bias0_en, drvr0_en, bias1_en, drvr1_en; + bool reverse = false; + u32 status; + int ret; + + ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); + if (ret < 0) + return ret; + /* * At least for 7nm DP PHY this has to be done after enabling link * clock. @@ -1618,6 +1892,63 @@ static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) return 0; } +static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy) +{ + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 bias0_en, drvr0_en, bias1_en, drvr1_en; + bool reverse = false; + u32 status; + int ret; + + ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); + if (ret < 0) + return ret; + + if (dp_opts->lanes == 1) { + bias0_en = reverse ? 0x3e : 0x1a; + drvr0_en = reverse ? 0x13 : 0x10; + bias1_en = reverse ? 0x15 : 0x3e; + drvr1_en = reverse ? 0x10 : 0x13; + } else if (dp_opts->lanes == 2) { + bias0_en = reverse ? 0x3f : 0x15; + drvr0_en = 0x10; + bias1_en = reverse ? 0x15 : 0x3f; + drvr1_en = 0x10; + } else { + bias0_en = 0x3f; + bias1_en = 0x3f; + drvr0_en = 0x10; + drvr1_en = 0x10; + } + + writel(drvr0_en, qphy->tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); + writel(bias0_en, qphy->tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); + writel(drvr1_en, qphy->tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); + writel(bias1_en, qphy->tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); + + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); + udelay(2000); + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x0a, qphy->tx + QSERDES_V5_5NM_TX_TX_POL_INV); + writel(0x0a, qphy->tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); + + writel(0x27, qphy->tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); + writel(0x27, qphy->tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); + + writel(0x20, qphy->tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); + writel(0x20, qphy->tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); + + return 0; +} + /* * We need to calibrate the aux setting here as many times * as the caller tries @@ -2512,6 +2843,10 @@ static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", .data = &sc8180x_usb3dpphy_cfg, }, + { + .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", + .data = &sc8280xp_usb43dpphy_combo_cfg, + }, { } }; MODULE_DEVICE_TABLE(of, qcom_qmp_combo_phy_of_match_table); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h index e1f2faa2493d..04f260711ea1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h @@ -18,6 +18,7 @@ #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 #define QPHY_V5_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V5_PCS_RX_CONFIG 0x1b0 #define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1 0x1c0 #define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2 0x1c4 #define QPHY_V5_PCS_PCS_TX_RX_CONFIG 0x1d0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h new file mode 100644 index 000000000000..a1c088bd5158 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h @@ -0,0 +1,333 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_ + +/* Only for QMP V5 5NM PHY - TX registers */ +#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78 +#define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c +#define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80 +#define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00 +#define QSERDES_V5_5NM_TX_BIST_INVERT 0x04 +#define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08 +#define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL 0x0c +#define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP 0x10 +#define QSERDES_V5_5NM_TX_TX_DRV_LVL 0x14 +#define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET 0x18 +#define QSERDES_V5_5NM_TX_RESET_TSYNC_EN 0x1c +#define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN 0x20 +#define QSERDES_V5_5NM_TX_LPB_EN 0x24 +#define QSERDES_V5_5NM_TX_RES_CODE_LANE_TX 0x28 +#define QSERDES_V5_5NM_TX_RES_CODE_LANE_RX 0x2c +#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_V5_5NM_TX_PERL_LENGTH1 0x38 +#define QSERDES_V5_5NM_TX_PERL_LENGTH2 0x3c +#define QSERDES_V5_5NM_TX_SERDES_BYP_EN_OUT 0x40 +#define QSERDES_V5_5NM_TX_DEBUG_BUS_SEL 0x44 +#define QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN 0x48 +#define QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN 0x4c +#define QSERDES_V5_5NM_TX_TX_POL_INV 0x50 +#define QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN 0x54 +#define QSERDES_V5_5NM_TX_BIST_PATTERN1 0x58 +#define QSERDES_V5_5NM_TX_BIST_PATTERN2 0x5c +#define QSERDES_V5_5NM_TX_BIST_PATTERN3 0x60 +#define QSERDES_V5_5NM_TX_BIST_PATTERN4 0x64 +#define QSERDES_V5_5NM_TX_BIST_PATTERN5 0x68 +#define QSERDES_V5_5NM_TX_BIST_PATTERN6 0x6c +#define QSERDES_V5_5NM_TX_BIST_PATTERN7 0x70 +#define QSERDES_V5_5NM_TX_BIST_PATTERN8 0x74 +#define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78 +#define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c +#define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80 +#define QSERDES_V5_5NM_TX_ATB_SEL1 0x84 +#define QSERDES_V5_5NM_TX_ATB_SEL2 0x88 +#define QSERDES_V5_5NM_TX_RCV_DETECT_LVL 0x8c +#define QSERDES_V5_5NM_TX_RCV_DETECT_LVL_2 0x90 +#define QSERDES_V5_5NM_TX_PRBS_SEED1 0x94 +#define QSERDES_V5_5NM_TX_PRBS_SEED2 0x98 +#define QSERDES_V5_5NM_TX_PRBS_SEED3 0x9c +#define QSERDES_V5_5NM_TX_PRBS_SEED4 0xa0 +#define QSERDES_V5_5NM_TX_RESET_GEN 0xa4 +#define QSERDES_V5_5NM_TX_RESET_GEN_MUXES 0xa8 +#define QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN 0xac +#define QSERDES_V5_5NM_TX_VMODE_CTRL1 0xb0 +#define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_CTRL_1 0xb4 +#define QSERDES_V5_5NM_TX_BIST_STATUS 0xb8 +#define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT1 0xbc +#define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT2 0xc0 +#define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_STATUS_1 0xc4 +#define QSERDES_V5_5NM_TX_LANE_DIG_CONFIG 0xc8 +#define QSERDES_V5_5NM_TX_PI_QEC_CTRL 0xcc +#define QSERDES_V5_5NM_TX_PRE_EMPH 0xd0 +#define QSERDES_V5_5NM_TX_SW_RESET 0xd4 +#define QSERDES_V5_5NM_TX_TX_BAND 0xd8 +#define QSERDES_V5_5NM_TX_SLEW_CNTL0 0xdc +#define QSERDES_V5_5NM_TX_SLEW_CNTL1 0xe0 +#define QSERDES_V5_5NM_TX_INTERFACE_SELECT 0xe4 +#define QSERDES_V5_5NM_TX_DIG_BKUP_CTRL 0xe8 +#define QSERDES_V5_5NM_TX_DEBUG_BUS0 0xec +#define QSERDES_V5_5NM_TX_DEBUG_BUS1 0xf0 +#define QSERDES_V5_5NM_TX_DEBUG_BUS2 0xf4 +#define QSERDES_V5_5NM_TX_DEBUG_BUS3 0xf8 +#define QSERDES_V5_5NM_TX_TX_BKUP_RO_BUS 0xfc + +/* Only for QMP V5 5NM PHY - RX registers */ +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE0 0x000 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x004 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x008 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x00c +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE0 0x010 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x014 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE2 0x018 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE3 0x01c +#define QSERDES_V5_5NM_RX_UCDR_SO_SATURATION 0x020 +#define QSERDES_V5_5NM_RX_UCDR_FO_TO_SO_DELAY 0x024 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x028 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x02c +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x030 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x034 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x038 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x03c +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x040 +#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x044 +#define QSERDES_V5_5NM_RX_UCDR_PI_CTRL1 0x048 +#define QSERDES_V5_5NM_RX_UCDR_PI_CTRL2 0x04c +#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE0 0x050 +#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE1 0x054 +#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE2 0x058 +#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE3 0x05c +#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE0 0x060 +#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE1 0x064 +#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE2 0x068 +#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE3 0x06c +#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE0 0x070 +#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE1 0x074 +#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE2 0x078 +#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE3 0x07c +#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE0 0x080 +#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE1 0x084 +#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2 0x088 +#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE3 0x08c +#define QSERDES_V5_5NM_RX_RXCLK_DIV2_CTRL 0x090 +#define QSERDES_V5_5NM_RX_RX_BAND 0x094 +#define QSERDES_V5_5NM_RX_RX_TERM_BW 0x098 +#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE0 0x09c +#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE1 0x0a0 +#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2 0x0a4 +#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE3 0x0a8 +#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE0 0x0ac +#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE1 0x0b0 +#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2 0x0b4 +#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE3 0x0b8 +#define QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS 0x0bc +#define QSERDES_V5_5NM_RX_UCDR_PD_DATA_FILTER_ENABLES 0x0c0 +#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0c4 +#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0c8 +#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0cc +#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0d0 +#define QSERDES_V5_5NM_RX_AUX_CONTROL 0x0d4 +#define QSERDES_V5_5NM_RX_AUXDATA_TB 0x0d8 +#define QSERDES_V5_5NM_RX_RCLK_AUXDATA_SEL 0x0dc +#define QSERDES_V5_5NM_RX_EOM_CTRL 0x0e0 +#define QSERDES_V5_5NM_RX_AC_JTAG_ENABLE 0x0e4 +#define QSERDES_V5_5NM_RX_AC_JTAG_INITP 0x0e8 +#define QSERDES_V5_5NM_RX_AC_JTAG_INITN 0x0ec +#define QSERDES_V5_5NM_RX_AC_JTAG_LVL 0x0f0 +#define QSERDES_V5_5NM_RX_AC_JTAG_MODE 0x0f4 +#define QSERDES_V5_5NM_RX_AC_JTAG_RESET 0x0f8 +#define QSERDES_V5_5NM_RX_RX_RCVR_IQ_EN 0x0fc +#define QSERDES_V5_5NM_RX_RX_Q_EN_RATES 0x100 +#define QSERDES_V5_5NM_RX_RX_IDAC_I0_DC_OFFSETS 0x104 +#define QSERDES_V5_5NM_RX_RX_IDAC_I0BAR_DC_OFFSETS 0x108 +#define QSERDES_V5_5NM_RX_RX_IDAC_I1_DC_OFFSETS 0x10c +#define QSERDES_V5_5NM_RX_RX_IDAC_I1BAR_DC_OFFSETS 0x110 +#define QSERDES_V5_5NM_RX_RX_IDAC_Q_DC_OFFSETS 0x114 +#define QSERDES_V5_5NM_RX_RX_IDAC_QBAR_DC_OFFSETS 0x118 +#define QSERDES_V5_5NM_RX_RX_IDAC_A_DC_OFFSETS 0x11c +#define QSERDES_V5_5NM_RX_RX_IDAC_ABAR_DC_OFFSETS 0x120 +#define QSERDES_V5_5NM_RX_RX_IDAC_EN 0x124 +#define QSERDES_V5_5NM_RX_RX_IDAC_ENABLES 0x128 +#define QSERDES_V5_5NM_RX_RX_IDAC_SIGN 0x12c +#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE 0x130 +#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL1 0x134 +#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2 0x138 +#define QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET 0x13c +#define QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE 0x140 +#define QSERDES_V5_5NM_RX_RX_HIGHZ_PARRATE 0x144 +#define QSERDES_V5_5NM_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x148 +#define QSERDES_V5_5NM_RX_DFE_1 0x14c +#define QSERDES_V5_5NM_RX_DFE_2 0x150 +#define QSERDES_V5_5NM_RX_DFE_3 0x154 +#define QSERDES_V5_5NM_RX_DFE_4 0x158 +#define QSERDES_V5_5NM_RX_DFE_TAP3_CTRL 0x15c +#define QSERDES_V5_5NM_RX_DFE_TAP3_MANVAL_KTAP 0x160 +#define QSERDES_V5_5NM_RX_DFE_TAP4_CTRL 0x164 +#define QSERDES_V5_5NM_RX_DFE_TAP4_MANVAL_KTAP 0x168 +#define QSERDES_V5_5NM_RX_DFE_TAP5_CTRL 0x16c +#define QSERDES_V5_5NM_RX_DFE_TAP5_MANVAL_KTAP 0x170 +#define QSERDES_V5_5NM_RX_TX_ADPT_CTRL 0x174 +#define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1 0x178 +#define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE2 0x17c +#define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH1 0x180 +#define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH2 0x184 +#define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH1 0x188 +#define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH2 0x18c +#define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH1 0x190 +#define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH2 0x194 +#define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1 0x198 +#define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL2 0x19c +#define QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL 0x1a0 +#define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL1 0x1a4 +#define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL2 0x1a8 +#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE0 0x1ac +#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE1 0x1b0 +#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE2 0x1b4 +#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE3 0x1b8 +#define QSERDES_V5_5NM_RX_GM_CAL 0x1bc +#define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK1 0x1c0 +#define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK2 0x1c4 +#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL2 0x1c8 +#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL3 0x1cc +#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL4 0x1d0 +#define QSERDES_V5_5NM_RX_RX_IDAC_TSETTLE_LOW 0x1d4 +#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_LSB 0x1d8 +#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_MSB 0x1dc +#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1e0 +#define QSERDES_V5_5NM_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x1e4 +#define QSERDES_V5_5NM_RX_SIGDET_ENABLES 0x1e8 +#define QSERDES_V5_5NM_RX_SIGDET_CNTRL 0x1ec +#define QSERDES_V5_5NM_RX_SIGDET_LVL 0x1f0 +#define QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL 0x1f4 +#define QSERDES_V5_5NM_RX_CDR_FREEZE_UP_DN 0x1f8 +#define QSERDES_V5_5NM_RX_CDR_RESET_OVERRIDE 0x1fc +#define QSERDES_V5_5NM_RX_RX_INTERFACE_MODE 0x200 +#define QSERDES_V5_5NM_RX_JITTER_GEN_MODE 0x204 +#define QSERDES_V5_5NM_RX_SJ_AMP1 0x208 +#define QSERDES_V5_5NM_RX_SJ_AMP2 0x20c +#define QSERDES_V5_5NM_RX_SJ_PER1 0x210 +#define QSERDES_V5_5NM_RX_SJ_PER2 0x214 +#define QSERDES_V5_5NM_RX_PPM_OFFSET1 0x218 +#define QSERDES_V5_5NM_RX_PPM_OFFSET2 0x21c +#define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD1 0x220 +#define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD2 0x224 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0 0x228 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1 0x22c +#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2 0x230 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3 0x234 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4 0x238 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5 0x23c +#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6 0x240 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7 0x244 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0 0x248 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1 0x24c +#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2 0x250 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3 0x254 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4 0x258 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5 0x25c +#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6 0x260 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7 0x264 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B0 0x268 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B1 0x26c +#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B2 0x270 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B3 0x274 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B4 0x278 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B5 0x27c +#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B6 0x280 +#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B7 0x284 +#define QSERDES_V5_5NM_RX_PHPRE_CTRL 0x288 +#define QSERDES_V5_5NM_RX_PHPRE_INITVAL 0x28c +#define QSERDES_V5_5NM_RX_DFE_EN_TIMER 0x290 +#define QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET 0x294 +#define QSERDES_V5_5NM_RX_DCC_CTRL1 0x298 +#define QSERDES_V5_5NM_RX_DCC_CTRL2 0x29c +#define QSERDES_V5_5NM_RX_DCC_OFFSET 0x2a0 +#define QSERDES_V5_5NM_RX_DCC_CMUX_POSTCAL_OFFSET 0x2a4 +#define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL1 0x2a8 +#define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL2 0x2ac +#define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_CTRL_1 0x2b0 +#define QSERDES_V5_5NM_RX_RX_MARG_CTRL1 0x2b4 +#define QSERDES_V5_5NM_RX_RX_MARG_CTRL2 0x2b8 +#define QSERDES_V5_5NM_RX_RX_MARG_CTRL3 0x2bc +#define QSERDES_V5_5NM_RX_RX_MARG_CTRL_4 0x2c0 +#define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_0_1 0x2c4 +#define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_2_3 0x2c8 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL1 0x2cc +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL2 0x2d0 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE210 0x2d4 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE3 0x2d8 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE210 0x2dc +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE3 0x2e0 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE210 0x2e4 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE3 0x2e8 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE210 0x2ec +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE3 0x2f0 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE210 0x2f4 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE3 0x2f8 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE210 0x2fc +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE3 0x300 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE210 0x304 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE3 0x308 +#define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE10 0x30c +#define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x310 +#define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CTRL 0x314 +#define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CODE 0x318 +#define QSERDES_V5_5NM_RX_RES_CODE_THRESH_HIGH_AND_BYP 0x31c +#define QSERDES_V5_5NM_RX_RES_CODE_THRESH_LOW 0x320 +#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL1 0x324 +#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL2 0x328 +#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL3 0x32c +#define QSERDES_V5_5NM_RX_PI_CTRL1 0x330 +#define QSERDES_V5_5NM_RX_PI_CTRL2 0x334 +#define QSERDES_V5_5NM_RX_PI_QUAD 0x338 +#define QSERDES_V5_5NM_RX_QPI_CTRL1 0x33c +#define QSERDES_V5_5NM_RX_QPI_CTRL2 0x340 +#define QSERDES_V5_5NM_RX_QPI_QUAD 0x344 +#define QSERDES_V5_5NM_RX_IDATA1 0x348 +#define QSERDES_V5_5NM_RX_IDATA2 0x34c +#define QSERDES_V5_5NM_RX_IDATA3 0x350 +#define QSERDES_V5_5NM_RX_AC_JTAG_OUTP 0x354 +#define QSERDES_V5_5NM_RX_AC_JTAG_OUTN 0x358 +#define QSERDES_V5_5NM_RX_RX_SIGDET 0x35c +#define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_STATUS_1 0x360 +#define QSERDES_V5_5NM_RX_READ_EQCODE 0x364 +#define QSERDES_V5_5NM_RX_READ_OFFSETCODE 0x368 +#define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_LOW 0x36c +#define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_HIGH 0x370 +#define QSERDES_V5_5NM_RX_VGA_READ_CODE 0x374 +#define QSERDES_V5_5NM_RX_VTHRESH_READ_CODE 0x378 +#define QSERDES_V5_5NM_RX_DFE_TAP1_READ_CODE 0x37c +#define QSERDES_V5_5NM_RX_DFE_TAP2_READ_CODE 0x380 +#define QSERDES_V5_5NM_RX_DFE_TAP3_READ_CODE 0x384 +#define QSERDES_V5_5NM_RX_DFE_TAP4_READ_CODE 0x388 +#define QSERDES_V5_5NM_RX_DFE_TAP5_READ_CODE 0x38c +#define QSERDES_V5_5NM_RX_IDAC_STATUS_I0 0x390 +#define QSERDES_V5_5NM_RX_IDAC_STATUS_I0BAR 0x394 +#define QSERDES_V5_5NM_RX_IDAC_STATUS_I1 0x398 +#define QSERDES_V5_5NM_RX_IDAC_STATUS_I1BAR 0x39c +#define QSERDES_V5_5NM_RX_IDAC_STATUS_Q 0x3a0 +#define QSERDES_V5_5NM_RX_IDAC_STATUS_QBAR 0x3a4 +#define QSERDES_V5_5NM_RX_IDAC_STATUS_A 0x3a8 +#define QSERDES_V5_5NM_RX_IDAC_STATUS_ABAR 0x3ac +#define QSERDES_V5_5NM_RX_IDAC_STATUS_SM_ON 0x3b0 +#define QSERDES_V5_5NM_RX_IDAC_STATUS_SIGNERROR 0x3b4 +#define QSERDES_V5_5NM_RX_IVCM_CAL_STATUS 0x3b8 +#define QSERDES_V5_5NM_RX_IVCM_CAL_DEBUG_STATUS 0x3bc +#define QSERDES_V5_5NM_RX_DCC_CAL_STATUS 0x3c0 +#define QSERDES_V5_5NM_RX_DCC_READ_CODE_STATUS 0x3c4 +#define QSERDES_V5_5NM_RX_RX_MARG_DEBUG1_STATUS 0x3c8 +#define QSERDES_V5_5NM_RX_RX_MARG_DEBUG2_STATUS 0x3cc +#define QSERDES_V5_5NM_RX_RX_MARG_READ_CODE_STATUS 0x3d0 +#define QSERDES_V5_5NM_RX_EOM_ERR_CNT_LSB_STATUS 0x3d4 +#define QSERDES_V5_5NM_RX_EOM_ERR_CNT_MSB_STATUS 0x3d8 +#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_TUNE_STATUS 0x3dc +#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS1_STATUS 0x3e0 +#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS2_STATUS 0x3e4 +#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS3_STATUS 0x3e8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index b139c8af5e8b..26274e3c0cf9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -19,6 +19,7 @@ #include "phy-qcom-qmp-qserdes-com-v5.h" #include "phy-qcom-qmp-qserdes-txrx-v5.h" #include "phy-qcom-qmp-qserdes-txrx-v5_20.h" +#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h" #include "phy-qcom-qmp-qserdes-pll.h" -- cgit v1.2.3 From 71351b0e5646c8c4e758fb70942667eda096d09c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 18 Aug 2022 23:00:56 +0200 Subject: phy: move from strlcpy with unused retval to strscpy Follow the advice of the below link and prefer 'strscpy' in this subsystem. Conversion is 1:1 because the return value is not used. Generated by a coccinelle script. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220818210056.7205-1-wsa+renesas@sang-engineering.com Signed-off-by: Vinod Koul --- drivers/phy/allwinner/phy-sun4i-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index d5f3b42eb8ce..3a3831f6059a 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -768,7 +768,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) if (data->cfg->dedicated_clocks) snprintf(name, sizeof(name), "usb%d_phy", i); else - strlcpy(name, "usb_phy", sizeof(name)); + strscpy(name, "usb_phy", sizeof(name)); phy->clk = devm_clk_get(dev, name); if (IS_ERR(phy->clk)) { -- cgit v1.2.3 From f8432544f9779a6300262fc0747ada2c17f1a02d Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 30 Aug 2022 13:29:18 +0200 Subject: phy: qcom-qmp-pcie: drop pipe clock lane suffix The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220830112923.3725-26-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2d65e1f56bfc..3ddbb8e89f04 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2314,7 +2314,6 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - char prop_name[MAX_PROP_NAME]; int ret; qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); @@ -2374,8 +2373,7 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, if (!qphy->pcs_misc) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); - snprintf(prop_name, sizeof(prop_name), "pipe%d", id); - qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(qphy->pipe_clk)) { return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), "failed to get lane%d pipe clock\n", id); -- cgit v1.2.3 From 27759490cfa344ec326592015a9618ec05c2184f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 30 Aug 2022 13:29:19 +0200 Subject: phy: qcom-qmp-combo: drop unused lane reset Drop the unused lane reset pointer which isn't used by any combo PHY. Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220830112923.3725-27-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index d01053c64d82..41e7548ef0b5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -926,7 +926,6 @@ struct qmp_phy_combo_cfg { * @pipe_clk: pipe clock * @index: lane index * @qmp: QMP phy to which this lane belongs - * @lane_rst: lane's reset controller * @mode: current PHY mode * @dp_aux_cfg: Display port aux config * @dp_opts: Display port optional config @@ -946,7 +945,6 @@ struct qmp_phy { struct clk *pipe_clk; unsigned int index; struct qcom_qmp *qmp; - struct reset_control *lane_rst; enum phy_mode mode; unsigned int dp_aux_cfg; struct phy_configure_opts_dp dp_opts; -- cgit v1.2.3 From 70e25cac53a0239bffa0540e26dca2917662cea9 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 30 Aug 2022 13:29:20 +0200 Subject: phy: qcom-qmp-combo: drop pipe clock lane suffix The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220830112923.3725-28-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 41e7548ef0b5..d200cd5ca4fa 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2723,7 +2723,6 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id struct phy *generic_phy; struct qmp_phy *qphy; const struct phy_ops *ops; - char prop_name[MAX_PROP_NAME]; int ret; qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); @@ -2789,8 +2788,7 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id * Otherwise, we initialize pipe clock to NULL for * all phys that don't need this. */ - snprintf(prop_name, sizeof(prop_name), "pipe%d", id); - qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(qphy->pipe_clk)) { if (cfg->type == PHY_TYPE_USB3) { ret = PTR_ERR(qphy->pipe_clk); -- cgit v1.2.3 From 302db460333622b940cb8df1a3a140ab774445c1 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 30 Aug 2022 13:29:21 +0200 Subject: phy: qcom-qmp-pcie-msm8996: drop pipe clock lane suffix The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220830112923.3725-29-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index be6a94439b6c..7b893c66cf75 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -892,8 +892,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, if (!qphy->pcs_misc) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); - snprintf(prop_name, sizeof(prop_name), "pipe%d", id); - qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(qphy->pipe_clk)) { return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), "failed to get lane%d pipe clock\n", id); -- cgit v1.2.3 From 5337b248ad848b5c4e5fd564afdc34d98ce2ca1d Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 30 Aug 2022 13:29:22 +0200 Subject: phy: qcom-qmp-pcie-msm8996: drop reset lane suffix The lane reset is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the reset name. Update driver to support the new binding where the "lane" reset name has been deprecated by instead requesting the reset by index. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220830112923.3725-30-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 7b893c66cf75..a4ff15b289cd 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -860,7 +860,6 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - char prop_name[MAX_PROP_NAME]; int ret; qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); @@ -898,9 +897,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, "failed to get lane%d pipe clock\n", id); } - /* Get lane reset, if any */ - snprintf(prop_name, sizeof(prop_name), "lane%d", id); - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); + qphy->lane_rst = of_reset_control_get_exclusive_by_index(np, 0); if (IS_ERR(qphy->lane_rst)) { dev_err(dev, "failed to get lane%d reset\n", id); return PTR_ERR(qphy->lane_rst); -- cgit v1.2.3 From c8c5d5e89ac52a462f48264863a7a32f0c76fa1d Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 30 Aug 2022 13:29:23 +0200 Subject: phy: qcom-qmp-usb: drop pipe clock lane suffix The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220830112923.3725-31-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index ce0e2acb7094..59ed6c89979d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2630,7 +2630,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - char prop_name[MAX_PROP_NAME]; int ret; qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); @@ -2689,8 +2688,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, if (!qphy->pcs_misc) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); - snprintf(prop_name, sizeof(prop_name), "pipe%d", id); - qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(qphy->pipe_clk)) { return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), "failed to get lane%d pipe clock\n", id); -- cgit v1.2.3 From 99d9ccd97385208b78b3d88e756451f4b70119fc Mon Sep 17 00:00:00 2001 From: Vincent Shih Date: Mon, 25 Jul 2022 10:44:11 +0800 Subject: phy: usb: Add USB2.0 phy driver for Sunplus SP7021 Add USB2.0 phy driver for Sunplus SP7021 Signed-off-by: Vincent Shih Link: https://lore.kernel.org/r/1658717052-26142-2-git-send-email-vincent.sunplus@gmail.com [vkoul: remove trailing line in driver file] Signed-off-by: Vinod Koul --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/sunplus/Kconfig | 12 ++ drivers/phy/sunplus/Makefile | 2 + drivers/phy/sunplus/phy-sunplus-usb2.c | 296 +++++++++++++++++++++++++++++++++ 5 files changed, 312 insertions(+) create mode 100644 drivers/phy/sunplus/Kconfig create mode 100644 drivers/phy/sunplus/Makefile create mode 100644 drivers/phy/sunplus/phy-sunplus-usb2.c (limited to 'drivers/phy') diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 300b0f2b5f84..7bd00a11d074 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -91,6 +91,7 @@ source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" source "drivers/phy/socionext/Kconfig" source "drivers/phy/st/Kconfig" +source "drivers/phy/sunplus/Kconfig" source "drivers/phy/tegra/Kconfig" source "drivers/phy/ti/Kconfig" source "drivers/phy/intel/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 01e9efffc726..54f312c10a40 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,6 +31,7 @@ obj-y += allwinner/ \ samsung/ \ socionext/ \ st/ \ + sunplus/ \ tegra/ \ ti/ \ xilinx/ diff --git a/drivers/phy/sunplus/Kconfig b/drivers/phy/sunplus/Kconfig new file mode 100644 index 000000000000..3bd3cfb53a63 --- /dev/null +++ b/drivers/phy/sunplus/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PHY_SUNPLUS_USB + tristate "Sunplus SP7021 USB 2.0 PHY driver" + depends on OF && (SOC_SP7021 || COMPILE_TEST) + select GENERIC_PHY + help + Enable this to support the USB 2.0 PHY on Sunplus SP7021 + SoC. The USB 2.0 PHY controller supports battery charger + and synchronous signals, various power down modes including + operating, partial and suspend modes, and high-speed, + full-speed and low-speed data transfer. diff --git a/drivers/phy/sunplus/Makefile b/drivers/phy/sunplus/Makefile new file mode 100644 index 000000000000..71754d5cb545 --- /dev/null +++ b/drivers/phy/sunplus/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_SUNPLUS_USB) += phy-sunplus-usb2.o diff --git a/drivers/phy/sunplus/phy-sunplus-usb2.c b/drivers/phy/sunplus/phy-sunplus-usb2.c new file mode 100644 index 000000000000..5269968b3060 --- /dev/null +++ b/drivers/phy/sunplus/phy-sunplus-usb2.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Sunplus SP7021 USB 2.0 phy driver + * + * Copyright (C) 2022 Sunplus Technology Inc., All rights reserved. + * + * Note 1 : non-posted write command for the registers accesses of + * Sunplus SP7021. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HIGH_MASK_BITS GENMASK(31, 16) +#define LOW_MASK_BITS GENMASK(15, 0) +#define OTP_DISC_LEVEL_DEFAULT 0xd + +/* GROUP UPHY */ +#define CONFIG1 0x4 +#define J_HS_TX_PWRSAV BIT(5) +#define CONFIG3 0xc +#define J_FORCE_DISC_ON BIT(5) +#define J_DEBUG_CTRL_ADDR_MACRO BIT(0) +#define CONFIG7 0x1c +#define J_DISC 0X1f +#define CONFIG9 0x24 +#define J_ECO_PATH BIT(6) +#define CONFIG16 0x40 +#define J_TBCWAIT_MASK GENMASK(6, 5) +#define J_TBCWAIT_1P1_MS FIELD_PREP(J_TBCWAIT_MASK, 0) +#define J_TVDM_SRC_DIS_MASK GENMASK(4, 3) +#define J_TVDM_SRC_DIS_8P2_MS FIELD_PREP(J_TVDM_SRC_DIS_MASK, 3) +#define J_TVDM_SRC_EN_MASK GENMASK(2, 1) +#define J_TVDM_SRC_EN_1P6_MS FIELD_PREP(J_TVDM_SRC_EN_MASK, 0) +#define J_BC_EN BIT(0) +#define CONFIG17 0x44 +#define IBG_TRIM0_MASK GENMASK(7, 5) +#define IBG_TRIM0_SSLVHT FIELD_PREP(IBG_TRIM0_MASK, 4) +#define J_VDATREE_TRIM_MASK GENMASK(4, 1) +#define J_VDATREE_TRIM_DEFAULT FIELD_PREP(J_VDATREE_TRIM_MASK, 9) +#define CONFIG23 0x5c +#define PROB_MASK GENMASK(5, 3) +#define PROB FIELD_PREP(PROB_MASK, 7) + +/* GROUP MOON4 */ +#define UPHY_CONTROL0 0x0 +#define UPHY_CONTROL1 0x4 +#define UPHY_CONTROL2 0x8 +#define MO1_UPHY_RX_CLK_SEL BIT(6) +#define MASK_MO1_UPHY_RX_CLK_SEL BIT(6 + 16) +#define UPHY_CONTROL3 0xc +#define MO1_UPHY_PLL_POWER_OFF_SEL BIT(7) +#define MASK_MO1_UPHY_PLL_POWER_OFF_SEL BIT(7 + 16) +#define MO1_UPHY_PLL_POWER_OFF BIT(3) +#define MASK_UPHY_PLL_POWER_OFF BIT(3 + 16) + +struct sp_usbphy { + struct device *dev; + struct resource *phy_res_mem; + struct resource *moon4_res_mem; + struct reset_control *rstc; + struct clk *phy_clk; + void __iomem *phy_regs; + void __iomem *moon4_regs; + u32 disc_vol_addr_off; +}; + +static int update_disc_vol(struct sp_usbphy *usbphy) +{ + struct nvmem_cell *cell; + char *disc_name = "disc_vol"; + ssize_t otp_l = 0; + char *otp_v; + u32 val, set; + + cell = nvmem_cell_get(usbphy->dev, disc_name); + if (IS_ERR_OR_NULL(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return -EPROBE_DEFER; + } + + otp_v = nvmem_cell_read(cell, &otp_l); + nvmem_cell_put(cell); + + if (otp_v) { + set = *(otp_v + 1); + set = (set << (sizeof(char) * 8)) | *otp_v; + set = (set >> usbphy->disc_vol_addr_off) & J_DISC; + } + + if (!otp_v || set == 0) + set = OTP_DISC_LEVEL_DEFAULT; + + val = readl(usbphy->phy_regs + CONFIG7); + val = (val & ~J_DISC) | set; + writel(val, usbphy->phy_regs + CONFIG7); + + return 0; +} + +static int sp_uphy_init(struct phy *phy) +{ + struct sp_usbphy *usbphy = phy_get_drvdata(phy); + u32 val; + int ret; + + ret = clk_prepare_enable(usbphy->phy_clk); + if (ret) + goto err_clk; + + ret = reset_control_deassert(usbphy->rstc); + if (ret) + goto err_reset; + + /* Default value modification */ + writel(HIGH_MASK_BITS | 0x4002, usbphy->moon4_regs + UPHY_CONTROL0); + writel(HIGH_MASK_BITS | 0x8747, usbphy->moon4_regs + UPHY_CONTROL1); + + /* disconnect voltage */ + ret = update_disc_vol(usbphy); + if (ret < 0) + return ret; + + /* board uphy 0 internal register modification for tid certification */ + val = readl(usbphy->phy_regs + CONFIG9); + val &= ~(J_ECO_PATH); + writel(val, usbphy->phy_regs + CONFIG9); + + val = readl(usbphy->phy_regs + CONFIG1); + val &= ~(J_HS_TX_PWRSAV); + writel(val, usbphy->phy_regs + CONFIG1); + + val = readl(usbphy->phy_regs + CONFIG23); + val = (val & ~PROB) | PROB; + writel(val, usbphy->phy_regs + CONFIG23); + + /* port 0 uphy clk fix */ + writel(MASK_MO1_UPHY_RX_CLK_SEL | MO1_UPHY_RX_CLK_SEL, + usbphy->moon4_regs + UPHY_CONTROL2); + + /* battery charger */ + writel(J_TBCWAIT_1P1_MS | J_TVDM_SRC_DIS_8P2_MS | J_TVDM_SRC_EN_1P6_MS | J_BC_EN, + usbphy->phy_regs + CONFIG16); + writel(IBG_TRIM0_SSLVHT | J_VDATREE_TRIM_DEFAULT, usbphy->phy_regs + CONFIG17); + + /* chirp mode */ + writel(J_FORCE_DISC_ON | J_DEBUG_CTRL_ADDR_MACRO, usbphy->phy_regs + CONFIG3); + + return 0; + +err_reset: + reset_control_assert(usbphy->rstc); +err_clk: + clk_disable_unprepare(usbphy->phy_clk); + + return ret; +} + +static int sp_uphy_power_on(struct phy *phy) +{ + struct sp_usbphy *usbphy = phy_get_drvdata(phy); + u32 pll_pwr_on, pll_pwr_off; + + /* PLL power off/on twice */ + pll_pwr_off = (readl(usbphy->moon4_regs + UPHY_CONTROL3) & ~LOW_MASK_BITS) + | MO1_UPHY_PLL_POWER_OFF_SEL | MO1_UPHY_PLL_POWER_OFF; + pll_pwr_on = (readl(usbphy->moon4_regs + UPHY_CONTROL3) & ~LOW_MASK_BITS) + | MO1_UPHY_PLL_POWER_OFF_SEL; + + writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off, + usbphy->moon4_regs + UPHY_CONTROL3); + mdelay(1); + writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_on, + usbphy->moon4_regs + UPHY_CONTROL3); + mdelay(1); + writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off, + usbphy->moon4_regs + UPHY_CONTROL3); + mdelay(1); + writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_on, + usbphy->moon4_regs + UPHY_CONTROL3); + mdelay(1); + writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | 0x0, + usbphy->moon4_regs + UPHY_CONTROL3); + + return 0; +} + +static int sp_uphy_power_off(struct phy *phy) +{ + struct sp_usbphy *usbphy = phy_get_drvdata(phy); + u32 pll_pwr_off; + + pll_pwr_off = (readl(usbphy->moon4_regs + UPHY_CONTROL3) & ~LOW_MASK_BITS) + | MO1_UPHY_PLL_POWER_OFF_SEL | MO1_UPHY_PLL_POWER_OFF; + + writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off, + usbphy->moon4_regs + UPHY_CONTROL3); + mdelay(1); + writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | 0x0, + usbphy->moon4_regs + UPHY_CONTROL3); + + return 0; +} + +static int sp_uphy_exit(struct phy *phy) +{ + struct sp_usbphy *usbphy = phy_get_drvdata(phy); + + reset_control_assert(usbphy->rstc); + clk_disable_unprepare(usbphy->phy_clk); + + return 0; +} + +static const struct phy_ops sp_uphy_ops = { + .init = sp_uphy_init, + .power_on = sp_uphy_power_on, + .power_off = sp_uphy_power_off, + .exit = sp_uphy_exit, +}; + +static const struct of_device_id sp_uphy_dt_ids[] = { + {.compatible = "sunplus,sp7021-usb2-phy", }, + { } +}; +MODULE_DEVICE_TABLE(of, sp_uphy_dt_ids); + +static int sp_usb_phy_probe(struct platform_device *pdev) +{ + struct sp_usbphy *usbphy; + struct phy_provider *phy_provider; + struct phy *phy; + int ret; + + usbphy = devm_kzalloc(&pdev->dev, sizeof(*usbphy), GFP_KERNEL); + if (!usbphy) + return -ENOMEM; + + usbphy->dev = &pdev->dev; + + usbphy->phy_res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); + usbphy->phy_regs = devm_ioremap_resource(&pdev->dev, usbphy->phy_res_mem); + if (IS_ERR(usbphy->phy_regs)) + return PTR_ERR(usbphy->phy_regs); + + usbphy->moon4_res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "moon4"); + usbphy->moon4_regs = devm_ioremap(&pdev->dev, usbphy->moon4_res_mem->start, + resource_size(usbphy->moon4_res_mem)); + if (IS_ERR(usbphy->moon4_regs)) + return PTR_ERR(usbphy->moon4_regs); + + usbphy->phy_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(usbphy->phy_clk)) + return PTR_ERR(usbphy->phy_clk); + + usbphy->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(usbphy->rstc)) + return PTR_ERR(usbphy->rstc); + + of_property_read_u32(pdev->dev.of_node, "sunplus,disc-vol-addr-off", + &usbphy->disc_vol_addr_off); + + phy = devm_phy_create(&pdev->dev, NULL, &sp_uphy_ops); + if (IS_ERR(phy)) { + ret = -PTR_ERR(phy); + return ret; + } + + phy_set_drvdata(phy, usbphy); + phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static struct platform_driver sunplus_usb_phy_driver = { + .probe = sp_usb_phy_probe, + .driver = { + .name = "sunplus-usb2-phy", + .of_match_table = sp_uphy_dt_ids, + }, +}; +module_platform_driver(sunplus_usb_phy_driver); + +MODULE_AUTHOR("Vincent Shih "); +MODULE_DESCRIPTION("Sunplus USB 2.0 phy driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From f2e35c75893c28ebc12f8efbc1d13b8530d19263 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 5 Aug 2022 08:44:32 -0700 Subject: phy: qcom: edp: Postpone clk_set_rate until the PLL is up When the platform was booted with the involved clocks enabled the clk_set_rate() of the link and pixel clocks will perculate to the children, which will fail to update because the PHY driver has just shut down the PLL. Postpone the clock rate updates until the PLL is back online to avoid reconfiguring the clocks while the PLL is not ticking. Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220805154432.546740-1-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-edp.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index de696108cf6e..fc8ca0f3018d 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -410,31 +410,30 @@ static int qcom_edp_configure_pll(const struct qcom_edp *edp) return 0; } -static int qcom_edp_set_vco_div(const struct qcom_edp *edp) +static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel_freq) { const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; - unsigned long pixel_freq; u32 vco_div; switch (dp_opts->link_rate) { case 1620: vco_div = 0x1; - pixel_freq = 1620000000UL / 2; + *pixel_freq = 1620000000UL / 2; break; case 2700: vco_div = 0x1; - pixel_freq = 2700000000UL / 2; + *pixel_freq = 2700000000UL / 2; break; case 5400: vco_div = 0x2; - pixel_freq = 5400000000UL / 4; + *pixel_freq = 5400000000UL / 4; break; case 8100: vco_div = 0x0; - pixel_freq = 8100000000UL / 6; + *pixel_freq = 8100000000UL / 6; break; default: @@ -444,9 +443,6 @@ static int qcom_edp_set_vco_div(const struct qcom_edp *edp) writel(vco_div, edp->edp + DP_PHY_VCO_DIV); - clk_set_rate(edp->dp_link_hw.clk, dp_opts->link_rate * 100000); - clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq); - return 0; } @@ -455,6 +451,7 @@ static int qcom_edp_phy_power_on(struct phy *phy) const struct qcom_edp *edp = phy_get_drvdata(phy); const struct qcom_edp_cfg *cfg = edp->cfg; u32 bias0_en, drvr0_en, bias1_en, drvr1_en; + unsigned long pixel_freq; u8 ldo_config; int timeout; int ret; @@ -508,7 +505,7 @@ static int qcom_edp_phy_power_on(struct phy *phy) writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN); writel(0x04, edp->tx1 + TXn_TX_BAND); - ret = qcom_edp_set_vco_div(edp); + ret = qcom_edp_set_vco_div(edp, &pixel_freq); if (ret) return ret; @@ -574,8 +571,15 @@ static int qcom_edp_phy_power_on(struct phy *phy) writel(0x19, edp->edp + DP_PHY_CFG); - return readl_poll_timeout(edp->edp + DP_PHY_STATUS, - val, val & BIT(1), 500, 10000); + ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS, + val, val & BIT(1), 500, 10000); + if (ret) + return ret; + + clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000); + clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq); + + return 0; } static int qcom_edp_phy_power_off(struct phy *phy) -- cgit v1.2.3 From 29c99fb085ad53e6d5504d1f8d32e6673b9b3a2c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 20 Jul 2022 11:15:26 +0200 Subject: phy: rockchip: add support for the rk356x variant to rockchip-inno-csidphy This adds support for variant found in Rockchip RK356x SoCs. Note that only the basic operating mode is supported, in which all four CSI lines are controlled by the Rockchip ISP. Signed-off-by: Michael Riesch Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220720091527.1270365-3-michael.riesch@wolfvision.net Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/phy') diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c index ca13a604ab4f..75f948bdea6a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -27,6 +27,9 @@ #define RK3368_GRF_SOC_CON6_OFFSET 0x0418 +#define RK3568_GRF_VI_CON0 0x0340 +#define RK3568_GRF_VI_CON1 0x0344 + /* PHY */ #define CSIDPHY_CTRL_LANE_ENABLE 0x00 #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) @@ -58,9 +61,11 @@ #define RK1808_CSIDPHY_CLK_WR_THS_SETTLE 0x160 #define RK3326_CSIDPHY_CLK_WR_THS_SETTLE 0x100 #define RK3368_CSIDPHY_CLK_WR_THS_SETTLE 0x100 +#define RK3568_CSIDPHY_CLK_WR_THS_SETTLE 0x160 /* Calibration reception enable */ #define RK1808_CSIDPHY_CLK_CALIB_EN 0x168 +#define RK3568_CSIDPHY_CLK_CALIB_EN 0x168 /* * The higher 16-bit of this register is used for write protection @@ -103,6 +108,12 @@ static const struct dphy_reg rk3368_grf_dphy_regs[] = { [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8), }; +static const struct dphy_reg rk3568_grf_dphy_regs[] = { + [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3568_GRF_VI_CON0, 4, 0), + [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 4, 4), + [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 1, 8), +}; + struct hsfreq_range { u32 range_h; u8 cfg_bit; @@ -352,6 +363,15 @@ static const struct dphy_drv_data rk3368_mipidphy_drv_data = { .grf_regs = rk3368_grf_dphy_regs, }; +static const struct dphy_drv_data rk3568_mipidphy_drv_data = { + .pwrctl_offset = -1, + .ths_settle_offset = RK3568_CSIDPHY_CLK_WR_THS_SETTLE, + .calib_offset = RK3568_CSIDPHY_CLK_CALIB_EN, + .hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), + .grf_regs = rk3568_grf_dphy_regs, +}; + static const struct of_device_id rockchip_inno_csidphy_match_id[] = { { .compatible = "rockchip,px30-csi-dphy", @@ -369,6 +389,10 @@ static const struct of_device_id rockchip_inno_csidphy_match_id[] = { .compatible = "rockchip,rk3368-csi-dphy", .data = &rk3368_mipidphy_drv_data, }, + { + .compatible = "rockchip,rk3568-csi-dphy", + .data = &rk3568_mipidphy_drv_data, + }, {} }; MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id); -- cgit v1.2.3 From 2e9bffc4f713db465177238f6033f7d367d6f151 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 25 Aug 2022 21:38:34 +0200 Subject: phy: rockchip: Support PCIe v3 RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. It use a dedicated PCIe-phy. Add support for this. Initial support by Shawn Lin, modifications by Peter Geis and Frank Wunderlich. Add data-lanes property for splitting pcie-lanes across controllers. The data-lanes is an array where x=0 means lane is disabled and x > 0 means controller x is assigned to phy lane. Signed-off-by: Shawn Lin Suggested-by: Peter Geis Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220825193836.54262-4-linux@fw-web.de Signed-off-by: Vinod Koul --- drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 319 +++++++++++++++++++++++++ 3 files changed, 329 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c (limited to 'drivers/phy') diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 9022e395c056..94360fc96a6f 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE help Enable this to support the Rockchip PCIe PHY. +config PHY_ROCKCHIP_SNPS_PCIE3 + tristate "Rockchip Snps PCIe3 PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST + depends on HAS_IOMEM + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the Rockchip snps PCIe3 PHY. + config PHY_ROCKCHIP_TYPEC tristate "Rockchip TYPEC PHY Driver" depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index a5041efb5b8f..7eab129230d1 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o +obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c new file mode 100644 index 000000000000..1917edda6b47 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PCIE3.0 phy driver + * + * Copyright (C) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register for RK3568 */ +#define GRF_PCIE30PHY_CON1 0x4 +#define GRF_PCIE30PHY_CON6 0x18 +#define GRF_PCIE30PHY_CON9 0x24 +#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31)) +#define GRF_PCIE30PHY_STATUS0 0x80 +#define GRF_PCIE30PHY_WR_EN (0xf << 16) +#define SRAM_INIT_DONE(reg) (reg & BIT(14)) + +#define RK3568_BIFURCATION_LANE_0_1 BIT(0) + +/* Register for RK3588 */ +#define PHP_GRF_PCIESEL_CON 0x100 +#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 +#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 +#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 +#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) + +#define RK3588_BIFURCATION_LANE_0_1 BIT(0) +#define RK3588_BIFURCATION_LANE_2_3 BIT(1) +#define RK3588_LANE_AGGREGATION BIT(2) + +struct rockchip_p3phy_ops; + +struct rockchip_p3phy_priv { + const struct rockchip_p3phy_ops *ops; + void __iomem *mmio; + /* mode: RC, EP */ + int mode; + /* pcie30_phymode: Aggregation, Bifurcation */ + int pcie30_phymode; + struct regmap *phy_grf; + struct regmap *pipe_grf; + struct reset_control *p30phy; + struct phy *phy; + struct clk_bulk_data *clks; + int num_clks; + int num_lanes; + u32 lanes[4]; +}; + +struct rockchip_p3phy_ops { + int (*phy_init)(struct rockchip_p3phy_priv *priv); +}; + +static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + /* Actually We don't care EP/RC mode, but just record it */ + switch (submode) { + case PHY_MODE_PCIE_RC: + priv->mode = PHY_MODE_PCIE_RC; + break; + case PHY_MODE_PCIE_EP: + priv->mode = PHY_MODE_PCIE_EP; + break; + default: + dev_err(&phy->dev, "%s, invalid mode\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) +{ + struct phy *phy = priv->phy; + bool bifurcation = false; + int ret; + u32 reg; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM); + + for (int i = 0; i < priv->num_lanes; i++) { + dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); + if (priv->lanes[i] > 1) + bifurcation = true; + } + + /* Set bifurcation if needed, and it doesn't care RC/EP */ + if (bifurcation) { + dev_info(&phy->dev, "bifurcation enabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, + GRF_PCIE30PHY_DA_OCM); + } else { + dev_dbg(&phy->dev, "bifurcation disabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + GRF_PCIE30PHY_STATUS0, + reg, SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3568_ops = { + .phy_init = rockchip_p3phy_rk3568_init, +}; + +static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) +{ + u32 reg = 0; + u8 mode = 0; + int ret; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); + + /* Set bifurcation if needed */ + for (int i = 0; i < priv->num_lanes; i++) { + if (!priv->lanes[i]) + mode |= (BIT(i) << 3); + + if (priv->lanes[i] > 1) + mode |= (BIT(i) >> 1); + } + + if (!mode) + reg = RK3588_LANE_AGGREGATION; + else { + if (mode & (BIT(0) | BIT(1))) + reg |= RK3588_BIFURCATION_LANE_0_1; + + if (mode & (BIT(2) | BIT(3))) + reg |= RK3588_BIFURCATION_LANE_2_3; + } + + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); + + /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ + if (!IS_ERR(priv->pipe_grf)) { + reg = (mode & (BIT(6) | BIT(7))) >> 6; + if (reg) + regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, + (reg << 16) | reg); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY0_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + ret |= regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY1_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n", + reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3588_ops = { + .phy_init = rockchip_p3phy_rk3588_init, +}; + +static int rochchip_p3phy_init(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret); + return ret; + } + + reset_control_assert(priv->p30phy); + udelay(1); + + if (priv->ops->phy_init) { + ret = priv->ops->phy_init(priv); + if (ret) + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + } + + return ret; +} + +static int rochchip_p3phy_exit(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->p30phy); + return 0; +} + +static const struct phy_ops rochchip_p3phy_ops = { + .init = rochchip_p3phy_init, + .exit = rochchip_p3phy_exit, + .set_mode = rockchip_p3phy_set_mode, + .owner = THIS_MODULE, +}; + +static int rockchip_p3phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_p3phy_priv *priv; + struct device_node *np = dev->of_node; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->ops = of_device_get_match_data(&pdev->dev); + if (!priv->ops) { + dev_err(dev, "no of match data provided\n"); + return -EINVAL; + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) + dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); + + priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", + priv->lanes, 2, + ARRAY_SIZE(priv->lanes)); + + /* if no data-lanes assume aggregation */ + if (priv->num_lanes == -EINVAL) { + dev_dbg(dev, "no data-lanes property found\n"); + priv->num_lanes = 1; + priv->lanes[0] = 1; + } else if (priv->num_lanes < 0) { + dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes); + return priv->num_lanes; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); + if (IS_ERR(priv->p30phy)) { + return dev_err_probe(dev, PTR_ERR(priv->p30phy), + "failed to get phy reset control\n"); + } + if (!priv->p30phy) + dev_info(dev, "no phy reset control specified\n"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -ENODEV; + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_p3phy_of_match[] = { + { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops }, + { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match); + +static struct platform_driver rockchip_p3phy_driver = { + .probe = rockchip_p3phy_probe, + .driver = { + .name = "rockchip-snps-pcie3-phy", + .of_match_table = rockchip_p3phy_of_match, + }, +}; +module_platform_driver(rockchip_p3phy_driver); +MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 766ab0ded4c2cca84ac80c036ea38686ff43765b Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Tue, 30 Aug 2022 19:16:07 +0200 Subject: phy: amlogic: use devm_clk_get_enabled() to simplify the code Simplify the code by using devm_clk_get_enabled(). Signed-off-by: Heiner Kallweit Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/9308a2a3-e828-bd9d-ab83-a68376aab5c3@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c | 32 +++++--------------------- 1 file changed, 6 insertions(+), 26 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c index 54d65a6f0fcc..d2a1da8d9e58 100644 --- a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c +++ b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c @@ -388,7 +388,6 @@ static int phy_g12a_usb3_pcie_probe(struct platform_device *pdev) struct phy_g12a_usb3_pcie_priv *priv; struct phy_provider *phy_provider; void __iomem *base; - int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -408,43 +407,24 @@ static int phy_g12a_usb3_pcie_probe(struct platform_device *pdev) if (IS_ERR(priv->regmap_cr)) return PTR_ERR(priv->regmap_cr); - priv->clk_ref = devm_clk_get(dev, "ref_clk"); + priv->clk_ref = devm_clk_get_enabled(dev, "ref_clk"); if (IS_ERR(priv->clk_ref)) return PTR_ERR(priv->clk_ref); - ret = clk_prepare_enable(priv->clk_ref); - if (ret) - return ret; - priv->reset = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(priv->reset)) { - ret = PTR_ERR(priv->reset); - goto err_disable_clk_ref; - } + if (IS_ERR(priv->reset)) + return PTR_ERR(priv->reset); priv->phy = devm_phy_create(dev, np, &phy_g12a_usb3_pcie_ops); - if (IS_ERR(priv->phy)) { - ret = PTR_ERR(priv->phy); - dev_err_probe(dev, ret, "failed to create PHY\n"); - goto err_disable_clk_ref; - } + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n"); phy_set_drvdata(priv->phy, priv); dev_set_drvdata(dev, priv); phy_provider = devm_of_phy_provider_register(dev, phy_g12a_usb3_pcie_xlate); - if (IS_ERR(phy_provider)) { - ret = PTR_ERR(phy_provider); - goto err_disable_clk_ref; - } - - return 0; - -err_disable_clk_ref: - clk_disable_unprepare(priv->clk_ref); - - return ret; + return PTR_ERR_OR_ZERO(phy_provider); } static const struct of_device_id phy_g12a_usb3_pcie_of_match[] = { -- cgit v1.2.3 From f340ed8664a55a467850ec1689996e63d9ee971a Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 2 Sep 2022 14:45:42 -0400 Subject: phy: rockchip-inno-usb2: Return zero after otg sync The otg sync state patch reuses the ret variable, but fails to set it to zero after use. This leads to a situation when the otg port is in peripheral mode where the otg phy aborts halfway through setup. It also fails to account for a failure to register the extcon notifier. Fix this by using our own variable and skipping otg sync in case of failure. Fixes: 8dc60f8da22f ("phy: rockchip-inno-usb2: Sync initial otg state") Reported-by: Markus Reichl Reported-by: Michael Riesch Signed-off-by: Peter Geis Tested-by: Michael Riesch Tested-by: Markus Reichl Reviewed-by: Samuel Holland Link: https://lore.kernel.org/r/20220902184543.1234835-1-pgwipeout@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 0b1e9337ee8e..e6ededc51523 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -1124,7 +1124,7 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport, struct device_node *child_np) { - int ret; + int ret, id; rport->port_id = USB2PHY_PORT_OTG; rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; @@ -1162,13 +1162,15 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, ret = devm_extcon_register_notifier(rphy->dev, rphy->edev, EXTCON_USB_HOST, &rport->event_nb); - if (ret) + if (ret) { dev_err(rphy->dev, "register USB HOST notifier failed\n"); + goto out; + } if (!of_property_read_bool(rphy->dev->of_node, "extcon")) { /* do initial sync of usb state */ - ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); - extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret); + id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); + extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); } } -- cgit v1.2.3 From b0131107335d21d0b25019ce18d82e93b13b9559 Mon Sep 17 00:00:00 2001 From: Horatiu Vultur Date: Thu, 1 Sep 2022 14:14:55 +0200 Subject: phy: Add RGMII support on lan966x The serdes driver contains also a mux to decide which interface type to use. Currently the driver supports GMII/SGMII/QSGMII and partially RGMII. As it doesn't support all the other RGMII interfaces like RGMII_TXID/RXID/ID and it could run only at 1G. Therefore extend this for all the other speeds(10/100) and also allow the other interfaces. Signed-off-by: Horatiu Vultur Link: https://lore.kernel.org/r/20220901121455.245103-1-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul --- drivers/phy/microchip/lan966x_serdes.c | 99 +++++++++++++++++++++++++---- drivers/phy/microchip/lan966x_serdes_regs.h | 42 ++++++++++++ 2 files changed, 129 insertions(+), 12 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/microchip/lan966x_serdes.c b/drivers/phy/microchip/lan966x_serdes.c index e86a879b92b5..fbc725ffa4ab 100644 --- a/drivers/phy/microchip/lan966x_serdes.c +++ b/drivers/phy/microchip/lan966x_serdes.c @@ -42,7 +42,10 @@ #define SERDES_MUX_QSGMII(i, p, m, c) \ SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c) #define SERDES_MUX_RGMII(i, p, m, c) \ - SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII, m, c) + SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII, m, c), \ + SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_TXID, m, c), \ + SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_RXID, m, c), \ + SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_ID, m, c) static void lan_rmw_(u32 val, u32 mask, void __iomem *mem, u32 offset) { @@ -94,21 +97,29 @@ static const struct serdes_mux lan966x_serdes_muxes[] = { HSIO_HW_CFG_SD6G_1_CFG_SET(1)), SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG | - HSIO_HW_CFG_RGMII_ENA, - HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) | - HSIO_HW_CFG_RGMII_ENA_SET(BIT(0))), + HSIO_HW_CFG_RGMII_ENA | + HSIO_HW_CFG_GMII_ENA, + HSIO_HW_CFG_RGMII_0_CFG_SET(0) | + HSIO_HW_CFG_RGMII_ENA_SET(BIT(0)) | + HSIO_HW_CFG_GMII_ENA_SET(BIT(2))), SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG | - HSIO_HW_CFG_RGMII_ENA, - HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) | - HSIO_HW_CFG_RGMII_ENA_SET(BIT(1))), + HSIO_HW_CFG_RGMII_ENA | + HSIO_HW_CFG_GMII_ENA, + HSIO_HW_CFG_RGMII_1_CFG_SET(0) | + HSIO_HW_CFG_RGMII_ENA_SET(BIT(1)) | + HSIO_HW_CFG_GMII_ENA_SET(BIT(3))), SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG | - HSIO_HW_CFG_RGMII_ENA, + HSIO_HW_CFG_RGMII_ENA | + HSIO_HW_CFG_GMII_ENA, HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) | - HSIO_HW_CFG_RGMII_ENA_SET(BIT(0))), + HSIO_HW_CFG_RGMII_ENA_SET(BIT(0)) | + HSIO_HW_CFG_GMII_ENA_SET(BIT(5))), SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG | - HSIO_HW_CFG_RGMII_ENA, + HSIO_HW_CFG_RGMII_ENA | + HSIO_HW_CFG_GMII_ENA, HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) | - HSIO_HW_CFG_RGMII_ENA_SET(BIT(1))), + HSIO_HW_CFG_RGMII_ENA_SET(BIT(1)) | + HSIO_HW_CFG_GMII_ENA_SET(BIT(6))), }; struct serdes_ctrl { @@ -382,6 +393,67 @@ static int lan966x_sd6g40_setup(struct serdes_macro *macro, u32 idx, int mode) return lan966x_sd6g40_setup_lane(macro, conf, idx); } +static int lan966x_rgmii_setup(struct serdes_macro *macro, u32 idx, int mode) +{ + bool tx_delay = false; + bool rx_delay = false; + + /* Configure RGMII */ + lan_rmw(HSIO_RGMII_CFG_RGMII_RX_RST_SET(0) | + HSIO_RGMII_CFG_RGMII_TX_RST_SET(0) | + HSIO_RGMII_CFG_TX_CLK_CFG_SET(macro->speed == SPEED_1000 ? 1 : + macro->speed == SPEED_100 ? 2 : + macro->speed == SPEED_10 ? 3 : 0), + HSIO_RGMII_CFG_RGMII_RX_RST | + HSIO_RGMII_CFG_RGMII_TX_RST | + HSIO_RGMII_CFG_TX_CLK_CFG, + macro->ctrl->regs, HSIO_RGMII_CFG(idx)); + + if (mode == PHY_INTERFACE_MODE_RGMII || + mode == PHY_INTERFACE_MODE_RGMII_TXID) + rx_delay = true; + + if (mode == PHY_INTERFACE_MODE_RGMII || + mode == PHY_INTERFACE_MODE_RGMII_RXID) + tx_delay = true; + + /* Setup DLL configuration */ + lan_rmw(HSIO_DLL_CFG_DLL_RST_SET(0) | + HSIO_DLL_CFG_DLL_ENA_SET(rx_delay), + HSIO_DLL_CFG_DLL_RST | + HSIO_DLL_CFG_DLL_ENA, + macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x0 : 0x2)); + + lan_rmw(HSIO_DLL_CFG_DELAY_ENA_SET(rx_delay), + HSIO_DLL_CFG_DELAY_ENA, + macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x0 : 0x2)); + + lan_rmw(HSIO_DLL_CFG_DLL_RST_SET(0) | + HSIO_DLL_CFG_DLL_ENA_SET(tx_delay), + HSIO_DLL_CFG_DLL_RST | + HSIO_DLL_CFG_DLL_ENA, + macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x1 : 0x3)); + + lan_rmw(HSIO_DLL_CFG_DELAY_ENA_SET(tx_delay), + HSIO_DLL_CFG_DELAY_ENA, + macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x1 : 0x3)); + + return 0; +} + +static int serdes_set_speed(struct phy *phy, int speed) +{ + struct serdes_macro *macro = phy_get_drvdata(phy); + + if (!phy_interface_mode_is_rgmii(macro->mode)) + return 0; + + macro->speed = speed; + lan966x_rgmii_setup(macro, macro->idx - (SERDES6G_MAX + 1), macro->mode); + + return 0; +} + static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct serdes_macro *macro = phy_get_drvdata(phy); @@ -424,7 +496,9 @@ static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) macro->mode); if (macro->idx < RGMII_MAX) - return 0; + return lan966x_rgmii_setup(macro, + macro->idx - (SERDES6G_MAX + 1), + macro->mode); return -EOPNOTSUPP; } @@ -434,6 +508,7 @@ static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) static const struct phy_ops serdes_ops = { .set_mode = serdes_set_mode, + .set_speed = serdes_set_speed, .owner = THIS_MODULE, }; diff --git a/drivers/phy/microchip/lan966x_serdes_regs.h b/drivers/phy/microchip/lan966x_serdes_regs.h index ea30f64ffd5c..ac54cd01fea6 100644 --- a/drivers/phy/microchip/lan966x_serdes_regs.h +++ b/drivers/phy/microchip/lan966x_serdes_regs.h @@ -206,4 +206,46 @@ enum lan966x_target { #define HSIO_HW_CFG_QSGMII_ENA_GET(x)\ FIELD_GET(HSIO_HW_CFG_QSGMII_ENA, x) +/* HSIO:HW_CFGSTAT:RGMII_CFG */ +#define HSIO_RGMII_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 20, r, 2, 4) + +#define HSIO_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2) +#define HSIO_RGMII_CFG_TX_CLK_CFG_SET(x)\ + FIELD_PREP(HSIO_RGMII_CFG_TX_CLK_CFG, x) +#define HSIO_RGMII_CFG_TX_CLK_CFG_GET(x)\ + FIELD_GET(HSIO_RGMII_CFG_TX_CLK_CFG, x) + +#define HSIO_RGMII_CFG_RGMII_TX_RST BIT(1) +#define HSIO_RGMII_CFG_RGMII_TX_RST_SET(x)\ + FIELD_PREP(HSIO_RGMII_CFG_RGMII_TX_RST, x) +#define HSIO_RGMII_CFG_RGMII_TX_RST_GET(x)\ + FIELD_GET(HSIO_RGMII_CFG_RGMII_TX_RST, x) + +#define HSIO_RGMII_CFG_RGMII_RX_RST BIT(0) +#define HSIO_RGMII_CFG_RGMII_RX_RST_SET(x)\ + FIELD_PREP(HSIO_RGMII_CFG_RGMII_RX_RST, x) +#define HSIO_RGMII_CFG_RGMII_RX_RST_GET(x)\ + FIELD_GET(HSIO_RGMII_CFG_RGMII_RX_RST, x) + +/* HSIO:HW_CFGSTAT:DLL_CFG */ +#define HSIO_DLL_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 36, r, 4, 4) + +#define HSIO_DLL_CFG_DELAY_ENA BIT(2) +#define HSIO_DLL_CFG_DELAY_ENA_SET(x)\ + FIELD_PREP(HSIO_DLL_CFG_DELAY_ENA, x) +#define HSIO_DLL_CFG_DELAY_ENA_GET(x)\ + FIELD_GET(HSIO_DLL_CFG_DELAY_ENA, x) + +#define HSIO_DLL_CFG_DLL_ENA BIT(1) +#define HSIO_DLL_CFG_DLL_ENA_SET(x)\ + FIELD_PREP(HSIO_DLL_CFG_DLL_ENA, x) +#define HSIO_DLL_CFG_DLL_ENA_GET(x)\ + FIELD_GET(HSIO_DLL_CFG_DLL_ENA, x) + +#define HSIO_DLL_CFG_DLL_RST BIT(0) +#define HSIO_DLL_CFG_DLL_RST_SET(x)\ + FIELD_PREP(HSIO_DLL_CFG_DLL_RST, x) +#define HSIO_DLL_CFG_DLL_RST_GET(x)\ + FIELD_GET(HSIO_DLL_CFG_DLL_RST, x) + #endif /* _LAN966X_HSIO_REGS_H_ */ -- cgit v1.2.3 From 95153de6b92818a132b9a2f7361ecd6e191f6aad Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 6 Sep 2022 09:45:48 +0200 Subject: phy: qcom-qmp-pcie: drop if (table) conditions Drop unused if (table) conditions, since the function qcom_qmp_phy_pcie_configure_lane() has this check anyway. Signed-off-by: Dmitry Baryshkov Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220906074550.4383-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 3ddbb8e89f04..536a6ac835c1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1930,8 +1930,7 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) int serdes_tbl_num = cfg->serdes_tbl_num; qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); - if (cfg->serdes_tbl_sec) - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); return 0; @@ -2037,44 +2036,38 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) /* Tx, Rx, and PCS configurations */ qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, + qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, + qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 2); } qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, + qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); if (cfg->is_dual_lane_phy) { qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, + qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 2); } qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, cfg->pcs_tbl_num_sec); qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); - if (cfg->pcs_misc_tbl_sec) - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, + qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec); /* -- cgit v1.2.3 From 278786153b908f225e1f6ac88b6bbd3fee7253d1 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 6 Sep 2022 09:45:49 +0200 Subject: phy: qcom-qmp-pcie: shorten function prefixes The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220906074550.4383-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 137 ++++++++++++++----------------- 1 file changed, 63 insertions(+), 74 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 536a6ac835c1..3766a6d44e87 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1891,7 +1891,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .pwrdn_delay_max = 1005, /* us */ }; -static void qcom_qmp_phy_pcie_configure_lane(void __iomem *base, +static void qmp_pcie_configure_lane(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num, @@ -1914,29 +1914,28 @@ static void qcom_qmp_phy_pcie_configure_lane(void __iomem *base, } } -static void qcom_qmp_phy_pcie_configure(void __iomem *base, - const unsigned int *regs, - const struct qmp_phy_init_tbl tbl[], - int num) +static void qmp_pcie_configure(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num) { - qcom_qmp_phy_pcie_configure_lane(base, regs, tbl, num, 0xff); + qmp_pcie_configure_lane(base, regs, tbl, num, 0xff); } -static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) +static int qmp_pcie_serdes_init(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, - cfg->serdes_tbl_num_sec); + qmp_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + qmp_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); return 0; } -static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) +static int qmp_pcie_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -1984,7 +1983,7 @@ err_disable_regulators: return ret; } -static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) +static int qmp_pcie_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -1998,21 +1997,21 @@ static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_pcie_init(struct phy *phy) +static int qmp_pcie_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; int ret; dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - ret = qcom_qmp_phy_pcie_com_init(qphy); + ret = qmp_pcie_com_init(qphy); if (ret) return ret; return 0; } -static int qcom_qmp_phy_pcie_power_on(struct phy *phy) +static int qmp_pcie_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -2025,7 +2024,7 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) unsigned int mask, val, ready; int ret; - qcom_qmp_phy_pcie_serdes_init(qphy); + qmp_pcie_serdes_init(qphy); ret = clk_prepare_enable(qphy->pipe_clk); if (ret) { @@ -2034,41 +2033,32 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) } /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 1); - qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 1); + qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); - qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 2); + qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, + cfg->tx_tbl_num, 2); + qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 2); } - qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 1); - qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); + qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); + qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); - qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl_sec, - cfg->rx_tbl_num_sec, 2); + qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, + cfg->rx_tbl_num, 2); + qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl_sec, + cfg->rx_tbl_num_sec, 2); } - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); + qmp_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, cfg->pcs_tbl_num_sec); - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, - cfg->pcs_misc_tbl_num); - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, - cfg->pcs_misc_tbl_num_sec); + qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); + qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec); /* * Pull out PHY from POWER DOWN state. @@ -2104,7 +2094,7 @@ err_disable_pipe_clk: return ret; } -static int qcom_qmp_phy_pcie_power_off(struct phy *phy) +static int qmp_pcie_power_off(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -2129,42 +2119,42 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy) return 0; } -static int qcom_qmp_phy_pcie_exit(struct phy *phy) +static int qmp_pcie_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - qcom_qmp_phy_pcie_com_exit(qphy); + qmp_pcie_com_exit(qphy); return 0; } -static int qcom_qmp_phy_pcie_enable(struct phy *phy) +static int qmp_pcie_enable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_pcie_init(phy); + ret = qmp_pcie_init(phy); if (ret) return ret; - ret = qcom_qmp_phy_pcie_power_on(phy); + ret = qmp_pcie_power_on(phy); if (ret) - qcom_qmp_phy_pcie_exit(phy); + qmp_pcie_exit(phy); return ret; } -static int qcom_qmp_phy_pcie_disable(struct phy *phy) +static int qmp_pcie_disable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_pcie_power_off(phy); + ret = qmp_pcie_power_off(phy); if (ret) return ret; - return qcom_qmp_phy_pcie_exit(phy); + + return qmp_pcie_exit(phy); } -static int qcom_qmp_phy_pcie_set_mode(struct phy *phy, - enum phy_mode mode, int submode) +static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct qmp_phy *qphy = phy_get_drvdata(phy); @@ -2173,7 +2163,7 @@ static int qcom_qmp_phy_pcie_set_mode(struct phy *phy, return 0; } -static int qcom_qmp_phy_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_vregs; @@ -2189,7 +2179,7 @@ static int qcom_qmp_phy_pcie_vreg_init(struct device *dev, const struct qmp_phy_ return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qcom_qmp_phy_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; @@ -2210,7 +2200,7 @@ static int qcom_qmp_phy_pcie_reset_init(struct device *dev, const struct qmp_phy return 0; } -static int qcom_qmp_phy_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_clks; @@ -2293,15 +2283,14 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -static const struct phy_ops qcom_qmp_phy_pcie_ops = { - .power_on = qcom_qmp_phy_pcie_enable, - .power_off = qcom_qmp_phy_pcie_disable, - .set_mode = qcom_qmp_phy_pcie_set_mode, +static const struct phy_ops qmp_pcie_ops = { + .power_on = qmp_pcie_enable, + .power_off = qmp_pcie_disable, + .set_mode = qmp_pcie_set_mode, .owner = THIS_MODULE, }; -static -int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, +static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -2372,7 +2361,7 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, "failed to get lane%d pipe clock\n", id); } - generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops); + generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); dev_err(dev, "failed to create qphy %d\n", ret); @@ -2388,7 +2377,7 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, return 0; } -static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = { +static const struct of_device_id qmp_pcie_of_match_table[] = { { .compatible = "qcom,msm8998-qmp-pcie-phy", .data = &msm8998_pciephy_cfg, @@ -2431,9 +2420,9 @@ static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = { }, { }, }; -MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_of_match_table); +MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); -static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) +static int qmp_pcie_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; struct device *dev = &pdev->dev; @@ -2461,15 +2450,15 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - ret = qcom_qmp_phy_pcie_clk_init(dev, cfg); + ret = qmp_pcie_clk_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_pcie_reset_init(dev, cfg); + ret = qmp_pcie_reset_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_pcie_vreg_init(dev, cfg); + ret = qmp_pcie_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to get regulator supplies: %d\n", @@ -2497,7 +2486,7 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) id = 0; for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ - ret = qcom_qmp_phy_pcie_create(dev, child, id, serdes, cfg); + ret = qmp_pcie_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -2532,15 +2521,15 @@ err_node_put: return ret; } -static struct platform_driver qcom_qmp_phy_pcie_driver = { - .probe = qcom_qmp_phy_pcie_probe, +static struct platform_driver qmp_pcie_driver = { + .probe = qmp_pcie_probe, .driver = { .name = "qcom-qmp-pcie-phy", - .of_match_table = qcom_qmp_phy_pcie_of_match_table, + .of_match_table = qmp_pcie_of_match_table, }, }; -module_platform_driver(qcom_qmp_phy_pcie_driver); +module_platform_driver(qmp_pcie_driver); MODULE_AUTHOR("Vivek Gautam "); MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); -- cgit v1.2.3 From ac439ce88edf68b468e8d472e09ee2b1a2be929f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 6 Sep 2022 09:45:50 +0200 Subject: phy: qcom-qmp: drop dual-lane comments Drop the obsolete and misleading dual-lane comments which gave the impression that only combo PHYs have a second lane. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220906074550.4383-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 - drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 - drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 1 - drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 1 - 4 files changed, 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index d200cd5ca4fa..af608c4dc869 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2139,7 +2139,6 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy) qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 3766a6d44e87..2923977b205a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2036,7 +2036,6 @@ static int qmp_pcie_power_on(struct phy *phy) qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); - /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index c8583f5a54bd..01a99a06fd4f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1020,7 +1020,6 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy) qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 59ed6c89979d..fba8e40441cb 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2283,7 +2283,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy) qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); -- cgit v1.2.3 From df2217ff17a8207295e77ec12a858545633bf4cb Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 6 Sep 2022 21:45:32 +0530 Subject: phy: qcom-snps: Add support for overriding phy tuning parameters Add support for overriding electrical signal tuning parameters for SNPS HS Phy. Signed-off-by: Krishna Kurapati Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1662480933-12326-3-git-send-email-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 255 +++++++++++++++++++++++++- 1 file changed, 253 insertions(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 5d203784f75d..25022949108b 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -52,6 +52,12 @@ #define USB2_SUSPEND_N BIT(2) #define USB2_SUSPEND_N_SEL BIT(3) +#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0 (0x6c) +#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1 (0x70) +#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2 (0x74) +#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78) +#define PARAM_OVRD_MASK 0xFF + #define USB2_PHY_USB_PHY_CFG0 (0x94) #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) @@ -60,12 +66,47 @@ #define REFCLK_SEL_MASK GENMASK(1, 0) #define REFCLK_SEL_DEFAULT (0x2 << 0) +#define HS_DISCONNECT_MASK GENMASK(2, 0) +#define SQUELCH_DETECTOR_MASK GENMASK(7, 5) + +#define HS_AMPLITUDE_MASK GENMASK(3, 0) +#define PREEMPHASIS_DURATION_MASK BIT(5) +#define PREEMPHASIS_AMPLITUDE_MASK GENMASK(7, 6) + +#define HS_RISE_FALL_MASK GENMASK(1, 0) +#define HS_CROSSOVER_VOLTAGE_MASK GENMASK(3, 2) +#define HS_OUTPUT_IMPEDANCE_MASK GENMASK(5, 4) + +#define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0) + static const char * const qcom_snps_hsphy_vreg_names[] = { "vdda-pll", "vdda33", "vdda18", }; #define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names) +struct override_param { + s32 value; + u8 reg_val; +}; + +struct override_param_map { + const char *prop_name; + const struct override_param *param_table; + u8 table_size; + u8 reg_offset; + u8 param_mask; +}; + +struct phy_override_seq { + bool need_update; + u8 offset; + u8 value; + u8 mask; +}; + +#define NUM_HSPHY_TUNING_PARAMS (9) + /** * struct qcom_snps_hsphy - snps hs phy attributes * @@ -91,6 +132,7 @@ struct qcom_snps_hsphy { bool phy_initialized; enum phy_mode mode; + struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS]; }; static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, @@ -173,10 +215,158 @@ static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode, return 0; } +static const struct override_param hs_disconnect_sc7280[] = { + { -272, 0 }, + { 0, 1 }, + { 317, 2 }, + { 630, 3 }, + { 973, 4 }, + { 1332, 5 }, + { 1743, 6 }, + { 2156, 7 }, +}; + +static const struct override_param squelch_det_threshold_sc7280[] = { + { -2090, 7 }, + { -1560, 6 }, + { -1030, 5 }, + { -530, 4 }, + { 0, 3 }, + { 530, 2 }, + { 1060, 1 }, + { 1590, 0 }, +}; + +static const struct override_param hs_amplitude_sc7280[] = { + { -660, 0 }, + { -440, 1 }, + { -220, 2 }, + { 0, 3 }, + { 230, 4 }, + { 440, 5 }, + { 650, 6 }, + { 890, 7 }, + { 1110, 8 }, + { 1330, 9 }, + { 1560, 10 }, + { 1780, 11 }, + { 2000, 12 }, + { 2220, 13 }, + { 2430, 14 }, + { 2670, 15 }, +}; + +static const struct override_param preemphasis_duration_sc7280[] = { + { 10000, 1 }, + { 20000, 0 }, +}; + +static const struct override_param preemphasis_amplitude_sc7280[] = { + { 10000, 1 }, + { 20000, 2 }, + { 30000, 3 }, + { 40000, 0 }, +}; + +static const struct override_param hs_rise_fall_time_sc7280[] = { + { -4100, 3 }, + { 0, 2 }, + { 2810, 1 }, + { 5430, 0 }, +}; + +static const struct override_param hs_crossover_voltage_sc7280[] = { + { -31000, 1 }, + { 0, 3 }, + { 28000, 2 }, +}; + +static const struct override_param hs_output_impedance_sc7280[] = { + { -2300000, 3 }, + { 0, 2 }, + { 2600000, 1 }, + { 6100000, 0 }, +}; + +static const struct override_param ls_fs_output_impedance_sc7280[] = { + { -1053, 15 }, + { -557, 7 }, + { 0, 3 }, + { 612, 1 }, + { 1310, 0 }, +}; + +static const struct override_param_map sc7280_snps_7nm_phy[] = { + { + "qcom,hs-disconnect-bp", + hs_disconnect_sc7280, + ARRAY_SIZE(hs_disconnect_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0, + HS_DISCONNECT_MASK + }, + { + "qcom,squelch-detector-bp", + squelch_det_threshold_sc7280, + ARRAY_SIZE(squelch_det_threshold_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0, + SQUELCH_DETECTOR_MASK + }, + { + "qcom,hs-amplitude-bp", + hs_amplitude_sc7280, + ARRAY_SIZE(hs_amplitude_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, + HS_AMPLITUDE_MASK + }, + { + "qcom,pre-emphasis-duration-bp", + preemphasis_duration_sc7280, + ARRAY_SIZE(preemphasis_duration_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, + PREEMPHASIS_DURATION_MASK, + }, + { + "qcom,pre-emphasis-amplitude-bp", + preemphasis_amplitude_sc7280, + ARRAY_SIZE(preemphasis_amplitude_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, + PREEMPHASIS_AMPLITUDE_MASK, + }, + { + "qcom,hs-rise-fall-time-bp", + hs_rise_fall_time_sc7280, + ARRAY_SIZE(hs_rise_fall_time_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2, + HS_RISE_FALL_MASK + }, + { + "qcom,hs-crossover-voltage-microvolt", + hs_crossover_voltage_sc7280, + ARRAY_SIZE(hs_crossover_voltage_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2, + HS_CROSSOVER_VOLTAGE_MASK + }, + { + "qcom,hs-output-impedance-micro-ohms", + hs_output_impedance_sc7280, + ARRAY_SIZE(hs_output_impedance_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2, + HS_OUTPUT_IMPEDANCE_MASK, + }, + { + "qcom,ls-fs-output-impedance-bp", + ls_fs_output_impedance_sc7280, + ARRAY_SIZE(ls_fs_output_impedance_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3, + LS_FS_OUTPUT_IMPEDANCE_MASK, + }, + {}, +}; + static int qcom_snps_hsphy_init(struct phy *phy) { struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); - int ret; + int ret, i; dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); @@ -223,6 +413,14 @@ static int qcom_snps_hsphy_init(struct phy *phy) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0); + for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) { + if (hsphy->update_seq_cfg[i].need_update) + qcom_snps_hsphy_write_mask(hsphy->base, + hsphy->update_seq_cfg[i].offset, + hsphy->update_seq_cfg[i].mask, + hsphy->update_seq_cfg[i].value); + } + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS); @@ -280,7 +478,10 @@ static const struct phy_ops qcom_snps_hsphy_gen_ops = { static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { { .compatible = "qcom,sm8150-usb-hs-phy", }, { .compatible = "qcom,usb-snps-hs-5nm-phy", }, - { .compatible = "qcom,usb-snps-hs-7nm-phy", }, + { + .compatible = "qcom,usb-snps-hs-7nm-phy", + .data = &sc7280_snps_7nm_phy, + }, { .compatible = "qcom,usb-snps-femto-v2-phy", }, { } }; @@ -291,6 +492,55 @@ static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = { qcom_snps_hsphy_runtime_resume, NULL) }; +static void qcom_snps_hsphy_override_param_update_val( + const struct override_param_map map, + s32 dt_val, struct phy_override_seq *seq_entry) +{ + int i; + + /* + * Param table for each param is in increasing order + * of dt values. We need to iterate over the list to + * select the entry that matches the dt value and pick + * up the corresponding register value. + */ + for (i = 0; i < map.table_size - 1; i++) { + if (map.param_table[i].value == dt_val) + break; + } + + seq_entry->need_update = true; + seq_entry->offset = map.reg_offset; + seq_entry->mask = map.param_mask; + seq_entry->value = map.param_table[i].reg_val << __ffs(map.param_mask); +} + +static void qcom_snps_hsphy_read_override_param_seq(struct device *dev) +{ + struct device_node *node = dev->of_node; + s32 val; + int ret, i; + struct qcom_snps_hsphy *hsphy; + const struct override_param_map *cfg = of_device_get_match_data(dev); + + if (!cfg) + return; + + hsphy = dev_get_drvdata(dev); + + for (i = 0; cfg[i].prop_name != NULL; i++) { + ret = of_property_read_s32(node, cfg[i].prop_name, &val); + if (ret) + continue; + + qcom_snps_hsphy_override_param_update_val(cfg[i], val, + &hsphy->update_seq_cfg[i]); + dev_dbg(&hsphy->phy->dev, "Read param: %s dt_val: %d reg_val: 0x%x\n", + cfg[i].prop_name, val, hsphy->update_seq_cfg[i].value); + + } +} + static int qcom_snps_hsphy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -352,6 +602,7 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev) dev_set_drvdata(dev, hsphy); phy_set_drvdata(generic_phy, hsphy); + qcom_snps_hsphy_read_override_param_seq(dev); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (!IS_ERR(phy_provider)) -- cgit v1.2.3 From 677c577e1762afaaee452ababe1c070c24c647c0 Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Fri, 9 Sep 2022 09:47:09 +0000 Subject: phy: usb: sunplus: Fix return value check in update_disc_vol() In case of error, the function nvmem_cell_read() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: 99d9ccd97385 ("phy: usb: Add USB2.0 phy driver for Sunplus SP7021") Signed-off-by: Wei Yongjun Link: https://lore.kernel.org/r/20220909094709.1790970-1-weiyongjun@huaweicloud.com Signed-off-by: Vinod Koul --- drivers/phy/sunplus/phy-sunplus-usb2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/sunplus/phy-sunplus-usb2.c b/drivers/phy/sunplus/phy-sunplus-usb2.c index 5269968b3060..b932087c55b2 100644 --- a/drivers/phy/sunplus/phy-sunplus-usb2.c +++ b/drivers/phy/sunplus/phy-sunplus-usb2.c @@ -92,13 +92,13 @@ static int update_disc_vol(struct sp_usbphy *usbphy) otp_v = nvmem_cell_read(cell, &otp_l); nvmem_cell_put(cell); - if (otp_v) { + if (!IS_ERR(otp_v)) { set = *(otp_v + 1); set = (set << (sizeof(char) * 8)) | *otp_v; set = (set >> usbphy->disc_vol_addr_off) & J_DISC; } - if (!otp_v || set == 0) + if (IS_ERR(otp_v) || set == 0) set = OTP_DISC_LEVEL_DEFAULT; val = readl(usbphy->phy_regs + CONFIG7); -- cgit v1.2.3 From af96579dc31761a5f5bcb207d046764f1183069a Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Mon, 12 Sep 2022 14:26:50 +0530 Subject: phy: ti: gmii-sel: Add support for CPSW5G GMII SEL in J7200 Each of the CPSW5G ports in J7200 support additional modes like QSGMII. Add a new compatible for J7200 to support the additional modes. In TI's J7200, each of the CPSW5G ethernet interfaces can act as a QSGMII or QSGMII-SUB port. The QSGMII interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. To indicate the interface which will serve as the main QSGMII interface, add a property "ti,qsgmii-main-ports", whose value indicates the port number of the interface which shall serve as the main QSGMII interface. The rest of the interfaces are then assigned QSGMII-SUB mode by default. The property "ti,qsgmii-main-ports" is used to configure the CTRLMMR_ENETx_CTRL register. Depending on the device, it is possible for more than one QSGMII main port to exist. Thus, the property "ti,qsgmii-main-ports" is defined as an array of values in order to reuse the property for other devices. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20220912085650.83263-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul --- drivers/phy/ti/phy-gmii-sel.c | 47 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index d0ab69750c6b..0bcfd6d96b4d 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -22,6 +22,12 @@ #define AM33XX_GMII_SEL_MODE_RMII 1 #define AM33XX_GMII_SEL_MODE_RGMII 2 +/* J72xx SoC specific definitions for the CONTROL port */ +#define J72XX_GMII_SEL_MODE_QSGMII 4 +#define J72XX_GMII_SEL_MODE_QSGMII_SUB 6 + +#define PHY_GMII_PORT(n) BIT((n) - 1) + enum { PHY_GMII_SEL_PORT_MODE = 0, PHY_GMII_SEL_RGMII_ID_MODE, @@ -43,6 +49,7 @@ struct phy_gmii_sel_soc_data { u32 features; const struct reg_field (*regfields)[PHY_GMII_SEL_LAST]; bool use_of_data; + u64 extra_modes; }; struct phy_gmii_sel_priv { @@ -53,6 +60,7 @@ struct phy_gmii_sel_priv { struct phy_gmii_sel_phy_priv *if_phys; u32 num_ports; u32 reg_offset; + u32 qsgmii_main_ports; }; static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode) @@ -88,10 +96,17 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode) gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII; break; + case PHY_INTERFACE_MODE_QSGMII: + if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII))) + goto unsupported; + if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1)) + gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII; + else + gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB; + break; + default: - dev_warn(dev, "port%u: unsupported mode: \"%s\"\n", - if_phy->id, phy_modes(submode)); - return -EINVAL; + goto unsupported; } if_phy->phy_if_mode = submode; @@ -123,6 +138,11 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode) } return 0; + +unsupported: + dev_warn(dev, "port%u: unsupported mode: \"%s\"\n", + if_phy->id, phy_modes(submode)); + return -EINVAL; } static const @@ -188,6 +208,13 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = { .regfields = phy_gmii_sel_fields_am654, }; +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { + .use_of_data = true, + .regfields = phy_gmii_sel_fields_am654, + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), +}; + static const struct of_device_id phy_gmii_sel_id_table[] = { { .compatible = "ti,am3352-phy-gmii-sel", @@ -209,6 +236,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = { .compatible = "ti,am654-phy-gmii-sel", .data = &phy_gmii_sel_soc_am654, }, + { + .compatible = "ti,j7200-cpsw5g-phy-gmii-sel", + .data = &phy_gmii_sel_cpsw5g_soc_j7200, + }, {} }; MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); @@ -350,6 +381,7 @@ static int phy_gmii_sel_probe(struct platform_device *pdev) struct device_node *node = dev->of_node; const struct of_device_id *of_id; struct phy_gmii_sel_priv *priv; + u32 main_ports = 1; int ret; of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node); @@ -363,6 +395,15 @@ static int phy_gmii_sel_probe(struct platform_device *pdev) priv->dev = &pdev->dev; priv->soc_data = of_id->data; priv->num_ports = priv->soc_data->num_ports; + of_property_read_u32(node, "ti,qsgmii-main-ports", &main_ports); + /* + * Ensure that main_ports is within bounds. If the property + * ti,qsgmii-main-ports is not mentioned, or the value mentioned + * is out of bounds, default to 1. + */ + if (main_ports < 1 || main_ports > 4) + main_ports = 1; + priv->qsgmii_main_ports = PHY_GMII_PORT(main_ports); priv->regmap = syscon_node_to_regmap(node->parent); if (IS_ERR(priv->regmap)) { -- cgit v1.2.3 From 4382d518d1887e62234560ea08a0203d11d28cc1 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:13 +0200 Subject: phy: qcom-qmp-combo: disable runtime PM on unbind Make sure to disable runtime PM also on driver unbind. Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index af608c4dc869..9ce2ab56be4c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2930,7 +2930,9 @@ static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) return -ENOMEM; pm_runtime_set_active(dev); - pm_runtime_enable(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; /* * Prevent runtime pm from being ON by default. Users can enable * it using power/control in sysfs. @@ -2987,13 +2989,10 @@ static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (!IS_ERR(phy_provider)) dev_info(dev, "Registered Qcom-QMP phy\n"); - else - pm_runtime_disable(dev); return PTR_ERR_OR_ZERO(phy_provider); err_node_put: - pm_runtime_disable(dev); of_node_put(child); return ret; } -- cgit v1.2.3 From beee6ed1d63f28284b3d2d9bc01c56436d4e9311 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:14 +0200 Subject: phy: qcom-qmp-combo: drop unused defines Drop defines and enums that are unused since the QMP driver split. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 9ce2ab56be4c..838f7e328b55 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -28,16 +28,11 @@ #define SW_RESET BIT(0) /* QPHY_POWER_DOWN_CONTROL */ #define SW_PWRDN BIT(0) -#define REFCLK_DRV_DSBL BIT(1) /* QPHY_START_CONTROL bits */ #define SERDES_START BIT(0) #define PCS_START BIT(1) -#define PLL_READY_GATE_EN BIT(3) /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) -#define PHYSTATUS_4_20 BIT(7) -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ -#define PCS_READY BIT(0) /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ /* DP PHY soft reset */ @@ -71,8 +66,6 @@ #define POWER_DOWN_DELAY_US_MIN 10 #define POWER_DOWN_DELAY_US_MAX 11 -#define MAX_PROP_NAME 32 - /* Define the assumed distance between lanes for underspecified device trees. */ #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 @@ -115,22 +108,14 @@ struct qmp_phy_init_tbl { /* set of registers with offsets different per-PHY */ enum qphy_reg_layout { - /* Common block control registers */ - QPHY_COM_SW_RESET, - QPHY_COM_POWER_DOWN_CONTROL, - QPHY_COM_START_CONTROL, - QPHY_COM_PCS_READY_STATUS, /* PCS registers */ QPHY_SW_RESET, QPHY_START_CTRL, - QPHY_PCS_READY_STATUS, QPHY_PCS_STATUS, QPHY_PCS_AUTONOMOUS_MODE_CTRL, QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, - /* PCS_MISC registers */ - QPHY_PCS_MISC_TYPEC_CTRL, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; -- cgit v1.2.3 From 9062e92a241b2c2ef9ba11403d73c812347e725b Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:15 +0200 Subject: phy: qcom-qmp-pcie: drop unused runtime PM implementation Drop the unused and incomplete runtime PM implementation, which was only used by USB PHYs before splitting the QMP driver. Note that the runtime PM was never disabled (and state restored) on driver unbind. This effectively reverts commit ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 38 -------------------------------- 1 file changed, 38 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2923977b205a..860620972d8a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -53,20 +53,6 @@ #define USB3_MODE BIT(0) /* enables USB3 mode */ #define DP_MODE BIT(1) /* enables DP mode */ -/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ -#define ARCVR_DTCT_EN BIT(0) -#define ALFPS_DTCT_EN BIT(1) -#define ARCVR_DTCT_EVENT_SEL BIT(4) - -/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ -#define IRQ_CLEAR BIT(0) - -/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ -#define RCVR_DETECT BIT(0) - -/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ -#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ - #define PHY_INIT_COMPLETE_TIMEOUT 10000 #define POWER_DOWN_DELAY_US_MIN 10 #define POWER_DOWN_DELAY_US_MAX 11 @@ -125,9 +111,6 @@ enum qphy_reg_layout { QPHY_START_CTRL, QPHY_PCS_READY_STATUS, QPHY_PCS_STATUS, - QPHY_PCS_AUTONOMOUS_MODE_CTRL, - QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, - QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, /* PCS_MISC registers */ QPHY_PCS_MISC_TYPEC_CTRL, @@ -2153,15 +2136,6 @@ static int qmp_pcie_disable(struct phy *phy) return qmp_pcie_exit(phy); } -static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - - qphy->mode = mode; - - return 0; -} - static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -2285,7 +2259,6 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) static const struct phy_ops qmp_pcie_ops = { .power_on = qmp_pcie_enable, .power_off = qmp_pcie_disable, - .set_mode = qmp_pcie_set_mode, .owner = THIS_MODULE, }; @@ -2474,14 +2447,6 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (!qmp->phys) return -ENOMEM; - pm_runtime_set_active(dev); - pm_runtime_enable(dev); - /* - * Prevent runtime pm from being ON by default. Users can enable - * it using power/control in sysfs. - */ - pm_runtime_forbid(dev); - id = 0; for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ @@ -2509,13 +2474,10 @@ static int qmp_pcie_probe(struct platform_device *pdev) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (!IS_ERR(phy_provider)) dev_info(dev, "Registered Qcom-QMP phy\n"); - else - pm_runtime_disable(dev); return PTR_ERR_OR_ZERO(phy_provider); err_node_put: - pm_runtime_disable(dev); of_node_put(child); return ret; } -- cgit v1.2.3 From 52d8d441a8546b836a91619a0c21cc7c4103cad4 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:16 +0200 Subject: phy: qcom-qmp-pcie: drop unused defines Drop defines and enums that are unused since the QMP driver split. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 860620972d8a..c5d8eedab4ea 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -32,32 +32,11 @@ /* QPHY_START_CONTROL bits */ #define SERDES_START BIT(0) #define PCS_START BIT(1) -#define PLL_READY_GATE_EN BIT(3) /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) #define PHYSTATUS_4_20 BIT(7) -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ -#define PCS_READY BIT(0) - -/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ -/* DP PHY soft reset */ -#define SW_DPPHY_RESET BIT(0) -/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ -#define SW_DPPHY_RESET_MUX BIT(1) -/* USB3 PHY soft reset */ -#define SW_USB3PHY_RESET BIT(2) -/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ -#define SW_USB3PHY_RESET_MUX BIT(3) - -/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ -#define USB3_MODE BIT(0) /* enables USB3 mode */ -#define DP_MODE BIT(1) /* enables DP mode */ #define PHY_INIT_COMPLETE_TIMEOUT 10000 -#define POWER_DOWN_DELAY_US_MIN 10 -#define POWER_DOWN_DELAY_US_MAX 11 - -#define MAX_PROP_NAME 32 /* Define the assumed distance between lanes for underspecified device trees. */ #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 @@ -109,11 +88,8 @@ enum qphy_reg_layout { /* PCS registers */ QPHY_SW_RESET, QPHY_START_CTRL, - QPHY_PCS_READY_STATUS, QPHY_PCS_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, - /* PCS_MISC registers */ - QPHY_PCS_MISC_TYPEC_CTRL, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; -- cgit v1.2.3 From cec61c070d408703c40446022f579ecb2aa050dc Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:17 +0200 Subject: phy: qcom-qmp-pcie-msm8996: drop unused runtime PM implementation Drop the unused and incomplete runtime PM implementation, which was only used by USB PHYs before splitting the QMP driver. Note that the runtime PM was never disabled (and state restored) on driver unbind. This effectively reverts commit ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-6-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 37 ------------------------ 1 file changed, 37 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index a4ff15b289cd..a5b9a81541c4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -53,17 +53,6 @@ #define USB3_MODE BIT(0) /* enables USB3 mode */ #define DP_MODE BIT(1) /* enables DP mode */ -/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ -#define ARCVR_DTCT_EN BIT(0) -#define ALFPS_DTCT_EN BIT(1) -#define ARCVR_DTCT_EVENT_SEL BIT(4) - -/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ -#define IRQ_CLEAR BIT(0) - -/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ -#define RCVR_DETECT BIT(0) - /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ @@ -125,9 +114,6 @@ enum qphy_reg_layout { QPHY_START_CTRL, QPHY_PCS_READY_STATUS, QPHY_PCS_STATUS, - QPHY_PCS_AUTONOMOUS_MODE_CTRL, - QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, - QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, /* PCS_MISC registers */ QPHY_PCS_MISC_TYPEC_CTRL, @@ -308,7 +294,6 @@ struct qmp_phy { unsigned int index; struct qcom_qmp *qmp; struct reset_control *lane_rst; - enum phy_mode mode; }; /** @@ -718,16 +703,6 @@ static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy) return qcom_qmp_phy_pcie_msm8996_exit(phy); } -static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy, - enum phy_mode mode, int submode) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - - qphy->mode = mode; - - return 0; -} - static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -844,7 +819,6 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = { .power_on = qcom_qmp_phy_pcie_msm8996_enable, .power_off = qcom_qmp_phy_pcie_msm8996_disable, - .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, .owner = THIS_MODULE, }; @@ -989,14 +963,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) if (!qmp->phys) return -ENOMEM; - pm_runtime_set_active(dev); - pm_runtime_enable(dev); - /* - * Prevent runtime pm from being ON by default. Users can enable - * it using power/control in sysfs. - */ - pm_runtime_forbid(dev); - id = 0; for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ @@ -1024,13 +990,10 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (!IS_ERR(phy_provider)) dev_info(dev, "Registered Qcom-QMP phy\n"); - else - pm_runtime_disable(dev); return PTR_ERR_OR_ZERO(phy_provider); err_node_put: - pm_runtime_disable(dev); of_node_put(child); return ret; } -- cgit v1.2.3 From 7936e5f32fd0ef6b123ed9e7390f3f4047c24770 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:18 +0200 Subject: phy: qcom-qmp-pcie-msm8996: drop unused defines Drop defines and enums that are unused since the QMP driver split. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220907110728.19092-7-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 27 +----------------------- 1 file changed, 1 insertion(+), 26 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index a5b9a81541c4..49df846c31e6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -36,35 +36,13 @@ /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) #define PHYSTATUS_4_20 BIT(7) -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ +/* QPHY_COM_PCS_READY_STATUS bit */ #define PCS_READY BIT(0) -/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ -/* DP PHY soft reset */ -#define SW_DPPHY_RESET BIT(0) -/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ -#define SW_DPPHY_RESET_MUX BIT(1) -/* USB3 PHY soft reset */ -#define SW_USB3PHY_RESET BIT(2) -/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ -#define SW_USB3PHY_RESET_MUX BIT(3) - -/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ -#define USB3_MODE BIT(0) /* enables USB3 mode */ -#define DP_MODE BIT(1) /* enables DP mode */ - -/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ -#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ - #define PHY_INIT_COMPLETE_TIMEOUT 10000 #define POWER_DOWN_DELAY_US_MIN 10 #define POWER_DOWN_DELAY_US_MAX 11 -#define MAX_PROP_NAME 32 - -/* Define the assumed distance between lanes for underspecified device trees. */ -#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 - struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -112,11 +90,8 @@ enum qphy_reg_layout { /* PCS registers */ QPHY_SW_RESET, QPHY_START_CTRL, - QPHY_PCS_READY_STATUS, QPHY_PCS_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, - /* PCS_MISC registers */ - QPHY_PCS_MISC_TYPEC_CTRL, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; -- cgit v1.2.3 From b3a467d9c6d1a1b6e93104bf5c093b16f2fa3c9e Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:19 +0200 Subject: phy: qcom-qmp-ufs: drop unused runtime PM implementation Drop the unused and incomplete runtime PM implementation, which was only used by USB PHYs before splitting the QMP driver. Note that the runtime PM was never disabled (and state restored) on driver unbind. This effectively reverts commit ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-8-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 38 --------------------------------- 1 file changed, 38 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 01a99a06fd4f..7bd3c992b841 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -53,17 +53,6 @@ #define USB3_MODE BIT(0) /* enables USB3 mode */ #define DP_MODE BIT(1) /* enables DP mode */ -/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ -#define ARCVR_DTCT_EN BIT(0) -#define ALFPS_DTCT_EN BIT(1) -#define ARCVR_DTCT_EVENT_SEL BIT(4) - -/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ -#define IRQ_CLEAR BIT(0) - -/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ -#define RCVR_DETECT BIT(0) - /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ @@ -125,9 +114,6 @@ enum qphy_reg_layout { QPHY_START_CTRL, QPHY_PCS_READY_STATUS, QPHY_PCS_STATUS, - QPHY_PCS_AUTONOMOUS_MODE_CTRL, - QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, - QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, /* PCS_MISC registers */ QPHY_PCS_MISC_TYPEC_CTRL, @@ -635,7 +621,6 @@ struct qmp_phy_cfg { * @pcs_misc: iomapped memory space for lane's pcs_misc * @index: lane index * @qmp: QMP phy to which this lane belongs - * @mode: current PHY mode */ struct qmp_phy { struct phy *phy; @@ -649,7 +634,6 @@ struct qmp_phy { void __iomem *pcs_misc; unsigned int index; struct qcom_qmp *qmp; - enum phy_mode mode; }; /** @@ -1117,16 +1101,6 @@ static int qcom_qmp_phy_ufs_disable(struct phy *phy) return qcom_qmp_phy_ufs_exit(phy); } -static int qcom_qmp_phy_ufs_set_mode(struct phy *phy, - enum phy_mode mode, int submode) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - - qphy->mode = mode; - - return 0; -} - static int qcom_qmp_phy_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -1162,7 +1136,6 @@ static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cf static const struct phy_ops qcom_qmp_ufs_ops = { .power_on = qcom_qmp_phy_ufs_enable, .power_off = qcom_qmp_phy_ufs_disable, - .set_mode = qcom_qmp_phy_ufs_set_mode, .owner = THIS_MODULE, }; @@ -1332,14 +1305,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) if (!qmp->phys) return -ENOMEM; - pm_runtime_set_active(dev); - pm_runtime_enable(dev); - /* - * Prevent runtime pm from being ON by default. Users can enable - * it using power/control in sysfs. - */ - pm_runtime_forbid(dev); - id = 0; for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ @@ -1356,13 +1321,10 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (!IS_ERR(phy_provider)) dev_info(dev, "Registered Qcom-QMP phy\n"); - else - pm_runtime_disable(dev); return PTR_ERR_OR_ZERO(phy_provider); err_node_put: - pm_runtime_disable(dev); of_node_put(child); return ret; } -- cgit v1.2.3 From 6d07bd6f46017aca6648fe387884916b36243096 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:20 +0200 Subject: phy: qcom-qmp-ufs: drop unused defines Drop defines and enums that are unused since the QMP driver split. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220907110728.19092-9-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 34 +-------------------------------- 1 file changed, 1 insertion(+), 33 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 7bd3c992b841..62e9007137c9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -28,39 +28,15 @@ #define SW_RESET BIT(0) /* QPHY_POWER_DOWN_CONTROL */ #define SW_PWRDN BIT(0) -#define REFCLK_DRV_DSBL BIT(1) /* QPHY_START_CONTROL bits */ #define SERDES_START BIT(0) #define PCS_START BIT(1) -#define PLL_READY_GATE_EN BIT(3) /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) -#define PHYSTATUS_4_20 BIT(7) -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ +/* QPHY_PCS_READY_STATUS bit */ #define PCS_READY BIT(0) -/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ -/* DP PHY soft reset */ -#define SW_DPPHY_RESET BIT(0) -/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ -#define SW_DPPHY_RESET_MUX BIT(1) -/* USB3 PHY soft reset */ -#define SW_USB3PHY_RESET BIT(2) -/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ -#define SW_USB3PHY_RESET_MUX BIT(3) - -/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ -#define USB3_MODE BIT(0) /* enables USB3 mode */ -#define DP_MODE BIT(1) /* enables DP mode */ - -/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ -#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ - #define PHY_INIT_COMPLETE_TIMEOUT 10000 -#define POWER_DOWN_DELAY_US_MIN 10 -#define POWER_DOWN_DELAY_US_MAX 11 - -#define MAX_PROP_NAME 32 /* Define the assumed distance between lanes for underspecified device trees. */ #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 @@ -104,19 +80,11 @@ struct qmp_phy_init_tbl { /* set of registers with offsets different per-PHY */ enum qphy_reg_layout { - /* Common block control registers */ - QPHY_COM_SW_RESET, - QPHY_COM_POWER_DOWN_CONTROL, - QPHY_COM_START_CONTROL, - QPHY_COM_PCS_READY_STATUS, /* PCS registers */ QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, - QPHY_PCS_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, - /* PCS_MISC registers */ - QPHY_PCS_MISC_TYPEC_CTRL, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; -- cgit v1.2.3 From e57655e66806750785f9121c98a962404d02395b Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:21 +0200 Subject: phy: qcom-qmp-usb: disable runtime PM on unbind Make sure to disable runtime PM also on driver unbind. Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-10-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index fba8e40441cb..b63183aaacb8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2838,7 +2838,9 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) return -ENOMEM; pm_runtime_set_active(dev); - pm_runtime_enable(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; /* * Prevent runtime pm from being ON by default. Users can enable * it using power/control in sysfs. @@ -2872,13 +2874,10 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (!IS_ERR(phy_provider)) dev_info(dev, "Registered Qcom-QMP phy\n"); - else - pm_runtime_disable(dev); return PTR_ERR_OR_ZERO(phy_provider); err_node_put: - pm_runtime_disable(dev); of_node_put(child); return ret; } -- cgit v1.2.3 From 613b30244b87d791b4da8c0a6cb06a3ca9935272 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:22 +0200 Subject: phy: qcom-qmp-usb: drop unused defines Drop defines and enums that are unused since the QMP driver split. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220907110728.19092-11-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index b63183aaacb8..c50ebe8d19bc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -28,16 +28,11 @@ #define SW_RESET BIT(0) /* QPHY_POWER_DOWN_CONTROL */ #define SW_PWRDN BIT(0) -#define REFCLK_DRV_DSBL BIT(1) /* QPHY_START_CONTROL bits */ #define SERDES_START BIT(0) #define PCS_START BIT(1) -#define PLL_READY_GATE_EN BIT(3) /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) -#define PHYSTATUS_4_20 BIT(7) -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ -#define PCS_READY BIT(0) /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ /* DP PHY soft reset */ @@ -71,8 +66,6 @@ #define POWER_DOWN_DELAY_US_MIN 10 #define POWER_DOWN_DELAY_US_MAX 11 -#define MAX_PROP_NAME 32 - /* Define the assumed distance between lanes for underspecified device trees. */ #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 @@ -115,15 +108,9 @@ struct qmp_phy_init_tbl { /* set of registers with offsets different per-PHY */ enum qphy_reg_layout { - /* Common block control registers */ - QPHY_COM_SW_RESET, - QPHY_COM_POWER_DOWN_CONTROL, - QPHY_COM_START_CONTROL, - QPHY_COM_PCS_READY_STATUS, /* PCS registers */ QPHY_SW_RESET, QPHY_START_CTRL, - QPHY_PCS_READY_STATUS, QPHY_PCS_STATUS, QPHY_PCS_AUTONOMOUS_MODE_CTRL, QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, -- cgit v1.2.3 From d44c3e1a1e02cb12496bfc7e03c7957c32f9de4c Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:23 +0200 Subject: phy: qcom-qmp: silence noisy probe Drivers should in general not log anything during unless there are errors. Drop the pointless registration info message from the QMP drivers. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-12-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 2 -- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 2 -- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 -- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 2 -- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 2 -- 5 files changed, 10 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 838f7e328b55..c03878fdf8a7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2972,8 +2972,6 @@ static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) } phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (!IS_ERR(phy_provider)) - dev_info(dev, "Registered Qcom-QMP phy\n"); return PTR_ERR_OR_ZERO(phy_provider); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 49df846c31e6..45701b498efc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -963,8 +963,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) } phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (!IS_ERR(phy_provider)) - dev_info(dev, "Registered Qcom-QMP phy\n"); return PTR_ERR_OR_ZERO(phy_provider); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index c5d8eedab4ea..e6bffb0e2da3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2448,8 +2448,6 @@ static int qmp_pcie_probe(struct platform_device *pdev) } phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (!IS_ERR(phy_provider)) - dev_info(dev, "Registered Qcom-QMP phy\n"); return PTR_ERR_OR_ZERO(phy_provider); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 62e9007137c9..28b75772cd0f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1287,8 +1287,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) } phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (!IS_ERR(phy_provider)) - dev_info(dev, "Registered Qcom-QMP phy\n"); return PTR_ERR_OR_ZERO(phy_provider); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index c50ebe8d19bc..08e0799e8832 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2859,8 +2859,6 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) } phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (!IS_ERR(phy_provider)) - dev_info(dev, "Registered Qcom-QMP phy\n"); return PTR_ERR_OR_ZERO(phy_provider); -- cgit v1.2.3 From e5cedefa7203c787ccadaa3e2400d0b8e252a0c1 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:24 +0200 Subject: phy: qcom-qmp-combo: shorten function prefixes The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-13-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 165 ++++++++++++++---------------- 1 file changed, 79 insertions(+), 86 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index c03878fdf8a7..f5d0d290d26e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1384,7 +1384,7 @@ static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { .dp_cfg = &sm8250_dpphy_cfg, }; -static void qcom_qmp_phy_combo_configure_lane(void __iomem *base, +static void qmp_combo_configure_lane(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num, @@ -1407,15 +1407,15 @@ static void qcom_qmp_phy_combo_configure_lane(void __iomem *base, } } -static void qcom_qmp_phy_combo_configure(void __iomem *base, +static void qmp_combo_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num) { - qcom_qmp_phy_combo_configure_lane(base, regs, tbl, num, 0xff); + qmp_combo_configure_lane(base, regs, tbl, num, 0xff); } -static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy) +static int qmp_combo_serdes_init(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; @@ -1423,27 +1423,27 @@ static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy) const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; - qcom_qmp_phy_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + qmp_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); if (cfg->type == PHY_TYPE_DP) { switch (dp_opts->link_rate) { case 1620: - qcom_qmp_phy_combo_configure(serdes, cfg->regs, + qmp_combo_configure(serdes, cfg->regs, cfg->serdes_tbl_rbr, cfg->serdes_tbl_rbr_num); break; case 2700: - qcom_qmp_phy_combo_configure(serdes, cfg->regs, + qmp_combo_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr, cfg->serdes_tbl_hbr_num); break; case 5400: - qcom_qmp_phy_combo_configure(serdes, cfg->regs, + qmp_combo_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr2, cfg->serdes_tbl_hbr2_num); break; case 8100: - qcom_qmp_phy_combo_configure(serdes, cfg->regs, + qmp_combo_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr3, cfg->serdes_tbl_hbr3_num); break; @@ -1499,7 +1499,7 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); } -static int qcom_qmp_phy_combo_configure_dp_swing(struct qmp_phy *qphy, +static int qmp_combo_configure_dp_swing(struct qmp_phy *qphy, unsigned int drv_lvl_reg, unsigned int emp_post_reg) { const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; @@ -1542,8 +1542,7 @@ static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; u32 bias_en, drvr_en; - if (qcom_qmp_phy_combo_configure_dp_swing(qphy, - QSERDES_V3_TX_TX_DRV_LVL, + if (qmp_combo_configure_dp_swing(qphy, QSERDES_V3_TX_TX_DRV_LVL, QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) return; @@ -1561,7 +1560,7 @@ static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); } -static bool qcom_qmp_phy_combo_configure_dp_mode(struct qmp_phy *qphy) +static bool qmp_combo_configure_dp_mode(struct qmp_phy *qphy) { u32 val; bool reverse = false; @@ -1598,7 +1597,7 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) u32 phy_vco_div, status; unsigned long pixel_freq; - qcom_qmp_phy_combo_configure_dp_mode(qphy); + qmp_combo_configure_dp_mode(qphy); writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); @@ -1718,8 +1717,7 @@ static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); - qcom_qmp_phy_combo_configure_dp_swing(qphy, - QSERDES_V4_TX_TX_DRV_LVL, + qmp_combo_configure_dp_swing(qphy, QSERDES_V4_TX_TX_DRV_LVL, QSERDES_V4_TX_TX_EMP_POST1_LVL); } @@ -1732,7 +1730,7 @@ static int qcom_qmp_v45_phy_configure_dp_phy(struct qmp_phy *qphy) writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); - qcom_qmp_phy_combo_configure_dp_mode(qphy); + qmp_combo_configure_dp_mode(qphy); writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); @@ -1976,7 +1974,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy) return 0; } -static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy) +static int qmp_combo_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -2058,7 +2056,7 @@ err_unlock: return ret; } -static int qcom_qmp_phy_combo_com_exit(struct qmp_phy *qphy) +static int qmp_combo_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -2082,7 +2080,7 @@ static int qcom_qmp_phy_combo_com_exit(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_combo_init(struct phy *phy) +static int qmp_combo_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -2090,7 +2088,7 @@ static int qcom_qmp_phy_combo_init(struct phy *phy) int ret; dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - ret = qcom_qmp_phy_combo_com_init(qphy); + ret = qmp_combo_com_init(qphy); if (ret) return ret; @@ -2100,7 +2098,7 @@ static int qcom_qmp_phy_combo_init(struct phy *phy) return 0; } -static int qcom_qmp_phy_combo_power_on(struct phy *phy) +static int qmp_combo_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -2112,7 +2110,7 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy) unsigned int mask, val, ready; int ret; - qcom_qmp_phy_combo_serdes_init(qphy); + qmp_combo_serdes_init(qphy); ret = clk_prepare_enable(qphy->pipe_clk); if (ret) { @@ -2121,32 +2119,29 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy) } /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); + qmp_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, + cfg->tx_tbl_num, 2); } /* Configure special DP tx tunings */ if (cfg->type == PHY_TYPE_DP) cfg->configure_dp_tx(qphy); - qcom_qmp_phy_combo_configure_lane(rx, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 1); + qmp_combo_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); + qmp_combo_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, + cfg->rx_tbl_num, 2); } /* Configure link rate, swing, etc. */ - if (cfg->type == PHY_TYPE_DP) { + if (cfg->type == PHY_TYPE_DP) cfg->configure_dp_phy(qphy); - } else { - qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - } + else + qmp_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ret = reset_control_deassert(qmp->ufs_reset); if (ret) @@ -2180,7 +2175,7 @@ err_disable_pipe_clk: return ret; } -static int qcom_qmp_phy_combo_power_off(struct phy *phy) +static int qmp_combo_power_off(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -2210,42 +2205,41 @@ static int qcom_qmp_phy_combo_power_off(struct phy *phy) return 0; } -static int qcom_qmp_phy_combo_exit(struct phy *phy) +static int qmp_combo_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - qcom_qmp_phy_combo_com_exit(qphy); + qmp_combo_com_exit(qphy); return 0; } -static int qcom_qmp_phy_combo_enable(struct phy *phy) +static int qmp_combo_enable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_combo_init(phy); + ret = qmp_combo_init(phy); if (ret) return ret; - ret = qcom_qmp_phy_combo_power_on(phy); + ret = qmp_combo_power_on(phy); if (ret) - qcom_qmp_phy_combo_exit(phy); + qmp_combo_exit(phy); return ret; } -static int qcom_qmp_phy_combo_disable(struct phy *phy) +static int qmp_combo_disable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_combo_power_off(phy); + ret = qmp_combo_power_off(phy); if (ret) return ret; - return qcom_qmp_phy_combo_exit(phy); + return qmp_combo_exit(phy); } -static int qcom_qmp_phy_combo_set_mode(struct phy *phy, - enum phy_mode mode, int submode) +static int qmp_combo_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct qmp_phy *qphy = phy_get_drvdata(phy); @@ -2254,7 +2248,7 @@ static int qcom_qmp_phy_combo_set_mode(struct phy *phy, return 0; } -static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy) +static void qmp_combo_enable_autonomous_mode(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; @@ -2283,7 +2277,7 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy) qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); } -static void qcom_qmp_phy_combo_disable_autonomous_mode(struct qmp_phy *qphy) +static void qmp_combo_disable_autonomous_mode(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb; @@ -2301,7 +2295,7 @@ static void qcom_qmp_phy_combo_disable_autonomous_mode(struct qmp_phy *qphy) qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); } -static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev) +static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; @@ -2318,7 +2312,7 @@ static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev) return 0; } - qcom_qmp_phy_combo_enable_autonomous_mode(qphy); + qmp_combo_enable_autonomous_mode(qphy); clk_disable_unprepare(qphy->pipe_clk); clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); @@ -2326,7 +2320,7 @@ static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev) return 0; } -static int __maybe_unused qcom_qmp_phy_combo_runtime_resume(struct device *dev) +static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; @@ -2355,12 +2349,12 @@ static int __maybe_unused qcom_qmp_phy_combo_runtime_resume(struct device *dev) return ret; } - qcom_qmp_phy_combo_disable_autonomous_mode(qphy); + qmp_combo_disable_autonomous_mode(qphy); return 0; } -static int qcom_qmp_phy_combo_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_combo_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_vregs; @@ -2392,7 +2386,7 @@ static int qcom_qmp_phy_combo_vreg_init(struct device *dev, const struct qmp_phy return 0; } -static int qcom_qmp_phy_combo_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_combo_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; @@ -2413,7 +2407,7 @@ static int qcom_qmp_phy_combo_reset_init(struct device *dev, const struct qmp_ph return 0; } -static int qcom_qmp_phy_combo_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_combo_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_clks; @@ -2681,26 +2675,25 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -static const struct phy_ops qcom_qmp_phy_combo_usb_ops = { - .init = qcom_qmp_phy_combo_enable, - .exit = qcom_qmp_phy_combo_disable, - .set_mode = qcom_qmp_phy_combo_set_mode, +static const struct phy_ops qmp_combo_usb_ops = { + .init = qmp_combo_enable, + .exit = qmp_combo_disable, + .set_mode = qmp_combo_set_mode, .owner = THIS_MODULE, }; -static const struct phy_ops qcom_qmp_phy_combo_dp_ops = { - .init = qcom_qmp_phy_combo_init, +static const struct phy_ops qmp_combo_dp_ops = { + .init = qmp_combo_init, .configure = qcom_qmp_dp_phy_configure, - .power_on = qcom_qmp_phy_combo_power_on, + .power_on = qmp_combo_power_on, .calibrate = qcom_qmp_dp_phy_calibrate, - .power_off = qcom_qmp_phy_combo_power_off, - .exit = qcom_qmp_phy_combo_exit, - .set_mode = qcom_qmp_phy_combo_set_mode, + .power_off = qmp_combo_power_off, + .exit = qmp_combo_exit, + .set_mode = qmp_combo_set_mode, .owner = THIS_MODULE, }; -static -int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id, +static int qmp_combo_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -2786,9 +2779,9 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id } if (cfg->type == PHY_TYPE_DP) - ops = &qcom_qmp_phy_combo_dp_ops; + ops = &qmp_combo_dp_ops; else - ops = &qcom_qmp_phy_combo_usb_ops; + ops = &qmp_combo_usb_ops; generic_phy = devm_phy_create(dev, np, ops); if (IS_ERR(generic_phy)) { @@ -2806,7 +2799,7 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id return 0; } -static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { +static const struct of_device_id qmp_combo_of_match_table[] = { { .compatible = "qcom,sc7180-qmp-usb3-dp-phy", .data = &sc7180_usb3dpphy_cfg, @@ -2829,14 +2822,14 @@ static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { }, { } }; -MODULE_DEVICE_TABLE(of, qcom_qmp_combo_phy_of_match_table); +MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); -static const struct dev_pm_ops qcom_qmp_phy_combo_pm_ops = { - SET_RUNTIME_PM_OPS(qcom_qmp_phy_combo_runtime_suspend, - qcom_qmp_phy_combo_runtime_resume, NULL) +static const struct dev_pm_ops qmp_combo_pm_ops = { + SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, + qmp_combo_runtime_resume, NULL) }; -static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) +static int qmp_combo_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; struct device *dev = &pdev->dev; @@ -2889,15 +2882,15 @@ static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) mutex_init(&qmp->phy_mutex); - ret = qcom_qmp_phy_combo_clk_init(dev, cfg); + ret = qmp_combo_clk_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_combo_reset_init(dev, cfg); + ret = qmp_combo_reset_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_combo_vreg_init(dev, cfg); + ret = qmp_combo_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to get regulator supplies: %d\n", @@ -2931,7 +2924,7 @@ static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) serdes = dp_serdes; /* Create per-lane phy */ - ret = qcom_qmp_phy_combo_create(dev, child, id, serdes, cfg); + ret = qmp_combo_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -2949,7 +2942,7 @@ static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) serdes = usb_serdes; /* Create per-lane phy */ - ret = qcom_qmp_phy_combo_create(dev, child, id, serdes, cfg); + ret = qmp_combo_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -2980,16 +2973,16 @@ err_node_put: return ret; } -static struct platform_driver qcom_qmp_phy_combo_driver = { - .probe = qcom_qmp_phy_combo_probe, +static struct platform_driver qmp_combo_driver = { + .probe = qmp_combo_probe, .driver = { .name = "qcom-qmp-combo-phy", - .pm = &qcom_qmp_phy_combo_pm_ops, - .of_match_table = qcom_qmp_combo_phy_of_match_table, + .pm = &qmp_combo_pm_ops, + .of_match_table = qmp_combo_of_match_table, }, }; -module_platform_driver(qcom_qmp_phy_combo_driver); +module_platform_driver(qmp_combo_driver); MODULE_AUTHOR("Vivek Gautam "); MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); -- cgit v1.2.3 From d0eec88b38a4302113508a41366efc7ce9446cae Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:25 +0200 Subject: phy: qcom-qmp-pcie-msm8996: drop unused secondary init tables Drop the secondary register initialisation tables which aren't used by this driver. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-14-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 26 ------------------------ 1 file changed, 26 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 45701b498efc..5566c28e8e6a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -196,24 +196,14 @@ struct qmp_phy_cfg { /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; int serdes_tbl_num; - const struct qmp_phy_init_tbl *serdes_tbl_sec; - int serdes_tbl_num_sec; const struct qmp_phy_init_tbl *tx_tbl; int tx_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl_sec; - int tx_tbl_num_sec; const struct qmp_phy_init_tbl *rx_tbl; int rx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl_sec; - int rx_tbl_num_sec; const struct qmp_phy_init_tbl *pcs_tbl; int pcs_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl_sec; - int pcs_tbl_num_sec; const struct qmp_phy_init_tbl *pcs_misc_tbl; int pcs_misc_tbl_num; - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; - int pcs_misc_tbl_num_sec; /* clock ids to be requested */ const char * const *clk_list; @@ -409,10 +399,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) int ret; qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); - if (cfg->serdes_tbl_sec) - qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, - cfg->serdes_tbl_num_sec); - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], @@ -560,26 +546,14 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) /* Tx, Rx, and PCS configurations */ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 1); qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); - if (cfg->pcs_misc_tbl_sec) - qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, - cfg->pcs_misc_tbl_num_sec); /* * Pull out PHY from POWER DOWN state. -- cgit v1.2.3 From c577468c77f9f43a5e2f09de21573f97aaea6bd6 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:26 +0200 Subject: phy: qcom-qmp-pcie-msm8996: shorten function prefixes The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-15-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 93 ++++++++++++------------ 1 file changed, 46 insertions(+), 47 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 5566c28e8e6a..2a5eef6b12f5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -356,7 +356,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; -static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base, +static void qmp_pcie_msm8996_configure_lane(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num, @@ -379,15 +379,15 @@ static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base, } } -static void qcom_qmp_phy_pcie_msm8996_configure(void __iomem *base, +static void qmp_pcie_msm8996_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num) { - qcom_qmp_phy_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff); + qmp_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff); } -static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) +static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -398,7 +398,7 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) unsigned int mask, val; int ret; - qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + qmp_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], @@ -418,7 +418,7 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) +static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -471,7 +471,7 @@ err_unlock: return ret; } -static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) +static int qmp_pcie_msm8996_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -501,21 +501,21 @@ static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy) +static int qmp_pcie_msm8996_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; int ret; dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy); + ret = qmp_pcie_msm8996_com_init(qphy); if (ret) return ret; return 0; } -static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) +static int qmp_pcie_msm8996_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -528,7 +528,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) unsigned int mask, val, ready; int ret; - qcom_qmp_phy_pcie_msm8996_serdes_init(qphy); + qmp_pcie_msm8996_serdes_init(qphy); ret = reset_control_deassert(qphy->lane_rst); if (ret) { @@ -544,15 +544,15 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) } /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl, + cfg->tx_tbl_num, 1); - qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 1); + qmp_pcie_msm8996_configure_lane(rx, cfg->regs, cfg->rx_tbl, + cfg->rx_tbl_num, 1); - qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, + qmp_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); /* @@ -591,7 +591,7 @@ err_reset_lane: return ret; } -static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) +static int qmp_pcie_msm8996_power_off(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -616,43 +616,43 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) return 0; } -static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy) +static int qmp_pcie_msm8996_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); reset_control_assert(qphy->lane_rst); - qcom_qmp_phy_pcie_msm8996_com_exit(qphy); + qmp_pcie_msm8996_com_exit(qphy); return 0; } -static int qcom_qmp_phy_pcie_msm8996_enable(struct phy *phy) +static int qmp_pcie_msm8996_enable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_pcie_msm8996_init(phy); + ret = qmp_pcie_msm8996_init(phy); if (ret) return ret; - ret = qcom_qmp_phy_pcie_msm8996_power_on(phy); + ret = qmp_pcie_msm8996_power_on(phy); if (ret) - qcom_qmp_phy_pcie_msm8996_exit(phy); + qmp_pcie_msm8996_exit(phy); return ret; } -static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy) +static int qmp_pcie_msm8996_disable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_pcie_msm8996_power_off(phy); + ret = qmp_pcie_msm8996_power_off(phy); if (ret) return ret; - return qcom_qmp_phy_pcie_msm8996_exit(phy); + return qmp_pcie_msm8996_exit(phy); } -static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_vregs; @@ -668,7 +668,7 @@ static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; @@ -689,7 +689,7 @@ static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct return 0; } -static int qcom_qmp_phy_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_clks; @@ -765,9 +765,9 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = { - .power_on = qcom_qmp_phy_pcie_msm8996_enable, - .power_off = qcom_qmp_phy_pcie_msm8996_disable, +static const struct phy_ops qmp_pcie_msm8996_ops = { + .power_on = qmp_pcie_msm8996_enable, + .power_off = qmp_pcie_msm8996_disable, .owner = THIS_MODULE, }; @@ -776,8 +776,7 @@ static void qcom_qmp_reset_control_put(void *data) reset_control_put(data); } -static -int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, int id, +static int qmp_pcie_msm8996_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -830,7 +829,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, if (ret) return ret; - generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops); + generic_phy = devm_phy_create(dev, np, &qmp_pcie_msm8996_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); dev_err(dev, "failed to create qphy %d\n", ret); @@ -846,16 +845,16 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, return 0; } -static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = { +static const struct of_device_id qmp_pcie_msm8996_of_match_table[] = { { .compatible = "qcom,msm8996-qmp-pcie-phy", .data = &msm8996_pciephy_cfg, }, { }, }; -MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table); +MODULE_DEVICE_TABLE(of, qmp_pcie_msm8996_of_match_table); -static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) +static int qmp_pcie_msm8996_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; struct device *dev = &pdev->dev; @@ -887,15 +886,15 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) mutex_init(&qmp->phy_mutex); - ret = qcom_qmp_phy_pcie_msm8996_clk_init(dev, cfg); + ret = qmp_pcie_msm8996_clk_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_pcie_msm8996_reset_init(dev, cfg); + ret = qmp_pcie_msm8996_reset_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_pcie_msm8996_vreg_init(dev, cfg); + ret = qmp_pcie_msm8996_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to get regulator supplies: %d\n", @@ -915,7 +914,7 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) id = 0; for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ - ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg); + ret = qmp_pcie_msm8996_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -945,15 +944,15 @@ err_node_put: return ret; } -static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = { - .probe = qcom_qmp_phy_pcie_msm8996_probe, +static struct platform_driver qmp_pcie_msm8996_driver = { + .probe = qmp_pcie_msm8996_probe, .driver = { .name = "qcom-qmp-msm8996-pcie-phy", - .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table, + .of_match_table = qmp_pcie_msm8996_of_match_table, }, }; -module_platform_driver(qcom_qmp_phy_pcie_msm8996_driver); +module_platform_driver(qmp_pcie_msm8996_driver); MODULE_AUTHOR("Vivek Gautam "); MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver"); -- cgit v1.2.3 From 4412817b12da6bb99e0590ab1c9cd3e894fc93d5 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:27 +0200 Subject: phy: qcom-qmp-ufs: shorten function prefixes The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-16-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 88 ++++++++++++++++----------------- 1 file changed, 43 insertions(+), 45 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 28b75772cd0f..b020409b92e0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -821,7 +821,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .is_dual_lane_phy = true, }; -static void qcom_qmp_phy_ufs_configure_lane(void __iomem *base, +static void qmp_ufs_configure_lane(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num, @@ -844,27 +844,27 @@ static void qcom_qmp_phy_ufs_configure_lane(void __iomem *base, } } -static void qcom_qmp_phy_ufs_configure(void __iomem *base, +static void qmp_ufs_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num) { - qcom_qmp_phy_ufs_configure_lane(base, regs, tbl, num, 0xff); + qmp_ufs_configure_lane(base, regs, tbl, num, 0xff); } -static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy) +static int qmp_ufs_serdes_init(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + qmp_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); return 0; } -static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy) +static int qmp_ufs_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -898,7 +898,7 @@ err_disable_regulators: return ret; } -static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy) +static int qmp_ufs_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -912,7 +912,7 @@ static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_ufs_init(struct phy *phy) +static int qmp_ufs_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -947,14 +947,14 @@ static int qcom_qmp_phy_ufs_init(struct phy *phy) return ret; } - ret = qcom_qmp_phy_ufs_com_init(qphy); + ret = qmp_ufs_com_init(qphy); if (ret) return ret; return 0; } -static int qcom_qmp_phy_ufs_power_on(struct phy *phy) +static int qmp_ufs_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -966,26 +966,24 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy) unsigned int mask, val, ready; int ret; - qcom_qmp_phy_ufs_serdes_init(qphy); + qmp_ufs_serdes_init(qphy); /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); + qmp_ufs_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); } - qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 1); + qmp_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); + qmp_ufs_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); } - qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ret = reset_control_deassert(qmp->ufs_reset); if (ret) @@ -1011,7 +1009,7 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy) return 0; } -static int qcom_qmp_phy_ufs_power_off(struct phy *phy) +static int qmp_ufs_power_off(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -1035,41 +1033,41 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy) return 0; } -static int qcom_qmp_phy_ufs_exit(struct phy *phy) +static int qmp_ufs_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - qcom_qmp_phy_ufs_com_exit(qphy); + qmp_ufs_com_exit(qphy); return 0; } -static int qcom_qmp_phy_ufs_enable(struct phy *phy) +static int qmp_ufs_enable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_ufs_init(phy); + ret = qmp_ufs_init(phy); if (ret) return ret; - ret = qcom_qmp_phy_ufs_power_on(phy); + ret = qmp_ufs_power_on(phy); if (ret) - qcom_qmp_phy_ufs_exit(phy); + qmp_ufs_exit(phy); return ret; } -static int qcom_qmp_phy_ufs_disable(struct phy *phy) +static int qmp_ufs_disable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_ufs_power_off(phy); + ret = qmp_ufs_power_off(phy); if (ret) return ret; - return qcom_qmp_phy_ufs_exit(phy); + return qmp_ufs_exit(phy); } -static int qcom_qmp_phy_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_vregs; @@ -1085,7 +1083,7 @@ static int qcom_qmp_phy_ufs_vreg_init(struct device *dev, const struct qmp_phy_c return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_clks; @@ -1102,13 +1100,13 @@ static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cf } static const struct phy_ops qcom_qmp_ufs_ops = { - .power_on = qcom_qmp_phy_ufs_enable, - .power_off = qcom_qmp_phy_ufs_disable, + .power_on = qmp_ufs_enable, + .power_off = qmp_ufs_disable, .owner = THIS_MODULE, }; static -int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, +int qmp_ufs_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -1185,7 +1183,7 @@ int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, return 0; } -static const struct of_device_id qcom_qmp_phy_ufs_of_match_table[] = { +static const struct of_device_id qmp_ufs_of_match_table[] = { { .compatible = "qcom,msm8996-qmp-ufs-phy", .data = &msm8996_ufs_cfg, @@ -1222,9 +1220,9 @@ static const struct of_device_id qcom_qmp_phy_ufs_of_match_table[] = { }, { }, }; -MODULE_DEVICE_TABLE(of, qcom_qmp_phy_ufs_of_match_table); +MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table); -static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) +static int qmp_ufs_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; struct device *dev = &pdev->dev; @@ -1252,11 +1250,11 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - ret = qcom_qmp_phy_ufs_clk_init(dev, cfg); + ret = qmp_ufs_clk_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_ufs_vreg_init(dev, cfg); + ret = qmp_ufs_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to get regulator supplies: %d\n", @@ -1276,7 +1274,7 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) id = 0; for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ - ret = qcom_qmp_phy_ufs_create(dev, child, id, serdes, cfg); + ret = qmp_ufs_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -1295,15 +1293,15 @@ err_node_put: return ret; } -static struct platform_driver qcom_qmp_phy_ufs_driver = { - .probe = qcom_qmp_phy_ufs_probe, +static struct platform_driver qmp_ufs_driver = { + .probe = qmp_ufs_probe, .driver = { .name = "qcom-qmp-ufs-phy", - .of_match_table = qcom_qmp_phy_ufs_of_match_table, + .of_match_table = qmp_ufs_of_match_table, }, }; -module_platform_driver(qcom_qmp_phy_ufs_driver); +module_platform_driver(qmp_ufs_driver); MODULE_AUTHOR("Vivek Gautam "); MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver"); -- cgit v1.2.3 From b767dedc05ec92a11e99bd9e4ec18ce6abe02388 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Sep 2022 13:07:28 +0200 Subject: phy: qcom-qmp-usb: shorten function prefixes The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220907110728.19092-17-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 +- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 121 ++++++++++++++++---------------- 2 files changed, 60 insertions(+), 64 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index b020409b92e0..4d0eee620f37 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1105,8 +1105,7 @@ static const struct phy_ops qcom_qmp_ufs_ops = { .owner = THIS_MODULE, }; -static -int qmp_ufs_create(struct device *dev, struct device_node *np, int id, +static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 08e0799e8832..41635c21e3ca 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2103,7 +2103,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { .is_dual_lane_phy = true, }; -static void qcom_qmp_phy_usb_configure_lane(void __iomem *base, +static void qmp_usb_configure_lane(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num, @@ -2126,27 +2126,27 @@ static void qcom_qmp_phy_usb_configure_lane(void __iomem *base, } } -static void qcom_qmp_phy_usb_configure(void __iomem *base, +static void qmp_usb_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num) { - qcom_qmp_phy_usb_configure_lane(base, regs, tbl, num, 0xff); + qmp_usb_configure_lane(base, regs, tbl, num, 0xff); } -static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) +static int qmp_usb_serdes_init(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; - qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + qmp_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); return 0; } -static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) +static int qmp_usb_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -2218,7 +2218,7 @@ err_disable_regulators: return ret; } -static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy) +static int qmp_usb_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -2232,21 +2232,21 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_usb_init(struct phy *phy) +static int qmp_usb_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; int ret; dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - ret = qcom_qmp_phy_usb_com_init(qphy); + ret = qmp_usb_com_init(qphy); if (ret) return ret; return 0; } -static int qcom_qmp_phy_usb_power_on(struct phy *phy) +static int qmp_usb_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -2258,7 +2258,7 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy) unsigned int mask, val, ready; int ret; - qcom_qmp_phy_usb_serdes_init(qphy); + qmp_usb_serdes_init(qphy); ret = clk_prepare_enable(qphy->pipe_clk); if (ret) { @@ -2267,24 +2267,22 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy) } /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); + qmp_usb_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); } - qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 1); + qmp_usb_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); + qmp_usb_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); } /* Configure link rate, swing, etc. */ - qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); @@ -2314,7 +2312,7 @@ err_disable_pipe_clk: return ret; } -static int qcom_qmp_phy_usb_power_off(struct phy *phy) +static int qmp_usb_power_off(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -2339,42 +2337,41 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy) return 0; } -static int qcom_qmp_phy_usb_exit(struct phy *phy) +static int qmp_usb_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - qcom_qmp_phy_usb_com_exit(qphy); + qmp_usb_com_exit(qphy); return 0; } -static int qcom_qmp_phy_usb_enable(struct phy *phy) +static int qmp_usb_enable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_usb_init(phy); + ret = qmp_usb_init(phy); if (ret) return ret; - ret = qcom_qmp_phy_usb_power_on(phy); + ret = qmp_usb_power_on(phy); if (ret) - qcom_qmp_phy_usb_exit(phy); + qmp_usb_exit(phy); return ret; } -static int qcom_qmp_phy_usb_disable(struct phy *phy) +static int qmp_usb_disable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_usb_power_off(phy); + ret = qmp_usb_power_off(phy); if (ret) return ret; - return qcom_qmp_phy_usb_exit(phy); + return qmp_usb_exit(phy); } -static int qcom_qmp_phy_usb_set_mode(struct phy *phy, - enum phy_mode mode, int submode) +static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct qmp_phy *qphy = phy_get_drvdata(phy); @@ -2383,7 +2380,7 @@ static int qcom_qmp_phy_usb_set_mode(struct phy *phy, return 0; } -static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy) +static void qmp_usb_enable_autonomous_mode(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; @@ -2412,7 +2409,7 @@ static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy) qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); } -static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy) +static void qmp_usb_disable_autonomous_mode(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; @@ -2430,7 +2427,7 @@ static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy) qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); } -static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev) +static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; @@ -2447,7 +2444,7 @@ static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev) return 0; } - qcom_qmp_phy_usb_enable_autonomous_mode(qphy); + qmp_usb_enable_autonomous_mode(qphy); clk_disable_unprepare(qphy->pipe_clk); clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); @@ -2455,7 +2452,7 @@ static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev) return 0; } -static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev) +static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; @@ -2484,12 +2481,12 @@ static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev) return ret; } - qcom_qmp_phy_usb_disable_autonomous_mode(qphy); + qmp_usb_disable_autonomous_mode(qphy); return 0; } -static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_vregs; @@ -2505,7 +2502,7 @@ static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_c return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; @@ -2526,7 +2523,7 @@ static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_ return 0; } -static int qcom_qmp_phy_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_clks; @@ -2602,15 +2599,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -static const struct phy_ops qcom_qmp_phy_usb_ops = { - .init = qcom_qmp_phy_usb_enable, - .exit = qcom_qmp_phy_usb_disable, - .set_mode = qcom_qmp_phy_usb_set_mode, +static const struct phy_ops qmp_usb_ops = { + .init = qmp_usb_enable, + .exit = qmp_usb_disable, + .set_mode = qmp_usb_set_mode, .owner = THIS_MODULE, }; static -int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, +int qmp_usb_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -2680,7 +2677,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, "failed to get lane%d pipe clock\n", id); } - generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops); + generic_phy = devm_phy_create(dev, np, &qmp_usb_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); dev_err(dev, "failed to create qphy %d\n", ret); @@ -2696,7 +2693,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, return 0; } -static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = { +static const struct of_device_id qmp_usb_of_match_table[] = { { .compatible = "qcom,ipq8074-qmp-usb3-phy", .data = &ipq8074_usb3phy_cfg, @@ -2757,14 +2754,14 @@ static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = { }, { }, }; -MODULE_DEVICE_TABLE(of, qcom_qmp_phy_usb_of_match_table); +MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table); -static const struct dev_pm_ops qcom_qmp_phy_usb_pm_ops = { - SET_RUNTIME_PM_OPS(qcom_qmp_phy_usb_runtime_suspend, - qcom_qmp_phy_usb_runtime_resume, NULL) +static const struct dev_pm_ops qmp_usb_pm_ops = { + SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, + qmp_usb_runtime_resume, NULL) }; -static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) +static int qmp_usb_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; struct device *dev = &pdev->dev; @@ -2799,15 +2796,15 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) return PTR_ERR(qmp->dp_com); } - ret = qcom_qmp_phy_usb_clk_init(dev, cfg); + ret = qmp_usb_clk_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_usb_reset_init(dev, cfg); + ret = qmp_usb_reset_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_usb_vreg_init(dev, cfg); + ret = qmp_usb_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to get regulator supplies: %d\n", @@ -2837,7 +2834,7 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) id = 0; for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ - ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg); + ret = qmp_usb_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -2867,16 +2864,16 @@ err_node_put: return ret; } -static struct platform_driver qcom_qmp_phy_usb_driver = { - .probe = qcom_qmp_phy_usb_probe, +static struct platform_driver qmp_usb_driver = { + .probe = qmp_usb_probe, .driver = { .name = "qcom-qmp-usb-phy", - .pm = &qcom_qmp_phy_usb_pm_ops, - .of_match_table = qcom_qmp_phy_usb_of_match_table, + .pm = &qmp_usb_pm_ops, + .of_match_table = qmp_usb_of_match_table, }, }; -module_platform_driver(qcom_qmp_phy_usb_driver); +module_platform_driver(qmp_usb_driver); MODULE_AUTHOR("Vivek Gautam "); MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); -- cgit v1.2.3 From ecd5507e72ea03659dc2cc3e4393fbf8f4e2e02a Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:30 +0200 Subject: phy: qcom-qmp-pcie: add pcs_misc sanity check Make sure that the (otherwise) optional pcs_misc IO region has been provided in case the configuration specifies a corresponding initialisation table to avoid crashing with malformed device trees. Note that the related debug message is now superfluous as the region is only used when the configuration has a pcs_misc table. Fixes: 421c9a0e9731 ("phy: qcom: qmp: Add SDM845 PCIe QMP PHY support") Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index e6bffb0e2da3..05e73625a619 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2300,8 +2300,10 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) qphy->pcs_misc = qphy->pcs + 0x400; - if (!qphy->pcs_misc) - dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + if (!qphy->pcs_misc) { + if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec) + return -EINVAL; + } qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(qphy->pipe_clk)) { -- cgit v1.2.3 From 4be26f695ffa458b065b7942dbff9393bf0836ea Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:31 +0200 Subject: phy: qcom-qmp-pcie: fix memleak on probe deferral Switch to using the device-managed of_iomap helper to avoid leaking memory on probe deferral and driver unbind. Note that this helper checks for already reserved regions and may fail if there are multiple devices claiming the same memory. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 34 ++++++++++++++++---------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 05e73625a619..e6636700871c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2258,17 +2258,17 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 * For single lane PHYs: pcs_misc (optional) -> 3. */ - qphy->tx = of_iomap(np, 0); - if (!qphy->tx) - return -ENOMEM; + qphy->tx = devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qphy->tx)) + return PTR_ERR(qphy->tx); - qphy->rx = of_iomap(np, 1); - if (!qphy->rx) - return -ENOMEM; + qphy->rx = devm_of_iomap(dev, np, 1, NULL); + if (IS_ERR(qphy->rx)) + return PTR_ERR(qphy->rx); - qphy->pcs = of_iomap(np, 2); - if (!qphy->pcs) - return -ENOMEM; + qphy->pcs = devm_of_iomap(dev, np, 2, NULL); + if (IS_ERR(qphy->pcs)) + return PTR_ERR(qphy->pcs); /* * If this is a dual-lane PHY, then there should be registers for the @@ -2277,9 +2277,9 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, * offset from the first lane. */ if (cfg->is_dual_lane_phy) { - qphy->tx2 = of_iomap(np, 3); - qphy->rx2 = of_iomap(np, 4); - if (!qphy->tx2 || !qphy->rx2) { + qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { dev_warn(dev, "Underspecified device tree, falling back to legacy register regions\n"); @@ -2289,20 +2289,20 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; } else { - qphy->pcs_misc = of_iomap(np, 5); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } } else { - qphy->pcs_misc = of_iomap(np, 3); + qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } - if (!qphy->pcs_misc && + if (IS_ERR(qphy->pcs_misc) && of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) qphy->pcs_misc = qphy->pcs + 0x400; - if (!qphy->pcs_misc) { + if (IS_ERR(qphy->pcs_misc)) { if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec) - return -EINVAL; + return PTR_ERR(qphy->pcs_misc); } qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); -- cgit v1.2.3 From 1f69ededf8e80c42352e7f1c165a003614de9cc2 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:32 +0200 Subject: phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral Switch to using the device-managed of_iomap helper to avoid leaking memory on probe deferral and driver unbind. Note that this helper checks for already reserved regions and may fail if there are multiple devices claiming the same memory. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 2a5eef6b12f5..6664d84bb599 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -796,21 +796,20 @@ static int qmp_pcie_msm8996_create(struct device *dev, struct device_node *np, i * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 * For single lane PHYs: pcs_misc (optional) -> 3. */ - qphy->tx = of_iomap(np, 0); - if (!qphy->tx) - return -ENOMEM; - - qphy->rx = of_iomap(np, 1); - if (!qphy->rx) - return -ENOMEM; + qphy->tx = devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qphy->tx)) + return PTR_ERR(qphy->tx); - qphy->pcs = of_iomap(np, 2); - if (!qphy->pcs) - return -ENOMEM; + qphy->rx = devm_of_iomap(dev, np, 1, NULL); + if (IS_ERR(qphy->rx)) + return PTR_ERR(qphy->rx); - qphy->pcs_misc = of_iomap(np, 3); + qphy->pcs = devm_of_iomap(dev, np, 2, NULL); + if (IS_ERR(qphy->pcs)) + return PTR_ERR(qphy->pcs); - if (!qphy->pcs_misc) + qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); + if (IS_ERR(qphy->pcs_misc)) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); -- cgit v1.2.3 From 2de8a325b1084330ae500380cc27edc39f488c30 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:33 +0200 Subject: phy: qcom-qmp-combo: fix memleak on probe deferral Switch to using the device-managed of_iomap helper to avoid leaking memory on probe deferral and driver unbind. Note that this helper checks for already reserved regions and may fail if there are multiple devices claiming the same memory. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 32 ++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index f5d0d290d26e..1d55892c6575 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2714,17 +2714,17 @@ static int qmp_combo_create(struct device *dev, struct device_node *np, int id, * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 * For single lane PHYs: pcs_misc (optional) -> 3. */ - qphy->tx = of_iomap(np, 0); - if (!qphy->tx) - return -ENOMEM; + qphy->tx = devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qphy->tx)) + return PTR_ERR(qphy->tx); - qphy->rx = of_iomap(np, 1); - if (!qphy->rx) - return -ENOMEM; + qphy->rx = devm_of_iomap(dev, np, 1, NULL); + if (IS_ERR(qphy->rx)) + return PTR_ERR(qphy->rx); - qphy->pcs = of_iomap(np, 2); - if (!qphy->pcs) - return -ENOMEM; + qphy->pcs = devm_of_iomap(dev, np, 2, NULL); + if (IS_ERR(qphy->pcs)) + return PTR_ERR(qphy->pcs); if (cfg->pcs_usb_offset) qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; @@ -2736,9 +2736,9 @@ static int qmp_combo_create(struct device *dev, struct device_node *np, int id, * offset from the first lane. */ if (cfg->is_dual_lane_phy) { - qphy->tx2 = of_iomap(np, 3); - qphy->rx2 = of_iomap(np, 4); - if (!qphy->tx2 || !qphy->rx2) { + qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { dev_warn(dev, "Underspecified device tree, falling back to legacy register regions\n"); @@ -2748,15 +2748,17 @@ static int qmp_combo_create(struct device *dev, struct device_node *np, int id, qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; } else { - qphy->pcs_misc = of_iomap(np, 5); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } } else { - qphy->pcs_misc = of_iomap(np, 3); + qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } - if (!qphy->pcs_misc) + if (IS_ERR(qphy->pcs_misc)) { dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + qphy->pcs_misc = NULL; + } /* * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 -- cgit v1.2.3 From ef74a97f0df8758efe4476b4645961286aa86f0d Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:34 +0200 Subject: phy: qcom-qmp-ufs: fix memleak on probe deferral Switch to using the device-managed of_iomap helper to avoid leaking memory on probe deferral and driver unbind. Note that this helper checks for already reserved regions and may fail if there are multiple devices claiming the same memory. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-6-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 4d0eee620f37..1b1ac20cf290 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1125,17 +1125,17 @@ static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 * For single lane PHYs: pcs_misc (optional) -> 3. */ - qphy->tx = of_iomap(np, 0); - if (!qphy->tx) - return -ENOMEM; + qphy->tx = devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qphy->tx)) + return PTR_ERR(qphy->tx); - qphy->rx = of_iomap(np, 1); - if (!qphy->rx) - return -ENOMEM; + qphy->rx = devm_of_iomap(dev, np, 1, NULL); + if (IS_ERR(qphy->rx)) + return PTR_ERR(qphy->rx); - qphy->pcs = of_iomap(np, 2); - if (!qphy->pcs) - return -ENOMEM; + qphy->pcs = devm_of_iomap(dev, np, 2, NULL); + if (IS_ERR(qphy->pcs)) + return PTR_ERR(qphy->pcs); /* * If this is a dual-lane PHY, then there should be registers for the @@ -1144,9 +1144,9 @@ static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, * offset from the first lane. */ if (cfg->is_dual_lane_phy) { - qphy->tx2 = of_iomap(np, 3); - qphy->rx2 = of_iomap(np, 4); - if (!qphy->tx2 || !qphy->rx2) { + qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { dev_warn(dev, "Underspecified device tree, falling back to legacy register regions\n"); @@ -1156,14 +1156,14 @@ static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; } else { - qphy->pcs_misc = of_iomap(np, 5); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } } else { - qphy->pcs_misc = of_iomap(np, 3); + qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } - if (!qphy->pcs_misc) + if (IS_ERR(qphy->pcs_misc)) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); generic_phy = devm_phy_create(dev, np, &qcom_qmp_ufs_ops); -- cgit v1.2.3 From a5d6b1ac56cbd6b5850a3a54e35f1cb71e8e8cdd Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:35 +0200 Subject: phy: qcom-qmp-usb: fix memleak on probe deferral Switch to using the device-managed of_iomap helper to avoid leaking memory on probe deferral and driver unbind. Note that this helper checks for already reserved regions and may fail if there are multiple devices claiming the same memory. Two bindings currently rely on overlapping mappings for the PCS region so fallback to non-exclusive mappings for those for now. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-7-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 57 ++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 15 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 41635c21e3ca..41513cef3d99 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2606,6 +2606,21 @@ static const struct phy_ops qmp_usb_ops = { .owner = THIS_MODULE, }; +static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, + int index, bool exclusive) +{ + struct resource res; + + if (!exclusive) { + if (of_address_to_resource(np, index, &res)) + return IOMEM_ERR_PTR(-EINVAL); + + return devm_ioremap(dev, res.start, resource_size(&res)); + } + + return devm_of_iomap(dev, np, index, NULL); +} + static int qmp_usb_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) @@ -2613,8 +2628,18 @@ int qmp_usb_create(struct device *dev, struct device_node *np, int id, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; + bool exclusive = true; int ret; + /* + * FIXME: These bindings should be fixed to not rely on overlapping + * mappings for PCS. + */ + if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) + exclusive = false; + if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) + exclusive = false; + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); if (!qphy) return -ENOMEM; @@ -2627,17 +2652,17 @@ int qmp_usb_create(struct device *dev, struct device_node *np, int id, * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 * For single lane PHYs: pcs_misc (optional) -> 3. */ - qphy->tx = of_iomap(np, 0); - if (!qphy->tx) - return -ENOMEM; + qphy->tx = devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qphy->tx)) + return PTR_ERR(qphy->tx); - qphy->rx = of_iomap(np, 1); - if (!qphy->rx) - return -ENOMEM; + qphy->rx = devm_of_iomap(dev, np, 1, NULL); + if (IS_ERR(qphy->rx)) + return PTR_ERR(qphy->rx); - qphy->pcs = of_iomap(np, 2); - if (!qphy->pcs) - return -ENOMEM; + qphy->pcs = qmp_usb_iomap(dev, np, 2, exclusive); + if (IS_ERR(qphy->pcs)) + return PTR_ERR(qphy->pcs); if (cfg->pcs_usb_offset) qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; @@ -2649,9 +2674,9 @@ int qmp_usb_create(struct device *dev, struct device_node *np, int id, * offset from the first lane. */ if (cfg->is_dual_lane_phy) { - qphy->tx2 = of_iomap(np, 3); - qphy->rx2 = of_iomap(np, 4); - if (!qphy->tx2 || !qphy->rx2) { + qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { dev_warn(dev, "Underspecified device tree, falling back to legacy register regions\n"); @@ -2661,15 +2686,17 @@ int qmp_usb_create(struct device *dev, struct device_node *np, int id, qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; } else { - qphy->pcs_misc = of_iomap(np, 5); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } } else { - qphy->pcs_misc = of_iomap(np, 3); + qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } - if (!qphy->pcs_misc) + if (IS_ERR(qphy->pcs_misc)) { dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + qphy->pcs_misc = NULL; + } qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(qphy->pipe_clk)) { -- cgit v1.2.3 From 79a03925f79e4cfada997db7af1fcd3e958c1a2a Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:36 +0200 Subject: phy: qcom-qmp-pcie-msm8996: drop unused pcs_misc handling The MSM8996 QMP PHY driver does not use the PCS_MISC IO region (and neither do the DT binding specify it) so remove the corresponding code from the driver. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-8-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 6664d84bb599..245f6dc1710e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -202,8 +202,6 @@ struct qmp_phy_cfg { int rx_tbl_num; const struct qmp_phy_init_tbl *pcs_tbl; int pcs_tbl_num; - const struct qmp_phy_init_tbl *pcs_misc_tbl; - int pcs_misc_tbl_num; /* clock ids to be requested */ const char * const *clk_list; @@ -240,7 +238,6 @@ struct qmp_phy_cfg { * @tx: iomapped memory space for lane's tx * @rx: iomapped memory space for lane's rx * @pcs: iomapped memory space for lane's pcs - * @pcs_misc: iomapped memory space for lane's pcs_misc * @pipe_clk: pipe clock * @index: lane index * @qmp: QMP phy to which this lane belongs @@ -254,7 +251,6 @@ struct qmp_phy { void __iomem *tx; void __iomem *rx; void __iomem *pcs; - void __iomem *pcs_misc; struct clk *pipe_clk; unsigned int index; struct qcom_qmp *qmp; @@ -523,7 +519,6 @@ static int qmp_pcie_msm8996_power_on(struct phy *phy) void __iomem *tx = qphy->tx; void __iomem *rx = qphy->rx; void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; void __iomem *status; unsigned int mask, val, ready; int ret; @@ -552,9 +547,6 @@ static int qmp_pcie_msm8996_power_on(struct phy *phy) qmp_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - qmp_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, - cfg->pcs_misc_tbl_num); - /* * Pull out PHY from POWER DOWN state. * This is active low enable signal to power-down PHY. @@ -793,8 +785,6 @@ static int qmp_pcie_msm8996_create(struct device *dev, struct device_node *np, i /* * Get memory resources for each phy lane: * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. - * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 - * For single lane PHYs: pcs_misc (optional) -> 3. */ qphy->tx = devm_of_iomap(dev, np, 0, NULL); if (IS_ERR(qphy->tx)) @@ -808,10 +798,6 @@ static int qmp_pcie_msm8996_create(struct device *dev, struct device_node *np, i if (IS_ERR(qphy->pcs)) return PTR_ERR(qphy->pcs); - qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); - if (IS_ERR(qphy->pcs_misc)) - dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); - qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(qphy->pipe_clk)) { return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), -- cgit v1.2.3 From 69c90cb51661290e2f49e3d4c18cbbbe56749337 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:37 +0200 Subject: phy: qcom-qmp-pcie: drop unused legacy DT workaround Commit 5e17b95d9893 ("phy: qcom-qmp: Utilize fully-specified DT registers") added a workaround for legacy devicetrees which did not specify register regions for the second lane of some dual-lane PHYs. At the time, the only two dual-lane PHYs supported by mainline were "qcom,sdm845-qmp-usb3-phy" and "qcom,sdm845-qmp-ufs-phy", neither of which is a PCIe PHY. Drop the workaround for malformed devicetrees, which should no longer be needed since the QMP driver split. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-9-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index e6636700871c..4939edcd8cb1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -38,9 +38,6 @@ #define PHY_INIT_COMPLETE_TIMEOUT 10000 -/* Define the assumed distance between lanes for underspecified device trees. */ -#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 - struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -2270,28 +2267,16 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, if (IS_ERR(qphy->pcs)) return PTR_ERR(qphy->pcs); - /* - * If this is a dual-lane PHY, then there should be registers for the - * second lane. Some old device trees did not specify this, so fall - * back to old legacy behavior of assuming they can be reached at an - * offset from the first lane. - */ if (cfg->is_dual_lane_phy) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); - if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { - dev_warn(dev, - "Underspecified device tree, falling back to legacy register regions\n"); + if (IS_ERR(qphy->tx2)) + return PTR_ERR(qphy->tx2); - /* In the old version, pcs_misc is at index 3. */ - qphy->pcs_misc = qphy->tx2; - qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; - qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; - - } else { - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); - } + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->rx2)) + return PTR_ERR(qphy->rx2); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } else { qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } -- cgit v1.2.3 From 064bbdba4f8d30f9ecd0b96c3bcca5535d8811e7 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:38 +0200 Subject: phy: qcom-qmp-combo: drop unused legacy DT workaround Commit 5e17b95d9893 ("phy: qcom-qmp: Utilize fully-specified DT registers") added a workaround for legacy devicetrees which did not specify register regions for the second lane of some dual-lane PHYs. At the time, the only two dual-lane PHYs supported by mainline were "qcom,sdm845-qmp-usb3-phy" and "qcom,sdm845-qmp-ufs-phy", neither of which is a combo PHY. Drop the workaround for malformed devicetrees, which should no longer be needed since the QMP driver split. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-10-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 1d55892c6575..b5dde7f06ea9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -66,9 +66,6 @@ #define POWER_DOWN_DELAY_US_MIN 10 #define POWER_DOWN_DELAY_US_MAX 11 -/* Define the assumed distance between lanes for underspecified device trees. */ -#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 - struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -2729,28 +2726,16 @@ static int qmp_combo_create(struct device *dev, struct device_node *np, int id, if (cfg->pcs_usb_offset) qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; - /* - * If this is a dual-lane PHY, then there should be registers for the - * second lane. Some old device trees did not specify this, so fall - * back to old legacy behavior of assuming they can be reached at an - * offset from the first lane. - */ if (cfg->is_dual_lane_phy) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); - if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { - dev_warn(dev, - "Underspecified device tree, falling back to legacy register regions\n"); + if (IS_ERR(qphy->tx2)) + return PTR_ERR(qphy->tx2); - /* In the old version, pcs_misc is at index 3. */ - qphy->pcs_misc = qphy->tx2; - qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; - qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; - - } else { - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); - } + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->rx2)) + return PTR_ERR(qphy->rx2); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } else { qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } -- cgit v1.2.3 From 638255587418a31eadc5b24105c3cee288ae1d0f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:39 +0200 Subject: phy: qcom-qmp-ufs: drop legacy DT workaround Commit 5e17b95d9893 ("phy: qcom-qmp: Utilize fully-specified DT registers") added a workaround for legacy devicetrees which did not specify register regions for the second lane of some dual-lane PHYs. At the time, the only two dual-lane PHYs supported by mainline were "qcom,sdm845-qmp-usb3-phy" and "qcom,sdm845-qmp-ufs-phy" and they had been added to the binding less than six months before the binding was fixed. Presumably no one is using four-year old SDM845 dtbs with mainline anymore so drop the workaround for malformed devicetrees. In the unlikely event that anyone complains, we can consider reverting. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-11-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 1b1ac20cf290..7b335b50b4a1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -38,9 +38,6 @@ #define PHY_INIT_COMPLETE_TIMEOUT 10000 -/* Define the assumed distance between lanes for underspecified device trees. */ -#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 - struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -1137,28 +1134,16 @@ static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, if (IS_ERR(qphy->pcs)) return PTR_ERR(qphy->pcs); - /* - * If this is a dual-lane PHY, then there should be registers for the - * second lane. Some old device trees did not specify this, so fall - * back to old legacy behavior of assuming they can be reached at an - * offset from the first lane. - */ if (cfg->is_dual_lane_phy) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); - if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { - dev_warn(dev, - "Underspecified device tree, falling back to legacy register regions\n"); + if (IS_ERR(qphy->tx2)) + return PTR_ERR(qphy->tx2); - /* In the old version, pcs_misc is at index 3. */ - qphy->pcs_misc = qphy->tx2; - qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; - qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; - - } else { - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); - } + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->rx2)) + return PTR_ERR(qphy->rx2); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } else { qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } -- cgit v1.2.3 From 264dac74e7a31a726bd0bee3d1403faa1e2ae529 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 16 Sep 2022 12:23:40 +0200 Subject: phy: qcom-qmp-usb: drop legacy DT workaround Commit 5e17b95d9893 ("phy: qcom-qmp: Utilize fully-specified DT registers") added a workaround for legacy devicetrees which did not specify register regions for the second lane of some dual-lane PHYs. At the time, the only two dual-lane PHYs supported by mainline were "qcom,sdm845-qmp-usb3-phy" and "qcom,sdm845-qmp-ufs-phy" and they had been added to the binding less than six months before the binding was fixed. Presumably no one is using four-year old SDM845 dtbs with mainline anymore so drop the workaround for malformed devicetrees. In the unlikely event that anyone complains, we can consider reverting. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220916102340.11520-12-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 41513cef3d99..93994f1a46e2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -66,9 +66,6 @@ #define POWER_DOWN_DELAY_US_MIN 10 #define POWER_DOWN_DELAY_US_MAX 11 -/* Define the assumed distance between lanes for underspecified device trees. */ -#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 - struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -2667,28 +2664,16 @@ int qmp_usb_create(struct device *dev, struct device_node *np, int id, if (cfg->pcs_usb_offset) qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; - /* - * If this is a dual-lane PHY, then there should be registers for the - * second lane. Some old device trees did not specify this, so fall - * back to old legacy behavior of assuming they can be reached at an - * offset from the first lane. - */ if (cfg->is_dual_lane_phy) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); - if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { - dev_warn(dev, - "Underspecified device tree, falling back to legacy register regions\n"); + if (IS_ERR(qphy->tx2)) + return PTR_ERR(qphy->tx2); - /* In the old version, pcs_misc is at index 3. */ - qphy->pcs_misc = qphy->tx2; - qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; - qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; - - } else { - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); - } + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->rx2)) + return PTR_ERR(qphy->rx2); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } else { qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } -- cgit v1.2.3 From b8ecfbaf2e7268d4f934678d00a3849eda0cf7c9 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 19 Sep 2022 11:46:15 -0500 Subject: phy: rockchip: inno-dsidphy: Add support for rk3568 Add support for the Rockchip RK3568 DSI-DPHY. Registers were taken from the BSP kernel driver and wherever possible cross referenced with the TRM. Refactor the code to allow the different compatible strings to set either a max 1GHz timing table (all existing hardware) or a max 2.5GHz timing table (the new RK356x). This works (for me) on both an RK3326 (PX30) and a new RK3566 device. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20220919164616.12492-3-macroalpha82@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++++++++++++++++++----- 1 file changed, 158 insertions(+), 46 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 630e01b5c19b..2c5847faff63 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -84,9 +84,25 @@ #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0) #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0) /* Analog Register Part: reg08 */ +#define PLL_POST_DIV_ENABLE_MASK BIT(5) +#define PLL_POST_DIV_ENABLE BIT(5) #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4) #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4) #define SAMPLE_CLOCK_DIRECTION_FORWARD 0 +#define LOWFRE_EN_MASK BIT(5) +#define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0 +#define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1 +/* Analog Register Part: reg0b */ +#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0) +#define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0) +#define VOD_MIN_RANGE 0x1 +#define VOD_MID_RANGE 0x3 +#define VOD_BIG_RANGE 0x7 +#define VOD_MAX_RANGE 0xf +/* Analog Register Part: reg1E */ +#define PLL_MODE_SEL_MASK GENMASK(6, 5) +#define PLL_MODE_SEL_LVDS_MODE 0 +#define PLL_MODE_SEL_MIPI_MODE BIT(5) /* Digital Register Part: reg00 */ #define REG_DIG_RSTN_MASK BIT(0) #define REG_DIG_RSTN_NORMAL BIT(0) @@ -102,20 +118,22 @@ #define T_LPX_CNT_MASK GENMASK(5, 0) #define T_LPX_CNT(x) UPDATE(x, 5, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ +#define T_HS_ZERO_CNT_HI_MASK BIT(7) +#define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7) #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0) #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ -#define T_HS_ZERO_CNT_MASK GENMASK(5, 0) -#define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0) +#define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0) +#define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0) #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ -#define T_HS_EXIT_CNT_MASK GENMASK(4, 0) -#define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0) +#define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0) +#define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ -#define T_CLK_POST_CNT_MASK GENMASK(3, 0) -#define T_CLK_POST_CNT(x) UPDATE(x, 3, 0) +#define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0) +#define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ #define LPDT_TX_PPI_SYNC_MASK BIT(2) #define LPDT_TX_PPI_SYNC_ENABLE BIT(2) @@ -129,9 +147,13 @@ #define T_CLK_PRE_CNT_MASK GENMASK(3, 0) #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ +#define T_CLK_POST_CNT_HI_MASK GENMASK(7, 6) +#define T_CLK_POST_CNT_HI(x) UPDATE(x, 7, 6) #define T_TA_GO_CNT_MASK GENMASK(5, 0) #define T_TA_GO_CNT(x) UPDATE(x, 5, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ +#define T_HS_EXIT_CNT_HI_MASK BIT(6) +#define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6) #define T_TA_SURE_CNT_MASK GENMASK(5, 0) #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0) /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ @@ -169,11 +191,23 @@ #define DSI_PHY_STATUS 0xb0 #define PHY_LOCK BIT(0) +enum phy_max_rate { + MAX_1GHZ, + MAX_2_5GHZ, +}; + +struct inno_video_phy_plat_data { + const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; + const unsigned int num_timings; + enum phy_max_rate max_rate; +}; + struct inno_dsidphy { struct device *dev; struct clk *ref_clk; struct clk *pclk_phy; struct clk *pclk_host; + const struct inno_video_phy_plat_data *pdata; void __iomem *phy_base; void __iomem *host_base; struct reset_control *rst; @@ -200,6 +234,53 @@ enum { REGISTER_PART_LVDS, }; +struct inno_mipi_dphy_timing { + unsigned long rate; + u8 lpx; + u8 hs_prepare; + u8 clk_lane_hs_zero; + u8 data_lane_hs_zero; + u8 hs_trail; +}; + +static const +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { + { 110000000, 0x0, 0x20, 0x16, 0x02, 0x22}, + { 150000000, 0x0, 0x06, 0x16, 0x03, 0x45}, + { 200000000, 0x0, 0x18, 0x17, 0x04, 0x0b}, + { 250000000, 0x0, 0x05, 0x17, 0x05, 0x16}, + { 300000000, 0x0, 0x51, 0x18, 0x06, 0x2c}, + { 400000000, 0x0, 0x64, 0x19, 0x07, 0x33}, + { 500000000, 0x0, 0x20, 0x1b, 0x07, 0x4e}, + { 600000000, 0x0, 0x6a, 0x1d, 0x08, 0x3a}, + { 700000000, 0x0, 0x3e, 0x1e, 0x08, 0x6a}, + { 800000000, 0x0, 0x21, 0x1f, 0x09, 0x29}, + {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27}, +}; + +static const +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { + { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02}, + { 150000000, 0x02, 0x7f, 0x16, 0x03, 0x02}, + { 200000000, 0x02, 0x7f, 0x17, 0x04, 0x02}, + { 250000000, 0x02, 0x7f, 0x17, 0x05, 0x04}, + { 300000000, 0x02, 0x7f, 0x18, 0x06, 0x04}, + { 400000000, 0x03, 0x7e, 0x19, 0x07, 0x04}, + { 500000000, 0x03, 0x7c, 0x1b, 0x07, 0x08}, + { 600000000, 0x03, 0x70, 0x1d, 0x08, 0x10}, + { 700000000, 0x05, 0x40, 0x1e, 0x08, 0x30}, + { 800000000, 0x05, 0x02, 0x1f, 0x09, 0x30}, + {1000000000, 0x05, 0x08, 0x20, 0x09, 0x30}, + {1200000000, 0x06, 0x03, 0x32, 0x14, 0x0f}, + {1400000000, 0x09, 0x03, 0x32, 0x14, 0x0f}, + {1600000000, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, + {1800000000, 0x0e, 0x47, 0x7a, 0x0e, 0x0f}, + {2000000000, 0x11, 0x64, 0x7a, 0x0e, 0x0b}, + {2200000000, 0x13, 0x64, 0x7e, 0x15, 0x0b}, + {2400000000, 0x13, 0x33, 0x7f, 0x15, 0x6a}, + {2500000000, 0x15, 0x54, 0x7f, 0x15, 0x6a}, +}; + static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw) { return container_of(hw, struct inno_dsidphy, pll.hw); @@ -290,31 +371,15 @@ static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno, static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) { struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg; - const struct { - unsigned long rate; - u8 hs_prepare; - u8 clk_lane_hs_zero; - u8 data_lane_hs_zero; - u8 hs_trail; - } timings[] = { - { 110000000, 0x20, 0x16, 0x02, 0x22}, - { 150000000, 0x06, 0x16, 0x03, 0x45}, - { 200000000, 0x18, 0x17, 0x04, 0x0b}, - { 250000000, 0x05, 0x17, 0x05, 0x16}, - { 300000000, 0x51, 0x18, 0x06, 0x2c}, - { 400000000, 0x64, 0x19, 0x07, 0x33}, - { 500000000, 0x20, 0x1b, 0x07, 0x4e}, - { 600000000, 0x6a, 0x1d, 0x08, 0x3a}, - { 700000000, 0x3e, 0x1e, 0x08, 0x6a}, - { 800000000, 0x21, 0x1f, 0x09, 0x29}, - {1000000000, 0x09, 0x20, 0x09, 0x27}, - }; + const struct inno_mipi_dphy_timing *timings; u32 t_txbyteclkhs, t_txclkesc; u32 txbyteclkhs, txclkesc, esc_clk_div; u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; unsigned int i; + timings = inno->pdata->inno_mipi_dphy_timing_table; + inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate); /* Select MIPI mode */ @@ -327,6 +392,13 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); + if (inno->pdata->max_rate == MAX_2_5GHZ) { + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, + PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, + CLOCK_LANE_VOD_RANGE_SET_MASK, + CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); + } /* Enable PLL and LDO */ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, REG_LDOPD_MASK | REG_PLLPD_MASK, @@ -367,14 +439,6 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) */ clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE); - /* - * The value of counter for HS Tlpx Time - * Tlpx = Tpin_txbyteclkhs * (2 + value) - */ - lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs); - if (lpx >= 2) - lpx -= 2; - /* * The value of counter for HS Tta-go * Tta-go for turnaround @@ -394,13 +458,24 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) */ ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc); - for (i = 0; i < ARRAY_SIZE(timings); i++) + for (i = 0; i < inno->pdata->num_timings; i++) if (inno->pll.rate <= timings[i].rate) break; - if (i == ARRAY_SIZE(timings)) + if (i == inno->pdata->num_timings) --i; + /* + * The value of counter for HS Tlpx Time + * Tlpx = Tpin_txbyteclkhs * (2 + value) + */ + if (inno->pdata->max_rate == MAX_1GHZ) { + lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs); + if (lpx >= 2) + lpx -= 2; + } else + lpx = timings[i].lpx; + hs_prepare = timings[i].hs_prepare; hs_trail = timings[i].hs_trail; clk_lane_hs_zero = timings[i].clk_lane_hs_zero; @@ -417,14 +492,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) T_LPX_CNT(lpx)); phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, T_HS_PREPARE_CNT(hs_prepare)); - phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK, - T_HS_ZERO_CNT(hs_zero)); + if (inno->pdata->max_rate == MAX_2_5GHZ) + phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK, + T_HS_ZERO_CNT_HI(hs_zero >> 6)); + phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK, + T_HS_ZERO_CNT_LO(hs_zero)); phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, T_HS_TRAIL_CNT(hs_trail)); - phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK, - T_HS_EXIT_CNT(hs_exit)); - phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK, - T_CLK_POST_CNT(clk_post)); + if (inno->pdata->max_rate == MAX_2_5GHZ) + phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK, + T_HS_EXIT_CNT_HI(hs_exit >> 5)); + phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK, + T_HS_EXIT_CNT_LO(hs_exit)); + if (inno->pdata->max_rate == MAX_2_5GHZ) + phy_update_bits(inno, i, 0x10, T_CLK_POST_CNT_HI_MASK, + T_CLK_POST_CNT_HI(clk_post >> 4)); + phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK, + T_CLK_POST_CNT_LO(clk_post)); phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, T_CLK_PRE_CNT(clk_pre)); phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, @@ -452,8 +536,9 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) /* Sample clock reverse direction */ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, - SAMPLE_CLOCK_DIRECTION_MASK, - SAMPLE_CLOCK_DIRECTION_REVERSE); + SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK, + SAMPLE_CLOCK_DIRECTION_REVERSE | + PLL_OUTPUT_FREQUENCY_DIV_BY_1); /* Select LVDS mode */ phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, @@ -473,6 +558,10 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) msleep(20); + /* Select PLL mode */ + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e, + PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE); + /* Reset LVDS digital logic */ phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, LVDS_DIGITAL_INTERNAL_RESET_MASK, @@ -592,6 +681,18 @@ static const struct phy_ops inno_dsidphy_ops = { .owner = THIS_MODULE, }; +static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = { + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), + .max_rate = MAX_1GHZ, +}; + +static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = { + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), + .max_rate = MAX_2_5GHZ, +}; + static int inno_dsidphy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -605,6 +706,7 @@ static int inno_dsidphy_probe(struct platform_device *pdev) return -ENOMEM; inno->dev = dev; + inno->pdata = of_device_get_match_data(inno->dev); platform_set_drvdata(pdev, inno); inno->phy_base = devm_platform_ioremap_resource(pdev, 0); @@ -663,9 +765,19 @@ static int inno_dsidphy_remove(struct platform_device *pdev) } static const struct of_device_id inno_dsidphy_of_match[] = { - { .compatible = "rockchip,px30-dsi-dphy", }, - { .compatible = "rockchip,rk3128-dsi-dphy", }, - { .compatible = "rockchip,rk3368-dsi-dphy", }, + { + .compatible = "rockchip,px30-dsi-dphy", + .data = &max_1ghz_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3128-dsi-dphy", + .data = &max_1ghz_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3368-dsi-dphy", + .data = &max_1ghz_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3568-dsi-dphy", + .data = &max_2_5ghz_video_phy_plat_data, + }, {} }; MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match); -- cgit v1.2.3 From f5d6b5d613e9135e78cd91632a6ed4d04c4e5e49 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 19 Sep 2022 11:57:00 +0200 Subject: phy: qcom-qmp-combo: fix sc8280xp PCS_USB offset The PCS_USB register block lives at an offset of 0x300 from the PCS region on SC8280XP so add the missing offset to avoid corrupting unrelated registers on runtime suspend. Note that this region should probably be described separately in the binding. Fixes: a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20220919095700.2228-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index b5dde7f06ea9..41f938126ff1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1243,6 +1243,7 @@ static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = { .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v4_usb3phy_regs_layout, + .pcs_usb_offset = 0x300, .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, -- cgit v1.2.3 From c4c349be07aeec5f397a349046dc5fc0f2657691 Mon Sep 17 00:00:00 2001 From: Liang He Date: Thu, 15 Sep 2022 17:35:06 +0800 Subject: phy: amlogic: phy-meson-axg-mipi-pcie-analog: Hold reference returned by of_get_parent() As the of_get_parent() will increase the refcount of the node->parent and the reference will be discarded, so we should hold the reference with which we can decrease the refcount when done. Fixes: 8eff8b4e22d9 ("phy: amlogic: phy-meson-axg-mipi-pcie-analog: add support for MIPI DSI analog") Signed-off-by: Liang He Link: https://lore.kernel.org/r/20220915093506.4009456-1-windhl@126.com Signed-off-by: Vinod Koul --- drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c index 1027ece6ca12..a3e1108b736d 100644 --- a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c +++ b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c @@ -197,7 +197,7 @@ static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev) struct phy_provider *phy; struct device *dev = &pdev->dev; struct phy_axg_mipi_pcie_analog_priv *priv; - struct device_node *np = dev->of_node; + struct device_node *np = dev->of_node, *parent_np; struct regmap *map; int ret; @@ -206,7 +206,9 @@ static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev) return -ENOMEM; /* Get the hhi system controller node */ - map = syscon_node_to_regmap(of_get_parent(dev->of_node)); + parent_np = of_get_parent(dev->of_node); + map = syscon_node_to_regmap(parent_np); + of_node_put(parent_np); if (IS_ERR(map)) { dev_err(dev, "failed to get HHI regmap\n"); -- cgit v1.2.3 From 8b8934ac6de5da734ebe1b693cc475d11515888f Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Wed, 14 Sep 2022 21:37:28 +0800 Subject: phy: rockchip-snps-pcie3: Use devm_platform_get_and_ioremap_resource() Use devm_platform_get_and_ioremap_resource() to simplify code. Signed-off-by: Yang Yingliang Link: https://lore.kernel.org/r/20220914133728.3781160-1-yangyingliang@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index 1917edda6b47..a8d5914c5ac5 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -231,15 +231,13 @@ static int rockchip_p3phy_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct rockchip_p3phy_priv *priv; struct device_node *np = dev->of_node; - struct resource *res; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->mmio = devm_ioremap_resource(dev, res); + priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(priv->mmio)) { ret = PTR_ERR(priv->mmio); return ret; -- cgit v1.2.3 From 930981b425d94fc09e7597779cda870b1838bc99 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Wed, 14 Sep 2022 14:07:42 +0800 Subject: phy: phy-mtk-tphy: add property to set pre-emphasis Add a property to set usb2 phy's pre-emphasis, it's disabled by default on some SoCs. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220914060746.10004-3-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 8ee7682b8e93..986fde0f63a0 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -72,6 +72,8 @@ #define PA5_RG_U2_HS_100U_U3_EN BIT(11) #define U3P_USBPHYACR6 0x018 +#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) +#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) #define PA6_RG_U2_BC11_SW_EN BIT(23) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) #define PA6_RG_U2_DISCTH GENMASK(7, 4) @@ -370,6 +372,7 @@ struct mtk_phy_instance { int eye_term; int intr; int discth; + int pre_emphasis; bool bc12_en; }; @@ -841,10 +844,13 @@ static void phy_parse_property(struct mtk_tphy *tphy, &instance->intr); device_property_read_u32(dev, "mediatek,discth", &instance->discth); + device_property_read_u32(dev, "mediatek,pre-emphasis", + &instance->pre_emphasis); dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n", instance->bc12_en, instance->eye_src, instance->eye_vrt, instance->eye_term, instance->intr, instance->discth); + dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis); } static void u2_phy_props_set(struct mtk_tphy *tphy, @@ -875,6 +881,10 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, if (instance->discth) mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(instance->discth)); + + if (instance->pre_emphasis) + mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, + PA6_RG_U2_PRE_EMP_VAL(instance->pre_emphasis)); } /* type switch for usb3/pcie/sgmii/sata */ -- cgit v1.2.3 From 8da71ebad8455cde05bb6c148c84f3954b788497 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Wed, 14 Sep 2022 14:07:43 +0800 Subject: phy: phy-mtk-tphy: disable hardware efuse when set INTR INTR's value is able autoload from hardware efuse by default, when software tries to update its value, should disable hardware efuse firstly. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chunfeng Yun Link: https://lore.kernel.org/r/20220914060746.10004-4-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 986fde0f63a0..7f40b8b052bd 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -874,9 +874,14 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, PA1_RG_TERM_SEL_VAL(instance->eye_term)); - if (instance->intr) + if (instance->intr) { + if (u2_banks->misc) + mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, + MR1_EFUSE_AUTO_LOAD_DIS); + mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, PA1_RG_INTR_CAL_VAL(instance->intr)); + } if (instance->discth) mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, -- cgit v1.2.3 From 3fbbb75c40e6c51bff67dd17959d855fb497c901 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Wed, 14 Sep 2022 14:07:44 +0800 Subject: phy: phy-mtk-tphy: disable gpio mode for all usb2 phys Disable DP/DM's GPIO mode for all usb2 phy, not only for the first usb2 phy which usually supports dual-role mode. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220914060746.10004-5-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-tphy.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 7f40b8b052bd..79920c066e59 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -532,8 +532,7 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy, /* disable switch 100uA current to SSUSB */ mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); - if (!index) - mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); + mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); if (tphy->pdata->avoid_rx_sen_degradation) { if (!index) { -- cgit v1.2.3 From 1e77f026eb094cac123e701f97a8c042c82b32a3 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Wed, 14 Sep 2022 14:07:45 +0800 Subject: phy: phy-mtk-tphy: set utmi 0 register in init() ops No need repeat to clear utmi 0 register in ->power_on() and ->power_off(), just do it in ->init() Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220914060746.10004-6-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-tphy.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 79920c066e59..e0f227a0d3cc 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -522,8 +522,8 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy, /* switch to USB function, and enable usb pll */ mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); - mtk_phy_update_bits(com + U3P_U2PHYDTM0, P2C_RG_XCVRSEL | P2C_RG_DATAIN, - P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0)); + mtk_phy_clear_bits(com + U3P_U2PHYDTM0, + P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN); @@ -565,9 +565,6 @@ static void u2_phy_instance_power_on(struct mtk_tphy *tphy, void __iomem *com = u2_banks->com; u32 index = instance->index; - mtk_phy_clear_bits(com + U3P_U2PHYDTM0, - P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); - /* OTG Enable */ mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); @@ -590,8 +587,6 @@ static void u2_phy_instance_power_off(struct mtk_tphy *tphy, void __iomem *com = u2_banks->com; u32 index = instance->index; - mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_XCVRSEL | P2C_RG_DATAIN); - /* OTG Disable */ mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); -- cgit v1.2.3 From 931c05a8cb1be029ef2fbc1e4af313d4cb297c47 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Wed, 14 Sep 2022 14:07:46 +0800 Subject: phy: phy-mtk-tphy: fix the phy type setting issue The PHY type is not set if the index is non zero, prepare type value according to the index, like as mask value. Fixes: 39099a443358 ("phy: phy-mtk-tphy: support type switch by pericfg") Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220914060746.10004-7-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index e0f227a0d3cc..cc10298bc70d 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -915,7 +915,7 @@ static int phy_type_syscon_get(struct mtk_phy_instance *instance, static int phy_type_set(struct mtk_phy_instance *instance) { int type; - u32 mask; + u32 offset; if (!instance->type_sw) return 0; @@ -938,8 +938,9 @@ static int phy_type_set(struct mtk_phy_instance *instance) return 0; } - mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE); - regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type); + offset = instance->type_sw_index * BITS_PER_BYTE; + regmap_update_bits(instance->type_sw, instance->type_sw_reg, + RG_PHY_SW_TYPE << offset, type << offset); return 0; } -- cgit v1.2.3 From 1fbef61beaad9d54f977947cecc9e9d4b34b3dfd Mon Sep 17 00:00:00 2001 From: Matt Ranostay Date: Fri, 9 Sep 2022 13:00:26 -0700 Subject: phy: ti: phy-j721e-wiz: stop name conflict if multiple serdes are initialized When multiple serdes instances are initialized the first will succeed but additional will conflict over clocks names and probing fails. Signed-off-by: Matt Ranostay Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20220909200026.3422-1-mranostay@ti.com Signed-off-by: Vinod Koul --- drivers/phy/ti/phy-j721e-wiz.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 20af142580ad..1f4f585a84ad 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -717,6 +717,8 @@ static int wiz_phy_en_refclk_register(struct wiz *wiz) struct device *dev = wiz->dev; struct clk_init_data *init; struct clk *clk; + char *clk_name; + unsigned int sz; wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); if (!wiz_phy_en_refclk) @@ -726,12 +728,23 @@ static int wiz_phy_en_refclk_register(struct wiz *wiz) init->ops = &wiz_phy_en_refclk_ops; init->flags = 0; - init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK]; + + sz = strlen(dev_name(dev)) + strlen(output_clk_names[TI_WIZ_PHY_EN_REFCLK]) + 2; + + clk_name = kzalloc(sz, GFP_KERNEL); + if (!clk_name) + return -ENOMEM; + + snprintf(clk_name, sz, "%s_%s", dev_name(dev), output_clk_names[TI_WIZ_PHY_EN_REFCLK]); + init->name = clk_name; wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; wiz_phy_en_refclk->hw.init = init; clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); + + kfree(clk_name); + if (IS_ERR(clk)) return PTR_ERR(clk); -- cgit v1.2.3 From 61ab46fe2a5bf0e04fb61f337c873b47ab4c9a52 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:10 +0200 Subject: phy: qcom-qmp-pcie: drop unused type from config The configuration PHY type is no longer used since the QMP driver split so drop it from the configurations. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 4939edcd8cb1..d25f9215b86f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1304,8 +1304,6 @@ struct qmp_phy; /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - /* phy-type - PCIE/UFS/USB */ - unsigned int type; /* number of lanes provided by phy */ int nlanes; @@ -1470,7 +1468,6 @@ static const char * const sdm845_pciephy_reset_l[] = { }; static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = ipq8074_pcie_serdes_tbl, @@ -1499,7 +1496,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { }; static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, @@ -1529,7 +1525,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { }; static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = ipq6018_pcie_serdes_tbl, @@ -1559,7 +1554,6 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { }; static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, @@ -1590,7 +1584,6 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { }; static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, @@ -1619,7 +1612,6 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { }; static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, @@ -1658,7 +1650,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { }; static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 2, .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, @@ -1698,7 +1689,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { }; static const struct qmp_phy_cfg msm8998_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = msm8998_pcie_serdes_tbl, @@ -1723,7 +1713,6 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { }; static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, @@ -1753,7 +1742,6 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { }; static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 2, .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, @@ -1785,7 +1773,6 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { }; static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 1, .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, @@ -1816,7 +1803,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { }; static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 2, .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, -- cgit v1.2.3 From 7a114df1f2a305d0b0b6855a029384ea628319a5 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:11 +0200 Subject: phy: qcom-qmp-pcie-msm8996: drop unused type from config The configuration PHY type is no longer used since the QMP driver split so drop it from the configuration. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 245f6dc1710e..20a76b1b23a2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -188,8 +188,6 @@ struct qmp_phy; /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - /* phy-type - PCIE/UFS/USB */ - unsigned int type; /* number of lanes provided by phy */ int nlanes; @@ -323,7 +321,6 @@ static const char * const qmp_phy_vreg_l[] = { }; static const struct qmp_phy_cfg msm8996_pciephy_cfg = { - .type = PHY_TYPE_PCIE, .nlanes = 3, .serdes_tbl = msm8996_pcie_serdes_tbl, -- cgit v1.2.3 From 877f3debb33e16f120133c00e62b3525e324e611 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:12 +0200 Subject: phy: qcom-qmp-ufs: drop unused type from config The configuration PHY type is no longer used since the QMP driver split so drop it from the configuration. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 7b335b50b4a1..e5c8d3a4fdaa 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -535,8 +535,6 @@ struct qmp_phy; /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - /* phy-type - PCIE/UFS/USB */ - unsigned int type; /* number of lanes provided by phy */ int nlanes; @@ -668,7 +666,6 @@ static const char * const qmp_phy_vreg_l[] = { }; static const struct qmp_phy_cfg msm8996_ufs_cfg = { - .type = PHY_TYPE_UFS, .nlanes = 1, .serdes_tbl = msm8996_ufs_serdes_tbl, @@ -694,7 +691,6 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { }; static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { - .type = PHY_TYPE_UFS, .nlanes = 2, .serdes_tbl = sdm845_ufsphy_serdes_tbl, @@ -720,7 +716,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { }; static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { - .type = PHY_TYPE_UFS, .nlanes = 1, .serdes_tbl = sm6115_ufsphy_serdes_tbl, @@ -744,7 +739,6 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { }; static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { - .type = PHY_TYPE_UFS, .nlanes = 2, .serdes_tbl = sm8150_ufsphy_serdes_tbl, @@ -769,7 +763,6 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { }; static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { - .type = PHY_TYPE_UFS, .nlanes = 2, .serdes_tbl = sm8350_ufsphy_serdes_tbl, @@ -794,7 +787,6 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { }; static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { - .type = PHY_TYPE_UFS, .nlanes = 2, .serdes_tbl = sm8350_ufsphy_serdes_tbl, -- cgit v1.2.3 From 44d1b5ad174c56b9257b18ece93afdad78c35b05 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:13 +0200 Subject: phy: qcom-qmp-usb: drop unused type from config The configuration PHY type is no longer needed since the QMP driver split so drop it from the configuration and suspend callbacks. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 26 -------------------------- 1 file changed, 26 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 93994f1a46e2..03481b6f1c35 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1431,8 +1431,6 @@ struct qmp_phy; /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - /* phy-type - PCIE/UFS/USB */ - unsigned int type; /* number of lanes provided by phy */ int nlanes; @@ -1609,7 +1607,6 @@ static const char * const qmp_phy_vreg_l[] = { }; static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = ipq8074_usb3_serdes_tbl, @@ -1634,7 +1631,6 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { }; static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = msm8996_usb3_serdes_tbl, @@ -1659,7 +1655,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { }; static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = qmp_v3_usb3_serdes_tbl, @@ -1691,7 +1686,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { }; static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = qmp_v3_usb3_serdes_tbl, @@ -1723,7 +1717,6 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { }; static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, @@ -1752,7 +1745,6 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, @@ -1781,7 +1773,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = msm8998_usb3_serdes_tbl, @@ -1808,7 +1799,6 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { }; static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sm8150_usb3_serdes_tbl, @@ -1844,7 +1834,6 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { }; static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -1876,7 +1865,6 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sm8150_usb3_serdes_tbl, @@ -1911,7 +1899,6 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { }; static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -1943,7 +1930,6 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -1975,7 +1961,6 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -2007,7 +1992,6 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sm8150_usb3_serdes_tbl, @@ -2042,7 +2026,6 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { }; static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -2074,7 +2057,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { - .type = PHY_TYPE_USB3, .nlanes = 1, .serdes_tbl = qcm2290_usb3_serdes_tbl, @@ -2432,10 +2414,6 @@ static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - if (!qphy->phy->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; @@ -2458,10 +2436,6 @@ static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - if (!qphy->phy->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; -- cgit v1.2.3 From 91174e2c52ea9b5069ee04cffbdfa14837a5b761 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:14 +0200 Subject: phy: qcom-qmp-pcie: drop init and exit wrappers Drop the unnecessary PHY init and exit callback wrappers. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-6-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index d25f9215b86f..525097e3b041 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1877,8 +1877,9 @@ static int qmp_pcie_serdes_init(struct qmp_phy *qphy) return 0; } -static int qmp_pcie_com_init(struct qmp_phy *qphy) +static int qmp_pcie_init(struct phy *phy) { + struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; @@ -1925,8 +1926,9 @@ err_disable_regulators: return ret; } -static int qmp_pcie_com_exit(struct qmp_phy *qphy) +static int qmp_pcie_exit(struct phy *phy) { + struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -1939,20 +1941,6 @@ static int qmp_pcie_com_exit(struct qmp_phy *qphy) return 0; } -static int qmp_pcie_init(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - int ret; - dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - - ret = qmp_pcie_com_init(qphy); - if (ret) - return ret; - - return 0; -} - static int qmp_pcie_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); @@ -2060,15 +2048,6 @@ static int qmp_pcie_power_off(struct phy *phy) return 0; } -static int qmp_pcie_exit(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - - qmp_pcie_com_exit(qphy); - - return 0; -} - static int qmp_pcie_enable(struct phy *phy) { int ret; -- cgit v1.2.3 From fe2da191f125d299835e0bb299e7b35f68aa26e6 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:15 +0200 Subject: phy: qcom-qmp-usb: drop init and exit wrappers Drop the unnecessary PHY init and exit callback wrappers. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-7-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 03481b6f1c35..a42e13905c15 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2125,8 +2125,9 @@ static int qmp_usb_serdes_init(struct qmp_phy *qphy) return 0; } -static int qmp_usb_com_init(struct qmp_phy *qphy) +static int qmp_usb_init(struct phy *phy) { + struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; @@ -2197,8 +2198,9 @@ err_disable_regulators: return ret; } -static int qmp_usb_com_exit(struct qmp_phy *qphy) +static int qmp_usb_exit(struct phy *phy) { + struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -2211,20 +2213,6 @@ static int qmp_usb_com_exit(struct qmp_phy *qphy) return 0; } -static int qmp_usb_init(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - int ret; - dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - - ret = qmp_usb_com_init(qphy); - if (ret) - return ret; - - return 0; -} - static int qmp_usb_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); @@ -2316,15 +2304,6 @@ static int qmp_usb_power_off(struct phy *phy) return 0; } -static int qmp_usb_exit(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - - qmp_usb_com_exit(qphy); - - return 0; -} - static int qmp_usb_enable(struct phy *phy) { int ret; -- cgit v1.2.3 From ec1f303b3eeda24aa78f91a3fd2eb5b09b182783 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:16 +0200 Subject: phy: qcom-qmp: drop unused forward declarations Only the combo QMP driver needs a forward declaration of struct qmp_phy. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-8-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 2 -- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 -- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 2 -- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 2 -- 4 files changed, 8 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 20a76b1b23a2..7e755213e9c5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -184,8 +184,6 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), }; -struct qmp_phy; - /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { /* number of lanes provided by phy */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 525097e3b041..666109a11329 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1300,8 +1300,6 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), }; -struct qmp_phy; - /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { /* number of lanes provided by phy */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index e5c8d3a4fdaa..cc49dec46df4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -531,8 +531,6 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; -struct qmp_phy; - /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { /* number of lanes provided by phy */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index a42e13905c15..820062a95211 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1427,8 +1427,6 @@ static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), }; -struct qmp_phy; - /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { /* number of lanes provided by phy */ -- cgit v1.2.3 From 7dbea6093d540fa5c8320ae9d024f2eae7314d22 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:17 +0200 Subject: phy: qcom-qmp-pcie-msm8996: drop unused kernel doc Drop the removed mode field from the struct qmp_phy kernel doc. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-9-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 7e755213e9c5..e261837aee32 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -238,7 +238,6 @@ struct qmp_phy_cfg { * @index: lane index * @qmp: QMP phy to which this lane belongs * @lane_rst: lane's reset controller - * @mode: current PHY mode */ struct qmp_phy { struct phy *phy; -- cgit v1.2.3 From 96da759b5306f8600b44fab81f1816daaab07651 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:18 +0200 Subject: phy: qcom-qmp-pcie: drop unused mode field Drop the unused mode field from struct qmp_phy. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-10-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 666109a11329..65825ca41e96 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1374,7 +1374,6 @@ struct qmp_phy_cfg { * @pipe_clk: pipe clock * @index: lane index * @qmp: QMP phy to which this lane belongs - * @mode: current PHY mode */ struct qmp_phy { struct phy *phy; @@ -1389,7 +1388,6 @@ struct qmp_phy { struct clk *pipe_clk; unsigned int index; struct qcom_qmp *qmp; - enum phy_mode mode; }; /** -- cgit v1.2.3 From a4683acfa4fb964cab6ac4f486a18095a7bb3131 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:19 +0200 Subject: phy: qcom-qmp-pcie: drop unused config field Drop the unused mask_com_pcs_ready field from struct qmp_phy_cfg. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-11-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 65825ca41e96..d22d2cf2fc18 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1342,7 +1342,6 @@ struct qmp_phy_cfg { unsigned int start_ctrl; unsigned int pwrdn_ctrl; - unsigned int mask_com_pcs_ready; /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ unsigned int phy_status; -- cgit v1.2.3 From b4e9da4d961faeae3c76ecbc26057f7d00965498 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:20 +0200 Subject: phy: qcom-qmp: drop unused index field Only the MSM8996 PCIe QMP driver uses the index field so drop it from the other drivers. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-12-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 3 --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 3 --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 --- 4 files changed, 12 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 41f938126ff1..08e96e383a29 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -906,7 +906,6 @@ struct qmp_phy_combo_cfg { * @pcs_misc: iomapped memory space for lane's pcs_misc * @pcs_usb: iomapped memory space for lane's pcs_usb * @pipe_clk: pipe clock - * @index: lane index * @qmp: QMP phy to which this lane belongs * @mode: current PHY mode * @dp_aux_cfg: Display port aux config @@ -925,7 +924,6 @@ struct qmp_phy { void __iomem *pcs_misc; void __iomem *pcs_usb; struct clk *pipe_clk; - unsigned int index; struct qcom_qmp *qmp; enum phy_mode mode; unsigned int dp_aux_cfg; @@ -2779,7 +2777,6 @@ static int qmp_combo_create(struct device *dev, struct device_node *np, int id, } qphy->phy = generic_phy; - qphy->index = id; qphy->qmp = qmp; qmp->phys[id] = qphy; phy_set_drvdata(generic_phy, qphy); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index d22d2cf2fc18..387abed33727 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1371,7 +1371,6 @@ struct qmp_phy_cfg { * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc * @pipe_clk: pipe clock - * @index: lane index * @qmp: QMP phy to which this lane belongs */ struct qmp_phy { @@ -1385,7 +1384,6 @@ struct qmp_phy { void __iomem *rx2; void __iomem *pcs_misc; struct clk *pipe_clk; - unsigned int index; struct qcom_qmp *qmp; }; @@ -2264,7 +2262,6 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, } qphy->phy = generic_phy; - qphy->index = id; qphy->qmp = qmp; qmp->phys[id] = qphy; phy_set_drvdata(generic_phy, qphy); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index cc49dec46df4..ca9a42250556 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -580,7 +580,6 @@ struct qmp_phy_cfg { * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc - * @index: lane index * @qmp: QMP phy to which this lane belongs */ struct qmp_phy { @@ -593,7 +592,6 @@ struct qmp_phy { void __iomem *tx2; void __iomem *rx2; void __iomem *pcs_misc; - unsigned int index; struct qcom_qmp *qmp; }; @@ -1149,7 +1147,6 @@ static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, } qphy->phy = generic_phy; - qphy->index = id; qphy->qmp = qmp; qmp->phys[id] = qphy; phy_set_drvdata(generic_phy, qphy); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 820062a95211..a34320738f60 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1491,7 +1491,6 @@ struct qmp_phy_cfg { * @pcs_misc: iomapped memory space for lane's pcs_misc * @pcs_usb: iomapped memory space for lane's pcs_usb * @pipe_clk: pipe clock - * @index: lane index * @qmp: QMP phy to which this lane belongs * @mode: current PHY mode */ @@ -1507,7 +1506,6 @@ struct qmp_phy { void __iomem *pcs_misc; void __iomem *pcs_usb; struct clk *pipe_clk; - unsigned int index; struct qcom_qmp *qmp; enum phy_mode mode; }; @@ -2648,7 +2646,6 @@ int qmp_usb_create(struct device *dev, struct device_node *np, int id, } qphy->phy = generic_phy; - qphy->index = id; qphy->qmp = qmp; qmp->phys[id] = qphy; phy_set_drvdata(generic_phy, qphy); -- cgit v1.2.3 From f02543fa5b2c96cc7196e40992e5b715aa4e6cfc Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:21 +0200 Subject: phy: qcom-qmp-pcie: consolidate lane config For legacy reasons, there are two configuration parameters that describe the number of lanes a PHY has. Replace them both with a new field simply named "lanes". Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-13-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 39 +++++++++++++------------------- 1 file changed, 16 insertions(+), 23 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 387abed33727..dde398105f03 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1302,8 +1302,7 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - /* number of lanes provided by phy */ - int nlanes; + int lanes; /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; @@ -1351,9 +1350,6 @@ struct qmp_phy_cfg { int pwrdn_delay_min; int pwrdn_delay_max; - /* true, if PHY has secondary tx/rx lanes to be configured */ - bool is_dual_lane_phy; - /* QMP PHY pipe clock interface rate */ unsigned long pipe_clock_rate; }; @@ -1461,7 +1457,7 @@ static const char * const sdm845_pciephy_reset_l[] = { }; static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = ipq8074_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), @@ -1489,7 +1485,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { }; static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), @@ -1518,7 +1514,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { }; static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = ipq6018_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), @@ -1547,7 +1543,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { }; static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), @@ -1577,7 +1573,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { }; static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), @@ -1605,7 +1601,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { }; static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), @@ -1643,7 +1639,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { }; static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { - .nlanes = 2, + .lanes = 2, .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), @@ -1675,14 +1671,13 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, - .is_dual_lane_phy = true, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ .pwrdn_delay_max = 1005, /* us */ }; static const struct qmp_phy_cfg msm8998_pciephy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = msm8998_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), @@ -1706,7 +1701,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { }; static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), @@ -1735,7 +1730,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { }; static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { - .nlanes = 2, + .lanes = 2, .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), @@ -1759,14 +1754,13 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS_4_20, - .is_dual_lane_phy = true, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ .pwrdn_delay_max = 1005, /* us */ }; static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), @@ -1796,7 +1790,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { }; static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { - .nlanes = 2, + .lanes = 2, .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), @@ -1820,7 +1814,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, - .is_dual_lane_phy = true, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ .pwrdn_delay_max = 1005, /* us */ @@ -1959,7 +1952,7 @@ static int qmp_pcie_power_on(struct phy *phy) qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl_sec, @@ -1969,7 +1962,7 @@ static int qmp_pcie_power_on(struct phy *phy) qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl_sec, @@ -2225,7 +2218,7 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, if (IS_ERR(qphy->pcs)) return PTR_ERR(qphy->pcs); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); if (IS_ERR(qphy->tx2)) return PTR_ERR(qphy->tx2); -- cgit v1.2.3 From 0d316ce5c0491410db8031a36d561f966995eea9 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:22 +0200 Subject: phy: qcom-qmp-pcie-msm8996: rename nlanes config The nlanes configuration parameter is really the number of PHYs provided by this QMP block on MSM8996. Rename it accordingly. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-14-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index e261837aee32..0f8e739936ab 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -186,8 +186,8 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - /* number of lanes provided by phy */ - int nlanes; + /* number of PHYs provided by this block */ + int num_phys; /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; @@ -318,7 +318,7 @@ static const char * const qmp_phy_vreg_l[] = { }; static const struct qmp_phy_cfg msm8996_pciephy_cfg = { - .nlanes = 3, + .num_phys = 3, .serdes_tbl = msm8996_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), @@ -861,7 +861,7 @@ static int qmp_pcie_msm8996_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - expected_phys = cfg->nlanes; + expected_phys = cfg->num_phys; mutex_init(&qmp->phy_mutex); -- cgit v1.2.3 From 099155615ac2ddb457bd8462038901c162e2cb96 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:23 +0200 Subject: phy: qcom-qmp-combo: consolidate lane config For legacy reasons, there are two configuration parameters that appear to describe the number of lanes a PHY has, even if "nlanes" was actually used for a different purpose. Replace them both with a new field simply named "lanes". Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-15-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 38 +++++++++++-------------------- 1 file changed, 13 insertions(+), 25 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 08e96e383a29..417e0fcf1a9f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -816,8 +816,7 @@ struct qmp_phy; struct qmp_phy_cfg { /* phy-type - PCIE/UFS/USB */ unsigned int type; - /* number of lanes provided by phy */ - int nlanes; + int lanes; /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; @@ -879,8 +878,6 @@ struct qmp_phy_cfg { /* true, if PHY has a separate DP_COM control block */ bool has_phy_dp_com_ctrl; - /* true, if PHY has secondary tx/rx lanes to be configured */ - bool is_dual_lane_phy; /* Offset from PCS to PCS_USB region */ unsigned int pcs_usb_offset; @@ -1029,7 +1026,7 @@ static const char * const sc7180_usb3phy_reset_l[] = { static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .type = PHY_TYPE_USB3, - .nlanes = 1, + .lanes = 2, .serdes_tbl = qmp_v3_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), @@ -1056,12 +1053,11 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sc7180_dpphy_cfg = { .type = PHY_TYPE_DP, - .nlanes = 1, + .lanes = 2, .serdes_tbl = qmp_v3_dp_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), @@ -1091,7 +1087,6 @@ static const struct qmp_phy_cfg sc7180_dpphy_cfg = { .regs = qmp_v3_usb3phy_regs_layout, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, @@ -1106,7 +1101,7 @@ static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { static const struct qmp_phy_cfg sdm845_usb3phy_cfg = { .type = PHY_TYPE_USB3, - .nlanes = 1, + .lanes = 2, .serdes_tbl = qmp_v3_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), @@ -1133,7 +1128,6 @@ static const struct qmp_phy_cfg sdm845_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = { @@ -1143,7 +1137,7 @@ static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = { static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { .type = PHY_TYPE_USB3, - .nlanes = 1, + .lanes = 2, .serdes_tbl = sm8150_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), @@ -1174,12 +1168,11 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { .type = PHY_TYPE_DP, - .nlanes = 1, + .lanes = 2, .serdes_tbl = qmp_v4_dp_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), @@ -1209,7 +1202,6 @@ static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { .regs = qmp_v3_usb3phy_regs_layout, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, @@ -1224,7 +1216,7 @@ static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = { .type = PHY_TYPE_USB3, - .nlanes = 1, + .lanes = 2, .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), @@ -1252,12 +1244,11 @@ static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = { .type = PHY_TYPE_DP, - .nlanes = 1, + .lanes = 2, .serdes_tbl = qmp_v5_dp_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), @@ -1287,7 +1278,6 @@ static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = { .regs = qmp_v4_usb3phy_regs_layout, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, @@ -1302,7 +1292,7 @@ static const struct qmp_phy_combo_cfg sc8280xp_usb43dpphy_combo_cfg = { static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { .type = PHY_TYPE_USB3, - .nlanes = 1, + .lanes = 2, .serdes_tbl = sm8150_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), @@ -1332,12 +1322,11 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sm8250_dpphy_cfg = { .type = PHY_TYPE_DP, - .nlanes = 1, + .lanes = 2, .serdes_tbl = qmp_v4_dp_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), @@ -1367,7 +1356,6 @@ static const struct qmp_phy_cfg sm8250_dpphy_cfg = { .regs = qmp_v4_usb3phy_regs_layout, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, @@ -2117,7 +2105,7 @@ static int qmp_combo_power_on(struct phy *phy) /* Tx, Rx, and PCS configurations */ qmp_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qmp_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); } @@ -2128,7 +2116,7 @@ static int qmp_combo_power_on(struct phy *phy) qmp_combo_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qmp_combo_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); } @@ -2725,7 +2713,7 @@ static int qmp_combo_create(struct device *dev, struct device_node *np, int id, if (cfg->pcs_usb_offset) qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); if (IS_ERR(qphy->tx2)) return PTR_ERR(qphy->tx2); -- cgit v1.2.3 From 07d386bf6d50a8a0e8e430a97c5efad616385fb0 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:24 +0200 Subject: phy: qcom-qmp-ufs: consolidate lane config For legacy reasons, there are two configuration parameters that describe the number of lanes a PHY has. Replace them both with a new field simply named "lanes". Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-16-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 31 ++++++++++--------------------- 1 file changed, 10 insertions(+), 21 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index ca9a42250556..d21b977850b3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -533,8 +533,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - /* number of lanes provided by phy */ - int nlanes; + int lanes; /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; @@ -561,9 +560,6 @@ struct qmp_phy_cfg { /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ unsigned int phy_status; - /* true, if PHY has secondary tx/rx lanes to be configured */ - bool is_dual_lane_phy; - /* true, if PCS block has no separate SW_RESET register */ bool no_pcs_sw_reset; }; @@ -662,7 +658,7 @@ static const char * const qmp_phy_vreg_l[] = { }; static const struct qmp_phy_cfg msm8996_ufs_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = msm8996_ufs_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), @@ -687,7 +683,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { }; static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { - .nlanes = 2, + .lanes = 2, .serdes_tbl = sdm845_ufsphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), @@ -707,12 +703,11 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS, - .is_dual_lane_phy = true, .no_pcs_sw_reset = true, }; static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sm6115_ufsphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), @@ -735,7 +730,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { }; static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { - .nlanes = 2, + .lanes = 2, .serdes_tbl = sm8150_ufsphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), @@ -754,12 +749,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { - .nlanes = 2, + .lanes = 2, .serdes_tbl = sm8350_ufsphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), @@ -778,12 +771,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { - .nlanes = 2, + .lanes = 2, .serdes_tbl = sm8350_ufsphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), @@ -802,8 +793,6 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, }; static void qmp_ufs_configure_lane(void __iomem *base, @@ -956,14 +945,14 @@ static int qmp_ufs_power_on(struct phy *phy) /* Tx, Rx, and PCS configurations */ qmp_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qmp_ufs_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); } qmp_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qmp_ufs_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); } @@ -1122,7 +1111,7 @@ static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, if (IS_ERR(qphy->pcs)) return PTR_ERR(qphy->pcs); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); if (IS_ERR(qphy->tx2)) return PTR_ERR(qphy->tx2); -- cgit v1.2.3 From a73a19ea382830cf27c49b9dda5aefe84c442a08 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:25 +0200 Subject: phy: qcom-qmp-usb: consolidate lane config For legacy reasons, there are two configuration parameters that appear to describe the number of lanes a PHY has, even if "nlanes" was actually used for a different purpose. Replace them both with a new field simply named "lanes". Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-17-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 52 +++++++++++++-------------------- 1 file changed, 20 insertions(+), 32 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index a34320738f60..f01b3022a10d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1429,8 +1429,7 @@ static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - /* number of lanes provided by phy */ - int nlanes; + int lanes; /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; @@ -1470,8 +1469,6 @@ struct qmp_phy_cfg { /* true, if PHY has a separate DP_COM control block */ bool has_phy_dp_com_ctrl; - /* true, if PHY has secondary tx/rx lanes to be configured */ - bool is_dual_lane_phy; /* Offset from PCS to PCS_USB region */ unsigned int pcs_usb_offset; @@ -1603,7 +1600,7 @@ static const char * const qmp_phy_vreg_l[] = { }; static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = ipq8074_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), @@ -1627,7 +1624,7 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { }; static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = msm8996_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), @@ -1651,7 +1648,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { }; static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { - .nlanes = 1, + .lanes = 2, .serdes_tbl = qmp_v3_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), @@ -1678,11 +1675,10 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { - .nlanes = 1, + .lanes = 2, .serdes_tbl = qmp_v3_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), @@ -1709,11 +1705,10 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), @@ -1741,7 +1736,7 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), @@ -1769,7 +1764,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { - .nlanes = 1, + .lanes = 2, .serdes_tbl = msm8998_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), @@ -1790,12 +1785,10 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { - .nlanes = 1, + .lanes = 2, .serdes_tbl = sm8150_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), @@ -1826,11 +1819,10 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), @@ -1861,7 +1853,7 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { - .nlanes = 1, + .lanes = 2, .serdes_tbl = sm8150_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), @@ -1891,11 +1883,10 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), @@ -1926,7 +1917,7 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), @@ -1957,7 +1948,7 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), @@ -1988,7 +1979,7 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { - .nlanes = 1, + .lanes = 2, .serdes_tbl = sm8150_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), @@ -2018,11 +2009,10 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, .has_phy_dp_com_ctrl = true, - .is_dual_lane_phy = true, }; static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { - .nlanes = 1, + .lanes = 1, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), @@ -2053,7 +2043,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { - .nlanes = 1, + .lanes = 2, .serdes_tbl = qcm2290_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), @@ -2074,8 +2064,6 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS, - - .is_dual_lane_phy = true, }; static void qmp_usb_configure_lane(void __iomem *base, @@ -2232,14 +2220,14 @@ static int qmp_usb_power_on(struct phy *phy) /* Tx, Rx, and PCS configurations */ qmp_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qmp_usb_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); } qmp_usb_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qmp_usb_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); } @@ -2613,7 +2601,7 @@ int qmp_usb_create(struct device *dev, struct device_node *np, int id, if (cfg->pcs_usb_offset) qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; - if (cfg->is_dual_lane_phy) { + if (cfg->lanes >= 2) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); if (IS_ERR(qphy->tx2)) return PTR_ERR(qphy->tx2); -- cgit v1.2.3 From 9d943961912cdbbe33d04ca0144b27997f890d10 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 20 Sep 2022 09:38:26 +0200 Subject: phy: qcom-qmp-combo: drop redundant DP config flag Drop the DP_COM control block flag from the configuration data, which is set for all combo PHYs and hence no longer needed since the QMP driver split. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220920073826.20811-18-johan+linaro@kernel.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 63 +++++++++---------------------- 1 file changed, 18 insertions(+), 45 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 417e0fcf1a9f..ad3b0aa22048 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -876,9 +876,6 @@ struct qmp_phy_cfg { int pwrdn_delay_min; int pwrdn_delay_max; - /* true, if PHY has a separate DP_COM control block */ - bool has_phy_dp_com_ctrl; - /* Offset from PCS to PCS_USB region */ unsigned int pcs_usb_offset; @@ -1051,8 +1048,6 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, }; static const struct qmp_phy_cfg sc7180_dpphy_cfg = { @@ -1086,8 +1081,6 @@ static const struct qmp_phy_cfg sc7180_dpphy_cfg = { .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v3_usb3phy_regs_layout, - .has_phy_dp_com_ctrl = true, - .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, @@ -1126,8 +1119,6 @@ static const struct qmp_phy_cfg sdm845_usb3phy_cfg = { .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, }; static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = { @@ -1166,8 +1157,6 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, }; static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { @@ -1201,8 +1190,6 @@ static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v3_usb3phy_regs_layout, - .has_phy_dp_com_ctrl = true, - .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, @@ -1242,8 +1229,6 @@ static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = { .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, }; static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = { @@ -1277,8 +1262,6 @@ static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = { .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v4_usb3phy_regs_layout, - .has_phy_dp_com_ctrl = true, - .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, .configure_dp_phy = qcom_qmp_v5_phy_configure_dp_phy, @@ -1320,8 +1303,6 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, - - .has_phy_dp_com_ctrl = true, }; static const struct qmp_phy_cfg sm8250_dpphy_cfg = { @@ -1355,8 +1336,6 @@ static const struct qmp_phy_cfg sm8250_dpphy_cfg = { .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v4_usb3phy_regs_layout, - .has_phy_dp_com_ctrl = true, - .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, @@ -1995,28 +1974,25 @@ static int qmp_combo_com_init(struct qmp_phy *qphy) if (ret) goto err_assert_reset; - if (cfg->has_phy_dp_com_ctrl) { - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, - SW_PWRDN); - /* override hardware control for reset of qmp phy */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); - /* Default type-c orientation, i.e CC1 */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); + /* override hardware control for reset of qmp phy */ + qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, - USB3_MODE | DP_MODE); + /* Default type-c orientation, i.e CC1 */ + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); - } + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ + qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) qphy_setbits(pcs, @@ -2838,12 +2814,9 @@ static int qmp_combo_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - /* per PHY dp_com; if PHY has dp_com control block */ - if (cfg->has_phy_dp_com_ctrl) { - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(qmp->dp_com)) - return PTR_ERR(qmp->dp_com); - } + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->dp_com)) + return PTR_ERR(qmp->dp_com); /* Only two serdes for combo PHY */ dp_serdes = devm_platform_ioremap_resource(pdev, 2); -- cgit v1.2.3 From 29c07477556eb68a64f0ff53235feb0bd1cf1f63 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:21 +0800 Subject: phy: mediatek: add a new helper to update bitfield Due to FIELD_PREP() macro can be used to prepare a bitfield value, local ones can be remove; add the new helper to make bitfield update easier. Signed-off-by: Chunfeng Yun Link: https://lore.kernel.org/r/20220920090038.15133-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-io.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-io.h b/drivers/phy/mediatek/phy-mtk-io.h index 500fcdab165d..a723d4afc9b4 100644 --- a/drivers/phy/mediatek/phy-mtk-io.h +++ b/drivers/phy/mediatek/phy-mtk-io.h @@ -8,6 +8,7 @@ #ifndef __PHY_MTK_H__ #define __PHY_MTK_H__ +#include #include static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits) @@ -35,4 +36,10 @@ static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) writel(tmp, reg); } +/* field @mask should be constant and continuous */ +static inline void mtk_phy_update_field(void __iomem *reg, u32 mask, u32 val) +{ + mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); +} + #endif -- cgit v1.2.3 From 6b5ef194611e581b7da2bf0f7d3ad3950b2aaba3 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:22 +0800 Subject: phy: mediatek: tphy: remove macros to prepare bitfield value Prefer to make use of FIELD_PREP() macro to prepare bitfield value, then no need local ones anymore. Signed-off-by: Chunfeng Yun Link: https://lore.kernel.org/r/20220920090038.15133-3-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-tphy.c | 193 +++++++++++++----------------------- 1 file changed, 67 insertions(+), 126 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index cc10298bc70d..e906a82791bd 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -49,37 +49,28 @@ #define U3P_USBPHYACR0 0x000 #define PA0_RG_U2PLL_FORCE_ON BIT(15) #define PA0_USB20_PLL_PREDIV GENMASK(7, 6) -#define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6) #define PA0_RG_USB20_INTR_EN BIT(5) #define U3P_USBPHYACR1 0x004 #define PA1_RG_INTR_CAL GENMASK(23, 19) -#define PA1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19) #define PA1_RG_VRT_SEL GENMASK(14, 12) -#define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12) #define PA1_RG_TERM_SEL GENMASK(10, 8) -#define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8) #define U3P_USBPHYACR2 0x008 #define PA2_RG_U2PLL_BW GENMASK(21, 19) -#define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19) #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) #define U3P_USBPHYACR5 0x014 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) -#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) #define PA5_RG_U2_HS_100U_U3_EN BIT(11) #define U3P_USBPHYACR6 0x018 #define PA6_RG_U2_PRE_EMP GENMASK(31, 30) -#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) #define PA6_RG_U2_BC11_SW_EN BIT(23) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) #define PA6_RG_U2_DISCTH GENMASK(7, 4) -#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) #define PA6_RG_U2_SQTH GENMASK(3, 0) -#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) #define U3P_U2PHYACR4 0x020 #define P2C_RG_USB20_GPIO_CTL BIT(9) @@ -106,11 +97,9 @@ #define P2C_FORCE_SUSPENDM BIT(18) #define P2C_FORCE_TERMSEL BIT(17) #define P2C_RG_DATAIN GENMASK(13, 10) -#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) #define P2C_RG_DMPULLDOWN BIT(7) #define P2C_RG_DPPULLDOWN BIT(6) #define P2C_RG_XCVRSEL GENMASK(5, 4) -#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) #define P2C_RG_SUSPENDM BIT(3) #define P2C_RG_TERMSEL BIT(2) #define P2C_DTM0_PART_MASK \ @@ -141,87 +130,65 @@ #define U3P_U3_PHYA_REG0 0x000 #define P3A_RG_IEXT_INTR GENMASK(15, 10) -#define P3A_RG_IEXT_INTR_VAL(x) ((0x3f & (x)) << 10) #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) -#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) #define U3P_U3_PHYA_REG1 0x004 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) -#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) #define U3P_U3_PHYA_REG6 0x018 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) -#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) #define U3P_U3_PHYA_REG9 0x024 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) -#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) #define U3P_U3_PHYA_DA_REG0 0x100 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) -#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) -#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) -#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) #define U3P_U3_PHYA_DA_REG4 0x108 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) -#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) #define U3P_U3_PHYA_DA_REG5 0x10c #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) -#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) -#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) #define U3P_U3_PHYA_DA_REG6 0x110 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) -#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) #define U3P_U3_PHYA_DA_REG7 0x114 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) -#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) #define U3P_U3_PHYA_DA_REG20 0x13c #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) -#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) #define U3P_U3_PHYA_DA_REG25 0x148 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) -#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) #define U3P_U3_PHYD_LFPS1 0x00c #define P3D_RG_FWAKE_TH GENMASK(21, 16) -#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) #define U3P_U3_PHYD_IMPCAL0 0x010 #define P3D_RG_FORCE_TX_IMPEL BIT(31) #define P3D_RG_TX_IMPEL GENMASK(28, 24) -#define P3D_RG_TX_IMPEL_VAL(x) ((0x1f & (x)) << 24) #define U3P_U3_PHYD_IMPCAL1 0x014 #define P3D_RG_FORCE_RX_IMPEL BIT(31) #define P3D_RG_RX_IMPEL GENMASK(28, 24) -#define P3D_RG_RX_IMPEL_VAL(x) ((0x1f & (x)) << 24) #define U3P_U3_PHYD_RSV 0x054 #define P3D_RG_EFUSE_AUTO_LOAD_DIS BIT(12) #define U3P_U3_PHYD_CDR1 0x05c #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) -#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) -#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) #define U3P_U3_PHYD_RXDET1 0x128 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) -#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) #define U3P_U3_PHYD_RXDET2 0x12c #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) -#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) #define U3P_SPLLC_XTALCTL3 0x018 #define XC3_RG_U3_XTAL_RX_PWD BIT(9) @@ -229,10 +196,8 @@ #define U3P_U2FREQ_FMCR0 0x00 #define P2F_RG_MONCLK_SEL GENMASK(27, 26) -#define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26) #define P2F_RG_FREQDET_EN BIT(24) #define P2F_RG_CYCLECNT GENMASK(23, 0) -#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) #define U3P_U2FREQ_VALUE 0x0c @@ -249,60 +214,45 @@ #define PHYD_CTRL_SIGNAL_MODE4 0x1c /* CDR Charge Pump P-path current adjustment */ #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) -#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) -#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) #define PHYD_DESIGN_OPTION2 0x24 /* Symbol lock count selection */ #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) -#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) #define PHYD_DESIGN_OPTION9 0x40 /* COMWAK GAP width window */ #define RG_TG_MAX_MSK GENMASK(20, 16) -#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) /* COMINIT GAP width window */ #define RG_T2_MAX_MSK GENMASK(13, 8) -#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) /* COMWAK GAP width window */ #define RG_TG_MIN_MSK GENMASK(7, 5) -#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) /* COMINIT GAP width window */ #define RG_T2_MIN_MSK GENMASK(4, 0) -#define RG_T2_MIN_VAL(x) (0x1f & (x)) #define ANA_RG_CTRL_SIGNAL1 0x4c /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) -#define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) #define ANA_RG_CTRL_SIGNAL4 0x58 #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) -#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) /* Loop filter R1 resistance adjustment for Gen1 speed */ #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) -#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) #define ANA_RG_CTRL_SIGNAL6 0x60 /* I-path capacitance adjustment for Gen1 */ #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) -#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) -#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c /* RX Gen1 LEQ tuning step */ #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) -#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) -#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) -#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) /* PHY switch between pcie/usb3/sgmii/sata */ #define USB_PHY_SWITCH_CTRL 0x0 @@ -414,9 +364,9 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, /* set cycle count as 1024, and select u2 channel */ tmp = readl(fmreg + U3P_U2FREQ_FMCR0); tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); - tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); + tmp |= FIELD_PREP(P2F_RG_CYCLECNT, U3P_FM_DET_CYCLE_CNT); if (tphy->pdata->version == MTK_PHY_V1) - tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); + tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1); writel(tmp, fmreg + U3P_U2FREQ_FMCR0); @@ -449,8 +399,8 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, tphy->src_ref_clk, tphy->src_coef); /* set HS slew rate */ - mtk_phy_update_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, - PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val)); + mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, + calibration_val); /* disable USB ring oscillator */ mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); @@ -460,33 +410,30 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { struct u3phy_banks *u3_banks = &instance->u3_banks; + void __iomem *phya = u3_banks->phya; + void __iomem *phyd = u3_banks->phyd; /* gating PCIe Analog XTAL clock */ mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); /* gating XSQ */ - mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_DA_REG0, - P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2); - mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG9, - P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); + mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4); - mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG6, - P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); + mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe); mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1, P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1, - P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3)); + FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) | + FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3)); - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_LFPS1, - P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34)); + mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34); - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET1, - P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10)); + mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10); - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET2, - P3D_RG_RXDET_STB2_SET_P3, P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); + mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10); dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); } @@ -500,11 +447,9 @@ static void u2_phy_pll_26m_set(struct mtk_tphy *tphy, if (!tphy->pdata->sw_pll_48m_to_26m) return; - mtk_phy_update_bits(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, - PA0_USB20_PLL_PREDIV_VAL(0)); + mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0); - mtk_phy_update_bits(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, - PA2_RG_U2PLL_BW_VAL(3)); + mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3); writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV); @@ -550,7 +495,7 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy, /* DP/DM BC1.1 path Disable */ mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN); - mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2)); + mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2); /* Workaround only for mt8195, HW fix it for others (V3) */ u2_phy_pll_26m_set(tphy, instance); @@ -653,43 +598,39 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy, mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, - P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2)); + FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | + FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2)); /* ref clk drive */ - mtk_phy_update_bits(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, - P3A_RG_CLKDRV_AMP_VAL(0x4)); + mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4); - mtk_phy_update_bits(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, - P3A_RG_CLKDRV_OFF_VAL(0x1)); + mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1); /* SSC delta -5000ppm */ - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, - P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c)); + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c); - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, - P3A_RG_PLL_DELTA_PE2H_VAL(0x36)); + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36); /* change pll BW 0.6M */ mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5, P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, - P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1)); + FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) | + FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1)); mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4, P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, - P3A_RG_PLL_BC_PE2H_VAL(0x3)); + FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3)); - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, - P3A_RG_PLL_IR_PE2H_VAL(0x2)); + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2); - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, - P3A_RG_PLL_BP_PE2H_VAL(0xa)); + mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa); /* Tx Detect Rx Timing: 10us -> 5us */ - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET1, - P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10)); + mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1, + P3D_RG_RXDET_STB2_SET, 0x10); - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET2, - P3D_RG_RXDET_STB2_SET_P3, P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); + mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2, + P3D_RG_RXDET_STB2_SET_P3, 0x10); /* wait for PCIe subsys register to active */ usleep_range(2500, 3000); @@ -730,38 +671,38 @@ static void sata_phy_instance_init(struct mtk_tphy *tphy, /* charge current adjustment */ mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6, RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK, - RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a)); + FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) | + FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a)); - mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, - RG_CDR_BIRLTD0_GEN1_VAL(0x18)); + mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18); - mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, - RG_CDR_BIRLTD0_GEN3_VAL(0x06)); + mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06); mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4, RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK, - RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07)); + FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) | + FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07)); mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4, RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK, - RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02)); + FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) | + FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02)); - mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, - RG_LOCK_CNT_SEL_VAL(0x02)); + mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02); mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, RG_T2_MIN_MSK | RG_TG_MIN_MSK, - RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04)); + FIELD_PREP(RG_T2_MIN_MSK, 0x12) | + FIELD_PREP(RG_TG_MIN_MSK, 0x04)); mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, RG_T2_MAX_MSK | RG_TG_MAX_MSK, - RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e)); + FIELD_PREP(RG_T2_MAX_MSK, 0x31) | + FIELD_PREP(RG_TG_MAX_MSK, 0x0e)); - mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, - RG_IDRV_0DB_GEN1_VAL(0x20)); + mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20); - mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, - RG_EQ_DLEQ_LFI_GEN1_VAL(0x03)); + mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03); dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); } @@ -857,33 +798,33 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN); if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) - mtk_phy_update_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, - PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src)); + mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, + instance->eye_src); if (instance->eye_vrt) - mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, - PA1_RG_VRT_SEL_VAL(instance->eye_vrt)); + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, + instance->eye_vrt); if (instance->eye_term) - mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, - PA1_RG_TERM_SEL_VAL(instance->eye_term)); + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, + instance->eye_term); if (instance->intr) { if (u2_banks->misc) mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS); - mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, - PA1_RG_INTR_CAL_VAL(instance->intr)); + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, + instance->intr); } if (instance->discth) - mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, - PA6_RG_U2_DISCTH_VAL(instance->discth)); + mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, + instance->discth); if (instance->pre_emphasis) - mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, - PA6_RG_U2_PRE_EMP_VAL(instance->pre_emphasis)); + mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, + instance->pre_emphasis); } /* type switch for usb3/pcie/sgmii/sata */ @@ -1032,23 +973,23 @@ static void phy_efuse_set(struct mtk_phy_instance *instance) case PHY_TYPE_USB2: mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS); - mtk_phy_update_bits(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, - PA1_RG_INTR_CAL_VAL(instance->efuse_intr)); + mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, + instance->efuse_intr); break; case PHY_TYPE_USB3: case PHY_TYPE_PCIE: mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS); - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, - P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp)); + mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, + instance->efuse_tx_imp); mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); - mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, - P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp)); + mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, + instance->efuse_rx_imp); mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); - mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, - P3A_RG_IEXT_INTR_VAL(instance->efuse_intr)); + mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, + instance->efuse_intr); break; default: dev_warn(dev, "no sw efuse for type %d\n", instance->type); -- cgit v1.2.3 From c221baa355483548fb01456442615a838e66aec6 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:23 +0800 Subject: phy: mediatek: xsphy: remove macros used to prepare bitfield value Prefer to make use of FIELD_PREP() macro to prepare bitfield value, then no need local ones anymore. Signed-off-by: Chunfeng Yun Link: https://lore.kernel.org/r/20220920090038.15133-4-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-xsphy.c | 46 +++++++++++++----------------------- 1 file changed, 17 insertions(+), 29 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-xsphy.c b/drivers/phy/mediatek/phy-mtk-xsphy.c index c0cdb78f77fa..b222fbbd71d1 100644 --- a/drivers/phy/mediatek/phy-mtk-xsphy.c +++ b/drivers/phy/mediatek/phy-mtk-xsphy.c @@ -37,7 +37,6 @@ #define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00) #define P2F_RG_FREQDET_EN BIT(24) #define P2F_RG_CYCLECNT GENMASK(23, 0) -#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) #define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c) @@ -50,16 +49,12 @@ #define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04) #define P2A1_RG_INTR_CAL GENMASK(23, 19) -#define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19) #define P2A1_RG_VRT_SEL GENMASK(14, 12) -#define P2A1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12) #define P2A1_RG_TERM_SEL GENMASK(10, 8) -#define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8) #define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014) #define P2A5_RG_HSTX_SRCAL_EN BIT(15) #define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12) -#define P2A5_RG_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) #define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018) #define P2A6_RG_BC11_SW_EN BIT(23) @@ -74,15 +69,12 @@ #define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00) #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16) -#define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x) ((0x3f & (x)) << 16) #define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04) #define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0) -#define RG_XTP_LN0_TX_IMPSEL_VAL(x) (0x1f & (x)) #define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014) #define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0) -#define RG_XTP_LN0_RX_IMPSEL_VAL(x) (0x1f & (x)) #define XSP_REF_CLK 26 /* MHZ */ #define XSP_SLEW_RATE_COEF 17 @@ -134,8 +126,8 @@ static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy, mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); /* set cycle count as 1024 */ - mtk_phy_update_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT, - P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT)); + mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT, + XSP_FM_DET_CYCLE_CNT); /* enable frequency meter */ mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); @@ -166,8 +158,7 @@ static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy, xsphy->src_ref_clk, xsphy->src_coef); /* set HS slew rate */ - mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, - P2A5_RG_HSTX_SRCTRL_VAL(calib_val)); + mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val); /* disable USB ring oscillator */ mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); @@ -280,20 +271,20 @@ static void u2_phy_props_set(struct mtk_xsphy *xsphy, void __iomem *pbase = inst->port_base; if (inst->efuse_intr) - mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL, - P2A1_RG_INTR_CAL_VAL(inst->efuse_intr)); + mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL, + inst->efuse_intr); if (inst->eye_src) - mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, - P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src)); + mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, + inst->eye_src); if (inst->eye_vrt) - mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL, - P2A1_RG_VRT_SEL_VAL(inst->eye_vrt)); + mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL, + inst->eye_vrt); if (inst->eye_term) - mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, - P2A1_RG_TERM_SEL_VAL(inst->eye_term)); + mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, + inst->eye_term); } static void u3_phy_props_set(struct mtk_xsphy *xsphy, @@ -302,19 +293,16 @@ static void u3_phy_props_set(struct mtk_xsphy *xsphy, void __iomem *pbase = inst->port_base; if (inst->efuse_intr) - mtk_phy_update_bits(xsphy->glb_base + SSPXTP_PHYA_GLB_00, - RG_XTP_GLB_BIAS_INTR_CTRL, - RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr)); + mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00, + RG_XTP_GLB_BIAS_INTR_CTRL, inst->efuse_intr); if (inst->efuse_tx_imp) - mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_04, - RG_XTP_LN0_TX_IMPSEL, - RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp)); + mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04, + RG_XTP_LN0_TX_IMPSEL, inst->efuse_tx_imp); if (inst->efuse_rx_imp) - mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_14, - RG_XTP_LN0_RX_IMPSEL, - RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp)); + mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14, + RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp); } static int mtk_phy_init(struct phy *phy) -- cgit v1.2.3 From 2b0c0043846c5c06d52f45f089f7996371359718 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:24 +0800 Subject: phy: mediatek: ufs: use common register access helpers No need define private register access helpers, use common ones defined in phy-mtk-io.h Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-5-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-ufs.c | 78 ++++++++++++++------------------------ 1 file changed, 28 insertions(+), 50 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c index a6af06941203..fc19e0fa8ed5 100644 --- a/drivers/phy/mediatek/phy-mtk-ufs.c +++ b/drivers/phy/mediatek/phy-mtk-ufs.c @@ -11,6 +11,8 @@ #include #include +#include "phy-mtk-io.h" + /* mphy register and offsets */ #define MP_GLB_DIG_8C 0x008C #define FRC_PLL_ISO_EN BIT(8) @@ -39,34 +41,6 @@ struct ufs_mtk_phy { struct clk_bulk_data clks[UFSPHY_CLKS_CNT]; }; -static inline u32 mphy_readl(struct ufs_mtk_phy *phy, u32 reg) -{ - return readl(phy->mmio + reg); -} - -static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg) -{ - writel(val, phy->mmio + reg); -} - -static void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit) -{ - u32 val; - - val = mphy_readl(phy, reg); - val |= bit; - mphy_writel(phy, val, reg); -} - -static void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit) -{ - u32 val; - - val = mphy_readl(phy, reg); - val &= ~bit; - mphy_writel(phy, val, reg); -} - static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy) { return (struct ufs_mtk_phy *)phy_get_drvdata(generic_phy); @@ -84,57 +58,61 @@ static int ufs_mtk_phy_clk_init(struct ufs_mtk_phy *phy) static void ufs_mtk_phy_set_active(struct ufs_mtk_phy *phy) { + void __iomem *mmio = phy->mmio; + /* release DA_MP_PLL_PWR_ON */ - mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON); - mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON); + mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); + mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); /* release DA_MP_PLL_ISO_EN */ - mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN); - mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN); + mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); + mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); /* release DA_MP_CDR_PWR_ON */ - mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON); - mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON); + mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); + mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); /* release DA_MP_CDR_ISO_EN */ - mphy_clr_bit(phy, MP_LN_RX_44, CDR_ISO_EN); - mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN); + mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); + mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); /* release DA_MP_RX0_SQ_EN */ - mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN); - mphy_clr_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); + mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); + mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); /* delay 1us to wait DIFZ stable */ udelay(1); /* release DIFZ */ - mphy_clr_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); + mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); } static void ufs_mtk_phy_set_deep_hibern(struct ufs_mtk_phy *phy) { + void __iomem *mmio = phy->mmio; + /* force DIFZ */ - mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); + mtk_phy_set_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); /* force DA_MP_RX0_SQ_EN */ - mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); - mphy_clr_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN); + mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); + mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); /* force DA_MP_CDR_ISO_EN */ - mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN); - mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN); + mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); + mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); /* force DA_MP_CDR_PWR_ON */ - mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON); - mphy_clr_bit(phy, MP_LN_RX_44, CDR_PWR_ON); + mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); + mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); /* force DA_MP_PLL_ISO_EN */ - mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN); - mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN); + mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); + mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); /* force DA_MP_PLL_PWR_ON */ - mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON); - mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON); + mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); + mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); } static int ufs_mtk_phy_power_on(struct phy *generic_phy) -- cgit v1.2.3 From d87f2b83739bdfdb5d2787886e247e5a174b4e90 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:25 +0800 Subject: phy: mediatek: pcie: use new helper to update register bits The new helper will use FIELD_PREP() macro to prepare bits value according to mask, then we no need do it anymore. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-6-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-pcie.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c index 7f29d43442bf..25dbd6e35722 100644 --- a/drivers/phy/mediatek/phy-mtk-pcie.c +++ b/drivers/phy/mediatek/phy-mtk-pcie.c @@ -89,14 +89,14 @@ static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy, addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG + lane * PEXTP_ANA_LANE_OFFSET; - mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL, - FIELD_PREP(EFUSE_LN_TX_PMOS_SEL, data->tx_pmos)); + mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL, + data->tx_pmos); - mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL, - FIELD_PREP(EFUSE_LN_TX_NMOS_SEL, data->tx_nmos)); + mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL, + data->tx_nmos); - mtk_phy_update_bits(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL, - FIELD_PREP(EFUSE_LN_RX_SEL, data->rx_data)); + mtk_phy_update_field(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL, + data->rx_data); } /** @@ -116,9 +116,8 @@ static int mtk_pcie_phy_init(struct phy *phy) return 0; /* Set global data */ - mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG, - EFUSE_GLB_INTR_SEL, - FIELD_PREP(EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr)); + mtk_phy_update_field(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG, + EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr); for (i = 0; i < pcie_phy->data->num_lanes; i++) mtk_pcie_efuse_set_lane(pcie_phy, i); -- cgit v1.2.3 From b0870c0151440121e78586c7681c5599a1e4eba8 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:26 +0800 Subject: phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits Use GENMASK() and BIT() macros to generate mask and bits Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-7-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 56 +++++++++++++++--------------- 1 file changed, 28 insertions(+), 28 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c index b74c65a1762c..ce36f37c698d 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c @@ -8,62 +8,62 @@ #define HDMI_CON0 0x00 #define RG_HDMITX_DRV_IBIAS 0 -#define RG_HDMITX_DRV_IBIAS_MASK (0x3f << 0) +#define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0) #define RG_HDMITX_EN_SER 12 -#define RG_HDMITX_EN_SER_MASK (0x0f << 12) +#define RG_HDMITX_EN_SER_MASK GENMASK(15, 12) #define RG_HDMITX_EN_SLDO 16 -#define RG_HDMITX_EN_SLDO_MASK (0x0f << 16) +#define RG_HDMITX_EN_SLDO_MASK GENMASK(19, 16) #define RG_HDMITX_EN_PRED 20 -#define RG_HDMITX_EN_PRED_MASK (0x0f << 20) +#define RG_HDMITX_EN_PRED_MASK GENMASK(23, 20) #define RG_HDMITX_EN_IMP 24 -#define RG_HDMITX_EN_IMP_MASK (0x0f << 24) +#define RG_HDMITX_EN_IMP_MASK GENMASK(27, 24) #define RG_HDMITX_EN_DRV 28 -#define RG_HDMITX_EN_DRV_MASK (0x0f << 28) +#define RG_HDMITX_EN_DRV_MASK GENMASK(31, 28) #define HDMI_CON1 0x04 #define RG_HDMITX_PRED_IBIAS 18 -#define RG_HDMITX_PRED_IBIAS_MASK (0x0f << 18) -#define RG_HDMITX_PRED_IMP (0x01 << 22) +#define RG_HDMITX_PRED_IBIAS_MASK GENMASK(21, 18) +#define RG_HDMITX_PRED_IMP BIT(22) #define RG_HDMITX_DRV_IMP 26 -#define RG_HDMITX_DRV_IMP_MASK (0x3f << 26) +#define RG_HDMITX_DRV_IMP_MASK GENMASK(31, 26) #define HDMI_CON2 0x08 -#define RG_HDMITX_EN_TX_CKLDO (0x01 << 0) -#define RG_HDMITX_EN_TX_POSDIV (0x01 << 1) +#define RG_HDMITX_EN_TX_CKLDO BIT(0) +#define RG_HDMITX_EN_TX_POSDIV BIT(1) #define RG_HDMITX_TX_POSDIV 3 -#define RG_HDMITX_TX_POSDIV_MASK (0x03 << 3) -#define RG_HDMITX_EN_MBIAS (0x01 << 6) -#define RG_HDMITX_MBIAS_LPF_EN (0x01 << 7) +#define RG_HDMITX_TX_POSDIV_MASK GENMASK(4, 3) +#define RG_HDMITX_EN_MBIAS BIT(6) +#define RG_HDMITX_MBIAS_LPF_EN BIT(7) #define HDMI_CON4 0x10 -#define RG_HDMITX_RESERVE_MASK (0xffffffff << 0) +#define RG_HDMITX_RESERVE_MASK GENMASK(31, 0) #define HDMI_CON6 0x18 #define RG_HTPLL_BR 0 -#define RG_HTPLL_BR_MASK (0x03 << 0) +#define RG_HTPLL_BR_MASK GENMASK(1, 0) #define RG_HTPLL_BC 2 -#define RG_HTPLL_BC_MASK (0x03 << 2) +#define RG_HTPLL_BC_MASK GENMASK(3, 2) #define RG_HTPLL_BP 4 -#define RG_HTPLL_BP_MASK (0x0f << 4) +#define RG_HTPLL_BP_MASK GENMASK(7, 4) #define RG_HTPLL_IR 8 -#define RG_HTPLL_IR_MASK (0x0f << 8) +#define RG_HTPLL_IR_MASK GENMASK(11, 8) #define RG_HTPLL_IC 12 -#define RG_HTPLL_IC_MASK (0x0f << 12) +#define RG_HTPLL_IC_MASK GENMASK(15, 12) #define RG_HTPLL_POSDIV 16 -#define RG_HTPLL_POSDIV_MASK (0x03 << 16) +#define RG_HTPLL_POSDIV_MASK GENMASK(17, 16) #define RG_HTPLL_PREDIV 18 -#define RG_HTPLL_PREDIV_MASK (0x03 << 18) +#define RG_HTPLL_PREDIV_MASK GENMASK(19, 18) #define RG_HTPLL_FBKSEL 20 -#define RG_HTPLL_FBKSEL_MASK (0x03 << 20) -#define RG_HTPLL_RLH_EN (0x01 << 22) +#define RG_HTPLL_FBKSEL_MASK GENMASK(21, 20) +#define RG_HTPLL_RLH_EN BIT(22) #define RG_HTPLL_FBKDIV 24 -#define RG_HTPLL_FBKDIV_MASK (0x7f << 24) -#define RG_HTPLL_EN (0x01 << 31) +#define RG_HTPLL_FBKDIV_MASK GENMASK(30, 24) +#define RG_HTPLL_EN BIT(31) #define HDMI_CON7 0x1c -#define RG_HTPLL_AUTOK_EN (0x01 << 23) +#define RG_HTPLL_AUTOK_EN BIT(23) #define RG_HTPLL_DIVEN 28 -#define RG_HTPLL_DIVEN_MASK (0x07 << 28) +#define RG_HTPLL_DIVEN_MASK GENMASK(30, 28) static int mtk_hdmi_pll_prepare(struct clk_hw *hw) { -- cgit v1.2.3 From a98d935eacc75a6e956045bdef91c7c2dad729f6 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:27 +0800 Subject: phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field Use FIELD_PREP() macro to prepare bits field value, then no need define macros of bits offset. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-8-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 60 +++++++++++------------------- 1 file changed, 21 insertions(+), 39 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c index ce36f37c698d..af6e8ed348cb 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c @@ -7,30 +7,21 @@ #include "phy-mtk-hdmi.h" #define HDMI_CON0 0x00 -#define RG_HDMITX_DRV_IBIAS 0 #define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0) -#define RG_HDMITX_EN_SER 12 #define RG_HDMITX_EN_SER_MASK GENMASK(15, 12) -#define RG_HDMITX_EN_SLDO 16 #define RG_HDMITX_EN_SLDO_MASK GENMASK(19, 16) -#define RG_HDMITX_EN_PRED 20 #define RG_HDMITX_EN_PRED_MASK GENMASK(23, 20) -#define RG_HDMITX_EN_IMP 24 #define RG_HDMITX_EN_IMP_MASK GENMASK(27, 24) -#define RG_HDMITX_EN_DRV 28 #define RG_HDMITX_EN_DRV_MASK GENMASK(31, 28) #define HDMI_CON1 0x04 -#define RG_HDMITX_PRED_IBIAS 18 #define RG_HDMITX_PRED_IBIAS_MASK GENMASK(21, 18) #define RG_HDMITX_PRED_IMP BIT(22) -#define RG_HDMITX_DRV_IMP 26 #define RG_HDMITX_DRV_IMP_MASK GENMASK(31, 26) #define HDMI_CON2 0x08 #define RG_HDMITX_EN_TX_CKLDO BIT(0) #define RG_HDMITX_EN_TX_POSDIV BIT(1) -#define RG_HDMITX_TX_POSDIV 3 #define RG_HDMITX_TX_POSDIV_MASK GENMASK(4, 3) #define RG_HDMITX_EN_MBIAS BIT(6) #define RG_HDMITX_MBIAS_LPF_EN BIT(7) @@ -39,30 +30,20 @@ #define RG_HDMITX_RESERVE_MASK GENMASK(31, 0) #define HDMI_CON6 0x18 -#define RG_HTPLL_BR 0 #define RG_HTPLL_BR_MASK GENMASK(1, 0) -#define RG_HTPLL_BC 2 #define RG_HTPLL_BC_MASK GENMASK(3, 2) -#define RG_HTPLL_BP 4 #define RG_HTPLL_BP_MASK GENMASK(7, 4) -#define RG_HTPLL_IR 8 #define RG_HTPLL_IR_MASK GENMASK(11, 8) -#define RG_HTPLL_IC 12 #define RG_HTPLL_IC_MASK GENMASK(15, 12) -#define RG_HTPLL_POSDIV 16 #define RG_HTPLL_POSDIV_MASK GENMASK(17, 16) -#define RG_HTPLL_PREDIV 18 #define RG_HTPLL_PREDIV_MASK GENMASK(19, 18) -#define RG_HTPLL_FBKSEL 20 #define RG_HTPLL_FBKSEL_MASK GENMASK(21, 20) #define RG_HTPLL_RLH_EN BIT(22) -#define RG_HTPLL_FBKDIV 24 #define RG_HTPLL_FBKDIV_MASK GENMASK(30, 24) #define RG_HTPLL_EN BIT(31) #define HDMI_CON7 0x1c #define RG_HTPLL_AUTOK_EN BIT(23) -#define RG_HTPLL_DIVEN 28 #define RG_HTPLL_DIVEN_MASK GENMASK(30, 28) static int mtk_hdmi_pll_prepare(struct clk_hw *hw) @@ -128,33 +109,33 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK); mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IC_MASK, 0x1), RG_HTPLL_IC_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IR_MASK, 0x1), RG_HTPLL_IR_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, FIELD_PREP(RG_HDMITX_TX_POSDIV_MASK, pos_div), RG_HDMITX_TX_POSDIV_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKSEL_MASK, 1), RG_HTPLL_FBKSEL_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKDIV_MASK, 19), RG_HTPLL_FBKDIV_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, FIELD_PREP(RG_HTPLL_DIVEN_MASK, 0x2), RG_HTPLL_DIVEN_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BP_MASK, 0xc), RG_HTPLL_BP_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BC_MASK, 0x2), RG_HTPLL_BC_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BR_MASK, 0x1), RG_HTPLL_BR_MASK); mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_PRED_IBIAS_MASK, 0x3), RG_HDMITX_PRED_IBIAS_MASK); mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_DRV_IMP_MASK, 0x28), RG_HDMITX_DRV_IMP_MASK); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS), + mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, FIELD_PREP(RG_HDMITX_DRV_IBIAS_MASK, 0xa), RG_HDMITX_DRV_IBIAS_MASK); return 0; } @@ -164,9 +145,10 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); unsigned long out_rate, val; + u32 tmp; - val = (readl(hdmi_phy->regs + HDMI_CON6) - & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV; + tmp = readl(hdmi_phy->regs + HDMI_CON6); + val = FIELD_GET(RG_HTPLL_PREDIV_MASK, tmp); switch (val) { case 0x00: out_rate = parent_rate; @@ -179,14 +161,14 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, break; } - val = (readl(hdmi_phy->regs + HDMI_CON6) - & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV; + val = FIELD_GET(RG_HTPLL_FBKDIV_MASK, tmp); out_rate *= (val + 1) * 2; - val = (readl(hdmi_phy->regs + HDMI_CON2) - & RG_HDMITX_TX_POSDIV_MASK); - out_rate >>= (val >> RG_HDMITX_TX_POSDIV); - if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV) + tmp = readl(hdmi_phy->regs + HDMI_CON2); + val = FIELD_GET(RG_HDMITX_TX_POSDIV_MASK, tmp); + out_rate >>= val; + + if (tmp & RG_HDMITX_EN_TX_POSDIV) out_rate /= 5; return out_rate; -- cgit v1.2.3 From cff81a618a53491c783bd798da304c085851361b Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:28 +0800 Subject: phy: mediatek: hdmi: mt2701: use common helper to access registers Use MediaTek phy's common helper to access registers, then we can remove hdmi's I/O helpers. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-9-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 146 ++++++++++++++--------------- 1 file changed, 71 insertions(+), 75 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c index af6e8ed348cb..e51b2d13eab4 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c @@ -5,6 +5,7 @@ */ #include "phy-mtk-hdmi.h" +#include "phy-mtk-io.h" #define HDMI_CON0 0x00 #define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0) @@ -49,20 +50,21 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); + void __iomem *base = hdmi_phy->regs; - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); + mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); usleep_range(80, 100); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); usleep_range(80, 100); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); usleep_range(80, 100); return 0; } @@ -70,20 +72,21 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); + void __iomem *base = hdmi_phy->regs; - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); usleep_range(80, 100); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); usleep_range(80, 100); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); + mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); usleep_range(80, 100); } @@ -97,6 +100,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); + void __iomem *base = hdmi_phy->regs; u32 pos_div; if (rate <= 64000000) @@ -106,37 +110,25 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, else pos_div = 1; - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IC_MASK, 0x1), - RG_HTPLL_IC_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IR_MASK, 0x1), - RG_HTPLL_IR_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, FIELD_PREP(RG_HDMITX_TX_POSDIV_MASK, pos_div), - RG_HDMITX_TX_POSDIV_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKSEL_MASK, 1), - RG_HTPLL_FBKSEL_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKDIV_MASK, 19), - RG_HTPLL_FBKDIV_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, FIELD_PREP(RG_HTPLL_DIVEN_MASK, 0x2), - RG_HTPLL_DIVEN_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BP_MASK, 0xc), - RG_HTPLL_BP_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BC_MASK, 0x2), - RG_HTPLL_BC_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BR_MASK, 0x1), - RG_HTPLL_BR_MASK); - - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_PRED_IBIAS_MASK, 0x3), - RG_HDMITX_PRED_IBIAS_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_DRV_IMP_MASK, 0x28), - RG_HDMITX_DRV_IMP_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, FIELD_PREP(RG_HDMITX_DRV_IBIAS_MASK, 0xa), - RG_HDMITX_DRV_IBIAS_MASK); + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK); + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1); + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1); + mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div); + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1); + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19); + mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2); + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc); + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2); + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1); + + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP); + mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK); + mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28); + mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28); + mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa); return 0; } @@ -184,37 +176,41 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = { static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) { - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); + void __iomem *base = hdmi_phy->regs; + + mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); usleep_range(80, 100); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); usleep_range(80, 100); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); usleep_range(80, 100); } static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) { - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); + void __iomem *base = hdmi_phy->regs; + + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); usleep_range(80, 100); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); usleep_range(80, 100); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); + mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); usleep_range(80, 100); } -- cgit v1.2.3 From a8a78274c6b4ce7af1616ff29551e1808ffa43bb Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:29 +0800 Subject: phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask Use GENMASK() macro to generate bits mask Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-10-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 88 +++++++++++++++--------------- 1 file changed, 44 insertions(+), 44 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c index 6cdfdf5a698a..55fe97f5465d 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c @@ -8,38 +8,38 @@ #define HDMI_CON0 0x00 #define RG_HDMITX_PLL_EN BIT(31) -#define RG_HDMITX_PLL_FBKDIV (0x7f << 24) +#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24) #define PLL_FBKDIV_SHIFT 24 -#define RG_HDMITX_PLL_FBKSEL (0x3 << 22) +#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22) #define PLL_FBKSEL_SHIFT 22 -#define RG_HDMITX_PLL_PREDIV (0x3 << 20) +#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20) #define PREDIV_SHIFT 20 -#define RG_HDMITX_PLL_POSDIV (0x3 << 18) +#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18) #define POSDIV_SHIFT 18 -#define RG_HDMITX_PLL_RST_DLY (0x3 << 16) -#define RG_HDMITX_PLL_IR (0xf << 12) +#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16) +#define RG_HDMITX_PLL_IR GENMASK(15, 12) #define PLL_IR_SHIFT 12 -#define RG_HDMITX_PLL_IC (0xf << 8) +#define RG_HDMITX_PLL_IC GENMASK(11, 8) #define PLL_IC_SHIFT 8 -#define RG_HDMITX_PLL_BP (0xf << 4) +#define RG_HDMITX_PLL_BP GENMASK(7, 4) #define PLL_BP_SHIFT 4 -#define RG_HDMITX_PLL_BR (0x3 << 2) +#define RG_HDMITX_PLL_BR GENMASK(3, 2) #define PLL_BR_SHIFT 2 -#define RG_HDMITX_PLL_BC (0x3 << 0) +#define RG_HDMITX_PLL_BC GENMASK(1, 0) #define PLL_BC_SHIFT 0 #define HDMI_CON1 0x04 -#define RG_HDMITX_PLL_DIVEN (0x7 << 29) +#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29) #define PLL_DIVEN_SHIFT 29 #define RG_HDMITX_PLL_AUTOK_EN BIT(28) -#define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26) -#define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24) +#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26) +#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24) #define RG_HDMITX_PLL_AUTOK_LOAD BIT(23) -#define RG_HDMITX_PLL_BAND (0x3f << 16) +#define RG_HDMITX_PLL_BAND GENMASK(21, 16) #define RG_HDMITX_PLL_REF_SEL BIT(15) #define RG_HDMITX_PLL_BIAS_EN BIT(14) #define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13) #define RG_HDMITX_PLL_TXDIV_EN BIT(12) -#define RG_HDMITX_PLL_TXDIV (0x3 << 10) +#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10) #define PLL_TXDIV_SHIFT 10 #define RG_HDMITX_PLL_LVROD_EN BIT(9) #define RG_HDMITX_PLL_MONVC_EN BIT(8) @@ -47,64 +47,64 @@ #define RG_HDMITX_PLL_MONREF_EN BIT(6) #define RG_HDMITX_PLL_TST_EN BIT(5) #define RG_HDMITX_PLL_TST_CK_EN BIT(4) -#define RG_HDMITX_PLL_TST_SEL (0xf << 0) +#define RG_HDMITX_PLL_TST_SEL GENMASK(3, 0) #define HDMI_CON2 0x08 -#define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8) +#define RGS_HDMITX_PLL_AUTOK_BAND GENMASK(14, 8) #define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1) #define RG_HDMITX_EN_TX_CKLDO BIT(0) #define HDMI_CON3 0x0c -#define RG_HDMITX_SER_EN (0xf << 28) -#define RG_HDMITX_PRD_EN (0xf << 24) -#define RG_HDMITX_PRD_IMP_EN (0xf << 20) -#define RG_HDMITX_DRV_EN (0xf << 16) -#define RG_HDMITX_DRV_IMP_EN (0xf << 12) +#define RG_HDMITX_SER_EN GENMASK(31, 28) +#define RG_HDMITX_PRD_EN GENMASK(27, 24) +#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20) +#define RG_HDMITX_DRV_EN GENMASK(19, 16) +#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12) #define DRV_IMP_EN_SHIFT 12 #define RG_HDMITX_MHLCK_FORCE BIT(10) #define RG_HDMITX_MHLCK_PPIX_EN BIT(9) #define RG_HDMITX_MHLCK_EN BIT(8) -#define RG_HDMITX_SER_DIN_SEL (0xf << 4) +#define RG_HDMITX_SER_DIN_SEL GENMASK(7, 4) #define RG_HDMITX_SER_5T1_BIST_EN BIT(3) #define RG_HDMITX_SER_BIST_TOG BIT(2) #define RG_HDMITX_SER_DIN_TOG BIT(1) #define RG_HDMITX_SER_CLKDIG_INV BIT(0) #define HDMI_CON4 0x10 -#define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24) -#define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16) -#define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8) -#define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0) +#define RG_HDMITX_PRD_IBIAS_CLK GENMASK(27, 24) +#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16) +#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8) +#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0) #define PRD_IBIAS_CLK_SHIFT 24 #define PRD_IBIAS_D2_SHIFT 16 #define PRD_IBIAS_D1_SHIFT 8 #define PRD_IBIAS_D0_SHIFT 0 #define HDMI_CON5 0x14 -#define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24) -#define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16) -#define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8) -#define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0) +#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24) +#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16) +#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8) +#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0) #define DRV_IBIAS_CLK_SHIFT 24 #define DRV_IBIAS_D2_SHIFT 16 #define DRV_IBIAS_D1_SHIFT 8 #define DRV_IBIAS_D0_SHIFT 0 #define HDMI_CON6 0x18 -#define RG_HDMITX_DRV_IMP_CLK (0x3f << 24) -#define RG_HDMITX_DRV_IMP_D2 (0x3f << 16) -#define RG_HDMITX_DRV_IMP_D1 (0x3f << 8) -#define RG_HDMITX_DRV_IMP_D0 (0x3f << 0) +#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24) +#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16) +#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8) +#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0) #define DRV_IMP_CLK_SHIFT 24 #define DRV_IMP_D2_SHIFT 16 #define DRV_IMP_D1_SHIFT 8 #define DRV_IMP_D0_SHIFT 0 #define HDMI_CON7 0x1c -#define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27) -#define RG_HDMITX_SER_DIN (0x3ff << 16) -#define RG_HDMITX_CHLDC_TST (0xf << 12) -#define RG_HDMITX_CHLCK_TST (0xf << 8) -#define RG_HDMITX_RESERVE (0xff << 0) +#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27) +#define RG_HDMITX_SER_DIN GENMASK(25, 16) +#define RG_HDMITX_CHLDC_TST GENMASK(15, 12) +#define RG_HDMITX_CHLCK_TST GENMASK(11, 8) +#define RG_HDMITX_RESERVE GENMASK(7, 0) #define HDMI_CON8 0x20 -#define RGS_HDMITX_2T1_LEV (0xf << 16) -#define RGS_HDMITX_2T1_EDG (0xf << 12) -#define RGS_HDMITX_5T1_LEV (0xf << 8) -#define RGS_HDMITX_5T1_EDG (0xf << 4) +#define RGS_HDMITX_2T1_LEV GENMASK(19, 16) +#define RGS_HDMITX_2T1_EDG GENMASK(15, 12) +#define RGS_HDMITX_5T1_LEV GENMASK(11, 8) +#define RGS_HDMITX_5T1_EDG GENMASK(7, 4) #define RGS_HDMITX_PLUG_TST BIT(0) static int mtk_hdmi_pll_prepare(struct clk_hw *hw) -- cgit v1.2.3 From 309b4fec539cee6fe7a52938fbfdb6a893237cbd Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:30 +0800 Subject: phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field Use FIELD_PREP() macro to prepare bits field value, then no need define macros of bits offset. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-11-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 70 +++++++++++------------------- 1 file changed, 26 insertions(+), 44 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c index 55fe97f5465d..8f93991fb09d 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c @@ -9,27 +9,17 @@ #define HDMI_CON0 0x00 #define RG_HDMITX_PLL_EN BIT(31) #define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24) -#define PLL_FBKDIV_SHIFT 24 #define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22) -#define PLL_FBKSEL_SHIFT 22 #define RG_HDMITX_PLL_PREDIV GENMASK(21, 20) -#define PREDIV_SHIFT 20 #define RG_HDMITX_PLL_POSDIV GENMASK(19, 18) -#define POSDIV_SHIFT 18 #define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16) #define RG_HDMITX_PLL_IR GENMASK(15, 12) -#define PLL_IR_SHIFT 12 #define RG_HDMITX_PLL_IC GENMASK(11, 8) -#define PLL_IC_SHIFT 8 #define RG_HDMITX_PLL_BP GENMASK(7, 4) -#define PLL_BP_SHIFT 4 #define RG_HDMITX_PLL_BR GENMASK(3, 2) -#define PLL_BR_SHIFT 2 #define RG_HDMITX_PLL_BC GENMASK(1, 0) -#define PLL_BC_SHIFT 0 #define HDMI_CON1 0x04 #define RG_HDMITX_PLL_DIVEN GENMASK(31, 29) -#define PLL_DIVEN_SHIFT 29 #define RG_HDMITX_PLL_AUTOK_EN BIT(28) #define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26) #define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24) @@ -40,7 +30,6 @@ #define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13) #define RG_HDMITX_PLL_TXDIV_EN BIT(12) #define RG_HDMITX_PLL_TXDIV GENMASK(11, 10) -#define PLL_TXDIV_SHIFT 10 #define RG_HDMITX_PLL_LVROD_EN BIT(9) #define RG_HDMITX_PLL_MONVC_EN BIT(8) #define RG_HDMITX_PLL_MONCK_EN BIT(7) @@ -58,7 +47,6 @@ #define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20) #define RG_HDMITX_DRV_EN GENMASK(19, 16) #define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12) -#define DRV_IMP_EN_SHIFT 12 #define RG_HDMITX_MHLCK_FORCE BIT(10) #define RG_HDMITX_MHLCK_PPIX_EN BIT(9) #define RG_HDMITX_MHLCK_EN BIT(8) @@ -72,28 +60,16 @@ #define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16) #define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8) #define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0) -#define PRD_IBIAS_CLK_SHIFT 24 -#define PRD_IBIAS_D2_SHIFT 16 -#define PRD_IBIAS_D1_SHIFT 8 -#define PRD_IBIAS_D0_SHIFT 0 #define HDMI_CON5 0x14 #define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24) #define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16) #define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8) #define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0) -#define DRV_IBIAS_CLK_SHIFT 24 -#define DRV_IBIAS_D2_SHIFT 16 -#define DRV_IBIAS_D1_SHIFT 8 -#define DRV_IBIAS_D0_SHIFT 0 #define HDMI_CON6 0x18 #define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24) #define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16) #define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8) #define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0) -#define DRV_IMP_CLK_SHIFT 24 -#define DRV_IMP_D2_SHIFT 16 -#define DRV_IMP_D1_SHIFT 8 -#define DRV_IMP_D0_SHIFT 0 #define HDMI_CON7 0x1c #define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27) #define RG_HDMITX_SER_DIN GENMASK(25, 16) @@ -178,21 +154,27 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, } mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV); + FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div), + RG_HDMITX_PLL_PREDIV); mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT), + FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) | + FIELD_PREP(RG_HDMITX_PLL_IR, 0x1), RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, - (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV); + FIELD_PREP(RG_HDMITX_PLL_TXDIV, div), + RG_HDMITX_PLL_TXDIV); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT), + FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) | + FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19), RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, - (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN); + FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2), + RG_HDMITX_PLL_DIVEN); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) | - (0x1 << PLL_BR_SHIFT), + FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) | + FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) | + FIELD_PREP(RG_HDMITX_PLL_BR, 0x1), RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | RG_HDMITX_PLL_BR); if (rate < 165000000) { @@ -209,29 +191,29 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, hdmi_ibias = hdmi_phy->ibias_up; } mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, - (pre_ibias << PRD_IBIAS_CLK_SHIFT) | - (pre_ibias << PRD_IBIAS_D2_SHIFT) | - (pre_ibias << PRD_IBIAS_D1_SHIFT) | - (pre_ibias << PRD_IBIAS_D0_SHIFT), + FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) | + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) | + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) | + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias), RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 | RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, - (imp_en << DRV_IMP_EN_SHIFT), + FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en), RG_HDMITX_DRV_IMP_EN); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, - (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | - (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | - (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) | - (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT), + FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) | + FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) | + FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) | + FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0), RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, - (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | - (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | - (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | - (hdmi_ibias << DRV_IBIAS_D0_SHIFT), + FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) | + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) | + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) | + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias), RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | RG_HDMITX_DRV_IBIAS_D1 | -- cgit v1.2.3 From 0fb5e57e67b299eed2859614f4229f40c6c19cfc Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:31 +0800 Subject: phy: mediatek: hdmi: mt8173: use common helper to access registers Use MediaTek phy's common helper to access registers, then we can remove hdmi's I/O helpers. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-12-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 140 ++++++++++++++--------------- 1 file changed, 65 insertions(+), 75 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c index 8f93991fb09d..d04758396046 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c @@ -5,6 +5,7 @@ */ #include "phy-mtk-hdmi.h" +#include "phy-mtk-io.h" #define HDMI_CON0 0x00 #define RG_HDMITX_PLL_EN BIT(31) @@ -86,16 +87,17 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); + void __iomem *base = hdmi_phy->regs; - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); + mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); + mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN); + mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); usleep_range(100, 150); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); usleep_range(100, 150); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); + mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); + mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); return 0; } @@ -103,15 +105,16 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); + void __iomem *base = hdmi_phy->regs; - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); usleep_range(100, 150); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); usleep_range(100, 150); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); usleep_range(100, 150); } @@ -133,6 +136,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); + void __iomem *base = hdmi_phy->regs; unsigned int pre_div; unsigned int div; unsigned int pre_ibias; @@ -153,71 +157,57 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, div = 1; } - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div), - RG_HDMITX_PLL_PREDIV); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) | - FIELD_PREP(RG_HDMITX_PLL_IR, 0x1), - RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, - FIELD_PREP(RG_HDMITX_PLL_TXDIV, div), - RG_HDMITX_PLL_TXDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) | - FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19), - RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, - FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2), - RG_HDMITX_PLL_DIVEN); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) | - FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) | - FIELD_PREP(RG_HDMITX_PLL_BR, 0x1), - RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | - RG_HDMITX_PLL_BR); + mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div); + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); + mtk_phy_update_bits(base + HDMI_CON0, + RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR, + FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) | + FIELD_PREP(RG_HDMITX_PLL_IR, 0x1)); + mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div); + mtk_phy_update_bits(base + HDMI_CON0, + RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV, + FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) | + FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19)); + mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2); + mtk_phy_update_bits(base + HDMI_CON0, + RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | + RG_HDMITX_PLL_BR, + FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) | + FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) | + FIELD_PREP(RG_HDMITX_PLL_BR, 0x1)); if (rate < 165000000) { - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, - RG_HDMITX_PRD_IMP_EN); + mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN); pre_ibias = 0x3; imp_en = 0x0; hdmi_ibias = hdmi_phy->ibias; } else { - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, - RG_HDMITX_PRD_IMP_EN); + mtk_phy_set_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN); pre_ibias = 0x6; imp_en = 0xf; hdmi_ibias = hdmi_phy->ibias_up; } - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, - FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) | - FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) | - FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) | - FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias), - RG_HDMITX_PRD_IBIAS_CLK | - RG_HDMITX_PRD_IBIAS_D2 | - RG_HDMITX_PRD_IBIAS_D1 | - RG_HDMITX_PRD_IBIAS_D0); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, - FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en), - RG_HDMITX_DRV_IMP_EN); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, - FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) | - FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) | - FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) | - FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0), - RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | - RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, - FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) | - FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) | - FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) | - FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias), - RG_HDMITX_DRV_IBIAS_CLK | - RG_HDMITX_DRV_IBIAS_D2 | - RG_HDMITX_DRV_IBIAS_D1 | - RG_HDMITX_DRV_IBIAS_D0); + mtk_phy_update_bits(base + HDMI_CON4, + RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 | + RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0, + FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) | + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) | + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) | + FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias)); + mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en); + mtk_phy_update_bits(base + HDMI_CON6, + RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | + RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0, + FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) | + FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) | + FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) | + FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0)); + mtk_phy_update_bits(base + HDMI_CON5, + RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | + RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0, + FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) | + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) | + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) | + FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias)); return 0; } @@ -239,17 +229,17 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = { static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) { - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, - RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | - RG_HDMITX_DRV_EN); + mtk_phy_set_bits(hdmi_phy->regs + HDMI_CON3, + RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | + RG_HDMITX_DRV_EN); usleep_range(100, 150); } static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) { - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, - RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | - RG_HDMITX_SER_EN); + mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CON3, + RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | + RG_HDMITX_SER_EN); } struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = { -- cgit v1.2.3 From 299a9c72ac7a4ac54cd0482c7d7829f482a88851 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:32 +0800 Subject: phy: mediatek: hdmi: remove register access helpers Remove private register access helpers, use the common ones instead. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-13-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-hdmi.c | 33 --------------------------------- drivers/phy/mediatek/phy-mtk-hdmi.h | 7 ------- 2 files changed, 40 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c index d4bd419abc3c..b16d437d6721 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c @@ -15,39 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = { .owner = THIS_MODULE, }; -void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits) -{ - void __iomem *reg = hdmi_phy->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp &= ~bits; - writel(tmp, reg); -} - -void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits) -{ - void __iomem *reg = hdmi_phy->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp |= bits; - writel(tmp, reg); -} - -void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 val, u32 mask) -{ - void __iomem *reg = hdmi_phy->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp = (tmp & ~mask) | (val & mask); - writel(tmp, reg); -} - inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw) { return container_of(hw, struct mtk_hdmi_phy, pll_hw); diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy-mtk-hdmi.h index dcf9bb13699b..c7fa65cff989 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.h +++ b/drivers/phy/mediatek/phy-mtk-hdmi.h @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -42,12 +41,6 @@ struct mtk_hdmi_phy { unsigned int ibias_up; }; -void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits); -void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits); -void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 val, u32 mask); struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw); extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf; -- cgit v1.2.3 From 7bd72714327d4783f82ccce12f611b415cbee0d5 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:33 +0800 Subject: phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask Use GENMASK() macro to generate bits mask Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-14-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 53 ++++++++++++++------------ 1 file changed, 29 insertions(+), 24 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c index 7a847954594f..5c257d67d7be 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c @@ -9,9 +9,9 @@ #define MIPITX_DSI_CON 0x00 #define RG_DSI_LDOCORE_EN BIT(0) #define RG_DSI_CKG_LDOOUT_EN BIT(1) -#define RG_DSI_BCLK_SEL (3 << 2) -#define RG_DSI_LD_IDX_SEL (7 << 4) -#define RG_DSI_PHYCLK_SEL (2 << 8) +#define RG_DSI_BCLK_SEL GENMASK(3, 2) +#define RG_DSI_LD_IDX_SEL GENMASK(6, 4) +#define RG_DSI_PHYCLK_SEL GENMASK(9, 8) #define RG_DSI_DSICLK_FREQ_SEL BIT(10) #define RG_DSI_LPTX_CLMP_EN BIT(11) @@ -27,41 +27,46 @@ #define RG_DSI_LNTx_LPTX_IMINUS BIT(4) #define RG_DSI_LNTx_LPCD_IPLUS BIT(5) #define RG_DSI_LNTx_LPCD_IMINUS BIT(6) -#define RG_DSI_LNTx_RT_CODE (0xf << 8) +#define RG_DSI_LNTx_RT_CODE GENMASK(11, 8) #define MIPITX_DSI_TOP_CON 0x40 #define RG_DSI_LNT_INTR_EN BIT(0) #define RG_DSI_LNT_HS_BIAS_EN BIT(1) #define RG_DSI_LNT_IMP_CAL_EN BIT(2) #define RG_DSI_LNT_TESTMODE_EN BIT(3) -#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4) -#define RG_DSI_LNT_AIO_SEL (7 << 8) +#define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4) +#define RG_DSI_LNT_AIO_SEL GENMASK(10, 8) #define RG_DSI_PAD_TIE_LOW_EN BIT(11) #define RG_DSI_DEBUG_INPUT_EN BIT(12) -#define RG_DSI_PRESERVE (7 << 13) +#define RG_DSI_PRESERVE GENMASK(15, 13) #define MIPITX_DSI_BG_CON 0x44 #define RG_DSI_BG_CORE_EN BIT(0) #define RG_DSI_BG_CKEN BIT(1) -#define RG_DSI_BG_DIV (0x3 << 2) +#define RG_DSI_BG_DIV GENMASK(3, 2) #define RG_DSI_BG_FAST_CHARGE BIT(4) -#define RG_DSI_VOUT_MSK (0x3ffff << 5) -#define RG_DSI_V12_SEL (7 << 5) -#define RG_DSI_V10_SEL (7 << 8) -#define RG_DSI_V072_SEL (7 << 11) -#define RG_DSI_V04_SEL (7 << 14) -#define RG_DSI_V032_SEL (7 << 17) -#define RG_DSI_V02_SEL (7 << 20) -#define RG_DSI_BG_R1_TRIM (0xf << 24) -#define RG_DSI_BG_R2_TRIM (0xf << 28) + +#define RG_DSI_V12_SEL GENMASK(7, 5) +#define RG_DSI_V10_SEL GENMASK(10, 8) +#define RG_DSI_V072_SEL GENMASK(13, 11) +#define RG_DSI_V04_SEL GENMASK(16, 14) +#define RG_DSI_V032_SEL GENMASK(19, 17) +#define RG_DSI_V02_SEL GENMASK(22, 20) +#define RG_DSI_VOUT_MSK \ + (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \ + RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL) +#define RG_DSI_BG_R1_TRIM GENMASK(27, 24) +#define RG_DSI_BG_R2_TRIM GENMASK(31, 28) #define MIPITX_DSI_PLL_CON0 0x50 #define RG_DSI_MPPLL_PLL_EN BIT(0) -#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1) -#define RG_DSI_MPPLL_PREDIV (3 << 1) -#define RG_DSI_MPPLL_TXDIV0 (3 << 3) -#define RG_DSI_MPPLL_TXDIV1 (3 << 5) -#define RG_DSI_MPPLL_POSDIV (7 << 7) +#define RG_DSI_MPPLL_PREDIV GENMASK(2, 1) +#define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3) +#define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5) +#define RG_DSI_MPPLL_POSDIV GENMASK(9, 7) +#define RG_DSI_MPPLL_DIV_MSK \ + (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \ + RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV) #define RG_DSI_MPPLL_MONVC_EN BIT(10) #define RG_DSI_MPPLL_MONREF_EN BIT(11) #define RG_DSI_MPPLL_VOD_EN BIT(12) @@ -70,12 +75,12 @@ #define RG_DSI_MPPLL_SDM_FRA_EN BIT(0) #define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1) #define RG_DSI_MPPLL_SDM_SSC_EN BIT(2) -#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16) +#define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16) #define MIPITX_DSI_PLL_CON2 0x58 #define MIPITX_DSI_PLL_TOP 0x64 -#define RG_DSI_MPPLL_PRESERVE (0xff << 8) +#define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8) #define MIPITX_DSI_PLL_PWR 0x68 #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0) -- cgit v1.2.3 From 993aa53ed076a987842be2943dba46b6099d8ec3 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:34 +0800 Subject: phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field Use FIELD_PREP() macro to prepare bits field value, then no need define macros of bits offset. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-15-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c index 5c257d67d7be..1e2ad617e8e3 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c @@ -153,15 +153,20 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, RG_DSI_VOUT_MSK | RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN, - (4 << 20) | (4 << 17) | (4 << 14) | - (4 << 11) | (4 << 8) | (4 << 5) | + FIELD_PREP(RG_DSI_V02_SEL, 4) | + FIELD_PREP(RG_DSI_V032_SEL, 4) | + FIELD_PREP(RG_DSI_V04_SEL, 4) | + FIELD_PREP(RG_DSI_V072_SEL, 4) | + FIELD_PREP(RG_DSI_V10_SEL, 4) | + FIELD_PREP(RG_DSI_V12_SEL, 4) | RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); usleep_range(30, 100); mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, - (8 << 4) | RG_DSI_LNT_HS_BIAS_EN); + FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) | + RG_DSI_LNT_HS_BIAS_EN); mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON, RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); @@ -177,7 +182,8 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_PREDIV, - (txdiv0 << 3) | (txdiv1 << 5)); + FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) | + FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1)); /* * PLL PCW config -- cgit v1.2.3 From bd4ba730ff28985c0ecb49da1c6f18488666aa4f Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:35 +0800 Subject: phy: mediatek: mipi: mt8173: use common helper to access registers Use MediaTek phy's common helper to access registers, then we can remove mipi-dsi's I/O helpers. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-16-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 117 ++++++++++++------------- 1 file changed, 55 insertions(+), 62 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c index 1e2ad617e8e3..673cb0f08959 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c @@ -4,6 +4,7 @@ * Author: jitao.shi */ +#include "phy-mtk-io.h" #include "phy-mtk-mipi-dsi.h" #define MIPITX_DSI_CON 0x00 @@ -121,6 +122,7 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) { struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); + void __iomem *base = mipi_tx->regs; u8 txdiv, txdiv0, txdiv1; u64 pcw; @@ -150,40 +152,38 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) return -EINVAL; } - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, - RG_DSI_VOUT_MSK | - RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN, - FIELD_PREP(RG_DSI_V02_SEL, 4) | - FIELD_PREP(RG_DSI_V032_SEL, 4) | - FIELD_PREP(RG_DSI_V04_SEL, 4) | - FIELD_PREP(RG_DSI_V072_SEL, 4) | - FIELD_PREP(RG_DSI_V10_SEL, 4) | - FIELD_PREP(RG_DSI_V12_SEL, 4) | - RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); + mtk_phy_update_bits(base + MIPITX_DSI_BG_CON, + RG_DSI_VOUT_MSK | RG_DSI_BG_CKEN | + RG_DSI_BG_CORE_EN, + FIELD_PREP(RG_DSI_V02_SEL, 4) | + FIELD_PREP(RG_DSI_V032_SEL, 4) | + FIELD_PREP(RG_DSI_V04_SEL, 4) | + FIELD_PREP(RG_DSI_V072_SEL, 4) | + FIELD_PREP(RG_DSI_V10_SEL, 4) | + FIELD_PREP(RG_DSI_V12_SEL, 4) | + RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); usleep_range(30, 100); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, - RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, - FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) | - RG_DSI_LNT_HS_BIAS_EN); + mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON, + RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, + FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) | + RG_DSI_LNT_HS_BIAS_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON, - RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); + mtk_phy_set_bits(base + MIPITX_DSI_CON, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, - RG_DSI_MPPLL_SDM_PWR_ON | - RG_DSI_MPPLL_SDM_ISO_EN, - RG_DSI_MPPLL_SDM_PWR_ON); + mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, + RG_DSI_MPPLL_SDM_PWR_ON | RG_DSI_MPPLL_SDM_ISO_EN, + RG_DSI_MPPLL_SDM_PWR_ON); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_PLL_EN); + mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | - RG_DSI_MPPLL_PREDIV, - FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) | - FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1)); + mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0, + RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | + RG_DSI_MPPLL_PREDIV, + FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) | + FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1)); /* * PLL PCW config @@ -193,23 +193,20 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) * Post DIV =4, so need data_Rate*4 * Ref_clk is 26MHz */ - pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, - 26000000); - writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2); + pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000); + writel(pcw, base + MIPITX_DSI_PLL_CON2); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1, - RG_DSI_MPPLL_SDM_FRA_EN); + mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); + mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); usleep_range(20, 100); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1, - RG_DSI_MPPLL_SDM_SSC_EN); + mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, - RG_DSI_MPPLL_PRESERVE, - mipi_tx->driver_data->mppll_preserve); + mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP, + RG_DSI_MPPLL_PRESERVE, + mipi_tx->driver_data->mppll_preserve); return 0; } @@ -217,31 +214,27 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw) { struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); + void __iomem *base = mipi_tx->regs; dev_dbg(mipi_tx->dev, "unprepare\n"); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_PLL_EN); + mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, - RG_DSI_MPPLL_PRESERVE, 0); + mtk_phy_clear_bits(base + MIPITX_DSI_PLL_TOP, RG_DSI_MPPLL_PRESERVE); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, - RG_DSI_MPPLL_SDM_ISO_EN | - RG_DSI_MPPLL_SDM_PWR_ON, - RG_DSI_MPPLL_SDM_ISO_EN); + mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, + RG_DSI_MPPLL_SDM_ISO_EN | RG_DSI_MPPLL_SDM_PWR_ON, + RG_DSI_MPPLL_SDM_ISO_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON, - RG_DSI_LNT_HS_BIAS_EN); + mtk_phy_clear_bits(base + MIPITX_DSI_TOP_CON, RG_DSI_LNT_HS_BIAS_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON, - RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); + mtk_phy_clear_bits(base + MIPITX_DSI_CON, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON, - RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); + mtk_phy_clear_bits(base + MIPITX_DSI_BG_CON, + RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, - RG_DSI_MPPLL_DIV_MSK); + mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK); } static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate, @@ -265,10 +258,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) for (reg = MIPITX_DSI_CLOCK_LANE; reg <= MIPITX_DSI_DATA_LANE3; reg += 4) - mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN); + mtk_phy_set_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON, - RG_DSI_PAD_TIE_LOW_EN); + mtk_phy_clear_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON, + RG_DSI_PAD_TIE_LOW_EN); } static void mtk_mipi_tx_power_off_signal(struct phy *phy) @@ -276,23 +269,23 @@ static void mtk_mipi_tx_power_off_signal(struct phy *phy) struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); u32 reg; - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON, - RG_DSI_PAD_TIE_LOW_EN); + mtk_phy_set_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON, + RG_DSI_PAD_TIE_LOW_EN); for (reg = MIPITX_DSI_CLOCK_LANE; reg <= MIPITX_DSI_DATA_LANE3; reg += 4) - mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN); + mtk_phy_clear_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN); } const struct mtk_mipitx_data mt2701_mipitx_data = { - .mppll_preserve = (3 << 8), + .mppll_preserve = 3, .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, }; const struct mtk_mipitx_data mt8173_mipitx_data = { - .mppll_preserve = (0 << 8), + .mppll_preserve = 0, .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, -- cgit v1.2.3 From d36d69a5517bb4e90a6ba07b043806bffffe19fb Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:36 +0800 Subject: phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask Use GENMASK() macro to generate bits mask Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-17-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c index 99108426d57c..1ec71ba2407e 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c @@ -18,7 +18,7 @@ #define RG_DSI_PAD_TIEL_SEL BIT(8) #define MIPITX_VOLTAGE_SEL 0x0010 -#define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6) +#define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6) #define MIPITX_PLL_PWR 0x0028 #define MIPITX_PLL_CON0 0x002c @@ -26,7 +26,7 @@ #define MIPITX_PLL_CON2 0x0034 #define MIPITX_PLL_CON3 0x0038 #define MIPITX_PLL_CON4 0x003c -#define RG_DSI_PLL_IBIAS (3 << 10) +#define RG_DSI_PLL_IBIAS GENMASK(11, 10) #define MIPITX_D2P_RTCODE 0x0100 #define MIPITX_D2_SW_CTL_EN 0x0144 @@ -41,7 +41,7 @@ #define AD_DSI_PLL_SDM_ISO_EN BIT(1) #define RG_DSI_PLL_EN BIT(4) -#define RG_DSI_PLL_POSDIV (0x7 << 8) +#define RG_DSI_PLL_POSDIV GENMASK(10, 8) static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) { -- cgit v1.2.3 From 5f88a93b5aa9bbc85831877c456a9114ba67ea4a Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:37 +0800 Subject: phy: mediatek: mipi: mt8183: use common helper to access registers Use MediaTek phy's common helper to access registers, then we can remove mipi-dsi's I/O helpers. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-18-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 68 +++++++++++++------------- 1 file changed, 34 insertions(+), 34 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c index 1ec71ba2407e..f021ec5a70e5 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c @@ -4,6 +4,7 @@ * Author: jitao.shi */ +#include "phy-mtk-io.h" #include "phy-mtk-mipi-dsi.h" #define MIPITX_LANE_CON 0x000c @@ -46,6 +47,7 @@ static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) { struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); + void __iomem *base = mipi_tx->regs; unsigned int txdiv, txdiv0; u64 pcw; @@ -70,17 +72,16 @@ static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) return -EINVAL; } - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS); + mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN); + mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); + mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); udelay(1); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); + mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000); - writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, - txdiv0 << 8); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN); + writel(pcw, base + MIPITX_PLL_CON0); + mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0); + mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); return 0; } @@ -88,11 +89,12 @@ static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) static void mtk_mipi_tx_pll_disable(struct clk_hw *hw) { struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); + void __iomem *base = mipi_tx->regs; - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN); + mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); + mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); + mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); } static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate, @@ -121,7 +123,7 @@ static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) mipi_tx->rt_code[i] |= 0x10 << 5; for (j = 0; j < 10; j++) - mtk_mipi_tx_update_bits(mipi_tx, + mtk_phy_update_bits(mipi_tx->regs + MIPITX_D2P_RTCODE * (i + 1) + j * 4, 1, mipi_tx->rt_code[i] >> j & 1); } @@ -130,44 +132,42 @@ static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) static void mtk_mipi_tx_power_on_signal(struct phy *phy) { struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); + void __iomem *base = mipi_tx->regs; /* BG_LPF_EN / BG_CORE_EN */ - writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, - mipi_tx->regs + MIPITX_LANE_CON); + writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON); usleep_range(30, 100); - writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, - mipi_tx->regs + MIPITX_LANE_CON); + writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON); /* Switch OFF each Lane */ - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL, - RG_DSI_HSTX_LDO_REF_SEL, - (mipi_tx->mipitx_drive - 3000) / 200 << 6); + mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL, + (mipi_tx->mipitx_drive - 3000) / 200); mtk_mipi_tx_config_calibration_data(mipi_tx); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); + mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); } static void mtk_mipi_tx_power_off_signal(struct phy *phy) { struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); + void __iomem *base = mipi_tx->regs; /* Switch ON each Lane */ - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); - mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); - - writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, - mipi_tx->regs + MIPITX_LANE_CON); - writel(RG_DSI_PAD_TIEL_SEL, mipi_tx->regs + MIPITX_LANE_CON); + mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + + writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON); + writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON); } const struct mtk_mipitx_data mt8183_mipitx_data = { -- cgit v1.2.3 From 60d9b6aaabe827e5ed025355e7d4622f6506b91e Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 20 Sep 2022 17:00:38 +0800 Subject: phy: mediatek: mipi: remove register access helpers Remove private register access helpers, use the common ones instead. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220920090038.15133-19-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 24 ------------------------ drivers/phy/mediatek/phy-mtk-mipi-dsi.h | 5 ----- 2 files changed, 29 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c index 28506932bd91..cf9c386385bb 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c @@ -10,30 +10,6 @@ inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw) return container_of(hw, struct mtk_mipi_tx, pll_hw); } -void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, - u32 bits) -{ - u32 temp = readl(mipi_tx->regs + offset); - - writel(temp & ~bits, mipi_tx->regs + offset); -} - -void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, - u32 bits) -{ - u32 temp = readl(mipi_tx->regs + offset); - - writel(temp | bits, mipi_tx->regs + offset); -} - -void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, - u32 mask, u32 data) -{ - u32 temp = readl(mipi_tx->regs + offset); - - writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset); -} - int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h index c76f07c3fdeb..47b60b1a7226 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -37,10 +36,6 @@ struct mtk_mipi_tx { }; struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw); -void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits); -void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits); -void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 mask, - u32 data); int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw, -- cgit v1.2.3 From a270cc137ba942af554c18db551b9487f04f43a4 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 22 Sep 2022 14:21:07 +0300 Subject: phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe() These two error paths need to call of_node_put(child_node) before returning. Fixes: edd473d4293a ("phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g") Fixes: 7ae14cf581f2 ("phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver") Signed-off-by: Dan Carpenter Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/YyxFI8aW23IC/21U@kili Signed-off-by: Vinod Koul --- drivers/phy/ti/phy-j721e-wiz.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 1f4f585a84ad..41725c6bcdf6 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -1413,7 +1413,8 @@ static int wiz_probe(struct platform_device *pdev) if (IS_ERR(wiz->scm_regmap)) { if (wiz->type == J7200_WIZ_10G) { dev_err(dev, "Couldn't get ti,scm regmap\n"); - return -ENODEV; + ret = -ENODEV; + goto err_addr_to_resource; } wiz->scm_regmap = NULL; @@ -1463,7 +1464,7 @@ static int wiz_probe(struct platform_device *pdev) ret = wiz_get_lane_phy_types(dev, wiz); if (ret) - return ret; + goto err_addr_to_resource; wiz->dev = dev; wiz->regmap = regmap; -- cgit v1.2.3 From a548b6b4e4d9de38ec9603608875aad914382cb8 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Thu, 22 Sep 2022 11:12:24 +0000 Subject: phy: qcom-qmp-pcie: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Andrew Halaney Link: https://lore.kernel.org/r/20220922111228.36355-4-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index dde398105f03..7aff3f9940a5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2344,12 +2344,9 @@ static int qmp_pcie_probe(struct platform_device *pdev) return ret; ret = qmp_pcie_vreg_init(dev, cfg); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get regulator supplies: %d\n", - ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ -- cgit v1.2.3 From 72f1f6085a731efb655ba6308e1ac54b787b416f Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Thu, 22 Sep 2022 11:12:27 +0000 Subject: phy: qcom-qusb2: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Andrew Halaney Link: https://lore.kernel.org/r/20220922111228.36355-7-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 7529a7e6e5df..2ef638b32e8f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -973,20 +973,14 @@ static int qusb2_phy_probe(struct platform_device *pdev) return PTR_ERR(qphy->base); qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); - if (IS_ERR(qphy->cfg_ahb_clk)) { - ret = PTR_ERR(qphy->cfg_ahb_clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get cfg ahb clk, %d\n", ret); - return ret; - } + if (IS_ERR(qphy->cfg_ahb_clk)) + return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk), + "failed to get cfg ahb clk\n"); qphy->ref_clk = devm_clk_get(dev, "ref"); - if (IS_ERR(qphy->ref_clk)) { - ret = PTR_ERR(qphy->ref_clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get ref clk, %d\n", ret); - return ret; - } + if (IS_ERR(qphy->ref_clk)) + return dev_err_probe(dev, PTR_ERR(qphy->ref_clk), + "failed to get ref clk\n"); qphy->iface_clk = devm_clk_get_optional(dev, "iface"); if (IS_ERR(qphy->iface_clk)) @@ -1003,12 +997,9 @@ static int qusb2_phy_probe(struct platform_device *pdev) qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; ret = devm_regulator_bulk_get(dev, num, qphy->vregs); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get regulator supplies: %d\n", - ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); /* Get the specific init parameters of QMP phy */ qphy->cfg = of_device_get_match_data(dev); -- cgit v1.2.3 From 668dc8afce43d4bc01feb3e929d6d5ffcb14f899 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Thu, 22 Sep 2022 11:12:28 +0000 Subject: phy: qcom-snps: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Reviewed-by: Dmitry Baryshkov Reviewed-by: Andrew Halaney Link: https://lore.kernel.org/r/20220922111228.36355-8-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 25022949108b..a59063596214 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -559,12 +559,9 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev) return PTR_ERR(hsphy->base); hsphy->ref_clk = devm_clk_get(dev, "ref"); - if (IS_ERR(hsphy->ref_clk)) { - ret = PTR_ERR(hsphy->ref_clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get ref clk, %d\n", ret); - return ret; - } + if (IS_ERR(hsphy->ref_clk)) + return dev_err_probe(dev, PTR_ERR(hsphy->ref_clk), + "failed to get ref clk\n"); hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(hsphy->phy_reset)) { @@ -577,12 +574,9 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev) hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i]; ret = devm_regulator_bulk_get(dev, num, hsphy->vregs); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get regulator supplies: %d\n", - ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); pm_runtime_set_active(dev); pm_runtime_enable(dev); -- cgit v1.2.3 From 6177f79644a0b4434d66fcfa93568979f3778173 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Thu, 22 Sep 2022 09:22:43 +0000 Subject: phy: tegra: xusb: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Link: https://lore.kernel.org/r/20220922092243.22281-1-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/tegra/xusb-tegra186.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index ae3915ed9fef..f1643fb7d351 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -1381,12 +1381,9 @@ tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl) return -ENOMEM; err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); - if (err) { - if (err != -EPROBE_DEFER) - dev_err(dev, "failed to read calibration fuse: %d\n", - err); - return err; - } + if (err) + return dev_err_probe(dev, err, + "failed to read calibration fuse\n"); dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value); -- cgit v1.2.3 From 7706630c56070f6205e8bad637472d802f883b1a Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Thu, 22 Sep 2022 11:15:51 +0000 Subject: phy: intel: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Link: https://lore.kernel.org/r/20220922111551.37188-1-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/intel/phy-intel-lgm-combo.c | 45 +++++++++++---------------------- 1 file changed, 15 insertions(+), 30 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/intel/phy-intel-lgm-combo.c b/drivers/phy/intel/phy-intel-lgm-combo.c index 157683d10367..6010e246d52e 100644 --- a/drivers/phy/intel/phy-intel-lgm-combo.c +++ b/drivers/phy/intel/phy-intel-lgm-combo.c @@ -413,44 +413,29 @@ static int intel_cbphy_fwnode_parse(struct intel_combo_phy *cbphy) u32 val; cbphy->core_clk = devm_clk_get(dev, NULL); - if (IS_ERR(cbphy->core_clk)) { - ret = PTR_ERR(cbphy->core_clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Get clk failed:%d!\n", ret); - return ret; - } + if (IS_ERR(cbphy->core_clk)) + return dev_err_probe(dev, PTR_ERR(cbphy->core_clk), + "Get clk failed!\n"); cbphy->core_rst = devm_reset_control_get_optional(dev, "core"); - if (IS_ERR(cbphy->core_rst)) { - ret = PTR_ERR(cbphy->core_rst); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Get core reset control err: %d!\n", ret); - return ret; - } + if (IS_ERR(cbphy->core_rst)) + return dev_err_probe(dev, PTR_ERR(cbphy->core_rst), + "Get core reset control err!\n"); cbphy->phy_rst = devm_reset_control_get_optional(dev, "phy"); - if (IS_ERR(cbphy->phy_rst)) { - ret = PTR_ERR(cbphy->phy_rst); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Get PHY reset control err: %d!\n", ret); - return ret; - } + if (IS_ERR(cbphy->phy_rst)) + return dev_err_probe(dev, PTR_ERR(cbphy->phy_rst), + "Get PHY reset control err!\n"); cbphy->iphy[0].app_rst = devm_reset_control_get_optional(dev, "iphy0"); - if (IS_ERR(cbphy->iphy[0].app_rst)) { - ret = PTR_ERR(cbphy->iphy[0].app_rst); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Get phy0 reset control err: %d!\n", ret); - return ret; - } + if (IS_ERR(cbphy->iphy[0].app_rst)) + return dev_err_probe(dev, PTR_ERR(cbphy->iphy[0].app_rst), + "Get phy0 reset control err!\n"); cbphy->iphy[1].app_rst = devm_reset_control_get_optional(dev, "iphy1"); - if (IS_ERR(cbphy->iphy[1].app_rst)) { - ret = PTR_ERR(cbphy->iphy[1].app_rst); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Get phy1 reset control err: %d!\n", ret); - return ret; - } + if (IS_ERR(cbphy->iphy[1].app_rst)) + return dev_err_probe(dev, PTR_ERR(cbphy->iphy[1].app_rst), + "Get phy1 reset control err!\n"); cbphy->app_base = devm_platform_ioremap_resource_byname(pdev, "app"); if (IS_ERR(cbphy->app_base)) -- cgit v1.2.3 From c3966ced8eb8dc53b6c8d7f97d32cc8a2107d83e Mon Sep 17 00:00:00 2001 From: Dongliang Mu Date: Wed, 14 Sep 2022 13:13:33 +0800 Subject: phy: qualcomm: call clk_disable_unprepare in the error handling Smatch reports the following error: drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on() warn: 'uphy->cal_clk' from clk_prepare_enable() not released on lines: 58. drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on() warn: 'uphy->cal_sleep_clk' from clk_prepare_enable() not released on lines: 58. drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on() warn: 'uphy->phy_clk' from clk_prepare_enable() not released on lines: 58. Fix this by calling proper clk_disable_unprepare calls. Fixes: 0b56e9a7e835 ("phy: Group vendor specific phy drivers") Signed-off-by: Dongliang Mu Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20220914051334.69282-1-dzm91@hust.edu.cn Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-usb-hsic.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c index 716a77748ed8..20f6dd37c7c1 100644 --- a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c +++ b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c @@ -54,8 +54,10 @@ static int qcom_usb_hsic_phy_power_on(struct phy *phy) /* Configure pins for HSIC functionality */ pins_default = pinctrl_lookup_state(uphy->pctl, PINCTRL_STATE_DEFAULT); - if (IS_ERR(pins_default)) - return PTR_ERR(pins_default); + if (IS_ERR(pins_default)) { + ret = PTR_ERR(pins_default); + goto err_ulpi; + } ret = pinctrl_select_state(uphy->pctl, pins_default); if (ret) -- cgit v1.2.3 From 4c0255e7957d5a536c6da7ba08cbb46540fb5d42 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Sat, 24 Sep 2022 07:02:57 +0000 Subject: phy: qcom-qmp-combo: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Reviewed-by: Dmitry Baryshkov Reviewed-by: Andrew Halaney Link: https://lore.kernel.org/r/20220924070300.25080-2-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index ad3b0aa22048..9807c4d935cd 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -2717,14 +2717,10 @@ static int qmp_combo_create(struct device *dev, struct device_node *np, int id, */ qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(qphy->pipe_clk)) { - if (cfg->type == PHY_TYPE_USB3) { - ret = PTR_ERR(qphy->pipe_clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, - "failed to get lane%d pipe_clk, %d\n", - id, ret); - return ret; - } + if (cfg->type == PHY_TYPE_USB3) + return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), + "failed to get lane%d pipe_clk\n", + id); qphy->pipe_clk = NULL; } @@ -2837,12 +2833,9 @@ static int qmp_combo_probe(struct platform_device *pdev) return ret; ret = qmp_combo_vreg_init(dev, cfg); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get regulator supplies: %d\n", - ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ -- cgit v1.2.3 From 413e048a2e51bcc96667c711785b40cf742fb366 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Sat, 24 Sep 2022 07:02:58 +0000 Subject: phy: qcom-qmp-pcie-msm8996: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Reviewed-by: Dmitry Baryshkov Reviewed-by: Andrew Halaney Link: https://lore.kernel.org/r/20220924070300.25080-3-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 0f8e739936ab..461f0b5d464a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -874,12 +874,9 @@ static int qmp_pcie_msm8996_probe(struct platform_device *pdev) return ret; ret = qmp_pcie_msm8996_vreg_init(dev, cfg); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get regulator supplies: %d\n", - ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ -- cgit v1.2.3 From 6d9b32fb3e432829e4f46427f334a8fc90233ef8 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Sat, 24 Sep 2022 07:02:59 +0000 Subject: phy: qcom-qmp-ufs: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Reviewed-by: Dmitry Baryshkov Reviewed-by: Andrew Halaney Link: https://lore.kernel.org/r/20220924070300.25080-4-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index d21b977850b3..c08d34ad1313 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1215,12 +1215,9 @@ static int qmp_ufs_probe(struct platform_device *pdev) return ret; ret = qmp_ufs_vreg_init(dev, cfg); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get regulator supplies: %d\n", - ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ -- cgit v1.2.3 From add7000bdd438c4195095dca7bff6877d54d06f4 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Sat, 24 Sep 2022 07:03:00 +0000 Subject: phy: qcom-qmp-usb: Use dev_err_probe() to simplify code In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can Reviewed-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Reviewed-by: Andrew Halaney Link: https://lore.kernel.org/r/20220924070300.25080-5-yuancan@huawei.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index f01b3022a10d..b84c0d4b5754 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2753,12 +2753,9 @@ static int qmp_usb_probe(struct platform_device *pdev) return ret; ret = qmp_usb_vreg_init(dev, cfg); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get regulator supplies: %d\n", - ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ -- cgit v1.2.3 From 84513eccd67804c02a0c42017bc7eaa4ad112478 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Wed, 28 Sep 2022 15:07:46 +0800 Subject: phy: mediatek: fix build warning of FIELD_PREP() Change the inline function mtk_phy_update_field() into a macro to avoid check warning of FIELD_PREP() with compiler parameter -Wtautological-constant-out-of-range-compare the warning is caused by mask check: "BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \" Fixes: 29c07477556e ("phy: mediatek: add a new helper to update bitfield") Reported-by: kernel test robot Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220928070746.5393-1-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-io.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-io.h b/drivers/phy/mediatek/phy-mtk-io.h index a723d4afc9b4..d20ad5e5be81 100644 --- a/drivers/phy/mediatek/phy-mtk-io.h +++ b/drivers/phy/mediatek/phy-mtk-io.h @@ -36,10 +36,11 @@ static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) writel(tmp, reg); } -/* field @mask should be constant and continuous */ -static inline void mtk_phy_update_field(void __iomem *reg, u32 mask, u32 val) -{ - mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); -} +/* field @mask shall be constant and continuous */ +#define mtk_phy_update_field(reg, mask, val) \ +({ \ + typeof(mask) mask_ = (mask); \ + mtk_phy_update_bits(reg, mask_, FIELD_PREP(mask_, val)); \ +}) #endif -- cgit v1.2.3 From 03b756d293484057b4248695345f4344b174af00 Mon Sep 17 00:00:00 2001 From: Wayne Chang Date: Wed, 28 Sep 2022 20:56:40 +0800 Subject: phy: tegra: xusb: Enable usb role switch attribute This patch enables the usb-role-switch attribute and lets users check the current device role of the otg capability ports Signed-off-by: Wayne Chang Signed-off-by: Haotien Hsu Link: https://lore.kernel.org/r/20220928125640.2219402-1-haotienh@nvidia.com Signed-off-by: Vinod Koul --- drivers/phy/tegra/xusb.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/phy') diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index d04a80c436c3..82fff4d9f4e6 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -656,6 +656,7 @@ static int tegra_xusb_setup_usb_role_switch(struct tegra_xusb_port *port) struct usb_role_switch_desc role_sx_desc = { .fwnode = dev_fwnode(&port->dev), .set = tegra_xusb_role_sw_set, + .allow_userspace_control = true, }; int err = 0; -- cgit v1.2.3 From 37d40a21473fdf1d0194089eb259b8ceeec2a4b9 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 27 Sep 2022 07:17:52 +0200 Subject: phy: rockchip-snps-pcie3: only look for rockchip,pipe-grf on rk3588 The rockchip,pipe-grf property is only used on rk3588, but not on rk3568. Therefore this property is not present on rk3568 devices, leading to the following message: rockchip-snps-pcie3-phy fe8c0000.phy: failed to find rockchip,pipe_grf regmap Fix that by only looking for this property on rk3588. Fixes: 2e9bffc4f713d ("phy: rockchip: Support PCIe v3") Signed-off-by: Aurelien Jarno Link: https://lore.kernel.org/r/20220927051752.53089-1-aurelien@aurel32.net Signed-off-by: Vinod Koul --- drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'drivers/phy') diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index a8d5914c5ac5..1d355b32ba55 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -255,10 +255,15 @@ static int rockchip_p3phy_probe(struct platform_device *pdev) return PTR_ERR(priv->phy_grf); } - priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, - "rockchip,pipe-grf"); - if (IS_ERR(priv->pipe_grf)) - dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); + if (of_device_is_compatible(np, "rockchip,rk3588-pcie3-phy")) { + priv->pipe_grf = + syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) + dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); + } else { + priv->pipe_grf = NULL; + } priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", priv->lanes, 2, -- cgit v1.2.3 From 0a40891b83f257b25a2b983758f72f6813f361cb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 26 Sep 2022 20:25:14 +0300 Subject: phy: qcom-qmp-pcie: fix resource mapping for SDM845 QHP PHY On SDM845 one of PCIe PHYs (the QHP one) has the same region for TX and RX registers. Since the commit 4be26f695ffa ("phy: qcom-qmp-pcie: fix memleak on probe deferral") added checking that resources are not allocated beforehand, this PHY can not be probed anymore. Fix this by skipping the map of ->rx resource on the QHP PHY and assign it manually. Fixes: 4be26f695ffa ("phy: qcom-qmp-pcie: fix memleak on probe deferral") Signed-off-by: Dmitry Baryshkov Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20220926172514.880776-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 7aff3f9940a5..5be5348fbb26 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2210,7 +2210,10 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, if (IS_ERR(qphy->tx)) return PTR_ERR(qphy->tx); - qphy->rx = devm_of_iomap(dev, np, 1, NULL); + if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) + qphy->rx = qphy->tx; + else + qphy->rx = devm_of_iomap(dev, np, 1, NULL); if (IS_ERR(qphy->rx)) return PTR_ERR(qphy->rx); -- cgit v1.2.3 From 9aa0dade8f6b4cdcbb114e1a06037939ee3238bc Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 29 Sep 2022 14:01:47 +0100 Subject: phy: phy-mtk-dp: make array driving_params static const Don't populate the read-only array driving_params on the stack but instead make it static const. Also makes the object code a little smaller. Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20220929130147.97375-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/mediatek/phy-mtk-dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/phy') diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c index 31266e7ca324..232fd3f1ff1b 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -85,7 +85,7 @@ struct mtk_dp_phy { static int mtk_dp_phy_init(struct phy *phy) { struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); - u32 driving_params[] = { + static const u32 driving_params[] = { DRIVING_PARAM_3_DEFAULT, DRIVING_PARAM_4_DEFAULT, DRIVING_PARAM_5_DEFAULT, -- cgit v1.2.3