From 645ec714545bca2a0ed13d7ac5b97d95e09da853 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 5 Jun 2014 15:26:00 +0200 Subject: pinctrl: sunxi: Remove irq_mask_ack and use irq_ack instead If irq_mask_ack is not defined, mask_ack_irq will call irq_mask and then irq_ack. In order to avoid code duplication, between irq_mask_ack and irq_mask, just declare irq_ack. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index f1ca75e6d7b1..657c4b21cda8 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -573,26 +573,14 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, return 0; } -static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) +static void sunxi_pinctrl_irq_ack(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq); - u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq); u32 status_reg = sunxi_irq_status_reg(d->hwirq); u8 status_idx = sunxi_irq_status_offset(d->hwirq); - unsigned long flags; - u32 val; - - spin_lock_irqsave(&pctl->lock, flags); - - /* Mask the IRQ */ - val = readl(pctl->membase + ctrl_reg); - writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg); /* Clear the IRQ */ writel(1 << status_idx, pctl->membase + status_reg); - - spin_unlock_irqrestore(&pctl->lock, flags); } static void sunxi_pinctrl_irq_mask(struct irq_data *d) @@ -638,8 +626,8 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d) } static struct irq_chip sunxi_pinctrl_irq_chip = { + .irq_ack = sunxi_pinctrl_irq_ack, .irq_mask = sunxi_pinctrl_irq_mask, - .irq_mask_ack = sunxi_pinctrl_irq_mask_ack, .irq_unmask = sunxi_pinctrl_irq_unmask, .irq_set_type = sunxi_pinctrl_irq_set_type, }; -- cgit v1.2.3 From 6e1c30239fe31aae6b415088c39ede7fa62b190c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 5 Jun 2014 15:26:01 +0200 Subject: pinctrl: sunxi: Add macro definition for pinctrl with more than one interrupt The A31 and A23, unlike the other Allwinner SoCs, have several interrupts banks and parent interrupts, while the other only have up to 32 interrupts in a single bank and a single parent interrupt. Start supporting it by introducing a function macro to declare irq functions and their banks. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 8169ba598876..cb87e15b1b3c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -77,6 +77,7 @@ struct sunxi_desc_function { const char *name; u8 muxval; + u8 irqbank; u8 irqnum; }; @@ -139,6 +140,14 @@ struct sunxi_pinctrl { .irqnum = _irq, \ } +#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ + { \ + .name = "irq", \ + .muxval = _val, \ + .irqbank = _bank, \ + .irqnum = _irq, \ + } + /* * The sunXi PIO registers are organized as is: * 0x00 - 0x0c Muxing values. -- cgit v1.2.3 From 8966ada2d40790214444c193be4902924e7ef02e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 5 Jun 2014 15:26:02 +0200 Subject: pinctrl: sunxi: Declare the number of interrupt banks in the descriptor Declare in the description structure associated to the compatible the number of interrupt banks the device has. For now, we're not doing anything with it. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 1 + drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 + 7 files changed, 7 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index fa1ff7c7e357..86b608bedca6 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -1010,6 +1010,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { .pins = sun4i_a10_pins, .npins = ARRAY_SIZE(sun4i_a10_pins), + .irq_banks = 1, }; static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c index 164d743f526c..2fa7430cabaf 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c @@ -661,6 +661,7 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = { .pins = sun5i_a10s_pins, .npins = ARRAY_SIZE(sun5i_a10s_pins), + .irq_banks = 1, }; static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c index 1188a2b7b988..29c734a60b51 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c @@ -382,6 +382,7 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { .pins = sun5i_a13_pins, .npins = ARRAY_SIZE(sun5i_a13_pins), + .irq_banks = 1, }; static int sun5i_a13_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c index 8fcba48e0a42..9a2517b65113 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -93,6 +93,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = { .pins = sun6i_a31_r_pins, .npins = ARRAY_SIZE(sun6i_a31_r_pins), .pin_base = PL_BASE, + .irq_banks = 2, }; static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 8dea5856458b..7adc4888eb27 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -836,6 +836,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { .pins = sun6i_a31_pins, .npins = ARRAY_SIZE(sun6i_a31_pins), + .irq_banks = 4, }; static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c index d8577ce5f1a4..dac99e02bfdb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c @@ -1036,6 +1036,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = { .pins = sun7i_a20_pins, .npins = ARRAY_SIZE(sun7i_a20_pins), + .irq_banks = 1, }; static int sun7i_a20_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index cb87e15b1b3c..7ddcce0f3c27 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -90,6 +90,7 @@ struct sunxi_pinctrl_desc { const struct sunxi_desc_pin *pins; int npins; unsigned pin_base; + unsigned irq_banks; }; struct sunxi_pinctrl_function { -- cgit v1.2.3 From c11a33c15ebc7c516551fef624efd9927da8cd81 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 5 Jun 2014 15:26:03 +0200 Subject: pinctrl: sunxi: Declare the interrupt function for the A31 The primary pinctrl device has 4 interrupt banks. As usual, to be able to generate interrupts, the pins supporting it need to be muxed to a special function. Declare these functions in the pins array. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 216 ++++++++++++++++++++---------- 1 file changed, 144 insertions(+), 72 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 7adc4888eb27..a2b4b85c5ad5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -24,208 +24,244 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */ - SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */ - SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */ - SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart1")), /* RING */ + SUNXI_FUNCTION(0x4, "uart1"), /* RING */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ - SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D8 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */ SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ - SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */ + SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */ SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ - SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */ + SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */ SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ - SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */ + SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */ SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ - SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */ + SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */ SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ - SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */ + SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */ SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ - SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */ + SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ - SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ - SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ - SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ - SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */ - SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */ + SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */ - SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */ + SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */ - SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */ + SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */ - SUNXI_FUNCTION(0x4, "spi3")), /* CLK */ + SUNXI_FUNCTION(0x4, "spi3"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* COL */ SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */ - SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */ + SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */ - SUNXI_FUNCTION(0x4, "spi3")), /* MISO */ + SUNXI_FUNCTION(0x4, "spi3"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ SUNXI_FUNCTION(0x3, "lcd1"), /* DE */ - SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */ + SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ - SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ - SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lcd1"), /* VSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */ + SUNXI_FUNCTION(0x4, "csi"), /* MCLK1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */ + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */ + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */ + SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ - SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ SUNXI_FUNCTION(0x3, "uart3"), /* TX */ - SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */ + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ SUNXI_FUNCTION(0x3, "uart3"), /* RX */ - SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */ + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "i2s0")), /* DI */ + SUNXI_FUNCTION(0x3, "i2s0"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -510,86 +546,103 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ - SUNXI_FUNCTION(0x3, "ts")), /* CLK */ + SUNXI_FUNCTION(0x3, "ts"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ - SUNXI_FUNCTION(0x3, "ts")), /* ERR */ + SUNXI_FUNCTION(0x3, "ts"), /* ERR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ + SUNXI_FUNCTION(0x3, "ts"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ + SUNXI_FUNCTION(0x3, "ts"), /* DVLD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D0 */ - SUNXI_FUNCTION(0x3, "uart5")), /* TX */ + SUNXI_FUNCTION(0x3, "uart5"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D1 */ - SUNXI_FUNCTION(0x3, "uart5")), /* RX */ + SUNXI_FUNCTION(0x3, "uart5"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D2 */ - SUNXI_FUNCTION(0x3, "uart5")), /* RTS */ + SUNXI_FUNCTION(0x3, "uart5"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D3 */ - SUNXI_FUNCTION(0x3, "uart5")), /* CTS */ + SUNXI_FUNCTION(0x3, "uart5"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D4 */ - SUNXI_FUNCTION(0x3, "ts")), /* D0 */ + SUNXI_FUNCTION(0x3, "ts"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D5 */ - SUNXI_FUNCTION(0x3, "ts")), /* D1 */ + SUNXI_FUNCTION(0x3, "ts"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D6 */ - SUNXI_FUNCTION(0x3, "ts")), /* D2 */ + SUNXI_FUNCTION(0x3, "ts"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D7 */ - SUNXI_FUNCTION(0x3, "ts")), /* D3 */ + SUNXI_FUNCTION(0x3, "ts"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D8 */ - SUNXI_FUNCTION(0x3, "ts")), /* D4 */ + SUNXI_FUNCTION(0x3, "ts"), /* D4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D9 */ - SUNXI_FUNCTION(0x3, "ts")), /* D5 */ + SUNXI_FUNCTION(0x3, "ts"), /* D5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D10 */ - SUNXI_FUNCTION(0x3, "ts")), /* D6 */ + SUNXI_FUNCTION(0x3, "ts"), /* D6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi"), /* D11 */ - SUNXI_FUNCTION(0x3, "ts")), /* D7 */ + SUNXI_FUNCTION(0x3, "ts"), /* D7 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */ + SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -625,86 +678,105 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */ + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */ + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */ + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */ + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */ + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */ + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart2")), /* TX */ + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart2")), /* RX */ + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart2")), /* RTS */ + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart2")), /* CTS */ + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ - SUNXI_FUNCTION(0x3, "usb")), /* DP3 */ + SUNXI_FUNCTION(0x3, "usb"), /* DP3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ - SUNXI_FUNCTION(0x3, "usb")), /* DM3 */ + SUNXI_FUNCTION(0x3, "usb"), /* DM3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ - SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */ + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */ + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */ + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */ + SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */ + SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart4")), /* TX */ + SUNXI_FUNCTION(0x2, "uart4"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart4")), /* RX */ + SUNXI_FUNCTION(0x2, "uart4"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), SUNXI_FUNCTION(0x0, "gpio_in"), -- cgit v1.2.3 From aebdc8abc9db86e2bd33070fc2f961012fff74b4 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 5 Jun 2014 15:26:04 +0200 Subject: pinctrl: sunxi: Implement multiple interrupt banks support The A23 and A31 support multiple interrupt banks. Support it by adding a linear domain covering all the banks. It's trickier than it should because there's an interrupt per bank, so we have multiple interrupts using the same domain. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 65 +++++++++++++++++++++++++++-------- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 34 +++++++++++++----- 2 files changed, 76 insertions(+), 23 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 657c4b21cda8..d989a10f7b10 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -636,17 +636,28 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) { struct irq_chip *chip = irq_get_chip(irq); struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); - const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); + unsigned long bank, reg, val; + + for (bank = 0; bank < pctl->desc->irq_banks; bank++) + if (irq == pctl->irq[bank]) + break; + + if (bank == pctl->desc->irq_banks) + return; + + reg = sunxi_irq_status_reg_from_bank(bank); + val = readl(pctl->membase + reg); /* Clear all interrupts */ - writel(reg, pctl->membase + IRQ_STATUS_REG); + writel(val, pctl->membase + reg); - if (reg) { + if (val) { int irqoffset; chained_irq_enter(chip, desc); - for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) { - int pin_irq = irq_find_mapping(pctl->domain, irqoffset); + for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { + int pin_irq = irq_find_mapping(pctl->domain, + bank * IRQ_PER_BANK + irqoffset); generic_handle_irq(pin_irq); } chained_irq_exit(chip, desc); @@ -714,8 +725,11 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev) while (func->name) { /* Create interrupt mapping while we're at it */ - if (!strcmp(func->name, "irq")) - pctl->irq_array[func->irqnum] = pin->pin.number; + if (!strcmp(func->name, "irq")) { + int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; + pctl->irq_array[irqnum] = pin->pin.number; + } + sunxi_pinctrl_add_function(pctl, func->name); func++; } @@ -785,6 +799,13 @@ int sunxi_pinctrl_init(struct platform_device *pdev, pctl->dev = &pdev->dev; pctl->desc = desc; + pctl->irq_array = devm_kcalloc(&pdev->dev, + IRQ_PER_BANK * pctl->desc->irq_banks, + sizeof(*pctl->irq_array), + GFP_KERNEL); + if (!pctl->irq_array) + return -ENOMEM; + ret = sunxi_pinctrl_build_state(pdev); if (ret) { dev_err(&pdev->dev, "dt probe failed: %d\n", ret); @@ -869,21 +890,34 @@ int sunxi_pinctrl_init(struct platform_device *pdev, if (ret) goto gpiochip_error; - pctl->irq = irq_of_parse_and_map(node, 0); + pctl->irq = devm_kcalloc(&pdev->dev, + pctl->desc->irq_banks, + sizeof(*pctl->irq), + GFP_KERNEL); if (!pctl->irq) { - ret = -EINVAL; + ret = -ENOMEM; goto clk_error; } - pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, - &irq_domain_simple_ops, NULL); + for (i = 0; i < pctl->desc->irq_banks; i++) { + pctl->irq[i] = platform_get_irq(pdev, i); + if (pctl->irq[i] < 0) { + ret = pctl->irq[i]; + goto clk_error; + } + } + + pctl->domain = irq_domain_add_linear(node, + pctl->desc->irq_banks * IRQ_PER_BANK, + &irq_domain_simple_ops, + NULL); if (!pctl->domain) { dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); ret = -ENOMEM; goto clk_error; } - for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { + for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { int irqno = irq_create_mapping(pctl->domain, i); irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, @@ -891,8 +925,11 @@ int sunxi_pinctrl_init(struct platform_device *pdev, irq_set_chip_data(irqno, pctl); }; - irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); - irq_set_handler_data(pctl->irq, pctl); + for (i = 0; i < pctl->desc->irq_banks; i++) { + irq_set_chained_handler(pctl->irq[i], + sunxi_pinctrl_irq_handler); + irq_set_handler_data(pctl->irq[i], pctl); + } dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 7ddcce0f3c27..4245b96c7996 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -53,7 +53,7 @@ #define PULL_PINS_BITS 2 #define PULL_PINS_MASK 0x03 -#define SUNXI_IRQ_NUMBER 32 +#define IRQ_PER_BANK 32 #define IRQ_CFG_REG 0x200 #define IRQ_CFG_IRQ_PER_REG 8 @@ -68,6 +68,8 @@ #define IRQ_STATUS_IRQ_BITS 1 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) +#define IRQ_MEM_SIZE 0x20 + #define IRQ_EDGE_RISING 0x00 #define IRQ_EDGE_FALLING 0x01 #define IRQ_LEVEL_HIGH 0x02 @@ -115,8 +117,8 @@ struct sunxi_pinctrl { unsigned nfunctions; struct sunxi_pinctrl_group *groups; unsigned ngroups; - int irq; - int irq_array[SUNXI_IRQ_NUMBER]; + int *irq; + unsigned *irq_array; spinlock_t lock; struct pinctrl_dev *pctl_dev; }; @@ -228,8 +230,10 @@ static inline u32 sunxi_pull_offset(u16 pin) static inline u32 sunxi_irq_cfg_reg(u16 irq) { - u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04; - return reg + IRQ_CFG_REG; + u8 bank = irq / IRQ_PER_BANK; + u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; + + return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg; } static inline u32 sunxi_irq_cfg_offset(u16 irq) @@ -238,10 +242,16 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq) return irq_num * IRQ_CFG_IRQ_BITS; } +static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank) +{ + return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE; +} + static inline u32 sunxi_irq_ctrl_reg(u16 irq) { - u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04; - return reg + IRQ_CTRL_REG; + u8 bank = irq / IRQ_PER_BANK; + + return sunxi_irq_ctrl_reg_from_bank(bank); } static inline u32 sunxi_irq_ctrl_offset(u16 irq) @@ -250,10 +260,16 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq) return irq_num * IRQ_CTRL_IRQ_BITS; } +static inline u32 sunxi_irq_status_reg_from_bank(u8 bank) +{ + return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE; +} + static inline u32 sunxi_irq_status_reg(u16 irq) { - u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04; - return reg + IRQ_STATUS_REG; + u8 bank = irq / IRQ_PER_BANK; + + return sunxi_irq_status_reg_from_bank(bank); } static inline u32 sunxi_irq_status_offset(u16 irq) -- cgit v1.2.3 From 22763bf527446fe1f25ac365d846b02fd040e19c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 29 May 2014 11:18:48 +0200 Subject: pinctrl: spear: switch plgpio to irqchip helpers This switches the SPEAr PLGPIO driver over to using the irqchip helpers. As part of this effort, also get rid of the strange irq_base calculation and failure to use d->hwirq for obtaining a local irqchip offset. Cc: Viresh Kumar Cc: Shiraz Hashim Cc: spear-devel@list.st.com Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/Kconfig | 1 + drivers/pinctrl/spear/pinctrl-plgpio.c | 81 +++++++++++++--------------------- 2 files changed, 31 insertions(+), 51 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig index 04d93e602674..9ef18eb958e1 100644 --- a/drivers/pinctrl/spear/Kconfig +++ b/drivers/pinctrl/spear/Kconfig @@ -48,6 +48,7 @@ config PINCTRL_SPEAR1340 config PINCTRL_SPEAR_PLGPIO bool "SPEAr SoC PLGPIO Controller" depends on GPIOLIB && PINCTRL_SPEAR + select GPIOLIB_IRQCHIP help Say yes here to support PLGPIO controller on ST Microelectronics SPEAr SoCs. diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index ff2940e9f2a7..3a20cdc65810 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -11,12 +11,11 @@ #include #include -#include +#include #include -#include -#include -#include #include +#include +#include #include #include #include @@ -54,7 +53,6 @@ struct plgpio_regs { * * lock: lock for guarding gpio registers * base: base address of plgpio block - * irq_base: irq number of plgpio0 * chip: gpio framework specific chip information structure * p2o: function ptr for pin to offset conversion. This is required only for * machines where mapping b/w pin and offset is not 1-to-1. @@ -68,8 +66,6 @@ struct plgpio { spinlock_t lock; void __iomem *base; struct clk *clk; - unsigned irq_base; - struct irq_domain *irq_domain; struct gpio_chip chip; int (*p2o)(int pin); /* pin_to_offset */ int (*o2p)(int offset); /* offset_to_pin */ @@ -280,21 +276,12 @@ disable_clk: pinctrl_free_gpio(gpio); } -static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct plgpio *plgpio = container_of(chip, struct plgpio, chip); - - if (IS_ERR_VALUE(plgpio->irq_base)) - return -EINVAL; - - return irq_find_mapping(plgpio->irq_domain, offset); -} - /* PLGPIO IRQ */ static void plgpio_irq_disable(struct irq_data *d) { - struct plgpio *plgpio = irq_data_get_irq_chip_data(d); - int offset = d->irq - plgpio->irq_base; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct plgpio *plgpio = container_of(gc, struct plgpio, chip); + int offset = d->hwirq; unsigned long flags; /* get correct offset for "offset" pin */ @@ -311,8 +298,9 @@ static void plgpio_irq_disable(struct irq_data *d) static void plgpio_irq_enable(struct irq_data *d) { - struct plgpio *plgpio = irq_data_get_irq_chip_data(d); - int offset = d->irq - plgpio->irq_base; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct plgpio *plgpio = container_of(gc, struct plgpio, chip); + int offset = d->hwirq; unsigned long flags; /* get correct offset for "offset" pin */ @@ -329,8 +317,9 @@ static void plgpio_irq_enable(struct irq_data *d) static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) { - struct plgpio *plgpio = irq_data_get_irq_chip_data(d); - int offset = d->irq - plgpio->irq_base; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct plgpio *plgpio = container_of(gc, struct plgpio, chip); + int offset = d->hwirq; void __iomem *reg_off; unsigned int supported_type = 0, val; @@ -369,7 +358,8 @@ static struct irq_chip plgpio_irqchip = { static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct plgpio *plgpio = irq_get_handler_data(irq); + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct plgpio *plgpio = container_of(gc, struct plgpio, chip); struct irq_chip *irqchip = irq_desc_get_chip(desc); int regs_count, count, pin, offset, i = 0; unsigned long pending; @@ -410,7 +400,8 @@ static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc) /* get correct irq line number */ pin = i * MAX_GPIO_PER_REG + pin; - generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin)); + generic_handle_irq( + irq_find_mapping(gc->irqdomain, pin)); } } chained_irq_exit(irqchip, desc); @@ -523,10 +514,9 @@ end: } static int plgpio_probe(struct platform_device *pdev) { - struct device_node *np = pdev->dev.of_node; struct plgpio *plgpio; struct resource *res; - int ret, irq, i; + int ret, irq; plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); if (!plgpio) { @@ -563,7 +553,6 @@ static int plgpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, plgpio); spin_lock_init(&plgpio->lock); - plgpio->irq_base = -1; plgpio->chip.base = -1; plgpio->chip.request = plgpio_request; plgpio->chip.free = plgpio_free; @@ -571,10 +560,10 @@ static int plgpio_probe(struct platform_device *pdev) plgpio->chip.direction_output = plgpio_direction_output; plgpio->chip.get = plgpio_get_value; plgpio->chip.set = plgpio_set_value; - plgpio->chip.to_irq = plgpio_to_irq; plgpio->chip.label = dev_name(&pdev->dev); plgpio->chip.dev = &pdev->dev; plgpio->chip.owner = THIS_MODULE; + plgpio->chip.of_node = pdev->dev.of_node; if (!IS_ERR(plgpio->clk)) { ret = clk_prepare(plgpio->clk); @@ -592,35 +581,25 @@ static int plgpio_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) { - dev_info(&pdev->dev, "irqs not supported\n"); - return 0; - } - - plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0); - if (IS_ERR_VALUE(plgpio->irq_base)) { - /* we would not support irq for gpio */ - dev_warn(&pdev->dev, "couldn't allocate irq base\n"); + dev_info(&pdev->dev, "PLGPIO registered without IRQs\n"); return 0; } - plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio, - plgpio->irq_base, 0, &irq_domain_simple_ops, NULL); - if (WARN_ON(!plgpio->irq_domain)) { - dev_err(&pdev->dev, "irq domain init failed\n"); - irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio); - ret = -ENXIO; + ret = gpiochip_irqchip_add(&plgpio->chip, + &plgpio_irqchip, + 0, + handle_simple_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(&pdev->dev, "failed to add irqchip to gpiochip\n"); goto remove_gpiochip; } - irq_set_chained_handler(irq, plgpio_irq_handler); - for (i = 0; i < plgpio->chip.ngpio; i++) { - irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip, - handle_simple_irq); - set_irq_flags(i + plgpio->irq_base, IRQF_VALID); - irq_set_chip_data(i + plgpio->irq_base, plgpio); - } + gpiochip_set_chained_irqchip(&plgpio->chip, + &plgpio_irqchip, + irq, + plgpio_irq_handler); - irq_set_handler_data(irq, plgpio); dev_info(&pdev->dev, "PLGPIO registered with IRQs\n"); return 0; -- cgit v1.2.3 From 244e95a7ad6a34278aa9c21677785093188d3fc8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 3 Jun 2014 10:02:36 +0200 Subject: pinctrl: hide CONFIG_PINMUX and CONFIG_PINCONF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These symbols are supposed to be selected by the drivers actually needing them. The only situation where it would make sense to enable them without a driver selecting them is when an out-of-tree pinctrl driver is used or for compile testing. Signed-off-by: Uwe Kleine-König Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0042ccb46b9a..4af9e3519388 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -11,10 +11,10 @@ menu "Pin controllers" depends on PINCTRL config PINMUX - bool "Support pin multiplexing controllers" + bool "Support pin multiplexing controllers" if COMPILE_TEST config PINCONF - bool "Support pin configuration controllers" + bool "Support pin configuration controllers" if COMPILE_TEST config GENERIC_PINCONF bool -- cgit v1.2.3 From 7d98fd3218b282d879101a92eb04f8db9505590b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 10 Jun 2014 11:37:15 +0900 Subject: pinctrl: sh-pfc: r8a7791: Add HSCIF pin support Signed-off-by: Nobuhiro Iwamatsu Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 250 +++++++++++++++++++++++++++++++++++ 1 file changed, 250 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 2e688dc4a3c8..394b234488cc 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1867,6 +1867,192 @@ static const unsigned int eth_rmii_mux[] = { ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, }; + +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 2), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; +static const unsigned int hscif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), +}; +static const unsigned int hscif0_data_b_mux[] = { + HRX0_B_MARK, HTX0_B_MARK, +}; +static const unsigned int hscif0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), +}; +static const unsigned int hscif0_ctrl_b_mux[] = { + HRTS0_N_B_MARK, HCTS0_N_B_MARK, +}; +static const unsigned int hscif0_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int hscif0_data_c_mux[] = { + HRX0_C_MARK, HTX0_C_MARK, +}; +static const unsigned int hscif0_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 31), +}; +static const unsigned int hscif0_clk_c_mux[] = { + HSCK0_C_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), +}; +static const unsigned int hscif1_data_mux[] = { + HRX1_MARK, HTX1_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 7), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCK1_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HRTS1_N_MARK, HCTS1_N_MARK, +}; +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), +}; +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; +static const unsigned int hscif1_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), +}; +static const unsigned int hscif1_data_c_mux[] = { + HRX1_C_MARK, HTX1_C_MARK, +}; +static const unsigned int hscif1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 16), +}; +static const unsigned int hscif1_clk_c_mux[] = { + HSCK1_C_MARK, +}; +static const unsigned int hscif1_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), +}; +static const unsigned int hscif1_ctrl_c_mux[] = { + HRTS1_N_C_MARK, HCTS1_N_C_MARK, +}; +static const unsigned int hscif1_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), +}; +static const unsigned int hscif1_data_d_mux[] = { + HRX1_D_MARK, HTX1_D_MARK, +}; +static const unsigned int hscif1_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), +}; +static const unsigned int hscif1_data_e_mux[] = { + HRX1_C_MARK, HTX1_C_MARK, +}; +static const unsigned int hscif1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int hscif1_clk_e_mux[] = { + HSCK1_E_MARK, +}; +static const unsigned int hscif1_ctrl_e_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), +}; +static const unsigned int hscif1_ctrl_e_mux[] = { + HRTS1_N_E_MARK, HCTS1_N_E_MARK, +}; +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), +}; +static const unsigned int hscif2_data_mux[] = { + HRX2_MARK, HTX2_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCK2_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HRTS2_N_MARK, HCTS2_N_MARK, +}; +static const unsigned int hscif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22), +}; +static const unsigned int hscif2_data_b_mux[] = { + HRX2_B_MARK, HTX2_B_MARK, +}; +static const unsigned int hscif2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21), +}; +static const unsigned int hscif2_ctrl_b_mux[] = { + HRTS2_N_B_MARK, HCTS2_N_B_MARK, +}; +static const unsigned int hscif2_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int hscif2_data_c_mux[] = { + HRX2_C_MARK, HTX2_C_MARK, +}; +static const unsigned int hscif2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 31), +}; +static const unsigned int hscif2_clk_c_mux[] = { + HSCK2_C_MARK, +}; +static const unsigned int hscif2_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31), +}; +static const unsigned int hscif2_data_d_mux[] = { + HRX2_B_MARK, HTX2_D_MARK, +}; /* - I2C0 ------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { /* SCL, SDA */ @@ -3885,6 +4071,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_clk_c), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_data_c), + SH_PFC_PIN_GROUP(hscif1_clk_c), + SH_PFC_PIN_GROUP(hscif1_ctrl_c), + SH_PFC_PIN_GROUP(hscif1_data_d), + SH_PFC_PIN_GROUP(hscif1_data_e), + SH_PFC_PIN_GROUP(hscif1_clk_e), + SH_PFC_PIN_GROUP(hscif1_ctrl_e), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_data_d), SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c0_b), SH_PFC_PIN_GROUP(i2c0_c), @@ -4183,6 +4395,41 @@ static const char * const eth_groups[] = { "eth_rmii", }; +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", + "hscif0_data_b", + "hscif0_ctrl_b", + "hscif0_data_c", + "hscif0_clk_c", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", + "hscif1_data_b", + "hscif1_data_c", + "hscif1_clk_c", + "hscif1_ctrl_c", + "hscif1_data_d", + "hscif1_data_e", + "hscif1_clk_e", + "hscif1_ctrl_e", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", + "hscif2_data_b", + "hscif2_ctrl_b", + "hscif2_data_c", + "hscif2_clk_c", + "hscif2_data_d", +}; + static const char * const i2c0_groups[] = { "i2c0", "i2c0_b", @@ -4547,6 +4794,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), -- cgit v1.2.3 From 578c0a8721278770b851ecd23c5873ceda598ae8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 29 Jun 2014 16:10:59 +0200 Subject: pinctrl: sunxi: Add IRQCHIP_SKIP_SET_WAKE flag for pinctrl irq chip The sunxi pinctrl irq chip driver does not support wakeup at the moment. Adding IRQCHIP_SKIP_SET_WAKE lets the irqs work with drivers using wakeup. Signed-off-by: Chen-Yu Tsai Signed-off-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index d989a10f7b10..c19933737fa5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -630,6 +630,7 @@ static struct irq_chip sunxi_pinctrl_irq_chip = { .irq_mask = sunxi_pinctrl_irq_mask, .irq_unmask = sunxi_pinctrl_irq_unmask, .irq_set_type = sunxi_pinctrl_irq_set_type, + .flags = IRQCHIP_SKIP_SET_WAKE, }; static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) -- cgit v1.2.3 From fea6d8efd023a2438c848c049480ea67ea0bca16 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 29 Jun 2014 16:11:00 +0200 Subject: pinctrl: sunxi: Move setting of mux to irq type With level triggered interrupt mask / unmask will get called for each interrupt, doing the somewhat expensive mux setting on each unmask thus is not a good idea. Instead add a request_resources callback and do it there. Signed-off-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index c19933737fa5..8bdd65b924ca 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -531,6 +531,21 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) return irq_find_mapping(pctl->domain, desc->irqnum); } +static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + struct sunxi_desc_function *func; + + func = sunxi_pinctrl_desc_find_function_by_pin(pctl, + pctl->irq_array[d->hwirq], "irq"); + if (!func) + return -EINVAL; + + /* Change muxing to INT mode */ + sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); + + return 0; +} static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) @@ -603,19 +618,11 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d) static void sunxi_pinctrl_irq_unmask(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - struct sunxi_desc_function *func; u32 reg = sunxi_irq_ctrl_reg(d->hwirq); u8 idx = sunxi_irq_ctrl_offset(d->hwirq); unsigned long flags; u32 val; - func = sunxi_pinctrl_desc_find_function_by_pin(pctl, - pctl->irq_array[d->hwirq], - "irq"); - - /* Change muxing to INT mode */ - sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); - spin_lock_irqsave(&pctl->lock, flags); /* Unmask the IRQ */ @@ -629,6 +636,7 @@ static struct irq_chip sunxi_pinctrl_irq_chip = { .irq_ack = sunxi_pinctrl_irq_ack, .irq_mask = sunxi_pinctrl_irq_mask, .irq_unmask = sunxi_pinctrl_irq_unmask, + .irq_request_resources = sunxi_pinctrl_irq_request_resources, .irq_set_type = sunxi_pinctrl_irq_set_type, .flags = IRQCHIP_SKIP_SET_WAKE, }; -- cgit v1.2.3 From f4c51c103b6a7373186dd6dc80759bc707bffdb4 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 29 Jun 2014 16:11:01 +0200 Subject: pinctrl: sunxi: Properly handle level triggered gpio interrupts For level triggered gpio interrupts we need to use handle_fasteoi_irq, like we do with the irq-sunxi-nmi driver. This is necessary to give threaded interrupt handlers a chance to actuall clear the source of the interrupt (which may involve sleeping waiting for i2c / spi / mmc transfers), before acknowledging the interrupt. Signed-off-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 39 ++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 8bdd65b924ca..c1f053014dd6 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -31,6 +31,9 @@ #include "../core.h" #include "pinctrl-sunxi.h" +static struct irq_chip sunxi_pinctrl_edge_irq_chip; +static struct irq_chip sunxi_pinctrl_level_irq_chip; + static struct sunxi_pinctrl_group * sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) { @@ -547,10 +550,10 @@ static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) return 0; } -static int sunxi_pinctrl_irq_set_type(struct irq_data *d, - unsigned int type) +static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + struct irq_desc *desc = container_of(d, struct irq_desc, irq_data); u32 reg = sunxi_irq_cfg_reg(d->hwirq); u8 index = sunxi_irq_cfg_offset(d->hwirq); unsigned long flags; @@ -577,6 +580,14 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, return -EINVAL; } + if (type & IRQ_TYPE_LEVEL_MASK) { + d->chip = &sunxi_pinctrl_level_irq_chip; + desc->handle_irq = handle_fasteoi_irq; + } else { + d->chip = &sunxi_pinctrl_edge_irq_chip; + desc->handle_irq = handle_edge_irq; + } + spin_lock_irqsave(&pctl->lock, flags); regval = readl(pctl->membase + reg); @@ -632,7 +643,7 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d) spin_unlock_irqrestore(&pctl->lock, flags); } -static struct irq_chip sunxi_pinctrl_irq_chip = { +static struct irq_chip sunxi_pinctrl_edge_irq_chip = { .irq_ack = sunxi_pinctrl_irq_ack, .irq_mask = sunxi_pinctrl_irq_mask, .irq_unmask = sunxi_pinctrl_irq_unmask, @@ -641,6 +652,16 @@ static struct irq_chip sunxi_pinctrl_irq_chip = { .flags = IRQCHIP_SKIP_SET_WAKE, }; +static struct irq_chip sunxi_pinctrl_level_irq_chip = { + .irq_eoi = sunxi_pinctrl_irq_ack, + .irq_mask = sunxi_pinctrl_irq_mask, + .irq_unmask = sunxi_pinctrl_irq_unmask, + .irq_request_resources = sunxi_pinctrl_irq_request_resources, + .irq_set_type = sunxi_pinctrl_irq_set_type, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | + IRQCHIP_EOI_IF_HANDLED, +}; + static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) { struct irq_chip *chip = irq_get_chip(irq); @@ -657,9 +678,6 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) reg = sunxi_irq_status_reg_from_bank(bank); val = readl(pctl->membase + reg); - /* Clear all interrupts */ - writel(val, pctl->membase + reg); - if (val) { int irqoffset; @@ -929,12 +947,17 @@ int sunxi_pinctrl_init(struct platform_device *pdev, for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { int irqno = irq_create_mapping(pctl->domain, i); - irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, - handle_simple_irq); + irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, + handle_edge_irq); irq_set_chip_data(irqno, pctl); }; for (i = 0; i < pctl->desc->irq_banks; i++) { + /* Mask and clear all IRQs before registering a handler */ + writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i)); + writel(0xffffffff, + pctl->membase + sunxi_irq_status_reg_from_bank(i)); + irq_set_chained_handler(pctl->irq[i], sunxi_pinctrl_irq_handler); irq_set_handler_data(pctl->irq[i], pctl); -- cgit v1.2.3 From d61e23e5250e2d189f6bcdac71abf3e997398714 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 29 Jun 2014 16:11:02 +0200 Subject: pinctrl: sunxi: Define enable / disable irq callbacks Some drivers use disable_irq / enable_irq and do the work clearing the source in another thread instead of using a threaded interrupt handler. The irqchip used not having irq_disable and irq_enable callbacks in this case, will lead to unnecessary spurious interrupts: On a disable_irq in a chip without a handler for this, the irq core will remember the disable, but not actually call into the irqchip. With a level triggered interrupt (where the source has not been cleared) this will lead to an immediate retrigger, at which point the irq-core will mask the irq. So having an irq_disable callback in the irqchip will save us the interrupt firing a 2nd time for nothing. Drivers using disable / enable_irq like this, will call enable_irq when they finally have cleared the interrupt source, without an enable_irq callback, this will turn into an unmask, at which point the irq will trigger immediately because when it was originally acked the level was still high, so the ack was a nop. Signed-off-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index c1f053014dd6..c641566c6efd 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -643,6 +643,12 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d) spin_unlock_irqrestore(&pctl->lock, flags); } +static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) +{ + sunxi_pinctrl_irq_ack(d); + sunxi_pinctrl_irq_unmask(d); +} + static struct irq_chip sunxi_pinctrl_edge_irq_chip = { .irq_ack = sunxi_pinctrl_irq_ack, .irq_mask = sunxi_pinctrl_irq_mask, @@ -656,6 +662,10 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip = { .irq_eoi = sunxi_pinctrl_irq_ack, .irq_mask = sunxi_pinctrl_irq_mask, .irq_unmask = sunxi_pinctrl_irq_unmask, + /* Define irq_enable / disable to avoid spurious irqs for drivers + * using these to suppress irqs while they clear the irq source */ + .irq_enable = sunxi_pinctrl_irq_ack_unmask, + .irq_disable = sunxi_pinctrl_irq_mask, .irq_request_resources = sunxi_pinctrl_irq_request_resources, .irq_set_type = sunxi_pinctrl_irq_set_type, .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | -- cgit v1.2.3 From 0d3bafac658de2f8e267df805a61e597449699b5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 1 Jul 2014 00:04:59 +0800 Subject: pinctrl: sunxi: Fix multi bank interrupt support in gpio_to_irq When mapping the interrupts, the gpio_to_irq function did not consider the bank number of the gpio pin in question, only the offset or the interrupt number in the bank. As a result, requests for interrupts in the later banks get mapped to the first bank. This issue was discovered while enabling mmc on the new sun8i platform. The tablet I have uses a pin/interrupt from the second bank to do mmc card detection. Tested on this very device with register inspection and actual mmc card insertion/removal. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index c641566c6efd..47f5e1bc50d0 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -520,6 +520,7 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); struct sunxi_desc_function *desc; + unsigned irqnum; if (offset >= chip->ngpio) return -ENXIO; @@ -528,10 +529,12 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) if (!desc) return -EINVAL; + irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; + dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", - chip->label, offset + chip->base, desc->irqnum); + chip->label, offset + chip->base, irqnum); - return irq_find_mapping(pctl->domain, desc->irqnum); + return irq_find_mapping(pctl->domain, irqnum); } static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) -- cgit v1.2.3 From 4877e51ed791ac0098471d547f9f8f84c147e1c6 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 3 Jun 2014 20:33:49 +0400 Subject: pinctrl: Add i.MX1 pincontrol driver This patch adds pincontrol driver for Freescale i.MX1 SOCs. Acked-by: Shawn Guo Signed-off-by: Alexander Shiyan Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 7 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-imx1.c | 279 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 287 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-imx1.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4af9e3519388..2744fa2825e0 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -130,6 +130,13 @@ config PINCTRL_IMX1_CORE select PINMUX select PINCONF +config PINCTRL_IMX1 + bool "IMX1 pinctrl driver" + depends on SOC_IMX1 + select PINCTRL_IMX1_CORE + help + Say Y here to enable the imx1 pinctrl driver + config PINCTRL_IMX27 bool "IMX27 pinctrl driver" depends on SOC_IMX27 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c4b5d405b8f5..c7d8f1b7311f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o +obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o diff --git a/drivers/pinctrl/pinctrl-imx1.c b/drivers/pinctrl/pinctrl-imx1.c new file mode 100644 index 000000000000..533a6e519648 --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx1.c @@ -0,0 +1,279 @@ +/* + * i.MX1 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2014 Alexander Shiyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +#include "pinctrl-imx1.h" + +#define PAD_ID(port, pin) ((port) * 32 + (pin)) +#define PA 0 +#define PB 1 +#define PC 2 +#define PD 3 + +enum imx1_pads { + MX1_PAD_A24 = PAD_ID(PA, 0), + MX1_PAD_TIN = PAD_ID(PA, 1), + MX1_PAD_PWMO = PAD_ID(PA, 2), + MX1_PAD_CSI_MCLK = PAD_ID(PA, 3), + MX1_PAD_CSI_D0 = PAD_ID(PA, 4), + MX1_PAD_CSI_D1 = PAD_ID(PA, 5), + MX1_PAD_CSI_D2 = PAD_ID(PA, 6), + MX1_PAD_CSI_D3 = PAD_ID(PA, 7), + MX1_PAD_CSI_D4 = PAD_ID(PA, 8), + MX1_PAD_CSI_D5 = PAD_ID(PA, 9), + MX1_PAD_CSI_D6 = PAD_ID(PA, 10), + MX1_PAD_CSI_D7 = PAD_ID(PA, 11), + MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12), + MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13), + MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14), + MX1_PAD_I2C_SDA = PAD_ID(PA, 15), + MX1_PAD_I2C_SCL = PAD_ID(PA, 16), + MX1_PAD_DTACK = PAD_ID(PA, 17), + MX1_PAD_BCLK = PAD_ID(PA, 18), + MX1_PAD_LBA = PAD_ID(PA, 19), + MX1_PAD_ECB = PAD_ID(PA, 20), + MX1_PAD_A0 = PAD_ID(PA, 21), + MX1_PAD_CS4 = PAD_ID(PA, 22), + MX1_PAD_CS5 = PAD_ID(PA, 23), + MX1_PAD_A16 = PAD_ID(PA, 24), + MX1_PAD_A17 = PAD_ID(PA, 25), + MX1_PAD_A18 = PAD_ID(PA, 26), + MX1_PAD_A19 = PAD_ID(PA, 27), + MX1_PAD_A20 = PAD_ID(PA, 28), + MX1_PAD_A21 = PAD_ID(PA, 29), + MX1_PAD_A22 = PAD_ID(PA, 30), + MX1_PAD_A23 = PAD_ID(PA, 31), + MX1_PAD_SD_DAT0 = PAD_ID(PB, 8), + MX1_PAD_SD_DAT1 = PAD_ID(PB, 9), + MX1_PAD_SD_DAT2 = PAD_ID(PB, 10), + MX1_PAD_SD_DAT3 = PAD_ID(PB, 11), + MX1_PAD_SD_SCLK = PAD_ID(PB, 12), + MX1_PAD_SD_CMD = PAD_ID(PB, 13), + MX1_PAD_SIM_SVEN = PAD_ID(PB, 14), + MX1_PAD_SIM_PD = PAD_ID(PB, 15), + MX1_PAD_SIM_TX = PAD_ID(PB, 16), + MX1_PAD_SIM_RX = PAD_ID(PB, 17), + MX1_PAD_SIM_RST = PAD_ID(PB, 18), + MX1_PAD_SIM_CLK = PAD_ID(PB, 19), + MX1_PAD_USBD_AFE = PAD_ID(PB, 20), + MX1_PAD_USBD_OE = PAD_ID(PB, 21), + MX1_PAD_USBD_RCV = PAD_ID(PB, 22), + MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23), + MX1_PAD_USBD_VP = PAD_ID(PB, 24), + MX1_PAD_USBD_VM = PAD_ID(PB, 25), + MX1_PAD_USBD_VPO = PAD_ID(PB, 26), + MX1_PAD_USBD_VMO = PAD_ID(PB, 27), + MX1_PAD_UART2_CTS = PAD_ID(PB, 28), + MX1_PAD_UART2_RTS = PAD_ID(PB, 29), + MX1_PAD_UART2_TXD = PAD_ID(PB, 30), + MX1_PAD_UART2_RXD = PAD_ID(PB, 31), + MX1_PAD_SSI_RXFS = PAD_ID(PC, 3), + MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4), + MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5), + MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6), + MX1_PAD_SSI_TXFS = PAD_ID(PC, 7), + MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8), + MX1_PAD_UART1_CTS = PAD_ID(PC, 9), + MX1_PAD_UART1_RTS = PAD_ID(PC, 10), + MX1_PAD_UART1_TXD = PAD_ID(PC, 11), + MX1_PAD_UART1_RXD = PAD_ID(PC, 12), + MX1_PAD_SPI1_RDY = PAD_ID(PC, 13), + MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14), + MX1_PAD_SPI1_SS = PAD_ID(PC, 15), + MX1_PAD_SPI1_MISO = PAD_ID(PC, 16), + MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17), + MX1_PAD_BT13 = PAD_ID(PC, 19), + MX1_PAD_BT12 = PAD_ID(PC, 20), + MX1_PAD_BT11 = PAD_ID(PC, 21), + MX1_PAD_BT10 = PAD_ID(PC, 22), + MX1_PAD_BT9 = PAD_ID(PC, 23), + MX1_PAD_BT8 = PAD_ID(PC, 24), + MX1_PAD_BT7 = PAD_ID(PC, 25), + MX1_PAD_BT6 = PAD_ID(PC, 26), + MX1_PAD_BT5 = PAD_ID(PC, 27), + MX1_PAD_BT4 = PAD_ID(PC, 28), + MX1_PAD_BT3 = PAD_ID(PC, 29), + MX1_PAD_BT2 = PAD_ID(PC, 30), + MX1_PAD_BT1 = PAD_ID(PC, 31), + MX1_PAD_LSCLK = PAD_ID(PD, 6), + MX1_PAD_REV = PAD_ID(PD, 7), + MX1_PAD_CLS = PAD_ID(PD, 8), + MX1_PAD_PS = PAD_ID(PD, 9), + MX1_PAD_SPL_SPR = PAD_ID(PD, 10), + MX1_PAD_CONTRAST = PAD_ID(PD, 11), + MX1_PAD_ACD_OE = PAD_ID(PD, 12), + MX1_PAD_LP_HSYNC = PAD_ID(PD, 13), + MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14), + MX1_PAD_LD0 = PAD_ID(PD, 15), + MX1_PAD_LD1 = PAD_ID(PD, 16), + MX1_PAD_LD2 = PAD_ID(PD, 17), + MX1_PAD_LD3 = PAD_ID(PD, 18), + MX1_PAD_LD4 = PAD_ID(PD, 19), + MX1_PAD_LD5 = PAD_ID(PD, 20), + MX1_PAD_LD6 = PAD_ID(PD, 21), + MX1_PAD_LD7 = PAD_ID(PD, 22), + MX1_PAD_LD8 = PAD_ID(PD, 23), + MX1_PAD_LD9 = PAD_ID(PD, 24), + MX1_PAD_LD10 = PAD_ID(PD, 25), + MX1_PAD_LD11 = PAD_ID(PD, 26), + MX1_PAD_LD12 = PAD_ID(PD, 27), + MX1_PAD_LD13 = PAD_ID(PD, 28), + MX1_PAD_LD14 = PAD_ID(PD, 29), + MX1_PAD_LD15 = PAD_ID(PD, 30), + MX1_PAD_TMR2OUT = PAD_ID(PD, 31), +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX1_PAD_A24), + IMX_PINCTRL_PIN(MX1_PAD_TIN), + IMX_PINCTRL_PIN(MX1_PAD_PWMO), + IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D0), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D1), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA), + IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL), + IMX_PINCTRL_PIN(MX1_PAD_DTACK), + IMX_PINCTRL_PIN(MX1_PAD_BCLK), + IMX_PINCTRL_PIN(MX1_PAD_LBA), + IMX_PINCTRL_PIN(MX1_PAD_ECB), + IMX_PINCTRL_PIN(MX1_PAD_A0), + IMX_PINCTRL_PIN(MX1_PAD_CS4), + IMX_PINCTRL_PIN(MX1_PAD_CS5), + IMX_PINCTRL_PIN(MX1_PAD_A16), + IMX_PINCTRL_PIN(MX1_PAD_A17), + IMX_PINCTRL_PIN(MX1_PAD_A18), + IMX_PINCTRL_PIN(MX1_PAD_A19), + IMX_PINCTRL_PIN(MX1_PAD_A20), + IMX_PINCTRL_PIN(MX1_PAD_A21), + IMX_PINCTRL_PIN(MX1_PAD_A22), + IMX_PINCTRL_PIN(MX1_PAD_A23), + IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0), + IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1), + IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2), + IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3), + IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK), + IMX_PINCTRL_PIN(MX1_PAD_SD_CMD), + IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN), + IMX_PINCTRL_PIN(MX1_PAD_SIM_PD), + IMX_PINCTRL_PIN(MX1_PAD_SIM_TX), + IMX_PINCTRL_PIN(MX1_PAD_SIM_RX), + IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK), + IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE), + IMX_PINCTRL_PIN(MX1_PAD_USBD_OE), + IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV), + IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND), + IMX_PINCTRL_PIN(MX1_PAD_USBD_VP), + IMX_PINCTRL_PIN(MX1_PAD_USBD_VM), + IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO), + IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO), + IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS), + IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK), + IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT), + IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT), + IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS), + IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK), + IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI), + IMX_PINCTRL_PIN(MX1_PAD_BT13), + IMX_PINCTRL_PIN(MX1_PAD_BT12), + IMX_PINCTRL_PIN(MX1_PAD_BT11), + IMX_PINCTRL_PIN(MX1_PAD_BT10), + IMX_PINCTRL_PIN(MX1_PAD_BT9), + IMX_PINCTRL_PIN(MX1_PAD_BT8), + IMX_PINCTRL_PIN(MX1_PAD_BT7), + IMX_PINCTRL_PIN(MX1_PAD_BT6), + IMX_PINCTRL_PIN(MX1_PAD_BT5), + IMX_PINCTRL_PIN(MX1_PAD_BT4), + IMX_PINCTRL_PIN(MX1_PAD_BT3), + IMX_PINCTRL_PIN(MX1_PAD_BT2), + IMX_PINCTRL_PIN(MX1_PAD_BT1), + IMX_PINCTRL_PIN(MX1_PAD_LSCLK), + IMX_PINCTRL_PIN(MX1_PAD_REV), + IMX_PINCTRL_PIN(MX1_PAD_CLS), + IMX_PINCTRL_PIN(MX1_PAD_PS), + IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR), + IMX_PINCTRL_PIN(MX1_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX1_PAD_ACD_OE), + IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC), + IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC), + IMX_PINCTRL_PIN(MX1_PAD_LD0), + IMX_PINCTRL_PIN(MX1_PAD_LD1), + IMX_PINCTRL_PIN(MX1_PAD_LD2), + IMX_PINCTRL_PIN(MX1_PAD_LD3), + IMX_PINCTRL_PIN(MX1_PAD_LD4), + IMX_PINCTRL_PIN(MX1_PAD_LD5), + IMX_PINCTRL_PIN(MX1_PAD_LD6), + IMX_PINCTRL_PIN(MX1_PAD_LD7), + IMX_PINCTRL_PIN(MX1_PAD_LD8), + IMX_PINCTRL_PIN(MX1_PAD_LD9), + IMX_PINCTRL_PIN(MX1_PAD_LD10), + IMX_PINCTRL_PIN(MX1_PAD_LD11), + IMX_PINCTRL_PIN(MX1_PAD_LD12), + IMX_PINCTRL_PIN(MX1_PAD_LD13), + IMX_PINCTRL_PIN(MX1_PAD_LD14), + IMX_PINCTRL_PIN(MX1_PAD_LD15), + IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT), +}; + +static struct imx1_pinctrl_soc_info imx1_pinctrl_info = { + .pins = imx1_pinctrl_pads, + .npins = ARRAY_SIZE(imx1_pinctrl_pads), +}; + +static int __init imx1_pinctrl_probe(struct platform_device *pdev) +{ + return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info); +} + +static const struct of_device_id imx1_pinctrl_of_match[] = { + { .compatible = "fsl,imx1-iomuxc", }, + { } +}; +MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match); + +static struct platform_driver imx1_pinctrl_driver = { + .driver = { + .name = "imx1-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx1_pinctrl_of_match, + }, + .remove = imx1_pinctrl_core_remove, +}; +module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe); + +MODULE_AUTHOR("Alexander Shiyan "); +MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From ae23f9b1afa718d7eaa52b111fa41f0ee31a0a33 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 3 Jun 2014 20:34:14 +0400 Subject: pinctrl: i.MX27: Remove unused structure definition struct imx27_pinctrl_private is not used in the driver. Remove this definition. Signed-off-by: Alexander Shiyan Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-imx27.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c index 417c99205bc2..27ae7ce1b0d4 100644 --- a/drivers/pinctrl/pinctrl-imx27.c +++ b/drivers/pinctrl/pinctrl-imx27.c @@ -440,12 +440,6 @@ static struct of_device_id imx27_pinctrl_of_match[] = { { /* sentinel */ } }; -struct imx27_pinctrl_private { - int num_gpio_childs; - struct platform_device **gpio_dev; - struct mxc_gpio_platform_data *gpio_pdata; -}; - static int imx27_pinctrl_probe(struct platform_device *pdev) { return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info); -- cgit v1.2.3 From 607af165c0470e7297e1a04f528176222849b5a9 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 3 Jun 2014 20:34:15 +0400 Subject: pinctrl: i.MX27: Remove nonexistent pad definitions Pads for PB0-PB3, PC0-PC4, PE26-PE31 and PF24-PF31 does not exist on the i.MX27 SOC. There is no reason to define them, the presence of such definitions in the DTS files is a bug. This patch removes these nonexistent pad definitions. Signed-off-by: Alexander Shiyan Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-imx27.c | 46 ----------------------------------------- 1 file changed, 46 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c index 27ae7ce1b0d4..f8dfefb69968 100644 --- a/drivers/pinctrl/pinctrl-imx27.c +++ b/drivers/pinctrl/pinctrl-imx27.c @@ -63,10 +63,6 @@ enum imx27_pads { MX27_PAD_CONTRAST = PAD_ID(PA, 30), MX27_PAD_OE_ACD = PAD_ID(PA, 31), - MX27_PAD_UNUSED0 = PAD_ID(PB, 0), - MX27_PAD_UNUSED1 = PAD_ID(PB, 1), - MX27_PAD_UNUSED2 = PAD_ID(PB, 2), - MX27_PAD_UNUSED3 = PAD_ID(PB, 3), MX27_PAD_SD2_D0 = PAD_ID(PB, 4), MX27_PAD_SD2_D1 = PAD_ID(PB, 5), MX27_PAD_SD2_D2 = PAD_ID(PB, 6), @@ -96,11 +92,6 @@ enum imx27_pads { MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), - MX27_PAD_UNUSED4 = PAD_ID(PC, 0), - MX27_PAD_UNUSED5 = PAD_ID(PC, 1), - MX27_PAD_UNUSED6 = PAD_ID(PC, 2), - MX27_PAD_UNUSED7 = PAD_ID(PC, 3), - MX27_PAD_UNUSED8 = PAD_ID(PC, 4), MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), @@ -188,12 +179,6 @@ enum imx27_pads { MX27_PAD_SD1_CLK = PAD_ID(PE, 23), MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), - MX27_PAD_UNUSED9 = PAD_ID(PE, 26), - MX27_PAD_UNUSED10 = PAD_ID(PE, 27), - MX27_PAD_UNUSED11 = PAD_ID(PE, 28), - MX27_PAD_UNUSED12 = PAD_ID(PE, 29), - MX27_PAD_UNUSED13 = PAD_ID(PE, 30), - MX27_PAD_UNUSED14 = PAD_ID(PE, 31), MX27_PAD_NFRB = PAD_ID(PF, 0), MX27_PAD_NFCLE = PAD_ID(PF, 1), @@ -219,14 +204,6 @@ enum imx27_pads { MX27_PAD_CS4_B = PAD_ID(PF, 21), MX27_PAD_CS5_B = PAD_ID(PF, 22), MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), - MX27_PAD_UNUSED15 = PAD_ID(PF, 24), - MX27_PAD_UNUSED16 = PAD_ID(PF, 25), - MX27_PAD_UNUSED17 = PAD_ID(PF, 26), - MX27_PAD_UNUSED18 = PAD_ID(PF, 27), - MX27_PAD_UNUSED19 = PAD_ID(PF, 28), - MX27_PAD_UNUSED20 = PAD_ID(PF, 29), - MX27_PAD_UNUSED21 = PAD_ID(PF, 30), - MX27_PAD_UNUSED22 = PAD_ID(PF, 31), }; /* Pad names for the pinmux subsystem */ @@ -264,10 +241,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX27_PAD_CONTRAST), IMX_PINCTRL_PIN(MX27_PAD_OE_ACD), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED0), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED1), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED2), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED3), IMX_PINCTRL_PIN(MX27_PAD_SD2_D0), IMX_PINCTRL_PIN(MX27_PAD_SD2_D1), IMX_PINCTRL_PIN(MX27_PAD_SD2_D2), @@ -297,11 +270,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM), IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED4), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED5), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED6), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED7), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED8), IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA), IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL), IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5), @@ -389,12 +357,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK), IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK), IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED9), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED10), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED11), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED12), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED13), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED14), IMX_PINCTRL_PIN(MX27_PAD_NFRB), IMX_PINCTRL_PIN(MX27_PAD_NFCLE), @@ -420,14 +382,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX27_PAD_CS4_B), IMX_PINCTRL_PIN(MX27_PAD_CS5_B), IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED15), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED16), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED17), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED18), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED19), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED20), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED21), - IMX_PINCTRL_PIN(MX27_PAD_UNUSED22), }; static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { -- cgit v1.2.3 From 2243a87d90b42eb38bc281957df3e57c712b5e56 Mon Sep 17 00:00:00 2001 From: Fan Wu Date: Mon, 9 Jun 2014 09:37:56 +0800 Subject: pinctrl: avoid duplicated calling enable_pinmux_setting for a pin What the patch does: 1. Call pinmux_disable_setting ahead of pinmux_enable_setting each time pinctrl_select_state is called 2. Remove the HW disable operation in pinmux_disable_setting function. 3. Remove the disable ops in struct pinmux_ops 4. Remove all the disable ops users in current code base. Notes: 1. Great thanks for the suggestion from Linus, Tony Lindgren and Stephen Warren and Everyone that shared comments on this patch. 2. The patch also includes comment fixes from Stephen Warren. The reason why we do this: 1. To avoid duplicated calling of the enable_setting operation without disabling operation inbetween which will let the pin descriptor desc->mux_usecount increase monotonously. 2. The HW pin disable operation is not useful for any of the existing platforms. And this can be used to avoid the HW glitch after using the item #1 modification. In the following case, the issue can be reproduced: 1. There is a driver that need to switch pin state dynamically, e.g. between "sleep" and "default" state 2. The pin setting configuration in a DTS node may be like this: component a { pinctrl-names = "default", "sleep"; pinctrl-0 = <&a_grp_setting &c_grp_setting>; pinctrl-1 = <&b_grp_setting &c_grp_setting>; } The "c_grp_setting" config node is totally identical, maybe like following one: c_grp_setting: c_grp_setting { pinctrl-single,pins = ; } 3. When switching the pin state in the following official pinctrl sequence: pin = pinctrl_get(); state = pinctrl_lookup_state(wanted_state); pinctrl_select_state(state); pinctrl_put(); Test Result: 1. The switch is completed as expected, that is: the device's pin configuration is changed according to the description in the "wanted_state" group setting 2. The "desc->mux_usecount" of the corresponding pins in "c_group" is increased without being decreased, because the "desc" is for each physical pin while the setting is for each setting node in the DTS. Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount will keep increasing without any chance to be decreased. According to the comments in the original code, only the setting, in old state but not in new state, will be "disabled" (calling pinmux_disable_setting), which is correct logic but not intact. We still need consider case that the setting is in both old state and new state. We can do this in the following two ways: 1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin setting" repeatedly 2. "Disable"(calling pinmux_disable_setting) the "same pin setting", actually two setting instances, ahead of enabling them. Analysis: 1. The solution #2 is better because it can avoid too much iteration. 2. If we disable all of the settings in the old state and one of the setting(s) exist in the new state, the pins mux function change may happen when some SoC vendors defined the "pinctrl-single,function-off" in their DTS file. old_setting => disabled_setting => new_setting. 3. In the pinmux framework, when a pin state is switched, the setting in the old state should be marked as "disabled". Conclusion: 1. To Remove the HW disabling operation to above the glitch mentioned above. 2. Handle the issue mentioned above by disabling all of the settings in old state and then enable the all of the settings in new state. Signed-off-by: Fan Wu Acked-by: Stephen Warren Acked-by: Patrice Chotard Acked-by: Heiko Stuebner Acked-by: Maxime Coquelin Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 24 +++------------ drivers/pinctrl/pinctrl-abx500.c | 15 --------- drivers/pinctrl/pinctrl-adi2.c | 30 ------------------ drivers/pinctrl/pinctrl-at91.c | 21 ------------- drivers/pinctrl/pinctrl-bcm2835.c | 11 ------- drivers/pinctrl/pinctrl-exynos5440.c | 8 ----- drivers/pinctrl/pinctrl-msm.c | 25 --------------- drivers/pinctrl/pinctrl-nomadik.c | 16 ---------- drivers/pinctrl/pinctrl-rockchip.c | 18 ----------- drivers/pinctrl/pinctrl-samsung.c | 8 ----- drivers/pinctrl/pinctrl-single.c | 56 --------------------------------- drivers/pinctrl/pinctrl-st.c | 6 ---- drivers/pinctrl/pinctrl-tb10x.c | 17 ---------- drivers/pinctrl/pinctrl-tegra.c | 13 -------- drivers/pinctrl/pinctrl-tz1090-pdc.c | 28 ----------------- drivers/pinctrl/pinctrl-tz1090.c | 58 ----------------------------------- drivers/pinctrl/pinctrl-u300.c | 14 --------- drivers/pinctrl/pinmux.c | 4 --- drivers/pinctrl/sh-pfc/pinctrl.c | 22 ------------- drivers/pinctrl/sirf/pinctrl-sirf.c | 10 ------ drivers/pinctrl/spear/pinctrl-spear.c | 7 ----- drivers/pinctrl/vt8500/pinctrl-wmt.c | 12 -------- 22 files changed, 5 insertions(+), 418 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index e09474ecde23..e4f65510c87e 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -992,29 +992,15 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state) if (p->state) { /* - * The set of groups with a mux configuration in the old state - * may not be identical to the set of groups with a mux setting - * in the new state. While this might be unusual, it's entirely - * possible for the "user"-supplied mapping table to be written - * that way. For each group that was configured in the old state - * but not in the new state, this code puts that group into a - * safe/disabled state. + * For each pinmux setting in the old state, forget SW's record + * of mux owner for that pingroup. Any pingroups which are + * still owned by the new state will be re-acquired by the call + * to pinmux_enable_setting() in the loop below. */ list_for_each_entry(setting, &p->state->settings, node) { - bool found = false; if (setting->type != PIN_MAP_TYPE_MUX_GROUP) continue; - list_for_each_entry(setting2, &state->settings, node) { - if (setting2->type != PIN_MAP_TYPE_MUX_GROUP) - continue; - if (setting2->data.mux.group == - setting->data.mux.group) { - found = true; - break; - } - } - if (!found) - pinmux_disable_setting(setting); + pinmux_disable_setting(setting); } } diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index 163da9c3ea0e..f3f8b24efe54 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -737,20 +737,6 @@ static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, return ret; } -static void abx500_pmx_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - const struct abx500_pingroup *g; - - g = &pct->soc->groups[group]; - if (g->altsetting < 0) - return; - - /* FIXME: poke out the mux, set the pin to some default state? */ - dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins); -} - static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) @@ -799,7 +785,6 @@ static const struct pinmux_ops abx500_pinmux_ops = { .get_function_name = abx500_pmx_get_func_name, .get_function_groups = abx500_pmx_get_func_groups, .enable = abx500_pmx_enable, - .disable = abx500_pmx_disable, .gpio_request_enable = abx500_gpio_request_enable, .gpio_disable_free = abx500_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 5c44feb54ebb..b02ee4f882c0 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -652,35 +652,6 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id, return 0; } -static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id, - unsigned group_id) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_port *port; - struct pinctrl_gpio_range *range; - unsigned long flags; - unsigned short *mux, pin; - - mux = (unsigned short *)pinctrl->soc->groups[group_id].mux; - - while (*mux) { - pin = P_IDENT(*mux); - - range = pinctrl_find_gpio_range_from_pin(pctldev, pin); - if (range == NULL) /* should not happen */ - return; - - port = container_of(range->gc, struct gpio_port, chip); - - spin_lock_irqsave(&port->lock, flags); - - port_setup(port, pin_to_offset(range, pin), true); - mux++; - - spin_unlock_irqrestore(&port->lock, flags); - } -} - static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) { struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); @@ -728,7 +699,6 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev, static struct pinmux_ops adi_pinmux_ops = { .enable = adi_pinmux_enable, - .disable = adi_pinmux_disable, .get_functions_count = adi_pinmux_get_funcs_count, .get_function_name = adi_pinmux_get_func_name, .get_function_groups = adi_pinmux_get_groups, diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 421493cb490c..bd57ab514aa4 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -611,26 +611,6 @@ static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; - const struct at91_pmx_pin *pin; - uint32_t npins = info->groups[group].npins; - int i; - unsigned mask; - void __iomem *pio; - - for (i = 0; i < npins; i++) { - pin = &pins_conf[i]; - at91_pin_dbg(info->dev, pin); - pio = pin_to_controller(info, pin->bank); - mask = pin_to_mask(pin->pin); - at91_mux_gpio_enable(pio, mask, 1); - } -} - static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) { struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); @@ -705,7 +685,6 @@ static const struct pinmux_ops at91_pmx_ops = { .get_function_name = at91_pmx_get_func_name, .get_function_groups = at91_pmx_get_groups, .enable = at91_pmx_enable, - .disable = at91_pmx_disable, .gpio_request_enable = at91_gpio_request_enable, .gpio_disable_free = at91_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c index 3d907de9bc91..5bcfd7ace0cd 100644 --- a/drivers/pinctrl/pinctrl-bcm2835.c +++ b/drivers/pinctrl/pinctrl-bcm2835.c @@ -841,16 +841,6 @@ static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev, return 0; } -static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev, - unsigned func_selector, - unsigned group_selector) -{ - struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); - - /* disable by setting to GPIO_IN */ - bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN); -} - static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) @@ -880,7 +870,6 @@ static const struct pinmux_ops bcm2835_pmx_ops = { .get_function_name = bcm2835_pmx_get_function_name, .get_function_groups = bcm2835_pmx_get_function_groups, .enable = bcm2835_pmx_enable, - .disable = bcm2835_pmx_disable, .gpio_disable_free = bcm2835_pmx_gpio_disable_free, .gpio_set_direction = bcm2835_pmx_gpio_set_direction, }; diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c index 8fe2ab0a7698..4b145b5db7a6 100644 --- a/drivers/pinctrl/pinctrl-exynos5440.c +++ b/drivers/pinctrl/pinctrl-exynos5440.c @@ -371,13 +371,6 @@ static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned select return 0; } -/* disable a specified pinmux by writing to registers */ -static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev, - unsigned selector, unsigned group) -{ - exynos5440_pinmux_setup(pctldev, selector, group, false); -} - /* * The calls to gpio_direction_output() and gpio_direction_input() * leads to this function call (via the pinctrl_gpio_direction_{input|output}() @@ -395,7 +388,6 @@ static const struct pinmux_ops exynos5440_pinmux_ops = { .get_function_name = exynos5440_pinmux_get_fname, .get_function_groups = exynos5440_pinmux_get_groups, .enable = exynos5440_pinmux_enable, - .disable = exynos5440_pinmux_disable, .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, }; diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c index df6dda4ce803..bdfaba4430f2 100644 --- a/drivers/pinctrl/pinctrl-msm.c +++ b/drivers/pinctrl/pinctrl-msm.c @@ -165,36 +165,11 @@ static int msm_pinmux_enable(struct pinctrl_dev *pctldev, return 0; } -static void msm_pinmux_disable(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[group]; - - if (WARN_ON(g->mux_bit < 0)) - return; - - spin_lock_irqsave(&pctrl->lock, flags); - - /* Clear the mux bits to select gpio mode */ - val = readl(pctrl->regs + g->ctl_reg); - val &= ~(0x7 << g->mux_bit); - writel(val, pctrl->regs + g->ctl_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - static const struct pinmux_ops msm_pinmux_ops = { .get_functions_count = msm_get_functions_count, .get_function_name = msm_get_function_name, .get_function_groups = msm_get_function_groups, .enable = msm_pinmux_enable, - .disable = msm_pinmux_disable, }; static int msm_config_reg(struct msm_pinctrl *pctrl, diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 8f6f16ef73f3..a564251fe093 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -1765,21 +1765,6 @@ out_glitch: return ret; } -static void nmk_pmx_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - const struct nmk_pingroup *g; - - g = &npct->soc->groups[group]; - - if (g->altsetting < 0) - return; - - /* Poke out the mux, set the pin to some default state? */ - dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); -} - static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) @@ -1826,7 +1811,6 @@ static const struct pinmux_ops nmk_pinmux_ops = { .get_function_name = nmk_pmx_get_func_name, .get_function_groups = nmk_pmx_get_func_groups, .enable = nmk_pmx_enable, - .disable = nmk_pmx_disable, .gpio_request_enable = nmk_gpio_request_enable, .gpio_disable_free = nmk_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index bb805d5e9ff0..51f67a6eadcb 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -657,23 +657,6 @@ static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static void rockchip_pmx_disable(struct pinctrl_dev *pctldev, - unsigned selector, unsigned group) -{ - struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - const unsigned int *pins = info->groups[group].pins; - struct rockchip_pin_bank *bank; - int cnt; - - dev_dbg(info->dev, "disable function %s group %s\n", - info->functions[selector].name, info->groups[group].name); - - for (cnt = 0; cnt < info->groups[group].npins; cnt++) { - bank = pin_to_bank(info, pins[cnt]); - rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); - } -} - /* * The calls to gpio_direction_output() and gpio_direction_input() * leads to this function call (via the pinctrl_gpio_direction_{input|output}() @@ -716,7 +699,6 @@ static const struct pinmux_ops rockchip_pmx_ops = { .get_function_name = rockchip_pmx_get_func_name, .get_function_groups = rockchip_pmx_get_groups, .enable = rockchip_pmx_enable, - .disable = rockchip_pmx_disable, .gpio_set_direction = rockchip_pmx_gpio_set_direction, }; diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 3e61d0f8f146..089abde35d44 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -333,13 +333,6 @@ static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -/* disable a specified pinmux by writing to registers */ -static void samsung_pinmux_disable(struct pinctrl_dev *pctldev, - unsigned selector, unsigned group) -{ - samsung_pinmux_setup(pctldev, selector, group, false); -} - /* * The calls to gpio_direction_output() and gpio_direction_input() * leads to this function call (via the pinctrl_gpio_direction_{input|output}() @@ -390,7 +383,6 @@ static const struct pinmux_ops samsung_pinmux_ops = { .get_function_name = samsung_pinmux_get_fname, .get_function_groups = samsung_pinmux_get_groups, .enable = samsung_pinmux_enable, - .disable = samsung_pinmux_disable, .gpio_set_direction = samsung_pinmux_gpio_set_direction, }; diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 2960557bfed9..ff6a2bda52e5 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -488,61 +488,6 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, return 0; } -static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, - unsigned group) -{ - struct pcs_device *pcs; - struct pcs_function *func; - int i; - - pcs = pinctrl_dev_get_drvdata(pctldev); - /* If function mask is null, needn't disable it. */ - if (!pcs->fmask) - return; - - func = radix_tree_lookup(&pcs->ftree, fselector); - if (!func) { - dev_err(pcs->dev, "%s could not find function%i\n", - __func__, fselector); - return; - } - - /* - * Ignore disable if function-off is not specified. Some hardware - * does not have clearly defined disable function. For pin specific - * off modes, you can use alternate named states as described in - * pinctrl-bindings.txt. - */ - if (pcs->foff == PCS_OFF_DISABLED) { - dev_dbg(pcs->dev, "ignoring disable for %s function%i\n", - func->name, fselector); - return; - } - - dev_dbg(pcs->dev, "disabling function%i %s\n", - fselector, func->name); - - for (i = 0; i < func->nvals; i++) { - struct pcs_func_vals *vals; - unsigned long flags; - unsigned val, mask; - - vals = &func->vals[i]; - raw_spin_lock_irqsave(&pcs->lock, flags); - val = pcs->read(vals->reg); - - if (pcs->bits_per_mux) - mask = vals->mask; - else - mask = pcs->fmask; - - val &= ~mask; - val |= pcs->foff << pcs->fshift; - pcs->write(val, vals->reg); - raw_spin_unlock_irqrestore(&pcs->lock, flags); - } -} - static int pcs_request_gpio(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin) { @@ -575,7 +520,6 @@ static const struct pinmux_ops pcs_pinmux_ops = { .get_function_name = pcs_get_function_name, .get_function_groups = pcs_get_function_groups, .enable = pcs_enable, - .disable = pcs_disable, .gpio_request_enable = pcs_request_gpio, }; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 1bd6363bc95e..e1919cd43117 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -930,11 +930,6 @@ static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector, return 0; } -static void st_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ -} - static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned gpio, bool input) @@ -957,7 +952,6 @@ static struct pinmux_ops st_pmxops = { .get_function_name = st_pmx_get_fname, .get_function_groups = st_pmx_get_groups, .enable = st_pmx_enable, - .disable = st_pmx_disable, .gpio_set_direction = st_pmx_set_gpio_direction, }; diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index 26ca6855f478..71c5d4f0c538 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -738,22 +738,6 @@ static int tb10x_pctl_enable(struct pinctrl_dev *pctl, return 0; } -static void tb10x_pctl_disable(struct pinctrl_dev *pctl, - unsigned func_selector, unsigned group_selector) -{ - struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); - const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector]; - - if (grp->port < 0) - return; - - mutex_lock(&state->mutex); - - state->ports[grp->port].count--; - - mutex_unlock(&state->mutex); -} - static struct pinmux_ops tb10x_pinmux_ops = { .get_functions_count = tb10x_get_functions_count, .get_function_name = tb10x_get_function_name, @@ -761,7 +745,6 @@ static struct pinmux_ops tb10x_pinmux_ops = { .gpio_request_enable = tb10x_gpio_request_enable, .gpio_disable_free = tb10x_gpio_disable_free, .enable = tb10x_pctl_enable, - .disable = tb10x_pctl_disable, }; static struct pinctrl_desc tb10x_pindesc = { diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index 2d43bff74f59..150af5503c09 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -290,24 +290,11 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, return 0; } -static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tegra_pingroup *g; - - g = &pmx->soc->groups[group]; - - if (WARN_ON(g->mux_reg < 0)) - return; -} - static const struct pinmux_ops tegra_pinmux_ops = { .get_functions_count = tegra_pinctrl_get_funcs_count, .get_function_name = tegra_pinctrl_get_func_name, .get_function_groups = tegra_pinctrl_get_func_groups, .enable = tegra_pinctrl_enable, - .disable = tegra_pinctrl_disable, }; static int tegra_pinconf_reg(struct tegra_pmx *pmx, diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index 5bf01c28925e..41e81a35cabb 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -574,33 +574,6 @@ static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev, return 0; } -static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev, - unsigned int function, - unsigned int group) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; - - dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n", - __func__, - function, tz1090_pdc_functions[function].name, - group, tz1090_pdc_groups[group].name); - - /* is it even a mux? */ - if (grp->drv) - return; - - /* does this group even control the function? */ - if (function != grp->func) - return; - - /* record the pin being unmuxed and update mux bit */ - spin_lock(&pmx->lock); - pmx->mux_en &= ~BIT(grp->pins[0]); - tz1090_pdc_pinctrl_mux(pmx, grp); - spin_unlock(&pmx->lock); -} - static const struct tz1090_pdc_pingroup *find_mux_group( struct tz1090_pdc_pmx *pmx, unsigned int pin) @@ -662,7 +635,6 @@ static struct pinmux_ops tz1090_pdc_pinmux_ops = { .get_function_name = tz1090_pdc_pinctrl_get_func_name, .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, .enable = tz1090_pdc_pinctrl_enable, - .disable = tz1090_pdc_pinctrl_disable, .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index bc9cd7a7602e..24082216842e 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1478,63 +1478,6 @@ mux_pins: return 0; } -/** - * tz1090_pinctrl_disable() - Disable a function on a pin group. - * @pctldev: Pin control data - * @function: Function index to disable - * @group: Group index to disable - * - * Disable a particular function on a group of pins. The per GPIO pin pseudo pin - * groups can be used (in which case the pin will be taken out of peripheral - * mode. Some convenience pin groups can also be used in which case the effect - * is the same as enabling the function on each individual pin in the group. - */ -static void tz1090_pinctrl_disable(struct pinctrl_dev *pctldev, - unsigned int function, unsigned int group) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct tz1090_pingroup *grp; - unsigned int pin_num, mux_group, i, npins; - const unsigned int *pins; - - /* group of pins? */ - if (group < ARRAY_SIZE(tz1090_groups)) { - grp = &tz1090_groups[group]; - npins = grp->npins; - pins = grp->pins; - /* - * All pins in the group must belong to the same mux group, - * which allows us to just use the mux group of the first pin. - * By explicitly listing permitted pingroups for each function - * the pinmux core should ensure this is always the case. - */ - } else { - pin_num = group - ARRAY_SIZE(tz1090_groups); - npins = 1; - pins = &pin_num; - } - mux_group = tz1090_mux_pins[*pins]; - - /* no mux group, but can still be individually muxed to peripheral */ - if (mux_group >= TZ1090_MUX_GROUP_MAX) { - if (function == TZ1090_MUX_PERIP) - goto unmux_pins; - return; - } - - /* mux group already set to a different function? */ - grp = &tz1090_mux_groups[mux_group]; - dev_dbg(pctldev->dev, "%s: unmuxing %u pin(s) in '%s' from '%s'\n", - __func__, npins, grp->name, tz1090_functions[function].name); - - /* subtract pins from ref count and unmux individually */ - WARN_ON(grp->func_count < npins); - grp->func_count -= npins; -unmux_pins: - for (i = 0; i < npins; ++i) - tz1090_pinctrl_perip_select(pmx, pins[i], false); -} - /** * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode. * @pctldev: Pin control data @@ -1575,7 +1518,6 @@ static struct pinmux_ops tz1090_pinmux_ops = { .get_function_name = tz1090_pinctrl_get_func_name, .get_function_groups = tz1090_pinctrl_get_func_groups, .enable = tz1090_pinctrl_enable, - .disable = tz1090_pinctrl_disable, .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 209a01b8bd3b..0959bb36450f 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -970,19 +970,6 @@ static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct u300_pmx *upmx; - - /* There is nothing to do with the power pins */ - if (selector == 0) - return; - - upmx = pinctrl_dev_get_drvdata(pctldev); - u300_pmx_endisable(upmx, selector, false); -} - static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(u300_pmx_functions); @@ -1008,7 +995,6 @@ static const struct pinmux_ops u300_pmx_ops = { .get_function_name = u300_pmx_get_func_name, .get_function_groups = u300_pmx_get_groups, .enable = u300_pmx_enable, - .disable = u300_pmx_disable, }; static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 051e8592990e..c055daf9a80f 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -471,7 +471,6 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - const struct pinmux_ops *ops = pctldev->desc->pmxops; int ret = 0; const unsigned *pins = NULL; unsigned num_pins = 0; @@ -518,9 +517,6 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting) pins[i], desc->name, gname); } } - - if (ops->disable) - ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group); } #ifdef CONFIG_DEBUG_FS diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index e758af95c209..11db3ee39d40 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -345,27 +345,6 @@ done: return ret; } -static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; - const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; - unsigned long flags; - unsigned int i; - - spin_lock_irqsave(&pfc->lock, flags); - - for (i = 0; i < grp->nr_pins; ++i) { - int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - - cfg->type = PINMUX_TYPE_NONE; - } - - spin_unlock_irqrestore(&pfc->lock, flags); -} - static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) @@ -464,7 +443,6 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = { .get_function_name = sh_pfc_get_function_name, .get_function_groups = sh_pfc_get_function_groups, .enable = sh_pfc_func_enable, - .disable = sh_pfc_func_disable, .gpio_request_enable = sh_pfc_gpio_request_enable, .gpio_disable_free = sh_pfc_gpio_disable_free, .gpio_set_direction = sh_pfc_gpio_set_direction, diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 014f5b1fee55..4c1d7c68666d 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -186,15 +186,6 @@ static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, return 0; } -static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, - unsigned group) -{ - struct sirfsoc_pmx *spmx; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - sirfsoc_pinmux_endisable(spmx, selector, false); -} - static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) { return sirfsoc_pmxfunc_cnt; @@ -240,7 +231,6 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, static struct pinmux_ops sirfsoc_pinmux_ops = { .enable = sirfsoc_pinmux_enable, - .disable = sirfsoc_pinmux_disable, .get_functions_count = sirfsoc_pinmux_get_funcs_count, .get_function_name = sirfsoc_pinmux_get_func_name, .get_function_groups = sirfsoc_pinmux_get_groups, diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index 58bf6867aa17..f72cc4e192bd 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -274,12 +274,6 @@ static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, return spear_pinctrl_endisable(pctldev, function, group, true); } -static void spear_pinctrl_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - spear_pinctrl_endisable(pctldev, function, group, false); -} - /* gpio with pinmux */ static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx, unsigned pin) @@ -345,7 +339,6 @@ static const struct pinmux_ops spear_pinmux_ops = { .get_function_name = spear_pinctrl_get_func_name, .get_function_groups = spear_pinctrl_get_func_groups, .enable = spear_pinctrl_enable, - .disable = spear_pinctrl_disable, .gpio_request_enable = gpio_request_enable, .gpio_disable_free = gpio_disable_free, }; diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index 2c61281bebd7..8c976c21eeee 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -141,17 +141,6 @@ static int wmt_pmx_enable(struct pinctrl_dev *pctldev, return wmt_set_pinmux(data, func_selector, pinnum); } -static void wmt_pmx_disable(struct pinctrl_dev *pctldev, - unsigned func_selector, - unsigned group_selector) -{ - struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); - u32 pinnum = data->pins[group_selector].number; - - /* disable by setting GPIO_IN */ - wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, pinnum); -} - static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) @@ -180,7 +169,6 @@ static struct pinmux_ops wmt_pinmux_ops = { .get_function_name = wmt_pmx_get_function_name, .get_function_groups = wmt_pmx_get_function_groups, .enable = wmt_pmx_enable, - .disable = wmt_pmx_disable, .gpio_disable_free = wmt_pmx_gpio_disable_free, .gpio_set_direction = wmt_pmx_gpio_set_direction, }; -- cgit v1.2.3 From fc72c923e50d5c0575faa5f6379bd55b900ed85a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Mon, 16 Jun 2014 01:36:05 +0200 Subject: pinctrl: rockchip: generalize bank-quirks Upcoming Rockchip SoCs have additional quirks to handle. Currently they would be handled by giving the bank a special compatible property. But the nature of the new quirks would require a lot of them. Also as we want to move to the separate dw_gpio driver in the future, these bank-definitions should be extended at all. Describing the bank quirks this way also enables us to deprecate the special bank compatible string for bank0 on rk3188 and simplify the handling code. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 58 +++++++++++++++++++++++++------------- 1 file changed, 39 insertions(+), 19 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 51f67a6eadcb..2f5ba046232e 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -64,9 +64,16 @@ enum rockchip_pinctrl_type { RK3188, }; -enum rockchip_pin_bank_type { - COMMON_BANK, - RK3188_BANK0, +/** + * Encode variants of iomux registers into a type variable + */ +#define IOMUX_GPIO_ONLY BIT(0) + +/** + * @type: iomux variant using IOMUX_* constants + */ +struct rockchip_iomux { + int type; }; /** @@ -78,6 +85,7 @@ enum rockchip_pin_bank_type { * @nr_pins: number of pins in this bank * @name: name of the bank * @bank_num: number of the bank, to account for holes + * @iomux: array describing the 4 iomux sources of the bank * @valid: are all necessary informations present * @of_node: dt node of this bank * @drvdata: common pinctrl basedata @@ -95,7 +103,7 @@ struct rockchip_pin_bank { u8 nr_pins; char *name; u8 bank_num; - enum rockchip_pin_bank_type bank_type; + struct rockchip_iomux iomux[4]; bool valid; struct device_node *of_node; struct rockchip_pinctrl *drvdata; @@ -113,6 +121,19 @@ struct rockchip_pin_bank { .name = label, \ } +#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, }, \ + { .type = iom1, }, \ + { .type = iom2, }, \ + { .type = iom3, }, \ + }, \ + } + /** */ struct rockchip_pin_ctrl { @@ -343,17 +364,21 @@ static const struct pinctrl_ops rockchip_pctrl_ops = { static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) { struct rockchip_pinctrl *info = bank->drvdata; + int iomux_num = (pin / 8); unsigned int val; int reg, ret; u8 bit; - if (bank->bank_type == RK3188_BANK0 && pin < 16) + if (iomux_num > 3) + return -EINVAL; + + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) return RK_FUNC_GPIO; /* get basic quadrupel of mux registers and the correct reg inside */ reg = info->ctrl->mux_offset; reg += bank->bank_num * 0x10; - reg += (pin / 8) * 4; + reg += iomux_num * 4; bit = (pin % 8) * 2; ret = regmap_read(info->regmap_base, reg, &val); @@ -379,16 +404,16 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; + int iomux_num = (pin / 8); int reg, ret; unsigned long flags; u8 bit; u32 data; - /* - * The first 16 pins of rk3188_bank0 are always gpios and do not have - * a mux register at all. - */ - if (bank->bank_type == RK3188_BANK0 && pin < 16) { + if (iomux_num > 3) + return -EINVAL; + + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { if (mux != RK_FUNC_GPIO) { dev_err(info->dev, "pin %d only supports a gpio mux\n", pin); @@ -404,7 +429,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) /* get basic quadrupel of mux registers and the correct reg inside */ reg = info->ctrl->mux_offset; reg += bank->bank_num * 0x10; - reg += (pin / 8) * 4; + reg += iomux_num * 4; bit = (pin % 8) * 2; spin_lock_irqsave(&bank->slock, flags); @@ -449,7 +474,7 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, struct rockchip_pinctrl *info = bank->drvdata; /* The first 12 pins of the first bank are located elsewhere */ - if (bank->bank_type == RK3188_BANK0 && pin_num < 12) { + if (bank->bank_num == 0 && pin_num < 12) { *regmap = info->regmap_pmu ? info->regmap_pmu : bank->regmap_pull; *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; @@ -1448,8 +1473,6 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, "rockchip,rk3188-gpio-bank0")) { struct device_node *node; - bank->bank_type = RK3188_BANK0; - node = of_parse_phandle(bank->of_node->parent, "rockchip,pmu", 0); if (!node) { @@ -1469,9 +1492,6 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, base, &rockchip_regmap_config); } - - } else { - bank->bank_type = COMMON_BANK; } bank->irq = irq_of_parse_and_map(bank->of_node, 0); @@ -1664,7 +1684,7 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { }; static struct rockchip_pin_bank rk3188_pin_banks[] = { - PIN_BANK(0, 32, "gpio0"), + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), PIN_BANK(1, 32, "gpio1"), PIN_BANK(2, 32, "gpio2"), PIN_BANK(3, 32, "gpio3"), -- cgit v1.2.3 From 6bc0d121a95b31b0962bf6a3f89099059bde409e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Mon, 16 Jun 2014 01:36:33 +0200 Subject: pinctrl: rockchip: precalculate iomux offsets An upcoming SoC introduces an interesting quirk to iomux handling making the calculation of the iomux register-offset harder. To keep the complexity down when getting/setting the mux, precalculate the actual register offset at probe-time. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 56 ++++++++++++++++++++++++++++++-------- 1 file changed, 45 insertions(+), 11 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 2f5ba046232e..202ac82082d2 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -71,9 +71,13 @@ enum rockchip_pinctrl_type { /** * @type: iomux variant using IOMUX_* constants + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset + * to a new value for autocalculating the following iomux registers. */ struct rockchip_iomux { int type; + int offset; }; /** @@ -119,6 +123,12 @@ struct rockchip_pin_bank { .bank_num = id, \ .nr_pins = pins, \ .name = label, \ + .iomux = { \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + }, \ } #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ @@ -127,10 +137,10 @@ struct rockchip_pin_bank { .nr_pins = pins, \ .name = label, \ .iomux = { \ - { .type = iom0, }, \ - { .type = iom1, }, \ - { .type = iom2, }, \ - { .type = iom3, }, \ + { .type = iom0, .offset = -1 }, \ + { .type = iom1, .offset = -1 }, \ + { .type = iom2, .offset = -1 }, \ + { .type = iom3, .offset = -1 }, \ }, \ } @@ -376,9 +386,7 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) return RK_FUNC_GPIO; /* get basic quadrupel of mux registers and the correct reg inside */ - reg = info->ctrl->mux_offset; - reg += bank->bank_num * 0x10; - reg += iomux_num * 4; + reg = bank->iomux[iomux_num].offset; bit = (pin % 8) * 2; ret = regmap_read(info->regmap_base, reg, &val); @@ -427,9 +435,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) bank->bank_num, pin, mux); /* get basic quadrupel of mux registers and the correct reg inside */ - reg = info->ctrl->mux_offset; - reg += bank->bank_num * 0x10; - reg += iomux_num * 4; + reg = bank->iomux[iomux_num].offset; bit = (pin % 8) * 2; spin_lock_irqsave(&bank->slock, flags); @@ -1515,7 +1521,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( struct device_node *np; struct rockchip_pin_ctrl *ctrl; struct rockchip_pin_bank *bank; - int i; + int grf_offs, i, j; match = of_match_node(rockchip_pinctrl_dt_match, node); ctrl = (struct rockchip_pin_ctrl *)match->data; @@ -1537,12 +1543,40 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( } } + grf_offs = ctrl->mux_offset; bank = ctrl->pin_banks; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + int bank_pins = 0; + spin_lock_init(&bank->slock); bank->drvdata = d; bank->pin_base = ctrl->nr_pins; ctrl->nr_pins += bank->nr_pins; + + /* calculate iomux offsets */ + for (j = 0; j < 4; j++) { + struct rockchip_iomux *iom = &bank->iomux[j]; + + if (bank_pins >= bank->nr_pins) + break; + + /* preset offset value, set new start value */ + if (iom->offset >= 0) { + grf_offs = iom->offset; + } else { /* set current offset */ + iom->offset = grf_offs; + } + + dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", + i, j, iom->offset); + + /* + * Increase offset according to iomux width. + */ + grf_offs += 4; + + bank_pins += 8; + } } return ctrl; -- cgit v1.2.3 From 03716e1dd01b0e761a7db8f82c81f11746a0ef97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Mon, 16 Jun 2014 01:36:57 +0200 Subject: pinctrl: rockchip: add support for 4bit wide iomux settings In the upcoming rk3288 SoC some iomux settings are 4bit wide instead of the regular 2bit. Therefore add a flag to mark iomuxes as such and adapt the mux-access as well as the offset calculation accordingly. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 202ac82082d2..07c06e7171e7 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -68,6 +68,7 @@ enum rockchip_pinctrl_type { * Encode variants of iomux registers into a type variable */ #define IOMUX_GPIO_ONLY BIT(0) +#define IOMUX_WIDTH_4BIT BIT(1) /** * @type: iomux variant using IOMUX_* constants @@ -376,7 +377,7 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) struct rockchip_pinctrl *info = bank->drvdata; int iomux_num = (pin / 8); unsigned int val; - int reg, ret; + int reg, ret, mask; u8 bit; if (iomux_num > 3) @@ -386,14 +387,21 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) return RK_FUNC_GPIO; /* get basic quadrupel of mux registers and the correct reg inside */ + mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; reg = bank->iomux[iomux_num].offset; - bit = (pin % 8) * 2; + if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + } else { + bit = (pin % 8) * 2; + } ret = regmap_read(info->regmap_base, reg, &val); if (ret) return ret; - return ((val >> bit) & 3); + return ((val >> bit) & mask); } /* @@ -413,7 +421,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; int iomux_num = (pin / 8); - int reg, ret; + int reg, ret, mask; unsigned long flags; u8 bit; u32 data; @@ -435,13 +443,20 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) bank->bank_num, pin, mux); /* get basic quadrupel of mux registers and the correct reg inside */ + mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; reg = bank->iomux[iomux_num].offset; - bit = (pin % 8) * 2; + if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + } else { + bit = (pin % 8) * 2; + } spin_lock_irqsave(&bank->slock, flags); - data = (3 << (bit + 16)); - data |= (mux & 3) << bit; + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; ret = regmap_write(info->regmap_base, reg, data); spin_unlock_irqrestore(&bank->slock, flags); @@ -1556,6 +1571,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( /* calculate iomux offsets */ for (j = 0; j < 4; j++) { struct rockchip_iomux *iom = &bank->iomux[j]; + int inc; if (bank_pins >= bank->nr_pins) break; @@ -1572,8 +1588,10 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( /* * Increase offset according to iomux width. + * 4bit iomux'es are spread over two registers. */ - grf_offs += 4; + inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; + grf_offs += inc; bank_pins += 8; } -- cgit v1.2.3 From 95ec8ae4498e99efaf319700e3e7b40fb4a4afd6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Mon, 16 Jun 2014 01:37:23 +0200 Subject: pinctrl: rockchip: enable iomuxes from pmu space The upcoming rk3288 moves some iomux settings to the pmu register space. Therefore add a flag for this and adapt the mux functions accordingly. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 42 +++++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 12 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 07c06e7171e7..cfdeb81035b6 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -69,6 +69,7 @@ enum rockchip_pinctrl_type { */ #define IOMUX_GPIO_ONLY BIT(0) #define IOMUX_WIDTH_4BIT BIT(1) +#define IOMUX_SOURCE_PMU BIT(2) /** * @type: iomux variant using IOMUX_* constants @@ -153,7 +154,8 @@ struct rockchip_pin_ctrl { u32 nr_pins; char *label; enum rockchip_pinctrl_type type; - int mux_offset; + int grf_mux_offset; + int pmu_mux_offset; void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); @@ -376,6 +378,7 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) { struct rockchip_pinctrl *info = bank->drvdata; int iomux_num = (pin / 8); + struct regmap *regmap; unsigned int val; int reg, ret, mask; u8 bit; @@ -386,6 +389,9 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) return RK_FUNC_GPIO; + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? info->regmap_pmu : info->regmap_base; + /* get basic quadrupel of mux registers and the correct reg inside */ mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; reg = bank->iomux[iomux_num].offset; @@ -397,7 +403,7 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) bit = (pin % 8) * 2; } - ret = regmap_read(info->regmap_base, reg, &val); + ret = regmap_read(regmap, reg, &val); if (ret) return ret; @@ -421,6 +427,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; int iomux_num = (pin / 8); + struct regmap *regmap; int reg, ret, mask; unsigned long flags; u8 bit; @@ -442,6 +449,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? info->regmap_pmu : info->regmap_base; + /* get basic quadrupel of mux registers and the correct reg inside */ mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; reg = bank->iomux[iomux_num].offset; @@ -457,7 +467,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) data = (mask << (bit + 16)); data |= (mux & mask) << bit; - ret = regmap_write(info->regmap_base, reg, data); + ret = regmap_write(regmap, reg, data); spin_unlock_irqrestore(&bank->slock, flags); @@ -1536,7 +1546,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( struct device_node *np; struct rockchip_pin_ctrl *ctrl; struct rockchip_pin_bank *bank; - int grf_offs, i, j; + int grf_offs, pmu_offs, i, j; match = of_match_node(rockchip_pinctrl_dt_match, node); ctrl = (struct rockchip_pin_ctrl *)match->data; @@ -1558,7 +1568,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( } } - grf_offs = ctrl->mux_offset; + grf_offs = ctrl->grf_mux_offset; + pmu_offs = ctrl->pmu_mux_offset; bank = ctrl->pin_banks; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0; @@ -1578,9 +1589,13 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( /* preset offset value, set new start value */ if (iom->offset >= 0) { - grf_offs = iom->offset; + if (iom->type & IOMUX_SOURCE_PMU) + pmu_offs = iom->offset; + else + grf_offs = iom->offset; } else { /* set current offset */ - iom->offset = grf_offs; + iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? + pmu_offs : grf_offs; } dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", @@ -1591,7 +1606,10 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( * 4bit iomux'es are spread over two registers. */ inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; - grf_offs += inc; + if (iom->type & IOMUX_SOURCE_PMU) + pmu_offs += inc; + else + grf_offs += inc; bank_pins += 8; } @@ -1698,7 +1716,7 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = { .nr_banks = ARRAY_SIZE(rk2928_pin_banks), .label = "RK2928-GPIO", .type = RK2928, - .mux_offset = 0xa8, + .grf_mux_offset = 0xa8, .pull_calc_reg = rk2928_calc_pull_reg_and_bit, }; @@ -1716,7 +1734,7 @@ static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), .label = "RK3066a-GPIO", .type = RK2928, - .mux_offset = 0xa8, + .grf_mux_offset = 0xa8, .pull_calc_reg = rk2928_calc_pull_reg_and_bit, }; @@ -1732,7 +1750,7 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), .label = "RK3066b-GPIO", .type = RK3066B, - .mux_offset = 0x60, + .grf_mux_offset = 0x60, }; static struct rockchip_pin_bank rk3188_pin_banks[] = { @@ -1747,7 +1765,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .nr_banks = ARRAY_SIZE(rk3188_pin_banks), .label = "RK3188-GPIO", .type = RK3188, - .mux_offset = 0x60, + .grf_mux_offset = 0x60, .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; -- cgit v1.2.3 From 62f49226b03b6464b6fa71ad926932f9b3c8232a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Mon, 16 Jun 2014 01:37:49 +0200 Subject: pinctrl: rockchip: support unrouted iomuxes per bank On the upcoming RK3288 SoC contain some unrouted pins in their banks. So while for example pin8 of bank5 stays pin8 with all its settings (register offset etc), pins 0 to 7 are not routed outside the SoC at all. Therefore add a flag to mark these unrouted iomuxes to prevent people from using them. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index cfdeb81035b6..65b73217c2c3 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -70,6 +70,7 @@ enum rockchip_pinctrl_type { #define IOMUX_GPIO_ONLY BIT(0) #define IOMUX_WIDTH_4BIT BIT(1) #define IOMUX_SOURCE_PMU BIT(2) +#define IOMUX_UNROUTED BIT(3) /** * @type: iomux variant using IOMUX_* constants @@ -386,6 +387,11 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) if (iomux_num > 3) return -EINVAL; + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { + dev_err(info->dev, "pin %d is unrouted\n", pin); + return -EINVAL; + } + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) return RK_FUNC_GPIO; @@ -436,6 +442,11 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (iomux_num > 3) return -EINVAL; + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { + dev_err(info->dev, "pin %d is unrouted\n", pin); + return -EINVAL; + } + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { if (mux != RK_FUNC_GPIO) { dev_err(info->dev, -- cgit v1.2.3 From 304f077d4c07d315b9325cb101fc47ba2ffc5466 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Mon, 16 Jun 2014 01:38:14 +0200 Subject: pinctrl: rockchip: add support for rk3288 pin-controller The pin-controller of the new RK3288 contains all the quirks just added in the previous patches. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 73 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 65b73217c2c3..192aaee8de07 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -543,6 +543,35 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, } } +#define RK3288_PULL_OFFSET 0x140 +static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3188_PULL_PMU_OFFSET; + + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3188_PULL_PINS_PER_REG; + *bit *= RK3188_PULL_BITS_PER_PIN; + } else { + *regmap = info->regmap_base; + *reg = RK3288_PULL_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; + } +} + static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; @@ -1780,6 +1809,48 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; +static struct rockchip_pin_bank rk3288_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_UNROUTED + ), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, + IOMUX_UNROUTED, + IOMUX_UNROUTED, + 0 + ), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, + 0 + ), + PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, + 0, + 0, + IOMUX_UNROUTED + ), + PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), + PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, + 0, + IOMUX_WIDTH_4BIT, + IOMUX_UNROUTED + ), + PIN_BANK(8, 16, "gpio8"), +}; + +static struct rockchip_pin_ctrl rk3288_pin_ctrl = { + .pin_banks = rk3288_pin_banks, + .nr_banks = ARRAY_SIZE(rk3288_pin_banks), + .label = "RK3288-GPIO", + .type = RK3188, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x84, + .pull_calc_reg = rk3288_calc_pull_reg_and_bit, +}; + static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk2928-pinctrl", .data = (void *)&rk2928_pin_ctrl }, @@ -1789,6 +1860,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3066b_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", .data = (void *)&rk3188_pin_ctrl }, + { .compatible = "rockchip,rk3288-pinctrl", + .data = (void *)&rk3288_pin_ctrl }, {}, }; MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); -- cgit v1.2.3 From c01607c7daa59ca9f9cd33c2421ccae98239ab54 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 1 Jul 2014 23:25:08 +0800 Subject: pinctrl: sunxi: Remove gpio_out function from sun5i-a13 PG0/1/2 pins The A13 user manual states pins PG0/1/2 only have GPIO input and interrupt functions. Remove the gpio_out functions for these pins. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c index 29c734a60b51..e47c33dbae3a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c @@ -330,15 +330,12 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), -- cgit v1.2.3 From d9ff081d9123af59144d3617668c8274b2cc3254 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sun, 29 Jun 2014 15:58:19 +0200 Subject: pinctrl: sunxi: Remove PINCTRL_SUNXI The PINCTRL_SUNXI configuration was kept only to deal with the introduction of per-machine symbols and the various pintrl drivers through different tree. Now that it's not useful anymore, we can just remove it. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/Kconfig | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 73e0a305ea13..4cbf458579d5 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -1,36 +1,33 @@ if ARCH_SUNXI -config PINCTRL_SUNXI - bool - config PINCTRL_SUNXI_COMMON bool select PINMUX select GENERIC_PINCONF config PINCTRL_SUN4I_A10 - def_bool PINCTRL_SUNXI || MACH_SUN4I + def_bool MACH_SUN4I select PINCTRL_SUNXI_COMMON config PINCTRL_SUN5I_A10S - def_bool PINCTRL_SUNXI || MACH_SUN5I + def_bool MACH_SUN5I select PINCTRL_SUNXI_COMMON config PINCTRL_SUN5I_A13 - def_bool PINCTRL_SUNXI || MACH_SUN5I + def_bool MACH_SUN5I select PINCTRL_SUNXI_COMMON config PINCTRL_SUN6I_A31 - def_bool PINCTRL_SUNXI || MACH_SUN6I + def_bool MACH_SUN6I select PINCTRL_SUNXI_COMMON config PINCTRL_SUN6I_A31_R - def_bool PINCTRL_SUNXI || MACH_SUN6I + def_bool MACH_SUN6I depends on RESET_CONTROLLER select PINCTRL_SUNXI_COMMON config PINCTRL_SUN7I_A20 - def_bool PINCTRL_SUNXI || MACH_SUN7I + def_bool MACH_SUN7I select PINCTRL_SUNXI_COMMON endif -- cgit v1.2.3 From 4c821d1c934c741b995d37cab206b7fca5ffd6a5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 17 Jun 2014 22:52:51 +0800 Subject: pinctrl: sunxi: Add A23 PIO controller support The A23 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c | 593 ++++++++++++++++++++++++++++++ 3 files changed, 598 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 4cbf458579d5..7e6a2684949a 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -30,4 +30,8 @@ config PINCTRL_SUN7I_A20 def_bool MACH_SUN7I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_A23 + def_bool MACH_SUN8I + select PINCTRL_SUNXI_COMMON + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 0f4461cbe11d..850cd5014dd8 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o +obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c new file mode 100644 index 000000000000..ac71e8c5901b --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c @@ -0,0 +1,593 @@ +/* + * Allwinner A23 SoCs pinctrl driver. + * + * Copyright (C) 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_a23_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PA_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag"), /* CKO */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PA_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag"), /* DOO */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PA_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag"), /* DIO */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PA_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart4"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PA_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart4"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PA_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart4"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PA_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart4"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PA_EINT7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PB_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PB_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PB_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PB_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PB_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PB_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PB_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s0"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PB_EINT7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "uart3")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "uart3")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "uart1")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "uart1")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "uart1")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "i2s1")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "i2s1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ + SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ + SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* PCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 13)), /* PG_EINT13 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm1")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS */ + SUNXI_FUNCTION(0x3, "uart3")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* DIN */ + SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ +}; + +static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = { + .pins = sun8i_a23_pins, + .npins = ARRAY_SIZE(sun8i_a23_pins), + .irq_banks = 3, +}; + +static int sun8i_a23_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_a23_pinctrl_data); +} + +static struct of_device_id sun8i_a23_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-a23-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun8i_a23_pinctrl_match); + +static struct platform_driver sun8i_a23_pinctrl_driver = { + .probe = sun8i_a23_pinctrl_probe, + .driver = { + .name = "sun8i-a23-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun8i_a23_pinctrl_match, + }, +}; +module_platform_driver(sun8i_a23_pinctrl_driver); + +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_AUTHOR("Maxime Ripard Date: Tue, 17 Jun 2014 22:52:52 +0800 Subject: pinctrl: sunxi: Add A23 R_PIO controller support The A23 has a R_PIO pin controller, similar to the one found on the A31 SoC. Add support for the pins controlled by the R_PIO controller. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 142 ++++++++++++++++++++++++++++ 3 files changed, 148 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 7e6a2684949a..a5e10f777ed2 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -34,4 +34,9 @@ config PINCTRL_SUN8I_A23 def_bool MACH_SUN8I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_A23_R + def_bool MACH_SUN8I + depends on RESET_CONTROLLER + select PINCTRL_SUNXI_COMMON + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 850cd5014dd8..e797efb02901 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o +obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c new file mode 100644 index 000000000000..90f3b3a7c51e --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -0,0 +1,142 @@ +/* + * Allwinner A23 SoCs special pins pinctrl driver. + * + * Copyright (C) 2014 Chen-Yu Tsai + * Chen-Yu Tsai + * + * Copyright (C) 2014 Boris Brezillon + * Boris Brezillon + * + * Copyright (C) 2014 Maxime Ripard + * Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_a23_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */ + SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */ + SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PL_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PL_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PL_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PL_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PL_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PL_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 8)), /* PL_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 9)), /* PL_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_pwm"), + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 10)), /* PL_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 11)), /* PL_EINT11 */ +}; + +static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = { + .pins = sun8i_a23_r_pins, + .npins = ARRAY_SIZE(sun8i_a23_r_pins), + .pin_base = PL_BASE, + .irq_banks = 1, +}; + +static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev) +{ + struct reset_control *rstc; + int ret; + + rstc = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(rstc)) { + dev_err(&pdev->dev, "Reset controller missing\n"); + return PTR_ERR(rstc); + } + + ret = reset_control_deassert(rstc); + if (ret) + return ret; + + ret = sunxi_pinctrl_init(pdev, + &sun8i_a23_r_pinctrl_data); + + if (ret) + reset_control_assert(rstc); + + return ret; +} + +static struct of_device_id sun8i_a23_r_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-a23-r-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun8i_a23_r_pinctrl_match); + +static struct platform_driver sun8i_a23_r_pinctrl_driver = { + .probe = sun8i_a23_r_pinctrl_probe, + .driver = { + .name = "sun8i-a23-r-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun8i_a23_r_pinctrl_match, + }, +}; +module_platform_driver(sun8i_a23_r_pinctrl_driver); + +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_AUTHOR("Boris Brezillon Date: Tue, 17 Jun 2014 23:49:11 -0500 Subject: pinctrl: qcom: Add BUS_HOLD pin bias This patch adds the BUS_HOLD (Keeper) bias option for pins. Signed-off-by: Andy Gross Acked-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-msm.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c index bdfaba4430f2..43d47b7cff92 100644 --- a/drivers/pinctrl/pinctrl-msm.c +++ b/drivers/pinctrl/pinctrl-msm.c @@ -181,6 +181,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_BUS_HOLD: case PIN_CONFIG_BIAS_PULL_UP: *bit = g->pull_bit; *mask = 3; @@ -218,6 +219,7 @@ static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, #define MSM_NO_PULL 0 #define MSM_PULL_DOWN 1 +#define MSM_KEEPER 2 #define MSM_PULL_UP 3 static unsigned msm_regval_to_drive(u32 val) @@ -255,6 +257,9 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_BIAS_PULL_DOWN: arg = arg == MSM_PULL_DOWN; break; + case PIN_CONFIG_BIAS_BUS_HOLD: + arg = arg == MSM_KEEPER; + break; case PIN_CONFIG_BIAS_PULL_UP: arg = arg == MSM_PULL_UP; break; @@ -314,6 +319,9 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_BIAS_PULL_DOWN: arg = MSM_PULL_DOWN; break; + case PIN_CONFIG_BIAS_BUS_HOLD: + arg = MSM_KEEPER; + break; case PIN_CONFIG_BIAS_PULL_UP: arg = MSM_PULL_UP; break; -- cgit v1.2.3 From 776667a8092d3c28c357191db595494349e83919 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 23 Jun 2014 17:08:18 +0530 Subject: pinctrl: bcm281xx: Staticize bcm281xx_pinctrl_probe bcm281xx_pinctrl_probe is local to this file. Make it static. Signed-off-by: Sachin Kamat Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-bcm281xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/pinctrl-bcm281xx.c index 3bed792b2c03..c5ca9e633fff 100644 --- a/drivers/pinctrl/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/pinctrl-bcm281xx.c @@ -1396,7 +1396,7 @@ static struct pinctrl_desc bcm281xx_pinctrl_desc = { .owner = THIS_MODULE, }; -int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) +static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) { struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl; struct resource *res; -- cgit v1.2.3 From 8708ebca7464af80accd52c6e1a1cf882593a4ab Mon Sep 17 00:00:00 2001 From: David PARIS Date: Wed, 25 Jun 2014 17:49:04 +0200 Subject: pinctrl: st: add IRQCHIP_SKIP_SET_WAKE flag no .irq_set_wake API is available for pinctrl-st driver. Add the IRQCHIP_SKIP_SET_WAKE flag to inform irq handler not to call this API. Signed-off-by: David Paris Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index e1919cd43117..506561131d7f 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1448,6 +1448,7 @@ static struct irq_chip st_gpio_irqchip = { .irq_mask = st_gpio_irq_mask, .irq_unmask = st_gpio_irq_unmask, .irq_set_type = st_gpio_irq_set_type, + .flags = IRQCHIP_SKIP_SET_WAKE, }; static int st_gpiolib_register_bank(struct st_pinctrl *info, -- cgit v1.2.3 From ca7162add9dc0b361cbf51084591c64db37199d8 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 13:26:45 +0200 Subject: pinctrl: pinctrl-at91.c: Cleaning up if unsigned is less than zero Remove checking if a unsigned is less than zero This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index bd57ab514aa4..ec9744f33403 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -924,7 +924,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np, /* Initialise function */ func->name = np->name; func->ngroups = of_get_child_count(np); - if (func->ngroups <= 0) { + if (func->ngroups == 0) { dev_err(info->dev, "no groups defined\n"); return -EINVAL; } -- cgit v1.2.3 From 9eedfd688cb267d0fee06f68cbbddaf94423482e Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 13:28:16 +0200 Subject: pinctrl: pinctrl-imx.c: Cleaning up if unsigned is less than zero Remove checking if a unsigned is less than zero This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index a24448e5d399..946d594a64dd 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -515,7 +515,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, /* Initialise function */ func->name = np->name; func->num_groups = of_get_child_count(np); - if (func->num_groups <= 0) { + if (func->num_groups == 0) { dev_err(info->dev, "no groups defined in %s\n", np->full_name); return -EINVAL; } -- cgit v1.2.3 From 5aa498b95496204d3d9918b5d9287f0a4910a2a1 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 13:29:49 +0200 Subject: pinctrl: pinctrl-imx1-core.c: Cleaning up if unsigned is less than zero Remove checking if a unsigned is less than zero This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-imx1-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c index 815384b377b5..483420757c9f 100644 --- a/drivers/pinctrl/pinctrl-imx1-core.c +++ b/drivers/pinctrl/pinctrl-imx1-core.c @@ -526,7 +526,7 @@ static int imx1_pinctrl_parse_functions(struct device_node *np, /* Initialise function */ func->name = np->name; func->num_groups = of_get_child_count(np); - if (func->num_groups <= 0) + if (func->num_groups == 0) return -EINVAL; func->groups = devm_kzalloc(info->dev, -- cgit v1.2.3 From 8b0c107ce049ddaf0ca9d8cd4faac1cf5c1e9f20 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 13:32:49 +0200 Subject: pinctrl: pinctrl-st.c: Cleaning up if unsigned is less than zero Remove checking if a unsigned is less than zero This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Acked-by: Srinivas Kandagatla Acked-by: Maxime Coquelin Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 506561131d7f..1845870413ea 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1250,7 +1250,7 @@ static int st_pctl_parse_functions(struct device_node *np, func = &info->functions[index]; func->name = np->name; func->ngroups = of_get_child_count(np); - if (func->ngroups <= 0) { + if (func->ngroups == 0) { dev_err(info->dev, "No groups defined\n"); return -EINVAL; } -- cgit v1.2.3 From 445d20260bb0a7633f9d7d46a3afb0d9ee4109a7 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 15:41:31 +0200 Subject: pinctrl: pinctrl-at91.c: Cleaning up values that are never used Remove variable that are never used This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index ec9744f33403..af1ba4fc150d 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -772,9 +772,9 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { unsigned long config; - int ret, val, num_conf = 0; + int val, num_conf = 0; - ret = at91_pinconf_get(pctldev, pin_id, &config); + at91_pinconf_get(pctldev, pin_id, &config); DBG_SHOW_FLAG(MULTI_DRIVE); DBG_SHOW_FLAG(PULL_UP); -- cgit v1.2.3 From 849bfe0637fd45bf50aac3b12e7e56248c0b9031 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 15:43:01 +0200 Subject: pinctrl: pinctrl-single.c: Cleaning up values that are never used Remove variable that are never used This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index ff6a2bda52e5..efeb12ad7b19 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1683,11 +1683,10 @@ static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc) { struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); struct irq_chip *chip; - int res; chip = irq_get_chip(irq); chained_irq_enter(chip, desc); - res = pcs_irq_handle(pcs_soc); + pcs_irq_handle(pcs_soc); /* REVISIT: export and add handle_bad_irq(irq, desc)? */ chained_irq_exit(chip, desc); -- cgit v1.2.3 From 719e231bed5b1c638c7f48a657547562fc2064a3 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 18:57:14 +0200 Subject: pinctrl: pinctrl-adi2.c: Cleaning up wrong format string usage %d in format string used, but the type is unsigned int This was found using a static code analysis program called cppcheck Signed-off-by: Rickard Strandqvist Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-adi2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index b02ee4f882c0..46413e93d850 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -401,7 +401,7 @@ static int adi_gpio_irq_type(struct irq_data *d, unsigned int type) if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - snprintf(buf, 16, "gpio-irq%d", irq); + snprintf(buf, 16, "gpio-irq%u", irq); port_setup(port, d->hwirq, true); } else goto out; -- cgit v1.2.3 From bf4cef6c70258e1f771ebfe08558b77ad24700c2 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 18:58:46 +0200 Subject: pinctrl: pinctrl-single.c: Cleaning up wrong format string usage %d in format string used, but the type is unsigned int This was found using a static code analysis program called cppcheck Signed-off-by: Rickard Strandqvist Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index efeb12ad7b19..95dd9cf55cb3 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -780,7 +780,7 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, pin = &pcs->pins.pa[i]; pn = &pcs->names[i]; - sprintf(pn->name, "%lx.%d", + sprintf(pn->name, "%lx.%u", (unsigned long)pcs->res->start + offset, pin_pos); pin->name = pn->name; pin->number = i; -- cgit v1.2.3 From 1f978217a0c687a4cfed6ad698a3173826be4c3f Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 26 Jun 2014 15:44:32 +0200 Subject: pinctrl: pinctrl-st.c: Cleaning up values that are never used Remove variable that are never used This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Acked-by: Patrice Chotard Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 1845870413ea..d0fb44a095e9 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1172,9 +1172,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np, const __be32 *list; struct property *pp; struct st_pinconf *conf; - phandle phandle; struct device_node *pins; - u32 pin; int i = 0, npins = 0, nr_props; pins = of_get_child_by_name(np, "st,pins"); @@ -1212,8 +1210,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np, conf = &grp->pin_conf[i]; /* bank & offset */ - phandle = be32_to_cpup(list++); - pin = be32_to_cpup(list++); + be32_to_cpup(list++); + be32_to_cpup(list++); conf->pin = of_get_named_gpio(pins, pp->name, 0); conf->name = pp->name; grp->pins[i] = conf->pin; -- cgit v1.2.3 From ff998356b644ebe723127bd9eec6040b59a4a4f6 Mon Sep 17 00:00:00 2001 From: Eric Ernst Date: Thu, 12 Jun 2014 11:06:20 -0700 Subject: pinctrl: baytrail: Warn if direct IRQ GPIO set to output For Baytrail, you should never set a GPIO set to direct_irq to output mode. When direct_irq_en is set for a GPIO, it is tied directly to an APIC internally, and making the pad output does not make any sense. Assert a WARN() in the event this happens. Signed-off-by: Eric Ernst Acked-by: Mika Westerberg Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-baytrail.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c index 975572e2f260..701a646a3d10 100644 --- a/drivers/pinctrl/pinctrl-baytrail.c +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -44,6 +44,7 @@ /* BYT_CONF0_REG register bits */ #define BYT_IODEN BIT(31) +#define BYT_DIRECT_IRQ_EN BIT(27) #define BYT_TRIG_NEG BIT(26) #define BYT_TRIG_POS BIT(25) #define BYT_TRIG_LVL BIT(24) @@ -303,12 +304,22 @@ static int byt_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { struct byt_gpio *vg = to_byt_gpio(chip); + void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG); void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); unsigned long flags; u32 reg_val; spin_lock_irqsave(&vg->lock, flags); + /* + * Before making any direction modifications, do a check if gpio + * is set for direct IRQ. On baytrail, setting GPIO to output does + * not make sense, so let's at least warn the caller before they shoot + * themselves in the foot. + */ + WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, + "Potential Error: Setting GPIO with direct_irq_en to output"); + reg_val = readl(reg) | BYT_DIR_MASK; reg_val &= ~BYT_OUTPUT_EN; -- cgit v1.2.3 From 0e9386752758b74fd42fda7cbdd6ccb5cb31033c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 2 Jul 2014 00:58:16 +0400 Subject: sh-pfc: r8a7791: add CAN pin groups Add CAN0/1 data/clock pin groups to R8A7791 PFC driver. Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 167 +++++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 394b234488cc..576d41b459e9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1726,6 +1726,133 @@ static const unsigned int audio_clkout_mux[] = { AUDIO_CLKOUT_MARK, }; +/* - CAN -------------------------------------------------------------------- */ + +static const unsigned int can0_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), +}; + +static const unsigned int can0_data_mux[] = { + CAN0_TX_MARK, CAN0_RX_MARK, +}; + +static const unsigned int can0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3), +}; + +static const unsigned int can0_data_b_mux[] = { + CAN0_TX_B_MARK, CAN0_RX_B_MARK, +}; + +static const unsigned int can0_data_c_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), +}; + +static const unsigned int can0_data_c_mux[] = { + CAN0_TX_C_MARK, CAN0_RX_C_MARK, +}; + +static const unsigned int can0_data_d_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), +}; + +static const unsigned int can0_data_d_mux[] = { + CAN0_TX_D_MARK, CAN0_RX_D_MARK, +}; + +static const unsigned int can0_data_e_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28), +}; + +static const unsigned int can0_data_e_mux[] = { + CAN0_TX_E_MARK, CAN0_RX_E_MARK, +}; + +static const unsigned int can0_data_f_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), +}; + +static const unsigned int can0_data_f_mux[] = { + CAN0_TX_F_MARK, CAN0_RX_F_MARK, +}; + +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20), +}; + +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; + +static const unsigned int can1_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), +}; + +static const unsigned int can1_data_b_mux[] = { + CAN1_TX_B_MARK, CAN1_RX_B_MARK, +}; + +static const unsigned int can1_data_c_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19), +}; + +static const unsigned int can1_data_c_mux[] = { + CAN1_TX_C_MARK, CAN1_RX_C_MARK, +}; + +static const unsigned int can1_data_d_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31), +}; + +static const unsigned int can1_data_d_mux[] = { + CAN1_TX_D_MARK, CAN1_RX_D_MARK, +}; + +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(7, 2), +}; + +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +static const unsigned int can_clk_b_pins[] = { + /* CLK */ + RCAR_GP_PIN(5, 21), +}; + +static const unsigned int can_clk_b_mux[] = { + CAN_CLK_B_MARK, +}; + +static const unsigned int can_clk_c_pins[] = { + /* CLK */ + RCAR_GP_PIN(4, 30), +}; + +static const unsigned int can_clk_c_mux[] = { + CAN_CLK_C_MARK, +}; + +static const unsigned int can_clk_d_pins[] = { + /* CLK */ + RCAR_GP_PIN(7, 19), +}; + +static const unsigned int can_clk_d_mux[] = { + CAN_CLK_D_MARK, +}; /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -4055,6 +4182,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_b_b), SH_PFC_PIN_GROUP(audio_clk_c), SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can0_data_c), + SH_PFC_PIN_GROUP(can0_data_d), + SH_PFC_PIN_GROUP(can0_data_e), + SH_PFC_PIN_GROUP(can0_data_f), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can1_data_c), + SH_PFC_PIN_GROUP(can1_data_d), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(can_clk_b), + SH_PFC_PIN_GROUP(can_clk_c), + SH_PFC_PIN_GROUP(can_clk_d), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -4367,6 +4508,30 @@ static const char * const audio_clk_groups[] = { "audio_clkout", }; +static const char * const can0_groups[] = { + "can0_data_a", + "can0_data_b", + "can0_data_c", + "can0_data_d", + "can0_data_e", + "can0_data_f", + "can_clk_a", + "can_clk_b", + "can_clk_c", + "can_clk_d", +}; + +static const char * const can1_groups[] = { + "can1_data_a", + "can1_data_b", + "can1_data_c", + "can1_data_d", + "can_clk_a", + "can_clk_b", + "can_clk_c", + "can_clk_d", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4790,6 +4955,8 @@ static const char * const vin2_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), -- cgit v1.2.3 From 18c28caa17d7127e0391e100a919d9f6c156e974 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 2 Jul 2014 17:40:59 +0200 Subject: pinctrl: samsung: Decouple direction setting from pinctrl This patch makes the pinctrl-samsung driver configure GPIO direction on its own, without using the pinctrl_gpio_direction_*() "helpers". The rationale behind this change is as follows: - pinctrl-samsung does not need translation from GPIO namespace to pinctrl namespace to handle GPIO operations - GPIO chip and offset therein are enough to calculate necessary offsets and bit masks in constant time, - the pinctrl_gpio_direction_*() functions do not do anything useful other than translating the pin into pinctrl namespace and calling the .gpio_set_direction() from pinmux_ops of the controller, - the undesirable side effect of using those helpers is losing the ability to change GPIO direction in atomic context, because they explicitly use a mutex for synchronization, Results of this patch are: - fixed warnings about scheduling while atomic in code that needs to set GPIO direction in atomic context (e.g. interrupt handler), - reduced overhead of bitbanging drivers that use gpio_direction_*(), e.g. i2c-gpio. Signed-off-by: Tomasz Figa Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-samsung.c | 99 +++++++++++++++++---------------------- 1 file changed, 44 insertions(+), 55 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 089abde35d44..5740f93d658c 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -333,57 +333,12 @@ static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -/* - * The calls to gpio_direction_output() and gpio_direction_input() - * leads to this function call (via the pinctrl_gpio_direction_{input|output}() - * function called from the gpiolib interface). - */ -static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned offset, bool input) -{ - struct samsung_pin_bank_type *type; - struct samsung_pin_bank *bank; - struct samsung_pinctrl_drv_data *drvdata; - void __iomem *reg; - u32 data, pin_offset, mask, shift; - unsigned long flags; - - bank = gc_to_pin_bank(range->gc); - type = bank->type; - drvdata = pinctrl_dev_get_drvdata(pctldev); - - pin_offset = offset - bank->pin_base; - reg = drvdata->virt_base + bank->pctl_offset + - type->reg_offset[PINCFG_TYPE_FUNC]; - - mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; - shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; - if (shift >= 32) { - /* Some banks have two config registers */ - shift -= 32; - reg += 4; - } - - spin_lock_irqsave(&bank->slock, flags); - - data = readl(reg); - data &= ~(mask << shift); - if (!input) - data |= FUNC_OUTPUT << shift; - writel(data, reg); - - spin_unlock_irqrestore(&bank->slock, flags); - - return 0; -} - /* list of pinmux callbacks for the pinmux vertical in pinctrl core */ static const struct pinmux_ops samsung_pinmux_ops = { .get_functions_count = samsung_get_functions_count, .get_function_name = samsung_pinmux_get_fname, .get_function_groups = samsung_pinmux_get_groups, .enable = samsung_pinmux_enable, - .gpio_set_direction = samsung_pinmux_gpio_set_direction, }; /* set or get the pin config settings for a specified pin */ @@ -532,25 +487,59 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset) } /* - * gpiolib gpio_direction_input callback function. The setting of the pin - * mux function as 'gpio input' will be handled by the pinctrl susbsystem - * interface. + * The calls to gpio_direction_output() and gpio_direction_input() + * leads to this function call. */ +static int samsung_gpio_set_direction(struct gpio_chip *gc, + unsigned offset, bool input) +{ + struct samsung_pin_bank_type *type; + struct samsung_pin_bank *bank; + struct samsung_pinctrl_drv_data *drvdata; + void __iomem *reg; + u32 data, mask, shift; + unsigned long flags; + + bank = gc_to_pin_bank(gc); + type = bank->type; + drvdata = bank->drvdata; + + reg = drvdata->virt_base + bank->pctl_offset + + type->reg_offset[PINCFG_TYPE_FUNC]; + + mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; + shift = offset * type->fld_width[PINCFG_TYPE_FUNC]; + if (shift >= 32) { + /* Some banks have two config registers */ + shift -= 32; + reg += 4; + } + + spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg); + data &= ~(mask << shift); + if (!input) + data |= FUNC_OUTPUT << shift; + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); + + return 0; +} + +/* gpiolib gpio_direction_input callback function. */ static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { - return pinctrl_gpio_direction_input(gc->base + offset); + return samsung_gpio_set_direction(gc, offset, true); } -/* - * gpiolib gpio_direction_output callback function. The setting of the pin - * mux function as 'gpio output' will be handled by the pinctrl susbsystem - * interface. - */ +/* gpiolib gpio_direction_output callback function. */ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int value) { samsung_gpio_set(gc, offset, value); - return pinctrl_gpio_direction_output(gc->base + offset); + return samsung_gpio_set_direction(gc, offset, false); } /* -- cgit v1.2.3 From 6c6ce620e08f8764fd9884094afb274e6e85a47a Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 2 Jul 2014 17:41:00 +0200 Subject: pinctrl: samsung: Handle GPIO request and free using pinctrl helpers This patch adds .request() and .free() operations to gpio_chip of pinctrl-samsung driver, which call pinctrl request and free helpers to request and free pinctrl pin along with GPIO pin. Signed-off-by: Tomasz Figa Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-samsung.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 5740f93d658c..a09d8209ac2c 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -771,7 +771,8 @@ static int samsung_pinctrl_register(struct platform_device *pdev, pin_bank = &drvdata->ctrl->pin_banks[bank]; pin_bank->grange.name = pin_bank->name; pin_bank->grange.id = bank; - pin_bank->grange.pin_base = pin_bank->pin_base; + pin_bank->grange.pin_base = drvdata->ctrl->base + + pin_bank->pin_base; pin_bank->grange.base = pin_bank->gpio_chip.base; pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; pin_bank->grange.gc = &pin_bank->gpio_chip; @@ -781,7 +782,19 @@ static int samsung_pinctrl_register(struct platform_device *pdev, return 0; } +static int samsung_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void samsung_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + static const struct gpio_chip samsung_gpiolib_chip = { + .request = samsung_gpio_request, + .free = samsung_gpio_free, .set = samsung_gpio_set, .get = samsung_gpio_get, .direction_input = samsung_gpio_direction_input, -- cgit v1.2.3 From 2e4a4fda30fcf961f06573336db98cd460d3bf72 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 2 Jul 2014 17:41:01 +0200 Subject: pinctrl: exynos: Consolidate irq_chips of GPIO and WKUP EINTs Handling of irq_chip operations for GPIO and WKUP external interrupts is mostly the same, with the difference being offset of registers. However currently the driver has all the code duplicated for both EINT types, which is undesirable, because changes in irq_chip operations have to be done to both instances of the same code. This patch fixes this by creating exynos_irq_chip struct that has normal irq_chip struct embedded and contain differences between particular EINT types, which are three register offsets. One instance of code is removed and the new structure is used instead to fetch necessary data instead of samsung_pin_ctrl struct used previously. While at it, the patch removes Exynos-specific fields from aforementioned structure to improve layering of the driver. Signed-off-by: Tomasz Figa Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-exynos.c | 307 ++++++++------------------------------ drivers/pinctrl/pinctrl-samsung.h | 17 --- 2 files changed, 60 insertions(+), 264 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 9609c23834ce..003bfd874a61 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c @@ -33,6 +33,18 @@ #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" +struct exynos_irq_chip { + struct irq_chip chip; + + u32 eint_con; + u32 eint_mask; + u32 eint_pend; +}; + +static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) +{ + return container_of(chip, struct exynos_irq_chip, chip); +} static struct samsung_pin_bank_type bank_type_off = { .fld_width = { 4, 1, 2, 2, 2, 2, }, @@ -50,11 +62,13 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { { } }; -static void exynos_gpio_irq_mask(struct irq_data *irqd) +static void exynos_irq_mask(struct irq_data *irqd) { + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; + unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; unsigned long mask; unsigned long flags; @@ -67,20 +81,24 @@ static void exynos_gpio_irq_mask(struct irq_data *irqd) spin_unlock_irqrestore(&bank->slock, flags); } -static void exynos_gpio_irq_ack(struct irq_data *irqd) +static void exynos_irq_ack(struct irq_data *irqd) { + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; + unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; writel(1 << irqd->hwirq, d->virt_base + reg_pend); } -static void exynos_gpio_irq_unmask(struct irq_data *irqd) +static void exynos_irq_unmask(struct irq_data *irqd) { + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; + unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; unsigned long mask; unsigned long flags; @@ -93,7 +111,7 @@ static void exynos_gpio_irq_unmask(struct irq_data *irqd) * masked. */ if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) - exynos_gpio_irq_ack(irqd); + exynos_irq_ack(irqd); spin_lock_irqsave(&bank->slock, flags); @@ -104,16 +122,17 @@ static void exynos_gpio_irq_unmask(struct irq_data *irqd) spin_unlock_irqrestore(&bank->slock, flags); } -static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) +static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) { + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pin_bank_type *bank_type = bank->type; struct samsung_pinctrl_drv_data *d = bank->drvdata; - struct samsung_pin_ctrl *ctrl = d->ctrl; unsigned int pin = irqd->hwirq; unsigned int shift = EXYNOS_EINT_CON_LEN * pin; unsigned int con, trig_type; - unsigned long reg_con = ctrl->geint_con + bank->eint_offset; + unsigned long reg_con = our_chip->eint_con + bank->eint_offset; unsigned long flags; unsigned int mask; @@ -167,12 +186,17 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) /* * irq_chip for gpio interrupts. */ -static struct irq_chip exynos_gpio_irq_chip = { - .name = "exynos_gpio_irq_chip", - .irq_unmask = exynos_gpio_irq_unmask, - .irq_mask = exynos_gpio_irq_mask, - .irq_ack = exynos_gpio_irq_ack, - .irq_set_type = exynos_gpio_irq_set_type, +static struct exynos_irq_chip exynos_gpio_irq_chip = { + .chip = { + .name = "exynos_gpio_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + }, + .eint_con = EXYNOS_GPIO_ECON_OFFSET, + .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, }; static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, @@ -181,7 +205,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, struct samsung_pin_bank *b = h->host_data; irq_set_chip_data(virq, b); - irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, + irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip, handle_level_irq); set_irq_flags(virq, IRQF_VALID); return 0; @@ -202,7 +226,7 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) struct samsung_pin_bank *bank = ctrl->pin_banks; unsigned int svc, group, pin, virq; - svc = readl(d->virt_base + ctrl->svc); + svc = readl(d->virt_base + EXYNOS_SVC_OFFSET); group = EXYNOS_SVC_GROUP(svc); pin = svc & EXYNOS_SVC_NUM_MASK; @@ -279,119 +303,6 @@ err_domains: return ret; } -static void exynos_wkup_irq_mask(struct irq_data *irqd) -{ - struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = b->drvdata; - unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; - unsigned long mask; - unsigned long flags; - - spin_lock_irqsave(&b->slock, flags); - - mask = readl(d->virt_base + reg_mask); - mask |= 1 << irqd->hwirq; - writel(mask, d->virt_base + reg_mask); - - spin_unlock_irqrestore(&b->slock, flags); -} - -static void exynos_wkup_irq_ack(struct irq_data *irqd) -{ - struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = b->drvdata; - unsigned long pend = d->ctrl->weint_pend + b->eint_offset; - - writel(1 << irqd->hwirq, d->virt_base + pend); -} - -static void exynos_wkup_irq_unmask(struct irq_data *irqd) -{ - struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = b->drvdata; - unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; - unsigned long mask; - unsigned long flags; - - /* - * Ack level interrupts right before unmask - * - * If we don't do this we'll get a double-interrupt. Level triggered - * interrupts must not fire an interrupt if the level is not - * _currently_ active, even if it was active while the interrupt was - * masked. - */ - if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) - exynos_wkup_irq_ack(irqd); - - spin_lock_irqsave(&b->slock, flags); - - mask = readl(d->virt_base + reg_mask); - mask &= ~(1 << irqd->hwirq); - writel(mask, d->virt_base + reg_mask); - - spin_unlock_irqrestore(&b->slock, flags); -} - -static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pin_bank_type *bank_type = bank->type; - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned int pin = irqd->hwirq; - unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset; - unsigned long shift = EXYNOS_EINT_CON_LEN * pin; - unsigned long con, trig_type; - unsigned long flags; - unsigned int mask; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - trig_type = EXYNOS_EINT_EDGE_RISING; - break; - case IRQ_TYPE_EDGE_FALLING: - trig_type = EXYNOS_EINT_EDGE_FALLING; - break; - case IRQ_TYPE_EDGE_BOTH: - trig_type = EXYNOS_EINT_EDGE_BOTH; - break; - case IRQ_TYPE_LEVEL_HIGH: - trig_type = EXYNOS_EINT_LEVEL_HIGH; - break; - case IRQ_TYPE_LEVEL_LOW: - trig_type = EXYNOS_EINT_LEVEL_LOW; - break; - default: - pr_err("unsupported external interrupt type\n"); - return -EINVAL; - } - - if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(irqd->irq, handle_edge_irq); - else - __irq_set_handler_locked(irqd->irq, handle_level_irq); - - con = readl(d->virt_base + reg_con); - con &= ~(EXYNOS_EINT_CON_MASK << shift); - con |= trig_type << shift; - writel(con, d->virt_base + reg_con); - - reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; - shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; - mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; - - spin_lock_irqsave(&bank->slock, flags); - - con = readl(d->virt_base + reg_con); - con &= ~(mask << shift); - con |= EXYNOS_EINT_FUNC << shift; - writel(con, d->virt_base + reg_con); - - spin_unlock_irqrestore(&bank->slock, flags); - - return 0; -} - static u32 exynos_eint_wake_mask = 0xffffffff; u32 exynos_get_eint_wake_mask(void) @@ -417,13 +328,18 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) /* * irq_chip for wakeup interrupts */ -static struct irq_chip exynos_wkup_irq_chip = { - .name = "exynos_wkup_irq_chip", - .irq_unmask = exynos_wkup_irq_unmask, - .irq_mask = exynos_wkup_irq_mask, - .irq_ack = exynos_wkup_irq_ack, - .irq_set_type = exynos_wkup_irq_set_type, - .irq_set_wake = exynos_wkup_irq_set_wake, +static struct exynos_irq_chip exynos_wkup_irq_chip = { + .chip = { + .name = "exynos_wkup_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, + }, + .eint_con = EXYNOS_WKUP_ECON_OFFSET, + .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, }; /* interrupt handler for wakeup interrupts 0..15 */ @@ -464,7 +380,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) struct irq_chip *chip = irq_get_chip(irq); struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; - struct samsung_pin_ctrl *ctrl = d->ctrl; unsigned long pend; unsigned long mask; int i; @@ -473,8 +388,10 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) for (i = 0; i < eintd->nr_banks; ++i) { struct samsung_pin_bank *b = eintd->banks[i]; - pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset); - mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset); + pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET + + b->eint_offset); + mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET + + b->eint_offset); exynos_irq_demux_eint(pend & ~mask, b->irq_domain); } @@ -484,7 +401,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { - irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); + irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip, + handle_level_irq); irq_set_chip_data(virq, h->host_data); set_irq_flags(virq, IRQF_VALID); return 0; @@ -703,13 +621,6 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = { /* pin-controller instance 0 data */ .pin_banks = s5pv210_pin_bank, .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .weint_con = EXYNOS_WKUP_ECON_OFFSET, - .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, - .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, @@ -758,10 +669,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = { /* pin-controller instance 0 data */ .pin_banks = exynos3250_pin_banks0, .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, @@ -770,13 +677,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = { /* pin-controller instance 1 data */ .pin_banks = exynos3250_pin_banks1, .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .weint_con = EXYNOS_WKUP_ECON_OFFSET, - .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, - .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, @@ -843,10 +743,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { /* pin-controller instance 0 data */ .pin_banks = exynos4210_pin_banks0, .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, @@ -855,13 +751,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { /* pin-controller instance 1 data */ .pin_banks = exynos4210_pin_banks1, .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .weint_con = EXYNOS_WKUP_ECON_OFFSET, - .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, - .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, @@ -942,10 +831,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { /* pin-controller instance 0 data */ .pin_banks = exynos4x12_pin_banks0, .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, @@ -954,13 +839,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { /* pin-controller instance 1 data */ .pin_banks = exynos4x12_pin_banks1, .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .weint_con = EXYNOS_WKUP_ECON_OFFSET, - .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, - .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, @@ -970,10 +848,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { /* pin-controller instance 2 data */ .pin_banks = exynos4x12_pin_banks2, .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, @@ -982,10 +856,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { /* pin-controller instance 3 data */ .pin_banks = exynos4x12_pin_banks3, .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, @@ -1058,13 +928,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { /* pin-controller instance 0 data */ .pin_banks = exynos5250_pin_banks0, .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .weint_con = EXYNOS_WKUP_ECON_OFFSET, - .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, - .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, @@ -1074,10 +937,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { /* pin-controller instance 1 data */ .pin_banks = exynos5250_pin_banks1, .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, @@ -1086,10 +945,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { /* pin-controller instance 2 data */ .pin_banks = exynos5250_pin_banks2, .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, @@ -1098,10 +953,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { /* pin-controller instance 3 data */ .pin_banks = exynos5250_pin_banks3, .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, @@ -1158,13 +1009,6 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { /* pin-controller instance 0 data */ .pin_banks = exynos5260_pin_banks0, .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .weint_con = EXYNOS_WKUP_ECON_OFFSET, - .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, - .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, .label = "exynos5260-gpio-ctrl0", @@ -1172,20 +1016,12 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { /* pin-controller instance 1 data */ .pin_banks = exynos5260_pin_banks1, .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .label = "exynos5260-gpio-ctrl1", }, { /* pin-controller instance 2 data */ .pin_banks = exynos5260_pin_banks2, .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .label = "exynos5260-gpio-ctrl2", }, @@ -1256,13 +1092,6 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { /* pin-controller instance 0 data */ .pin_banks = exynos5420_pin_banks0, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .weint_con = EXYNOS_WKUP_ECON_OFFSET, - .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, - .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, .label = "exynos5420-gpio-ctrl0", @@ -1270,40 +1099,24 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { /* pin-controller instance 1 data */ .pin_banks = exynos5420_pin_banks1, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .label = "exynos5420-gpio-ctrl1", }, { /* pin-controller instance 2 data */ .pin_banks = exynos5420_pin_banks2, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .label = "exynos5420-gpio-ctrl2", }, { /* pin-controller instance 3 data */ .pin_banks = exynos5420_pin_banks3, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .label = "exynos5420-gpio-ctrl3", }, { /* pin-controller instance 4 data */ .pin_banks = exynos5420_pin_banks4, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), - .geint_con = EXYNOS_GPIO_ECON_OFFSET, - .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, - .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .label = "exynos5420-gpio-ctrl4", }, diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index b3e41fa5798b..e2dce4731a01 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -156,13 +156,6 @@ struct samsung_pin_bank { * @nr_banks: number of pin banks. * @base: starting system wide pin number. * @nr_pins: number of pins supported by the controller. - * @geint_con: offset of the ext-gpio controller registers. - * @geint_mask: offset of the ext-gpio interrupt mask registers. - * @geint_pend: offset of the ext-gpio interrupt pending registers. - * @weint_con: offset of the ext-wakeup controller registers. - * @weint_mask: offset of the ext-wakeup interrupt mask registers. - * @weint_pend: offset of the ext-wakeup interrupt pending registers. - * @svc: offset of the interrupt service register. * @eint_gpio_init: platform specific callback to setup the external gpio * interrupts for the controller. * @eint_wkup_init: platform specific callback to setup the external wakeup @@ -176,16 +169,6 @@ struct samsung_pin_ctrl { u32 base; u32 nr_pins; - u32 geint_con; - u32 geint_mask; - u32 geint_pend; - - u32 weint_con; - u32 weint_mask; - u32 weint_pend; - - u32 svc; - int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); void (*suspend)(struct samsung_pinctrl_drv_data *); -- cgit v1.2.3 From 9a2c1c3b91aae73ef7aa97cce1f88002d0a7cfe8 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 2 Jul 2014 17:41:03 +0200 Subject: pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes One of remaining limitations of current pinctrl-samsung driver was the inability to parse multiple pinmux/pinconf group nodes grouped inside a single device tree node. It made defining groups of pins for single purpose, but with different parameters very inconvenient. This patch implements Tegra-like support for grouping multiple pinctrl groups inside one device tree node, by completely changing the way pin groups and functions are parsed from device tree. The code creating pinctrl maps from DT nodes has been borrowed from pinctrl-tegra, while the initial creation of groups and functions has been completely rewritten with following assumptions: - each group consists of just one pin and does not depend on data from device tree, - each function is represented by a device tree child node of the pin controller, which in turn can contain multiple child nodes for pins that need to have different configuration values. Device Tree bindings are fully backwards compatible. New functionality can be used by defining a new pinctrl group consisting of several child nodes, as on following example: sd4_bus8: sd4-bus-width8 { part-1 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; samsung,pin-drv = <3>; }; part-2 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <4>; samsung,pin-pud = <4>; samsung,pin-drv = <3>; }; }; Tested on Exynos4210-Trats board and a custom Exynos4212-based one. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Reviewed-by: Stephen Warren Cc: devicetree@vger.kernel.org Cc: Rob Herring Cc: Mark Rutland Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-samsung.c | 613 ++++++++++++++++++++++---------------- drivers/pinctrl/pinctrl-samsung.h | 1 + 2 files changed, 362 insertions(+), 252 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index a09d8209ac2c..b7de66c3b51d 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -40,9 +40,9 @@ /* list of all possible config options supported */ static struct pin_config { - char *prop_cfg; - unsigned int cfg_type; -} pcfgs[] = { + const char *property; + enum pincfg_type param; +} cfg_params[] = { { "samsung,pin-pud", PINCFG_TYPE_PUD }, { "samsung,pin-drv", PINCFG_TYPE_DRV }, { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN }, @@ -59,163 +59,242 @@ static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) return container_of(gc, struct samsung_pin_bank, gpio_chip); } -/* check if the selector is a valid pin group selector */ static int samsung_get_group_count(struct pinctrl_dev *pctldev) { - struct samsung_pinctrl_drv_data *drvdata; + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); - drvdata = pinctrl_dev_get_drvdata(pctldev); - return drvdata->nr_groups; + return pmx->nr_groups; } -/* return the name of the group selected by the group selector */ static const char *samsung_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) + unsigned group) { - struct samsung_pinctrl_drv_data *drvdata; + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); - drvdata = pinctrl_dev_get_drvdata(pctldev); - return drvdata->pin_groups[selector].name; + return pmx->pin_groups[group].name; } -/* return the pin numbers associated with the specified group */ static int samsung_get_group_pins(struct pinctrl_dev *pctldev, - unsigned selector, const unsigned **pins, unsigned *num_pins) + unsigned group, + const unsigned **pins, + unsigned *num_pins) { - struct samsung_pinctrl_drv_data *drvdata; + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); + + *pins = pmx->pin_groups[group].pins; + *num_pins = pmx->pin_groups[group].num_pins; - drvdata = pinctrl_dev_get_drvdata(pctldev); - *pins = drvdata->pin_groups[selector].pins; - *num_pins = drvdata->pin_groups[selector].num_pins; return 0; } -/* create pinctrl_map entries by parsing device tree nodes */ -static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, struct pinctrl_map **maps, - unsigned *nmaps) +static int reserve_map(struct device *dev, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps, + unsigned reserve) { - struct device *dev = pctldev->dev; - struct pinctrl_map *map; - unsigned long *cfg = NULL; - char *gname, *fname; - int cfg_cnt = 0, map_cnt = 0, idx = 0; - - /* count the number of config options specfied in the node */ - for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) { - if (of_find_property(np, pcfgs[idx].prop_cfg, NULL)) - cfg_cnt++; - } + unsigned old_num = *reserved_maps; + unsigned new_num = *num_maps + reserve; + struct pinctrl_map *new_map; - /* - * Find out the number of map entries to create. All the config options - * can be accomadated into a single config map entry. - */ - if (cfg_cnt) - map_cnt = 1; - if (of_find_property(np, "samsung,pin-function", NULL)) - map_cnt++; - if (!map_cnt) { - dev_err(dev, "node %s does not have either config or function " - "configurations\n", np->name); - return -EINVAL; - } + if (old_num >= new_num) + return 0; - /* Allocate memory for pin-map entries */ - map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); - if (!map) { - dev_err(dev, "could not alloc memory for pin-maps\n"); + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(dev, "krealloc(map) failed\n"); return -ENOMEM; } - *nmaps = 0; - /* - * Allocate memory for pin group name. The pin group name is derived - * from the node name from which these map entries are be created. - */ - gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); - if (!gname) { - dev_err(dev, "failed to alloc memory for group name\n"); - goto free_map; + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function) +{ + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int add_map_configs(struct device *dev, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps, + const char *group, unsigned long *configs, + unsigned num_configs) +{ + unsigned long *dup_configs; + + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) { + dev_err(dev, "kmemdup(configs) failed\n"); + return -ENOMEM; } - sprintf(gname, "%s%s", np->name, GROUP_SUFFIX); - /* - * don't have config options? then skip over to creating function - * map entries. - */ - if (!cfg_cnt) - goto skip_cfgs; - - /* Allocate memory for config entries */ - cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); - if (!cfg) { - dev_err(dev, "failed to alloc memory for configs\n"); - goto free_gname; + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static int add_config(struct device *dev, unsigned long **configs, + unsigned *num_configs, unsigned long config) +{ + unsigned old_num = *num_configs; + unsigned new_num = old_num + 1; + unsigned long *new_configs; + + new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, + GFP_KERNEL); + if (!new_configs) { + dev_err(dev, "krealloc(configs) failed\n"); + return -ENOMEM; } - /* Prepare a list of config settings */ - for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { - u32 value; - if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value)) - cfg[cfg_cnt++] = - PINCFG_PACK(pcfgs[idx].cfg_type, value); + new_configs[old_num] = config; + + *configs = new_configs; + *num_configs = new_num; + + return 0; +} + +static void samsung_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +static int samsung_dt_subnode_to_map(struct samsung_pinctrl_drv_data *drvdata, + struct device *dev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + int ret, i; + u32 val; + unsigned long config; + unsigned long *configs = NULL; + unsigned num_configs = 0; + unsigned reserve; + struct property *prop; + const char *group; + bool has_func = false; + + ret = of_property_read_u32(np, "samsung,pin-function", &val); + if (!ret) + has_func = true; + + for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { + ret = of_property_read_u32(np, cfg_params[i].property, &val); + if (!ret) { + config = PINCFG_PACK(cfg_params[i].param, val); + ret = add_config(dev, &configs, &num_configs, config); + if (ret < 0) + goto exit; + /* EINVAL=missing, which is fine since it's optional */ + } else if (ret != -EINVAL) { + dev_err(dev, "could not parse property %s\n", + cfg_params[i].property); + } } - /* create the config map entry */ - map[*nmaps].data.configs.group_or_pin = gname; - map[*nmaps].data.configs.configs = cfg; - map[*nmaps].data.configs.num_configs = cfg_cnt; - map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - *nmaps += 1; - -skip_cfgs: - /* create the function map entry */ - if (of_find_property(np, "samsung,pin-function", NULL)) { - fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); - if (!fname) { - dev_err(dev, "failed to alloc memory for func name\n"); - goto free_cfg; + reserve = 0; + if (has_func) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "samsung,pins"); + if (ret < 0) { + dev_err(dev, "could not parse property samsung,pins\n"); + goto exit; + } + reserve *= ret; + + ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "samsung,pins", prop, group) { + if (has_func) { + ret = add_map_mux(map, reserved_maps, + num_maps, group, np->full_name); + if (ret < 0) + goto exit; } - sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX); - map[*nmaps].data.mux.group = gname; - map[*nmaps].data.mux.function = fname; - map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP; - *nmaps += 1; + if (num_configs) { + ret = add_map_configs(dev, map, reserved_maps, + num_maps, group, configs, + num_configs); + if (ret < 0) + goto exit; + } } - *maps = map; - return 0; + ret = 0; -free_cfg: - kfree(cfg); -free_gname: - kfree(gname); -free_map: - kfree(map); - return -ENOMEM; +exit: + kfree(configs); + return ret; } -/* free the memory allocated to hold the pin-map table */ -static void samsung_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) +static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) { - int idx; - - for (idx = 0; idx < num_maps; idx++) { - if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) { - kfree(map[idx].data.mux.function); - if (!idx) - kfree(map[idx].data.mux.group); - } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) { - kfree(map[idx].data.configs.configs); - if (!idx) - kfree(map[idx].data.configs.group_or_pin); + struct samsung_pinctrl_drv_data *drvdata; + unsigned reserved_maps; + struct device_node *np; + int ret; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + if (!of_get_child_count(np_config)) + return samsung_dt_subnode_to_map(drvdata, pctldev->dev, + np_config, map, + &reserved_maps, + num_maps); + + for_each_child_of_node(np_config, np) { + ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + samsung_dt_free_map(pctldev, *map, *num_maps); + return ret; } - }; + } - kfree(map); + return 0; } /* list of pinctrl callbacks for the pinctrl core */ @@ -286,43 +365,38 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, unsigned group, bool enable) { struct samsung_pinctrl_drv_data *drvdata; - const unsigned int *pins; + struct samsung_pin_bank_type *type; struct samsung_pin_bank *bank; void __iomem *reg; - u32 mask, shift, data, pin_offset, cnt; + u32 mask, shift, data, pin_offset; unsigned long flags; + const struct samsung_pmx_func *func; + const struct samsung_pin_group *grp; drvdata = pinctrl_dev_get_drvdata(pctldev); - pins = drvdata->pin_groups[group].pins; + func = &drvdata->pmx_functions[selector]; + grp = &drvdata->pin_groups[group]; - /* - * for each pin in the pin group selected, program the correspoding pin - * pin function number in the config register. - */ - for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) { - struct samsung_pin_bank_type *type; - - pin_to_reg_bank(drvdata, pins[cnt] - drvdata->ctrl->base, - ®, &pin_offset, &bank); - type = bank->type; - mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; - shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; - if (shift >= 32) { - /* Some banks have two config registers */ - shift -= 32; - reg += 4; - } + pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->ctrl->base, + ®, &pin_offset, &bank); + type = bank->type; + mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; + shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; + if (shift >= 32) { + /* Some banks have two config registers */ + shift -= 32; + reg += 4; + } - spin_lock_irqsave(&bank->slock, flags); + spin_lock_irqsave(&bank->slock, flags); - data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); - data &= ~(mask << shift); - if (enable) - data |= drvdata->pin_groups[group].func << shift; - writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); + data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); + data &= ~(mask << shift); + if (enable) + data |= func->val << shift; + writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); - spin_unlock_irqrestore(&bank->slock, flags); - } + spin_unlock_irqrestore(&bank->slock, flags); } /* enable a specified pinmux by writing to registers */ @@ -559,87 +633,115 @@ static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset) return (virq) ? : -ENXIO; } -/* - * Parse the pin names listed in the 'samsung,pins' property and convert it - * into a list of gpio numbers are create a pin group from it. - */ -static int samsung_pinctrl_parse_dt_pins(struct platform_device *pdev, - struct device_node *cfg_np, - struct pinctrl_desc *pctl, - unsigned int **pin_list, - unsigned int *npins) +static struct samsung_pin_group *samsung_pinctrl_create_groups( + struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + unsigned int *cnt) { - struct device *dev = &pdev->dev; - struct property *prop; - struct pinctrl_pin_desc const *pdesc = pctl->pins; - unsigned int idx = 0, cnt; - const char *pin_name; + struct pinctrl_desc *ctrldesc = &drvdata->pctl; + struct samsung_pin_group *groups, *grp; + const struct pinctrl_pin_desc *pdesc; + int i; + + groups = devm_kzalloc(dev, ctrldesc->npins * sizeof(*groups), + GFP_KERNEL); + if (!groups) + return ERR_PTR(-EINVAL); + grp = groups; + + pdesc = ctrldesc->pins; + for (i = 0; i < ctrldesc->npins; ++i, ++pdesc, ++grp) { + grp->name = pdesc->name; + grp->pins = &pdesc->number; + grp->num_pins = 1; + } + + *cnt = ctrldesc->npins; + return groups; +} - *npins = of_property_count_strings(cfg_np, "samsung,pins"); - if (IS_ERR_VALUE(*npins)) { - dev_err(dev, "invalid pin list in %s node", cfg_np->name); +static int samsung_pinctrl_create_function(struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + struct device_node *func_np, + struct samsung_pmx_func *func) +{ + int npins; + int ret; + int i; + + if (of_property_read_u32(func_np, "samsung,pin-function", &func->val)) + return 0; + + npins = of_property_count_strings(func_np, "samsung,pins"); + if (npins < 1) { + dev_err(dev, "invalid pin list in %s node", func_np->name); return -EINVAL; } - *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); - if (!*pin_list) { - dev_err(dev, "failed to allocate memory for pin list\n"); + func->name = func_np->full_name; + + func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL); + if (!func->groups) return -ENOMEM; - } - of_property_for_each_string(cfg_np, "samsung,pins", prop, pin_name) { - for (cnt = 0; cnt < pctl->npins; cnt++) { - if (pdesc[cnt].name) { - if (!strcmp(pin_name, pdesc[cnt].name)) { - (*pin_list)[idx++] = pdesc[cnt].number; - break; - } - } - } - if (cnt == pctl->npins) { - dev_err(dev, "pin %s not valid in %s node\n", - pin_name, cfg_np->name); - devm_kfree(dev, *pin_list); - return -EINVAL; + for (i = 0; i < npins; ++i) { + const char *gname; + + ret = of_property_read_string_index(func_np, "samsung,pins", + i, &gname); + if (ret) { + dev_err(dev, + "failed to read pin name %d from %s node\n", + i, func_np->name); + return ret; } + + func->groups[i] = gname; } - return 0; + func->num_groups = npins; + return 1; } -/* - * Parse the information about all the available pin groups and pin functions - * from device node of the pin-controller. A pin group is formed with all - * the pins listed in the "samsung,pins" property. - */ -static int samsung_pinctrl_parse_dt(struct platform_device *pdev, - struct samsung_pinctrl_drv_data *drvdata) +static struct samsung_pmx_func *samsung_pinctrl_create_functions( + struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + unsigned int *cnt) { - struct device *dev = &pdev->dev; + struct samsung_pmx_func *functions, *func; struct device_node *dev_np = dev->of_node; struct device_node *cfg_np; - struct samsung_pin_group *groups, *grp; - struct samsung_pmx_func *functions, *func; - unsigned *pin_list; - unsigned int npins, grp_cnt, func_idx = 0; - char *gname, *fname; + unsigned int func_cnt = 0; int ret; - grp_cnt = of_get_child_count(dev_np); - if (!grp_cnt) - return -EINVAL; + /* + * Iterate over all the child nodes of the pin controller node + * and create pin groups and pin function lists. + */ + for_each_child_of_node(dev_np, cfg_np) { + struct device_node *func_np; - groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); - if (!groups) { - dev_err(dev, "failed allocate memory for ping group list\n"); - return -EINVAL; + if (!of_get_child_count(cfg_np)) { + if (!of_find_property(cfg_np, + "samsung,pin-function", NULL)) + continue; + ++func_cnt; + continue; + } + + for_each_child_of_node(cfg_np, func_np) { + if (!of_find_property(func_np, + "samsung,pin-function", NULL)) + continue; + ++func_cnt; + } } - grp = groups; - functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); + functions = devm_kzalloc(dev, func_cnt * sizeof(*functions), + GFP_KERNEL); if (!functions) { dev_err(dev, "failed to allocate memory for function list\n"); - return -EINVAL; + return ERR_PTR(-EINVAL); } func = functions; @@ -647,61 +749,68 @@ static int samsung_pinctrl_parse_dt(struct platform_device *pdev, * Iterate over all the child nodes of the pin controller node * and create pin groups and pin function lists. */ + func_cnt = 0; for_each_child_of_node(dev_np, cfg_np) { - u32 function; - if (!of_find_property(cfg_np, "samsung,pins", NULL)) + struct device_node *func_np; + + if (!of_get_child_count(cfg_np)) { + ret = samsung_pinctrl_create_function(dev, drvdata, + cfg_np, func); + if (ret < 0) + return ERR_PTR(ret); + if (ret > 0) { + ++func; + ++func_cnt; + } continue; + } - ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np, - &drvdata->pctl, &pin_list, &npins); - if (ret) - return ret; - - /* derive pin group name from the node name */ - gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, - GFP_KERNEL); - if (!gname) { - dev_err(dev, "failed to alloc memory for group name\n"); - return -ENOMEM; + for_each_child_of_node(cfg_np, func_np) { + ret = samsung_pinctrl_create_function(dev, drvdata, + func_np, func); + if (ret < 0) + return ERR_PTR(ret); + if (ret > 0) { + ++func; + ++func_cnt; + } } - sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX); + } - grp->name = gname; - grp->pins = pin_list; - grp->num_pins = npins; - of_property_read_u32(cfg_np, "samsung,pin-function", &function); - grp->func = function; - grp++; + *cnt = func_cnt; + return functions; +} - if (!of_find_property(cfg_np, "samsung,pin-function", NULL)) - continue; +/* + * Parse the information about all the available pin groups and pin functions + * from device node of the pin-controller. A pin group is formed with all + * the pins listed in the "samsung,pins" property. + */ - /* derive function name from the node name */ - fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, - GFP_KERNEL); - if (!fname) { - dev_err(dev, "failed to alloc memory for func name\n"); - return -ENOMEM; - } - sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX); - - func->name = fname; - func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); - if (!func->groups) { - dev_err(dev, "failed to alloc memory for group list " - "in pin function"); - return -ENOMEM; - } - func->groups[0] = gname; - func->num_groups = 1; - func++; - func_idx++; +static int samsung_pinctrl_parse_dt(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct device *dev = &pdev->dev; + struct samsung_pin_group *groups; + struct samsung_pmx_func *functions; + unsigned int grp_cnt = 0, func_cnt = 0; + + groups = samsung_pinctrl_create_groups(dev, drvdata, &grp_cnt); + if (IS_ERR(groups)) { + dev_err(dev, "failed to parse pin groups\n"); + return PTR_ERR(groups); + } + + functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt); + if (IS_ERR(functions)) { + dev_err(dev, "failed to parse pin functions\n"); + return PTR_ERR(groups); } drvdata->pin_groups = groups; drvdata->nr_groups = grp_cnt; drvdata->pmx_functions = functions; - drvdata->nr_functions = func_idx; + drvdata->nr_functions = func_cnt; return 0; } diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index e2dce4731a01..2b882320e8e9 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -231,6 +231,7 @@ struct samsung_pmx_func { const char *name; const char **groups; u8 num_groups; + u32 val; }; /* list of all exported SoC specific data */ -- cgit v1.2.3 From 2700bc013572e3c07e3a28e3715f277fd94b678a Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 2 Jul 2014 17:41:04 +0200 Subject: pinctrl: samsung: Allow pin value to be initialized using pinfunc This patch extends the range of settings configurable via pinfunc API to cover pin value as well. This allows configuration of default values of pins, which is useful for pins that are not supposed to be used by any dedicated driver, but need certain board-specific setting. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-samsung.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index b7de66c3b51d..52f849ac06c1 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -47,6 +47,7 @@ static struct pin_config { { "samsung,pin-drv", PINCFG_TYPE_DRV }, { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN }, { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, + { "samsung,pin-val", PINCFG_TYPE_DAT }, }; /* Global list of devices (struct samsung_pinctrl_drv_data) */ -- cgit v1.2.3 From 14d40ff8f8b25a1ae6a273b62e239c7064e5bc9f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 8 Jul 2014 21:59:31 -0700 Subject: pinctrl: msm: Add msm8960 definitions Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-msm8960.c | 1254 +++++++++++++++++++++++++++++++++++++ 3 files changed, 1263 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-msm8960.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 2744fa2825e0..c0f49fb3276c 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -256,6 +256,14 @@ config PINCTRL_IPQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. +config PINCTRL_MSM8960 + tristate "Qualcomm 8960 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8960 platform. + config PINCTRL_MSM8X74 tristate "Qualcomm 8x74 pin controller driver" depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c7d8f1b7311f..80bced77446a 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o diff --git a/drivers/pinctrl/pinctrl-msm8960.c b/drivers/pinctrl/pinctrl-msm8960.c new file mode 100644 index 000000000000..564543bb2c1c --- /dev/null +++ b/drivers/pinctrl/pinctrl-msm8960.c @@ -0,0 +1,1254 @@ +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8960_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), + PINCTRL_PIN(155, "SDC3_CLK"), + PINCTRL_PIN(156, "SDC3_CMD"), + PINCTRL_PIN(157, "SDC3_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); + +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; +static const unsigned int sdc3_clk_pins[] = { 155 }; +static const unsigned int sdc3_cmd_pins[] = { 156 }; +static const unsigned int sdc3_data_pins[] = { 157 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_NA, /* gpio mode */ \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7, \ + MSM_MUX_##f8, \ + MSM_MUX_##f9, \ + MSM_MUX_##f10, \ + MSM_MUX_##f11 \ + }, \ + .nfuncs = 12, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8960_functions { + MSM_MUX_audio_pcm, + MSM_MUX_bt, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_cam_mclk2, + MSM_MUX_codec_mic_i2s, + MSM_MUX_codec_spkr_i2s, + MSM_MUX_ext_gps, + MSM_MUX_fm, + MSM_MUX_gps_blanking, + MSM_MUX_gps_pps_in, + MSM_MUX_gps_pps_out, + MSM_MUX_gp_clk_0a, + MSM_MUX_gp_clk_0b, + MSM_MUX_gp_clk_1a, + MSM_MUX_gp_clk_1b, + MSM_MUX_gp_clk_2a, + MSM_MUX_gp_clk_2b, + MSM_MUX_gp_mn, + MSM_MUX_gp_pdm_0a, + MSM_MUX_gp_pdm_0b, + MSM_MUX_gp_pdm_1a, + MSM_MUX_gp_pdm_1b, + MSM_MUX_gp_pdm_2a, + MSM_MUX_gp_pdm_2b, + MSM_MUX_gsbi1, + MSM_MUX_gsbi1_spi_cs1_n, + MSM_MUX_gsbi1_spi_cs2a_n, + MSM_MUX_gsbi1_spi_cs2b_n, + MSM_MUX_gsbi1_spi_cs3_n, + MSM_MUX_gsbi2, + MSM_MUX_gsbi2_spi_cs1_n, + MSM_MUX_gsbi2_spi_cs2_n, + MSM_MUX_gsbi2_spi_cs3_n, + MSM_MUX_gsbi3, + MSM_MUX_gsbi4, + MSM_MUX_gsbi4_3d_cam_i2c_l, + MSM_MUX_gsbi4_3d_cam_i2c_r, + MSM_MUX_gsbi5, + MSM_MUX_gsbi5_3d_cam_i2c_l, + MSM_MUX_gsbi5_3d_cam_i2c_r, + MSM_MUX_gsbi6, + MSM_MUX_gsbi7, + MSM_MUX_gsbi8, + MSM_MUX_gsbi9, + MSM_MUX_gsbi10, + MSM_MUX_gsbi11, + MSM_MUX_gsbi11_spi_cs1a_n, + MSM_MUX_gsbi11_spi_cs1b_n, + MSM_MUX_gsbi11_spi_cs2a_n, + MSM_MUX_gsbi11_spi_cs2b_n, + MSM_MUX_gsbi11_spi_cs3_n, + MSM_MUX_gsbi12, + MSM_MUX_hdmi_cec, + MSM_MUX_hdmi_ddc_clock, + MSM_MUX_hdmi_ddc_data, + MSM_MUX_hdmi_hot_plug_detect, + MSM_MUX_hsic, + MSM_MUX_mdp_vsync, + MSM_MUX_mi2s, + MSM_MUX_mic_i2s, + MSM_MUX_pmb_clk, + MSM_MUX_pmb_ext_ctrl, + MSM_MUX_ps_hold, + MSM_MUX_rpm_wdog, + MSM_MUX_sdc2, + MSM_MUX_sdc4, + MSM_MUX_sdc5, + MSM_MUX_slimbus1, + MSM_MUX_slimbus2, + MSM_MUX_spkr_i2s, + MSM_MUX_ssbi1, + MSM_MUX_ssbi2, + MSM_MUX_ssbi_ext_gps, + MSM_MUX_ssbi_pmic2, + MSM_MUX_ssbi_qpa1, + MSM_MUX_ssbi_ts, + MSM_MUX_tsif1, + MSM_MUX_tsif2, + MSM_MUX_ts_eoc, + MSM_MUX_usb_fs1, + MSM_MUX_usb_fs1_oe, + MSM_MUX_usb_fs1_oe_n, + MSM_MUX_usb_fs2, + MSM_MUX_usb_fs2_oe, + MSM_MUX_usb_fs2_oe_n, + MSM_MUX_vfe_camif_timer1_a, + MSM_MUX_vfe_camif_timer1_b, + MSM_MUX_vfe_camif_timer2, + MSM_MUX_vfe_camif_timer3_a, + MSM_MUX_vfe_camif_timer3_b, + MSM_MUX_vfe_camif_timer4_a, + MSM_MUX_vfe_camif_timer4_b, + MSM_MUX_vfe_camif_timer4_c, + MSM_MUX_vfe_camif_timer5_a, + MSM_MUX_vfe_camif_timer5_b, + MSM_MUX_vfe_camif_timer6_a, + MSM_MUX_vfe_camif_timer6_b, + MSM_MUX_vfe_camif_timer6_c, + MSM_MUX_vfe_camif_timer7_a, + MSM_MUX_vfe_camif_timer7_b, + MSM_MUX_vfe_camif_timer7_c, + MSM_MUX_wlan, + MSM_MUX_NA, +}; + +static const char * const audio_pcm_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; + +static const char * const bt_groups[] = { + "gpio28", "gpio29", "gpio83" +}; + +static const char * const cam_mclk0_groups[] = { + "gpio5" +}; + +static const char * const cam_mclk1_groups[] = { + "gpio4" +}; + +static const char * const cam_mclk2_groups[] = { + "gpio2" +}; + +static const char * const codec_mic_i2s_groups[] = { + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58" +}; + +static const char * const codec_spkr_i2s_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62" +}; + +static const char * const ext_gps_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; + +static const char * const fm_groups[] = { + "gpio26", "gpio27" +}; + +static const char * const gps_blanking_groups[] = { + "gpio137" +}; + +static const char * const gps_pps_in_groups[] = { + "gpio37" +}; + +static const char * const gps_pps_out_groups[] = { + "gpio37" +}; + +static const char * const gp_clk_0a_groups[] = { + "gpio3" +}; + +static const char * const gp_clk_0b_groups[] = { + "gpio54" +}; + +static const char * const gp_clk_1a_groups[] = { + "gpio4" +}; + +static const char * const gp_clk_1b_groups[] = { + "gpio70" +}; + +static const char * const gp_clk_2a_groups[] = { + "gpio52" +}; + +static const char * const gp_clk_2b_groups[] = { + "gpio37" +}; + +static const char * const gp_mn_groups[] = { + "gpio2" +}; + +static const char * const gp_pdm_0a_groups[] = { + "gpio58" +}; + +static const char * const gp_pdm_0b_groups[] = { + "gpio39" +}; + +static const char * const gp_pdm_1a_groups[] = { + "gpio94" +}; + +static const char * const gp_pdm_1b_groups[] = { + "gpio64" +}; + +static const char * const gp_pdm_2a_groups[] = { + "gpio69" +}; + +static const char * const gp_pdm_2b_groups[] = { + "gpio53" +}; + +static const char * const gsbi1_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9" +}; + +static const char * const gsbi1_spi_cs1_n_groups[] = { + "gpio14" +}; + +static const char * const gsbi1_spi_cs2a_n_groups[] = { + "gpio15" +}; + +static const char * const gsbi1_spi_cs2b_n_groups[] = { + "gpio17" +}; + +static const char * const gsbi1_spi_cs3_n_groups[] = { + "gpio16" +}; + +static const char * const gsbi2_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; + +static const char * const gsbi2_spi_cs1_n_groups[] = { + "gpio52" +}; + +static const char * const gsbi2_spi_cs2_n_groups[] = { + "gpio68" +}; + +static const char * const gsbi2_spi_cs3_n_groups[] = { + "gpio56" +}; + +static const char * const gsbi3_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17" +}; + +static const char * const gsbi4_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21" +}; + +static const char * const gsbi4_3d_cam_i2c_l_groups[] = { + "gpio18", "gpio19" +}; + +static const char * const gsbi4_3d_cam_i2c_r_groups[] = { + "gpio20", "gpio21" +}; + +static const char * const gsbi5_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; + +static const char * const gsbi5_3d_cam_i2c_l_groups[] = { + "gpio22", "gpio23" +}; + +static const char * const gsbi5_3d_cam_i2c_r_groups[] = { + "gpio24", "gpio25" +}; + +static const char * const gsbi6_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29" +}; + +static const char * const gsbi7_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33" +}; + +static const char * const gsbi8_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37" +}; + +static const char * const gsbi9_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gsbi10_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74" +}; + +static const char * const gsbi11_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41" +}; + +static const char * const gsbi11_spi_cs1a_n_groups[] = { + "gpio36" +}; + +static const char * const gsbi11_spi_cs1b_n_groups[] = { + "gpio18" +}; + +static const char * const gsbi11_spi_cs2a_n_groups[] = { + "gpio37" +}; + +static const char * const gsbi11_spi_cs2b_n_groups[] = { + "gpio19" +}; + +static const char * const gsbi11_spi_cs3_n_groups[] = { + "gpio76" +}; + +static const char * const gsbi12_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45" +}; + +static const char * const hdmi_cec_groups[] = { + "gpio99" +}; + +static const char * const hdmi_ddc_clock_groups[] = { + "gpio100" +}; + +static const char * const hdmi_ddc_data_groups[] = { + "gpio101" +}; + +static const char * const hdmi_hot_plug_detect_groups[] = { + "gpio102" +}; + +static const char * const hsic_groups[] = { + "gpio150", "gpio151" +}; + +static const char * const mdp_vsync_groups[] = { + "gpio0", "gpio1", "gpio19" +}; + +static const char * const mi2s_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53" +}; + +static const char * const mic_i2s_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74" +}; + +static const char * const pmb_clk_groups[] = { + "gpio21", "gpio86", "gpio112" +}; + +static const char * const pmb_ext_ctrl_groups[] = { + "gpio4", "gpio5" +}; + +static const char * const ps_hold_groups[] = { + "gpio108" +}; + +static const char * const rpm_wdog_groups[] = { + "gpio12" +}; + +static const char * const sdc2_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98" +}; + +static const char * const sdc4_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const sdc5_groups[] = { + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const slimbus1_groups[] = { + "gpio50", "gpio51", "gpio60", "gpio61" +}; + +static const char * const slimbus2_groups[] = { + "gpio42", "gpio43" +}; + +static const char * const spkr_i2s_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70" +}; + +static const char * const ssbi1_groups[] = { + "gpio141", "gpio143" +}; + +static const char * const ssbi2_groups[] = { + "gpio140", "gpio142" +}; + +static const char * const ssbi_ext_gps_groups[] = { + "gpio23" +}; + +static const char * const ssbi_pmic2_groups[] = { + "gpio149" +}; + +static const char * const ssbi_qpa1_groups[] = { + "gpio131" +}; + +static const char * const ssbi_ts_groups[] = { + "gpio10" +}; + +static const char * const tsif1_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio82" +}; + +static const char * const tsif2_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81" +}; + +static const char * const ts_eoc_groups[] = { + "gpio11" +}; + +static const char * const usb_fs1_groups[] = { + "gpio32", "gpio33" +}; + +static const char * const usb_fs1_oe_groups[] = { + "gpio31" +}; + +static const char * const usb_fs1_oe_n_groups[] = { + "gpio31" +}; + +static const char * const usb_fs2_groups[] = { + "gpio34", "gpio35" +}; + +static const char * const usb_fs2_oe_groups[] = { + "gpio36" +}; + +static const char * const usb_fs2_oe_n_groups[] = { + "gpio36" +}; + +static const char * const vfe_camif_timer1_a_groups[] = { + "gpio2" +}; + +static const char * const vfe_camif_timer1_b_groups[] = { + "gpio38" +}; + +static const char * const vfe_camif_timer2_groups[] = { + "gpio3" +}; + +static const char * const vfe_camif_timer3_a_groups[] = { + "gpio4" +}; + +static const char * const vfe_camif_timer3_b_groups[] = { + "gpio151" +}; + +static const char * const vfe_camif_timer4_a_groups[] = { + "gpio65" +}; + +static const char * const vfe_camif_timer4_b_groups[] = { + "gpio150" +}; + +static const char * const vfe_camif_timer4_c_groups[] = { + "gpio10" +}; + +static const char * const vfe_camif_timer5_a_groups[] = { + "gpio66" +}; + +static const char * const vfe_camif_timer5_b_groups[] = { + "gpio39" +}; + +static const char * const vfe_camif_timer6_a_groups[] = { + "gpio71" +}; + +static const char * const vfe_camif_timer6_b_groups[] = { + "gpio0" +}; + +static const char * const vfe_camif_timer6_c_groups[] = { + "gpio18" +}; + +static const char * const vfe_camif_timer7_a_groups[] = { + "gpio67" +}; + +static const char * const vfe_camif_timer7_b_groups[] = { + "gpio1" +}; + +static const char * const vfe_camif_timer7_c_groups[] = { + "gpio19" +}; + +static const char * const wlan_groups[] = { + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const struct msm_function msm8960_functions[] = { + FUNCTION(audio_pcm), + FUNCTION(bt), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cam_mclk2), + FUNCTION(codec_mic_i2s), + FUNCTION(codec_spkr_i2s), + FUNCTION(ext_gps), + FUNCTION(fm), + FUNCTION(gps_blanking), + FUNCTION(gps_pps_in), + FUNCTION(gps_pps_out), + FUNCTION(gp_clk_0a), + FUNCTION(gp_clk_0b), + FUNCTION(gp_clk_1a), + FUNCTION(gp_clk_1b), + FUNCTION(gp_clk_2a), + FUNCTION(gp_clk_2b), + FUNCTION(gp_mn), + FUNCTION(gp_pdm_0a), + FUNCTION(gp_pdm_0b), + FUNCTION(gp_pdm_1a), + FUNCTION(gp_pdm_1b), + FUNCTION(gp_pdm_2a), + FUNCTION(gp_pdm_2b), + FUNCTION(gsbi1), + FUNCTION(gsbi1_spi_cs1_n), + FUNCTION(gsbi1_spi_cs2a_n), + FUNCTION(gsbi1_spi_cs2b_n), + FUNCTION(gsbi1_spi_cs3_n), + FUNCTION(gsbi2), + FUNCTION(gsbi2_spi_cs1_n), + FUNCTION(gsbi2_spi_cs2_n), + FUNCTION(gsbi2_spi_cs3_n), + FUNCTION(gsbi3), + FUNCTION(gsbi4), + FUNCTION(gsbi4_3d_cam_i2c_l), + FUNCTION(gsbi4_3d_cam_i2c_r), + FUNCTION(gsbi5), + FUNCTION(gsbi5_3d_cam_i2c_l), + FUNCTION(gsbi5_3d_cam_i2c_r), + FUNCTION(gsbi6), + FUNCTION(gsbi7), + FUNCTION(gsbi8), + FUNCTION(gsbi9), + FUNCTION(gsbi10), + FUNCTION(gsbi11), + FUNCTION(gsbi11_spi_cs1a_n), + FUNCTION(gsbi11_spi_cs1b_n), + FUNCTION(gsbi11_spi_cs2a_n), + FUNCTION(gsbi11_spi_cs2b_n), + FUNCTION(gsbi11_spi_cs3_n), + FUNCTION(gsbi12), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc_clock), + FUNCTION(hdmi_ddc_data), + FUNCTION(hdmi_hot_plug_detect), + FUNCTION(hsic), + FUNCTION(mdp_vsync), + FUNCTION(mi2s), + FUNCTION(mic_i2s), + FUNCTION(pmb_clk), + FUNCTION(pmb_ext_ctrl), + FUNCTION(ps_hold), + FUNCTION(rpm_wdog), + FUNCTION(sdc2), + FUNCTION(sdc4), + FUNCTION(sdc5), + FUNCTION(slimbus1), + FUNCTION(slimbus2), + FUNCTION(spkr_i2s), + FUNCTION(ssbi1), + FUNCTION(ssbi2), + FUNCTION(ssbi_ext_gps), + FUNCTION(ssbi_pmic2), + FUNCTION(ssbi_qpa1), + FUNCTION(ssbi_ts), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(ts_eoc), + FUNCTION(usb_fs1), + FUNCTION(usb_fs1_oe), + FUNCTION(usb_fs1_oe_n), + FUNCTION(usb_fs2), + FUNCTION(usb_fs2_oe), + FUNCTION(usb_fs2_oe_n), + FUNCTION(vfe_camif_timer1_a), + FUNCTION(vfe_camif_timer1_b), + FUNCTION(vfe_camif_timer2), + FUNCTION(vfe_camif_timer3_a), + FUNCTION(vfe_camif_timer3_b), + FUNCTION(vfe_camif_timer4_a), + FUNCTION(vfe_camif_timer4_b), + FUNCTION(vfe_camif_timer4_c), + FUNCTION(vfe_camif_timer5_a), + FUNCTION(vfe_camif_timer5_b), + FUNCTION(vfe_camif_timer6_a), + FUNCTION(vfe_camif_timer6_b), + FUNCTION(vfe_camif_timer6_c), + FUNCTION(vfe_camif_timer7_a), + FUNCTION(vfe_camif_timer7_b), + FUNCTION(vfe_camif_timer7_c), + FUNCTION(wlan), +}; + +static const struct msm_pingroup msm8960_groups[] = { + PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA), + PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), + PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), + PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), + PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), + PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA), + PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA), + PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b), + PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 152 + +static const struct msm_pinctrl_soc_data msm8960_pinctrl = { + .pins = msm8960_pins, + .npins = ARRAY_SIZE(msm8960_pins), + .functions = msm8960_functions, + .nfunctions = ARRAY_SIZE(msm8960_functions), + .groups = msm8960_groups, + .ngroups = ARRAY_SIZE(msm8960_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8960_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8960_pinctrl); +} + +static const struct of_device_id msm8960_pinctrl_of_match[] = { + { .compatible = "qcom,msm8960-pinctrl", }, + { }, +}; + +static struct platform_driver msm8960_pinctrl_driver = { + .driver = { + .name = "msm8960-pinctrl", + .owner = THIS_MODULE, + .of_match_table = msm8960_pinctrl_of_match, + }, + .probe = msm8960_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8960_pinctrl_init(void) +{ + return platform_driver_register(&msm8960_pinctrl_driver); +} +arch_initcall(msm8960_pinctrl_init); + +static void __exit msm8960_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8960_pinctrl_driver); +} +module_exit(msm8960_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); -- cgit v1.2.3 From 69b78b8de65b28f65f2e31029462521855c7c351 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 9 Jul 2014 13:55:12 +0200 Subject: pinctrl: msm: move all qualcomm drivers to subdir We have four Qualcomm-related pin control drivers, and now there are drivers coming in for the PMICs on these systems, so let's create a qcom subdirectory to hold all the Qualcomm stuff. Acked-by: Ivan T. Ivanov Acked-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 40 +- drivers/pinctrl/Makefile | 6 +- drivers/pinctrl/pinctrl-apq8064.c | 613 ---------------- drivers/pinctrl/pinctrl-ipq8064.c | 653 ----------------- drivers/pinctrl/pinctrl-msm.c | 922 ----------------------- drivers/pinctrl/pinctrl-msm.h | 121 --- drivers/pinctrl/pinctrl-msm8960.c | 1254 -------------------------------- drivers/pinctrl/pinctrl-msm8x74.c | 1040 -------------------------- drivers/pinctrl/qcom/Kconfig | 42 ++ drivers/pinctrl/qcom/Makefile | 6 + drivers/pinctrl/qcom/pinctrl-apq8064.c | 613 ++++++++++++++++ drivers/pinctrl/qcom/pinctrl-ipq8064.c | 653 +++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.c | 922 +++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 121 +++ drivers/pinctrl/qcom/pinctrl-msm8960.c | 1254 ++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm8x74.c | 1040 ++++++++++++++++++++++++++ 16 files changed, 4653 insertions(+), 4647 deletions(-) delete mode 100644 drivers/pinctrl/pinctrl-apq8064.c delete mode 100644 drivers/pinctrl/pinctrl-ipq8064.c delete mode 100644 drivers/pinctrl/pinctrl-msm.c delete mode 100644 drivers/pinctrl/pinctrl-msm.h delete mode 100644 drivers/pinctrl/pinctrl-msm8960.c delete mode 100644 drivers/pinctrl/pinctrl-msm8x74.c create mode 100644 drivers/pinctrl/qcom/Kconfig create mode 100644 drivers/pinctrl/qcom/Makefile create mode 100644 drivers/pinctrl/qcom/pinctrl-apq8064.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8064.c create mode 100644 drivers/pinctrl/qcom/pinctrl-msm.c create mode 100644 drivers/pinctrl/qcom/pinctrl-msm.h create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8960.c create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8x74.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c0f49fb3276c..e2c7e09783fa 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -233,45 +233,6 @@ config PINCTRL_IMX28 bool select PINCTRL_MXS -config PINCTRL_MSM - bool - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB_IRQCHIP - -config PINCTRL_APQ8064 - tristate "Qualcomm APQ8064 pin controller driver" - depends on GPIOLIB && OF - select PINCTRL_MSM - help - This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm APQ8064 platform. - -config PINCTRL_IPQ8064 - tristate "Qualcomm IPQ8064 pin controller driver" - depends on GPIOLIB && OF - select PINCTRL_MSM - help - This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. - -config PINCTRL_MSM8960 - tristate "Qualcomm 8960 pin controller driver" - depends on GPIOLIB && OF - select PINCTRL_MSM - help - This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm 8960 platform. - -config PINCTRL_MSM8X74 - tristate "Qualcomm 8x74 pin controller driver" - depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST) - select PINCTRL_MSM - help - This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm 8974 platform. - config PINCTRL_NOMADIK bool "Nomadik pin controller driver" depends on ARCH_U8500 || ARCH_NOMADIK @@ -410,6 +371,7 @@ config PINCTRL_S3C64XX source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" +source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 80bced77446a..abe17724036c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -39,11 +39,6 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o -obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o -obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o -obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o -obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o -obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o @@ -74,6 +69,7 @@ obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_PLAT_ORION) += mvebu/ +obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ obj-$(CONFIG_SUPERH) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ diff --git a/drivers/pinctrl/pinctrl-apq8064.c b/drivers/pinctrl/pinctrl-apq8064.c deleted file mode 100644 index 519f7886b0f1..000000000000 --- a/drivers/pinctrl/pinctrl-apq8064.c +++ /dev/null @@ -1,613 +0,0 @@ -/* - * Copyright (c) 2014, Sony Mobile Communications AB. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -static const struct pinctrl_pin_desc apq8064_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - PINCTRL_PIN(69, "GPIO_69"), - PINCTRL_PIN(70, "GPIO_70"), - PINCTRL_PIN(71, "GPIO_71"), - PINCTRL_PIN(72, "GPIO_72"), - PINCTRL_PIN(73, "GPIO_73"), - PINCTRL_PIN(74, "GPIO_74"), - PINCTRL_PIN(75, "GPIO_75"), - PINCTRL_PIN(76, "GPIO_76"), - PINCTRL_PIN(77, "GPIO_77"), - PINCTRL_PIN(78, "GPIO_78"), - PINCTRL_PIN(79, "GPIO_79"), - PINCTRL_PIN(80, "GPIO_80"), - PINCTRL_PIN(81, "GPIO_81"), - PINCTRL_PIN(82, "GPIO_82"), - PINCTRL_PIN(83, "GPIO_83"), - PINCTRL_PIN(84, "GPIO_84"), - PINCTRL_PIN(85, "GPIO_85"), - PINCTRL_PIN(86, "GPIO_86"), - PINCTRL_PIN(87, "GPIO_87"), - PINCTRL_PIN(88, "GPIO_88"), - PINCTRL_PIN(89, "GPIO_89"), - - PINCTRL_PIN(90, "SDC1_CLK"), - PINCTRL_PIN(91, "SDC1_CMD"), - PINCTRL_PIN(92, "SDC1_DATA"), - PINCTRL_PIN(93, "SDC3_CLK"), - PINCTRL_PIN(94, "SDC3_CMD"), - PINCTRL_PIN(95, "SDC3_DATA"), -}; - -#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_APQ_GPIO_PINS(0); -DECLARE_APQ_GPIO_PINS(1); -DECLARE_APQ_GPIO_PINS(2); -DECLARE_APQ_GPIO_PINS(3); -DECLARE_APQ_GPIO_PINS(4); -DECLARE_APQ_GPIO_PINS(5); -DECLARE_APQ_GPIO_PINS(6); -DECLARE_APQ_GPIO_PINS(7); -DECLARE_APQ_GPIO_PINS(8); -DECLARE_APQ_GPIO_PINS(9); -DECLARE_APQ_GPIO_PINS(10); -DECLARE_APQ_GPIO_PINS(11); -DECLARE_APQ_GPIO_PINS(12); -DECLARE_APQ_GPIO_PINS(13); -DECLARE_APQ_GPIO_PINS(14); -DECLARE_APQ_GPIO_PINS(15); -DECLARE_APQ_GPIO_PINS(16); -DECLARE_APQ_GPIO_PINS(17); -DECLARE_APQ_GPIO_PINS(18); -DECLARE_APQ_GPIO_PINS(19); -DECLARE_APQ_GPIO_PINS(20); -DECLARE_APQ_GPIO_PINS(21); -DECLARE_APQ_GPIO_PINS(22); -DECLARE_APQ_GPIO_PINS(23); -DECLARE_APQ_GPIO_PINS(24); -DECLARE_APQ_GPIO_PINS(25); -DECLARE_APQ_GPIO_PINS(26); -DECLARE_APQ_GPIO_PINS(27); -DECLARE_APQ_GPIO_PINS(28); -DECLARE_APQ_GPIO_PINS(29); -DECLARE_APQ_GPIO_PINS(30); -DECLARE_APQ_GPIO_PINS(31); -DECLARE_APQ_GPIO_PINS(32); -DECLARE_APQ_GPIO_PINS(33); -DECLARE_APQ_GPIO_PINS(34); -DECLARE_APQ_GPIO_PINS(35); -DECLARE_APQ_GPIO_PINS(36); -DECLARE_APQ_GPIO_PINS(37); -DECLARE_APQ_GPIO_PINS(38); -DECLARE_APQ_GPIO_PINS(39); -DECLARE_APQ_GPIO_PINS(40); -DECLARE_APQ_GPIO_PINS(41); -DECLARE_APQ_GPIO_PINS(42); -DECLARE_APQ_GPIO_PINS(43); -DECLARE_APQ_GPIO_PINS(44); -DECLARE_APQ_GPIO_PINS(45); -DECLARE_APQ_GPIO_PINS(46); -DECLARE_APQ_GPIO_PINS(47); -DECLARE_APQ_GPIO_PINS(48); -DECLARE_APQ_GPIO_PINS(49); -DECLARE_APQ_GPIO_PINS(50); -DECLARE_APQ_GPIO_PINS(51); -DECLARE_APQ_GPIO_PINS(52); -DECLARE_APQ_GPIO_PINS(53); -DECLARE_APQ_GPIO_PINS(54); -DECLARE_APQ_GPIO_PINS(55); -DECLARE_APQ_GPIO_PINS(56); -DECLARE_APQ_GPIO_PINS(57); -DECLARE_APQ_GPIO_PINS(58); -DECLARE_APQ_GPIO_PINS(59); -DECLARE_APQ_GPIO_PINS(60); -DECLARE_APQ_GPIO_PINS(61); -DECLARE_APQ_GPIO_PINS(62); -DECLARE_APQ_GPIO_PINS(63); -DECLARE_APQ_GPIO_PINS(64); -DECLARE_APQ_GPIO_PINS(65); -DECLARE_APQ_GPIO_PINS(66); -DECLARE_APQ_GPIO_PINS(67); -DECLARE_APQ_GPIO_PINS(68); -DECLARE_APQ_GPIO_PINS(69); -DECLARE_APQ_GPIO_PINS(70); -DECLARE_APQ_GPIO_PINS(71); -DECLARE_APQ_GPIO_PINS(72); -DECLARE_APQ_GPIO_PINS(73); -DECLARE_APQ_GPIO_PINS(74); -DECLARE_APQ_GPIO_PINS(75); -DECLARE_APQ_GPIO_PINS(76); -DECLARE_APQ_GPIO_PINS(77); -DECLARE_APQ_GPIO_PINS(78); -DECLARE_APQ_GPIO_PINS(79); -DECLARE_APQ_GPIO_PINS(80); -DECLARE_APQ_GPIO_PINS(81); -DECLARE_APQ_GPIO_PINS(82); -DECLARE_APQ_GPIO_PINS(83); -DECLARE_APQ_GPIO_PINS(84); -DECLARE_APQ_GPIO_PINS(85); -DECLARE_APQ_GPIO_PINS(86); -DECLARE_APQ_GPIO_PINS(87); -DECLARE_APQ_GPIO_PINS(88); -DECLARE_APQ_GPIO_PINS(89); - -static const unsigned int sdc1_clk_pins[] = { 90 }; -static const unsigned int sdc1_cmd_pins[] = { 91 }; -static const unsigned int sdc1_data_pins[] = { 92 }; -static const unsigned int sdc3_clk_pins[] = { 93 }; -static const unsigned int sdc3_cmd_pins[] = { 94 }; -static const unsigned int sdc3_data_pins[] = { 95 }; - -#define FUNCTION(fname) \ - [APQ_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - APQ_MUX_NA, /* gpio mode */ \ - APQ_MUX_##f1, \ - APQ_MUX_##f2, \ - APQ_MUX_##f3, \ - APQ_MUX_##f4, \ - APQ_MUX_##f5, \ - APQ_MUX_##f6, \ - APQ_MUX_##f7, \ - APQ_MUX_##f8, \ - APQ_MUX_##f9, \ - APQ_MUX_##f10, \ - }, \ - .nfuncs = 11, \ - .ctl_reg = 0x1000 + 0x10 * id, \ - .io_reg = 0x1004 + 0x10 * id, \ - .intr_cfg_reg = 0x1008 + 0x10 * id, \ - .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x400 + 0x4 * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_ack_high = 1, \ - .intr_target_bit = 0, \ - .intr_raw_status_bit = 3, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 1, \ - } - -#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -enum apq8064_functions { - APQ_MUX_cam_mclk, - APQ_MUX_codec_mic_i2s, - APQ_MUX_codec_spkr_i2s, - APQ_MUX_gsbi1, - APQ_MUX_gsbi2, - APQ_MUX_gsbi3, - APQ_MUX_gsbi4, - APQ_MUX_gsbi4_cam_i2c, - APQ_MUX_gsbi5, - APQ_MUX_gsbi5_spi_cs1, - APQ_MUX_gsbi5_spi_cs2, - APQ_MUX_gsbi5_spi_cs3, - APQ_MUX_gsbi6, - APQ_MUX_gsbi6_spi_cs1, - APQ_MUX_gsbi6_spi_cs2, - APQ_MUX_gsbi6_spi_cs3, - APQ_MUX_gsbi7, - APQ_MUX_gsbi7_spi_cs1, - APQ_MUX_gsbi7_spi_cs2, - APQ_MUX_gsbi7_spi_cs3, - APQ_MUX_gsbi_cam_i2c, - APQ_MUX_hdmi, - APQ_MUX_mi2s, - APQ_MUX_riva_bt, - APQ_MUX_riva_fm, - APQ_MUX_riva_wlan, - APQ_MUX_sdc2, - APQ_MUX_sdc4, - APQ_MUX_slimbus, - APQ_MUX_spkr_i2s, - APQ_MUX_tsif1, - APQ_MUX_tsif2, - APQ_MUX_usb2_hsic, - APQ_MUX_NA, -}; - -static const char * const cam_mclk_groups[] = { - "gpio4" "gpio5" -}; -static const char * const codec_mic_i2s_groups[] = { - "gpio34", "gpio35", "gpio36", "gpio37", "gpio38" -}; -static const char * const codec_spkr_i2s_groups[] = { - "gpio39", "gpio40", "gpio41", "gpio42" -}; -static const char * const gsbi1_groups[] = { - "gpio18", "gpio19", "gpio20", "gpio21" -}; -static const char * const gsbi2_groups[] = { - "gpio22", "gpio23", "gpio24", "gpio25" -}; -static const char * const gsbi3_groups[] = { - "gpio6", "gpio7", "gpio8", "gpio9" -}; -static const char * const gsbi4_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13" -}; -static const char * const gsbi4_cam_i2c_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13" -}; -static const char * const gsbi5_groups[] = { - "gpio51", "gpio52", "gpio53", "gpio54" -}; -static const char * const gsbi5_spi_cs1_groups[] = { - "gpio47" -}; -static const char * const gsbi5_spi_cs2_groups[] = { - "gpio31" -}; -static const char * const gsbi5_spi_cs3_groups[] = { - "gpio32" -}; -static const char * const gsbi6_groups[] = { - "gpio14", "gpio15", "gpio16", "gpio17" -}; -static const char * const gsbi6_spi_cs1_groups[] = { - "gpio47" -}; -static const char * const gsbi6_spi_cs2_groups[] = { - "gpio31" -}; -static const char * const gsbi6_spi_cs3_groups[] = { - "gpio32" -}; -static const char * const gsbi7_groups[] = { - "gpio82", "gpio83", "gpio84", "gpio85" -}; -static const char * const gsbi7_spi_cs1_groups[] = { - "gpio47" -}; -static const char * const gsbi7_spi_cs2_groups[] = { - "gpio31" -}; -static const char * const gsbi7_spi_cs3_groups[] = { - "gpio32" -}; -static const char * const gsbi_cam_i2c_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13" -}; -static const char * const hdmi_groups[] = { - "gpio69", "gpio70", "gpio71", "gpio72" -}; -static const char * const mi2s_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33" -}; -static const char * const riva_bt_groups[] = { - "gpio16", "gpio17" -}; -static const char * const riva_fm_groups[] = { - "gpio14", "gpio15" -}; -static const char * const riva_wlan_groups[] = { - "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" -}; -static const char * const sdc2_groups[] = { - "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62" -}; -static const char * const sdc4_groups[] = { - "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" -}; -static const char * const slimbus_groups[] = { - "gpio40", "gpio41" -}; -static const char * const spkr_i2s_groups[] = { - "gpio47", "gpio48", "gpio49", "gpio50" -}; -static const char * const tsif1_groups[] = { - "gpio55", "gpio56", "gpio57" -}; -static const char * const tsif2_groups[] = { - "gpio58", "gpio59", "gpio60" -}; -static const char * const usb2_hsic_groups[] = { - "gpio88", "gpio89" -}; - -static const struct msm_function apq8064_functions[] = { - FUNCTION(cam_mclk), - FUNCTION(codec_mic_i2s), - FUNCTION(codec_spkr_i2s), - FUNCTION(gsbi1), - FUNCTION(gsbi2), - FUNCTION(gsbi3), - FUNCTION(gsbi4), - FUNCTION(gsbi4_cam_i2c), - FUNCTION(gsbi5), - FUNCTION(gsbi5_spi_cs1), - FUNCTION(gsbi5_spi_cs2), - FUNCTION(gsbi5_spi_cs3), - FUNCTION(gsbi6), - FUNCTION(gsbi6_spi_cs1), - FUNCTION(gsbi6_spi_cs2), - FUNCTION(gsbi6_spi_cs3), - FUNCTION(gsbi7), - FUNCTION(gsbi7_spi_cs1), - FUNCTION(gsbi7_spi_cs2), - FUNCTION(gsbi7_spi_cs3), - FUNCTION(gsbi_cam_i2c), - FUNCTION(hdmi), - FUNCTION(mi2s), - FUNCTION(riva_bt), - FUNCTION(riva_fm), - FUNCTION(riva_wlan), - FUNCTION(sdc2), - FUNCTION(sdc4), - FUNCTION(slimbus), - FUNCTION(spkr_i2s), - FUNCTION(tsif1), - FUNCTION(tsif2), - FUNCTION(usb2_hsic), -}; - -static const struct msm_pingroup apq8064_groups[] = { - PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(10, gsbi4, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c, NA), - PINGROUP(11, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c), - PINGROUP(12, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), - PINGROUP(13, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), - PINGROUP(14, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(16, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(17, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(18, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(19, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(20, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(21, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA), - PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA), - PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA), - PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(54, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(55, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(56, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(57, tsif1, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(58, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(59, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(60, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(61, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(62, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, NA, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(69, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(70, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(71, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(72, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(82, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(83, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(84, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(85, NA, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - - SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), - SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), - SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), - - SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), - SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), - SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), -}; - -#define NUM_GPIO_PINGROUPS 90 - -static const struct msm_pinctrl_soc_data apq8064_pinctrl = { - .pins = apq8064_pins, - .npins = ARRAY_SIZE(apq8064_pins), - .functions = apq8064_functions, - .nfunctions = ARRAY_SIZE(apq8064_functions), - .groups = apq8064_groups, - .ngroups = ARRAY_SIZE(apq8064_groups), - .ngpios = NUM_GPIO_PINGROUPS, -}; - -static int apq8064_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &apq8064_pinctrl); -} - -static const struct of_device_id apq8064_pinctrl_of_match[] = { - { .compatible = "qcom,apq8064-pinctrl", }, - { }, -}; - -static struct platform_driver apq8064_pinctrl_driver = { - .driver = { - .name = "apq8064-pinctrl", - .owner = THIS_MODULE, - .of_match_table = apq8064_pinctrl_of_match, - }, - .probe = apq8064_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init apq8064_pinctrl_init(void) -{ - return platform_driver_register(&apq8064_pinctrl_driver); -} -arch_initcall(apq8064_pinctrl_init); - -static void __exit apq8064_pinctrl_exit(void) -{ - platform_driver_unregister(&apq8064_pinctrl_driver); -} -module_exit(apq8064_pinctrl_exit); - -MODULE_AUTHOR("Bjorn Andersson "); -MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-ipq8064.c b/drivers/pinctrl/pinctrl-ipq8064.c deleted file mode 100644 index acafea4c3a33..000000000000 --- a/drivers/pinctrl/pinctrl-ipq8064.c +++ /dev/null @@ -1,653 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -static const struct pinctrl_pin_desc ipq8064_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - - PINCTRL_PIN(69, "SDC3_CLK"), - PINCTRL_PIN(70, "SDC3_CMD"), - PINCTRL_PIN(71, "SDC3_DATA"), -}; - -#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_IPQ_GPIO_PINS(0); -DECLARE_IPQ_GPIO_PINS(1); -DECLARE_IPQ_GPIO_PINS(2); -DECLARE_IPQ_GPIO_PINS(3); -DECLARE_IPQ_GPIO_PINS(4); -DECLARE_IPQ_GPIO_PINS(5); -DECLARE_IPQ_GPIO_PINS(6); -DECLARE_IPQ_GPIO_PINS(7); -DECLARE_IPQ_GPIO_PINS(8); -DECLARE_IPQ_GPIO_PINS(9); -DECLARE_IPQ_GPIO_PINS(10); -DECLARE_IPQ_GPIO_PINS(11); -DECLARE_IPQ_GPIO_PINS(12); -DECLARE_IPQ_GPIO_PINS(13); -DECLARE_IPQ_GPIO_PINS(14); -DECLARE_IPQ_GPIO_PINS(15); -DECLARE_IPQ_GPIO_PINS(16); -DECLARE_IPQ_GPIO_PINS(17); -DECLARE_IPQ_GPIO_PINS(18); -DECLARE_IPQ_GPIO_PINS(19); -DECLARE_IPQ_GPIO_PINS(20); -DECLARE_IPQ_GPIO_PINS(21); -DECLARE_IPQ_GPIO_PINS(22); -DECLARE_IPQ_GPIO_PINS(23); -DECLARE_IPQ_GPIO_PINS(24); -DECLARE_IPQ_GPIO_PINS(25); -DECLARE_IPQ_GPIO_PINS(26); -DECLARE_IPQ_GPIO_PINS(27); -DECLARE_IPQ_GPIO_PINS(28); -DECLARE_IPQ_GPIO_PINS(29); -DECLARE_IPQ_GPIO_PINS(30); -DECLARE_IPQ_GPIO_PINS(31); -DECLARE_IPQ_GPIO_PINS(32); -DECLARE_IPQ_GPIO_PINS(33); -DECLARE_IPQ_GPIO_PINS(34); -DECLARE_IPQ_GPIO_PINS(35); -DECLARE_IPQ_GPIO_PINS(36); -DECLARE_IPQ_GPIO_PINS(37); -DECLARE_IPQ_GPIO_PINS(38); -DECLARE_IPQ_GPIO_PINS(39); -DECLARE_IPQ_GPIO_PINS(40); -DECLARE_IPQ_GPIO_PINS(41); -DECLARE_IPQ_GPIO_PINS(42); -DECLARE_IPQ_GPIO_PINS(43); -DECLARE_IPQ_GPIO_PINS(44); -DECLARE_IPQ_GPIO_PINS(45); -DECLARE_IPQ_GPIO_PINS(46); -DECLARE_IPQ_GPIO_PINS(47); -DECLARE_IPQ_GPIO_PINS(48); -DECLARE_IPQ_GPIO_PINS(49); -DECLARE_IPQ_GPIO_PINS(50); -DECLARE_IPQ_GPIO_PINS(51); -DECLARE_IPQ_GPIO_PINS(52); -DECLARE_IPQ_GPIO_PINS(53); -DECLARE_IPQ_GPIO_PINS(54); -DECLARE_IPQ_GPIO_PINS(55); -DECLARE_IPQ_GPIO_PINS(56); -DECLARE_IPQ_GPIO_PINS(57); -DECLARE_IPQ_GPIO_PINS(58); -DECLARE_IPQ_GPIO_PINS(59); -DECLARE_IPQ_GPIO_PINS(60); -DECLARE_IPQ_GPIO_PINS(61); -DECLARE_IPQ_GPIO_PINS(62); -DECLARE_IPQ_GPIO_PINS(63); -DECLARE_IPQ_GPIO_PINS(64); -DECLARE_IPQ_GPIO_PINS(65); -DECLARE_IPQ_GPIO_PINS(66); -DECLARE_IPQ_GPIO_PINS(67); -DECLARE_IPQ_GPIO_PINS(68); - -static const unsigned int sdc3_clk_pins[] = { 69 }; -static const unsigned int sdc3_cmd_pins[] = { 70 }; -static const unsigned int sdc3_data_pins[] = { 71 }; - -#define FUNCTION(fname) \ - [IPQ_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - IPQ_MUX_NA, /* gpio mode */ \ - IPQ_MUX_##f1, \ - IPQ_MUX_##f2, \ - IPQ_MUX_##f3, \ - IPQ_MUX_##f4, \ - IPQ_MUX_##f5, \ - IPQ_MUX_##f6, \ - IPQ_MUX_##f7, \ - IPQ_MUX_##f8, \ - IPQ_MUX_##f9, \ - IPQ_MUX_##f10, \ - }, \ - .nfuncs = 11, \ - .ctl_reg = 0x1000 + 0x10 * id, \ - .io_reg = 0x1004 + 0x10 * id, \ - .intr_cfg_reg = 0x1008 + 0x10 * id, \ - .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x400 + 0x4 * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_ack_high = 1, \ - .intr_target_bit = 0, \ - .intr_raw_status_bit = 3, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 1, \ - } - -#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -enum ipq8064_functions { - IPQ_MUX_mdio, - IPQ_MUX_mi2s, - IPQ_MUX_pdm, - IPQ_MUX_ssbi, - IPQ_MUX_spmi, - IPQ_MUX_audio_pcm, - IPQ_MUX_gsbi1, - IPQ_MUX_gsbi2, - IPQ_MUX_gsbi4, - IPQ_MUX_gsbi5, - IPQ_MUX_gsbi5_spi_cs1, - IPQ_MUX_gsbi5_spi_cs2, - IPQ_MUX_gsbi5_spi_cs3, - IPQ_MUX_gsbi6, - IPQ_MUX_gsbi7, - IPQ_MUX_nss_spi, - IPQ_MUX_sdc1, - IPQ_MUX_spdif, - IPQ_MUX_nand, - IPQ_MUX_tsif1, - IPQ_MUX_tsif2, - IPQ_MUX_usb_fs_n, - IPQ_MUX_usb_fs, - IPQ_MUX_usb2_hsic, - IPQ_MUX_rgmii2, - IPQ_MUX_sata, - IPQ_MUX_pcie1_rst, - IPQ_MUX_pcie1_prsnt, - IPQ_MUX_pcie1_pwrflt, - IPQ_MUX_pcie1_pwren_n, - IPQ_MUX_pcie1_pwren, - IPQ_MUX_pcie1_clk_req, - IPQ_MUX_pcie2_rst, - IPQ_MUX_pcie2_prsnt, - IPQ_MUX_pcie2_pwrflt, - IPQ_MUX_pcie2_pwren_n, - IPQ_MUX_pcie2_pwren, - IPQ_MUX_pcie2_clk_req, - IPQ_MUX_pcie3_rst, - IPQ_MUX_pcie3_prsnt, - IPQ_MUX_pcie3_pwrflt, - IPQ_MUX_pcie3_pwren_n, - IPQ_MUX_pcie3_pwren, - IPQ_MUX_pcie3_clk_req, - IPQ_MUX_ps_hold, - IPQ_MUX_NA, -}; - -static const char * const mdio_groups[] = { - "gpio0", "gpio1", "gpio10", "gpio11", -}; - -static const char * const mi2s_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio33", "gpio55", "gpio56", "gpio57", "gpio58", -}; - -static const char * const pdm_groups[] = { - "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31", - "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58", - "gpio59", -}; - -static const char * const ssbi_groups[] = { - "gpio10", "gpio11", -}; - -static const char * const spmi_groups[] = { - "gpio10", "gpio11", -}; - -static const char * const audio_pcm_groups[] = { - "gpio14", "gpio15", "gpio16", "gpio17", -}; - -static const char * const gsbi1_groups[] = { - "gpio51", "gpio52", "gpio53", "gpio54", -}; - -static const char * const gsbi2_groups[] = { - "gpio22", "gpio23", "gpio24", "gpio25", -}; - -static const char * const gsbi4_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13", -}; - -static const char * const gsbi5_groups[] = { - "gpio18", "gpio19", "gpio20", "gpio21", -}; - -static const char * const gsbi5_spi_cs1_groups[] = { - "gpio6", "gpio61", -}; - -static const char * const gsbi5_spi_cs2_groups[] = { - "gpio7", "gpio62", -}; - -static const char * const gsbi5_spi_cs3_groups[] = { - "gpio2", -}; - -static const char * const gsbi6_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56", - "gpio57", "gpio58", -}; - -static const char * const gsbi7_groups[] = { - "gpio6", "gpio7", "gpio8", "gpio9", -}; - -static const char * const nss_spi_groups[] = { - "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56", - "gpio57", "gpio58", -}; - -static const char * const sdc1_groups[] = { - "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", - "gpio44", "gpio45", "gpio46", "gpio47", -}; - -static const char * const spdif_groups[] = { - "gpio10", "gpio48", -}; - -static const char * const nand_groups[] = { - "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", - "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47", -}; - -static const char * const tsif1_groups[] = { - "gpio55", "gpio56", "gpio57", "gpio58", -}; - -static const char * const tsif2_groups[] = { - "gpio59", "gpio60", "gpio61", "gpio62", -}; - -static const char * const usb_fs_n_groups[] = { - "gpio6", -}; - -static const char * const usb_fs_groups[] = { - "gpio6", "gpio7", "gpio8", -}; - -static const char * const usb2_hsic_groups[] = { - "gpio67", "gpio68", -}; - -static const char * const rgmii2_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", -}; - -static const char * const sata_groups[] = { - "gpio10", -}; - -static const char * const pcie1_rst_groups[] = { - "gpio3", -}; - -static const char * const pcie1_prsnt_groups[] = { - "gpio3", "gpio11", -}; - -static const char * const pcie1_pwren_n_groups[] = { - "gpio4", "gpio12", -}; - -static const char * const pcie1_pwren_groups[] = { - "gpio4", "gpio12", -}; - -static const char * const pcie1_pwrflt_groups[] = { - "gpio5", "gpio13", -}; - -static const char * const pcie1_clk_req_groups[] = { - "gpio5", -}; - -static const char * const pcie2_rst_groups[] = { - "gpio48", -}; - -static const char * const pcie2_prsnt_groups[] = { - "gpio11", "gpio48", -}; - -static const char * const pcie2_pwren_n_groups[] = { - "gpio12", "gpio49", -}; - -static const char * const pcie2_pwren_groups[] = { - "gpio12", "gpio49", -}; - -static const char * const pcie2_pwrflt_groups[] = { - "gpio13", "gpio50", -}; - -static const char * const pcie2_clk_req_groups[] = { - "gpio50", -}; - -static const char * const pcie3_rst_groups[] = { - "gpio63", -}; - -static const char * const pcie3_prsnt_groups[] = { - "gpio11", -}; - -static const char * const pcie3_pwren_n_groups[] = { - "gpio12", -}; - -static const char * const pcie3_pwren_groups[] = { - "gpio12", -}; - -static const char * const pcie3_pwrflt_groups[] = { - "gpio13", -}; - -static const char * const pcie3_clk_req_groups[] = { - "gpio65", -}; - -static const char * const ps_hold_groups[] = { - "gpio26", -}; - -static const struct msm_function ipq8064_functions[] = { - FUNCTION(mdio), - FUNCTION(ssbi), - FUNCTION(spmi), - FUNCTION(mi2s), - FUNCTION(pdm), - FUNCTION(audio_pcm), - FUNCTION(gsbi1), - FUNCTION(gsbi2), - FUNCTION(gsbi4), - FUNCTION(gsbi5), - FUNCTION(gsbi5_spi_cs1), - FUNCTION(gsbi5_spi_cs2), - FUNCTION(gsbi5_spi_cs3), - FUNCTION(gsbi6), - FUNCTION(gsbi7), - FUNCTION(nss_spi), - FUNCTION(sdc1), - FUNCTION(spdif), - FUNCTION(nand), - FUNCTION(tsif1), - FUNCTION(tsif2), - FUNCTION(usb_fs_n), - FUNCTION(usb_fs), - FUNCTION(usb2_hsic), - FUNCTION(rgmii2), - FUNCTION(sata), - FUNCTION(pcie1_rst), - FUNCTION(pcie1_prsnt), - FUNCTION(pcie1_pwren_n), - FUNCTION(pcie1_pwren), - FUNCTION(pcie1_pwrflt), - FUNCTION(pcie1_clk_req), - FUNCTION(pcie2_rst), - FUNCTION(pcie2_prsnt), - FUNCTION(pcie2_pwren_n), - FUNCTION(pcie2_pwren), - FUNCTION(pcie2_pwrflt), - FUNCTION(pcie2_clk_req), - FUNCTION(pcie3_rst), - FUNCTION(pcie3_prsnt), - FUNCTION(pcie3_pwren_n), - FUNCTION(pcie3_pwren), - FUNCTION(pcie3_pwrflt), - FUNCTION(pcie3_clk_req), - FUNCTION(ps_hold), -}; - -static const struct msm_pingroup ipq8064_groups[] = { - PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA), - PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA), - PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA), - PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA), - PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA), - PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA), - PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), - PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), - PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA), - PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), - PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), - SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3), - SDC_PINGROUP(sdc3_data, 0x204a, 9, 0), -}; - -#define NUM_GPIO_PINGROUPS 69 - -static const struct msm_pinctrl_soc_data ipq8064_pinctrl = { - .pins = ipq8064_pins, - .npins = ARRAY_SIZE(ipq8064_pins), - .functions = ipq8064_functions, - .nfunctions = ARRAY_SIZE(ipq8064_functions), - .groups = ipq8064_groups, - .ngroups = ARRAY_SIZE(ipq8064_groups), - .ngpios = NUM_GPIO_PINGROUPS, -}; - -static int ipq8064_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &ipq8064_pinctrl); -} - -static const struct of_device_id ipq8064_pinctrl_of_match[] = { - { .compatible = "qcom,ipq8064-pinctrl", }, - { }, -}; - -static struct platform_driver ipq8064_pinctrl_driver = { - .driver = { - .name = "ipq8064-pinctrl", - .owner = THIS_MODULE, - .of_match_table = ipq8064_pinctrl_of_match, - }, - .probe = ipq8064_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init ipq8064_pinctrl_init(void) -{ - return platform_driver_register(&ipq8064_pinctrl_driver); -} -arch_initcall(ipq8064_pinctrl_init); - -static void __exit ipq8064_pinctrl_exit(void) -{ - platform_driver_unregister(&ipq8064_pinctrl_driver); -} -module_exit(ipq8064_pinctrl_exit); - -MODULE_AUTHOR("Andy Gross "); -MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c deleted file mode 100644 index 43d47b7cff92..000000000000 --- a/drivers/pinctrl/pinctrl-msm.c +++ /dev/null @@ -1,922 +0,0 @@ -/* - * Copyright (c) 2013, Sony Mobile Communications AB. - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" -#include "pinconf.h" -#include "pinctrl-msm.h" -#include "pinctrl-utils.h" - -#define MAX_NR_GPIO 300 - -/** - * struct msm_pinctrl - state for a pinctrl-msm device - * @dev: device handle. - * @pctrl: pinctrl handle. - * @chip: gpiochip handle. - * @irq: parent irq for the TLMM irq_chip. - * @lock: Spinlock to protect register resources as well - * as msm_pinctrl data structures. - * @enabled_irqs: Bitmap of currently enabled irqs. - * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge - * detection. - * @soc; Reference to soc_data of platform specific data. - * @regs: Base address for the TLMM register map. - */ -struct msm_pinctrl { - struct device *dev; - struct pinctrl_dev *pctrl; - struct gpio_chip chip; - int irq; - - spinlock_t lock; - - DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); - DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); - - const struct msm_pinctrl_soc_data *soc; - void __iomem *regs; -}; - -static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) -{ - return container_of(gc, struct msm_pinctrl, chip); -} - -static int msm_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->ngroups; -} - -static const char *msm_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->groups[group].name; -} - -static int msm_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, - const unsigned **pins, - unsigned *num_pins) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *pins = pctrl->soc->groups[group].pins; - *num_pins = pctrl->soc->groups[group].npins; - return 0; -} - -static const struct pinctrl_ops msm_pinctrl_ops = { - .get_groups_count = msm_get_groups_count, - .get_group_name = msm_get_group_name, - .get_group_pins = msm_get_group_pins, - .dt_node_to_map = pinconf_generic_dt_node_to_map_group, - .dt_free_map = pinctrl_utils_dt_free_map, -}; - -static int msm_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->nfunctions; -} - -static const char *msm_get_function_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->functions[function].name; -} - -static int msm_get_function_groups(struct pinctrl_dev *pctldev, - unsigned function, - const char * const **groups, - unsigned * const num_groups) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctrl->soc->functions[function].groups; - *num_groups = pctrl->soc->functions[function].ngroups; - return 0; -} - -static int msm_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - int i; - - g = &pctrl->soc->groups[group]; - - if (WARN_ON(g->mux_bit < 0)) - return -EINVAL; - - for (i = 0; i < g->nfuncs; i++) { - if (g->funcs[i] == function) - break; - } - - if (WARN_ON(i == g->nfuncs)) - return -EINVAL; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->ctl_reg); - val &= ~(0x7 << g->mux_bit); - val |= i << g->mux_bit; - writel(val, pctrl->regs + g->ctl_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - -static const struct pinmux_ops msm_pinmux_ops = { - .get_functions_count = msm_get_functions_count, - .get_function_name = msm_get_function_name, - .get_function_groups = msm_get_function_groups, - .enable = msm_pinmux_enable, -}; - -static int msm_config_reg(struct msm_pinctrl *pctrl, - const struct msm_pingroup *g, - unsigned param, - unsigned *mask, - unsigned *bit) -{ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_BUS_HOLD: - case PIN_CONFIG_BIAS_PULL_UP: - *bit = g->pull_bit; - *mask = 3; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - *bit = g->drv_bit; - *mask = 7; - break; - case PIN_CONFIG_OUTPUT: - *bit = g->oe_bit; - *mask = 1; - break; - default: - dev_err(pctrl->dev, "Invalid config param %04x\n", param); - return -ENOTSUPP; - } - - return 0; -} - -static int msm_config_get(struct pinctrl_dev *pctldev, - unsigned int pin, - unsigned long *config) -{ - dev_err(pctldev->dev, "pin_config_set op not supported\n"); - return -ENOTSUPP; -} - -static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned num_configs) -{ - dev_err(pctldev->dev, "pin_config_set op not supported\n"); - return -ENOTSUPP; -} - -#define MSM_NO_PULL 0 -#define MSM_PULL_DOWN 1 -#define MSM_KEEPER 2 -#define MSM_PULL_UP 3 - -static unsigned msm_regval_to_drive(u32 val) -{ - return (val + 1) * 2; -} - -static int msm_config_group_get(struct pinctrl_dev *pctldev, - unsigned int group, - unsigned long *config) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned param = pinconf_to_config_param(*config); - unsigned mask; - unsigned arg; - unsigned bit; - int ret; - u32 val; - - g = &pctrl->soc->groups[group]; - - ret = msm_config_reg(pctrl, g, param, &mask, &bit); - if (ret < 0) - return ret; - - val = readl(pctrl->regs + g->ctl_reg); - arg = (val >> bit) & mask; - - /* Convert register value to pinconf value */ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - arg = arg == MSM_NO_PULL; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - arg = arg == MSM_PULL_DOWN; - break; - case PIN_CONFIG_BIAS_BUS_HOLD: - arg = arg == MSM_KEEPER; - break; - case PIN_CONFIG_BIAS_PULL_UP: - arg = arg == MSM_PULL_UP; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - arg = msm_regval_to_drive(arg); - break; - case PIN_CONFIG_OUTPUT: - /* Pin is not output */ - if (!arg) - return -EINVAL; - - val = readl(pctrl->regs + g->io_reg); - arg = !!(val & BIT(g->in_bit)); - break; - default: - dev_err(pctrl->dev, "Unsupported config parameter: %x\n", - param); - return -EINVAL; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int msm_config_group_set(struct pinctrl_dev *pctldev, - unsigned group, - unsigned long *configs, - unsigned num_configs) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned long flags; - unsigned param; - unsigned mask; - unsigned arg; - unsigned bit; - int ret; - u32 val; - int i; - - g = &pctrl->soc->groups[group]; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - ret = msm_config_reg(pctrl, g, param, &mask, &bit); - if (ret < 0) - return ret; - - /* Convert pinconf values to register values */ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - arg = MSM_NO_PULL; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - arg = MSM_PULL_DOWN; - break; - case PIN_CONFIG_BIAS_BUS_HOLD: - arg = MSM_KEEPER; - break; - case PIN_CONFIG_BIAS_PULL_UP: - arg = MSM_PULL_UP; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - /* Check for invalid values */ - if (arg > 16 || arg < 2 || (arg % 2) != 0) - arg = -1; - else - arg = (arg / 2) - 1; - break; - case PIN_CONFIG_OUTPUT: - /* set output value */ - spin_lock_irqsave(&pctrl->lock, flags); - val = readl(pctrl->regs + g->io_reg); - if (arg) - val |= BIT(g->out_bit); - else - val &= ~BIT(g->out_bit); - writel(val, pctrl->regs + g->io_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); - - /* enable output */ - arg = 1; - break; - default: - dev_err(pctrl->dev, "Unsupported config parameter: %x\n", - param); - return -EINVAL; - } - - /* Range-check user-supplied value */ - if (arg & ~mask) { - dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); - return -EINVAL; - } - - spin_lock_irqsave(&pctrl->lock, flags); - val = readl(pctrl->regs + g->ctl_reg); - val &= ~(mask << bit); - val |= arg << bit; - writel(val, pctrl->regs + g->ctl_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); - } - - return 0; -} - -static const struct pinconf_ops msm_pinconf_ops = { - .pin_config_get = msm_config_get, - .pin_config_set = msm_config_set, - .pin_config_group_get = msm_config_group_get, - .pin_config_group_set = msm_config_group_set, -}; - -static struct pinctrl_desc msm_pinctrl_desc = { - .pctlops = &msm_pinctrl_ops, - .pmxops = &msm_pinmux_ops, - .confops = &msm_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[offset]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->ctl_reg); - val &= ~BIT(g->oe_bit); - writel(val, pctrl->regs + g->ctl_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - -static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[offset]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->io_reg); - if (value) - val |= BIT(g->out_bit); - else - val &= ~BIT(g->out_bit); - writel(val, pctrl->regs + g->io_reg); - - val = readl(pctrl->regs + g->ctl_reg); - val |= BIT(g->oe_bit); - writel(val, pctrl->regs + g->ctl_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - -static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - u32 val; - - g = &pctrl->soc->groups[offset]; - - val = readl(pctrl->regs + g->io_reg); - return !!(val & BIT(g->in_bit)); -} - -static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[offset]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->io_reg); - if (value) - val |= BIT(g->out_bit); - else - val &= ~BIT(g->out_bit); - writel(val, pctrl->regs + g->io_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - -static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - return pinctrl_request_gpio(gpio); -} - -static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - return pinctrl_free_gpio(gpio); -} - -#ifdef CONFIG_DEBUG_FS -#include - -static void msm_gpio_dbg_show_one(struct seq_file *s, - struct pinctrl_dev *pctldev, - struct gpio_chip *chip, - unsigned offset, - unsigned gpio) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - unsigned func; - int is_out; - int drive; - int pull; - u32 ctl_reg; - - static const char * const pulls[] = { - "no pull", - "pull down", - "keeper", - "pull up" - }; - - g = &pctrl->soc->groups[offset]; - ctl_reg = readl(pctrl->regs + g->ctl_reg); - - is_out = !!(ctl_reg & BIT(g->oe_bit)); - func = (ctl_reg >> g->mux_bit) & 7; - drive = (ctl_reg >> g->drv_bit) & 7; - pull = (ctl_reg >> g->pull_bit) & 3; - - seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); - seq_printf(s, " %dmA", msm_regval_to_drive(drive)); - seq_printf(s, " %s", pulls[pull]); -} - -static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - unsigned gpio = chip->base; - unsigned i; - - for (i = 0; i < chip->ngpio; i++, gpio++) { - msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); - seq_puts(s, "\n"); - } -} - -#else -#define msm_gpio_dbg_show NULL -#endif - -static struct gpio_chip msm_gpio_template = { - .direction_input = msm_gpio_direction_input, - .direction_output = msm_gpio_direction_output, - .get = msm_gpio_get, - .set = msm_gpio_set, - .request = msm_gpio_request, - .free = msm_gpio_free, - .dbg_show = msm_gpio_dbg_show, -}; - -/* For dual-edge interrupts in software, since some hardware has no - * such support: - * - * At appropriate moments, this function may be called to flip the polarity - * settings of both-edge irq lines to try and catch the next edge. - * - * The attempt is considered successful if: - * - the status bit goes high, indicating that an edge was caught, or - * - the input value of the gpio doesn't change during the attempt. - * If the value changes twice during the process, that would cause the first - * test to fail but would force the second, as two opposite - * transitions would cause a detection no matter the polarity setting. - * - * The do-loop tries to sledge-hammer closed the timing hole between - * the initial value-read and the polarity-write - if the line value changes - * during that window, an interrupt is lost, the new polarity setting is - * incorrect, and the first success test will fail, causing a retry. - * - * Algorithm comes from Google's msmgpio driver. - */ -static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, - const struct msm_pingroup *g, - struct irq_data *d) -{ - int loop_limit = 100; - unsigned val, val2, intstat; - unsigned pol; - - do { - val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); - - pol = readl(pctrl->regs + g->intr_cfg_reg); - pol ^= BIT(g->intr_polarity_bit); - writel(pol, pctrl->regs + g->intr_cfg_reg); - - val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); - intstat = readl(pctrl->regs + g->intr_status_reg); - if (intstat || (val == val2)) - return; - } while (loop_limit-- > 0); - dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", - val, val2); -} - -static void msm_gpio_irq_mask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[d->hwirq]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->intr_cfg_reg); - val &= ~BIT(g->intr_enable_bit); - writel(val, pctrl->regs + g->intr_cfg_reg); - - clear_bit(d->hwirq, pctrl->enabled_irqs); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - -static void msm_gpio_irq_unmask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[d->hwirq]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->intr_status_reg); - val &= ~BIT(g->intr_status_bit); - writel(val, pctrl->regs + g->intr_status_reg); - - val = readl(pctrl->regs + g->intr_cfg_reg); - val |= BIT(g->intr_enable_bit); - writel(val, pctrl->regs + g->intr_cfg_reg); - - set_bit(d->hwirq, pctrl->enabled_irqs); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - -static void msm_gpio_irq_ack(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[d->hwirq]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->intr_status_reg); - if (g->intr_ack_high) - val |= BIT(g->intr_status_bit); - else - val &= ~BIT(g->intr_status_bit); - writel(val, pctrl->regs + g->intr_status_reg); - - if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) - msm_gpio_update_dual_edge_pos(pctrl, g, d); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - -#define INTR_TARGET_PROC_APPS 4 - -static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[d->hwirq]; - - spin_lock_irqsave(&pctrl->lock, flags); - - /* - * For hw without possibility of detecting both edges - */ - if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) - set_bit(d->hwirq, pctrl->dual_edge_irqs); - else - clear_bit(d->hwirq, pctrl->dual_edge_irqs); - - /* Route interrupts to application cpu */ - val = readl(pctrl->regs + g->intr_target_reg); - val &= ~(7 << g->intr_target_bit); - val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; - writel(val, pctrl->regs + g->intr_target_reg); - - /* Update configuration for gpio. - * RAW_STATUS_EN is left on for all gpio irqs. Due to the - * internal circuitry of TLMM, toggling the RAW_STATUS - * could cause the INTR_STATUS to be set for EDGE interrupts. - */ - val = readl(pctrl->regs + g->intr_cfg_reg); - val |= BIT(g->intr_raw_status_bit); - if (g->intr_detection_width == 2) { - val &= ~(3 << g->intr_detection_bit); - val &= ~(1 << g->intr_polarity_bit); - switch (type) { - case IRQ_TYPE_EDGE_RISING: - val |= 1 << g->intr_detection_bit; - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_EDGE_FALLING: - val |= 2 << g->intr_detection_bit; - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_EDGE_BOTH: - val |= 3 << g->intr_detection_bit; - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_LEVEL_LOW: - break; - case IRQ_TYPE_LEVEL_HIGH: - val |= BIT(g->intr_polarity_bit); - break; - } - } else if (g->intr_detection_width == 1) { - val &= ~(1 << g->intr_detection_bit); - val &= ~(1 << g->intr_polarity_bit); - switch (type) { - case IRQ_TYPE_EDGE_RISING: - val |= BIT(g->intr_detection_bit); - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_EDGE_FALLING: - val |= BIT(g->intr_detection_bit); - break; - case IRQ_TYPE_EDGE_BOTH: - val |= BIT(g->intr_detection_bit); - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_LEVEL_LOW: - break; - case IRQ_TYPE_LEVEL_HIGH: - val |= BIT(g->intr_polarity_bit); - break; - } - } else { - BUG(); - } - writel(val, pctrl->regs + g->intr_cfg_reg); - - if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) - msm_gpio_update_dual_edge_pos(pctrl, g, d); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __irq_set_handler_locked(d->irq, handle_level_irq); - else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __irq_set_handler_locked(d->irq, handle_edge_irq); - - return 0; -} - -static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - unsigned long flags; - - spin_lock_irqsave(&pctrl->lock, flags); - - irq_set_irq_wake(pctrl->irq, on); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - -static struct irq_chip msm_gpio_irq_chip = { - .name = "msmgpio", - .irq_mask = msm_gpio_irq_mask, - .irq_unmask = msm_gpio_irq_unmask, - .irq_ack = msm_gpio_irq_ack, - .irq_set_type = msm_gpio_irq_set_type, - .irq_set_wake = msm_gpio_irq_set_wake, -}; - -static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - struct irq_chip *chip = irq_get_chip(irq); - int irq_pin; - int handled = 0; - u32 val; - int i; - - chained_irq_enter(chip, desc); - - /* - * Each pin has it's own IRQ status register, so use - * enabled_irq bitmap to limit the number of reads. - */ - for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { - g = &pctrl->soc->groups[i]; - val = readl(pctrl->regs + g->intr_status_reg); - if (val & BIT(g->intr_status_bit)) { - irq_pin = irq_find_mapping(gc->irqdomain, i); - generic_handle_irq(irq_pin); - handled++; - } - } - - /* No interrupts were flagged */ - if (handled == 0) - handle_bad_irq(irq, desc); - - chained_irq_exit(chip, desc); -} - -static int msm_gpio_init(struct msm_pinctrl *pctrl) -{ - struct gpio_chip *chip; - int ret; - unsigned ngpio = pctrl->soc->ngpios; - - if (WARN_ON(ngpio > MAX_NR_GPIO)) - return -EINVAL; - - chip = &pctrl->chip; - chip->base = 0; - chip->ngpio = ngpio; - chip->label = dev_name(pctrl->dev); - chip->dev = pctrl->dev; - chip->owner = THIS_MODULE; - chip->of_node = pctrl->dev->of_node; - - ret = gpiochip_add(&pctrl->chip); - if (ret) { - dev_err(pctrl->dev, "Failed register gpiochip\n"); - return ret; - } - - ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); - if (ret) { - dev_err(pctrl->dev, "Failed to add pin range\n"); - return ret; - } - - ret = gpiochip_irqchip_add(chip, - &msm_gpio_irq_chip, - 0, - handle_edge_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); - return -ENOSYS; - } - - gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, - msm_gpio_irq_handler); - - return 0; -} - -int msm_pinctrl_probe(struct platform_device *pdev, - const struct msm_pinctrl_soc_data *soc_data) -{ - struct msm_pinctrl *pctrl; - struct resource *res; - int ret; - - pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); - if (!pctrl) { - dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); - return -ENOMEM; - } - pctrl->dev = &pdev->dev; - pctrl->soc = soc_data; - pctrl->chip = msm_gpio_template; - - spin_lock_init(&pctrl->lock); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pctrl->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pctrl->regs)) - return PTR_ERR(pctrl->regs); - - pctrl->irq = platform_get_irq(pdev, 0); - if (pctrl->irq < 0) { - dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); - return pctrl->irq; - } - - msm_pinctrl_desc.name = dev_name(&pdev->dev); - msm_pinctrl_desc.pins = pctrl->soc->pins; - msm_pinctrl_desc.npins = pctrl->soc->npins; - pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); - if (!pctrl->pctrl) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; - } - - ret = msm_gpio_init(pctrl); - if (ret) { - pinctrl_unregister(pctrl->pctrl); - return ret; - } - - platform_set_drvdata(pdev, pctrl); - - dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); - - return 0; -} -EXPORT_SYMBOL(msm_pinctrl_probe); - -int msm_pinctrl_remove(struct platform_device *pdev) -{ - struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); - int ret; - - ret = gpiochip_remove(&pctrl->chip); - if (ret) { - dev_err(&pdev->dev, "Failed to remove gpiochip\n"); - return ret; - } - - pinctrl_unregister(pctrl->pctrl); - - return 0; -} -EXPORT_SYMBOL(msm_pinctrl_remove); - diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/pinctrl-msm.h deleted file mode 100644 index 7b2a227a590a..000000000000 --- a/drivers/pinctrl/pinctrl-msm.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2013, Sony Mobile Communications AB. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __PINCTRL_MSM_H__ -#define __PINCTRL_MSM_H__ - -struct pinctrl_pin_desc; - -/** - * struct msm_function - a pinmux function - * @name: Name of the pinmux function. - * @groups: List of pingroups for this function. - * @ngroups: Number of entries in @groups. - */ -struct msm_function { - const char *name; - const char * const *groups; - unsigned ngroups; -}; - -/** - * struct msm_pingroup - Qualcomm pingroup definition - * @name: Name of the pingroup. - * @pins: A list of pins assigned to this pingroup. - * @npins: Number of entries in @pins. - * @funcs: A list of pinmux functions that can be selected for - * this group. The index of the selected function is used - * for programming the function selector. - * Entries should be indices into the groups list of the - * struct msm_pinctrl_soc_data. - * @ctl_reg: Offset of the register holding control bits for this group. - * @io_reg: Offset of the register holding input/output bits for this group. - * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. - * @intr_status_reg: Offset of the register holding the status bits for this group. - * @intr_target_reg: Offset of the register specifying routing of the interrupts - * from this group. - * @mux_bit: Offset in @ctl_reg for the pinmux function selection. - * @pull_bit: Offset in @ctl_reg for the bias configuration. - * @drv_bit: Offset in @ctl_reg for the drive strength configuration. - * @oe_bit: Offset in @ctl_reg for controlling output enable. - * @in_bit: Offset in @io_reg for the input bit value. - * @out_bit: Offset in @io_reg for the output bit value. - * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. - * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt - * status. - * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. - * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. - * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. - * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. - * @intr_detection_width: Number of bits used for specifying interrupt type, - * Should be 2 for SoCs that can detect both edges in hardware, - * otherwise 1. - */ -struct msm_pingroup { - const char *name; - const unsigned *pins; - unsigned npins; - - unsigned *funcs; - unsigned nfuncs; - - s16 ctl_reg; - s16 io_reg; - s16 intr_cfg_reg; - s16 intr_status_reg; - s16 intr_target_reg; - - unsigned mux_bit:5; - - unsigned pull_bit:5; - unsigned drv_bit:5; - - unsigned oe_bit:5; - unsigned in_bit:5; - unsigned out_bit:5; - - unsigned intr_enable_bit:5; - unsigned intr_status_bit:5; - unsigned intr_ack_high:1; - - unsigned intr_target_bit:5; - unsigned intr_raw_status_bit:5; - unsigned intr_polarity_bit:5; - unsigned intr_detection_bit:5; - unsigned intr_detection_width:5; -}; - -/** - * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration - * @pins: An array describing all pins the pin controller affects. - * @npins: The number of entries in @pins. - * @functions: An array describing all mux functions the SoC supports. - * @nfunctions: The number of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The numbmer of entries in @groups. - * @ngpio: The number of pingroups the driver should expose as GPIOs. - */ -struct msm_pinctrl_soc_data { - const struct pinctrl_pin_desc *pins; - unsigned npins; - const struct msm_function *functions; - unsigned nfunctions; - const struct msm_pingroup *groups; - unsigned ngroups; - unsigned ngpios; -}; - -int msm_pinctrl_probe(struct platform_device *pdev, - const struct msm_pinctrl_soc_data *soc_data); -int msm_pinctrl_remove(struct platform_device *pdev); - -#endif diff --git a/drivers/pinctrl/pinctrl-msm8960.c b/drivers/pinctrl/pinctrl-msm8960.c deleted file mode 100644 index 564543bb2c1c..000000000000 --- a/drivers/pinctrl/pinctrl-msm8960.c +++ /dev/null @@ -1,1254 +0,0 @@ -/* - * Copyright (c) 2014, Sony Mobile Communications AB. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -static const struct pinctrl_pin_desc msm8960_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - PINCTRL_PIN(69, "GPIO_69"), - PINCTRL_PIN(70, "GPIO_70"), - PINCTRL_PIN(71, "GPIO_71"), - PINCTRL_PIN(72, "GPIO_72"), - PINCTRL_PIN(73, "GPIO_73"), - PINCTRL_PIN(74, "GPIO_74"), - PINCTRL_PIN(75, "GPIO_75"), - PINCTRL_PIN(76, "GPIO_76"), - PINCTRL_PIN(77, "GPIO_77"), - PINCTRL_PIN(78, "GPIO_78"), - PINCTRL_PIN(79, "GPIO_79"), - PINCTRL_PIN(80, "GPIO_80"), - PINCTRL_PIN(81, "GPIO_81"), - PINCTRL_PIN(82, "GPIO_82"), - PINCTRL_PIN(83, "GPIO_83"), - PINCTRL_PIN(84, "GPIO_84"), - PINCTRL_PIN(85, "GPIO_85"), - PINCTRL_PIN(86, "GPIO_86"), - PINCTRL_PIN(87, "GPIO_87"), - PINCTRL_PIN(88, "GPIO_88"), - PINCTRL_PIN(89, "GPIO_89"), - PINCTRL_PIN(90, "GPIO_90"), - PINCTRL_PIN(91, "GPIO_91"), - PINCTRL_PIN(92, "GPIO_92"), - PINCTRL_PIN(93, "GPIO_93"), - PINCTRL_PIN(94, "GPIO_94"), - PINCTRL_PIN(95, "GPIO_95"), - PINCTRL_PIN(96, "GPIO_96"), - PINCTRL_PIN(97, "GPIO_97"), - PINCTRL_PIN(98, "GPIO_98"), - PINCTRL_PIN(99, "GPIO_99"), - PINCTRL_PIN(100, "GPIO_100"), - PINCTRL_PIN(101, "GPIO_101"), - PINCTRL_PIN(102, "GPIO_102"), - PINCTRL_PIN(103, "GPIO_103"), - PINCTRL_PIN(104, "GPIO_104"), - PINCTRL_PIN(105, "GPIO_105"), - PINCTRL_PIN(106, "GPIO_106"), - PINCTRL_PIN(107, "GPIO_107"), - PINCTRL_PIN(108, "GPIO_108"), - PINCTRL_PIN(109, "GPIO_109"), - PINCTRL_PIN(110, "GPIO_110"), - PINCTRL_PIN(111, "GPIO_111"), - PINCTRL_PIN(112, "GPIO_112"), - PINCTRL_PIN(113, "GPIO_113"), - PINCTRL_PIN(114, "GPIO_114"), - PINCTRL_PIN(115, "GPIO_115"), - PINCTRL_PIN(116, "GPIO_116"), - PINCTRL_PIN(117, "GPIO_117"), - PINCTRL_PIN(118, "GPIO_118"), - PINCTRL_PIN(119, "GPIO_119"), - PINCTRL_PIN(120, "GPIO_120"), - PINCTRL_PIN(121, "GPIO_121"), - PINCTRL_PIN(122, "GPIO_122"), - PINCTRL_PIN(123, "GPIO_123"), - PINCTRL_PIN(124, "GPIO_124"), - PINCTRL_PIN(125, "GPIO_125"), - PINCTRL_PIN(126, "GPIO_126"), - PINCTRL_PIN(127, "GPIO_127"), - PINCTRL_PIN(128, "GPIO_128"), - PINCTRL_PIN(129, "GPIO_129"), - PINCTRL_PIN(130, "GPIO_130"), - PINCTRL_PIN(131, "GPIO_131"), - PINCTRL_PIN(132, "GPIO_132"), - PINCTRL_PIN(133, "GPIO_133"), - PINCTRL_PIN(134, "GPIO_134"), - PINCTRL_PIN(135, "GPIO_135"), - PINCTRL_PIN(136, "GPIO_136"), - PINCTRL_PIN(137, "GPIO_137"), - PINCTRL_PIN(138, "GPIO_138"), - PINCTRL_PIN(139, "GPIO_139"), - PINCTRL_PIN(140, "GPIO_140"), - PINCTRL_PIN(141, "GPIO_141"), - PINCTRL_PIN(142, "GPIO_142"), - PINCTRL_PIN(143, "GPIO_143"), - PINCTRL_PIN(144, "GPIO_144"), - PINCTRL_PIN(145, "GPIO_145"), - PINCTRL_PIN(146, "GPIO_146"), - PINCTRL_PIN(147, "GPIO_147"), - PINCTRL_PIN(148, "GPIO_148"), - PINCTRL_PIN(149, "GPIO_149"), - PINCTRL_PIN(150, "GPIO_150"), - PINCTRL_PIN(151, "GPIO_151"), - - PINCTRL_PIN(152, "SDC1_CLK"), - PINCTRL_PIN(153, "SDC1_CMD"), - PINCTRL_PIN(154, "SDC1_DATA"), - PINCTRL_PIN(155, "SDC3_CLK"), - PINCTRL_PIN(156, "SDC3_CMD"), - PINCTRL_PIN(157, "SDC3_DATA"), -}; - -#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_MSM_GPIO_PINS(0); -DECLARE_MSM_GPIO_PINS(1); -DECLARE_MSM_GPIO_PINS(2); -DECLARE_MSM_GPIO_PINS(3); -DECLARE_MSM_GPIO_PINS(4); -DECLARE_MSM_GPIO_PINS(5); -DECLARE_MSM_GPIO_PINS(6); -DECLARE_MSM_GPIO_PINS(7); -DECLARE_MSM_GPIO_PINS(8); -DECLARE_MSM_GPIO_PINS(9); -DECLARE_MSM_GPIO_PINS(10); -DECLARE_MSM_GPIO_PINS(11); -DECLARE_MSM_GPIO_PINS(12); -DECLARE_MSM_GPIO_PINS(13); -DECLARE_MSM_GPIO_PINS(14); -DECLARE_MSM_GPIO_PINS(15); -DECLARE_MSM_GPIO_PINS(16); -DECLARE_MSM_GPIO_PINS(17); -DECLARE_MSM_GPIO_PINS(18); -DECLARE_MSM_GPIO_PINS(19); -DECLARE_MSM_GPIO_PINS(20); -DECLARE_MSM_GPIO_PINS(21); -DECLARE_MSM_GPIO_PINS(22); -DECLARE_MSM_GPIO_PINS(23); -DECLARE_MSM_GPIO_PINS(24); -DECLARE_MSM_GPIO_PINS(25); -DECLARE_MSM_GPIO_PINS(26); -DECLARE_MSM_GPIO_PINS(27); -DECLARE_MSM_GPIO_PINS(28); -DECLARE_MSM_GPIO_PINS(29); -DECLARE_MSM_GPIO_PINS(30); -DECLARE_MSM_GPIO_PINS(31); -DECLARE_MSM_GPIO_PINS(32); -DECLARE_MSM_GPIO_PINS(33); -DECLARE_MSM_GPIO_PINS(34); -DECLARE_MSM_GPIO_PINS(35); -DECLARE_MSM_GPIO_PINS(36); -DECLARE_MSM_GPIO_PINS(37); -DECLARE_MSM_GPIO_PINS(38); -DECLARE_MSM_GPIO_PINS(39); -DECLARE_MSM_GPIO_PINS(40); -DECLARE_MSM_GPIO_PINS(41); -DECLARE_MSM_GPIO_PINS(42); -DECLARE_MSM_GPIO_PINS(43); -DECLARE_MSM_GPIO_PINS(44); -DECLARE_MSM_GPIO_PINS(45); -DECLARE_MSM_GPIO_PINS(46); -DECLARE_MSM_GPIO_PINS(47); -DECLARE_MSM_GPIO_PINS(48); -DECLARE_MSM_GPIO_PINS(49); -DECLARE_MSM_GPIO_PINS(50); -DECLARE_MSM_GPIO_PINS(51); -DECLARE_MSM_GPIO_PINS(52); -DECLARE_MSM_GPIO_PINS(53); -DECLARE_MSM_GPIO_PINS(54); -DECLARE_MSM_GPIO_PINS(55); -DECLARE_MSM_GPIO_PINS(56); -DECLARE_MSM_GPIO_PINS(57); -DECLARE_MSM_GPIO_PINS(58); -DECLARE_MSM_GPIO_PINS(59); -DECLARE_MSM_GPIO_PINS(60); -DECLARE_MSM_GPIO_PINS(61); -DECLARE_MSM_GPIO_PINS(62); -DECLARE_MSM_GPIO_PINS(63); -DECLARE_MSM_GPIO_PINS(64); -DECLARE_MSM_GPIO_PINS(65); -DECLARE_MSM_GPIO_PINS(66); -DECLARE_MSM_GPIO_PINS(67); -DECLARE_MSM_GPIO_PINS(68); -DECLARE_MSM_GPIO_PINS(69); -DECLARE_MSM_GPIO_PINS(70); -DECLARE_MSM_GPIO_PINS(71); -DECLARE_MSM_GPIO_PINS(72); -DECLARE_MSM_GPIO_PINS(73); -DECLARE_MSM_GPIO_PINS(74); -DECLARE_MSM_GPIO_PINS(75); -DECLARE_MSM_GPIO_PINS(76); -DECLARE_MSM_GPIO_PINS(77); -DECLARE_MSM_GPIO_PINS(78); -DECLARE_MSM_GPIO_PINS(79); -DECLARE_MSM_GPIO_PINS(80); -DECLARE_MSM_GPIO_PINS(81); -DECLARE_MSM_GPIO_PINS(82); -DECLARE_MSM_GPIO_PINS(83); -DECLARE_MSM_GPIO_PINS(84); -DECLARE_MSM_GPIO_PINS(85); -DECLARE_MSM_GPIO_PINS(86); -DECLARE_MSM_GPIO_PINS(87); -DECLARE_MSM_GPIO_PINS(88); -DECLARE_MSM_GPIO_PINS(89); -DECLARE_MSM_GPIO_PINS(90); -DECLARE_MSM_GPIO_PINS(91); -DECLARE_MSM_GPIO_PINS(92); -DECLARE_MSM_GPIO_PINS(93); -DECLARE_MSM_GPIO_PINS(94); -DECLARE_MSM_GPIO_PINS(95); -DECLARE_MSM_GPIO_PINS(96); -DECLARE_MSM_GPIO_PINS(97); -DECLARE_MSM_GPIO_PINS(98); -DECLARE_MSM_GPIO_PINS(99); -DECLARE_MSM_GPIO_PINS(100); -DECLARE_MSM_GPIO_PINS(101); -DECLARE_MSM_GPIO_PINS(102); -DECLARE_MSM_GPIO_PINS(103); -DECLARE_MSM_GPIO_PINS(104); -DECLARE_MSM_GPIO_PINS(105); -DECLARE_MSM_GPIO_PINS(106); -DECLARE_MSM_GPIO_PINS(107); -DECLARE_MSM_GPIO_PINS(108); -DECLARE_MSM_GPIO_PINS(109); -DECLARE_MSM_GPIO_PINS(110); -DECLARE_MSM_GPIO_PINS(111); -DECLARE_MSM_GPIO_PINS(112); -DECLARE_MSM_GPIO_PINS(113); -DECLARE_MSM_GPIO_PINS(114); -DECLARE_MSM_GPIO_PINS(115); -DECLARE_MSM_GPIO_PINS(116); -DECLARE_MSM_GPIO_PINS(117); -DECLARE_MSM_GPIO_PINS(118); -DECLARE_MSM_GPIO_PINS(119); -DECLARE_MSM_GPIO_PINS(120); -DECLARE_MSM_GPIO_PINS(121); -DECLARE_MSM_GPIO_PINS(122); -DECLARE_MSM_GPIO_PINS(123); -DECLARE_MSM_GPIO_PINS(124); -DECLARE_MSM_GPIO_PINS(125); -DECLARE_MSM_GPIO_PINS(126); -DECLARE_MSM_GPIO_PINS(127); -DECLARE_MSM_GPIO_PINS(128); -DECLARE_MSM_GPIO_PINS(129); -DECLARE_MSM_GPIO_PINS(130); -DECLARE_MSM_GPIO_PINS(131); -DECLARE_MSM_GPIO_PINS(132); -DECLARE_MSM_GPIO_PINS(133); -DECLARE_MSM_GPIO_PINS(134); -DECLARE_MSM_GPIO_PINS(135); -DECLARE_MSM_GPIO_PINS(136); -DECLARE_MSM_GPIO_PINS(137); -DECLARE_MSM_GPIO_PINS(138); -DECLARE_MSM_GPIO_PINS(139); -DECLARE_MSM_GPIO_PINS(140); -DECLARE_MSM_GPIO_PINS(141); -DECLARE_MSM_GPIO_PINS(142); -DECLARE_MSM_GPIO_PINS(143); -DECLARE_MSM_GPIO_PINS(144); -DECLARE_MSM_GPIO_PINS(145); -DECLARE_MSM_GPIO_PINS(146); -DECLARE_MSM_GPIO_PINS(147); -DECLARE_MSM_GPIO_PINS(148); -DECLARE_MSM_GPIO_PINS(149); -DECLARE_MSM_GPIO_PINS(150); -DECLARE_MSM_GPIO_PINS(151); - -static const unsigned int sdc1_clk_pins[] = { 152 }; -static const unsigned int sdc1_cmd_pins[] = { 153 }; -static const unsigned int sdc1_data_pins[] = { 154 }; -static const unsigned int sdc3_clk_pins[] = { 155 }; -static const unsigned int sdc3_cmd_pins[] = { 156 }; -static const unsigned int sdc3_data_pins[] = { 157 }; - -#define FUNCTION(fname) \ - [MSM_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - MSM_MUX_NA, /* gpio mode */ \ - MSM_MUX_##f1, \ - MSM_MUX_##f2, \ - MSM_MUX_##f3, \ - MSM_MUX_##f4, \ - MSM_MUX_##f5, \ - MSM_MUX_##f6, \ - MSM_MUX_##f7, \ - MSM_MUX_##f8, \ - MSM_MUX_##f9, \ - MSM_MUX_##f10, \ - MSM_MUX_##f11 \ - }, \ - .nfuncs = 12, \ - .ctl_reg = 0x1000 + 0x10 * id, \ - .io_reg = 0x1004 + 0x10 * id, \ - .intr_cfg_reg = 0x1008 + 0x10 * id, \ - .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x400 + 0x4 * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_ack_high = 1, \ - .intr_target_bit = 0, \ - .intr_raw_status_bit = 3, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 1, \ - } - -#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -enum msm8960_functions { - MSM_MUX_audio_pcm, - MSM_MUX_bt, - MSM_MUX_cam_mclk0, - MSM_MUX_cam_mclk1, - MSM_MUX_cam_mclk2, - MSM_MUX_codec_mic_i2s, - MSM_MUX_codec_spkr_i2s, - MSM_MUX_ext_gps, - MSM_MUX_fm, - MSM_MUX_gps_blanking, - MSM_MUX_gps_pps_in, - MSM_MUX_gps_pps_out, - MSM_MUX_gp_clk_0a, - MSM_MUX_gp_clk_0b, - MSM_MUX_gp_clk_1a, - MSM_MUX_gp_clk_1b, - MSM_MUX_gp_clk_2a, - MSM_MUX_gp_clk_2b, - MSM_MUX_gp_mn, - MSM_MUX_gp_pdm_0a, - MSM_MUX_gp_pdm_0b, - MSM_MUX_gp_pdm_1a, - MSM_MUX_gp_pdm_1b, - MSM_MUX_gp_pdm_2a, - MSM_MUX_gp_pdm_2b, - MSM_MUX_gsbi1, - MSM_MUX_gsbi1_spi_cs1_n, - MSM_MUX_gsbi1_spi_cs2a_n, - MSM_MUX_gsbi1_spi_cs2b_n, - MSM_MUX_gsbi1_spi_cs3_n, - MSM_MUX_gsbi2, - MSM_MUX_gsbi2_spi_cs1_n, - MSM_MUX_gsbi2_spi_cs2_n, - MSM_MUX_gsbi2_spi_cs3_n, - MSM_MUX_gsbi3, - MSM_MUX_gsbi4, - MSM_MUX_gsbi4_3d_cam_i2c_l, - MSM_MUX_gsbi4_3d_cam_i2c_r, - MSM_MUX_gsbi5, - MSM_MUX_gsbi5_3d_cam_i2c_l, - MSM_MUX_gsbi5_3d_cam_i2c_r, - MSM_MUX_gsbi6, - MSM_MUX_gsbi7, - MSM_MUX_gsbi8, - MSM_MUX_gsbi9, - MSM_MUX_gsbi10, - MSM_MUX_gsbi11, - MSM_MUX_gsbi11_spi_cs1a_n, - MSM_MUX_gsbi11_spi_cs1b_n, - MSM_MUX_gsbi11_spi_cs2a_n, - MSM_MUX_gsbi11_spi_cs2b_n, - MSM_MUX_gsbi11_spi_cs3_n, - MSM_MUX_gsbi12, - MSM_MUX_hdmi_cec, - MSM_MUX_hdmi_ddc_clock, - MSM_MUX_hdmi_ddc_data, - MSM_MUX_hdmi_hot_plug_detect, - MSM_MUX_hsic, - MSM_MUX_mdp_vsync, - MSM_MUX_mi2s, - MSM_MUX_mic_i2s, - MSM_MUX_pmb_clk, - MSM_MUX_pmb_ext_ctrl, - MSM_MUX_ps_hold, - MSM_MUX_rpm_wdog, - MSM_MUX_sdc2, - MSM_MUX_sdc4, - MSM_MUX_sdc5, - MSM_MUX_slimbus1, - MSM_MUX_slimbus2, - MSM_MUX_spkr_i2s, - MSM_MUX_ssbi1, - MSM_MUX_ssbi2, - MSM_MUX_ssbi_ext_gps, - MSM_MUX_ssbi_pmic2, - MSM_MUX_ssbi_qpa1, - MSM_MUX_ssbi_ts, - MSM_MUX_tsif1, - MSM_MUX_tsif2, - MSM_MUX_ts_eoc, - MSM_MUX_usb_fs1, - MSM_MUX_usb_fs1_oe, - MSM_MUX_usb_fs1_oe_n, - MSM_MUX_usb_fs2, - MSM_MUX_usb_fs2_oe, - MSM_MUX_usb_fs2_oe_n, - MSM_MUX_vfe_camif_timer1_a, - MSM_MUX_vfe_camif_timer1_b, - MSM_MUX_vfe_camif_timer2, - MSM_MUX_vfe_camif_timer3_a, - MSM_MUX_vfe_camif_timer3_b, - MSM_MUX_vfe_camif_timer4_a, - MSM_MUX_vfe_camif_timer4_b, - MSM_MUX_vfe_camif_timer4_c, - MSM_MUX_vfe_camif_timer5_a, - MSM_MUX_vfe_camif_timer5_b, - MSM_MUX_vfe_camif_timer6_a, - MSM_MUX_vfe_camif_timer6_b, - MSM_MUX_vfe_camif_timer6_c, - MSM_MUX_vfe_camif_timer7_a, - MSM_MUX_vfe_camif_timer7_b, - MSM_MUX_vfe_camif_timer7_c, - MSM_MUX_wlan, - MSM_MUX_NA, -}; - -static const char * const audio_pcm_groups[] = { - "gpio63", "gpio64", "gpio65", "gpio66" -}; - -static const char * const bt_groups[] = { - "gpio28", "gpio29", "gpio83" -}; - -static const char * const cam_mclk0_groups[] = { - "gpio5" -}; - -static const char * const cam_mclk1_groups[] = { - "gpio4" -}; - -static const char * const cam_mclk2_groups[] = { - "gpio2" -}; - -static const char * const codec_mic_i2s_groups[] = { - "gpio54", "gpio55", "gpio56", "gpio57", "gpio58" -}; - -static const char * const codec_spkr_i2s_groups[] = { - "gpio59", "gpio60", "gpio61", "gpio62" -}; - -static const char * const ext_gps_groups[] = { - "gpio22", "gpio23", "gpio24", "gpio25" -}; - -static const char * const fm_groups[] = { - "gpio26", "gpio27" -}; - -static const char * const gps_blanking_groups[] = { - "gpio137" -}; - -static const char * const gps_pps_in_groups[] = { - "gpio37" -}; - -static const char * const gps_pps_out_groups[] = { - "gpio37" -}; - -static const char * const gp_clk_0a_groups[] = { - "gpio3" -}; - -static const char * const gp_clk_0b_groups[] = { - "gpio54" -}; - -static const char * const gp_clk_1a_groups[] = { - "gpio4" -}; - -static const char * const gp_clk_1b_groups[] = { - "gpio70" -}; - -static const char * const gp_clk_2a_groups[] = { - "gpio52" -}; - -static const char * const gp_clk_2b_groups[] = { - "gpio37" -}; - -static const char * const gp_mn_groups[] = { - "gpio2" -}; - -static const char * const gp_pdm_0a_groups[] = { - "gpio58" -}; - -static const char * const gp_pdm_0b_groups[] = { - "gpio39" -}; - -static const char * const gp_pdm_1a_groups[] = { - "gpio94" -}; - -static const char * const gp_pdm_1b_groups[] = { - "gpio64" -}; - -static const char * const gp_pdm_2a_groups[] = { - "gpio69" -}; - -static const char * const gp_pdm_2b_groups[] = { - "gpio53" -}; - -static const char * const gsbi1_groups[] = { - "gpio6", "gpio7", "gpio8", "gpio9" -}; - -static const char * const gsbi1_spi_cs1_n_groups[] = { - "gpio14" -}; - -static const char * const gsbi1_spi_cs2a_n_groups[] = { - "gpio15" -}; - -static const char * const gsbi1_spi_cs2b_n_groups[] = { - "gpio17" -}; - -static const char * const gsbi1_spi_cs3_n_groups[] = { - "gpio16" -}; - -static const char * const gsbi2_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13" -}; - -static const char * const gsbi2_spi_cs1_n_groups[] = { - "gpio52" -}; - -static const char * const gsbi2_spi_cs2_n_groups[] = { - "gpio68" -}; - -static const char * const gsbi2_spi_cs3_n_groups[] = { - "gpio56" -}; - -static const char * const gsbi3_groups[] = { - "gpio14", "gpio15", "gpio16", "gpio17" -}; - -static const char * const gsbi4_groups[] = { - "gpio18", "gpio19", "gpio20", "gpio21" -}; - -static const char * const gsbi4_3d_cam_i2c_l_groups[] = { - "gpio18", "gpio19" -}; - -static const char * const gsbi4_3d_cam_i2c_r_groups[] = { - "gpio20", "gpio21" -}; - -static const char * const gsbi5_groups[] = { - "gpio22", "gpio23", "gpio24", "gpio25" -}; - -static const char * const gsbi5_3d_cam_i2c_l_groups[] = { - "gpio22", "gpio23" -}; - -static const char * const gsbi5_3d_cam_i2c_r_groups[] = { - "gpio24", "gpio25" -}; - -static const char * const gsbi6_groups[] = { - "gpio26", "gpio27", "gpio28", "gpio29" -}; - -static const char * const gsbi7_groups[] = { - "gpio30", "gpio31", "gpio32", "gpio33" -}; - -static const char * const gsbi8_groups[] = { - "gpio34", "gpio35", "gpio36", "gpio37" -}; - -static const char * const gsbi9_groups[] = { - "gpio93", "gpio94", "gpio95", "gpio96" -}; - -static const char * const gsbi10_groups[] = { - "gpio71", "gpio72", "gpio73", "gpio74" -}; - -static const char * const gsbi11_groups[] = { - "gpio38", "gpio39", "gpio40", "gpio41" -}; - -static const char * const gsbi11_spi_cs1a_n_groups[] = { - "gpio36" -}; - -static const char * const gsbi11_spi_cs1b_n_groups[] = { - "gpio18" -}; - -static const char * const gsbi11_spi_cs2a_n_groups[] = { - "gpio37" -}; - -static const char * const gsbi11_spi_cs2b_n_groups[] = { - "gpio19" -}; - -static const char * const gsbi11_spi_cs3_n_groups[] = { - "gpio76" -}; - -static const char * const gsbi12_groups[] = { - "gpio42", "gpio43", "gpio44", "gpio45" -}; - -static const char * const hdmi_cec_groups[] = { - "gpio99" -}; - -static const char * const hdmi_ddc_clock_groups[] = { - "gpio100" -}; - -static const char * const hdmi_ddc_data_groups[] = { - "gpio101" -}; - -static const char * const hdmi_hot_plug_detect_groups[] = { - "gpio102" -}; - -static const char * const hsic_groups[] = { - "gpio150", "gpio151" -}; - -static const char * const mdp_vsync_groups[] = { - "gpio0", "gpio1", "gpio19" -}; - -static const char * const mi2s_groups[] = { - "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53" -}; - -static const char * const mic_i2s_groups[] = { - "gpio71", "gpio72", "gpio73", "gpio74" -}; - -static const char * const pmb_clk_groups[] = { - "gpio21", "gpio86", "gpio112" -}; - -static const char * const pmb_ext_ctrl_groups[] = { - "gpio4", "gpio5" -}; - -static const char * const ps_hold_groups[] = { - "gpio108" -}; - -static const char * const rpm_wdog_groups[] = { - "gpio12" -}; - -static const char * const sdc2_groups[] = { - "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", - "gpio96", "gpio97", "gpio98" -}; - -static const char * const sdc4_groups[] = { - "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" -}; - -static const char * const sdc5_groups[] = { - "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" -}; - -static const char * const slimbus1_groups[] = { - "gpio50", "gpio51", "gpio60", "gpio61" -}; - -static const char * const slimbus2_groups[] = { - "gpio42", "gpio43" -}; - -static const char * const spkr_i2s_groups[] = { - "gpio67", "gpio68", "gpio69", "gpio70" -}; - -static const char * const ssbi1_groups[] = { - "gpio141", "gpio143" -}; - -static const char * const ssbi2_groups[] = { - "gpio140", "gpio142" -}; - -static const char * const ssbi_ext_gps_groups[] = { - "gpio23" -}; - -static const char * const ssbi_pmic2_groups[] = { - "gpio149" -}; - -static const char * const ssbi_qpa1_groups[] = { - "gpio131" -}; - -static const char * const ssbi_ts_groups[] = { - "gpio10" -}; - -static const char * const tsif1_groups[] = { - "gpio75", "gpio76", "gpio77", "gpio82" -}; - -static const char * const tsif2_groups[] = { - "gpio78", "gpio79", "gpio80", "gpio81" -}; - -static const char * const ts_eoc_groups[] = { - "gpio11" -}; - -static const char * const usb_fs1_groups[] = { - "gpio32", "gpio33" -}; - -static const char * const usb_fs1_oe_groups[] = { - "gpio31" -}; - -static const char * const usb_fs1_oe_n_groups[] = { - "gpio31" -}; - -static const char * const usb_fs2_groups[] = { - "gpio34", "gpio35" -}; - -static const char * const usb_fs2_oe_groups[] = { - "gpio36" -}; - -static const char * const usb_fs2_oe_n_groups[] = { - "gpio36" -}; - -static const char * const vfe_camif_timer1_a_groups[] = { - "gpio2" -}; - -static const char * const vfe_camif_timer1_b_groups[] = { - "gpio38" -}; - -static const char * const vfe_camif_timer2_groups[] = { - "gpio3" -}; - -static const char * const vfe_camif_timer3_a_groups[] = { - "gpio4" -}; - -static const char * const vfe_camif_timer3_b_groups[] = { - "gpio151" -}; - -static const char * const vfe_camif_timer4_a_groups[] = { - "gpio65" -}; - -static const char * const vfe_camif_timer4_b_groups[] = { - "gpio150" -}; - -static const char * const vfe_camif_timer4_c_groups[] = { - "gpio10" -}; - -static const char * const vfe_camif_timer5_a_groups[] = { - "gpio66" -}; - -static const char * const vfe_camif_timer5_b_groups[] = { - "gpio39" -}; - -static const char * const vfe_camif_timer6_a_groups[] = { - "gpio71" -}; - -static const char * const vfe_camif_timer6_b_groups[] = { - "gpio0" -}; - -static const char * const vfe_camif_timer6_c_groups[] = { - "gpio18" -}; - -static const char * const vfe_camif_timer7_a_groups[] = { - "gpio67" -}; - -static const char * const vfe_camif_timer7_b_groups[] = { - "gpio1" -}; - -static const char * const vfe_camif_timer7_c_groups[] = { - "gpio19" -}; - -static const char * const wlan_groups[] = { - "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" -}; - -static const struct msm_function msm8960_functions[] = { - FUNCTION(audio_pcm), - FUNCTION(bt), - FUNCTION(cam_mclk0), - FUNCTION(cam_mclk1), - FUNCTION(cam_mclk2), - FUNCTION(codec_mic_i2s), - FUNCTION(codec_spkr_i2s), - FUNCTION(ext_gps), - FUNCTION(fm), - FUNCTION(gps_blanking), - FUNCTION(gps_pps_in), - FUNCTION(gps_pps_out), - FUNCTION(gp_clk_0a), - FUNCTION(gp_clk_0b), - FUNCTION(gp_clk_1a), - FUNCTION(gp_clk_1b), - FUNCTION(gp_clk_2a), - FUNCTION(gp_clk_2b), - FUNCTION(gp_mn), - FUNCTION(gp_pdm_0a), - FUNCTION(gp_pdm_0b), - FUNCTION(gp_pdm_1a), - FUNCTION(gp_pdm_1b), - FUNCTION(gp_pdm_2a), - FUNCTION(gp_pdm_2b), - FUNCTION(gsbi1), - FUNCTION(gsbi1_spi_cs1_n), - FUNCTION(gsbi1_spi_cs2a_n), - FUNCTION(gsbi1_spi_cs2b_n), - FUNCTION(gsbi1_spi_cs3_n), - FUNCTION(gsbi2), - FUNCTION(gsbi2_spi_cs1_n), - FUNCTION(gsbi2_spi_cs2_n), - FUNCTION(gsbi2_spi_cs3_n), - FUNCTION(gsbi3), - FUNCTION(gsbi4), - FUNCTION(gsbi4_3d_cam_i2c_l), - FUNCTION(gsbi4_3d_cam_i2c_r), - FUNCTION(gsbi5), - FUNCTION(gsbi5_3d_cam_i2c_l), - FUNCTION(gsbi5_3d_cam_i2c_r), - FUNCTION(gsbi6), - FUNCTION(gsbi7), - FUNCTION(gsbi8), - FUNCTION(gsbi9), - FUNCTION(gsbi10), - FUNCTION(gsbi11), - FUNCTION(gsbi11_spi_cs1a_n), - FUNCTION(gsbi11_spi_cs1b_n), - FUNCTION(gsbi11_spi_cs2a_n), - FUNCTION(gsbi11_spi_cs2b_n), - FUNCTION(gsbi11_spi_cs3_n), - FUNCTION(gsbi12), - FUNCTION(hdmi_cec), - FUNCTION(hdmi_ddc_clock), - FUNCTION(hdmi_ddc_data), - FUNCTION(hdmi_hot_plug_detect), - FUNCTION(hsic), - FUNCTION(mdp_vsync), - FUNCTION(mi2s), - FUNCTION(mic_i2s), - FUNCTION(pmb_clk), - FUNCTION(pmb_ext_ctrl), - FUNCTION(ps_hold), - FUNCTION(rpm_wdog), - FUNCTION(sdc2), - FUNCTION(sdc4), - FUNCTION(sdc5), - FUNCTION(slimbus1), - FUNCTION(slimbus2), - FUNCTION(spkr_i2s), - FUNCTION(ssbi1), - FUNCTION(ssbi2), - FUNCTION(ssbi_ext_gps), - FUNCTION(ssbi_pmic2), - FUNCTION(ssbi_qpa1), - FUNCTION(ssbi_ts), - FUNCTION(tsif1), - FUNCTION(tsif2), - FUNCTION(ts_eoc), - FUNCTION(usb_fs1), - FUNCTION(usb_fs1_oe), - FUNCTION(usb_fs1_oe_n), - FUNCTION(usb_fs2), - FUNCTION(usb_fs2_oe), - FUNCTION(usb_fs2_oe_n), - FUNCTION(vfe_camif_timer1_a), - FUNCTION(vfe_camif_timer1_b), - FUNCTION(vfe_camif_timer2), - FUNCTION(vfe_camif_timer3_a), - FUNCTION(vfe_camif_timer3_b), - FUNCTION(vfe_camif_timer4_a), - FUNCTION(vfe_camif_timer4_b), - FUNCTION(vfe_camif_timer4_c), - FUNCTION(vfe_camif_timer5_a), - FUNCTION(vfe_camif_timer5_b), - FUNCTION(vfe_camif_timer6_a), - FUNCTION(vfe_camif_timer6_b), - FUNCTION(vfe_camif_timer6_c), - FUNCTION(vfe_camif_timer7_a), - FUNCTION(vfe_camif_timer7_b), - FUNCTION(vfe_camif_timer7_c), - FUNCTION(wlan), -}; - -static const struct msm_pingroup msm8960_groups[] = { - PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA), - PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA), - PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), - PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), - PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), - PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), - PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA), - PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA), - PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b), - PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA), - - SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), - SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), - SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), - - SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), - SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), - SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), -}; - -#define NUM_GPIO_PINGROUPS 152 - -static const struct msm_pinctrl_soc_data msm8960_pinctrl = { - .pins = msm8960_pins, - .npins = ARRAY_SIZE(msm8960_pins), - .functions = msm8960_functions, - .nfunctions = ARRAY_SIZE(msm8960_functions), - .groups = msm8960_groups, - .ngroups = ARRAY_SIZE(msm8960_groups), - .ngpios = NUM_GPIO_PINGROUPS, -}; - -static int msm8960_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &msm8960_pinctrl); -} - -static const struct of_device_id msm8960_pinctrl_of_match[] = { - { .compatible = "qcom,msm8960-pinctrl", }, - { }, -}; - -static struct platform_driver msm8960_pinctrl_driver = { - .driver = { - .name = "msm8960-pinctrl", - .owner = THIS_MODULE, - .of_match_table = msm8960_pinctrl_of_match, - }, - .probe = msm8960_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init msm8960_pinctrl_init(void) -{ - return platform_driver_register(&msm8960_pinctrl_driver); -} -arch_initcall(msm8960_pinctrl_init); - -static void __exit msm8960_pinctrl_exit(void) -{ - platform_driver_unregister(&msm8960_pinctrl_driver); -} -module_exit(msm8960_pinctrl_exit); - -MODULE_AUTHOR("Bjorn Andersson "); -MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c deleted file mode 100644 index 418306911a6f..000000000000 --- a/drivers/pinctrl/pinctrl-msm8x74.c +++ /dev/null @@ -1,1040 +0,0 @@ -/* - * Copyright (c) 2013, Sony Mobile Communications AB. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -static const struct pinctrl_pin_desc msm8x74_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - PINCTRL_PIN(69, "GPIO_69"), - PINCTRL_PIN(70, "GPIO_70"), - PINCTRL_PIN(71, "GPIO_71"), - PINCTRL_PIN(72, "GPIO_72"), - PINCTRL_PIN(73, "GPIO_73"), - PINCTRL_PIN(74, "GPIO_74"), - PINCTRL_PIN(75, "GPIO_75"), - PINCTRL_PIN(76, "GPIO_76"), - PINCTRL_PIN(77, "GPIO_77"), - PINCTRL_PIN(78, "GPIO_78"), - PINCTRL_PIN(79, "GPIO_79"), - PINCTRL_PIN(80, "GPIO_80"), - PINCTRL_PIN(81, "GPIO_81"), - PINCTRL_PIN(82, "GPIO_82"), - PINCTRL_PIN(83, "GPIO_83"), - PINCTRL_PIN(84, "GPIO_84"), - PINCTRL_PIN(85, "GPIO_85"), - PINCTRL_PIN(86, "GPIO_86"), - PINCTRL_PIN(87, "GPIO_87"), - PINCTRL_PIN(88, "GPIO_88"), - PINCTRL_PIN(89, "GPIO_89"), - PINCTRL_PIN(90, "GPIO_90"), - PINCTRL_PIN(91, "GPIO_91"), - PINCTRL_PIN(92, "GPIO_92"), - PINCTRL_PIN(93, "GPIO_93"), - PINCTRL_PIN(94, "GPIO_94"), - PINCTRL_PIN(95, "GPIO_95"), - PINCTRL_PIN(96, "GPIO_96"), - PINCTRL_PIN(97, "GPIO_97"), - PINCTRL_PIN(98, "GPIO_98"), - PINCTRL_PIN(99, "GPIO_99"), - PINCTRL_PIN(100, "GPIO_100"), - PINCTRL_PIN(101, "GPIO_101"), - PINCTRL_PIN(102, "GPIO_102"), - PINCTRL_PIN(103, "GPIO_103"), - PINCTRL_PIN(104, "GPIO_104"), - PINCTRL_PIN(105, "GPIO_105"), - PINCTRL_PIN(106, "GPIO_106"), - PINCTRL_PIN(107, "GPIO_107"), - PINCTRL_PIN(108, "GPIO_108"), - PINCTRL_PIN(109, "GPIO_109"), - PINCTRL_PIN(110, "GPIO_110"), - PINCTRL_PIN(111, "GPIO_111"), - PINCTRL_PIN(112, "GPIO_112"), - PINCTRL_PIN(113, "GPIO_113"), - PINCTRL_PIN(114, "GPIO_114"), - PINCTRL_PIN(115, "GPIO_115"), - PINCTRL_PIN(116, "GPIO_116"), - PINCTRL_PIN(117, "GPIO_117"), - PINCTRL_PIN(118, "GPIO_118"), - PINCTRL_PIN(119, "GPIO_119"), - PINCTRL_PIN(120, "GPIO_120"), - PINCTRL_PIN(121, "GPIO_121"), - PINCTRL_PIN(122, "GPIO_122"), - PINCTRL_PIN(123, "GPIO_123"), - PINCTRL_PIN(124, "GPIO_124"), - PINCTRL_PIN(125, "GPIO_125"), - PINCTRL_PIN(126, "GPIO_126"), - PINCTRL_PIN(127, "GPIO_127"), - PINCTRL_PIN(128, "GPIO_128"), - PINCTRL_PIN(129, "GPIO_129"), - PINCTRL_PIN(130, "GPIO_130"), - PINCTRL_PIN(131, "GPIO_131"), - PINCTRL_PIN(132, "GPIO_132"), - PINCTRL_PIN(133, "GPIO_133"), - PINCTRL_PIN(134, "GPIO_134"), - PINCTRL_PIN(135, "GPIO_135"), - PINCTRL_PIN(136, "GPIO_136"), - PINCTRL_PIN(137, "GPIO_137"), - PINCTRL_PIN(138, "GPIO_138"), - PINCTRL_PIN(139, "GPIO_139"), - PINCTRL_PIN(140, "GPIO_140"), - PINCTRL_PIN(141, "GPIO_141"), - PINCTRL_PIN(142, "GPIO_142"), - PINCTRL_PIN(143, "GPIO_143"), - PINCTRL_PIN(144, "GPIO_144"), - PINCTRL_PIN(145, "GPIO_145"), - - PINCTRL_PIN(146, "SDC1_CLK"), - PINCTRL_PIN(147, "SDC1_CMD"), - PINCTRL_PIN(148, "SDC1_DATA"), - PINCTRL_PIN(149, "SDC2_CLK"), - PINCTRL_PIN(150, "SDC2_CMD"), - PINCTRL_PIN(151, "SDC2_DATA"), -}; - -#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_MSM_GPIO_PINS(0); -DECLARE_MSM_GPIO_PINS(1); -DECLARE_MSM_GPIO_PINS(2); -DECLARE_MSM_GPIO_PINS(3); -DECLARE_MSM_GPIO_PINS(4); -DECLARE_MSM_GPIO_PINS(5); -DECLARE_MSM_GPIO_PINS(6); -DECLARE_MSM_GPIO_PINS(7); -DECLARE_MSM_GPIO_PINS(8); -DECLARE_MSM_GPIO_PINS(9); -DECLARE_MSM_GPIO_PINS(10); -DECLARE_MSM_GPIO_PINS(11); -DECLARE_MSM_GPIO_PINS(12); -DECLARE_MSM_GPIO_PINS(13); -DECLARE_MSM_GPIO_PINS(14); -DECLARE_MSM_GPIO_PINS(15); -DECLARE_MSM_GPIO_PINS(16); -DECLARE_MSM_GPIO_PINS(17); -DECLARE_MSM_GPIO_PINS(18); -DECLARE_MSM_GPIO_PINS(19); -DECLARE_MSM_GPIO_PINS(20); -DECLARE_MSM_GPIO_PINS(21); -DECLARE_MSM_GPIO_PINS(22); -DECLARE_MSM_GPIO_PINS(23); -DECLARE_MSM_GPIO_PINS(24); -DECLARE_MSM_GPIO_PINS(25); -DECLARE_MSM_GPIO_PINS(26); -DECLARE_MSM_GPIO_PINS(27); -DECLARE_MSM_GPIO_PINS(28); -DECLARE_MSM_GPIO_PINS(29); -DECLARE_MSM_GPIO_PINS(30); -DECLARE_MSM_GPIO_PINS(31); -DECLARE_MSM_GPIO_PINS(32); -DECLARE_MSM_GPIO_PINS(33); -DECLARE_MSM_GPIO_PINS(34); -DECLARE_MSM_GPIO_PINS(35); -DECLARE_MSM_GPIO_PINS(36); -DECLARE_MSM_GPIO_PINS(37); -DECLARE_MSM_GPIO_PINS(38); -DECLARE_MSM_GPIO_PINS(39); -DECLARE_MSM_GPIO_PINS(40); -DECLARE_MSM_GPIO_PINS(41); -DECLARE_MSM_GPIO_PINS(42); -DECLARE_MSM_GPIO_PINS(43); -DECLARE_MSM_GPIO_PINS(44); -DECLARE_MSM_GPIO_PINS(45); -DECLARE_MSM_GPIO_PINS(46); -DECLARE_MSM_GPIO_PINS(47); -DECLARE_MSM_GPIO_PINS(48); -DECLARE_MSM_GPIO_PINS(49); -DECLARE_MSM_GPIO_PINS(50); -DECLARE_MSM_GPIO_PINS(51); -DECLARE_MSM_GPIO_PINS(52); -DECLARE_MSM_GPIO_PINS(53); -DECLARE_MSM_GPIO_PINS(54); -DECLARE_MSM_GPIO_PINS(55); -DECLARE_MSM_GPIO_PINS(56); -DECLARE_MSM_GPIO_PINS(57); -DECLARE_MSM_GPIO_PINS(58); -DECLARE_MSM_GPIO_PINS(59); -DECLARE_MSM_GPIO_PINS(60); -DECLARE_MSM_GPIO_PINS(61); -DECLARE_MSM_GPIO_PINS(62); -DECLARE_MSM_GPIO_PINS(63); -DECLARE_MSM_GPIO_PINS(64); -DECLARE_MSM_GPIO_PINS(65); -DECLARE_MSM_GPIO_PINS(66); -DECLARE_MSM_GPIO_PINS(67); -DECLARE_MSM_GPIO_PINS(68); -DECLARE_MSM_GPIO_PINS(69); -DECLARE_MSM_GPIO_PINS(70); -DECLARE_MSM_GPIO_PINS(71); -DECLARE_MSM_GPIO_PINS(72); -DECLARE_MSM_GPIO_PINS(73); -DECLARE_MSM_GPIO_PINS(74); -DECLARE_MSM_GPIO_PINS(75); -DECLARE_MSM_GPIO_PINS(76); -DECLARE_MSM_GPIO_PINS(77); -DECLARE_MSM_GPIO_PINS(78); -DECLARE_MSM_GPIO_PINS(79); -DECLARE_MSM_GPIO_PINS(80); -DECLARE_MSM_GPIO_PINS(81); -DECLARE_MSM_GPIO_PINS(82); -DECLARE_MSM_GPIO_PINS(83); -DECLARE_MSM_GPIO_PINS(84); -DECLARE_MSM_GPIO_PINS(85); -DECLARE_MSM_GPIO_PINS(86); -DECLARE_MSM_GPIO_PINS(87); -DECLARE_MSM_GPIO_PINS(88); -DECLARE_MSM_GPIO_PINS(89); -DECLARE_MSM_GPIO_PINS(90); -DECLARE_MSM_GPIO_PINS(91); -DECLARE_MSM_GPIO_PINS(92); -DECLARE_MSM_GPIO_PINS(93); -DECLARE_MSM_GPIO_PINS(94); -DECLARE_MSM_GPIO_PINS(95); -DECLARE_MSM_GPIO_PINS(96); -DECLARE_MSM_GPIO_PINS(97); -DECLARE_MSM_GPIO_PINS(98); -DECLARE_MSM_GPIO_PINS(99); -DECLARE_MSM_GPIO_PINS(100); -DECLARE_MSM_GPIO_PINS(101); -DECLARE_MSM_GPIO_PINS(102); -DECLARE_MSM_GPIO_PINS(103); -DECLARE_MSM_GPIO_PINS(104); -DECLARE_MSM_GPIO_PINS(105); -DECLARE_MSM_GPIO_PINS(106); -DECLARE_MSM_GPIO_PINS(107); -DECLARE_MSM_GPIO_PINS(108); -DECLARE_MSM_GPIO_PINS(109); -DECLARE_MSM_GPIO_PINS(110); -DECLARE_MSM_GPIO_PINS(111); -DECLARE_MSM_GPIO_PINS(112); -DECLARE_MSM_GPIO_PINS(113); -DECLARE_MSM_GPIO_PINS(114); -DECLARE_MSM_GPIO_PINS(115); -DECLARE_MSM_GPIO_PINS(116); -DECLARE_MSM_GPIO_PINS(117); -DECLARE_MSM_GPIO_PINS(118); -DECLARE_MSM_GPIO_PINS(119); -DECLARE_MSM_GPIO_PINS(120); -DECLARE_MSM_GPIO_PINS(121); -DECLARE_MSM_GPIO_PINS(122); -DECLARE_MSM_GPIO_PINS(123); -DECLARE_MSM_GPIO_PINS(124); -DECLARE_MSM_GPIO_PINS(125); -DECLARE_MSM_GPIO_PINS(126); -DECLARE_MSM_GPIO_PINS(127); -DECLARE_MSM_GPIO_PINS(128); -DECLARE_MSM_GPIO_PINS(129); -DECLARE_MSM_GPIO_PINS(130); -DECLARE_MSM_GPIO_PINS(131); -DECLARE_MSM_GPIO_PINS(132); -DECLARE_MSM_GPIO_PINS(133); -DECLARE_MSM_GPIO_PINS(134); -DECLARE_MSM_GPIO_PINS(135); -DECLARE_MSM_GPIO_PINS(136); -DECLARE_MSM_GPIO_PINS(137); -DECLARE_MSM_GPIO_PINS(138); -DECLARE_MSM_GPIO_PINS(139); -DECLARE_MSM_GPIO_PINS(140); -DECLARE_MSM_GPIO_PINS(141); -DECLARE_MSM_GPIO_PINS(142); -DECLARE_MSM_GPIO_PINS(143); -DECLARE_MSM_GPIO_PINS(144); -DECLARE_MSM_GPIO_PINS(145); - -static const unsigned int sdc1_clk_pins[] = { 146 }; -static const unsigned int sdc1_cmd_pins[] = { 147 }; -static const unsigned int sdc1_data_pins[] = { 148 }; -static const unsigned int sdc2_clk_pins[] = { 149 }; -static const unsigned int sdc2_cmd_pins[] = { 150 }; -static const unsigned int sdc2_data_pins[] = { 151 }; - -#define FUNCTION(fname) \ - [MSM_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - MSM_MUX_NA, /* gpio mode */ \ - MSM_MUX_##f1, \ - MSM_MUX_##f2, \ - MSM_MUX_##f3, \ - MSM_MUX_##f4, \ - MSM_MUX_##f5, \ - MSM_MUX_##f6, \ - MSM_MUX_##f7 \ - }, \ - .nfuncs = 8, \ - .ctl_reg = 0x1000 + 0x10 * id, \ - .io_reg = 0x1004 + 0x10 * id, \ - .intr_cfg_reg = 0x1008 + 0x10 * id, \ - .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x1008 + 0x10 * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_target_bit = 5, \ - .intr_raw_status_bit = 4, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 2, \ - } - -#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -/* - * TODO: Add the rest of the possible functions and fill out - * the pingroup table below. - */ -enum msm8x74_functions { - MSM_MUX_cci_i2c0, - MSM_MUX_cci_i2c1, - MSM_MUX_blsp_i2c1, - MSM_MUX_blsp_i2c2, - MSM_MUX_blsp_i2c3, - MSM_MUX_blsp_i2c4, - MSM_MUX_blsp_i2c5, - MSM_MUX_blsp_i2c6, - MSM_MUX_blsp_i2c7, - MSM_MUX_blsp_i2c8, - MSM_MUX_blsp_i2c9, - MSM_MUX_blsp_i2c10, - MSM_MUX_blsp_i2c11, - MSM_MUX_blsp_i2c12, - MSM_MUX_blsp_spi1, - MSM_MUX_blsp_spi1_cs1, - MSM_MUX_blsp_spi1_cs2, - MSM_MUX_blsp_spi1_cs3, - MSM_MUX_blsp_spi2, - MSM_MUX_blsp_spi2_cs1, - MSM_MUX_blsp_spi2_cs2, - MSM_MUX_blsp_spi2_cs3, - MSM_MUX_blsp_spi3, - MSM_MUX_blsp_spi4, - MSM_MUX_blsp_spi5, - MSM_MUX_blsp_spi6, - MSM_MUX_blsp_spi7, - MSM_MUX_blsp_spi8, - MSM_MUX_blsp_spi9, - MSM_MUX_blsp_spi10, - MSM_MUX_blsp_spi10_cs1, - MSM_MUX_blsp_spi10_cs2, - MSM_MUX_blsp_spi10_cs3, - MSM_MUX_blsp_spi11, - MSM_MUX_blsp_spi12, - MSM_MUX_blsp_uart1, - MSM_MUX_blsp_uart2, - MSM_MUX_blsp_uart3, - MSM_MUX_blsp_uart4, - MSM_MUX_blsp_uart5, - MSM_MUX_blsp_uart6, - MSM_MUX_blsp_uart7, - MSM_MUX_blsp_uart8, - MSM_MUX_blsp_uart9, - MSM_MUX_blsp_uart10, - MSM_MUX_blsp_uart11, - MSM_MUX_blsp_uart12, - MSM_MUX_blsp_uim1, - MSM_MUX_blsp_uim2, - MSM_MUX_blsp_uim3, - MSM_MUX_blsp_uim4, - MSM_MUX_blsp_uim5, - MSM_MUX_blsp_uim6, - MSM_MUX_blsp_uim7, - MSM_MUX_blsp_uim8, - MSM_MUX_blsp_uim9, - MSM_MUX_blsp_uim10, - MSM_MUX_blsp_uim11, - MSM_MUX_blsp_uim12, - MSM_MUX_uim1, - MSM_MUX_uim2, - MSM_MUX_uim_batt_alarm, - MSM_MUX_sdc3, - MSM_MUX_sdc4, - MSM_MUX_gcc_gp_clk1, - MSM_MUX_gcc_gp_clk2, - MSM_MUX_gcc_gp_clk3, - MSM_MUX_qua_mi2s, - MSM_MUX_pri_mi2s, - MSM_MUX_spkr_mi2s, - MSM_MUX_ter_mi2s, - MSM_MUX_sec_mi2s, - MSM_MUX_hdmi_cec, - MSM_MUX_hdmi_ddc, - MSM_MUX_hdmi_hpd, - MSM_MUX_edp_hpd, - MSM_MUX_mdp_vsync, - MSM_MUX_cam_mclk0, - MSM_MUX_cam_mclk1, - MSM_MUX_cam_mclk2, - MSM_MUX_cam_mclk3, - MSM_MUX_cci_timer0, - MSM_MUX_cci_timer1, - MSM_MUX_cci_timer2, - MSM_MUX_cci_timer3, - MSM_MUX_cci_timer4, - MSM_MUX_cci_async_in0, - MSM_MUX_cci_async_in1, - MSM_MUX_cci_async_in2, - MSM_MUX_gp_pdm0, - MSM_MUX_gp_pdm1, - MSM_MUX_gp_pdm2, - MSM_MUX_gp0_clk, - MSM_MUX_gp1_clk, - MSM_MUX_gp_mn, - MSM_MUX_tsif1, - MSM_MUX_tsif2, - MSM_MUX_hsic, - MSM_MUX_grfc, - MSM_MUX_audio_ref_clk, - MSM_MUX_bt, - MSM_MUX_fm, - MSM_MUX_wlan, - MSM_MUX_slimbus, - MSM_MUX_NA, -}; - -static const char * const blsp_uart1_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3" -}; -static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; -static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; -static const char * const blsp_spi1_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3" -}; -static const char * const blsp_spi1_cs1_groups[] = { "gpio8" }; -static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" }; -static const char * const blsp_spi1_cs3_groups[] = { "gpio10" }; - -static const char * const blsp_uart2_groups[] = { - "gpio4", "gpio5", "gpio6", "gpio7" -}; -static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; -static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; -static const char * const blsp_spi2_groups[] = { - "gpio4", "gpio5", "gpio6", "gpio7" -}; -static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" }; -static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" }; -static const char * const blsp_spi2_cs3_groups[] = { "gpio66" }; - -static const char * const blsp_uart3_groups[] = { - "gpio8", "gpio9", "gpio10", "gpio11" -}; -static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; -static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; -static const char * const blsp_spi3_groups[] = { - "gpio8", "gpio9", "gpio10", "gpio11" -}; - -static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" }; -static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" }; - -static const char * const blsp_uart4_groups[] = { - "gpio19", "gpio20", "gpio21", "gpio22" -}; -static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" }; -static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" }; -static const char * const blsp_spi4_groups[] = { - "gpio19", "gpio20", "gpio21", "gpio22" -}; - -static const char * const blsp_uart5_groups[] = { - "gpio23", "gpio24", "gpio25", "gpio26" -}; -static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" }; -static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" }; -static const char * const blsp_spi5_groups[] = { - "gpio23", "gpio24", "gpio25", "gpio26" -}; - -static const char * const blsp_uart6_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30" -}; -static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" }; -static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; -static const char * const blsp_spi6_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30" -}; - -static const char * const blsp_uart7_groups[] = { - "gpio41", "gpio42", "gpio43", "gpio44" -}; -static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" }; -static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" }; -static const char * const blsp_spi7_groups[] = { - "gpio41", "gpio42", "gpio43", "gpio44" -}; - -static const char * const blsp_uart8_groups[] = { - "gpio45", "gpio46", "gpio47", "gpio48" -}; -static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" }; -static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" }; -static const char * const blsp_spi8_groups[] = { - "gpio45", "gpio46", "gpio47", "gpio48" -}; - -static const char * const blsp_uart9_groups[] = { - "gpio49", "gpio50", "gpio51", "gpio52" -}; -static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" }; -static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" }; -static const char * const blsp_spi9_groups[] = { - "gpio49", "gpio50", "gpio51", "gpio52" -}; - -static const char * const blsp_uart10_groups[] = { - "gpio53", "gpio54", "gpio55", "gpio56" -}; -static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" }; -static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" }; -static const char * const blsp_spi10_groups[] = { - "gpio53", "gpio54", "gpio55", "gpio56" -}; -static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" }; -static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" }; -static const char * const blsp_spi10_cs3_groups[] = { "gpio90" }; - -static const char * const blsp_uart11_groups[] = { - "gpio81", "gpio82", "gpio83", "gpio84" -}; -static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" }; -static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; -static const char * const blsp_spi11_groups[] = { - "gpio81", "gpio82", "gpio83", "gpio84" -}; - -static const char * const blsp_uart12_groups[] = { - "gpio85", "gpio86", "gpio87", "gpio88" -}; -static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" }; -static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" }; -static const char * const blsp_spi12_groups[] = { - "gpio85", "gpio86", "gpio87", "gpio88" -}; - -static const char * const uim1_groups[] = { - "gpio97", "gpio98", "gpio99", "gpio100" -}; - -static const char * const uim2_groups[] = { - "gpio49", "gpio50", "gpio51", "gpio52" -}; - -static const char * const uim_batt_alarm_groups[] = { "gpio101" }; - -static const char * const sdc3_groups[] = { - "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" -}; - -static const char * const sdc4_groups[] = { - "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" -}; - -static const char * const gp0_clk_groups[] = { "gpio26" }; -static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" }; -static const char * const gp_mn_groups[] = { "gpio29" }; -static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" }; -static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" }; -static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" }; - -static const char * const qua_mi2s_groups[] = { - "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", -}; - -static const char * const pri_mi2s_groups[] = { - "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" -}; - -static const char * const spkr_mi2s_groups[] = { - "gpio69", "gpio70", "gpio71", "gpio72" -}; - -static const char * const ter_mi2s_groups[] = { - "gpio73", "gpio74", "gpio75", "gpio76", "gpio77" -}; - -static const char * const sec_mi2s_groups[] = { - "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" -}; - -static const char * const hdmi_cec_groups[] = { "gpio31" }; -static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" }; -static const char * const hdmi_hpd_groups[] = { "gpio34" }; -static const char * const edp_hpd_groups[] = { "gpio102" }; - -static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" }; -static const char * const cam_mclk0_groups[] = { "gpio15" }; -static const char * const cam_mclk1_groups[] = { "gpio16" }; -static const char * const cam_mclk2_groups[] = { "gpio17" }; -static const char * const cam_mclk3_groups[] = { "gpio18" }; - -static const char * const cci_timer0_groups[] = { "gpio23" }; -static const char * const cci_timer1_groups[] = { "gpio24" }; -static const char * const cci_timer2_groups[] = { "gpio25" }; -static const char * const cci_timer3_groups[] = { "gpio26" }; -static const char * const cci_timer4_groups[] = { "gpio27" }; -static const char * const cci_async_in0_groups[] = { "gpio28" }; -static const char * const cci_async_in1_groups[] = { "gpio26" }; -static const char * const cci_async_in2_groups[] = { "gpio27" }; - -static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" }; -static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" }; -static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" }; - -static const char * const tsif1_groups[] = { - "gpio89", "gpio90", "gpio91", "gpio92" -}; - -static const char * const tsif2_groups[] = { - "gpio93", "gpio94", "gpio95", "gpio96" -}; - -static const char * const hsic_groups[] = { "gpio144", "gpio145" }; -static const char * const grfc_groups[] = { - "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", - "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", - "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", - "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", - "gpio128", "gpio136", "gpio137", "gpio141", "gpio143" -}; - -static const char * const audio_ref_clk_groups[] = { "gpio69" }; - -static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" }; - -static const char * const fm_groups[] = { "gpio41", "gpio42" }; - -static const char * const wlan_groups[] = { - "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" -}; - -static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; - -static const struct msm_function msm8x74_functions[] = { - FUNCTION(cci_i2c0), - FUNCTION(cci_i2c1), - FUNCTION(uim1), - FUNCTION(uim2), - FUNCTION(uim_batt_alarm), - FUNCTION(blsp_uim1), - FUNCTION(blsp_uim2), - FUNCTION(blsp_uim3), - FUNCTION(blsp_uim4), - FUNCTION(blsp_uim5), - FUNCTION(blsp_uim6), - FUNCTION(blsp_uim7), - FUNCTION(blsp_uim8), - FUNCTION(blsp_uim9), - FUNCTION(blsp_uim10), - FUNCTION(blsp_uim11), - FUNCTION(blsp_uim12), - FUNCTION(blsp_i2c1), - FUNCTION(blsp_i2c2), - FUNCTION(blsp_i2c3), - FUNCTION(blsp_i2c4), - FUNCTION(blsp_i2c5), - FUNCTION(blsp_i2c6), - FUNCTION(blsp_i2c7), - FUNCTION(blsp_i2c8), - FUNCTION(blsp_i2c9), - FUNCTION(blsp_i2c10), - FUNCTION(blsp_i2c11), - FUNCTION(blsp_i2c12), - FUNCTION(blsp_spi1), - FUNCTION(blsp_spi1_cs1), - FUNCTION(blsp_spi1_cs2), - FUNCTION(blsp_spi1_cs3), - FUNCTION(blsp_spi2), - FUNCTION(blsp_spi2_cs1), - FUNCTION(blsp_spi2_cs2), - FUNCTION(blsp_spi2_cs3), - FUNCTION(blsp_spi3), - FUNCTION(blsp_spi4), - FUNCTION(blsp_spi5), - FUNCTION(blsp_spi6), - FUNCTION(blsp_spi7), - FUNCTION(blsp_spi8), - FUNCTION(blsp_spi9), - FUNCTION(blsp_spi10), - FUNCTION(blsp_spi10_cs1), - FUNCTION(blsp_spi10_cs2), - FUNCTION(blsp_spi10_cs3), - FUNCTION(blsp_spi11), - FUNCTION(blsp_spi12), - FUNCTION(blsp_uart1), - FUNCTION(blsp_uart2), - FUNCTION(blsp_uart3), - FUNCTION(blsp_uart4), - FUNCTION(blsp_uart5), - FUNCTION(blsp_uart6), - FUNCTION(blsp_uart7), - FUNCTION(blsp_uart8), - FUNCTION(blsp_uart9), - FUNCTION(blsp_uart10), - FUNCTION(blsp_uart11), - FUNCTION(blsp_uart12), - FUNCTION(sdc3), - FUNCTION(sdc4), - FUNCTION(gcc_gp_clk1), - FUNCTION(gcc_gp_clk2), - FUNCTION(gcc_gp_clk3), - FUNCTION(qua_mi2s), - FUNCTION(pri_mi2s), - FUNCTION(spkr_mi2s), - FUNCTION(ter_mi2s), - FUNCTION(sec_mi2s), - FUNCTION(mdp_vsync), - FUNCTION(cam_mclk0), - FUNCTION(cam_mclk1), - FUNCTION(cam_mclk2), - FUNCTION(cam_mclk3), - FUNCTION(cci_timer0), - FUNCTION(cci_timer1), - FUNCTION(cci_timer2), - FUNCTION(cci_timer3), - FUNCTION(cci_timer4), - FUNCTION(cci_async_in0), - FUNCTION(cci_async_in1), - FUNCTION(cci_async_in2), - FUNCTION(hdmi_cec), - FUNCTION(hdmi_ddc), - FUNCTION(hdmi_hpd), - FUNCTION(edp_hpd), - FUNCTION(gp_pdm0), - FUNCTION(gp_pdm1), - FUNCTION(gp_pdm2), - FUNCTION(gp0_clk), - FUNCTION(gp1_clk), - FUNCTION(gp_mn), - FUNCTION(tsif1), - FUNCTION(tsif2), - FUNCTION(hsic), - FUNCTION(grfc), - FUNCTION(audio_ref_clk), - FUNCTION(bt), - FUNCTION(fm), - FUNCTION(wlan), - FUNCTION(slimbus), -}; - -static const struct msm_pingroup msm8x74_groups[] = { - PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), - PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), - PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), - PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), - PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), - PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), - PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), - PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), - PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA), - PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA), - PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA), - PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA), - PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), - PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), - PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), - PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), - PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), - PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), - PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), - PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), - PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), - PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), - PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), - PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), - PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), - PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA), - PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA), - PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA), - PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA), - PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA), - PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), - PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), - PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), - PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), - PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA), - PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA), - PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), - PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), - PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), - PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), - PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), - PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), - PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA), - PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA), - PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), - PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), - PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), - PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), - PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA), - PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA), - PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), - PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), - PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), - PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA), - PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA), - PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA), - PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA), - PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA), - PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA), - PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA), - PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA), - PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), - PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), - PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA), - PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), - PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA), - PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA), - PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA), - PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), - PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), - PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), - PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA), - PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), - PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), - PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA), - PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA), - PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA), - PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA), - PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA), - PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA), - PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA), - PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA), - PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA), - PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA), - PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA), - PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA), - PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA), - PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA), - PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(129, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(130, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(131, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(132, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(133, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(134, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(135, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(140, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(142, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA), - PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA), - SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), - SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), - SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), - SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), - SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), - SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), -}; - -#define NUM_GPIO_PINGROUPS 146 - -static const struct msm_pinctrl_soc_data msm8x74_pinctrl = { - .pins = msm8x74_pins, - .npins = ARRAY_SIZE(msm8x74_pins), - .functions = msm8x74_functions, - .nfunctions = ARRAY_SIZE(msm8x74_functions), - .groups = msm8x74_groups, - .ngroups = ARRAY_SIZE(msm8x74_groups), - .ngpios = NUM_GPIO_PINGROUPS, -}; - -static int msm8x74_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &msm8x74_pinctrl); -} - -static const struct of_device_id msm8x74_pinctrl_of_match[] = { - { .compatible = "qcom,msm8974-pinctrl", }, - { }, -}; - -static struct platform_driver msm8x74_pinctrl_driver = { - .driver = { - .name = "msm8x74-pinctrl", - .owner = THIS_MODULE, - .of_match_table = msm8x74_pinctrl_of_match, - }, - .probe = msm8x74_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init msm8x74_pinctrl_init(void) -{ - return platform_driver_register(&msm8x74_pinctrl_driver); -} -arch_initcall(msm8x74_pinctrl_init); - -static void __exit msm8x74_pinctrl_exit(void) -{ - platform_driver_unregister(&msm8x74_pinctrl_driver); -} -module_exit(msm8x74_pinctrl_exit); - -MODULE_AUTHOR("Bjorn Andersson "); -MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); - diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig new file mode 100644 index 000000000000..d160a710d704 --- /dev/null +++ b/drivers/pinctrl/qcom/Kconfig @@ -0,0 +1,42 @@ +if (ARCH_QCOM || COMPILE_TEST) + +config PINCTRL_MSM + bool + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB_IRQCHIP + +config PINCTRL_APQ8064 + tristate "Qualcomm APQ8064 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm APQ8064 platform. + +config PINCTRL_IPQ8064 + tristate "Qualcomm IPQ8064 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. + +config PINCTRL_MSM8960 + tristate "Qualcomm 8960 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8960 platform. + +config PINCTRL_MSM8X74 + tristate "Qualcomm 8x74 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8974 platform. + +endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile new file mode 100644 index 000000000000..2a02602d715c --- /dev/null +++ b/drivers/pinctrl/qcom/Makefile @@ -0,0 +1,6 @@ +# Qualcomm pin control drivers +obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o +obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o +obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o +obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c new file mode 100644 index 000000000000..519f7886b0f1 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -0,0 +1,613 @@ +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc apq8064_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + + PINCTRL_PIN(90, "SDC1_CLK"), + PINCTRL_PIN(91, "SDC1_CMD"), + PINCTRL_PIN(92, "SDC1_DATA"), + PINCTRL_PIN(93, "SDC3_CLK"), + PINCTRL_PIN(94, "SDC3_CMD"), + PINCTRL_PIN(95, "SDC3_DATA"), +}; + +#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_APQ_GPIO_PINS(0); +DECLARE_APQ_GPIO_PINS(1); +DECLARE_APQ_GPIO_PINS(2); +DECLARE_APQ_GPIO_PINS(3); +DECLARE_APQ_GPIO_PINS(4); +DECLARE_APQ_GPIO_PINS(5); +DECLARE_APQ_GPIO_PINS(6); +DECLARE_APQ_GPIO_PINS(7); +DECLARE_APQ_GPIO_PINS(8); +DECLARE_APQ_GPIO_PINS(9); +DECLARE_APQ_GPIO_PINS(10); +DECLARE_APQ_GPIO_PINS(11); +DECLARE_APQ_GPIO_PINS(12); +DECLARE_APQ_GPIO_PINS(13); +DECLARE_APQ_GPIO_PINS(14); +DECLARE_APQ_GPIO_PINS(15); +DECLARE_APQ_GPIO_PINS(16); +DECLARE_APQ_GPIO_PINS(17); +DECLARE_APQ_GPIO_PINS(18); +DECLARE_APQ_GPIO_PINS(19); +DECLARE_APQ_GPIO_PINS(20); +DECLARE_APQ_GPIO_PINS(21); +DECLARE_APQ_GPIO_PINS(22); +DECLARE_APQ_GPIO_PINS(23); +DECLARE_APQ_GPIO_PINS(24); +DECLARE_APQ_GPIO_PINS(25); +DECLARE_APQ_GPIO_PINS(26); +DECLARE_APQ_GPIO_PINS(27); +DECLARE_APQ_GPIO_PINS(28); +DECLARE_APQ_GPIO_PINS(29); +DECLARE_APQ_GPIO_PINS(30); +DECLARE_APQ_GPIO_PINS(31); +DECLARE_APQ_GPIO_PINS(32); +DECLARE_APQ_GPIO_PINS(33); +DECLARE_APQ_GPIO_PINS(34); +DECLARE_APQ_GPIO_PINS(35); +DECLARE_APQ_GPIO_PINS(36); +DECLARE_APQ_GPIO_PINS(37); +DECLARE_APQ_GPIO_PINS(38); +DECLARE_APQ_GPIO_PINS(39); +DECLARE_APQ_GPIO_PINS(40); +DECLARE_APQ_GPIO_PINS(41); +DECLARE_APQ_GPIO_PINS(42); +DECLARE_APQ_GPIO_PINS(43); +DECLARE_APQ_GPIO_PINS(44); +DECLARE_APQ_GPIO_PINS(45); +DECLARE_APQ_GPIO_PINS(46); +DECLARE_APQ_GPIO_PINS(47); +DECLARE_APQ_GPIO_PINS(48); +DECLARE_APQ_GPIO_PINS(49); +DECLARE_APQ_GPIO_PINS(50); +DECLARE_APQ_GPIO_PINS(51); +DECLARE_APQ_GPIO_PINS(52); +DECLARE_APQ_GPIO_PINS(53); +DECLARE_APQ_GPIO_PINS(54); +DECLARE_APQ_GPIO_PINS(55); +DECLARE_APQ_GPIO_PINS(56); +DECLARE_APQ_GPIO_PINS(57); +DECLARE_APQ_GPIO_PINS(58); +DECLARE_APQ_GPIO_PINS(59); +DECLARE_APQ_GPIO_PINS(60); +DECLARE_APQ_GPIO_PINS(61); +DECLARE_APQ_GPIO_PINS(62); +DECLARE_APQ_GPIO_PINS(63); +DECLARE_APQ_GPIO_PINS(64); +DECLARE_APQ_GPIO_PINS(65); +DECLARE_APQ_GPIO_PINS(66); +DECLARE_APQ_GPIO_PINS(67); +DECLARE_APQ_GPIO_PINS(68); +DECLARE_APQ_GPIO_PINS(69); +DECLARE_APQ_GPIO_PINS(70); +DECLARE_APQ_GPIO_PINS(71); +DECLARE_APQ_GPIO_PINS(72); +DECLARE_APQ_GPIO_PINS(73); +DECLARE_APQ_GPIO_PINS(74); +DECLARE_APQ_GPIO_PINS(75); +DECLARE_APQ_GPIO_PINS(76); +DECLARE_APQ_GPIO_PINS(77); +DECLARE_APQ_GPIO_PINS(78); +DECLARE_APQ_GPIO_PINS(79); +DECLARE_APQ_GPIO_PINS(80); +DECLARE_APQ_GPIO_PINS(81); +DECLARE_APQ_GPIO_PINS(82); +DECLARE_APQ_GPIO_PINS(83); +DECLARE_APQ_GPIO_PINS(84); +DECLARE_APQ_GPIO_PINS(85); +DECLARE_APQ_GPIO_PINS(86); +DECLARE_APQ_GPIO_PINS(87); +DECLARE_APQ_GPIO_PINS(88); +DECLARE_APQ_GPIO_PINS(89); + +static const unsigned int sdc1_clk_pins[] = { 90 }; +static const unsigned int sdc1_cmd_pins[] = { 91 }; +static const unsigned int sdc1_data_pins[] = { 92 }; +static const unsigned int sdc3_clk_pins[] = { 93 }; +static const unsigned int sdc3_cmd_pins[] = { 94 }; +static const unsigned int sdc3_data_pins[] = { 95 }; + +#define FUNCTION(fname) \ + [APQ_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + APQ_MUX_NA, /* gpio mode */ \ + APQ_MUX_##f1, \ + APQ_MUX_##f2, \ + APQ_MUX_##f3, \ + APQ_MUX_##f4, \ + APQ_MUX_##f5, \ + APQ_MUX_##f6, \ + APQ_MUX_##f7, \ + APQ_MUX_##f8, \ + APQ_MUX_##f9, \ + APQ_MUX_##f10, \ + }, \ + .nfuncs = 11, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum apq8064_functions { + APQ_MUX_cam_mclk, + APQ_MUX_codec_mic_i2s, + APQ_MUX_codec_spkr_i2s, + APQ_MUX_gsbi1, + APQ_MUX_gsbi2, + APQ_MUX_gsbi3, + APQ_MUX_gsbi4, + APQ_MUX_gsbi4_cam_i2c, + APQ_MUX_gsbi5, + APQ_MUX_gsbi5_spi_cs1, + APQ_MUX_gsbi5_spi_cs2, + APQ_MUX_gsbi5_spi_cs3, + APQ_MUX_gsbi6, + APQ_MUX_gsbi6_spi_cs1, + APQ_MUX_gsbi6_spi_cs2, + APQ_MUX_gsbi6_spi_cs3, + APQ_MUX_gsbi7, + APQ_MUX_gsbi7_spi_cs1, + APQ_MUX_gsbi7_spi_cs2, + APQ_MUX_gsbi7_spi_cs3, + APQ_MUX_gsbi_cam_i2c, + APQ_MUX_hdmi, + APQ_MUX_mi2s, + APQ_MUX_riva_bt, + APQ_MUX_riva_fm, + APQ_MUX_riva_wlan, + APQ_MUX_sdc2, + APQ_MUX_sdc4, + APQ_MUX_slimbus, + APQ_MUX_spkr_i2s, + APQ_MUX_tsif1, + APQ_MUX_tsif2, + APQ_MUX_usb2_hsic, + APQ_MUX_NA, +}; + +static const char * const cam_mclk_groups[] = { + "gpio4" "gpio5" +}; +static const char * const codec_mic_i2s_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38" +}; +static const char * const codec_spkr_i2s_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42" +}; +static const char * const gsbi1_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21" +}; +static const char * const gsbi2_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char * const gsbi3_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9" +}; +static const char * const gsbi4_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const gsbi4_cam_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const gsbi5_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54" +}; +static const char * const gsbi5_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi5_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi5_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi6_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17" +}; +static const char * const gsbi6_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi6_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi6_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi7_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85" +}; +static const char * const gsbi7_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi7_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi7_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi_cam_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const hdmi_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; +static const char * const mi2s_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33" +}; +static const char * const riva_bt_groups[] = { + "gpio16", "gpio17" +}; +static const char * const riva_fm_groups[] = { + "gpio14", "gpio15" +}; +static const char * const riva_wlan_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const sdc2_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62" +}; +static const char * const sdc4_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const slimbus_groups[] = { + "gpio40", "gpio41" +}; +static const char * const spkr_i2s_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50" +}; +static const char * const tsif1_groups[] = { + "gpio55", "gpio56", "gpio57" +}; +static const char * const tsif2_groups[] = { + "gpio58", "gpio59", "gpio60" +}; +static const char * const usb2_hsic_groups[] = { + "gpio88", "gpio89" +}; + +static const struct msm_function apq8064_functions[] = { + FUNCTION(cam_mclk), + FUNCTION(codec_mic_i2s), + FUNCTION(codec_spkr_i2s), + FUNCTION(gsbi1), + FUNCTION(gsbi2), + FUNCTION(gsbi3), + FUNCTION(gsbi4), + FUNCTION(gsbi4_cam_i2c), + FUNCTION(gsbi5), + FUNCTION(gsbi5_spi_cs1), + FUNCTION(gsbi5_spi_cs2), + FUNCTION(gsbi5_spi_cs3), + FUNCTION(gsbi6), + FUNCTION(gsbi6_spi_cs1), + FUNCTION(gsbi6_spi_cs2), + FUNCTION(gsbi6_spi_cs3), + FUNCTION(gsbi7), + FUNCTION(gsbi7_spi_cs1), + FUNCTION(gsbi7_spi_cs2), + FUNCTION(gsbi7_spi_cs3), + FUNCTION(gsbi_cam_i2c), + FUNCTION(hdmi), + FUNCTION(mi2s), + FUNCTION(riva_bt), + FUNCTION(riva_fm), + FUNCTION(riva_wlan), + FUNCTION(sdc2), + FUNCTION(sdc4), + FUNCTION(slimbus), + FUNCTION(spkr_i2s), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(usb2_hsic), +}; + +static const struct msm_pingroup apq8064_groups[] = { + PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi4, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c, NA), + PINGROUP(11, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c), + PINGROUP(12, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), + PINGROUP(13, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), + PINGROUP(14, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA), + PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA), + PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA), + PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, tsif1, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 90 + +static const struct msm_pinctrl_soc_data apq8064_pinctrl = { + .pins = apq8064_pins, + .npins = ARRAY_SIZE(apq8064_pins), + .functions = apq8064_functions, + .nfunctions = ARRAY_SIZE(apq8064_functions), + .groups = apq8064_groups, + .ngroups = ARRAY_SIZE(apq8064_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int apq8064_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &apq8064_pinctrl); +} + +static const struct of_device_id apq8064_pinctrl_of_match[] = { + { .compatible = "qcom,apq8064-pinctrl", }, + { }, +}; + +static struct platform_driver apq8064_pinctrl_driver = { + .driver = { + .name = "apq8064-pinctrl", + .owner = THIS_MODULE, + .of_match_table = apq8064_pinctrl_of_match, + }, + .probe = apq8064_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init apq8064_pinctrl_init(void) +{ + return platform_driver_register(&apq8064_pinctrl_driver); +} +arch_initcall(apq8064_pinctrl_init); + +static void __exit apq8064_pinctrl_exit(void) +{ + platform_driver_unregister(&apq8064_pinctrl_driver); +} +module_exit(apq8064_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c new file mode 100644 index 000000000000..acafea4c3a33 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -0,0 +1,653 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc ipq8064_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + + PINCTRL_PIN(69, "SDC3_CLK"), + PINCTRL_PIN(70, "SDC3_CMD"), + PINCTRL_PIN(71, "SDC3_DATA"), +}; + +#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_IPQ_GPIO_PINS(0); +DECLARE_IPQ_GPIO_PINS(1); +DECLARE_IPQ_GPIO_PINS(2); +DECLARE_IPQ_GPIO_PINS(3); +DECLARE_IPQ_GPIO_PINS(4); +DECLARE_IPQ_GPIO_PINS(5); +DECLARE_IPQ_GPIO_PINS(6); +DECLARE_IPQ_GPIO_PINS(7); +DECLARE_IPQ_GPIO_PINS(8); +DECLARE_IPQ_GPIO_PINS(9); +DECLARE_IPQ_GPIO_PINS(10); +DECLARE_IPQ_GPIO_PINS(11); +DECLARE_IPQ_GPIO_PINS(12); +DECLARE_IPQ_GPIO_PINS(13); +DECLARE_IPQ_GPIO_PINS(14); +DECLARE_IPQ_GPIO_PINS(15); +DECLARE_IPQ_GPIO_PINS(16); +DECLARE_IPQ_GPIO_PINS(17); +DECLARE_IPQ_GPIO_PINS(18); +DECLARE_IPQ_GPIO_PINS(19); +DECLARE_IPQ_GPIO_PINS(20); +DECLARE_IPQ_GPIO_PINS(21); +DECLARE_IPQ_GPIO_PINS(22); +DECLARE_IPQ_GPIO_PINS(23); +DECLARE_IPQ_GPIO_PINS(24); +DECLARE_IPQ_GPIO_PINS(25); +DECLARE_IPQ_GPIO_PINS(26); +DECLARE_IPQ_GPIO_PINS(27); +DECLARE_IPQ_GPIO_PINS(28); +DECLARE_IPQ_GPIO_PINS(29); +DECLARE_IPQ_GPIO_PINS(30); +DECLARE_IPQ_GPIO_PINS(31); +DECLARE_IPQ_GPIO_PINS(32); +DECLARE_IPQ_GPIO_PINS(33); +DECLARE_IPQ_GPIO_PINS(34); +DECLARE_IPQ_GPIO_PINS(35); +DECLARE_IPQ_GPIO_PINS(36); +DECLARE_IPQ_GPIO_PINS(37); +DECLARE_IPQ_GPIO_PINS(38); +DECLARE_IPQ_GPIO_PINS(39); +DECLARE_IPQ_GPIO_PINS(40); +DECLARE_IPQ_GPIO_PINS(41); +DECLARE_IPQ_GPIO_PINS(42); +DECLARE_IPQ_GPIO_PINS(43); +DECLARE_IPQ_GPIO_PINS(44); +DECLARE_IPQ_GPIO_PINS(45); +DECLARE_IPQ_GPIO_PINS(46); +DECLARE_IPQ_GPIO_PINS(47); +DECLARE_IPQ_GPIO_PINS(48); +DECLARE_IPQ_GPIO_PINS(49); +DECLARE_IPQ_GPIO_PINS(50); +DECLARE_IPQ_GPIO_PINS(51); +DECLARE_IPQ_GPIO_PINS(52); +DECLARE_IPQ_GPIO_PINS(53); +DECLARE_IPQ_GPIO_PINS(54); +DECLARE_IPQ_GPIO_PINS(55); +DECLARE_IPQ_GPIO_PINS(56); +DECLARE_IPQ_GPIO_PINS(57); +DECLARE_IPQ_GPIO_PINS(58); +DECLARE_IPQ_GPIO_PINS(59); +DECLARE_IPQ_GPIO_PINS(60); +DECLARE_IPQ_GPIO_PINS(61); +DECLARE_IPQ_GPIO_PINS(62); +DECLARE_IPQ_GPIO_PINS(63); +DECLARE_IPQ_GPIO_PINS(64); +DECLARE_IPQ_GPIO_PINS(65); +DECLARE_IPQ_GPIO_PINS(66); +DECLARE_IPQ_GPIO_PINS(67); +DECLARE_IPQ_GPIO_PINS(68); + +static const unsigned int sdc3_clk_pins[] = { 69 }; +static const unsigned int sdc3_cmd_pins[] = { 70 }; +static const unsigned int sdc3_data_pins[] = { 71 }; + +#define FUNCTION(fname) \ + [IPQ_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + IPQ_MUX_NA, /* gpio mode */ \ + IPQ_MUX_##f1, \ + IPQ_MUX_##f2, \ + IPQ_MUX_##f3, \ + IPQ_MUX_##f4, \ + IPQ_MUX_##f5, \ + IPQ_MUX_##f6, \ + IPQ_MUX_##f7, \ + IPQ_MUX_##f8, \ + IPQ_MUX_##f9, \ + IPQ_MUX_##f10, \ + }, \ + .nfuncs = 11, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum ipq8064_functions { + IPQ_MUX_mdio, + IPQ_MUX_mi2s, + IPQ_MUX_pdm, + IPQ_MUX_ssbi, + IPQ_MUX_spmi, + IPQ_MUX_audio_pcm, + IPQ_MUX_gsbi1, + IPQ_MUX_gsbi2, + IPQ_MUX_gsbi4, + IPQ_MUX_gsbi5, + IPQ_MUX_gsbi5_spi_cs1, + IPQ_MUX_gsbi5_spi_cs2, + IPQ_MUX_gsbi5_spi_cs3, + IPQ_MUX_gsbi6, + IPQ_MUX_gsbi7, + IPQ_MUX_nss_spi, + IPQ_MUX_sdc1, + IPQ_MUX_spdif, + IPQ_MUX_nand, + IPQ_MUX_tsif1, + IPQ_MUX_tsif2, + IPQ_MUX_usb_fs_n, + IPQ_MUX_usb_fs, + IPQ_MUX_usb2_hsic, + IPQ_MUX_rgmii2, + IPQ_MUX_sata, + IPQ_MUX_pcie1_rst, + IPQ_MUX_pcie1_prsnt, + IPQ_MUX_pcie1_pwrflt, + IPQ_MUX_pcie1_pwren_n, + IPQ_MUX_pcie1_pwren, + IPQ_MUX_pcie1_clk_req, + IPQ_MUX_pcie2_rst, + IPQ_MUX_pcie2_prsnt, + IPQ_MUX_pcie2_pwrflt, + IPQ_MUX_pcie2_pwren_n, + IPQ_MUX_pcie2_pwren, + IPQ_MUX_pcie2_clk_req, + IPQ_MUX_pcie3_rst, + IPQ_MUX_pcie3_prsnt, + IPQ_MUX_pcie3_pwrflt, + IPQ_MUX_pcie3_pwren_n, + IPQ_MUX_pcie3_pwren, + IPQ_MUX_pcie3_clk_req, + IPQ_MUX_ps_hold, + IPQ_MUX_NA, +}; + +static const char * const mdio_groups[] = { + "gpio0", "gpio1", "gpio10", "gpio11", +}; + +static const char * const mi2s_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const pdm_groups[] = { + "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31", + "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58", + "gpio59", +}; + +static const char * const ssbi_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const spmi_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const audio_pcm_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const gsbi1_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54", +}; + +static const char * const gsbi2_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char * const gsbi4_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const gsbi5_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const gsbi5_spi_cs1_groups[] = { + "gpio6", "gpio61", +}; + +static const char * const gsbi5_spi_cs2_groups[] = { + "gpio7", "gpio62", +}; + +static const char * const gsbi5_spi_cs3_groups[] = { + "gpio2", +}; + +static const char * const gsbi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56", + "gpio57", "gpio58", +}; + +static const char * const gsbi7_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const nss_spi_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56", + "gpio57", "gpio58", +}; + +static const char * const sdc1_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const spdif_groups[] = { + "gpio10", "gpio48", +}; + +static const char * const nand_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", +}; + +static const char * const tsif1_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const tsif2_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const usb_fs_n_groups[] = { + "gpio6", +}; + +static const char * const usb_fs_groups[] = { + "gpio6", "gpio7", "gpio8", +}; + +static const char * const usb2_hsic_groups[] = { + "gpio67", "gpio68", +}; + +static const char * const rgmii2_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const sata_groups[] = { + "gpio10", +}; + +static const char * const pcie1_rst_groups[] = { + "gpio3", +}; + +static const char * const pcie1_prsnt_groups[] = { + "gpio3", "gpio11", +}; + +static const char * const pcie1_pwren_n_groups[] = { + "gpio4", "gpio12", +}; + +static const char * const pcie1_pwren_groups[] = { + "gpio4", "gpio12", +}; + +static const char * const pcie1_pwrflt_groups[] = { + "gpio5", "gpio13", +}; + +static const char * const pcie1_clk_req_groups[] = { + "gpio5", +}; + +static const char * const pcie2_rst_groups[] = { + "gpio48", +}; + +static const char * const pcie2_prsnt_groups[] = { + "gpio11", "gpio48", +}; + +static const char * const pcie2_pwren_n_groups[] = { + "gpio12", "gpio49", +}; + +static const char * const pcie2_pwren_groups[] = { + "gpio12", "gpio49", +}; + +static const char * const pcie2_pwrflt_groups[] = { + "gpio13", "gpio50", +}; + +static const char * const pcie2_clk_req_groups[] = { + "gpio50", +}; + +static const char * const pcie3_rst_groups[] = { + "gpio63", +}; + +static const char * const pcie3_prsnt_groups[] = { + "gpio11", +}; + +static const char * const pcie3_pwren_n_groups[] = { + "gpio12", +}; + +static const char * const pcie3_pwren_groups[] = { + "gpio12", +}; + +static const char * const pcie3_pwrflt_groups[] = { + "gpio13", +}; + +static const char * const pcie3_clk_req_groups[] = { + "gpio65", +}; + +static const char * const ps_hold_groups[] = { + "gpio26", +}; + +static const struct msm_function ipq8064_functions[] = { + FUNCTION(mdio), + FUNCTION(ssbi), + FUNCTION(spmi), + FUNCTION(mi2s), + FUNCTION(pdm), + FUNCTION(audio_pcm), + FUNCTION(gsbi1), + FUNCTION(gsbi2), + FUNCTION(gsbi4), + FUNCTION(gsbi5), + FUNCTION(gsbi5_spi_cs1), + FUNCTION(gsbi5_spi_cs2), + FUNCTION(gsbi5_spi_cs3), + FUNCTION(gsbi6), + FUNCTION(gsbi7), + FUNCTION(nss_spi), + FUNCTION(sdc1), + FUNCTION(spdif), + FUNCTION(nand), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(usb_fs_n), + FUNCTION(usb_fs), + FUNCTION(usb2_hsic), + FUNCTION(rgmii2), + FUNCTION(sata), + FUNCTION(pcie1_rst), + FUNCTION(pcie1_prsnt), + FUNCTION(pcie1_pwren_n), + FUNCTION(pcie1_pwren), + FUNCTION(pcie1_pwrflt), + FUNCTION(pcie1_clk_req), + FUNCTION(pcie2_rst), + FUNCTION(pcie2_prsnt), + FUNCTION(pcie2_pwren_n), + FUNCTION(pcie2_pwren), + FUNCTION(pcie2_pwrflt), + FUNCTION(pcie2_clk_req), + FUNCTION(pcie3_rst), + FUNCTION(pcie3_prsnt), + FUNCTION(pcie3_pwren_n), + FUNCTION(pcie3_pwren), + FUNCTION(pcie3_pwrflt), + FUNCTION(pcie3_clk_req), + FUNCTION(ps_hold), +}; + +static const struct msm_pingroup ipq8064_groups[] = { + PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA), + PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA), + PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA), + PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA), + PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA), + PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3), + SDC_PINGROUP(sdc3_data, 0x204a, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 69 + +static const struct msm_pinctrl_soc_data ipq8064_pinctrl = { + .pins = ipq8064_pins, + .npins = ARRAY_SIZE(ipq8064_pins), + .functions = ipq8064_functions, + .nfunctions = ARRAY_SIZE(ipq8064_functions), + .groups = ipq8064_groups, + .ngroups = ARRAY_SIZE(ipq8064_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int ipq8064_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq8064_pinctrl); +} + +static const struct of_device_id ipq8064_pinctrl_of_match[] = { + { .compatible = "qcom,ipq8064-pinctrl", }, + { }, +}; + +static struct platform_driver ipq8064_pinctrl_driver = { + .driver = { + .name = "ipq8064-pinctrl", + .owner = THIS_MODULE, + .of_match_table = ipq8064_pinctrl_of_match, + }, + .probe = ipq8064_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq8064_pinctrl_init(void) +{ + return platform_driver_register(&ipq8064_pinctrl_driver); +} +arch_initcall(ipq8064_pinctrl_init); + +static void __exit ipq8064_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq8064_pinctrl_driver); +} +module_exit(ipq8064_pinctrl_exit); + +MODULE_AUTHOR("Andy Gross "); +MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c new file mode 100644 index 000000000000..90d383d3ce17 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -0,0 +1,922 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinconf.h" +#include "pinctrl-msm.h" +#include "../pinctrl-utils.h" + +#define MAX_NR_GPIO 300 + +/** + * struct msm_pinctrl - state for a pinctrl-msm device + * @dev: device handle. + * @pctrl: pinctrl handle. + * @chip: gpiochip handle. + * @irq: parent irq for the TLMM irq_chip. + * @lock: Spinlock to protect register resources as well + * as msm_pinctrl data structures. + * @enabled_irqs: Bitmap of currently enabled irqs. + * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge + * detection. + * @soc; Reference to soc_data of platform specific data. + * @regs: Base address for the TLMM register map. + */ +struct msm_pinctrl { + struct device *dev; + struct pinctrl_dev *pctrl; + struct gpio_chip chip; + int irq; + + spinlock_t lock; + + DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + + const struct msm_pinctrl_soc_data *soc; + void __iomem *regs; +}; + +static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) +{ + return container_of(gc, struct msm_pinctrl, chip); +} + +static int msm_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->ngroups; +} + +static const char *msm_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->groups[group].name; +} + +static int msm_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->soc->groups[group].pins; + *num_pins = pctrl->soc->groups[group].npins; + return 0; +} + +static const struct pinctrl_ops msm_pinctrl_ops = { + .get_groups_count = msm_get_groups_count, + .get_group_name = msm_get_group_name, + .get_group_pins = msm_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int msm_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->nfunctions; +} + +static const char *msm_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->functions[function].name; +} + +static int msm_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->soc->functions[function].groups; + *num_groups = pctrl->soc->functions[function].ngroups; + return 0; +} + +static int msm_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + int i; + + g = &pctrl->soc->groups[group]; + + if (WARN_ON(g->mux_bit < 0)) + return -EINVAL; + + for (i = 0; i < g->nfuncs; i++) { + if (g->funcs[i] == function) + break; + } + + if (WARN_ON(i == g->nfuncs)) + return -EINVAL; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->ctl_reg); + val &= ~(0x7 << g->mux_bit); + val |= i << g->mux_bit; + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static const struct pinmux_ops msm_pinmux_ops = { + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, + .get_function_groups = msm_get_function_groups, + .enable = msm_pinmux_enable, +}; + +static int msm_config_reg(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g, + unsigned param, + unsigned *mask, + unsigned *bit) +{ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_BUS_HOLD: + case PIN_CONFIG_BIAS_PULL_UP: + *bit = g->pull_bit; + *mask = 3; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *bit = g->drv_bit; + *mask = 7; + break; + case PIN_CONFIG_OUTPUT: + *bit = g->oe_bit; + *mask = 1; + break; + default: + dev_err(pctrl->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + + return 0; +} + +static int msm_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + dev_err(pctldev->dev, "pin_config_set op not supported\n"); + return -ENOTSUPP; +} + +static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + dev_err(pctldev->dev, "pin_config_set op not supported\n"); + return -ENOTSUPP; +} + +#define MSM_NO_PULL 0 +#define MSM_PULL_DOWN 1 +#define MSM_KEEPER 2 +#define MSM_PULL_UP 3 + +static unsigned msm_regval_to_drive(u32 val) +{ + return (val + 1) * 2; +} + +static int msm_config_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned param = pinconf_to_config_param(*config); + unsigned mask; + unsigned arg; + unsigned bit; + int ret; + u32 val; + + g = &pctrl->soc->groups[group]; + + ret = msm_config_reg(pctrl, g, param, &mask, &bit); + if (ret < 0) + return ret; + + val = readl(pctrl->regs + g->ctl_reg); + arg = (val >> bit) & mask; + + /* Convert register value to pinconf value */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = arg == MSM_NO_PULL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = arg == MSM_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + arg = arg == MSM_KEEPER; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = arg == MSM_PULL_UP; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = msm_regval_to_drive(arg); + break; + case PIN_CONFIG_OUTPUT: + /* Pin is not output */ + if (!arg) + return -EINVAL; + + val = readl(pctrl->regs + g->io_reg); + arg = !!(val & BIT(g->in_bit)); + break; + default: + dev_err(pctrl->dev, "Unsupported config parameter: %x\n", + param); + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int msm_config_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + unsigned param; + unsigned mask; + unsigned arg; + unsigned bit; + int ret; + u32 val; + int i; + + g = &pctrl->soc->groups[group]; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + ret = msm_config_reg(pctrl, g, param, &mask, &bit); + if (ret < 0) + return ret; + + /* Convert pinconf values to register values */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = MSM_NO_PULL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = MSM_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + arg = MSM_KEEPER; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = MSM_PULL_UP; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + /* Check for invalid values */ + if (arg > 16 || arg < 2 || (arg % 2) != 0) + arg = -1; + else + arg = (arg / 2) - 1; + break; + case PIN_CONFIG_OUTPUT: + /* set output value */ + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->io_reg); + if (arg) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + + /* enable output */ + arg = 1; + break; + default: + dev_err(pctrl->dev, "Unsupported config parameter: %x\n", + param); + return -EINVAL; + } + + /* Range-check user-supplied value */ + if (arg & ~mask) { + dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); + return -EINVAL; + } + + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->ctl_reg); + val &= ~(mask << bit); + val |= arg << bit; + writel(val, pctrl->regs + g->ctl_reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + } + + return 0; +} + +static const struct pinconf_ops msm_pinconf_ops = { + .pin_config_get = msm_config_get, + .pin_config_set = msm_config_set, + .pin_config_group_get = msm_config_group_get, + .pin_config_group_set = msm_config_group_set, +}; + +static struct pinctrl_desc msm_pinctrl_desc = { + .pctlops = &msm_pinctrl_ops, + .pmxops = &msm_pinmux_ops, + .confops = &msm_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->ctl_reg); + val &= ~BIT(g->oe_bit); + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->io_reg); + if (value) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + + val = readl(pctrl->regs + g->ctl_reg); + val |= BIT(g->oe_bit); + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + u32 val; + + g = &pctrl->soc->groups[offset]; + + val = readl(pctrl->regs + g->io_reg); + return !!(val & BIT(g->in_bit)); +} + +static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->io_reg); + if (value) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + return pinctrl_request_gpio(gpio); +} + +static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + return pinctrl_free_gpio(gpio); +} + +#ifdef CONFIG_DEBUG_FS +#include + +static void msm_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, + unsigned gpio) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned func; + int is_out; + int drive; + int pull; + u32 ctl_reg; + + static const char * const pulls[] = { + "no pull", + "pull down", + "keeper", + "pull up" + }; + + g = &pctrl->soc->groups[offset]; + ctl_reg = readl(pctrl->regs + g->ctl_reg); + + is_out = !!(ctl_reg & BIT(g->oe_bit)); + func = (ctl_reg >> g->mux_bit) & 7; + drive = (ctl_reg >> g->drv_bit) & 7; + pull = (ctl_reg >> g->pull_bit) & 3; + + seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); + seq_printf(s, " %dmA", msm_regval_to_drive(drive)); + seq_printf(s, " %s", pulls[pull]); +} + +static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned gpio = chip->base; + unsigned i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define msm_gpio_dbg_show NULL +#endif + +static struct gpio_chip msm_gpio_template = { + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get = msm_gpio_get, + .set = msm_gpio_set, + .request = msm_gpio_request, + .free = msm_gpio_free, + .dbg_show = msm_gpio_dbg_show, +}; + +/* For dual-edge interrupts in software, since some hardware has no + * such support: + * + * At appropriate moments, this function may be called to flip the polarity + * settings of both-edge irq lines to try and catch the next edge. + * + * The attempt is considered successful if: + * - the status bit goes high, indicating that an edge was caught, or + * - the input value of the gpio doesn't change during the attempt. + * If the value changes twice during the process, that would cause the first + * test to fail but would force the second, as two opposite + * transitions would cause a detection no matter the polarity setting. + * + * The do-loop tries to sledge-hammer closed the timing hole between + * the initial value-read and the polarity-write - if the line value changes + * during that window, an interrupt is lost, the new polarity setting is + * incorrect, and the first success test will fail, causing a retry. + * + * Algorithm comes from Google's msmgpio driver. + */ +static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g, + struct irq_data *d) +{ + int loop_limit = 100; + unsigned val, val2, intstat; + unsigned pol; + + do { + val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); + + pol = readl(pctrl->regs + g->intr_cfg_reg); + pol ^= BIT(g->intr_polarity_bit); + writel(pol, pctrl->regs + g->intr_cfg_reg); + + val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); + intstat = readl(pctrl->regs + g->intr_status_reg); + if (intstat || (val == val2)) + return; + } while (loop_limit-- > 0); + dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", + val, val2); +} + +static void msm_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_cfg_reg); + val &= ~BIT(g->intr_enable_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + + clear_bit(d->hwirq, pctrl->enabled_irqs); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_status_reg); + val &= ~BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + + val = readl(pctrl->regs + g->intr_cfg_reg); + val |= BIT(g->intr_enable_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + + set_bit(d->hwirq, pctrl->enabled_irqs); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_status_reg); + if (g->intr_ack_high) + val |= BIT(g->intr_status_bit); + else + val &= ~BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(pctrl, g, d); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +#define INTR_TARGET_PROC_APPS 4 + +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* + * For hw without possibility of detecting both edges + */ + if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) + set_bit(d->hwirq, pctrl->dual_edge_irqs); + else + clear_bit(d->hwirq, pctrl->dual_edge_irqs); + + /* Route interrupts to application cpu */ + val = readl(pctrl->regs + g->intr_target_reg); + val &= ~(7 << g->intr_target_bit); + val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; + writel(val, pctrl->regs + g->intr_target_reg); + + /* Update configuration for gpio. + * RAW_STATUS_EN is left on for all gpio irqs. Due to the + * internal circuitry of TLMM, toggling the RAW_STATUS + * could cause the INTR_STATUS to be set for EDGE interrupts. + */ + val = readl(pctrl->regs + g->intr_cfg_reg); + val |= BIT(g->intr_raw_status_bit); + if (g->intr_detection_width == 2) { + val &= ~(3 << g->intr_detection_bit); + val &= ~(1 << g->intr_polarity_bit); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val |= 1 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_FALLING: + val |= 2 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_BOTH: + val |= 3 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_LEVEL_LOW: + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= BIT(g->intr_polarity_bit); + break; + } + } else if (g->intr_detection_width == 1) { + val &= ~(1 << g->intr_detection_bit); + val &= ~(1 << g->intr_polarity_bit); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val |= BIT(g->intr_detection_bit); + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_FALLING: + val |= BIT(g->intr_detection_bit); + break; + case IRQ_TYPE_EDGE_BOTH: + val |= BIT(g->intr_detection_bit); + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_LEVEL_LOW: + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= BIT(g->intr_polarity_bit); + break; + } + } else { + BUG(); + } + writel(val, pctrl->regs + g->intr_cfg_reg); + + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(pctrl, g, d); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + __irq_set_handler_locked(d->irq, handle_level_irq); + else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + __irq_set_handler_locked(d->irq, handle_edge_irq); + + return 0; +} + +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + unsigned long flags; + + spin_lock_irqsave(&pctrl->lock, flags); + + irq_set_irq_wake(pctrl->irq, on); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static struct irq_chip msm_gpio_irq_chip = { + .name = "msmgpio", + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_ack = msm_gpio_irq_ack, + .irq_set_type = msm_gpio_irq_set_type, + .irq_set_wake = msm_gpio_irq_set_wake, +}; + +static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + struct irq_chip *chip = irq_get_chip(irq); + int irq_pin; + int handled = 0; + u32 val; + int i; + + chained_irq_enter(chip, desc); + + /* + * Each pin has it's own IRQ status register, so use + * enabled_irq bitmap to limit the number of reads. + */ + for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { + g = &pctrl->soc->groups[i]; + val = readl(pctrl->regs + g->intr_status_reg); + if (val & BIT(g->intr_status_bit)) { + irq_pin = irq_find_mapping(gc->irqdomain, i); + generic_handle_irq(irq_pin); + handled++; + } + } + + /* No interrupts were flagged */ + if (handled == 0) + handle_bad_irq(irq, desc); + + chained_irq_exit(chip, desc); +} + +static int msm_gpio_init(struct msm_pinctrl *pctrl) +{ + struct gpio_chip *chip; + int ret; + unsigned ngpio = pctrl->soc->ngpios; + + if (WARN_ON(ngpio > MAX_NR_GPIO)) + return -EINVAL; + + chip = &pctrl->chip; + chip->base = 0; + chip->ngpio = ngpio; + chip->label = dev_name(pctrl->dev); + chip->dev = pctrl->dev; + chip->owner = THIS_MODULE; + chip->of_node = pctrl->dev->of_node; + + ret = gpiochip_add(&pctrl->chip); + if (ret) { + dev_err(pctrl->dev, "Failed register gpiochip\n"); + return ret; + } + + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); + if (ret) { + dev_err(pctrl->dev, "Failed to add pin range\n"); + return ret; + } + + ret = gpiochip_irqchip_add(chip, + &msm_gpio_irq_chip, + 0, + handle_edge_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); + return -ENOSYS; + } + + gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, + msm_gpio_irq_handler); + + return 0; +} + +int msm_pinctrl_probe(struct platform_device *pdev, + const struct msm_pinctrl_soc_data *soc_data) +{ + struct msm_pinctrl *pctrl; + struct resource *res; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) { + dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); + return -ENOMEM; + } + pctrl->dev = &pdev->dev; + pctrl->soc = soc_data; + pctrl->chip = msm_gpio_template; + + spin_lock_init(&pctrl->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctrl->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->regs)) + return PTR_ERR(pctrl->regs); + + pctrl->irq = platform_get_irq(pdev, 0); + if (pctrl->irq < 0) { + dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); + return pctrl->irq; + } + + msm_pinctrl_desc.name = dev_name(&pdev->dev); + msm_pinctrl_desc.pins = pctrl->soc->pins; + msm_pinctrl_desc.npins = pctrl->soc->npins; + pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); + if (!pctrl->pctrl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + + ret = msm_gpio_init(pctrl); + if (ret) { + pinctrl_unregister(pctrl->pctrl); + return ret; + } + + platform_set_drvdata(pdev, pctrl); + + dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); + + return 0; +} +EXPORT_SYMBOL(msm_pinctrl_probe); + +int msm_pinctrl_remove(struct platform_device *pdev) +{ + struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&pctrl->chip); + if (ret) { + dev_err(&pdev->dev, "Failed to remove gpiochip\n"); + return ret; + } + + pinctrl_unregister(pctrl->pctrl); + + return 0; +} +EXPORT_SYMBOL(msm_pinctrl_remove); + diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h new file mode 100644 index 000000000000..7b2a227a590a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __PINCTRL_MSM_H__ +#define __PINCTRL_MSM_H__ + +struct pinctrl_pin_desc; + +/** + * struct msm_function - a pinmux function + * @name: Name of the pinmux function. + * @groups: List of pingroups for this function. + * @ngroups: Number of entries in @groups. + */ +struct msm_function { + const char *name; + const char * const *groups; + unsigned ngroups; +}; + +/** + * struct msm_pingroup - Qualcomm pingroup definition + * @name: Name of the pingroup. + * @pins: A list of pins assigned to this pingroup. + * @npins: Number of entries in @pins. + * @funcs: A list of pinmux functions that can be selected for + * this group. The index of the selected function is used + * for programming the function selector. + * Entries should be indices into the groups list of the + * struct msm_pinctrl_soc_data. + * @ctl_reg: Offset of the register holding control bits for this group. + * @io_reg: Offset of the register holding input/output bits for this group. + * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. + * @intr_status_reg: Offset of the register holding the status bits for this group. + * @intr_target_reg: Offset of the register specifying routing of the interrupts + * from this group. + * @mux_bit: Offset in @ctl_reg for the pinmux function selection. + * @pull_bit: Offset in @ctl_reg for the bias configuration. + * @drv_bit: Offset in @ctl_reg for the drive strength configuration. + * @oe_bit: Offset in @ctl_reg for controlling output enable. + * @in_bit: Offset in @io_reg for the input bit value. + * @out_bit: Offset in @io_reg for the output bit value. + * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. + * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt + * status. + * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. + * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. + * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. + * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. + * @intr_detection_width: Number of bits used for specifying interrupt type, + * Should be 2 for SoCs that can detect both edges in hardware, + * otherwise 1. + */ +struct msm_pingroup { + const char *name; + const unsigned *pins; + unsigned npins; + + unsigned *funcs; + unsigned nfuncs; + + s16 ctl_reg; + s16 io_reg; + s16 intr_cfg_reg; + s16 intr_status_reg; + s16 intr_target_reg; + + unsigned mux_bit:5; + + unsigned pull_bit:5; + unsigned drv_bit:5; + + unsigned oe_bit:5; + unsigned in_bit:5; + unsigned out_bit:5; + + unsigned intr_enable_bit:5; + unsigned intr_status_bit:5; + unsigned intr_ack_high:1; + + unsigned intr_target_bit:5; + unsigned intr_raw_status_bit:5; + unsigned intr_polarity_bit:5; + unsigned intr_detection_bit:5; + unsigned intr_detection_width:5; +}; + +/** + * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration + * @pins: An array describing all pins the pin controller affects. + * @npins: The number of entries in @pins. + * @functions: An array describing all mux functions the SoC supports. + * @nfunctions: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The numbmer of entries in @groups. + * @ngpio: The number of pingroups the driver should expose as GPIOs. + */ +struct msm_pinctrl_soc_data { + const struct pinctrl_pin_desc *pins; + unsigned npins; + const struct msm_function *functions; + unsigned nfunctions; + const struct msm_pingroup *groups; + unsigned ngroups; + unsigned ngpios; +}; + +int msm_pinctrl_probe(struct platform_device *pdev, + const struct msm_pinctrl_soc_data *soc_data); +int msm_pinctrl_remove(struct platform_device *pdev); + +#endif diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c new file mode 100644 index 000000000000..564543bb2c1c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -0,0 +1,1254 @@ +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8960_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), + PINCTRL_PIN(155, "SDC3_CLK"), + PINCTRL_PIN(156, "SDC3_CMD"), + PINCTRL_PIN(157, "SDC3_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); + +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; +static const unsigned int sdc3_clk_pins[] = { 155 }; +static const unsigned int sdc3_cmd_pins[] = { 156 }; +static const unsigned int sdc3_data_pins[] = { 157 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_NA, /* gpio mode */ \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7, \ + MSM_MUX_##f8, \ + MSM_MUX_##f9, \ + MSM_MUX_##f10, \ + MSM_MUX_##f11 \ + }, \ + .nfuncs = 12, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8960_functions { + MSM_MUX_audio_pcm, + MSM_MUX_bt, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_cam_mclk2, + MSM_MUX_codec_mic_i2s, + MSM_MUX_codec_spkr_i2s, + MSM_MUX_ext_gps, + MSM_MUX_fm, + MSM_MUX_gps_blanking, + MSM_MUX_gps_pps_in, + MSM_MUX_gps_pps_out, + MSM_MUX_gp_clk_0a, + MSM_MUX_gp_clk_0b, + MSM_MUX_gp_clk_1a, + MSM_MUX_gp_clk_1b, + MSM_MUX_gp_clk_2a, + MSM_MUX_gp_clk_2b, + MSM_MUX_gp_mn, + MSM_MUX_gp_pdm_0a, + MSM_MUX_gp_pdm_0b, + MSM_MUX_gp_pdm_1a, + MSM_MUX_gp_pdm_1b, + MSM_MUX_gp_pdm_2a, + MSM_MUX_gp_pdm_2b, + MSM_MUX_gsbi1, + MSM_MUX_gsbi1_spi_cs1_n, + MSM_MUX_gsbi1_spi_cs2a_n, + MSM_MUX_gsbi1_spi_cs2b_n, + MSM_MUX_gsbi1_spi_cs3_n, + MSM_MUX_gsbi2, + MSM_MUX_gsbi2_spi_cs1_n, + MSM_MUX_gsbi2_spi_cs2_n, + MSM_MUX_gsbi2_spi_cs3_n, + MSM_MUX_gsbi3, + MSM_MUX_gsbi4, + MSM_MUX_gsbi4_3d_cam_i2c_l, + MSM_MUX_gsbi4_3d_cam_i2c_r, + MSM_MUX_gsbi5, + MSM_MUX_gsbi5_3d_cam_i2c_l, + MSM_MUX_gsbi5_3d_cam_i2c_r, + MSM_MUX_gsbi6, + MSM_MUX_gsbi7, + MSM_MUX_gsbi8, + MSM_MUX_gsbi9, + MSM_MUX_gsbi10, + MSM_MUX_gsbi11, + MSM_MUX_gsbi11_spi_cs1a_n, + MSM_MUX_gsbi11_spi_cs1b_n, + MSM_MUX_gsbi11_spi_cs2a_n, + MSM_MUX_gsbi11_spi_cs2b_n, + MSM_MUX_gsbi11_spi_cs3_n, + MSM_MUX_gsbi12, + MSM_MUX_hdmi_cec, + MSM_MUX_hdmi_ddc_clock, + MSM_MUX_hdmi_ddc_data, + MSM_MUX_hdmi_hot_plug_detect, + MSM_MUX_hsic, + MSM_MUX_mdp_vsync, + MSM_MUX_mi2s, + MSM_MUX_mic_i2s, + MSM_MUX_pmb_clk, + MSM_MUX_pmb_ext_ctrl, + MSM_MUX_ps_hold, + MSM_MUX_rpm_wdog, + MSM_MUX_sdc2, + MSM_MUX_sdc4, + MSM_MUX_sdc5, + MSM_MUX_slimbus1, + MSM_MUX_slimbus2, + MSM_MUX_spkr_i2s, + MSM_MUX_ssbi1, + MSM_MUX_ssbi2, + MSM_MUX_ssbi_ext_gps, + MSM_MUX_ssbi_pmic2, + MSM_MUX_ssbi_qpa1, + MSM_MUX_ssbi_ts, + MSM_MUX_tsif1, + MSM_MUX_tsif2, + MSM_MUX_ts_eoc, + MSM_MUX_usb_fs1, + MSM_MUX_usb_fs1_oe, + MSM_MUX_usb_fs1_oe_n, + MSM_MUX_usb_fs2, + MSM_MUX_usb_fs2_oe, + MSM_MUX_usb_fs2_oe_n, + MSM_MUX_vfe_camif_timer1_a, + MSM_MUX_vfe_camif_timer1_b, + MSM_MUX_vfe_camif_timer2, + MSM_MUX_vfe_camif_timer3_a, + MSM_MUX_vfe_camif_timer3_b, + MSM_MUX_vfe_camif_timer4_a, + MSM_MUX_vfe_camif_timer4_b, + MSM_MUX_vfe_camif_timer4_c, + MSM_MUX_vfe_camif_timer5_a, + MSM_MUX_vfe_camif_timer5_b, + MSM_MUX_vfe_camif_timer6_a, + MSM_MUX_vfe_camif_timer6_b, + MSM_MUX_vfe_camif_timer6_c, + MSM_MUX_vfe_camif_timer7_a, + MSM_MUX_vfe_camif_timer7_b, + MSM_MUX_vfe_camif_timer7_c, + MSM_MUX_wlan, + MSM_MUX_NA, +}; + +static const char * const audio_pcm_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; + +static const char * const bt_groups[] = { + "gpio28", "gpio29", "gpio83" +}; + +static const char * const cam_mclk0_groups[] = { + "gpio5" +}; + +static const char * const cam_mclk1_groups[] = { + "gpio4" +}; + +static const char * const cam_mclk2_groups[] = { + "gpio2" +}; + +static const char * const codec_mic_i2s_groups[] = { + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58" +}; + +static const char * const codec_spkr_i2s_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62" +}; + +static const char * const ext_gps_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; + +static const char * const fm_groups[] = { + "gpio26", "gpio27" +}; + +static const char * const gps_blanking_groups[] = { + "gpio137" +}; + +static const char * const gps_pps_in_groups[] = { + "gpio37" +}; + +static const char * const gps_pps_out_groups[] = { + "gpio37" +}; + +static const char * const gp_clk_0a_groups[] = { + "gpio3" +}; + +static const char * const gp_clk_0b_groups[] = { + "gpio54" +}; + +static const char * const gp_clk_1a_groups[] = { + "gpio4" +}; + +static const char * const gp_clk_1b_groups[] = { + "gpio70" +}; + +static const char * const gp_clk_2a_groups[] = { + "gpio52" +}; + +static const char * const gp_clk_2b_groups[] = { + "gpio37" +}; + +static const char * const gp_mn_groups[] = { + "gpio2" +}; + +static const char * const gp_pdm_0a_groups[] = { + "gpio58" +}; + +static const char * const gp_pdm_0b_groups[] = { + "gpio39" +}; + +static const char * const gp_pdm_1a_groups[] = { + "gpio94" +}; + +static const char * const gp_pdm_1b_groups[] = { + "gpio64" +}; + +static const char * const gp_pdm_2a_groups[] = { + "gpio69" +}; + +static const char * const gp_pdm_2b_groups[] = { + "gpio53" +}; + +static const char * const gsbi1_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9" +}; + +static const char * const gsbi1_spi_cs1_n_groups[] = { + "gpio14" +}; + +static const char * const gsbi1_spi_cs2a_n_groups[] = { + "gpio15" +}; + +static const char * const gsbi1_spi_cs2b_n_groups[] = { + "gpio17" +}; + +static const char * const gsbi1_spi_cs3_n_groups[] = { + "gpio16" +}; + +static const char * const gsbi2_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; + +static const char * const gsbi2_spi_cs1_n_groups[] = { + "gpio52" +}; + +static const char * const gsbi2_spi_cs2_n_groups[] = { + "gpio68" +}; + +static const char * const gsbi2_spi_cs3_n_groups[] = { + "gpio56" +}; + +static const char * const gsbi3_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17" +}; + +static const char * const gsbi4_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21" +}; + +static const char * const gsbi4_3d_cam_i2c_l_groups[] = { + "gpio18", "gpio19" +}; + +static const char * const gsbi4_3d_cam_i2c_r_groups[] = { + "gpio20", "gpio21" +}; + +static const char * const gsbi5_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; + +static const char * const gsbi5_3d_cam_i2c_l_groups[] = { + "gpio22", "gpio23" +}; + +static const char * const gsbi5_3d_cam_i2c_r_groups[] = { + "gpio24", "gpio25" +}; + +static const char * const gsbi6_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29" +}; + +static const char * const gsbi7_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33" +}; + +static const char * const gsbi8_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37" +}; + +static const char * const gsbi9_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gsbi10_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74" +}; + +static const char * const gsbi11_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41" +}; + +static const char * const gsbi11_spi_cs1a_n_groups[] = { + "gpio36" +}; + +static const char * const gsbi11_spi_cs1b_n_groups[] = { + "gpio18" +}; + +static const char * const gsbi11_spi_cs2a_n_groups[] = { + "gpio37" +}; + +static const char * const gsbi11_spi_cs2b_n_groups[] = { + "gpio19" +}; + +static const char * const gsbi11_spi_cs3_n_groups[] = { + "gpio76" +}; + +static const char * const gsbi12_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45" +}; + +static const char * const hdmi_cec_groups[] = { + "gpio99" +}; + +static const char * const hdmi_ddc_clock_groups[] = { + "gpio100" +}; + +static const char * const hdmi_ddc_data_groups[] = { + "gpio101" +}; + +static const char * const hdmi_hot_plug_detect_groups[] = { + "gpio102" +}; + +static const char * const hsic_groups[] = { + "gpio150", "gpio151" +}; + +static const char * const mdp_vsync_groups[] = { + "gpio0", "gpio1", "gpio19" +}; + +static const char * const mi2s_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53" +}; + +static const char * const mic_i2s_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74" +}; + +static const char * const pmb_clk_groups[] = { + "gpio21", "gpio86", "gpio112" +}; + +static const char * const pmb_ext_ctrl_groups[] = { + "gpio4", "gpio5" +}; + +static const char * const ps_hold_groups[] = { + "gpio108" +}; + +static const char * const rpm_wdog_groups[] = { + "gpio12" +}; + +static const char * const sdc2_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98" +}; + +static const char * const sdc4_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const sdc5_groups[] = { + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const slimbus1_groups[] = { + "gpio50", "gpio51", "gpio60", "gpio61" +}; + +static const char * const slimbus2_groups[] = { + "gpio42", "gpio43" +}; + +static const char * const spkr_i2s_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70" +}; + +static const char * const ssbi1_groups[] = { + "gpio141", "gpio143" +}; + +static const char * const ssbi2_groups[] = { + "gpio140", "gpio142" +}; + +static const char * const ssbi_ext_gps_groups[] = { + "gpio23" +}; + +static const char * const ssbi_pmic2_groups[] = { + "gpio149" +}; + +static const char * const ssbi_qpa1_groups[] = { + "gpio131" +}; + +static const char * const ssbi_ts_groups[] = { + "gpio10" +}; + +static const char * const tsif1_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio82" +}; + +static const char * const tsif2_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81" +}; + +static const char * const ts_eoc_groups[] = { + "gpio11" +}; + +static const char * const usb_fs1_groups[] = { + "gpio32", "gpio33" +}; + +static const char * const usb_fs1_oe_groups[] = { + "gpio31" +}; + +static const char * const usb_fs1_oe_n_groups[] = { + "gpio31" +}; + +static const char * const usb_fs2_groups[] = { + "gpio34", "gpio35" +}; + +static const char * const usb_fs2_oe_groups[] = { + "gpio36" +}; + +static const char * const usb_fs2_oe_n_groups[] = { + "gpio36" +}; + +static const char * const vfe_camif_timer1_a_groups[] = { + "gpio2" +}; + +static const char * const vfe_camif_timer1_b_groups[] = { + "gpio38" +}; + +static const char * const vfe_camif_timer2_groups[] = { + "gpio3" +}; + +static const char * const vfe_camif_timer3_a_groups[] = { + "gpio4" +}; + +static const char * const vfe_camif_timer3_b_groups[] = { + "gpio151" +}; + +static const char * const vfe_camif_timer4_a_groups[] = { + "gpio65" +}; + +static const char * const vfe_camif_timer4_b_groups[] = { + "gpio150" +}; + +static const char * const vfe_camif_timer4_c_groups[] = { + "gpio10" +}; + +static const char * const vfe_camif_timer5_a_groups[] = { + "gpio66" +}; + +static const char * const vfe_camif_timer5_b_groups[] = { + "gpio39" +}; + +static const char * const vfe_camif_timer6_a_groups[] = { + "gpio71" +}; + +static const char * const vfe_camif_timer6_b_groups[] = { + "gpio0" +}; + +static const char * const vfe_camif_timer6_c_groups[] = { + "gpio18" +}; + +static const char * const vfe_camif_timer7_a_groups[] = { + "gpio67" +}; + +static const char * const vfe_camif_timer7_b_groups[] = { + "gpio1" +}; + +static const char * const vfe_camif_timer7_c_groups[] = { + "gpio19" +}; + +static const char * const wlan_groups[] = { + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const struct msm_function msm8960_functions[] = { + FUNCTION(audio_pcm), + FUNCTION(bt), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cam_mclk2), + FUNCTION(codec_mic_i2s), + FUNCTION(codec_spkr_i2s), + FUNCTION(ext_gps), + FUNCTION(fm), + FUNCTION(gps_blanking), + FUNCTION(gps_pps_in), + FUNCTION(gps_pps_out), + FUNCTION(gp_clk_0a), + FUNCTION(gp_clk_0b), + FUNCTION(gp_clk_1a), + FUNCTION(gp_clk_1b), + FUNCTION(gp_clk_2a), + FUNCTION(gp_clk_2b), + FUNCTION(gp_mn), + FUNCTION(gp_pdm_0a), + FUNCTION(gp_pdm_0b), + FUNCTION(gp_pdm_1a), + FUNCTION(gp_pdm_1b), + FUNCTION(gp_pdm_2a), + FUNCTION(gp_pdm_2b), + FUNCTION(gsbi1), + FUNCTION(gsbi1_spi_cs1_n), + FUNCTION(gsbi1_spi_cs2a_n), + FUNCTION(gsbi1_spi_cs2b_n), + FUNCTION(gsbi1_spi_cs3_n), + FUNCTION(gsbi2), + FUNCTION(gsbi2_spi_cs1_n), + FUNCTION(gsbi2_spi_cs2_n), + FUNCTION(gsbi2_spi_cs3_n), + FUNCTION(gsbi3), + FUNCTION(gsbi4), + FUNCTION(gsbi4_3d_cam_i2c_l), + FUNCTION(gsbi4_3d_cam_i2c_r), + FUNCTION(gsbi5), + FUNCTION(gsbi5_3d_cam_i2c_l), + FUNCTION(gsbi5_3d_cam_i2c_r), + FUNCTION(gsbi6), + FUNCTION(gsbi7), + FUNCTION(gsbi8), + FUNCTION(gsbi9), + FUNCTION(gsbi10), + FUNCTION(gsbi11), + FUNCTION(gsbi11_spi_cs1a_n), + FUNCTION(gsbi11_spi_cs1b_n), + FUNCTION(gsbi11_spi_cs2a_n), + FUNCTION(gsbi11_spi_cs2b_n), + FUNCTION(gsbi11_spi_cs3_n), + FUNCTION(gsbi12), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc_clock), + FUNCTION(hdmi_ddc_data), + FUNCTION(hdmi_hot_plug_detect), + FUNCTION(hsic), + FUNCTION(mdp_vsync), + FUNCTION(mi2s), + FUNCTION(mic_i2s), + FUNCTION(pmb_clk), + FUNCTION(pmb_ext_ctrl), + FUNCTION(ps_hold), + FUNCTION(rpm_wdog), + FUNCTION(sdc2), + FUNCTION(sdc4), + FUNCTION(sdc5), + FUNCTION(slimbus1), + FUNCTION(slimbus2), + FUNCTION(spkr_i2s), + FUNCTION(ssbi1), + FUNCTION(ssbi2), + FUNCTION(ssbi_ext_gps), + FUNCTION(ssbi_pmic2), + FUNCTION(ssbi_qpa1), + FUNCTION(ssbi_ts), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(ts_eoc), + FUNCTION(usb_fs1), + FUNCTION(usb_fs1_oe), + FUNCTION(usb_fs1_oe_n), + FUNCTION(usb_fs2), + FUNCTION(usb_fs2_oe), + FUNCTION(usb_fs2_oe_n), + FUNCTION(vfe_camif_timer1_a), + FUNCTION(vfe_camif_timer1_b), + FUNCTION(vfe_camif_timer2), + FUNCTION(vfe_camif_timer3_a), + FUNCTION(vfe_camif_timer3_b), + FUNCTION(vfe_camif_timer4_a), + FUNCTION(vfe_camif_timer4_b), + FUNCTION(vfe_camif_timer4_c), + FUNCTION(vfe_camif_timer5_a), + FUNCTION(vfe_camif_timer5_b), + FUNCTION(vfe_camif_timer6_a), + FUNCTION(vfe_camif_timer6_b), + FUNCTION(vfe_camif_timer6_c), + FUNCTION(vfe_camif_timer7_a), + FUNCTION(vfe_camif_timer7_b), + FUNCTION(vfe_camif_timer7_c), + FUNCTION(wlan), +}; + +static const struct msm_pingroup msm8960_groups[] = { + PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA), + PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), + PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), + PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), + PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), + PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA), + PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA), + PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b), + PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 152 + +static const struct msm_pinctrl_soc_data msm8960_pinctrl = { + .pins = msm8960_pins, + .npins = ARRAY_SIZE(msm8960_pins), + .functions = msm8960_functions, + .nfunctions = ARRAY_SIZE(msm8960_functions), + .groups = msm8960_groups, + .ngroups = ARRAY_SIZE(msm8960_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8960_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8960_pinctrl); +} + +static const struct of_device_id msm8960_pinctrl_of_match[] = { + { .compatible = "qcom,msm8960-pinctrl", }, + { }, +}; + +static struct platform_driver msm8960_pinctrl_driver = { + .driver = { + .name = "msm8960-pinctrl", + .owner = THIS_MODULE, + .of_match_table = msm8960_pinctrl_of_match, + }, + .probe = msm8960_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8960_pinctrl_init(void) +{ + return platform_driver_register(&msm8960_pinctrl_driver); +} +arch_initcall(msm8960_pinctrl_init); + +static void __exit msm8960_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8960_pinctrl_driver); +} +module_exit(msm8960_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c new file mode 100644 index 000000000000..418306911a6f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -0,0 +1,1040 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8x74_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + + PINCTRL_PIN(146, "SDC1_CLK"), + PINCTRL_PIN(147, "SDC1_CMD"), + PINCTRL_PIN(148, "SDC1_DATA"), + PINCTRL_PIN(149, "SDC2_CLK"), + PINCTRL_PIN(150, "SDC2_CMD"), + PINCTRL_PIN(151, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); + +static const unsigned int sdc1_clk_pins[] = { 146 }; +static const unsigned int sdc1_cmd_pins[] = { 147 }; +static const unsigned int sdc1_data_pins[] = { 148 }; +static const unsigned int sdc2_clk_pins[] = { 149 }; +static const unsigned int sdc2_cmd_pins[] = { 150 }; +static const unsigned int sdc2_data_pins[] = { 151 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_NA, /* gpio mode */ \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +/* + * TODO: Add the rest of the possible functions and fill out + * the pingroup table below. + */ +enum msm8x74_functions { + MSM_MUX_cci_i2c0, + MSM_MUX_cci_i2c1, + MSM_MUX_blsp_i2c1, + MSM_MUX_blsp_i2c2, + MSM_MUX_blsp_i2c3, + MSM_MUX_blsp_i2c4, + MSM_MUX_blsp_i2c5, + MSM_MUX_blsp_i2c6, + MSM_MUX_blsp_i2c7, + MSM_MUX_blsp_i2c8, + MSM_MUX_blsp_i2c9, + MSM_MUX_blsp_i2c10, + MSM_MUX_blsp_i2c11, + MSM_MUX_blsp_i2c12, + MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi1_cs1, + MSM_MUX_blsp_spi1_cs2, + MSM_MUX_blsp_spi1_cs3, + MSM_MUX_blsp_spi2, + MSM_MUX_blsp_spi2_cs1, + MSM_MUX_blsp_spi2_cs2, + MSM_MUX_blsp_spi2_cs3, + MSM_MUX_blsp_spi3, + MSM_MUX_blsp_spi4, + MSM_MUX_blsp_spi5, + MSM_MUX_blsp_spi6, + MSM_MUX_blsp_spi7, + MSM_MUX_blsp_spi8, + MSM_MUX_blsp_spi9, + MSM_MUX_blsp_spi10, + MSM_MUX_blsp_spi10_cs1, + MSM_MUX_blsp_spi10_cs2, + MSM_MUX_blsp_spi10_cs3, + MSM_MUX_blsp_spi11, + MSM_MUX_blsp_spi12, + MSM_MUX_blsp_uart1, + MSM_MUX_blsp_uart2, + MSM_MUX_blsp_uart3, + MSM_MUX_blsp_uart4, + MSM_MUX_blsp_uart5, + MSM_MUX_blsp_uart6, + MSM_MUX_blsp_uart7, + MSM_MUX_blsp_uart8, + MSM_MUX_blsp_uart9, + MSM_MUX_blsp_uart10, + MSM_MUX_blsp_uart11, + MSM_MUX_blsp_uart12, + MSM_MUX_blsp_uim1, + MSM_MUX_blsp_uim2, + MSM_MUX_blsp_uim3, + MSM_MUX_blsp_uim4, + MSM_MUX_blsp_uim5, + MSM_MUX_blsp_uim6, + MSM_MUX_blsp_uim7, + MSM_MUX_blsp_uim8, + MSM_MUX_blsp_uim9, + MSM_MUX_blsp_uim10, + MSM_MUX_blsp_uim11, + MSM_MUX_blsp_uim12, + MSM_MUX_uim1, + MSM_MUX_uim2, + MSM_MUX_uim_batt_alarm, + MSM_MUX_sdc3, + MSM_MUX_sdc4, + MSM_MUX_gcc_gp_clk1, + MSM_MUX_gcc_gp_clk2, + MSM_MUX_gcc_gp_clk3, + MSM_MUX_qua_mi2s, + MSM_MUX_pri_mi2s, + MSM_MUX_spkr_mi2s, + MSM_MUX_ter_mi2s, + MSM_MUX_sec_mi2s, + MSM_MUX_hdmi_cec, + MSM_MUX_hdmi_ddc, + MSM_MUX_hdmi_hpd, + MSM_MUX_edp_hpd, + MSM_MUX_mdp_vsync, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_cam_mclk2, + MSM_MUX_cam_mclk3, + MSM_MUX_cci_timer0, + MSM_MUX_cci_timer1, + MSM_MUX_cci_timer2, + MSM_MUX_cci_timer3, + MSM_MUX_cci_timer4, + MSM_MUX_cci_async_in0, + MSM_MUX_cci_async_in1, + MSM_MUX_cci_async_in2, + MSM_MUX_gp_pdm0, + MSM_MUX_gp_pdm1, + MSM_MUX_gp_pdm2, + MSM_MUX_gp0_clk, + MSM_MUX_gp1_clk, + MSM_MUX_gp_mn, + MSM_MUX_tsif1, + MSM_MUX_tsif2, + MSM_MUX_hsic, + MSM_MUX_grfc, + MSM_MUX_audio_ref_clk, + MSM_MUX_bt, + MSM_MUX_fm, + MSM_MUX_wlan, + MSM_MUX_slimbus, + MSM_MUX_NA, +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi1_cs1_groups[] = { "gpio8" }; +static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" }; +static const char * const blsp_spi1_cs3_groups[] = { "gpio10" }; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" }; +static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" }; +static const char * const blsp_spi2_cs3_groups[] = { "gpio66" }; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" }; +static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" }; + +static const char * const blsp_uart4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; +static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" }; +static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" }; +static const char * const blsp_spi4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; + +static const char * const blsp_uart5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; +static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" }; +static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" }; +static const char * const blsp_spi5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; + +static const char * const blsp_uart6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" }; +static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; +static const char * const blsp_spi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; + +static const char * const blsp_uart7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" }; +static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" }; +static const char * const blsp_spi7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const char * const blsp_uart8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; +static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" }; +static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" }; +static const char * const blsp_spi8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; + +static const char * const blsp_uart9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" }; +static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" }; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const blsp_uart10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" }; +static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" }; +static const char * const blsp_spi10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" }; +static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" }; +static const char * const blsp_spi10_cs3_groups[] = { "gpio90" }; + +static const char * const blsp_uart11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; +static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" }; +static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; +static const char * const blsp_spi11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; + +static const char * const blsp_uart12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; +static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" }; +static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" }; +static const char * const blsp_spi12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const uim1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100" +}; + +static const char * const uim2_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const uim_batt_alarm_groups[] = { "gpio101" }; + +static const char * const sdc3_groups[] = { + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const sdc4_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gp0_clk_groups[] = { "gpio26" }; +static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" }; +static const char * const gp_mn_groups[] = { "gpio29" }; +static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" }; +static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" }; +static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" }; + +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; + +static const char * const spkr_mi2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; + +static const char * const ter_mi2s_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77" +}; + +static const char * const sec_mi2s_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const hdmi_cec_groups[] = { "gpio31" }; +static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" }; +static const char * const hdmi_hpd_groups[] = { "gpio34" }; +static const char * const edp_hpd_groups[] = { "gpio102" }; + +static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" }; +static const char * const cam_mclk0_groups[] = { "gpio15" }; +static const char * const cam_mclk1_groups[] = { "gpio16" }; +static const char * const cam_mclk2_groups[] = { "gpio17" }; +static const char * const cam_mclk3_groups[] = { "gpio18" }; + +static const char * const cci_timer0_groups[] = { "gpio23" }; +static const char * const cci_timer1_groups[] = { "gpio24" }; +static const char * const cci_timer2_groups[] = { "gpio25" }; +static const char * const cci_timer3_groups[] = { "gpio26" }; +static const char * const cci_timer4_groups[] = { "gpio27" }; +static const char * const cci_async_in0_groups[] = { "gpio28" }; +static const char * const cci_async_in1_groups[] = { "gpio26" }; +static const char * const cci_async_in2_groups[] = { "gpio27" }; + +static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" }; +static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" }; +static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" }; + +static const char * const tsif1_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92" +}; + +static const char * const tsif2_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const hsic_groups[] = { "gpio144", "gpio145" }; +static const char * const grfc_groups[] = { + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", + "gpio128", "gpio136", "gpio137", "gpio141", "gpio143" +}; + +static const char * const audio_ref_clk_groups[] = { "gpio69" }; + +static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" }; + +static const char * const fm_groups[] = { "gpio41", "gpio42" }; + +static const char * const wlan_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; + +static const struct msm_function msm8x74_functions[] = { + FUNCTION(cci_i2c0), + FUNCTION(cci_i2c1), + FUNCTION(uim1), + FUNCTION(uim2), + FUNCTION(uim_batt_alarm), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim4), + FUNCTION(blsp_uim5), + FUNCTION(blsp_uim6), + FUNCTION(blsp_uim7), + FUNCTION(blsp_uim8), + FUNCTION(blsp_uim9), + FUNCTION(blsp_uim10), + FUNCTION(blsp_uim11), + FUNCTION(blsp_uim12), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_i2c7), + FUNCTION(blsp_i2c8), + FUNCTION(blsp_i2c9), + FUNCTION(blsp_i2c10), + FUNCTION(blsp_i2c11), + FUNCTION(blsp_i2c12), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi1_cs1), + FUNCTION(blsp_spi1_cs2), + FUNCTION(blsp_spi1_cs3), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi2_cs1), + FUNCTION(blsp_spi2_cs2), + FUNCTION(blsp_spi2_cs3), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_spi7), + FUNCTION(blsp_spi8), + FUNCTION(blsp_spi9), + FUNCTION(blsp_spi10), + FUNCTION(blsp_spi10_cs1), + FUNCTION(blsp_spi10_cs2), + FUNCTION(blsp_spi10_cs3), + FUNCTION(blsp_spi11), + FUNCTION(blsp_spi12), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(blsp_uart5), + FUNCTION(blsp_uart6), + FUNCTION(blsp_uart7), + FUNCTION(blsp_uart8), + FUNCTION(blsp_uart9), + FUNCTION(blsp_uart10), + FUNCTION(blsp_uart11), + FUNCTION(blsp_uart12), + FUNCTION(sdc3), + FUNCTION(sdc4), + FUNCTION(gcc_gp_clk1), + FUNCTION(gcc_gp_clk2), + FUNCTION(gcc_gp_clk3), + FUNCTION(qua_mi2s), + FUNCTION(pri_mi2s), + FUNCTION(spkr_mi2s), + FUNCTION(ter_mi2s), + FUNCTION(sec_mi2s), + FUNCTION(mdp_vsync), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cam_mclk2), + FUNCTION(cam_mclk3), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cci_async_in0), + FUNCTION(cci_async_in1), + FUNCTION(cci_async_in2), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc), + FUNCTION(hdmi_hpd), + FUNCTION(edp_hpd), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gp0_clk), + FUNCTION(gp1_clk), + FUNCTION(gp_mn), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(hsic), + FUNCTION(grfc), + FUNCTION(audio_ref_clk), + FUNCTION(bt), + FUNCTION(fm), + FUNCTION(wlan), + FUNCTION(slimbus), +}; + +static const struct msm_pingroup msm8x74_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), + PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), + PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA), + PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA), + PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA), + PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA), + PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA), + PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA), + PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA), + PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA), + PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA), + PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA), + PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA), + PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA), + PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA), + PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA), + PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA), + PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA), + PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA), + PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA), + PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA), + PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA), + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA), + PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA), + PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA), + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA), + PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA), + PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA), + PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 146 + +static const struct msm_pinctrl_soc_data msm8x74_pinctrl = { + .pins = msm8x74_pins, + .npins = ARRAY_SIZE(msm8x74_pins), + .functions = msm8x74_functions, + .nfunctions = ARRAY_SIZE(msm8x74_functions), + .groups = msm8x74_groups, + .ngroups = ARRAY_SIZE(msm8x74_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8x74_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8x74_pinctrl); +} + +static const struct of_device_id msm8x74_pinctrl_of_match[] = { + { .compatible = "qcom,msm8974-pinctrl", }, + { }, +}; + +static struct platform_driver msm8x74_pinctrl_driver = { + .driver = { + .name = "msm8x74-pinctrl", + .owner = THIS_MODULE, + .of_match_table = msm8x74_pinctrl_of_match, + }, + .probe = msm8x74_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8x74_pinctrl_init(void) +{ + return platform_driver_register(&msm8x74_pinctrl_driver); +} +arch_initcall(msm8x74_pinctrl_init); + +static void __exit msm8x74_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8x74_pinctrl_driver); +} +module_exit(msm8x74_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); + -- cgit v1.2.3 From aef1d0003d8c9f913fd66a0e06aeb292b29ab6dd Mon Sep 17 00:00:00 2001 From: Himangi Saraogi Date: Mon, 7 Jul 2014 21:39:16 +0530 Subject: sh-pfc: sh73a0: Introduce the use of devm_regulator_register This patch moves data allocated using regulator_register to devm_regulator_register and does away the calls to regulator_unregister. The sh73a0_pinmux_soc_exit function is no longer needed and is removed. Signed-off-by: Himangi Saraogi Acked-by: Julia Lawall Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index ee370de4609a..0bd8f4401b42 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3842,7 +3842,8 @@ static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) cfg.init_data = &sh73a0_vccq_mc0_init_data; cfg.driver_data = pfc; - data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg); + data->vccq_mc0 = devm_regulator_register(pfc->dev, + &sh73a0_vccq_mc0_desc, &cfg); if (IS_ERR(data->vccq_mc0)) { ret = PTR_ERR(data->vccq_mc0); dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", @@ -3855,16 +3856,8 @@ static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) return 0; } -static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc) -{ - struct sh73a0_pinmux_data *data = pfc->soc_data; - - regulator_unregister(data->vccq_mc0); -} - static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { .init = sh73a0_pinmux_soc_init, - .exit = sh73a0_pinmux_soc_exit, .get_bias = sh73a0_pinmux_get_bias, .set_bias = sh73a0_pinmux_set_bias, }; -- cgit v1.2.3 From ebe629a39e04db3fe876d34833a2d8a6a6d4c134 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 10 Jul 2014 17:33:27 +0530 Subject: pinctrl: samsung: Group all drivers in a sub-dir Group all pin control drivers of Samsung platform together in a sub-directory for easy maintenance. Signed-off-by: Sachin Kamat Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 27 +- drivers/pinctrl/Makefile | 8 +- drivers/pinctrl/pinctrl-exynos.c | 1123 ---------------------- drivers/pinctrl/pinctrl-exynos.h | 99 -- drivers/pinctrl/pinctrl-exynos5440.c | 1061 --------------------- drivers/pinctrl/pinctrl-s3c24xx.c | 651 ------------- drivers/pinctrl/pinctrl-s3c64xx.c | 816 ---------------- drivers/pinctrl/pinctrl-samsung.c | 1285 -------------------------- drivers/pinctrl/pinctrl-samsung.h | 251 ----- drivers/pinctrl/samsung/Kconfig | 28 + drivers/pinctrl/samsung/Makefile | 7 + drivers/pinctrl/samsung/pinctrl-exynos.c | 1123 ++++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 99 ++ drivers/pinctrl/samsung/pinctrl-exynos5440.c | 1061 +++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 651 +++++++++++++ drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 816 ++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 1285 ++++++++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.h | 251 +++++ 18 files changed, 5324 insertions(+), 5318 deletions(-) delete mode 100644 drivers/pinctrl/pinctrl-exynos.c delete mode 100644 drivers/pinctrl/pinctrl-exynos.h delete mode 100644 drivers/pinctrl/pinctrl-exynos5440.c delete mode 100644 drivers/pinctrl/pinctrl-s3c24xx.c delete mode 100644 drivers/pinctrl/pinctrl-s3c64xx.c delete mode 100644 drivers/pinctrl/pinctrl-samsung.c delete mode 100644 drivers/pinctrl/pinctrl-samsung.h create mode 100644 drivers/pinctrl/samsung/Kconfig create mode 100644 drivers/pinctrl/samsung/Makefile create mode 100644 drivers/pinctrl/samsung/pinctrl-exynos.c create mode 100644 drivers/pinctrl/samsung/pinctrl-exynos.h create mode 100644 drivers/pinctrl/samsung/pinctrl-exynos5440.c create mode 100644 drivers/pinctrl/samsung/pinctrl-s3c24xx.c create mode 100644 drivers/pinctrl/samsung/pinctrl-s3c64xx.c create mode 100644 drivers/pinctrl/samsung/pinctrl-samsung.c create mode 100644 drivers/pinctrl/samsung/pinctrl-samsung.h (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e2c7e09783fa..53e07c70951f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -332,22 +332,6 @@ config PINCTRL_COH901 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 ports of 8 GPIO pins each. -config PINCTRL_SAMSUNG - bool - select PINMUX - select PINCONF - -config PINCTRL_EXYNOS - bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440" - depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210) - select PINCTRL_SAMSUNG - -config PINCTRL_EXYNOS5440 - bool "Samsung EXYNOS5440 SoC pinctrl driver" - depends on SOC_EXYNOS5440 - select PINMUX - select PINCONF - config PINCTRL_PALMAS bool "Pinctrl driver for the PALMAS Series MFD devices" depends on OF && MFD_PALMAS @@ -359,19 +343,10 @@ config PINCTRL_PALMAS open drain configuration for the Palmas series devices like TPS65913, TPS80036 etc. -config PINCTRL_S3C24XX - bool "Samsung S3C24XX SoC pinctrl driver" - depends on ARCH_S3C24XX - select PINCTRL_SAMSUNG - -config PINCTRL_S3C64XX - bool "Samsung S3C64XX SoC pinctrl driver" - depends on ARCH_S3C64XX - select PINCTRL_SAMSUNG - source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/qcom/Kconfig" +source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index abe17724036c..df6099df7aad 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -56,11 +56,6 @@ obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o -obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o -obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o -obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o -obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o -obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o @@ -70,8 +65,9 @@ obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-$(CONFIG_ARCH_QCOM) += qcom/ +obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ obj-$(CONFIG_SUPERH) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ -obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ +obj-$(CONFIG_ARCH_VT8500) += vt8500/ diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c deleted file mode 100644 index 003bfd874a61..000000000000 --- a/drivers/pinctrl/pinctrl-exynos.c +++ /dev/null @@ -1,1123 +0,0 @@ -/* - * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2012 Linaro Ltd - * http://www.linaro.org - * - * Author: Thomas Abraham - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This file contains the Samsung Exynos specific information required by the - * the Samsung pinctrl/gpiolib driver. It also includes the implementation of - * external gpio and wakeup interrupt support. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-samsung.h" -#include "pinctrl-exynos.h" - -struct exynos_irq_chip { - struct irq_chip chip; - - u32 eint_con; - u32 eint_mask; - u32 eint_pend; -}; - -static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) -{ - return container_of(chip, struct exynos_irq_chip, chip); -} - -static struct samsung_pin_bank_type bank_type_off = { - .fld_width = { 4, 1, 2, 2, 2, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, -}; - -static struct samsung_pin_bank_type bank_type_alive = { - .fld_width = { 4, 1, 2, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, -}; - -/* list of external wakeup controllers supported */ -static const struct of_device_id exynos_wkup_irq_ids[] = { - { .compatible = "samsung,exynos4210-wakeup-eint", }, - { } -}; - -static void exynos_irq_mask(struct irq_data *irqd) -{ - struct irq_chip *chip = irq_data_get_irq_chip(irqd); - struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; - unsigned long mask; - unsigned long flags; - - spin_lock_irqsave(&bank->slock, flags); - - mask = readl(d->virt_base + reg_mask); - mask |= 1 << irqd->hwirq; - writel(mask, d->virt_base + reg_mask); - - spin_unlock_irqrestore(&bank->slock, flags); -} - -static void exynos_irq_ack(struct irq_data *irqd) -{ - struct irq_chip *chip = irq_data_get_irq_chip(irqd); - struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; - - writel(1 << irqd->hwirq, d->virt_base + reg_pend); -} - -static void exynos_irq_unmask(struct irq_data *irqd) -{ - struct irq_chip *chip = irq_data_get_irq_chip(irqd); - struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; - unsigned long mask; - unsigned long flags; - - /* - * Ack level interrupts right before unmask - * - * If we don't do this we'll get a double-interrupt. Level triggered - * interrupts must not fire an interrupt if the level is not - * _currently_ active, even if it was active while the interrupt was - * masked. - */ - if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) - exynos_irq_ack(irqd); - - spin_lock_irqsave(&bank->slock, flags); - - mask = readl(d->virt_base + reg_mask); - mask &= ~(1 << irqd->hwirq); - writel(mask, d->virt_base + reg_mask); - - spin_unlock_irqrestore(&bank->slock, flags); -} - -static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) -{ - struct irq_chip *chip = irq_data_get_irq_chip(irqd); - struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pin_bank_type *bank_type = bank->type; - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned int pin = irqd->hwirq; - unsigned int shift = EXYNOS_EINT_CON_LEN * pin; - unsigned int con, trig_type; - unsigned long reg_con = our_chip->eint_con + bank->eint_offset; - unsigned long flags; - unsigned int mask; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - trig_type = EXYNOS_EINT_EDGE_RISING; - break; - case IRQ_TYPE_EDGE_FALLING: - trig_type = EXYNOS_EINT_EDGE_FALLING; - break; - case IRQ_TYPE_EDGE_BOTH: - trig_type = EXYNOS_EINT_EDGE_BOTH; - break; - case IRQ_TYPE_LEVEL_HIGH: - trig_type = EXYNOS_EINT_LEVEL_HIGH; - break; - case IRQ_TYPE_LEVEL_LOW: - trig_type = EXYNOS_EINT_LEVEL_LOW; - break; - default: - pr_err("unsupported external interrupt type\n"); - return -EINVAL; - } - - if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(irqd->irq, handle_edge_irq); - else - __irq_set_handler_locked(irqd->irq, handle_level_irq); - - con = readl(d->virt_base + reg_con); - con &= ~(EXYNOS_EINT_CON_MASK << shift); - con |= trig_type << shift; - writel(con, d->virt_base + reg_con); - - reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; - shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; - mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; - - spin_lock_irqsave(&bank->slock, flags); - - con = readl(d->virt_base + reg_con); - con &= ~(mask << shift); - con |= EXYNOS_EINT_FUNC << shift; - writel(con, d->virt_base + reg_con); - - spin_unlock_irqrestore(&bank->slock, flags); - - return 0; -} - -/* - * irq_chip for gpio interrupts. - */ -static struct exynos_irq_chip exynos_gpio_irq_chip = { - .chip = { - .name = "exynos_gpio_irq_chip", - .irq_unmask = exynos_irq_unmask, - .irq_mask = exynos_irq_mask, - .irq_ack = exynos_irq_ack, - .irq_set_type = exynos_irq_set_type, - }, - .eint_con = EXYNOS_GPIO_ECON_OFFSET, - .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, - .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, -}; - -static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct samsung_pin_bank *b = h->host_data; - - irq_set_chip_data(virq, b); - irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip, - handle_level_irq); - set_irq_flags(virq, IRQF_VALID); - return 0; -} - -/* - * irq domain callbacks for external gpio interrupt controller. - */ -static const struct irq_domain_ops exynos_gpio_irqd_ops = { - .map = exynos_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) -{ - struct samsung_pinctrl_drv_data *d = data; - struct samsung_pin_ctrl *ctrl = d->ctrl; - struct samsung_pin_bank *bank = ctrl->pin_banks; - unsigned int svc, group, pin, virq; - - svc = readl(d->virt_base + EXYNOS_SVC_OFFSET); - group = EXYNOS_SVC_GROUP(svc); - pin = svc & EXYNOS_SVC_NUM_MASK; - - if (!group) - return IRQ_HANDLED; - bank += (group - 1); - - virq = irq_linear_revmap(bank->irq_domain, pin); - if (!virq) - return IRQ_NONE; - generic_handle_irq(virq); - return IRQ_HANDLED; -} - -struct exynos_eint_gpio_save { - u32 eint_con; - u32 eint_fltcon0; - u32 eint_fltcon1; -}; - -/* - * exynos_eint_gpio_init() - setup handling of external gpio interrupts. - * @d: driver data of samsung pinctrl driver. - */ -static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) -{ - struct samsung_pin_bank *bank; - struct device *dev = d->dev; - int ret; - int i; - - if (!d->irq) { - dev_err(dev, "irq number not available\n"); - return -EINVAL; - } - - ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, - 0, dev_name(dev), d); - if (ret) { - dev_err(dev, "irq request failed\n"); - return -ENXIO; - } - - bank = d->ctrl->pin_banks; - for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { - if (bank->eint_type != EINT_TYPE_GPIO) - continue; - bank->irq_domain = irq_domain_add_linear(bank->of_node, - bank->nr_pins, &exynos_gpio_irqd_ops, bank); - if (!bank->irq_domain) { - dev_err(dev, "gpio irq domain add failed\n"); - ret = -ENXIO; - goto err_domains; - } - - bank->soc_priv = devm_kzalloc(d->dev, - sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); - if (!bank->soc_priv) { - irq_domain_remove(bank->irq_domain); - ret = -ENOMEM; - goto err_domains; - } - } - - return 0; - -err_domains: - for (--i, --bank; i >= 0; --i, --bank) { - if (bank->eint_type != EINT_TYPE_GPIO) - continue; - irq_domain_remove(bank->irq_domain); - } - - return ret; -} - -static u32 exynos_eint_wake_mask = 0xffffffff; - -u32 exynos_get_eint_wake_mask(void) -{ - return exynos_eint_wake_mask; -} - -static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); - - pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); - - if (!on) - exynos_eint_wake_mask |= bit; - else - exynos_eint_wake_mask &= ~bit; - - return 0; -} - -/* - * irq_chip for wakeup interrupts - */ -static struct exynos_irq_chip exynos_wkup_irq_chip = { - .chip = { - .name = "exynos_wkup_irq_chip", - .irq_unmask = exynos_irq_unmask, - .irq_mask = exynos_irq_mask, - .irq_ack = exynos_irq_ack, - .irq_set_type = exynos_irq_set_type, - .irq_set_wake = exynos_wkup_irq_set_wake, - }, - .eint_con = EXYNOS_WKUP_ECON_OFFSET, - .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, - .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, -}; - -/* interrupt handler for wakeup interrupts 0..15 */ -static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) -{ - struct exynos_weint_data *eintd = irq_get_handler_data(irq); - struct samsung_pin_bank *bank = eintd->bank; - struct irq_chip *chip = irq_get_chip(irq); - int eint_irq; - - chained_irq_enter(chip, desc); - chip->irq_mask(&desc->irq_data); - - if (chip->irq_ack) - chip->irq_ack(&desc->irq_data); - - eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); - generic_handle_irq(eint_irq); - chip->irq_unmask(&desc->irq_data); - chained_irq_exit(chip, desc); -} - -static inline void exynos_irq_demux_eint(unsigned long pend, - struct irq_domain *domain) -{ - unsigned int irq; - - while (pend) { - irq = fls(pend) - 1; - generic_handle_irq(irq_find_mapping(domain, irq)); - pend &= ~(1 << irq); - } -} - -/* interrupt handler for wakeup interrupt 16 */ -static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) -{ - struct irq_chip *chip = irq_get_chip(irq); - struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); - struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; - unsigned long pend; - unsigned long mask; - int i; - - chained_irq_enter(chip, desc); - - for (i = 0; i < eintd->nr_banks; ++i) { - struct samsung_pin_bank *b = eintd->banks[i]; - pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET - + b->eint_offset); - mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET - + b->eint_offset); - exynos_irq_demux_eint(pend & ~mask, b->irq_domain); - } - - chained_irq_exit(chip, desc); -} - -static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip, - handle_level_irq); - irq_set_chip_data(virq, h->host_data); - set_irq_flags(virq, IRQF_VALID); - return 0; -} - -/* - * irq domain callbacks for external wakeup interrupt controller. - */ -static const struct irq_domain_ops exynos_wkup_irqd_ops = { - .map = exynos_wkup_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -/* - * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. - * @d: driver data of samsung pinctrl driver. - */ -static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) -{ - struct device *dev = d->dev; - struct device_node *wkup_np = NULL; - struct device_node *np; - struct samsung_pin_bank *bank; - struct exynos_weint_data *weint_data; - struct exynos_muxed_weint_data *muxed_data; - unsigned int muxed_banks = 0; - unsigned int i; - int idx, irq; - - for_each_child_of_node(dev->of_node, np) { - if (of_match_node(exynos_wkup_irq_ids, np)) { - wkup_np = np; - break; - } - } - if (!wkup_np) - return -ENODEV; - - bank = d->ctrl->pin_banks; - for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { - if (bank->eint_type != EINT_TYPE_WKUP) - continue; - - bank->irq_domain = irq_domain_add_linear(bank->of_node, - bank->nr_pins, &exynos_wkup_irqd_ops, bank); - if (!bank->irq_domain) { - dev_err(dev, "wkup irq domain add failed\n"); - return -ENXIO; - } - - if (!of_find_property(bank->of_node, "interrupts", NULL)) { - bank->eint_type = EINT_TYPE_WKUP_MUX; - ++muxed_banks; - continue; - } - - weint_data = devm_kzalloc(dev, bank->nr_pins - * sizeof(*weint_data), GFP_KERNEL); - if (!weint_data) { - dev_err(dev, "could not allocate memory for weint_data\n"); - return -ENOMEM; - } - - for (idx = 0; idx < bank->nr_pins; ++idx) { - irq = irq_of_parse_and_map(bank->of_node, idx); - if (!irq) { - dev_err(dev, "irq number for eint-%s-%d not found\n", - bank->name, idx); - continue; - } - weint_data[idx].irq = idx; - weint_data[idx].bank = bank; - irq_set_handler_data(irq, &weint_data[idx]); - irq_set_chained_handler(irq, exynos_irq_eint0_15); - } - } - - if (!muxed_banks) - return 0; - - irq = irq_of_parse_and_map(wkup_np, 0); - if (!irq) { - dev_err(dev, "irq number for muxed EINTs not found\n"); - return 0; - } - - muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) - + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); - if (!muxed_data) { - dev_err(dev, "could not allocate memory for muxed_data\n"); - return -ENOMEM; - } - - irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); - irq_set_handler_data(irq, muxed_data); - - bank = d->ctrl->pin_banks; - idx = 0; - for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { - if (bank->eint_type != EINT_TYPE_WKUP_MUX) - continue; - - muxed_data->banks[idx++] = bank; - } - muxed_data->nr_banks = muxed_banks; - - return 0; -} - -static void exynos_pinctrl_suspend_bank( - struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) -{ - struct exynos_eint_gpio_save *save = bank->soc_priv; - void __iomem *regs = drvdata->virt_base; - - save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset); - save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset); - save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4); - - pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); - pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); - pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); -} - -static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) -{ - struct samsung_pin_ctrl *ctrl = drvdata->ctrl; - struct samsung_pin_bank *bank = ctrl->pin_banks; - int i; - - for (i = 0; i < ctrl->nr_banks; ++i, ++bank) - if (bank->eint_type == EINT_TYPE_GPIO) - exynos_pinctrl_suspend_bank(drvdata, bank); -} - -static void exynos_pinctrl_resume_bank( - struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) -{ - struct exynos_eint_gpio_save *save = bank->soc_priv; - void __iomem *regs = drvdata->virt_base; - - pr_debug("%s: con %#010x => %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset), save->eint_con); - pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset), save->eint_fltcon0); - pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4), save->eint_fltcon1); - - writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset); - writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset); - writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4); -} - -static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) -{ - struct samsung_pin_ctrl *ctrl = drvdata->ctrl; - struct samsung_pin_bank *bank = ctrl->pin_banks; - int i; - - for (i = 0; i < ctrl->nr_banks; ++i, ++bank) - if (bank->eint_type == EINT_TYPE_GPIO) - exynos_pinctrl_resume_bank(drvdata, bank); -} - -/* pin banks of s5pv210 pin-controller */ -static struct samsung_pin_bank s5pv210_pin_bank[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), - EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), - EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), - EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), - EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), - EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), - EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), - EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), - EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), - EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), - EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), - EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), - EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), - EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), - EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), - EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), - EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), - EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), - EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), - EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), - EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), - EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), - EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), - EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), -}; - -struct samsung_pin_ctrl s5pv210_pin_ctrl[] = { - { - /* pin-controller instance 0 data */ - .pin_banks = s5pv210_pin_bank, - .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "s5pv210-gpio-ctrl0", - }, -}; - -/* pin banks of exynos3250 pin-controller 0 */ -static struct samsung_pin_bank exynos3250_pin_banks0[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), -}; - -/* pin banks of exynos3250 pin-controller 1 */ -static struct samsung_pin_bank exynos3250_pin_banks1[] = { - EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), - EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), - EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), - EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), - EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), - EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), - EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), -}; - -/* - * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes - * two gpio/pin-mux/pinconfig controllers. - */ -struct samsung_pin_ctrl exynos3250_pin_ctrl[] = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos3250_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos3250-gpio-ctrl0", - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos3250_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos3250-gpio-ctrl1", - }, -}; - -/* pin banks of exynos4210 pin-controller 0 */ -static struct samsung_pin_bank exynos4210_pin_banks0[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), - EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), - EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), - EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), - EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), - EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), - EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), -}; - -/* pin banks of exynos4210 pin-controller 1 */ -static struct samsung_pin_bank exynos4210_pin_banks1[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), - EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), - EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), - EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), - EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), - EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), - EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), - EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos4210 pin-controller 2 */ -static struct samsung_pin_bank exynos4210_pin_banks2[] = { - EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), -}; - -/* - * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes - * three gpio/pin-mux/pinconfig controllers. - */ -struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos4210_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos4210-gpio-ctrl0", - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos4210_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos4210-gpio-ctrl1", - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos4210_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), - .label = "exynos4210-gpio-ctrl2", - }, -}; - -/* pin banks of exynos4x12 pin-controller 0 */ -static struct samsung_pin_bank exynos4x12_pin_banks0[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), - EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), - EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), - EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), - EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), -}; - -/* pin banks of exynos4x12 pin-controller 1 */ -static struct samsung_pin_bank exynos4x12_pin_banks1[] = { - EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), - EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), - EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), - EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), - EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), - EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), - EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), - EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), - EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos4x12 pin-controller 2 */ -static struct samsung_pin_bank exynos4x12_pin_banks2[] = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), -}; - -/* pin banks of exynos4x12 pin-controller 3 */ -static struct samsung_pin_bank exynos4x12_pin_banks3[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), - EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), -}; - -/* - * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes - * four gpio/pin-mux/pinconfig controllers. - */ -struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos4x12_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos4x12-gpio-ctrl0", - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos4x12_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos4x12-gpio-ctrl1", - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos4x12_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos4x12-gpio-ctrl2", - }, { - /* pin-controller instance 3 data */ - .pin_banks = exynos4x12_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos4x12-gpio-ctrl3", - }, -}; - -/* pin banks of exynos5250 pin-controller 0 */ -static struct samsung_pin_bank exynos5250_pin_banks0[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), - EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), - EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), - EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), - EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), - EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), - EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos5250 pin-controller 1 */ -static struct samsung_pin_bank exynos5250_pin_banks1[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), - EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), - EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), - EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), - EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), - EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), -}; - -/* pin banks of exynos5250 pin-controller 2 */ -static struct samsung_pin_bank exynos5250_pin_banks2[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), - EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), -}; - -/* pin banks of exynos5250 pin-controller 3 */ -static struct samsung_pin_bank exynos5250_pin_banks3[] = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), -}; - -/* - * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes - * four gpio/pin-mux/pinconfig controllers. - */ -struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos5250_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos5250-gpio-ctrl0", - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos5250_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos5250-gpio-ctrl1", - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos5250_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos5250-gpio-ctrl2", - }, { - /* pin-controller instance 3 data */ - .pin_banks = exynos5250_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .label = "exynos5250-gpio-ctrl3", - }, -}; - -/* pin banks of exynos5260 pin-controller 0 */ -static struct samsung_pin_bank exynos5260_pin_banks0[] = { - EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), - EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), - EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), - EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), - EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), - EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), - EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), - EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), - EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), - EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), -}; - -/* pin banks of exynos5260 pin-controller 1 */ -static struct samsung_pin_bank exynos5260_pin_banks1[] = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), - EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), - EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), - EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), -}; - -/* pin banks of exynos5260 pin-controller 2 */ -static struct samsung_pin_bank exynos5260_pin_banks2[] = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), - EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), -}; - -/* - * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes - * three gpio/pin-mux/pinconfig controllers. - */ -struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos5260_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .label = "exynos5260-gpio-ctrl0", - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos5260_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .label = "exynos5260-gpio-ctrl1", - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos5260_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .label = "exynos5260-gpio-ctrl2", - }, -}; - -/* pin banks of exynos5420 pin-controller 0 */ -static struct samsung_pin_bank exynos5420_pin_banks0[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos5420 pin-controller 1 */ -static struct samsung_pin_bank exynos5420_pin_banks1[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), - EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), - EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), - EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), - EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), -}; - -/* pin banks of exynos5420 pin-controller 2 */ -static struct samsung_pin_bank exynos5420_pin_banks2[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), - EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), - EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), - EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), - EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), -}; - -/* pin banks of exynos5420 pin-controller 3 */ -static struct samsung_pin_bank exynos5420_pin_banks3[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), - EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), -}; - -/* pin banks of exynos5420 pin-controller 4 */ -static struct samsung_pin_bank exynos5420_pin_banks4[] = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), -}; - -/* - * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes - * four gpio/pin-mux/pinconfig controllers. - */ -struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos5420_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .label = "exynos5420-gpio-ctrl0", - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos5420_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .label = "exynos5420-gpio-ctrl1", - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos5420_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .label = "exynos5420-gpio-ctrl2", - }, { - /* pin-controller instance 3 data */ - .pin_banks = exynos5420_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - .label = "exynos5420-gpio-ctrl3", - }, { - /* pin-controller instance 4 data */ - .pin_banks = exynos5420_pin_banks4, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), - .eint_gpio_init = exynos_eint_gpio_init, - .label = "exynos5420-gpio-ctrl4", - }, -}; diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h deleted file mode 100644 index 3c91c357792f..000000000000 --- a/drivers/pinctrl/pinctrl-exynos.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Exynos specific definitions for Samsung pinctrl and gpiolib driver. - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2012 Linaro Ltd - * http://www.linaro.org - * - * This file contains the Exynos specific definitions for the Samsung - * pinctrl/gpiolib interface drivers. - * - * Author: Thomas Abraham - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/* External GPIO and wakeup interrupt related definitions */ -#define EXYNOS_GPIO_ECON_OFFSET 0x700 -#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 -#define EXYNOS_GPIO_EMASK_OFFSET 0x900 -#define EXYNOS_GPIO_EPEND_OFFSET 0xA00 -#define EXYNOS_WKUP_ECON_OFFSET 0xE00 -#define EXYNOS_WKUP_EMASK_OFFSET 0xF00 -#define EXYNOS_WKUP_EPEND_OFFSET 0xF40 -#define EXYNOS_SVC_OFFSET 0xB08 -#define EXYNOS_EINT_FUNC 0xF - -/* helpers to access interrupt service register */ -#define EXYNOS_SVC_GROUP_SHIFT 3 -#define EXYNOS_SVC_GROUP_MASK 0x1f -#define EXYNOS_SVC_NUM_MASK 7 -#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ - EXYNOS_SVC_GROUP_MASK) - -/* Exynos specific external interrupt trigger types */ -#define EXYNOS_EINT_LEVEL_LOW 0 -#define EXYNOS_EINT_LEVEL_HIGH 1 -#define EXYNOS_EINT_EDGE_FALLING 2 -#define EXYNOS_EINT_EDGE_RISING 3 -#define EXYNOS_EINT_EDGE_BOTH 4 -#define EXYNOS_EINT_CON_MASK 0xF -#define EXYNOS_EINT_CON_LEN 4 - -#define EXYNOS_EINT_MAX_PER_BANK 8 -#define EXYNOS_EINT_NR_WKUP_EINT - -#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ - { \ - .type = &bank_type_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ - { \ - .type = &bank_type_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_GPIO, \ - .eint_offset = offs, \ - .name = id \ - } - -#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ - { \ - .type = &bank_type_alive, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_offset = offs, \ - .name = id \ - } - -/** - * struct exynos_weint_data: irq specific data for all the wakeup interrupts - * generated by the external wakeup interrupt controller. - * @irq: interrupt number within the domain. - * @bank: bank responsible for this interrupt - */ -struct exynos_weint_data { - unsigned int irq; - struct samsung_pin_bank *bank; -}; - -/** - * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts - * generated by the external wakeup interrupt controller. - * @nr_banks: count of banks being part of the mux - * @banks: array of banks being part of the mux - */ -struct exynos_muxed_weint_data { - unsigned int nr_banks; - struct samsung_pin_bank *banks[]; -}; diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c deleted file mode 100644 index 4b145b5db7a6..000000000000 --- a/drivers/pinctrl/pinctrl-exynos5440.c +++ /dev/null @@ -1,1061 +0,0 @@ -/* - * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC. - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "core.h" - -/* EXYNOS5440 GPIO and Pinctrl register offsets */ -#define GPIO_MUX 0x00 -#define GPIO_IE 0x04 -#define GPIO_INT 0x08 -#define GPIO_TYPE 0x0C -#define GPIO_VAL 0x10 -#define GPIO_OE 0x14 -#define GPIO_IN 0x18 -#define GPIO_PE 0x1C -#define GPIO_PS 0x20 -#define GPIO_SR 0x24 -#define GPIO_DS0 0x28 -#define GPIO_DS1 0x2C - -#define EXYNOS5440_MAX_PINS 23 -#define EXYNOS5440_MAX_GPIO_INT 8 -#define PIN_NAME_LENGTH 10 - -#define GROUP_SUFFIX "-grp" -#define GSUFFIX_LEN sizeof(GROUP_SUFFIX) -#define FUNCTION_SUFFIX "-mux" -#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX) - -/* - * pin configuration type and its value are packed together into a 16-bits. - * The upper 8-bits represent the configuration type and the lower 8-bits - * hold the value of the configuration type. - */ -#define PINCFG_TYPE_MASK 0xFF -#define PINCFG_VALUE_SHIFT 8 -#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) -#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) -#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) -#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ - PINCFG_VALUE_SHIFT) - -/** - * enum pincfg_type - possible pin configuration types supported. - * @PINCFG_TYPE_PUD: Pull up/down configuration. - * @PINCFG_TYPE_DRV: Drive strength configuration. - * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration. - * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration. - */ -enum pincfg_type { - PINCFG_TYPE_PUD, - PINCFG_TYPE_DRV, - PINCFG_TYPE_SKEW_RATE, - PINCFG_TYPE_INPUT_TYPE -}; - -/** - * struct exynos5440_pin_group: represent group of pins for pincfg setting. - * @name: name of the pin group, used to lookup the group. - * @pins: the pins included in this group. - * @num_pins: number of pins included in this group. - */ -struct exynos5440_pin_group { - const char *name; - const unsigned int *pins; - u8 num_pins; -}; - -/** - * struct exynos5440_pmx_func: represent a pin function. - * @name: name of the pin function, used to lookup the function. - * @groups: one or more names of pin groups that provide this function. - * @num_groups: number of groups included in @groups. - * @function: the function number to be programmed when selected. - */ -struct exynos5440_pmx_func { - const char *name; - const char **groups; - u8 num_groups; - unsigned long function; -}; - -/** - * struct exynos5440_pinctrl_priv_data: driver's private runtime data. - * @reg_base: ioremapped based address of the register space. - * @gc: gpio chip registered with gpiolib. - * @pin_groups: list of pin groups parsed from device tree. - * @nr_groups: number of pin groups available. - * @pmx_functions: list of pin functions parsed from device tree. - * @nr_functions: number of pin functions available. - */ -struct exynos5440_pinctrl_priv_data { - void __iomem *reg_base; - struct gpio_chip *gc; - struct irq_domain *irq_domain; - - const struct exynos5440_pin_group *pin_groups; - unsigned int nr_groups; - const struct exynos5440_pmx_func *pmx_functions; - unsigned int nr_functions; -}; - -/** - * struct exynos5440_gpio_intr_data: private data for gpio interrupts. - * @priv: driver's private runtime data. - * @gpio_int: gpio interrupt number. - */ -struct exynos5440_gpio_intr_data { - struct exynos5440_pinctrl_priv_data *priv; - unsigned int gpio_int; -}; - -/* list of all possible config options supported */ -static struct pin_config { - char *prop_cfg; - unsigned int cfg_type; -} pcfgs[] = { - { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD }, - { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV }, - { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE }, - { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE }, -}; - -/* check if the selector is a valid pin group selector */ -static int exynos5440_get_group_count(struct pinctrl_dev *pctldev) -{ - struct exynos5440_pinctrl_priv_data *priv; - - priv = pinctrl_dev_get_drvdata(pctldev); - return priv->nr_groups; -} - -/* return the name of the group selected by the group selector */ -static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct exynos5440_pinctrl_priv_data *priv; - - priv = pinctrl_dev_get_drvdata(pctldev); - return priv->pin_groups[selector].name; -} - -/* return the pin numbers associated with the specified group */ -static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev, - unsigned selector, const unsigned **pins, unsigned *num_pins) -{ - struct exynos5440_pinctrl_priv_data *priv; - - priv = pinctrl_dev_get_drvdata(pctldev); - *pins = priv->pin_groups[selector].pins; - *num_pins = priv->pin_groups[selector].num_pins; - return 0; -} - -/* create pinctrl_map entries by parsing device tree nodes */ -static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, struct pinctrl_map **maps, - unsigned *nmaps) -{ - struct device *dev = pctldev->dev; - struct pinctrl_map *map; - unsigned long *cfg = NULL; - char *gname, *fname; - int cfg_cnt = 0, map_cnt = 0, idx = 0; - - /* count the number of config options specfied in the node */ - for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) - if (of_find_property(np, pcfgs[idx].prop_cfg, NULL)) - cfg_cnt++; - - /* - * Find out the number of map entries to create. All the config options - * can be accomadated into a single config map entry. - */ - if (cfg_cnt) - map_cnt = 1; - if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) - map_cnt++; - if (!map_cnt) { - dev_err(dev, "node %s does not have either config or function " - "configurations\n", np->name); - return -EINVAL; - } - - /* Allocate memory for pin-map entries */ - map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); - if (!map) { - dev_err(dev, "could not alloc memory for pin-maps\n"); - return -ENOMEM; - } - *nmaps = 0; - - /* - * Allocate memory for pin group name. The pin group name is derived - * from the node name from which these map entries are be created. - */ - gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); - if (!gname) { - dev_err(dev, "failed to alloc memory for group name\n"); - goto free_map; - } - snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX); - - /* - * don't have config options? then skip over to creating function - * map entries. - */ - if (!cfg_cnt) - goto skip_cfgs; - - /* Allocate memory for config entries */ - cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); - if (!cfg) { - dev_err(dev, "failed to alloc memory for configs\n"); - goto free_gname; - } - - /* Prepare a list of config settings */ - for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { - u32 value; - if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value)) - cfg[cfg_cnt++] = - PINCFG_PACK(pcfgs[idx].cfg_type, value); - } - - /* create the config map entry */ - map[*nmaps].data.configs.group_or_pin = gname; - map[*nmaps].data.configs.configs = cfg; - map[*nmaps].data.configs.num_configs = cfg_cnt; - map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - *nmaps += 1; - -skip_cfgs: - /* create the function map entry */ - if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { - fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); - if (!fname) { - dev_err(dev, "failed to alloc memory for func name\n"); - goto free_cfg; - } - snprintf(fname, strlen(np->name) + 4, "%s%s", np->name, - FUNCTION_SUFFIX); - - map[*nmaps].data.mux.group = gname; - map[*nmaps].data.mux.function = fname; - map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP; - *nmaps += 1; - } - - *maps = map; - return 0; - -free_cfg: - kfree(cfg); -free_gname: - kfree(gname); -free_map: - kfree(map); - return -ENOMEM; -} - -/* free the memory allocated to hold the pin-map table */ -static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int idx; - - for (idx = 0; idx < num_maps; idx++) { - if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) { - kfree(map[idx].data.mux.function); - if (!idx) - kfree(map[idx].data.mux.group); - } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) { - kfree(map[idx].data.configs.configs); - if (!idx) - kfree(map[idx].data.configs.group_or_pin); - } - }; - - kfree(map); -} - -/* list of pinctrl callbacks for the pinctrl core */ -static const struct pinctrl_ops exynos5440_pctrl_ops = { - .get_groups_count = exynos5440_get_group_count, - .get_group_name = exynos5440_get_group_name, - .get_group_pins = exynos5440_get_group_pins, - .dt_node_to_map = exynos5440_dt_node_to_map, - .dt_free_map = exynos5440_dt_free_map, -}; - -/* check if the selector is a valid pin function selector */ -static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct exynos5440_pinctrl_priv_data *priv; - - priv = pinctrl_dev_get_drvdata(pctldev); - return priv->nr_functions; -} - -/* return the name of the pin function specified */ -static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct exynos5440_pinctrl_priv_data *priv; - - priv = pinctrl_dev_get_drvdata(pctldev); - return priv->pmx_functions[selector].name; -} - -/* return the groups associated for the specified function selector */ -static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev, - unsigned selector, const char * const **groups, - unsigned * const num_groups) -{ - struct exynos5440_pinctrl_priv_data *priv; - - priv = pinctrl_dev_get_drvdata(pctldev); - *groups = priv->pmx_functions[selector].groups; - *num_groups = priv->pmx_functions[selector].num_groups; - return 0; -} - -/* enable or disable a pinmux function */ -static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group, bool enable) -{ - struct exynos5440_pinctrl_priv_data *priv; - void __iomem *base; - u32 function; - u32 data; - - priv = pinctrl_dev_get_drvdata(pctldev); - base = priv->reg_base; - function = priv->pmx_functions[selector].function; - - data = readl(base + GPIO_MUX); - if (enable) - data |= (1 << function); - else - data &= ~(1 << function); - writel(data, base + GPIO_MUX); -} - -/* enable a specified pinmux by writing to registers */ -static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - exynos5440_pinmux_setup(pctldev, selector, group, true); - return 0; -} - -/* - * The calls to gpio_direction_output() and gpio_direction_input() - * leads to this function call (via the pinctrl_gpio_direction_{input|output}() - * function called from the gpiolib interface). - */ -static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned offset, bool input) -{ - return 0; -} - -/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ -static const struct pinmux_ops exynos5440_pinmux_ops = { - .get_functions_count = exynos5440_get_functions_count, - .get_function_name = exynos5440_pinmux_get_fname, - .get_function_groups = exynos5440_pinmux_get_groups, - .enable = exynos5440_pinmux_enable, - .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, -}; - -/* set the pin config settings for a specified pin */ -static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, - unsigned num_configs) -{ - struct exynos5440_pinctrl_priv_data *priv; - void __iomem *base; - enum pincfg_type cfg_type; - u32 cfg_value; - u32 data; - int i; - - priv = pinctrl_dev_get_drvdata(pctldev); - base = priv->reg_base; - - for (i = 0; i < num_configs; i++) { - cfg_type = PINCFG_UNPACK_TYPE(configs[i]); - cfg_value = PINCFG_UNPACK_VALUE(configs[i]); - - switch (cfg_type) { - case PINCFG_TYPE_PUD: - /* first set pull enable/disable bit */ - data = readl(base + GPIO_PE); - data &= ~(1 << pin); - if (cfg_value) - data |= (1 << pin); - writel(data, base + GPIO_PE); - - /* then set pull up/down bit */ - data = readl(base + GPIO_PS); - data &= ~(1 << pin); - if (cfg_value == 2) - data |= (1 << pin); - writel(data, base + GPIO_PS); - break; - - case PINCFG_TYPE_DRV: - /* set the first bit of the drive strength */ - data = readl(base + GPIO_DS0); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_DS0); - cfg_value >>= 1; - - /* set the second bit of the driver strength */ - data = readl(base + GPIO_DS1); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_DS1); - break; - case PINCFG_TYPE_SKEW_RATE: - data = readl(base + GPIO_SR); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_SR); - break; - case PINCFG_TYPE_INPUT_TYPE: - data = readl(base + GPIO_TYPE); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_TYPE); - break; - default: - WARN_ON(1); - return -EINVAL; - } - } /* for each config */ - - return 0; -} - -/* get the pin config settings for a specified pin */ -static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *config) -{ - struct exynos5440_pinctrl_priv_data *priv; - void __iomem *base; - enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); - u32 data; - - priv = pinctrl_dev_get_drvdata(pctldev); - base = priv->reg_base; - - switch (cfg_type) { - case PINCFG_TYPE_PUD: - data = readl(base + GPIO_PE); - data = (data >> pin) & 1; - if (!data) - *config = 0; - else - *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1; - break; - case PINCFG_TYPE_DRV: - data = readl(base + GPIO_DS0); - data = (data >> pin) & 1; - *config = data; - data = readl(base + GPIO_DS1); - data = (data >> pin) & 1; - *config |= (data << 1); - break; - case PINCFG_TYPE_SKEW_RATE: - data = readl(base + GPIO_SR); - *config = (data >> pin) & 1; - break; - case PINCFG_TYPE_INPUT_TYPE: - data = readl(base + GPIO_TYPE); - *config = (data >> pin) & 1; - break; - default: - WARN_ON(1); - return -EINVAL; - } - - return 0; -} - -/* set the pin config settings for a specified pin group */ -static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long *configs, - unsigned num_configs) -{ - struct exynos5440_pinctrl_priv_data *priv; - const unsigned int *pins; - unsigned int cnt; - - priv = pinctrl_dev_get_drvdata(pctldev); - pins = priv->pin_groups[group].pins; - - for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++) - exynos5440_pinconf_set(pctldev, pins[cnt], configs, - num_configs); - - return 0; -} - -/* get the pin config settings for a specified pin group */ -static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long *config) -{ - struct exynos5440_pinctrl_priv_data *priv; - const unsigned int *pins; - - priv = pinctrl_dev_get_drvdata(pctldev); - pins = priv->pin_groups[group].pins; - exynos5440_pinconf_get(pctldev, pins[0], config); - return 0; -} - -/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ -static const struct pinconf_ops exynos5440_pinconf_ops = { - .pin_config_get = exynos5440_pinconf_get, - .pin_config_set = exynos5440_pinconf_set, - .pin_config_group_get = exynos5440_pinconf_group_get, - .pin_config_group_set = exynos5440_pinconf_group_set, -}; - -/* gpiolib gpio_set callback function */ -static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value) -{ - struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); - void __iomem *base = priv->reg_base; - u32 data; - - data = readl(base + GPIO_VAL); - data &= ~(1 << offset); - if (value) - data |= 1 << offset; - writel(data, base + GPIO_VAL); -} - -/* gpiolib gpio_get callback function */ -static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset) -{ - struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); - void __iomem *base = priv->reg_base; - u32 data; - - data = readl(base + GPIO_IN); - data >>= offset; - data &= 1; - return data; -} - -/* gpiolib gpio_direction_input callback function */ -static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset) -{ - struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); - void __iomem *base = priv->reg_base; - u32 data; - - /* first disable the data output enable on this pin */ - data = readl(base + GPIO_OE); - data &= ~(1 << offset); - writel(data, base + GPIO_OE); - - /* now enable input on this pin */ - data = readl(base + GPIO_IE); - data |= 1 << offset; - writel(data, base + GPIO_IE); - return 0; -} - -/* gpiolib gpio_direction_output callback function */ -static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset, - int value) -{ - struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); - void __iomem *base = priv->reg_base; - u32 data; - - exynos5440_gpio_set(gc, offset, value); - - /* first disable the data input enable on this pin */ - data = readl(base + GPIO_IE); - data &= ~(1 << offset); - writel(data, base + GPIO_IE); - - /* now enable output on this pin */ - data = readl(base + GPIO_OE); - data |= 1 << offset; - writel(data, base + GPIO_OE); - return 0; -} - -/* gpiolib gpio_to_irq callback function */ -static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset) -{ - struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); - unsigned int virq; - - if (offset < 16 || offset > 23) - return -ENXIO; - - if (!priv->irq_domain) - return -ENXIO; - - virq = irq_create_mapping(priv->irq_domain, offset - 16); - return virq ? : -ENXIO; -} - -/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */ -static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev, - struct device_node *cfg_np, unsigned int **pin_list, - unsigned int *npins) -{ - struct device *dev = &pdev->dev; - struct property *prop; - - prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL); - if (!prop) - return -ENOENT; - - *npins = prop->length / sizeof(unsigned long); - if (!*npins) { - dev_err(dev, "invalid pin list in %s node", cfg_np->name); - return -EINVAL; - } - - *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); - if (!*pin_list) { - dev_err(dev, "failed to allocate memory for pin list\n"); - return -ENOMEM; - } - - return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins", - *pin_list, *npins); -} - -/* - * Parse the information about all the available pin groups and pin functions - * from device node of the pin-controller. - */ -static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, - struct exynos5440_pinctrl_priv_data *priv) -{ - struct device *dev = &pdev->dev; - struct device_node *dev_np = dev->of_node; - struct device_node *cfg_np; - struct exynos5440_pin_group *groups, *grp; - struct exynos5440_pmx_func *functions, *func; - unsigned *pin_list; - unsigned int npins, grp_cnt, func_idx = 0; - char *gname, *fname; - int ret; - - grp_cnt = of_get_child_count(dev_np); - if (!grp_cnt) - return -EINVAL; - - groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); - if (!groups) { - dev_err(dev, "failed allocate memory for ping group list\n"); - return -EINVAL; - } - grp = groups; - - functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); - if (!functions) { - dev_err(dev, "failed to allocate memory for function list\n"); - return -EINVAL; - } - func = functions; - - /* - * Iterate over all the child nodes of the pin controller node - * and create pin groups and pin function lists. - */ - for_each_child_of_node(dev_np, cfg_np) { - u32 function; - - ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np, - &pin_list, &npins); - if (ret) { - gname = NULL; - goto skip_to_pin_function; - } - - /* derive pin group name from the node name */ - gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, - GFP_KERNEL); - if (!gname) { - dev_err(dev, "failed to alloc memory for group name\n"); - return -ENOMEM; - } - snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, - GROUP_SUFFIX); - - grp->name = gname; - grp->pins = pin_list; - grp->num_pins = npins; - grp++; - -skip_to_pin_function: - ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function", - &function); - if (ret) - continue; - - /* derive function name from the node name */ - fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, - GFP_KERNEL); - if (!fname) { - dev_err(dev, "failed to alloc memory for func name\n"); - return -ENOMEM; - } - snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, - FUNCTION_SUFFIX); - - func->name = fname; - func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); - if (!func->groups) { - dev_err(dev, "failed to alloc memory for group list " - "in pin function"); - return -ENOMEM; - } - func->groups[0] = gname; - func->num_groups = gname ? 1 : 0; - func->function = function; - func++; - func_idx++; - } - - priv->pin_groups = groups; - priv->nr_groups = grp_cnt; - priv->pmx_functions = functions; - priv->nr_functions = func_idx; - return 0; -} - -/* register the pinctrl interface with the pinctrl subsystem */ -static int exynos5440_pinctrl_register(struct platform_device *pdev, - struct exynos5440_pinctrl_priv_data *priv) -{ - struct device *dev = &pdev->dev; - struct pinctrl_desc *ctrldesc; - struct pinctrl_dev *pctl_dev; - struct pinctrl_pin_desc *pindesc, *pdesc; - struct pinctrl_gpio_range grange; - char *pin_names; - int pin, ret; - - ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL); - if (!ctrldesc) { - dev_err(dev, "could not allocate memory for pinctrl desc\n"); - return -ENOMEM; - } - - ctrldesc->name = "exynos5440-pinctrl"; - ctrldesc->owner = THIS_MODULE; - ctrldesc->pctlops = &exynos5440_pctrl_ops; - ctrldesc->pmxops = &exynos5440_pinmux_ops; - ctrldesc->confops = &exynos5440_pinconf_ops; - - pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * - EXYNOS5440_MAX_PINS, GFP_KERNEL); - if (!pindesc) { - dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); - return -ENOMEM; - } - ctrldesc->pins = pindesc; - ctrldesc->npins = EXYNOS5440_MAX_PINS; - - /* dynamically populate the pin number and pin name for pindesc */ - for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) - pdesc->number = pin; - - /* - * allocate space for storing the dynamically generated names for all - * the pins which belong to this pin-controller. - */ - pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * - ctrldesc->npins, GFP_KERNEL); - if (!pin_names) { - dev_err(&pdev->dev, "mem alloc for pin names failed\n"); - return -ENOMEM; - } - - /* for each pin, set the name of the pin */ - for (pin = 0; pin < ctrldesc->npins; pin++) { - snprintf(pin_names, 6, "gpio%02d", pin); - pdesc = pindesc + pin; - pdesc->name = pin_names; - pin_names += PIN_NAME_LENGTH; - } - - ret = exynos5440_pinctrl_parse_dt(pdev, priv); - if (ret) - return ret; - - pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv); - if (!pctl_dev) { - dev_err(&pdev->dev, "could not register pinctrl driver\n"); - return -EINVAL; - } - - grange.name = "exynos5440-pctrl-gpio-range"; - grange.id = 0; - grange.base = 0; - grange.npins = EXYNOS5440_MAX_PINS; - grange.gc = priv->gc; - pinctrl_add_gpio_range(pctl_dev, &grange); - return 0; -} - -/* register the gpiolib interface with the gpiolib subsystem */ -static int exynos5440_gpiolib_register(struct platform_device *pdev, - struct exynos5440_pinctrl_priv_data *priv) -{ - struct gpio_chip *gc; - int ret; - - gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); - if (!gc) { - dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n"); - return -ENOMEM; - } - - priv->gc = gc; - gc->base = 0; - gc->ngpio = EXYNOS5440_MAX_PINS; - gc->dev = &pdev->dev; - gc->set = exynos5440_gpio_set; - gc->get = exynos5440_gpio_get; - gc->direction_input = exynos5440_gpio_direction_input; - gc->direction_output = exynos5440_gpio_direction_output; - gc->to_irq = exynos5440_gpio_to_irq; - gc->label = "gpiolib-exynos5440"; - gc->owner = THIS_MODULE; - ret = gpiochip_add(gc); - if (ret) { - dev_err(&pdev->dev, "failed to register gpio_chip %s, error " - "code: %d\n", gc->label, ret); - return ret; - } - - return 0; -} - -/* unregister the gpiolib interface with the gpiolib subsystem */ -static int exynos5440_gpiolib_unregister(struct platform_device *pdev, - struct exynos5440_pinctrl_priv_data *priv) -{ - int ret = gpiochip_remove(priv->gc); - if (ret) { - dev_err(&pdev->dev, "gpio chip remove failed\n"); - return ret; - } - return 0; -} - -static void exynos5440_gpio_irq_unmask(struct irq_data *irqd) -{ - struct exynos5440_pinctrl_priv_data *d; - unsigned long gpio_int; - - d = irq_data_get_irq_chip_data(irqd); - gpio_int = readl(d->reg_base + GPIO_INT); - gpio_int |= 1 << irqd->hwirq; - writel(gpio_int, d->reg_base + GPIO_INT); -} - -static void exynos5440_gpio_irq_mask(struct irq_data *irqd) -{ - struct exynos5440_pinctrl_priv_data *d; - unsigned long gpio_int; - - d = irq_data_get_irq_chip_data(irqd); - gpio_int = readl(d->reg_base + GPIO_INT); - gpio_int &= ~(1 << irqd->hwirq); - writel(gpio_int, d->reg_base + GPIO_INT); -} - -/* irq_chip for gpio interrupts */ -static struct irq_chip exynos5440_gpio_irq_chip = { - .name = "exynos5440_gpio_irq_chip", - .irq_unmask = exynos5440_gpio_irq_unmask, - .irq_mask = exynos5440_gpio_irq_mask, -}; - -/* interrupt handler for GPIO interrupts 0..7 */ -static irqreturn_t exynos5440_gpio_irq(int irq, void *data) -{ - struct exynos5440_gpio_intr_data *intd = data; - struct exynos5440_pinctrl_priv_data *d = intd->priv; - int virq; - - virq = irq_linear_revmap(d->irq_domain, intd->gpio_int); - if (!virq) - return IRQ_NONE; - generic_handle_irq(virq); - return IRQ_HANDLED; -} - -static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct exynos5440_pinctrl_priv_data *d = h->host_data; - - irq_set_chip_data(virq, d); - irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip, - handle_level_irq); - set_irq_flags(virq, IRQF_VALID); - return 0; -} - -/* irq domain callbacks for gpio interrupt controller */ -static const struct irq_domain_ops exynos5440_gpio_irqd_ops = { - .map = exynos5440_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -/* setup handling of gpio interrupts */ -static int exynos5440_gpio_irq_init(struct platform_device *pdev, - struct exynos5440_pinctrl_priv_data *priv) -{ - struct device *dev = &pdev->dev; - struct exynos5440_gpio_intr_data *intd; - int i, irq, ret; - - intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT, - GFP_KERNEL); - if (!intd) { - dev_err(dev, "failed to allocate memory for gpio intr data\n"); - return -ENOMEM; - } - - for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) { - irq = irq_of_parse_and_map(dev->of_node, i); - if (irq <= 0) { - dev_err(dev, "irq parsing failed\n"); - return -EINVAL; - } - - intd->gpio_int = i; - intd->priv = priv; - ret = devm_request_irq(dev, irq, exynos5440_gpio_irq, - 0, dev_name(dev), intd++); - if (ret) { - dev_err(dev, "irq request failed\n"); - return -ENXIO; - } - } - - priv->irq_domain = irq_domain_add_linear(dev->of_node, - EXYNOS5440_MAX_GPIO_INT, - &exynos5440_gpio_irqd_ops, priv); - if (!priv->irq_domain) { - dev_err(dev, "failed to create irq domain\n"); - return -ENXIO; - } - - return 0; -} - -static int exynos5440_pinctrl_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct exynos5440_pinctrl_priv_data *priv; - struct resource *res; - int ret; - - if (!dev->of_node) { - dev_err(dev, "device tree node not found\n"); - return -ENODEV; - } - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) { - dev_err(dev, "could not allocate memory for private data\n"); - return -ENOMEM; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->reg_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(priv->reg_base)) - return PTR_ERR(priv->reg_base); - - ret = exynos5440_gpiolib_register(pdev, priv); - if (ret) - return ret; - - ret = exynos5440_pinctrl_register(pdev, priv); - if (ret) { - exynos5440_gpiolib_unregister(pdev, priv); - return ret; - } - - ret = exynos5440_gpio_irq_init(pdev, priv); - if (ret) { - dev_err(dev, "failed to setup gpio interrupts\n"); - return ret; - } - - platform_set_drvdata(pdev, priv); - dev_info(dev, "EXYNOS5440 pinctrl driver registered\n"); - return 0; -} - -static const struct of_device_id exynos5440_pinctrl_dt_match[] = { - { .compatible = "samsung,exynos5440-pinctrl" }, - {}, -}; -MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match); - -static struct platform_driver exynos5440_pinctrl_driver = { - .probe = exynos5440_pinctrl_probe, - .driver = { - .name = "exynos5440-pinctrl", - .owner = THIS_MODULE, - .of_match_table = exynos5440_pinctrl_dt_match, - }, -}; - -static int __init exynos5440_pinctrl_drv_register(void) -{ - return platform_driver_register(&exynos5440_pinctrl_driver); -} -postcore_initcall(exynos5440_pinctrl_drv_register); - -static void __exit exynos5440_pinctrl_drv_unregister(void) -{ - platform_driver_unregister(&exynos5440_pinctrl_driver); -} -module_exit(exynos5440_pinctrl_drv_unregister); - -MODULE_AUTHOR("Thomas Abraham "); -MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c b/drivers/pinctrl/pinctrl-s3c24xx.c deleted file mode 100644 index ad3eaad17001..000000000000 --- a/drivers/pinctrl/pinctrl-s3c24xx.c +++ /dev/null @@ -1,651 +0,0 @@ -/* - * S3C24XX specific support for Samsung pinctrl/gpiolib driver. - * - * Copyright (c) 2013 Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This file contains the SamsungS3C24XX specific information required by the - * Samsung pinctrl/gpiolib driver. It also includes the implementation of - * external gpio and wakeup interrupt support. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-samsung.h" - -#define NUM_EINT 24 -#define NUM_EINT_IRQ 6 -#define EINT_MAX_PER_GROUP 8 - -#define EINTPEND_REG 0xa8 -#define EINTMASK_REG 0xa4 - -#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP)) -#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88) -#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4) - -#define EINT_LEVEL_LOW 0 -#define EINT_LEVEL_HIGH 1 -#define EINT_EDGE_FALLING 2 -#define EINT_EDGE_RISING 4 -#define EINT_EDGE_BOTH 6 -#define EINT_MASK 0xf - -static struct samsung_pin_bank_type bank_type_1bit = { - .fld_width = { 1, 1, }, - .reg_offset = { 0x00, 0x04, }, -}; - -static struct samsung_pin_bank_type bank_type_2bit = { - .fld_width = { 2, 1, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, }, -}; - -#define PIN_BANK_A(pins, reg, id) \ - { \ - .type = &bank_type_1bit, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define PIN_BANK_2BIT(pins, reg, id) \ - { \ - .type = &bank_type_2bit, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\ - { \ - .type = &bank_type_2bit, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_func = 2, \ - .eint_mask = emask, \ - .eint_offset = eoffs, \ - .name = id \ - } - -/** - * struct s3c24xx_eint_data: EINT common data - * @drvdata: pin controller driver data - * @domains: IRQ domains of particular EINT interrupts - * @parents: mapped parent irqs in the main interrupt controller - */ -struct s3c24xx_eint_data { - struct samsung_pinctrl_drv_data *drvdata; - struct irq_domain *domains[NUM_EINT]; - int parents[NUM_EINT_IRQ]; -}; - -/** - * struct s3c24xx_eint_domain_data: per irq-domain data - * @bank: pin bank related to the domain - * @eint_data: common data - * eint0_3_parent_only: live eints 0-3 only in the main intc - */ -struct s3c24xx_eint_domain_data { - struct samsung_pin_bank *bank; - struct s3c24xx_eint_data *eint_data; - bool eint0_3_parent_only; -}; - -static int s3c24xx_eint_get_trigger(unsigned int type) -{ - switch (type) { - case IRQ_TYPE_EDGE_RISING: - return EINT_EDGE_RISING; - break; - case IRQ_TYPE_EDGE_FALLING: - return EINT_EDGE_FALLING; - break; - case IRQ_TYPE_EDGE_BOTH: - return EINT_EDGE_BOTH; - break; - case IRQ_TYPE_LEVEL_HIGH: - return EINT_LEVEL_HIGH; - break; - case IRQ_TYPE_LEVEL_LOW: - return EINT_LEVEL_LOW; - break; - default: - return -EINVAL; - } -} - -static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type) -{ - /* Edge- and level-triggered interrupts need different handlers */ - if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(irq, handle_edge_irq); - else - __irq_set_handler_locked(irq, handle_level_irq); -} - -static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, - struct samsung_pin_bank *bank, int pin) -{ - struct samsung_pin_bank_type *bank_type = bank->type; - unsigned long flags; - void __iomem *reg; - u8 shift; - u32 mask; - u32 val; - - /* Make sure that pin is configured as interrupt */ - reg = d->virt_base + bank->pctl_offset; - shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; - mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; - - spin_lock_irqsave(&bank->slock, flags); - - val = readl(reg); - val &= ~(mask << shift); - val |= bank->eint_func << shift; - writel(val, reg); - - spin_unlock_irqrestore(&bank->slock, flags); -} - -static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - int index = bank->eint_offset + data->hwirq; - void __iomem *reg; - int trigger; - u8 shift; - u32 val; - - trigger = s3c24xx_eint_get_trigger(type); - if (trigger < 0) { - dev_err(d->dev, "unsupported external interrupt type\n"); - return -EINVAL; - } - - s3c24xx_eint_set_handler(data->irq, type); - - /* Set up interrupt trigger */ - reg = d->virt_base + EINT_REG(index); - shift = EINT_OFFS(index); - - val = readl(reg); - val &= ~(EINT_MASK << shift); - val |= trigger << shift; - writel(val, reg); - - s3c24xx_eint_set_function(d, bank, data->hwirq); - - return 0; -} - -/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */ - -static void s3c2410_eint0_3_ack(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; - struct s3c24xx_eint_data *eint_data = ddata->eint_data; - int parent_irq = eint_data->parents[data->hwirq]; - struct irq_chip *parent_chip = irq_get_chip(parent_irq); - - parent_chip->irq_ack(irq_get_irq_data(parent_irq)); -} - -static void s3c2410_eint0_3_mask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; - struct s3c24xx_eint_data *eint_data = ddata->eint_data; - int parent_irq = eint_data->parents[data->hwirq]; - struct irq_chip *parent_chip = irq_get_chip(parent_irq); - - parent_chip->irq_mask(irq_get_irq_data(parent_irq)); -} - -static void s3c2410_eint0_3_unmask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; - struct s3c24xx_eint_data *eint_data = ddata->eint_data; - int parent_irq = eint_data->parents[data->hwirq]; - struct irq_chip *parent_chip = irq_get_chip(parent_irq); - - parent_chip->irq_unmask(irq_get_irq_data(parent_irq)); -} - -static struct irq_chip s3c2410_eint0_3_chip = { - .name = "s3c2410-eint0_3", - .irq_ack = s3c2410_eint0_3_ack, - .irq_mask = s3c2410_eint0_3_mask, - .irq_unmask = s3c2410_eint0_3_unmask, - .irq_set_type = s3c24xx_eint_type, -}; - -static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc) -{ - struct irq_data *data = irq_desc_get_irq_data(desc); - struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); - unsigned int virq; - - /* the first 4 eints have a simple 1 to 1 mapping */ - virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); - /* Something must be really wrong if an unmapped EINT is unmasked */ - BUG_ON(!virq); - - generic_handle_irq(virq); -} - -/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */ - -static void s3c2412_eint0_3_ack(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - - unsigned long bitval = 1UL << data->hwirq; - writel(bitval, d->virt_base + EINTPEND_REG); -} - -static void s3c2412_eint0_3_mask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long mask; - - mask = readl(d->virt_base + EINTMASK_REG); - mask |= (1UL << data->hwirq); - writel(mask, d->virt_base + EINTMASK_REG); -} - -static void s3c2412_eint0_3_unmask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long mask; - - mask = readl(d->virt_base + EINTMASK_REG); - mask &= ~(1UL << data->hwirq); - writel(mask, d->virt_base + EINTMASK_REG); -} - -static struct irq_chip s3c2412_eint0_3_chip = { - .name = "s3c2412-eint0_3", - .irq_ack = s3c2412_eint0_3_ack, - .irq_mask = s3c2412_eint0_3_mask, - .irq_unmask = s3c2412_eint0_3_unmask, - .irq_set_type = s3c24xx_eint_type, -}; - -static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc) -{ - struct irq_chip *chip = irq_get_chip(irq); - struct irq_data *data = irq_desc_get_irq_data(desc); - struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); - unsigned int virq; - - chained_irq_enter(chip, desc); - - /* the first 4 eints have a simple 1 to 1 mapping */ - virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); - /* Something must be really wrong if an unmapped EINT is unmasked */ - BUG_ON(!virq); - - generic_handle_irq(virq); - - chained_irq_exit(chip, desc); -} - -/* Handling of all other eints */ - -static void s3c24xx_eint_ack(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned char index = bank->eint_offset + data->hwirq; - - writel(1UL << index, d->virt_base + EINTPEND_REG); -} - -static void s3c24xx_eint_mask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned char index = bank->eint_offset + data->hwirq; - unsigned long mask; - - mask = readl(d->virt_base + EINTMASK_REG); - mask |= (1UL << index); - writel(mask, d->virt_base + EINTMASK_REG); -} - -static void s3c24xx_eint_unmask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned char index = bank->eint_offset + data->hwirq; - unsigned long mask; - - mask = readl(d->virt_base + EINTMASK_REG); - mask &= ~(1UL << index); - writel(mask, d->virt_base + EINTMASK_REG); -} - -static struct irq_chip s3c24xx_eint_chip = { - .name = "s3c-eint", - .irq_ack = s3c24xx_eint_ack, - .irq_mask = s3c24xx_eint_mask, - .irq_unmask = s3c24xx_eint_unmask, - .irq_set_type = s3c24xx_eint_type, -}; - -static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, - u32 offset, u32 range) -{ - struct irq_chip *chip = irq_get_chip(irq); - struct s3c24xx_eint_data *data = irq_get_handler_data(irq); - struct samsung_pinctrl_drv_data *d = data->drvdata; - unsigned int pend, mask; - - chained_irq_enter(chip, desc); - - pend = readl(d->virt_base + EINTPEND_REG); - mask = readl(d->virt_base + EINTMASK_REG); - - pend &= ~mask; - pend &= range; - - while (pend) { - unsigned int virq; - - irq = __ffs(pend); - pend &= ~(1 << irq); - virq = irq_linear_revmap(data->domains[irq], irq - offset); - /* Something is really wrong if an unmapped EINT is unmasked */ - BUG_ON(!virq); - - generic_handle_irq(virq); - } - - chained_irq_exit(chip, desc); -} - -static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc) -{ - s3c24xx_demux_eint(irq, desc, 0, 0xf0); -} - -static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc) -{ - s3c24xx_demux_eint(irq, desc, 8, 0xffff00); -} - -static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = { - s3c2410_demux_eint0_3, - s3c2410_demux_eint0_3, - s3c2410_demux_eint0_3, - s3c2410_demux_eint0_3, - s3c24xx_demux_eint4_7, - s3c24xx_demux_eint8_23, -}; - -static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = { - s3c2412_demux_eint0_3, - s3c2412_demux_eint0_3, - s3c2412_demux_eint0_3, - s3c2412_demux_eint0_3, - s3c24xx_demux_eint4_7, - s3c24xx_demux_eint8_23, -}; - -static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct s3c24xx_eint_domain_data *ddata = h->host_data; - struct samsung_pin_bank *bank = ddata->bank; - - if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) - return -EINVAL; - - if (hw <= 3) { - if (ddata->eint0_3_parent_only) - irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip, - handle_edge_irq); - else - irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip, - handle_edge_irq); - } else { - irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, - handle_edge_irq); - } - irq_set_chip_data(virq, bank); - set_irq_flags(virq, IRQF_VALID); - return 0; -} - -static const struct irq_domain_ops s3c24xx_gpf_irq_ops = { - .map = s3c24xx_gpf_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct s3c24xx_eint_domain_data *ddata = h->host_data; - struct samsung_pin_bank *bank = ddata->bank; - - if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) - return -EINVAL; - - irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq); - irq_set_chip_data(virq, bank); - set_irq_flags(virq, IRQF_VALID); - return 0; -} - -static const struct irq_domain_ops s3c24xx_gpg_irq_ops = { - .map = s3c24xx_gpg_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static const struct of_device_id s3c24xx_eint_irq_ids[] = { - { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 }, - { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 }, - { } -}; - -static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d) -{ - struct device *dev = d->dev; - const struct of_device_id *match; - struct device_node *eint_np = NULL; - struct device_node *np; - struct samsung_pin_bank *bank; - struct s3c24xx_eint_data *eint_data; - const struct irq_domain_ops *ops; - unsigned int i; - bool eint0_3_parent_only; - irq_flow_handler_t *handlers; - - for_each_child_of_node(dev->of_node, np) { - match = of_match_node(s3c24xx_eint_irq_ids, np); - if (match) { - eint_np = np; - eint0_3_parent_only = (bool)match->data; - break; - } - } - if (!eint_np) - return -ENODEV; - - eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL); - if (!eint_data) - return -ENOMEM; - - eint_data->drvdata = d; - - handlers = eint0_3_parent_only ? s3c2410_eint_handlers - : s3c2412_eint_handlers; - for (i = 0; i < NUM_EINT_IRQ; ++i) { - unsigned int irq; - - irq = irq_of_parse_and_map(eint_np, i); - if (!irq) { - dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); - return -ENXIO; - } - - eint_data->parents[i] = irq; - irq_set_chained_handler(irq, handlers[i]); - irq_set_handler_data(irq, eint_data); - } - - bank = d->ctrl->pin_banks; - for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { - struct s3c24xx_eint_domain_data *ddata; - unsigned int mask; - unsigned int irq; - unsigned int pin; - - if (bank->eint_type != EINT_TYPE_WKUP) - continue; - - ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); - if (!ddata) - return -ENOMEM; - - ddata->bank = bank; - ddata->eint_data = eint_data; - ddata->eint0_3_parent_only = eint0_3_parent_only; - - ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops - : &s3c24xx_gpg_irq_ops; - - bank->irq_domain = irq_domain_add_linear(bank->of_node, - bank->nr_pins, ops, ddata); - if (!bank->irq_domain) { - dev_err(dev, "wkup irq domain add failed\n"); - return -ENXIO; - } - - irq = bank->eint_offset; - mask = bank->eint_mask; - for (pin = 0; mask; ++pin, mask >>= 1) { - if (irq >= NUM_EINT) - break; - if (!(mask & 1)) - continue; - eint_data->domains[irq] = bank->irq_domain; - ++irq; - } - } - - return 0; -} - -static struct samsung_pin_bank s3c2412_pin_banks[] = { - PIN_BANK_A(23, 0x000, "gpa"), - PIN_BANK_2BIT(11, 0x010, "gpb"), - PIN_BANK_2BIT(16, 0x020, "gpc"), - PIN_BANK_2BIT(16, 0x030, "gpd"), - PIN_BANK_2BIT(16, 0x040, "gpe"), - PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), - PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), - PIN_BANK_2BIT(11, 0x070, "gph"), - PIN_BANK_2BIT(13, 0x080, "gpj"), -}; - -struct samsung_pin_ctrl s3c2412_pin_ctrl[] = { - { - .pin_banks = s3c2412_pin_banks, - .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), - .eint_wkup_init = s3c24xx_eint_init, - .label = "S3C2412-GPIO", - }, -}; - -static struct samsung_pin_bank s3c2416_pin_banks[] = { - PIN_BANK_A(27, 0x000, "gpa"), - PIN_BANK_2BIT(11, 0x010, "gpb"), - PIN_BANK_2BIT(16, 0x020, "gpc"), - PIN_BANK_2BIT(16, 0x030, "gpd"), - PIN_BANK_2BIT(16, 0x040, "gpe"), - PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), - PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00), - PIN_BANK_2BIT(15, 0x070, "gph"), - PIN_BANK_2BIT(16, 0x0e0, "gpk"), - PIN_BANK_2BIT(14, 0x0f0, "gpl"), - PIN_BANK_2BIT(2, 0x100, "gpm"), -}; - -struct samsung_pin_ctrl s3c2416_pin_ctrl[] = { - { - .pin_banks = s3c2416_pin_banks, - .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), - .eint_wkup_init = s3c24xx_eint_init, - .label = "S3C2416-GPIO", - }, -}; - -static struct samsung_pin_bank s3c2440_pin_banks[] = { - PIN_BANK_A(25, 0x000, "gpa"), - PIN_BANK_2BIT(11, 0x010, "gpb"), - PIN_BANK_2BIT(16, 0x020, "gpc"), - PIN_BANK_2BIT(16, 0x030, "gpd"), - PIN_BANK_2BIT(16, 0x040, "gpe"), - PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), - PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), - PIN_BANK_2BIT(11, 0x070, "gph"), - PIN_BANK_2BIT(13, 0x0d0, "gpj"), -}; - -struct samsung_pin_ctrl s3c2440_pin_ctrl[] = { - { - .pin_banks = s3c2440_pin_banks, - .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), - .eint_wkup_init = s3c24xx_eint_init, - .label = "S3C2440-GPIO", - }, -}; - -static struct samsung_pin_bank s3c2450_pin_banks[] = { - PIN_BANK_A(28, 0x000, "gpa"), - PIN_BANK_2BIT(11, 0x010, "gpb"), - PIN_BANK_2BIT(16, 0x020, "gpc"), - PIN_BANK_2BIT(16, 0x030, "gpd"), - PIN_BANK_2BIT(16, 0x040, "gpe"), - PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), - PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), - PIN_BANK_2BIT(15, 0x070, "gph"), - PIN_BANK_2BIT(16, 0x0d0, "gpj"), - PIN_BANK_2BIT(16, 0x0e0, "gpk"), - PIN_BANK_2BIT(15, 0x0f0, "gpl"), - PIN_BANK_2BIT(2, 0x100, "gpm"), -}; - -struct samsung_pin_ctrl s3c2450_pin_ctrl[] = { - { - .pin_banks = s3c2450_pin_banks, - .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), - .eint_wkup_init = s3c24xx_eint_init, - .label = "S3C2450-GPIO", - }, -}; diff --git a/drivers/pinctrl/pinctrl-s3c64xx.c b/drivers/pinctrl/pinctrl-s3c64xx.c deleted file mode 100644 index 89143c903000..000000000000 --- a/drivers/pinctrl/pinctrl-s3c64xx.c +++ /dev/null @@ -1,816 +0,0 @@ -/* - * S3C64xx specific support for pinctrl-samsung driver. - * - * Copyright (c) 2013 Tomasz Figa - * - * Based on pinctrl-exynos.c, please see the file for original copyrights. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This file contains the Samsung S3C64xx specific information required by the - * the Samsung pinctrl/gpiolib driver. It also includes the implementation of - * external gpio and wakeup interrupt support. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-samsung.h" - -#define NUM_EINT0 28 -#define NUM_EINT0_IRQ 4 -#define EINT_MAX_PER_REG 16 -#define EINT_MAX_PER_GROUP 16 - -/* External GPIO and wakeup interrupt related definitions */ -#define SVC_GROUP_SHIFT 4 -#define SVC_GROUP_MASK 0xf -#define SVC_NUM_MASK 0xf -#define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \ - SVC_GROUP_MASK) - -#define EINT12CON_REG 0x200 -#define EINT12MASK_REG 0x240 -#define EINT12PEND_REG 0x260 - -#define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP)) -#define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP) -#define EINT_REG(g) (4 * ((g) / 2)) - -#define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i))) -#define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i))) -#define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i))) - -#define SERVICE_REG 0x284 -#define SERVICEPEND_REG 0x288 - -#define EINT0CON0_REG 0x900 -#define EINT0MASK_REG 0x920 -#define EINT0PEND_REG 0x924 - -/* S3C64xx specific external interrupt trigger types */ -#define EINT_LEVEL_LOW 0 -#define EINT_LEVEL_HIGH 1 -#define EINT_EDGE_FALLING 2 -#define EINT_EDGE_RISING 4 -#define EINT_EDGE_BOTH 6 -#define EINT_CON_MASK 0xF -#define EINT_CON_LEN 4 - -static struct samsung_pin_bank_type bank_type_4bit_off = { - .fld_width = { 4, 1, 2, 0, 2, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, -}; - -static struct samsung_pin_bank_type bank_type_4bit_alive = { - .fld_width = { 4, 1, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, }, -}; - -static struct samsung_pin_bank_type bank_type_4bit2_off = { - .fld_width = { 4, 1, 2, 0, 2, 2, }, - .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, }, -}; - -static struct samsung_pin_bank_type bank_type_4bit2_alive = { - .fld_width = { 4, 1, 2, }, - .reg_offset = { 0x00, 0x08, 0x0c, }, -}; - -static struct samsung_pin_bank_type bank_type_2bit_off = { - .fld_width = { 2, 1, 2, 0, 2, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, -}; - -static struct samsung_pin_bank_type bank_type_2bit_alive = { - .fld_width = { 2, 1, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, }, -}; - -#define PIN_BANK_4BIT(pins, reg, id) \ - { \ - .type = &bank_type_4bit_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \ - { \ - .type = &bank_type_4bit_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_GPIO, \ - .eint_func = 7, \ - .eint_mask = (1 << (pins)) - 1, \ - .eint_offset = eoffs, \ - .name = id \ - } - -#define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \ - { \ - .type = &bank_type_4bit_alive,\ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_func = 3, \ - .eint_mask = emask, \ - .eint_offset = eoffs, \ - .name = id \ - } - -#define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \ - { \ - .type = &bank_type_4bit2_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_GPIO, \ - .eint_func = 7, \ - .eint_mask = (1 << (pins)) - 1, \ - .eint_offset = eoffs, \ - .name = id \ - } - -#define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \ - { \ - .type = &bank_type_4bit2_alive,\ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_func = 3, \ - .eint_mask = emask, \ - .eint_offset = eoffs, \ - .name = id \ - } - -#define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \ - { \ - .type = &bank_type_4bit2_alive,\ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define PIN_BANK_2BIT(pins, reg, id) \ - { \ - .type = &bank_type_2bit_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \ - { \ - .type = &bank_type_2bit_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_GPIO, \ - .eint_func = 3, \ - .eint_mask = emask, \ - .eint_offset = eoffs, \ - .name = id \ - } - -#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \ - { \ - .type = &bank_type_2bit_alive,\ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_func = 2, \ - .eint_mask = (1 << (pins)) - 1, \ - .eint_offset = eoffs, \ - .name = id \ - } - -/** - * struct s3c64xx_eint0_data: EINT0 common data - * @drvdata: pin controller driver data - * @domains: IRQ domains of particular EINT0 interrupts - * @pins: pin offsets inside of banks of particular EINT0 interrupts - */ -struct s3c64xx_eint0_data { - struct samsung_pinctrl_drv_data *drvdata; - struct irq_domain *domains[NUM_EINT0]; - u8 pins[NUM_EINT0]; -}; - -/** - * struct s3c64xx_eint0_domain_data: EINT0 per-domain data - * @bank: pin bank related to the domain - * @eints: EINT0 interrupts related to the domain - */ -struct s3c64xx_eint0_domain_data { - struct samsung_pin_bank *bank; - u8 eints[]; -}; - -/** - * struct s3c64xx_eint_gpio_data: GPIO EINT data - * @drvdata: pin controller driver data - * @domains: array of domains related to EINT interrupt groups - */ -struct s3c64xx_eint_gpio_data { - struct samsung_pinctrl_drv_data *drvdata; - struct irq_domain *domains[]; -}; - -/* - * Common functions for S3C64xx EINT configuration - */ - -static int s3c64xx_irq_get_trigger(unsigned int type) -{ - int trigger; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - trigger = EINT_EDGE_RISING; - break; - case IRQ_TYPE_EDGE_FALLING: - trigger = EINT_EDGE_FALLING; - break; - case IRQ_TYPE_EDGE_BOTH: - trigger = EINT_EDGE_BOTH; - break; - case IRQ_TYPE_LEVEL_HIGH: - trigger = EINT_LEVEL_HIGH; - break; - case IRQ_TYPE_LEVEL_LOW: - trigger = EINT_LEVEL_LOW; - break; - default: - return -EINVAL; - } - - return trigger; -} - -static void s3c64xx_irq_set_handler(unsigned int irq, unsigned int type) -{ - /* Edge- and level-triggered interrupts need different handlers */ - if (type & IRQ_TYPE_EDGE_BOTH) - __irq_set_handler_locked(irq, handle_edge_irq); - else - __irq_set_handler_locked(irq, handle_level_irq); -} - -static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, - struct samsung_pin_bank *bank, int pin) -{ - struct samsung_pin_bank_type *bank_type = bank->type; - unsigned long flags; - void __iomem *reg; - u8 shift; - u32 mask; - u32 val; - - /* Make sure that pin is configured as interrupt */ - reg = d->virt_base + bank->pctl_offset; - shift = pin; - if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) { - /* 4-bit bank type with 2 con regs */ - reg += 4; - shift -= 8; - } - - shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC]; - mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; - - spin_lock_irqsave(&bank->slock, flags); - - val = readl(reg); - val &= ~(mask << shift); - val |= bank->eint_func << shift; - writel(val, reg); - - spin_unlock_irqrestore(&bank->slock, flags); -} - -/* - * Functions for EINT GPIO configuration (EINT groups 1-9) - */ - -static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; - void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset); - u32 val; - - val = readl(reg); - if (mask) - val |= 1 << index; - else - val &= ~(1 << index); - writel(val, reg); -} - -static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd) -{ - s3c64xx_gpio_irq_set_mask(irqd, false); -} - -static void s3c64xx_gpio_irq_mask(struct irq_data *irqd) -{ - s3c64xx_gpio_irq_set_mask(irqd, true); -} - -static void s3c64xx_gpio_irq_ack(struct irq_data *irqd) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; - void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset); - - writel(1 << index, reg); -} - -static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - void __iomem *reg; - int trigger; - u8 shift; - u32 val; - - trigger = s3c64xx_irq_get_trigger(type); - if (trigger < 0) { - pr_err("unsupported external interrupt type\n"); - return -EINVAL; - } - - s3c64xx_irq_set_handler(irqd->irq, type); - - /* Set up interrupt trigger */ - reg = d->virt_base + EINTCON_REG(bank->eint_offset); - shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq; - shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */ - - val = readl(reg); - val &= ~(EINT_CON_MASK << shift); - val |= trigger << shift; - writel(val, reg); - - s3c64xx_irq_set_function(d, bank, irqd->hwirq); - - return 0; -} - -/* - * irq_chip for gpio interrupts. - */ -static struct irq_chip s3c64xx_gpio_irq_chip = { - .name = "GPIO", - .irq_unmask = s3c64xx_gpio_irq_unmask, - .irq_mask = s3c64xx_gpio_irq_mask, - .irq_ack = s3c64xx_gpio_irq_ack, - .irq_set_type = s3c64xx_gpio_irq_set_type, -}; - -static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct samsung_pin_bank *bank = h->host_data; - - if (!(bank->eint_mask & (1 << hw))) - return -EINVAL; - - irq_set_chip_and_handler(virq, - &s3c64xx_gpio_irq_chip, handle_level_irq); - irq_set_chip_data(virq, bank); - set_irq_flags(virq, IRQF_VALID); - - return 0; -} - -/* - * irq domain callbacks for external gpio interrupt controller. - */ -static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = { - .map = s3c64xx_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static void s3c64xx_eint_gpio_irq(unsigned int irq, struct irq_desc *desc) -{ - struct irq_chip *chip = irq_get_chip(irq); - struct s3c64xx_eint_gpio_data *data = irq_get_handler_data(irq); - struct samsung_pinctrl_drv_data *drvdata = data->drvdata; - - chained_irq_enter(chip, desc); - - do { - unsigned int svc; - unsigned int group; - unsigned int pin; - unsigned int virq; - - svc = readl(drvdata->virt_base + SERVICE_REG); - group = SVC_GROUP(svc); - pin = svc & SVC_NUM_MASK; - - if (!group) - break; - - /* Group 1 is used for two pin banks */ - if (group == 1) { - if (pin < 8) - group = 0; - else - pin -= 8; - } - - virq = irq_linear_revmap(data->domains[group], pin); - /* - * Something must be really wrong if an unmapped EINT - * was unmasked... - */ - BUG_ON(!virq); - - generic_handle_irq(virq); - } while (1); - - chained_irq_exit(chip, desc); -} - -/** - * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts. - * @d: driver data of samsung pinctrl driver. - */ -static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d) -{ - struct s3c64xx_eint_gpio_data *data; - struct samsung_pin_bank *bank; - struct device *dev = d->dev; - unsigned int nr_domains; - unsigned int i; - - if (!d->irq) { - dev_err(dev, "irq number not available\n"); - return -EINVAL; - } - - nr_domains = 0; - bank = d->ctrl->pin_banks; - for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { - unsigned int nr_eints; - unsigned int mask; - - if (bank->eint_type != EINT_TYPE_GPIO) - continue; - - mask = bank->eint_mask; - nr_eints = fls(mask); - - bank->irq_domain = irq_domain_add_linear(bank->of_node, - nr_eints, &s3c64xx_gpio_irqd_ops, bank); - if (!bank->irq_domain) { - dev_err(dev, "gpio irq domain add failed\n"); - return -ENXIO; - } - - ++nr_domains; - } - - data = devm_kzalloc(dev, sizeof(*data) - + nr_domains * sizeof(*data->domains), GFP_KERNEL); - if (!data) { - dev_err(dev, "failed to allocate handler data\n"); - return -ENOMEM; - } - data->drvdata = d; - - bank = d->ctrl->pin_banks; - nr_domains = 0; - for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { - if (bank->eint_type != EINT_TYPE_GPIO) - continue; - - data->domains[nr_domains++] = bank->irq_domain; - } - - irq_set_chained_handler(d->irq, s3c64xx_eint_gpio_irq); - irq_set_handler_data(d->irq, data); - - return 0; -} - -/* - * Functions for configuration of EINT0 wake-up interrupts - */ - -static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask) -{ - struct s3c64xx_eint0_domain_data *ddata = - irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; - u32 val; - - val = readl(d->virt_base + EINT0MASK_REG); - if (mask) - val |= 1 << ddata->eints[irqd->hwirq]; - else - val &= ~(1 << ddata->eints[irqd->hwirq]); - writel(val, d->virt_base + EINT0MASK_REG); -} - -static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd) -{ - s3c64xx_eint0_irq_set_mask(irqd, false); -} - -static void s3c64xx_eint0_irq_mask(struct irq_data *irqd) -{ - s3c64xx_eint0_irq_set_mask(irqd, true); -} - -static void s3c64xx_eint0_irq_ack(struct irq_data *irqd) -{ - struct s3c64xx_eint0_domain_data *ddata = - irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; - - writel(1 << ddata->eints[irqd->hwirq], - d->virt_base + EINT0PEND_REG); -} - -static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type) -{ - struct s3c64xx_eint0_domain_data *ddata = - irq_data_get_irq_chip_data(irqd); - struct samsung_pin_bank *bank = ddata->bank; - struct samsung_pinctrl_drv_data *d = bank->drvdata; - void __iomem *reg; - int trigger; - u8 shift; - u32 val; - - trigger = s3c64xx_irq_get_trigger(type); - if (trigger < 0) { - pr_err("unsupported external interrupt type\n"); - return -EINVAL; - } - - s3c64xx_irq_set_handler(irqd->irq, type); - - /* Set up interrupt trigger */ - reg = d->virt_base + EINT0CON0_REG; - shift = ddata->eints[irqd->hwirq]; - if (shift >= EINT_MAX_PER_REG) { - reg += 4; - shift -= EINT_MAX_PER_REG; - } - shift = EINT_CON_LEN * (shift / 2); - - val = readl(reg); - val &= ~(EINT_CON_MASK << shift); - val |= trigger << shift; - writel(val, reg); - - s3c64xx_irq_set_function(d, bank, irqd->hwirq); - - return 0; -} - -/* - * irq_chip for wakeup interrupts - */ -static struct irq_chip s3c64xx_eint0_irq_chip = { - .name = "EINT0", - .irq_unmask = s3c64xx_eint0_irq_unmask, - .irq_mask = s3c64xx_eint0_irq_mask, - .irq_ack = s3c64xx_eint0_irq_ack, - .irq_set_type = s3c64xx_eint0_irq_set_type, -}; - -static inline void s3c64xx_irq_demux_eint(unsigned int irq, - struct irq_desc *desc, u32 range) -{ - struct irq_chip *chip = irq_get_chip(irq); - struct s3c64xx_eint0_data *data = irq_get_handler_data(irq); - struct samsung_pinctrl_drv_data *drvdata = data->drvdata; - unsigned int pend, mask; - - chained_irq_enter(chip, desc); - - pend = readl(drvdata->virt_base + EINT0PEND_REG); - mask = readl(drvdata->virt_base + EINT0MASK_REG); - - pend = pend & range & ~mask; - pend &= range; - - while (pend) { - unsigned int virq; - - irq = fls(pend) - 1; - pend &= ~(1 << irq); - - virq = irq_linear_revmap(data->domains[irq], data->pins[irq]); - /* - * Something must be really wrong if an unmapped EINT - * was unmasked... - */ - BUG_ON(!virq); - - generic_handle_irq(virq); - } - - chained_irq_exit(chip, desc); -} - -static void s3c64xx_demux_eint0_3(unsigned int irq, struct irq_desc *desc) -{ - s3c64xx_irq_demux_eint(irq, desc, 0xf); -} - -static void s3c64xx_demux_eint4_11(unsigned int irq, struct irq_desc *desc) -{ - s3c64xx_irq_demux_eint(irq, desc, 0xff0); -} - -static void s3c64xx_demux_eint12_19(unsigned int irq, struct irq_desc *desc) -{ - s3c64xx_irq_demux_eint(irq, desc, 0xff000); -} - -static void s3c64xx_demux_eint20_27(unsigned int irq, struct irq_desc *desc) -{ - s3c64xx_irq_demux_eint(irq, desc, 0xff00000); -} - -static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = { - s3c64xx_demux_eint0_3, - s3c64xx_demux_eint4_11, - s3c64xx_demux_eint12_19, - s3c64xx_demux_eint20_27, -}; - -static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct s3c64xx_eint0_domain_data *ddata = h->host_data; - struct samsung_pin_bank *bank = ddata->bank; - - if (!(bank->eint_mask & (1 << hw))) - return -EINVAL; - - irq_set_chip_and_handler(virq, - &s3c64xx_eint0_irq_chip, handle_level_irq); - irq_set_chip_data(virq, ddata); - set_irq_flags(virq, IRQF_VALID); - - return 0; -} - -/* - * irq domain callbacks for external wakeup interrupt controller. - */ -static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = { - .map = s3c64xx_eint0_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -/* list of external wakeup controllers supported */ -static const struct of_device_id s3c64xx_eint0_irq_ids[] = { - { .compatible = "samsung,s3c64xx-wakeup-eint", }, - { } -}; - -/** - * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts. - * @d: driver data of samsung pinctrl driver. - */ -static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d) -{ - struct device *dev = d->dev; - struct device_node *eint0_np = NULL; - struct device_node *np; - struct samsung_pin_bank *bank; - struct s3c64xx_eint0_data *data; - unsigned int i; - - for_each_child_of_node(dev->of_node, np) { - if (of_match_node(s3c64xx_eint0_irq_ids, np)) { - eint0_np = np; - break; - } - } - if (!eint0_np) - return -ENODEV; - - data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); - if (!data) { - dev_err(dev, "could not allocate memory for wkup eint data\n"); - return -ENOMEM; - } - data->drvdata = d; - - for (i = 0; i < NUM_EINT0_IRQ; ++i) { - unsigned int irq; - - irq = irq_of_parse_and_map(eint0_np, i); - if (!irq) { - dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); - return -ENXIO; - } - - irq_set_chained_handler(irq, s3c64xx_eint0_handlers[i]); - irq_set_handler_data(irq, data); - } - - bank = d->ctrl->pin_banks; - for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { - struct s3c64xx_eint0_domain_data *ddata; - unsigned int nr_eints; - unsigned int mask; - unsigned int irq; - unsigned int pin; - - if (bank->eint_type != EINT_TYPE_WKUP) - continue; - - mask = bank->eint_mask; - nr_eints = fls(mask); - - ddata = devm_kzalloc(dev, - sizeof(*ddata) + nr_eints, GFP_KERNEL); - if (!ddata) { - dev_err(dev, "failed to allocate domain data\n"); - return -ENOMEM; - } - ddata->bank = bank; - - bank->irq_domain = irq_domain_add_linear(bank->of_node, - nr_eints, &s3c64xx_eint0_irqd_ops, ddata); - if (!bank->irq_domain) { - dev_err(dev, "wkup irq domain add failed\n"); - return -ENXIO; - } - - irq = bank->eint_offset; - mask = bank->eint_mask; - for (pin = 0; mask; ++pin, mask >>= 1) { - if (!(mask & 1)) - continue; - data->domains[irq] = bank->irq_domain; - data->pins[irq] = pin; - ddata->eints[pin] = irq; - ++irq; - } - } - - return 0; -} - -/* pin banks of s3c64xx pin-controller 0 */ -static struct samsung_pin_bank s3c64xx_pin_banks0[] = { - PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0), - PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8), - PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16), - PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32), - PIN_BANK_4BIT(5, 0x080, "gpe"), - PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff), - PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64), - PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80), - PIN_BANK_2BIT(16, 0x100, "gpi"), - PIN_BANK_2BIT(12, 0x120, "gpj"), - PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"), - PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00), - PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f), - PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0), - PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff), - PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff), - PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff), -}; - -/* - * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes - * one gpio/pin-mux/pinconfig controller. - */ -struct samsung_pin_ctrl s3c64xx_pin_ctrl[] = { - { - /* pin-controller instance 1 data */ - .pin_banks = s3c64xx_pin_banks0, - .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0), - .eint_gpio_init = s3c64xx_eint_gpio_init, - .eint_wkup_init = s3c64xx_eint_eint0_init, - .label = "S3C64xx-GPIO", - }, -}; diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c deleted file mode 100644 index 52f849ac06c1..000000000000 --- a/drivers/pinctrl/pinctrl-samsung.c +++ /dev/null @@ -1,1285 +0,0 @@ -/* - * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2012 Linaro Ltd - * http://www.linaro.org - * - * Author: Thomas Abraham - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This driver implements the Samsung pinctrl driver. It supports setting up of - * pinmux and pinconf configurations. The gpiolib interface is also included. - * External interrupt (gpio and wakeup) support are not included in this driver - * but provides extensions to which platform specific implementation of the gpio - * and wakeup interrupts can be hooked to. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" -#include "pinctrl-samsung.h" - -#define GROUP_SUFFIX "-grp" -#define GSUFFIX_LEN sizeof(GROUP_SUFFIX) -#define FUNCTION_SUFFIX "-mux" -#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX) - -/* list of all possible config options supported */ -static struct pin_config { - const char *property; - enum pincfg_type param; -} cfg_params[] = { - { "samsung,pin-pud", PINCFG_TYPE_PUD }, - { "samsung,pin-drv", PINCFG_TYPE_DRV }, - { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN }, - { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, - { "samsung,pin-val", PINCFG_TYPE_DAT }, -}; - -/* Global list of devices (struct samsung_pinctrl_drv_data) */ -static LIST_HEAD(drvdata_list); - -static unsigned int pin_base; - -static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) -{ - return container_of(gc, struct samsung_pin_bank, gpio_chip); -} - -static int samsung_get_group_count(struct pinctrl_dev *pctldev) -{ - struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->nr_groups; -} - -static const char *samsung_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->pin_groups[group].name; -} - -static int samsung_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, - const unsigned **pins, - unsigned *num_pins) -{ - struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); - - *pins = pmx->pin_groups[group].pins; - *num_pins = pmx->pin_groups[group].num_pins; - - return 0; -} - -static int reserve_map(struct device *dev, struct pinctrl_map **map, - unsigned *reserved_maps, unsigned *num_maps, - unsigned reserve) -{ - unsigned old_num = *reserved_maps; - unsigned new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) { - dev_err(dev, "krealloc(map) failed\n"); - return -ENOMEM; - } - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, const char *group, - const char *function) -{ - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -static int add_map_configs(struct device *dev, struct pinctrl_map **map, - unsigned *reserved_maps, unsigned *num_maps, - const char *group, unsigned long *configs, - unsigned num_configs) -{ - unsigned long *dup_configs; - - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) { - dev_err(dev, "kmemdup(configs) failed\n"); - return -ENOMEM; - } - - (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static int add_config(struct device *dev, unsigned long **configs, - unsigned *num_configs, unsigned long config) -{ - unsigned old_num = *num_configs; - unsigned new_num = old_num + 1; - unsigned long *new_configs; - - new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, - GFP_KERNEL); - if (!new_configs) { - dev_err(dev, "krealloc(configs) failed\n"); - return -ENOMEM; - } - - new_configs[old_num] = config; - - *configs = new_configs; - *num_configs = new_num; - - return 0; -} - -static void samsung_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, - unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - - kfree(map); -} - -static int samsung_dt_subnode_to_map(struct samsung_pinctrl_drv_data *drvdata, - struct device *dev, - struct device_node *np, - struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps) -{ - int ret, i; - u32 val; - unsigned long config; - unsigned long *configs = NULL; - unsigned num_configs = 0; - unsigned reserve; - struct property *prop; - const char *group; - bool has_func = false; - - ret = of_property_read_u32(np, "samsung,pin-function", &val); - if (!ret) - has_func = true; - - for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { - ret = of_property_read_u32(np, cfg_params[i].property, &val); - if (!ret) { - config = PINCFG_PACK(cfg_params[i].param, val); - ret = add_config(dev, &configs, &num_configs, config); - if (ret < 0) - goto exit; - /* EINVAL=missing, which is fine since it's optional */ - } else if (ret != -EINVAL) { - dev_err(dev, "could not parse property %s\n", - cfg_params[i].property); - } - } - - reserve = 0; - if (has_func) - reserve++; - if (num_configs) - reserve++; - ret = of_property_count_strings(np, "samsung,pins"); - if (ret < 0) { - dev_err(dev, "could not parse property samsung,pins\n"); - goto exit; - } - reserve *= ret; - - ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "samsung,pins", prop, group) { - if (has_func) { - ret = add_map_mux(map, reserved_maps, - num_maps, group, np->full_name); - if (ret < 0) - goto exit; - } - - if (num_configs) { - ret = add_map_configs(dev, map, reserved_maps, - num_maps, group, configs, - num_configs); - if (ret < 0) - goto exit; - } - } - - ret = 0; - -exit: - kfree(configs); - return ret; -} - -static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - unsigned *num_maps) -{ - struct samsung_pinctrl_drv_data *drvdata; - unsigned reserved_maps; - struct device_node *np; - int ret; - - drvdata = pinctrl_dev_get_drvdata(pctldev); - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - if (!of_get_child_count(np_config)) - return samsung_dt_subnode_to_map(drvdata, pctldev->dev, - np_config, map, - &reserved_maps, - num_maps); - - for_each_child_of_node(np_config, np) { - ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map, - &reserved_maps, num_maps); - if (ret < 0) { - samsung_dt_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; -} - -/* list of pinctrl callbacks for the pinctrl core */ -static const struct pinctrl_ops samsung_pctrl_ops = { - .get_groups_count = samsung_get_group_count, - .get_group_name = samsung_get_group_name, - .get_group_pins = samsung_get_group_pins, - .dt_node_to_map = samsung_dt_node_to_map, - .dt_free_map = samsung_dt_free_map, -}; - -/* check if the selector is a valid pin function selector */ -static int samsung_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct samsung_pinctrl_drv_data *drvdata; - - drvdata = pinctrl_dev_get_drvdata(pctldev); - return drvdata->nr_functions; -} - -/* return the name of the pin function specified */ -static const char *samsung_pinmux_get_fname(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct samsung_pinctrl_drv_data *drvdata; - - drvdata = pinctrl_dev_get_drvdata(pctldev); - return drvdata->pmx_functions[selector].name; -} - -/* return the groups associated for the specified function selector */ -static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev, - unsigned selector, const char * const **groups, - unsigned * const num_groups) -{ - struct samsung_pinctrl_drv_data *drvdata; - - drvdata = pinctrl_dev_get_drvdata(pctldev); - *groups = drvdata->pmx_functions[selector].groups; - *num_groups = drvdata->pmx_functions[selector].num_groups; - return 0; -} - -/* - * given a pin number that is local to a pin controller, find out the pin bank - * and the register base of the pin bank. - */ -static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, - unsigned pin, void __iomem **reg, u32 *offset, - struct samsung_pin_bank **bank) -{ - struct samsung_pin_bank *b; - - b = drvdata->ctrl->pin_banks; - - while ((pin >= b->pin_base) && - ((b->pin_base + b->nr_pins - 1) < pin)) - b++; - - *reg = drvdata->virt_base + b->pctl_offset; - *offset = pin - b->pin_base; - if (bank) - *bank = b; -} - -/* enable or disable a pinmux function */ -static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group, bool enable) -{ - struct samsung_pinctrl_drv_data *drvdata; - struct samsung_pin_bank_type *type; - struct samsung_pin_bank *bank; - void __iomem *reg; - u32 mask, shift, data, pin_offset; - unsigned long flags; - const struct samsung_pmx_func *func; - const struct samsung_pin_group *grp; - - drvdata = pinctrl_dev_get_drvdata(pctldev); - func = &drvdata->pmx_functions[selector]; - grp = &drvdata->pin_groups[group]; - - pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->ctrl->base, - ®, &pin_offset, &bank); - type = bank->type; - mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; - shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; - if (shift >= 32) { - /* Some banks have two config registers */ - shift -= 32; - reg += 4; - } - - spin_lock_irqsave(&bank->slock, flags); - - data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); - data &= ~(mask << shift); - if (enable) - data |= func->val << shift; - writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); - - spin_unlock_irqrestore(&bank->slock, flags); -} - -/* enable a specified pinmux by writing to registers */ -static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - samsung_pinmux_setup(pctldev, selector, group, true); - return 0; -} - -/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ -static const struct pinmux_ops samsung_pinmux_ops = { - .get_functions_count = samsung_get_functions_count, - .get_function_name = samsung_pinmux_get_fname, - .get_function_groups = samsung_pinmux_get_groups, - .enable = samsung_pinmux_enable, -}; - -/* set or get the pin config settings for a specified pin */ -static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *config, bool set) -{ - struct samsung_pinctrl_drv_data *drvdata; - struct samsung_pin_bank_type *type; - struct samsung_pin_bank *bank; - void __iomem *reg_base; - enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); - u32 data, width, pin_offset, mask, shift; - u32 cfg_value, cfg_reg; - unsigned long flags; - - drvdata = pinctrl_dev_get_drvdata(pctldev); - pin_to_reg_bank(drvdata, pin - drvdata->ctrl->base, ®_base, - &pin_offset, &bank); - type = bank->type; - - if (cfg_type >= PINCFG_TYPE_NUM || !type->fld_width[cfg_type]) - return -EINVAL; - - width = type->fld_width[cfg_type]; - cfg_reg = type->reg_offset[cfg_type]; - - spin_lock_irqsave(&bank->slock, flags); - - mask = (1 << width) - 1; - shift = pin_offset * width; - data = readl(reg_base + cfg_reg); - - if (set) { - cfg_value = PINCFG_UNPACK_VALUE(*config); - data &= ~(mask << shift); - data |= (cfg_value << shift); - writel(data, reg_base + cfg_reg); - } else { - data >>= shift; - data &= mask; - *config = PINCFG_PACK(cfg_type, data); - } - - spin_unlock_irqrestore(&bank->slock, flags); - - return 0; -} - -/* set the pin config settings for a specified pin */ -static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned num_configs) -{ - int i, ret; - - for (i = 0; i < num_configs; i++) { - ret = samsung_pinconf_rw(pctldev, pin, &configs[i], true); - if (ret < 0) - return ret; - } /* for each config */ - - return 0; -} - -/* get the pin config settings for a specified pin */ -static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *config) -{ - return samsung_pinconf_rw(pctldev, pin, config, false); -} - -/* set the pin config settings for a specified pin group */ -static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long *configs, - unsigned num_configs) -{ - struct samsung_pinctrl_drv_data *drvdata; - const unsigned int *pins; - unsigned int cnt; - - drvdata = pinctrl_dev_get_drvdata(pctldev); - pins = drvdata->pin_groups[group].pins; - - for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) - samsung_pinconf_set(pctldev, pins[cnt], configs, num_configs); - - return 0; -} - -/* get the pin config settings for a specified pin group */ -static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long *config) -{ - struct samsung_pinctrl_drv_data *drvdata; - const unsigned int *pins; - - drvdata = pinctrl_dev_get_drvdata(pctldev); - pins = drvdata->pin_groups[group].pins; - samsung_pinconf_get(pctldev, pins[0], config); - return 0; -} - -/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ -static const struct pinconf_ops samsung_pinconf_ops = { - .pin_config_get = samsung_pinconf_get, - .pin_config_set = samsung_pinconf_set, - .pin_config_group_get = samsung_pinconf_group_get, - .pin_config_group_set = samsung_pinconf_group_set, -}; - -/* gpiolib gpio_set callback function */ -static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) -{ - struct samsung_pin_bank *bank = gc_to_pin_bank(gc); - struct samsung_pin_bank_type *type = bank->type; - unsigned long flags; - void __iomem *reg; - u32 data; - - reg = bank->drvdata->virt_base + bank->pctl_offset; - - spin_lock_irqsave(&bank->slock, flags); - - data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); - data &= ~(1 << offset); - if (value) - data |= 1 << offset; - writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]); - - spin_unlock_irqrestore(&bank->slock, flags); -} - -/* gpiolib gpio_get callback function */ -static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset) -{ - void __iomem *reg; - u32 data; - struct samsung_pin_bank *bank = gc_to_pin_bank(gc); - struct samsung_pin_bank_type *type = bank->type; - - reg = bank->drvdata->virt_base + bank->pctl_offset; - - data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); - data >>= offset; - data &= 1; - return data; -} - -/* - * The calls to gpio_direction_output() and gpio_direction_input() - * leads to this function call. - */ -static int samsung_gpio_set_direction(struct gpio_chip *gc, - unsigned offset, bool input) -{ - struct samsung_pin_bank_type *type; - struct samsung_pin_bank *bank; - struct samsung_pinctrl_drv_data *drvdata; - void __iomem *reg; - u32 data, mask, shift; - unsigned long flags; - - bank = gc_to_pin_bank(gc); - type = bank->type; - drvdata = bank->drvdata; - - reg = drvdata->virt_base + bank->pctl_offset + - type->reg_offset[PINCFG_TYPE_FUNC]; - - mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; - shift = offset * type->fld_width[PINCFG_TYPE_FUNC]; - if (shift >= 32) { - /* Some banks have two config registers */ - shift -= 32; - reg += 4; - } - - spin_lock_irqsave(&bank->slock, flags); - - data = readl(reg); - data &= ~(mask << shift); - if (!input) - data |= FUNC_OUTPUT << shift; - writel(data, reg); - - spin_unlock_irqrestore(&bank->slock, flags); - - return 0; -} - -/* gpiolib gpio_direction_input callback function. */ -static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) -{ - return samsung_gpio_set_direction(gc, offset, true); -} - -/* gpiolib gpio_direction_output callback function. */ -static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, - int value) -{ - samsung_gpio_set(gc, offset, value); - return samsung_gpio_set_direction(gc, offset, false); -} - -/* - * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin - * and a virtual IRQ, if not already present. - */ -static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset) -{ - struct samsung_pin_bank *bank = gc_to_pin_bank(gc); - unsigned int virq; - - if (!bank->irq_domain) - return -ENXIO; - - virq = irq_create_mapping(bank->irq_domain, offset); - - return (virq) ? : -ENXIO; -} - -static struct samsung_pin_group *samsung_pinctrl_create_groups( - struct device *dev, - struct samsung_pinctrl_drv_data *drvdata, - unsigned int *cnt) -{ - struct pinctrl_desc *ctrldesc = &drvdata->pctl; - struct samsung_pin_group *groups, *grp; - const struct pinctrl_pin_desc *pdesc; - int i; - - groups = devm_kzalloc(dev, ctrldesc->npins * sizeof(*groups), - GFP_KERNEL); - if (!groups) - return ERR_PTR(-EINVAL); - grp = groups; - - pdesc = ctrldesc->pins; - for (i = 0; i < ctrldesc->npins; ++i, ++pdesc, ++grp) { - grp->name = pdesc->name; - grp->pins = &pdesc->number; - grp->num_pins = 1; - } - - *cnt = ctrldesc->npins; - return groups; -} - -static int samsung_pinctrl_create_function(struct device *dev, - struct samsung_pinctrl_drv_data *drvdata, - struct device_node *func_np, - struct samsung_pmx_func *func) -{ - int npins; - int ret; - int i; - - if (of_property_read_u32(func_np, "samsung,pin-function", &func->val)) - return 0; - - npins = of_property_count_strings(func_np, "samsung,pins"); - if (npins < 1) { - dev_err(dev, "invalid pin list in %s node", func_np->name); - return -EINVAL; - } - - func->name = func_np->full_name; - - func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL); - if (!func->groups) - return -ENOMEM; - - for (i = 0; i < npins; ++i) { - const char *gname; - - ret = of_property_read_string_index(func_np, "samsung,pins", - i, &gname); - if (ret) { - dev_err(dev, - "failed to read pin name %d from %s node\n", - i, func_np->name); - return ret; - } - - func->groups[i] = gname; - } - - func->num_groups = npins; - return 1; -} - -static struct samsung_pmx_func *samsung_pinctrl_create_functions( - struct device *dev, - struct samsung_pinctrl_drv_data *drvdata, - unsigned int *cnt) -{ - struct samsung_pmx_func *functions, *func; - struct device_node *dev_np = dev->of_node; - struct device_node *cfg_np; - unsigned int func_cnt = 0; - int ret; - - /* - * Iterate over all the child nodes of the pin controller node - * and create pin groups and pin function lists. - */ - for_each_child_of_node(dev_np, cfg_np) { - struct device_node *func_np; - - if (!of_get_child_count(cfg_np)) { - if (!of_find_property(cfg_np, - "samsung,pin-function", NULL)) - continue; - ++func_cnt; - continue; - } - - for_each_child_of_node(cfg_np, func_np) { - if (!of_find_property(func_np, - "samsung,pin-function", NULL)) - continue; - ++func_cnt; - } - } - - functions = devm_kzalloc(dev, func_cnt * sizeof(*functions), - GFP_KERNEL); - if (!functions) { - dev_err(dev, "failed to allocate memory for function list\n"); - return ERR_PTR(-EINVAL); - } - func = functions; - - /* - * Iterate over all the child nodes of the pin controller node - * and create pin groups and pin function lists. - */ - func_cnt = 0; - for_each_child_of_node(dev_np, cfg_np) { - struct device_node *func_np; - - if (!of_get_child_count(cfg_np)) { - ret = samsung_pinctrl_create_function(dev, drvdata, - cfg_np, func); - if (ret < 0) - return ERR_PTR(ret); - if (ret > 0) { - ++func; - ++func_cnt; - } - continue; - } - - for_each_child_of_node(cfg_np, func_np) { - ret = samsung_pinctrl_create_function(dev, drvdata, - func_np, func); - if (ret < 0) - return ERR_PTR(ret); - if (ret > 0) { - ++func; - ++func_cnt; - } - } - } - - *cnt = func_cnt; - return functions; -} - -/* - * Parse the information about all the available pin groups and pin functions - * from device node of the pin-controller. A pin group is formed with all - * the pins listed in the "samsung,pins" property. - */ - -static int samsung_pinctrl_parse_dt(struct platform_device *pdev, - struct samsung_pinctrl_drv_data *drvdata) -{ - struct device *dev = &pdev->dev; - struct samsung_pin_group *groups; - struct samsung_pmx_func *functions; - unsigned int grp_cnt = 0, func_cnt = 0; - - groups = samsung_pinctrl_create_groups(dev, drvdata, &grp_cnt); - if (IS_ERR(groups)) { - dev_err(dev, "failed to parse pin groups\n"); - return PTR_ERR(groups); - } - - functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt); - if (IS_ERR(functions)) { - dev_err(dev, "failed to parse pin functions\n"); - return PTR_ERR(groups); - } - - drvdata->pin_groups = groups; - drvdata->nr_groups = grp_cnt; - drvdata->pmx_functions = functions; - drvdata->nr_functions = func_cnt; - - return 0; -} - -/* register the pinctrl interface with the pinctrl subsystem */ -static int samsung_pinctrl_register(struct platform_device *pdev, - struct samsung_pinctrl_drv_data *drvdata) -{ - struct pinctrl_desc *ctrldesc = &drvdata->pctl; - struct pinctrl_pin_desc *pindesc, *pdesc; - struct samsung_pin_bank *pin_bank; - char *pin_names; - int pin, bank, ret; - - ctrldesc->name = "samsung-pinctrl"; - ctrldesc->owner = THIS_MODULE; - ctrldesc->pctlops = &samsung_pctrl_ops; - ctrldesc->pmxops = &samsung_pinmux_ops; - ctrldesc->confops = &samsung_pinconf_ops; - - pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * - drvdata->ctrl->nr_pins, GFP_KERNEL); - if (!pindesc) { - dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); - return -ENOMEM; - } - ctrldesc->pins = pindesc; - ctrldesc->npins = drvdata->ctrl->nr_pins; - - /* dynamically populate the pin number and pin name for pindesc */ - for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) - pdesc->number = pin + drvdata->ctrl->base; - - /* - * allocate space for storing the dynamically generated names for all - * the pins which belong to this pin-controller. - */ - pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * - drvdata->ctrl->nr_pins, GFP_KERNEL); - if (!pin_names) { - dev_err(&pdev->dev, "mem alloc for pin names failed\n"); - return -ENOMEM; - } - - /* for each pin, the name of the pin is pin-bank name + pin number */ - for (bank = 0; bank < drvdata->ctrl->nr_banks; bank++) { - pin_bank = &drvdata->ctrl->pin_banks[bank]; - for (pin = 0; pin < pin_bank->nr_pins; pin++) { - sprintf(pin_names, "%s-%d", pin_bank->name, pin); - pdesc = pindesc + pin_bank->pin_base + pin; - pdesc->name = pin_names; - pin_names += PIN_NAME_LENGTH; - } - } - - ret = samsung_pinctrl_parse_dt(pdev, drvdata); - if (ret) - return ret; - - drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata); - if (!drvdata->pctl_dev) { - dev_err(&pdev->dev, "could not register pinctrl driver\n"); - return -EINVAL; - } - - for (bank = 0; bank < drvdata->ctrl->nr_banks; ++bank) { - pin_bank = &drvdata->ctrl->pin_banks[bank]; - pin_bank->grange.name = pin_bank->name; - pin_bank->grange.id = bank; - pin_bank->grange.pin_base = drvdata->ctrl->base - + pin_bank->pin_base; - pin_bank->grange.base = pin_bank->gpio_chip.base; - pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; - pin_bank->grange.gc = &pin_bank->gpio_chip; - pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); - } - - return 0; -} - -static int samsung_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - return pinctrl_request_gpio(chip->base + offset); -} - -static void samsung_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - pinctrl_free_gpio(chip->base + offset); -} - -static const struct gpio_chip samsung_gpiolib_chip = { - .request = samsung_gpio_request, - .free = samsung_gpio_free, - .set = samsung_gpio_set, - .get = samsung_gpio_get, - .direction_input = samsung_gpio_direction_input, - .direction_output = samsung_gpio_direction_output, - .to_irq = samsung_gpio_to_irq, - .owner = THIS_MODULE, -}; - -/* register the gpiolib interface with the gpiolib subsystem */ -static int samsung_gpiolib_register(struct platform_device *pdev, - struct samsung_pinctrl_drv_data *drvdata) -{ - struct samsung_pin_ctrl *ctrl = drvdata->ctrl; - struct samsung_pin_bank *bank = ctrl->pin_banks; - struct gpio_chip *gc; - int ret; - int i; - - for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { - bank->gpio_chip = samsung_gpiolib_chip; - - gc = &bank->gpio_chip; - gc->base = ctrl->base + bank->pin_base; - gc->ngpio = bank->nr_pins; - gc->dev = &pdev->dev; - gc->of_node = bank->of_node; - gc->label = bank->name; - - ret = gpiochip_add(gc); - if (ret) { - dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", - gc->label, ret); - goto fail; - } - } - - return 0; - -fail: - for (--i, --bank; i >= 0; --i, --bank) - if (gpiochip_remove(&bank->gpio_chip)) - dev_err(&pdev->dev, "gpio chip %s remove failed\n", - bank->gpio_chip.label); - return ret; -} - -/* unregister the gpiolib interface with the gpiolib subsystem */ -static int samsung_gpiolib_unregister(struct platform_device *pdev, - struct samsung_pinctrl_drv_data *drvdata) -{ - struct samsung_pin_ctrl *ctrl = drvdata->ctrl; - struct samsung_pin_bank *bank = ctrl->pin_banks; - int ret = 0; - int i; - - for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) - ret = gpiochip_remove(&bank->gpio_chip); - - if (ret) - dev_err(&pdev->dev, "gpio chip remove failed\n"); - - return ret; -} - -static const struct of_device_id samsung_pinctrl_dt_match[]; - -/* retrieve the soc specific data */ -static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data( - struct samsung_pinctrl_drv_data *d, - struct platform_device *pdev) -{ - int id; - const struct of_device_id *match; - struct device_node *node = pdev->dev.of_node; - struct device_node *np; - struct samsung_pin_ctrl *ctrl; - struct samsung_pin_bank *bank; - int i; - - id = of_alias_get_id(node, "pinctrl"); - if (id < 0) { - dev_err(&pdev->dev, "failed to get alias id\n"); - return NULL; - } - match = of_match_node(samsung_pinctrl_dt_match, node); - ctrl = (struct samsung_pin_ctrl *)match->data + id; - - bank = ctrl->pin_banks; - for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { - spin_lock_init(&bank->slock); - bank->drvdata = d; - bank->pin_base = ctrl->nr_pins; - ctrl->nr_pins += bank->nr_pins; - } - - for_each_child_of_node(node, np) { - if (!of_find_property(np, "gpio-controller", NULL)) - continue; - bank = ctrl->pin_banks; - for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { - if (!strcmp(bank->name, np->name)) { - bank->of_node = np; - break; - } - } - } - - ctrl->base = pin_base; - pin_base += ctrl->nr_pins; - - return ctrl; -} - -static int samsung_pinctrl_probe(struct platform_device *pdev) -{ - struct samsung_pinctrl_drv_data *drvdata; - struct device *dev = &pdev->dev; - struct samsung_pin_ctrl *ctrl; - struct resource *res; - int ret; - - if (!dev->of_node) { - dev_err(dev, "device tree node not found\n"); - return -ENODEV; - } - - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) { - dev_err(dev, "failed to allocate memory for driver's " - "private data\n"); - return -ENOMEM; - } - - ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev); - if (!ctrl) { - dev_err(&pdev->dev, "driver data not available\n"); - return -EINVAL; - } - drvdata->ctrl = ctrl; - drvdata->dev = dev; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - drvdata->virt_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(drvdata->virt_base)) - return PTR_ERR(drvdata->virt_base); - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (res) - drvdata->irq = res->start; - - ret = samsung_gpiolib_register(pdev, drvdata); - if (ret) - return ret; - - ret = samsung_pinctrl_register(pdev, drvdata); - if (ret) { - samsung_gpiolib_unregister(pdev, drvdata); - return ret; - } - - if (ctrl->eint_gpio_init) - ctrl->eint_gpio_init(drvdata); - if (ctrl->eint_wkup_init) - ctrl->eint_wkup_init(drvdata); - - platform_set_drvdata(pdev, drvdata); - - /* Add to the global list */ - list_add_tail(&drvdata->node, &drvdata_list); - - return 0; -} - -#ifdef CONFIG_PM - -/** - * samsung_pinctrl_suspend_dev - save pinctrl state for suspend for a device - * - * Save data for all banks handled by this device. - */ -static void samsung_pinctrl_suspend_dev( - struct samsung_pinctrl_drv_data *drvdata) -{ - struct samsung_pin_ctrl *ctrl = drvdata->ctrl; - void __iomem *virt_base = drvdata->virt_base; - int i; - - for (i = 0; i < ctrl->nr_banks; i++) { - struct samsung_pin_bank *bank = &ctrl->pin_banks[i]; - void __iomem *reg = virt_base + bank->pctl_offset; - - u8 *offs = bank->type->reg_offset; - u8 *widths = bank->type->fld_width; - enum pincfg_type type; - - /* Registers without a powerdown config aren't lost */ - if (!widths[PINCFG_TYPE_CON_PDN]) - continue; - - for (type = 0; type < PINCFG_TYPE_NUM; type++) - if (widths[type]) - bank->pm_save[type] = readl(reg + offs[type]); - - if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { - /* Some banks have two config registers */ - bank->pm_save[PINCFG_TYPE_NUM] = - readl(reg + offs[PINCFG_TYPE_FUNC] + 4); - pr_debug("Save %s @ %p (con %#010x %08x)\n", - bank->name, reg, - bank->pm_save[PINCFG_TYPE_FUNC], - bank->pm_save[PINCFG_TYPE_NUM]); - } else { - pr_debug("Save %s @ %p (con %#010x)\n", bank->name, - reg, bank->pm_save[PINCFG_TYPE_FUNC]); - } - } - - if (ctrl->suspend) - ctrl->suspend(drvdata); -} - -/** - * samsung_pinctrl_resume_dev - restore pinctrl state from suspend for a device - * - * Restore one of the banks that was saved during suspend. - * - * We don't bother doing anything complicated to avoid glitching lines since - * we're called before pad retention is turned off. - */ -static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata) -{ - struct samsung_pin_ctrl *ctrl = drvdata->ctrl; - void __iomem *virt_base = drvdata->virt_base; - int i; - - if (ctrl->resume) - ctrl->resume(drvdata); - - for (i = 0; i < ctrl->nr_banks; i++) { - struct samsung_pin_bank *bank = &ctrl->pin_banks[i]; - void __iomem *reg = virt_base + bank->pctl_offset; - - u8 *offs = bank->type->reg_offset; - u8 *widths = bank->type->fld_width; - enum pincfg_type type; - - /* Registers without a powerdown config aren't lost */ - if (!widths[PINCFG_TYPE_CON_PDN]) - continue; - - if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { - /* Some banks have two config registers */ - pr_debug("%s @ %p (con %#010x %08x => %#010x %08x)\n", - bank->name, reg, - readl(reg + offs[PINCFG_TYPE_FUNC]), - readl(reg + offs[PINCFG_TYPE_FUNC] + 4), - bank->pm_save[PINCFG_TYPE_FUNC], - bank->pm_save[PINCFG_TYPE_NUM]); - writel(bank->pm_save[PINCFG_TYPE_NUM], - reg + offs[PINCFG_TYPE_FUNC] + 4); - } else { - pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name, - reg, readl(reg + offs[PINCFG_TYPE_FUNC]), - bank->pm_save[PINCFG_TYPE_FUNC]); - } - for (type = 0; type < PINCFG_TYPE_NUM; type++) - if (widths[type]) - writel(bank->pm_save[type], reg + offs[type]); - } -} - -/** - * samsung_pinctrl_suspend - save pinctrl state for suspend - * - * Save data for all banks across all devices. - */ -static int samsung_pinctrl_suspend(void) -{ - struct samsung_pinctrl_drv_data *drvdata; - - list_for_each_entry(drvdata, &drvdata_list, node) { - samsung_pinctrl_suspend_dev(drvdata); - } - - return 0; -} - -/** - * samsung_pinctrl_resume - restore pinctrl state for suspend - * - * Restore data for all banks across all devices. - */ -static void samsung_pinctrl_resume(void) -{ - struct samsung_pinctrl_drv_data *drvdata; - - list_for_each_entry_reverse(drvdata, &drvdata_list, node) { - samsung_pinctrl_resume_dev(drvdata); - } -} - -#else -#define samsung_pinctrl_suspend NULL -#define samsung_pinctrl_resume NULL -#endif - -static struct syscore_ops samsung_pinctrl_syscore_ops = { - .suspend = samsung_pinctrl_suspend, - .resume = samsung_pinctrl_resume, -}; - -static const struct of_device_id samsung_pinctrl_dt_match[] = { -#ifdef CONFIG_PINCTRL_EXYNOS - { .compatible = "samsung,exynos3250-pinctrl", - .data = (void *)exynos3250_pin_ctrl }, - { .compatible = "samsung,exynos4210-pinctrl", - .data = (void *)exynos4210_pin_ctrl }, - { .compatible = "samsung,exynos4x12-pinctrl", - .data = (void *)exynos4x12_pin_ctrl }, - { .compatible = "samsung,exynos5250-pinctrl", - .data = (void *)exynos5250_pin_ctrl }, - { .compatible = "samsung,exynos5260-pinctrl", - .data = (void *)exynos5260_pin_ctrl }, - { .compatible = "samsung,exynos5420-pinctrl", - .data = (void *)exynos5420_pin_ctrl }, - { .compatible = "samsung,s5pv210-pinctrl", - .data = (void *)s5pv210_pin_ctrl }, -#endif -#ifdef CONFIG_PINCTRL_S3C64XX - { .compatible = "samsung,s3c64xx-pinctrl", - .data = s3c64xx_pin_ctrl }, -#endif -#ifdef CONFIG_PINCTRL_S3C24XX - { .compatible = "samsung,s3c2412-pinctrl", - .data = s3c2412_pin_ctrl }, - { .compatible = "samsung,s3c2416-pinctrl", - .data = s3c2416_pin_ctrl }, - { .compatible = "samsung,s3c2440-pinctrl", - .data = s3c2440_pin_ctrl }, - { .compatible = "samsung,s3c2450-pinctrl", - .data = s3c2450_pin_ctrl }, -#endif - {}, -}; -MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); - -static struct platform_driver samsung_pinctrl_driver = { - .probe = samsung_pinctrl_probe, - .driver = { - .name = "samsung-pinctrl", - .owner = THIS_MODULE, - .of_match_table = samsung_pinctrl_dt_match, - }, -}; - -static int __init samsung_pinctrl_drv_register(void) -{ - /* - * Register syscore ops for save/restore of registers across suspend. - * It's important to ensure that this driver is running at an earlier - * initcall level than any arch-specific init calls that install syscore - * ops that turn off pad retention (like exynos_pm_resume). - */ - register_syscore_ops(&samsung_pinctrl_syscore_ops); - - return platform_driver_register(&samsung_pinctrl_driver); -} -postcore_initcall(samsung_pinctrl_drv_register); - -static void __exit samsung_pinctrl_drv_unregister(void) -{ - platform_driver_unregister(&samsung_pinctrl_driver); -} -module_exit(samsung_pinctrl_drv_unregister); - -MODULE_AUTHOR("Thomas Abraham "); -MODULE_DESCRIPTION("Samsung pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h deleted file mode 100644 index 2b882320e8e9..000000000000 --- a/drivers/pinctrl/pinctrl-samsung.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2012 Linaro Ltd - * http://www.linaro.org - * - * Author: Thomas Abraham - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __PINCTRL_SAMSUNG_H -#define __PINCTRL_SAMSUNG_H - -#include -#include -#include -#include -#include - -#include - -/* pinmux function number for pin as gpio output line */ -#define FUNC_OUTPUT 0x1 - -/** - * enum pincfg_type - possible pin configuration types supported. - * @PINCFG_TYPE_FUNC: Function configuration. - * @PINCFG_TYPE_DAT: Pin value configuration. - * @PINCFG_TYPE_PUD: Pull up/down configuration. - * @PINCFG_TYPE_DRV: Drive strength configuration. - * @PINCFG_TYPE_CON_PDN: Pin function in power down mode. - * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode. - */ -enum pincfg_type { - PINCFG_TYPE_FUNC, - PINCFG_TYPE_DAT, - PINCFG_TYPE_PUD, - PINCFG_TYPE_DRV, - PINCFG_TYPE_CON_PDN, - PINCFG_TYPE_PUD_PDN, - - PINCFG_TYPE_NUM -}; - -/* - * pin configuration (pull up/down and drive strength) type and its value are - * packed together into a 16-bits. The upper 8-bits represent the configuration - * type and the lower 8-bits hold the value of the configuration type. - */ -#define PINCFG_TYPE_MASK 0xFF -#define PINCFG_VALUE_SHIFT 8 -#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) -#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) -#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) -#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ - PINCFG_VALUE_SHIFT) -/** - * enum eint_type - possible external interrupt types. - * @EINT_TYPE_NONE: bank does not support external interrupts - * @EINT_TYPE_GPIO: bank supportes external gpio interrupts - * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts - * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts - * - * Samsung GPIO controller groups all the available pins into banks. The pins - * in a pin bank can support external gpio interrupts or external wakeup - * interrupts or no interrupts at all. From a software perspective, the only - * difference between external gpio and external wakeup interrupts is that - * the wakeup interrupts can additionally wakeup the system if it is in - * suspended state. - */ -enum eint_type { - EINT_TYPE_NONE, - EINT_TYPE_GPIO, - EINT_TYPE_WKUP, - EINT_TYPE_WKUP_MUX, -}; - -/* maximum length of a pin in pin descriptor (example: "gpa0-0") */ -#define PIN_NAME_LENGTH 10 - -#define PIN_GROUP(n, p, f) \ - { \ - .name = n, \ - .pins = p, \ - .num_pins = ARRAY_SIZE(p), \ - .func = f \ - } - -#define PMX_FUNC(n, g) \ - { \ - .name = n, \ - .groups = g, \ - .num_groups = ARRAY_SIZE(g), \ - } - -struct samsung_pinctrl_drv_data; - -/** - * struct samsung_pin_bank_type: pin bank type description - * @fld_width: widths of configuration bitfields (0 if unavailable) - * @reg_offset: offsets of configuration registers (don't care of width is 0) - */ -struct samsung_pin_bank_type { - u8 fld_width[PINCFG_TYPE_NUM]; - u8 reg_offset[PINCFG_TYPE_NUM]; -}; - -/** - * struct samsung_pin_bank: represent a controller pin-bank. - * @type: type of the bank (register offsets and bitfield widths) - * @pctl_offset: starting offset of the pin-bank registers. - * @pin_base: starting pin number of the bank. - * @nr_pins: number of pins included in this bank. - * @eint_func: function to set in CON register to configure pin as EINT. - * @eint_type: type of the external interrupt supported by the bank. - * @eint_mask: bit mask of pins which support EINT function. - * @name: name to be prefixed for each pin in this pin bank. - * @of_node: OF node of the bank. - * @drvdata: link to controller driver data - * @irq_domain: IRQ domain of the bank. - * @gpio_chip: GPIO chip of the bank. - * @grange: linux gpio pin range supported by this bank. - * @slock: spinlock protecting bank registers - * @pm_save: saved register values during suspend - */ -struct samsung_pin_bank { - struct samsung_pin_bank_type *type; - u32 pctl_offset; - u32 pin_base; - u8 nr_pins; - u8 eint_func; - enum eint_type eint_type; - u32 eint_mask; - u32 eint_offset; - char *name; - void *soc_priv; - struct device_node *of_node; - struct samsung_pinctrl_drv_data *drvdata; - struct irq_domain *irq_domain; - struct gpio_chip gpio_chip; - struct pinctrl_gpio_range grange; - spinlock_t slock; - - u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ -}; - -/** - * struct samsung_pin_ctrl: represent a pin controller. - * @pin_banks: list of pin banks included in this controller. - * @nr_banks: number of pin banks. - * @base: starting system wide pin number. - * @nr_pins: number of pins supported by the controller. - * @eint_gpio_init: platform specific callback to setup the external gpio - * interrupts for the controller. - * @eint_wkup_init: platform specific callback to setup the external wakeup - * interrupts for the controller. - * @label: for debug information. - */ -struct samsung_pin_ctrl { - struct samsung_pin_bank *pin_banks; - u32 nr_banks; - - u32 base; - u32 nr_pins; - - int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); - int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); - void (*suspend)(struct samsung_pinctrl_drv_data *); - void (*resume)(struct samsung_pinctrl_drv_data *); - - char *label; -}; - -/** - * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. - * @node: global list node - * @virt_base: register base address of the controller. - * @dev: device instance representing the controller. - * @irq: interrpt number used by the controller to notify gpio interrupts. - * @ctrl: pin controller instance managed by the driver. - * @pctl: pin controller descriptor registered with the pinctrl subsystem. - * @pctl_dev: cookie representing pinctrl device instance. - * @pin_groups: list of pin groups available to the driver. - * @nr_groups: number of such pin groups. - * @pmx_functions: list of pin functions available to the driver. - * @nr_function: number of such pin functions. - */ -struct samsung_pinctrl_drv_data { - struct list_head node; - void __iomem *virt_base; - struct device *dev; - int irq; - - struct samsung_pin_ctrl *ctrl; - struct pinctrl_desc pctl; - struct pinctrl_dev *pctl_dev; - - const struct samsung_pin_group *pin_groups; - unsigned int nr_groups; - const struct samsung_pmx_func *pmx_functions; - unsigned int nr_functions; -}; - -/** - * struct samsung_pin_group: represent group of pins of a pinmux function. - * @name: name of the pin group, used to lookup the group. - * @pins: the pins included in this group. - * @num_pins: number of pins included in this group. - * @func: the function number to be programmed when selected. - */ -struct samsung_pin_group { - const char *name; - const unsigned int *pins; - u8 num_pins; - u8 func; -}; - -/** - * struct samsung_pmx_func: represent a pin function. - * @name: name of the pin function, used to lookup the function. - * @groups: one or more names of pin groups that provide this function. - * @num_groups: number of groups included in @groups. - */ -struct samsung_pmx_func { - const char *name; - const char **groups; - u8 num_groups; - u32 val; -}; - -/* list of all exported SoC specific data */ -extern struct samsung_pin_ctrl exynos3250_pin_ctrl[]; -extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; -extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; -extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; -extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; -extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; -extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; -extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; -extern struct samsung_pin_ctrl s3c2416_pin_ctrl[]; -extern struct samsung_pin_ctrl s3c2440_pin_ctrl[]; -extern struct samsung_pin_ctrl s3c2450_pin_ctrl[]; -extern struct samsung_pin_ctrl s5pv210_pin_ctrl[]; - -#endif /* __PINCTRL_SAMSUNG_H */ diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig new file mode 100644 index 000000000000..d0461cd5d707 --- /dev/null +++ b/drivers/pinctrl/samsung/Kconfig @@ -0,0 +1,28 @@ +# +# Samsung Pin control drivers +# +config PINCTRL_SAMSUNG + bool + select PINMUX + select PINCONF + +config PINCTRL_EXYNOS + bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440" + depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210) + select PINCTRL_SAMSUNG + +config PINCTRL_EXYNOS5440 + bool "Samsung EXYNOS5440 SoC pinctrl driver" + depends on SOC_EXYNOS5440 + select PINMUX + select PINCONF + +config PINCTRL_S3C24XX + bool "Samsung S3C24XX SoC pinctrl driver" + depends on ARCH_S3C24XX + select PINCTRL_SAMSUNG + +config PINCTRL_S3C64XX + bool "Samsung S3C64XX SoC pinctrl driver" + depends on ARCH_S3C64XX + select PINCTRL_SAMSUNG diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile new file mode 100644 index 000000000000..70160c059edd --- /dev/null +++ b/drivers/pinctrl/samsung/Makefile @@ -0,0 +1,7 @@ +# Samsung pin control drivers + +obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o +obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o +obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o +obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o +obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c new file mode 100644 index 000000000000..003bfd874a61 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -0,0 +1,1123 @@ +/* + * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * Author: Thomas Abraham + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file contains the Samsung Exynos specific information required by the + * the Samsung pinctrl/gpiolib driver. It also includes the implementation of + * external gpio and wakeup interrupt support. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-samsung.h" +#include "pinctrl-exynos.h" + +struct exynos_irq_chip { + struct irq_chip chip; + + u32 eint_con; + u32 eint_mask; + u32 eint_pend; +}; + +static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) +{ + return container_of(chip, struct exynos_irq_chip, chip); +} + +static struct samsung_pin_bank_type bank_type_off = { + .fld_width = { 4, 1, 2, 2, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +static struct samsung_pin_bank_type bank_type_alive = { + .fld_width = { 4, 1, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* list of external wakeup controllers supported */ +static const struct of_device_id exynos_wkup_irq_ids[] = { + { .compatible = "samsung,exynos4210-wakeup-eint", }, + { } +}; + +static void exynos_irq_mask(struct irq_data *irqd) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; + unsigned long mask; + unsigned long flags; + + spin_lock_irqsave(&bank->slock, flags); + + mask = readl(d->virt_base + reg_mask); + mask |= 1 << irqd->hwirq; + writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +static void exynos_irq_ack(struct irq_data *irqd) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; + + writel(1 << irqd->hwirq, d->virt_base + reg_pend); +} + +static void exynos_irq_unmask(struct irq_data *irqd) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; + unsigned long mask; + unsigned long flags; + + /* + * Ack level interrupts right before unmask + * + * If we don't do this we'll get a double-interrupt. Level triggered + * interrupts must not fire an interrupt if the level is not + * _currently_ active, even if it was active while the interrupt was + * masked. + */ + if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) + exynos_irq_ack(irqd); + + spin_lock_irqsave(&bank->slock, flags); + + mask = readl(d->virt_base + reg_mask); + mask &= ~(1 << irqd->hwirq); + writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pin_bank_type *bank_type = bank->type; + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned int pin = irqd->hwirq; + unsigned int shift = EXYNOS_EINT_CON_LEN * pin; + unsigned int con, trig_type; + unsigned long reg_con = our_chip->eint_con + bank->eint_offset; + unsigned long flags; + unsigned int mask; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + trig_type = EXYNOS_EINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + trig_type = EXYNOS_EINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + trig_type = EXYNOS_EINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + trig_type = EXYNOS_EINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + trig_type = EXYNOS_EINT_LEVEL_LOW; + break; + default: + pr_err("unsupported external interrupt type\n"); + return -EINVAL; + } + + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(irqd->irq, handle_edge_irq); + else + __irq_set_handler_locked(irqd->irq, handle_level_irq); + + con = readl(d->virt_base + reg_con); + con &= ~(EXYNOS_EINT_CON_MASK << shift); + con |= trig_type << shift; + writel(con, d->virt_base + reg_con); + + reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; + shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + spin_lock_irqsave(&bank->slock, flags); + + con = readl(d->virt_base + reg_con); + con &= ~(mask << shift); + con |= EXYNOS_EINT_FUNC << shift; + writel(con, d->virt_base + reg_con); + + spin_unlock_irqrestore(&bank->slock, flags); + + return 0; +} + +/* + * irq_chip for gpio interrupts. + */ +static struct exynos_irq_chip exynos_gpio_irq_chip = { + .chip = { + .name = "exynos_gpio_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + }, + .eint_con = EXYNOS_GPIO_ECON_OFFSET, + .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, +}; + +static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct samsung_pin_bank *b = h->host_data; + + irq_set_chip_data(virq, b); + irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip, + handle_level_irq); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +/* + * irq domain callbacks for external gpio interrupt controller. + */ +static const struct irq_domain_ops exynos_gpio_irqd_ops = { + .map = exynos_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) +{ + struct samsung_pinctrl_drv_data *d = data; + struct samsung_pin_ctrl *ctrl = d->ctrl; + struct samsung_pin_bank *bank = ctrl->pin_banks; + unsigned int svc, group, pin, virq; + + svc = readl(d->virt_base + EXYNOS_SVC_OFFSET); + group = EXYNOS_SVC_GROUP(svc); + pin = svc & EXYNOS_SVC_NUM_MASK; + + if (!group) + return IRQ_HANDLED; + bank += (group - 1); + + virq = irq_linear_revmap(bank->irq_domain, pin); + if (!virq) + return IRQ_NONE; + generic_handle_irq(virq); + return IRQ_HANDLED; +} + +struct exynos_eint_gpio_save { + u32 eint_con; + u32 eint_fltcon0; + u32 eint_fltcon1; +}; + +/* + * exynos_eint_gpio_init() - setup handling of external gpio interrupts. + * @d: driver data of samsung pinctrl driver. + */ +static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) +{ + struct samsung_pin_bank *bank; + struct device *dev = d->dev; + int ret; + int i; + + if (!d->irq) { + dev_err(dev, "irq number not available\n"); + return -EINVAL; + } + + ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, + 0, dev_name(dev), d); + if (ret) { + dev_err(dev, "irq request failed\n"); + return -ENXIO; + } + + bank = d->ctrl->pin_banks; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + bank->irq_domain = irq_domain_add_linear(bank->of_node, + bank->nr_pins, &exynos_gpio_irqd_ops, bank); + if (!bank->irq_domain) { + dev_err(dev, "gpio irq domain add failed\n"); + ret = -ENXIO; + goto err_domains; + } + + bank->soc_priv = devm_kzalloc(d->dev, + sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); + if (!bank->soc_priv) { + irq_domain_remove(bank->irq_domain); + ret = -ENOMEM; + goto err_domains; + } + } + + return 0; + +err_domains: + for (--i, --bank; i >= 0; --i, --bank) { + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + irq_domain_remove(bank->irq_domain); + } + + return ret; +} + +static u32 exynos_eint_wake_mask = 0xffffffff; + +u32 exynos_get_eint_wake_mask(void) +{ + return exynos_eint_wake_mask; +} + +static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); + + pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); + + if (!on) + exynos_eint_wake_mask |= bit; + else + exynos_eint_wake_mask &= ~bit; + + return 0; +} + +/* + * irq_chip for wakeup interrupts + */ +static struct exynos_irq_chip exynos_wkup_irq_chip = { + .chip = { + .name = "exynos_wkup_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, + }, + .eint_con = EXYNOS_WKUP_ECON_OFFSET, + .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, +}; + +/* interrupt handler for wakeup interrupts 0..15 */ +static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) +{ + struct exynos_weint_data *eintd = irq_get_handler_data(irq); + struct samsung_pin_bank *bank = eintd->bank; + struct irq_chip *chip = irq_get_chip(irq); + int eint_irq; + + chained_irq_enter(chip, desc); + chip->irq_mask(&desc->irq_data); + + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + + eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); + generic_handle_irq(eint_irq); + chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); +} + +static inline void exynos_irq_demux_eint(unsigned long pend, + struct irq_domain *domain) +{ + unsigned int irq; + + while (pend) { + irq = fls(pend) - 1; + generic_handle_irq(irq_find_mapping(domain, irq)); + pend &= ~(1 << irq); + } +} + +/* interrupt handler for wakeup interrupt 16 */ +static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); + struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; + unsigned long pend; + unsigned long mask; + int i; + + chained_irq_enter(chip, desc); + + for (i = 0; i < eintd->nr_banks; ++i) { + struct samsung_pin_bank *b = eintd->banks[i]; + pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET + + b->eint_offset); + mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET + + b->eint_offset); + exynos_irq_demux_eint(pend & ~mask, b->irq_domain); + } + + chained_irq_exit(chip, desc); +} + +static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip, + handle_level_irq); + irq_set_chip_data(virq, h->host_data); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +/* + * irq domain callbacks for external wakeup interrupt controller. + */ +static const struct irq_domain_ops exynos_wkup_irqd_ops = { + .map = exynos_wkup_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +/* + * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. + * @d: driver data of samsung pinctrl driver. + */ +static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) +{ + struct device *dev = d->dev; + struct device_node *wkup_np = NULL; + struct device_node *np; + struct samsung_pin_bank *bank; + struct exynos_weint_data *weint_data; + struct exynos_muxed_weint_data *muxed_data; + unsigned int muxed_banks = 0; + unsigned int i; + int idx, irq; + + for_each_child_of_node(dev->of_node, np) { + if (of_match_node(exynos_wkup_irq_ids, np)) { + wkup_np = np; + break; + } + } + if (!wkup_np) + return -ENODEV; + + bank = d->ctrl->pin_banks; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + if (bank->eint_type != EINT_TYPE_WKUP) + continue; + + bank->irq_domain = irq_domain_add_linear(bank->of_node, + bank->nr_pins, &exynos_wkup_irqd_ops, bank); + if (!bank->irq_domain) { + dev_err(dev, "wkup irq domain add failed\n"); + return -ENXIO; + } + + if (!of_find_property(bank->of_node, "interrupts", NULL)) { + bank->eint_type = EINT_TYPE_WKUP_MUX; + ++muxed_banks; + continue; + } + + weint_data = devm_kzalloc(dev, bank->nr_pins + * sizeof(*weint_data), GFP_KERNEL); + if (!weint_data) { + dev_err(dev, "could not allocate memory for weint_data\n"); + return -ENOMEM; + } + + for (idx = 0; idx < bank->nr_pins; ++idx) { + irq = irq_of_parse_and_map(bank->of_node, idx); + if (!irq) { + dev_err(dev, "irq number for eint-%s-%d not found\n", + bank->name, idx); + continue; + } + weint_data[idx].irq = idx; + weint_data[idx].bank = bank; + irq_set_handler_data(irq, &weint_data[idx]); + irq_set_chained_handler(irq, exynos_irq_eint0_15); + } + } + + if (!muxed_banks) + return 0; + + irq = irq_of_parse_and_map(wkup_np, 0); + if (!irq) { + dev_err(dev, "irq number for muxed EINTs not found\n"); + return 0; + } + + muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) + + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); + if (!muxed_data) { + dev_err(dev, "could not allocate memory for muxed_data\n"); + return -ENOMEM; + } + + irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); + irq_set_handler_data(irq, muxed_data); + + bank = d->ctrl->pin_banks; + idx = 0; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + if (bank->eint_type != EINT_TYPE_WKUP_MUX) + continue; + + muxed_data->banks[idx++] = bank; + } + muxed_data->nr_banks = muxed_banks; + + return 0; +} + +static void exynos_pinctrl_suspend_bank( + struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = drvdata->virt_base; + + save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + + pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); + pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); +} + +static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + struct samsung_pin_bank *bank = ctrl->pin_banks; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) + if (bank->eint_type == EINT_TYPE_GPIO) + exynos_pinctrl_suspend_bank(drvdata, bank); +} + +static void exynos_pinctrl_resume_bank( + struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = drvdata->virt_base; + + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset), save->eint_fltcon0); + pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4), save->eint_fltcon1); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); +} + +static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + struct samsung_pin_bank *bank = ctrl->pin_banks; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) + if (bank->eint_type == EINT_TYPE_GPIO) + exynos_pinctrl_resume_bank(drvdata, bank); +} + +/* pin banks of s5pv210 pin-controller */ +static struct samsung_pin_bank s5pv210_pin_bank[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), + EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), + EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), + EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), + EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), + EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), + EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), + EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), + EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), + EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), + EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), + EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), + EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), + EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), +}; + +struct samsung_pin_ctrl s5pv210_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = s5pv210_pin_bank, + .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "s5pv210-gpio-ctrl0", + }, +}; + +/* pin banks of exynos3250 pin-controller 0 */ +static struct samsung_pin_bank exynos3250_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), +}; + +/* pin banks of exynos3250 pin-controller 1 */ +static struct samsung_pin_bank exynos3250_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), + EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* + * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes + * two gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos3250_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos3250_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos3250-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos3250_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos3250-gpio-ctrl1", + }, +}; + +/* pin banks of exynos4210 pin-controller 0 */ +static struct samsung_pin_bank exynos4210_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), + EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), + EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), + EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), +}; + +/* pin banks of exynos4210 pin-controller 1 */ +static struct samsung_pin_bank exynos4210_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), + EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos4210 pin-controller 2 */ +static struct samsung_pin_bank exynos4210_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), +}; + +/* + * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos4210_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos4210-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos4210_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos4210-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos4210_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), + .label = "exynos4210-gpio-ctrl2", + }, +}; + +/* pin banks of exynos4x12 pin-controller 0 */ +static struct samsung_pin_bank exynos4x12_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), + EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), + EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), +}; + +/* pin banks of exynos4x12 pin-controller 1 */ +static struct samsung_pin_bank exynos4x12_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), + EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), + EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos4x12 pin-controller 2 */ +static struct samsung_pin_bank exynos4x12_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* pin banks of exynos4x12 pin-controller 3 */ +static struct samsung_pin_bank exynos4x12_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), +}; + +/* + * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos4x12_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos4x12-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos4x12_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos4x12-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos4x12_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos4x12-gpio-ctrl2", + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos4x12_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos4x12-gpio-ctrl3", + }, +}; + +/* pin banks of exynos5250 pin-controller 0 */ +static struct samsung_pin_bank exynos5250_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), + EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), + EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), + EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5250 pin-controller 1 */ +static struct samsung_pin_bank exynos5250_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), +}; + +/* pin banks of exynos5250 pin-controller 2 */ +static struct samsung_pin_bank exynos5250_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5250 pin-controller 3 */ +static struct samsung_pin_bank exynos5250_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5250_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5250-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5250_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5250-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5250_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5250-gpio-ctrl2", + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5250_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5250-gpio-ctrl3", + }, +}; + +/* pin banks of exynos5260 pin-controller 0 */ +static struct samsung_pin_bank exynos5260_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5260 pin-controller 1 */ +static struct samsung_pin_bank exynos5260_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), +}; + +/* pin banks of exynos5260 pin-controller 2 */ +static struct samsung_pin_bank exynos5260_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5260_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5260-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5260_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5260_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl2", + }, +}; + +/* pin banks of exynos5420 pin-controller 0 */ +static struct samsung_pin_bank exynos5420_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5420 pin-controller 1 */ +static struct samsung_pin_bank exynos5420_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), + EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), +}; + +/* pin banks of exynos5420 pin-controller 2 */ +static struct samsung_pin_bank exynos5420_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), +}; + +/* pin banks of exynos5420 pin-controller 3 */ +static struct samsung_pin_bank exynos5420_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), +}; + +/* pin banks of exynos5420 pin-controller 4 */ +static struct samsung_pin_bank exynos5420_pin_banks4[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5420_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5420-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5420_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5420_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl2", + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5420_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl3", + }, { + /* pin-controller instance 4 data */ + .pin_banks = exynos5420_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl4", + }, +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h new file mode 100644 index 000000000000..3c91c357792f --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -0,0 +1,99 @@ +/* + * Exynos specific definitions for Samsung pinctrl and gpiolib driver. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * This file contains the Exynos specific definitions for the Samsung + * pinctrl/gpiolib interface drivers. + * + * Author: Thomas Abraham + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/* External GPIO and wakeup interrupt related definitions */ +#define EXYNOS_GPIO_ECON_OFFSET 0x700 +#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 +#define EXYNOS_GPIO_EMASK_OFFSET 0x900 +#define EXYNOS_GPIO_EPEND_OFFSET 0xA00 +#define EXYNOS_WKUP_ECON_OFFSET 0xE00 +#define EXYNOS_WKUP_EMASK_OFFSET 0xF00 +#define EXYNOS_WKUP_EPEND_OFFSET 0xF40 +#define EXYNOS_SVC_OFFSET 0xB08 +#define EXYNOS_EINT_FUNC 0xF + +/* helpers to access interrupt service register */ +#define EXYNOS_SVC_GROUP_SHIFT 3 +#define EXYNOS_SVC_GROUP_MASK 0x1f +#define EXYNOS_SVC_NUM_MASK 7 +#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ + EXYNOS_SVC_GROUP_MASK) + +/* Exynos specific external interrupt trigger types */ +#define EXYNOS_EINT_LEVEL_LOW 0 +#define EXYNOS_EINT_LEVEL_HIGH 1 +#define EXYNOS_EINT_EDGE_FALLING 2 +#define EXYNOS_EINT_EDGE_RISING 3 +#define EXYNOS_EINT_EDGE_BOTH 4 +#define EXYNOS_EINT_CON_MASK 0xF +#define EXYNOS_EINT_CON_LEN 4 + +#define EXYNOS_EINT_MAX_PER_BANK 8 +#define EXYNOS_EINT_NR_WKUP_EINT + +#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + +/** + * struct exynos_weint_data: irq specific data for all the wakeup interrupts + * generated by the external wakeup interrupt controller. + * @irq: interrupt number within the domain. + * @bank: bank responsible for this interrupt + */ +struct exynos_weint_data { + unsigned int irq; + struct samsung_pin_bank *bank; +}; + +/** + * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts + * generated by the external wakeup interrupt controller. + * @nr_banks: count of banks being part of the mux + * @banks: array of banks being part of the mux + */ +struct exynos_muxed_weint_data { + unsigned int nr_banks; + struct samsung_pin_bank *banks[]; +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c new file mode 100644 index 000000000000..603da2f9dd95 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -0,0 +1,1061 @@ +/* + * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../core.h" + +/* EXYNOS5440 GPIO and Pinctrl register offsets */ +#define GPIO_MUX 0x00 +#define GPIO_IE 0x04 +#define GPIO_INT 0x08 +#define GPIO_TYPE 0x0C +#define GPIO_VAL 0x10 +#define GPIO_OE 0x14 +#define GPIO_IN 0x18 +#define GPIO_PE 0x1C +#define GPIO_PS 0x20 +#define GPIO_SR 0x24 +#define GPIO_DS0 0x28 +#define GPIO_DS1 0x2C + +#define EXYNOS5440_MAX_PINS 23 +#define EXYNOS5440_MAX_GPIO_INT 8 +#define PIN_NAME_LENGTH 10 + +#define GROUP_SUFFIX "-grp" +#define GSUFFIX_LEN sizeof(GROUP_SUFFIX) +#define FUNCTION_SUFFIX "-mux" +#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX) + +/* + * pin configuration type and its value are packed together into a 16-bits. + * The upper 8-bits represent the configuration type and the lower 8-bits + * hold the value of the configuration type. + */ +#define PINCFG_TYPE_MASK 0xFF +#define PINCFG_VALUE_SHIFT 8 +#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) +#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) +#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) +#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ + PINCFG_VALUE_SHIFT) + +/** + * enum pincfg_type - possible pin configuration types supported. + * @PINCFG_TYPE_PUD: Pull up/down configuration. + * @PINCFG_TYPE_DRV: Drive strength configuration. + * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration. + * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration. + */ +enum pincfg_type { + PINCFG_TYPE_PUD, + PINCFG_TYPE_DRV, + PINCFG_TYPE_SKEW_RATE, + PINCFG_TYPE_INPUT_TYPE +}; + +/** + * struct exynos5440_pin_group: represent group of pins for pincfg setting. + * @name: name of the pin group, used to lookup the group. + * @pins: the pins included in this group. + * @num_pins: number of pins included in this group. + */ +struct exynos5440_pin_group { + const char *name; + const unsigned int *pins; + u8 num_pins; +}; + +/** + * struct exynos5440_pmx_func: represent a pin function. + * @name: name of the pin function, used to lookup the function. + * @groups: one or more names of pin groups that provide this function. + * @num_groups: number of groups included in @groups. + * @function: the function number to be programmed when selected. + */ +struct exynos5440_pmx_func { + const char *name; + const char **groups; + u8 num_groups; + unsigned long function; +}; + +/** + * struct exynos5440_pinctrl_priv_data: driver's private runtime data. + * @reg_base: ioremapped based address of the register space. + * @gc: gpio chip registered with gpiolib. + * @pin_groups: list of pin groups parsed from device tree. + * @nr_groups: number of pin groups available. + * @pmx_functions: list of pin functions parsed from device tree. + * @nr_functions: number of pin functions available. + */ +struct exynos5440_pinctrl_priv_data { + void __iomem *reg_base; + struct gpio_chip *gc; + struct irq_domain *irq_domain; + + const struct exynos5440_pin_group *pin_groups; + unsigned int nr_groups; + const struct exynos5440_pmx_func *pmx_functions; + unsigned int nr_functions; +}; + +/** + * struct exynos5440_gpio_intr_data: private data for gpio interrupts. + * @priv: driver's private runtime data. + * @gpio_int: gpio interrupt number. + */ +struct exynos5440_gpio_intr_data { + struct exynos5440_pinctrl_priv_data *priv; + unsigned int gpio_int; +}; + +/* list of all possible config options supported */ +static struct pin_config { + char *prop_cfg; + unsigned int cfg_type; +} pcfgs[] = { + { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD }, + { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV }, + { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE }, + { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE }, +}; + +/* check if the selector is a valid pin group selector */ +static int exynos5440_get_group_count(struct pinctrl_dev *pctldev) +{ + struct exynos5440_pinctrl_priv_data *priv; + + priv = pinctrl_dev_get_drvdata(pctldev); + return priv->nr_groups; +} + +/* return the name of the group selected by the group selector */ +static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct exynos5440_pinctrl_priv_data *priv; + + priv = pinctrl_dev_get_drvdata(pctldev); + return priv->pin_groups[selector].name; +} + +/* return the pin numbers associated with the specified group */ +static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, const unsigned **pins, unsigned *num_pins) +{ + struct exynos5440_pinctrl_priv_data *priv; + + priv = pinctrl_dev_get_drvdata(pctldev); + *pins = priv->pin_groups[selector].pins; + *num_pins = priv->pin_groups[selector].num_pins; + return 0; +} + +/* create pinctrl_map entries by parsing device tree nodes */ +static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, struct pinctrl_map **maps, + unsigned *nmaps) +{ + struct device *dev = pctldev->dev; + struct pinctrl_map *map; + unsigned long *cfg = NULL; + char *gname, *fname; + int cfg_cnt = 0, map_cnt = 0, idx = 0; + + /* count the number of config options specfied in the node */ + for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) + if (of_find_property(np, pcfgs[idx].prop_cfg, NULL)) + cfg_cnt++; + + /* + * Find out the number of map entries to create. All the config options + * can be accomadated into a single config map entry. + */ + if (cfg_cnt) + map_cnt = 1; + if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) + map_cnt++; + if (!map_cnt) { + dev_err(dev, "node %s does not have either config or function " + "configurations\n", np->name); + return -EINVAL; + } + + /* Allocate memory for pin-map entries */ + map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); + if (!map) { + dev_err(dev, "could not alloc memory for pin-maps\n"); + return -ENOMEM; + } + *nmaps = 0; + + /* + * Allocate memory for pin group name. The pin group name is derived + * from the node name from which these map entries are be created. + */ + gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); + if (!gname) { + dev_err(dev, "failed to alloc memory for group name\n"); + goto free_map; + } + snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX); + + /* + * don't have config options? then skip over to creating function + * map entries. + */ + if (!cfg_cnt) + goto skip_cfgs; + + /* Allocate memory for config entries */ + cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); + if (!cfg) { + dev_err(dev, "failed to alloc memory for configs\n"); + goto free_gname; + } + + /* Prepare a list of config settings */ + for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { + u32 value; + if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value)) + cfg[cfg_cnt++] = + PINCFG_PACK(pcfgs[idx].cfg_type, value); + } + + /* create the config map entry */ + map[*nmaps].data.configs.group_or_pin = gname; + map[*nmaps].data.configs.configs = cfg; + map[*nmaps].data.configs.num_configs = cfg_cnt; + map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + *nmaps += 1; + +skip_cfgs: + /* create the function map entry */ + if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { + fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); + if (!fname) { + dev_err(dev, "failed to alloc memory for func name\n"); + goto free_cfg; + } + snprintf(fname, strlen(np->name) + 4, "%s%s", np->name, + FUNCTION_SUFFIX); + + map[*nmaps].data.mux.group = gname; + map[*nmaps].data.mux.function = fname; + map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + *nmaps += 1; + } + + *maps = map; + return 0; + +free_cfg: + kfree(cfg); +free_gname: + kfree(gname); +free_map: + kfree(map); + return -ENOMEM; +} + +/* free the memory allocated to hold the pin-map table */ +static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int idx; + + for (idx = 0; idx < num_maps; idx++) { + if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) { + kfree(map[idx].data.mux.function); + if (!idx) + kfree(map[idx].data.mux.group); + } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) { + kfree(map[idx].data.configs.configs); + if (!idx) + kfree(map[idx].data.configs.group_or_pin); + } + }; + + kfree(map); +} + +/* list of pinctrl callbacks for the pinctrl core */ +static const struct pinctrl_ops exynos5440_pctrl_ops = { + .get_groups_count = exynos5440_get_group_count, + .get_group_name = exynos5440_get_group_name, + .get_group_pins = exynos5440_get_group_pins, + .dt_node_to_map = exynos5440_dt_node_to_map, + .dt_free_map = exynos5440_dt_free_map, +}; + +/* check if the selector is a valid pin function selector */ +static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct exynos5440_pinctrl_priv_data *priv; + + priv = pinctrl_dev_get_drvdata(pctldev); + return priv->nr_functions; +} + +/* return the name of the pin function specified */ +static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct exynos5440_pinctrl_priv_data *priv; + + priv = pinctrl_dev_get_drvdata(pctldev); + return priv->pmx_functions[selector].name; +} + +/* return the groups associated for the specified function selector */ +static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **groups, + unsigned * const num_groups) +{ + struct exynos5440_pinctrl_priv_data *priv; + + priv = pinctrl_dev_get_drvdata(pctldev); + *groups = priv->pmx_functions[selector].groups; + *num_groups = priv->pmx_functions[selector].num_groups; + return 0; +} + +/* enable or disable a pinmux function */ +static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group, bool enable) +{ + struct exynos5440_pinctrl_priv_data *priv; + void __iomem *base; + u32 function; + u32 data; + + priv = pinctrl_dev_get_drvdata(pctldev); + base = priv->reg_base; + function = priv->pmx_functions[selector].function; + + data = readl(base + GPIO_MUX); + if (enable) + data |= (1 << function); + else + data &= ~(1 << function); + writel(data, base + GPIO_MUX); +} + +/* enable a specified pinmux by writing to registers */ +static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + exynos5440_pinmux_setup(pctldev, selector, group, true); + return 0; +} + +/* + * The calls to gpio_direction_output() and gpio_direction_input() + * leads to this function call (via the pinctrl_gpio_direction_{input|output}() + * function called from the gpiolib interface). + */ +static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned offset, bool input) +{ + return 0; +} + +/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ +static const struct pinmux_ops exynos5440_pinmux_ops = { + .get_functions_count = exynos5440_get_functions_count, + .get_function_name = exynos5440_pinmux_get_fname, + .get_function_groups = exynos5440_pinmux_get_groups, + .enable = exynos5440_pinmux_enable, + .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, +}; + +/* set the pin config settings for a specified pin */ +static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, + unsigned num_configs) +{ + struct exynos5440_pinctrl_priv_data *priv; + void __iomem *base; + enum pincfg_type cfg_type; + u32 cfg_value; + u32 data; + int i; + + priv = pinctrl_dev_get_drvdata(pctldev); + base = priv->reg_base; + + for (i = 0; i < num_configs; i++) { + cfg_type = PINCFG_UNPACK_TYPE(configs[i]); + cfg_value = PINCFG_UNPACK_VALUE(configs[i]); + + switch (cfg_type) { + case PINCFG_TYPE_PUD: + /* first set pull enable/disable bit */ + data = readl(base + GPIO_PE); + data &= ~(1 << pin); + if (cfg_value) + data |= (1 << pin); + writel(data, base + GPIO_PE); + + /* then set pull up/down bit */ + data = readl(base + GPIO_PS); + data &= ~(1 << pin); + if (cfg_value == 2) + data |= (1 << pin); + writel(data, base + GPIO_PS); + break; + + case PINCFG_TYPE_DRV: + /* set the first bit of the drive strength */ + data = readl(base + GPIO_DS0); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_DS0); + cfg_value >>= 1; + + /* set the second bit of the driver strength */ + data = readl(base + GPIO_DS1); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_DS1); + break; + case PINCFG_TYPE_SKEW_RATE: + data = readl(base + GPIO_SR); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_SR); + break; + case PINCFG_TYPE_INPUT_TYPE: + data = readl(base + GPIO_TYPE); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_TYPE); + break; + default: + WARN_ON(1); + return -EINVAL; + } + } /* for each config */ + + return 0; +} + +/* get the pin config settings for a specified pin */ +static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct exynos5440_pinctrl_priv_data *priv; + void __iomem *base; + enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); + u32 data; + + priv = pinctrl_dev_get_drvdata(pctldev); + base = priv->reg_base; + + switch (cfg_type) { + case PINCFG_TYPE_PUD: + data = readl(base + GPIO_PE); + data = (data >> pin) & 1; + if (!data) + *config = 0; + else + *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1; + break; + case PINCFG_TYPE_DRV: + data = readl(base + GPIO_DS0); + data = (data >> pin) & 1; + *config = data; + data = readl(base + GPIO_DS1); + data = (data >> pin) & 1; + *config |= (data << 1); + break; + case PINCFG_TYPE_SKEW_RATE: + data = readl(base + GPIO_SR); + *config = (data >> pin) & 1; + break; + case PINCFG_TYPE_INPUT_TYPE: + data = readl(base + GPIO_TYPE); + *config = (data >> pin) & 1; + break; + default: + WARN_ON(1); + return -EINVAL; + } + + return 0; +} + +/* set the pin config settings for a specified pin group */ +static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *configs, + unsigned num_configs) +{ + struct exynos5440_pinctrl_priv_data *priv; + const unsigned int *pins; + unsigned int cnt; + + priv = pinctrl_dev_get_drvdata(pctldev); + pins = priv->pin_groups[group].pins; + + for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++) + exynos5440_pinconf_set(pctldev, pins[cnt], configs, + num_configs); + + return 0; +} + +/* get the pin config settings for a specified pin group */ +static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + struct exynos5440_pinctrl_priv_data *priv; + const unsigned int *pins; + + priv = pinctrl_dev_get_drvdata(pctldev); + pins = priv->pin_groups[group].pins; + exynos5440_pinconf_get(pctldev, pins[0], config); + return 0; +} + +/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ +static const struct pinconf_ops exynos5440_pinconf_ops = { + .pin_config_get = exynos5440_pinconf_get, + .pin_config_set = exynos5440_pinconf_set, + .pin_config_group_get = exynos5440_pinconf_group_get, + .pin_config_group_set = exynos5440_pinconf_group_set, +}; + +/* gpiolib gpio_set callback function */ +static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value) +{ + struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); + void __iomem *base = priv->reg_base; + u32 data; + + data = readl(base + GPIO_VAL); + data &= ~(1 << offset); + if (value) + data |= 1 << offset; + writel(data, base + GPIO_VAL); +} + +/* gpiolib gpio_get callback function */ +static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset) +{ + struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); + void __iomem *base = priv->reg_base; + u32 data; + + data = readl(base + GPIO_IN); + data >>= offset; + data &= 1; + return data; +} + +/* gpiolib gpio_direction_input callback function */ +static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +{ + struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); + void __iomem *base = priv->reg_base; + u32 data; + + /* first disable the data output enable on this pin */ + data = readl(base + GPIO_OE); + data &= ~(1 << offset); + writel(data, base + GPIO_OE); + + /* now enable input on this pin */ + data = readl(base + GPIO_IE); + data |= 1 << offset; + writel(data, base + GPIO_IE); + return 0; +} + +/* gpiolib gpio_direction_output callback function */ +static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset, + int value) +{ + struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); + void __iomem *base = priv->reg_base; + u32 data; + + exynos5440_gpio_set(gc, offset, value); + + /* first disable the data input enable on this pin */ + data = readl(base + GPIO_IE); + data &= ~(1 << offset); + writel(data, base + GPIO_IE); + + /* now enable output on this pin */ + data = readl(base + GPIO_OE); + data |= 1 << offset; + writel(data, base + GPIO_OE); + return 0; +} + +/* gpiolib gpio_to_irq callback function */ +static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); + unsigned int virq; + + if (offset < 16 || offset > 23) + return -ENXIO; + + if (!priv->irq_domain) + return -ENXIO; + + virq = irq_create_mapping(priv->irq_domain, offset - 16); + return virq ? : -ENXIO; +} + +/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */ +static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev, + struct device_node *cfg_np, unsigned int **pin_list, + unsigned int *npins) +{ + struct device *dev = &pdev->dev; + struct property *prop; + + prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL); + if (!prop) + return -ENOENT; + + *npins = prop->length / sizeof(unsigned long); + if (!*npins) { + dev_err(dev, "invalid pin list in %s node", cfg_np->name); + return -EINVAL; + } + + *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); + if (!*pin_list) { + dev_err(dev, "failed to allocate memory for pin list\n"); + return -ENOMEM; + } + + return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins", + *pin_list, *npins); +} + +/* + * Parse the information about all the available pin groups and pin functions + * from device node of the pin-controller. + */ +static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, + struct exynos5440_pinctrl_priv_data *priv) +{ + struct device *dev = &pdev->dev; + struct device_node *dev_np = dev->of_node; + struct device_node *cfg_np; + struct exynos5440_pin_group *groups, *grp; + struct exynos5440_pmx_func *functions, *func; + unsigned *pin_list; + unsigned int npins, grp_cnt, func_idx = 0; + char *gname, *fname; + int ret; + + grp_cnt = of_get_child_count(dev_np); + if (!grp_cnt) + return -EINVAL; + + groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); + if (!groups) { + dev_err(dev, "failed allocate memory for ping group list\n"); + return -EINVAL; + } + grp = groups; + + functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); + if (!functions) { + dev_err(dev, "failed to allocate memory for function list\n"); + return -EINVAL; + } + func = functions; + + /* + * Iterate over all the child nodes of the pin controller node + * and create pin groups and pin function lists. + */ + for_each_child_of_node(dev_np, cfg_np) { + u32 function; + + ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np, + &pin_list, &npins); + if (ret) { + gname = NULL; + goto skip_to_pin_function; + } + + /* derive pin group name from the node name */ + gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, + GFP_KERNEL); + if (!gname) { + dev_err(dev, "failed to alloc memory for group name\n"); + return -ENOMEM; + } + snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, + GROUP_SUFFIX); + + grp->name = gname; + grp->pins = pin_list; + grp->num_pins = npins; + grp++; + +skip_to_pin_function: + ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function", + &function); + if (ret) + continue; + + /* derive function name from the node name */ + fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, + GFP_KERNEL); + if (!fname) { + dev_err(dev, "failed to alloc memory for func name\n"); + return -ENOMEM; + } + snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, + FUNCTION_SUFFIX); + + func->name = fname; + func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); + if (!func->groups) { + dev_err(dev, "failed to alloc memory for group list " + "in pin function"); + return -ENOMEM; + } + func->groups[0] = gname; + func->num_groups = gname ? 1 : 0; + func->function = function; + func++; + func_idx++; + } + + priv->pin_groups = groups; + priv->nr_groups = grp_cnt; + priv->pmx_functions = functions; + priv->nr_functions = func_idx; + return 0; +} + +/* register the pinctrl interface with the pinctrl subsystem */ +static int exynos5440_pinctrl_register(struct platform_device *pdev, + struct exynos5440_pinctrl_priv_data *priv) +{ + struct device *dev = &pdev->dev; + struct pinctrl_desc *ctrldesc; + struct pinctrl_dev *pctl_dev; + struct pinctrl_pin_desc *pindesc, *pdesc; + struct pinctrl_gpio_range grange; + char *pin_names; + int pin, ret; + + ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL); + if (!ctrldesc) { + dev_err(dev, "could not allocate memory for pinctrl desc\n"); + return -ENOMEM; + } + + ctrldesc->name = "exynos5440-pinctrl"; + ctrldesc->owner = THIS_MODULE; + ctrldesc->pctlops = &exynos5440_pctrl_ops; + ctrldesc->pmxops = &exynos5440_pinmux_ops; + ctrldesc->confops = &exynos5440_pinconf_ops; + + pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * + EXYNOS5440_MAX_PINS, GFP_KERNEL); + if (!pindesc) { + dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); + return -ENOMEM; + } + ctrldesc->pins = pindesc; + ctrldesc->npins = EXYNOS5440_MAX_PINS; + + /* dynamically populate the pin number and pin name for pindesc */ + for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) + pdesc->number = pin; + + /* + * allocate space for storing the dynamically generated names for all + * the pins which belong to this pin-controller. + */ + pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * + ctrldesc->npins, GFP_KERNEL); + if (!pin_names) { + dev_err(&pdev->dev, "mem alloc for pin names failed\n"); + return -ENOMEM; + } + + /* for each pin, set the name of the pin */ + for (pin = 0; pin < ctrldesc->npins; pin++) { + snprintf(pin_names, 6, "gpio%02d", pin); + pdesc = pindesc + pin; + pdesc->name = pin_names; + pin_names += PIN_NAME_LENGTH; + } + + ret = exynos5440_pinctrl_parse_dt(pdev, priv); + if (ret) + return ret; + + pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv); + if (!pctl_dev) { + dev_err(&pdev->dev, "could not register pinctrl driver\n"); + return -EINVAL; + } + + grange.name = "exynos5440-pctrl-gpio-range"; + grange.id = 0; + grange.base = 0; + grange.npins = EXYNOS5440_MAX_PINS; + grange.gc = priv->gc; + pinctrl_add_gpio_range(pctl_dev, &grange); + return 0; +} + +/* register the gpiolib interface with the gpiolib subsystem */ +static int exynos5440_gpiolib_register(struct platform_device *pdev, + struct exynos5440_pinctrl_priv_data *priv) +{ + struct gpio_chip *gc; + int ret; + + gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); + if (!gc) { + dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n"); + return -ENOMEM; + } + + priv->gc = gc; + gc->base = 0; + gc->ngpio = EXYNOS5440_MAX_PINS; + gc->dev = &pdev->dev; + gc->set = exynos5440_gpio_set; + gc->get = exynos5440_gpio_get; + gc->direction_input = exynos5440_gpio_direction_input; + gc->direction_output = exynos5440_gpio_direction_output; + gc->to_irq = exynos5440_gpio_to_irq; + gc->label = "gpiolib-exynos5440"; + gc->owner = THIS_MODULE; + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "failed to register gpio_chip %s, error " + "code: %d\n", gc->label, ret); + return ret; + } + + return 0; +} + +/* unregister the gpiolib interface with the gpiolib subsystem */ +static int exynos5440_gpiolib_unregister(struct platform_device *pdev, + struct exynos5440_pinctrl_priv_data *priv) +{ + int ret = gpiochip_remove(priv->gc); + if (ret) { + dev_err(&pdev->dev, "gpio chip remove failed\n"); + return ret; + } + return 0; +} + +static void exynos5440_gpio_irq_unmask(struct irq_data *irqd) +{ + struct exynos5440_pinctrl_priv_data *d; + unsigned long gpio_int; + + d = irq_data_get_irq_chip_data(irqd); + gpio_int = readl(d->reg_base + GPIO_INT); + gpio_int |= 1 << irqd->hwirq; + writel(gpio_int, d->reg_base + GPIO_INT); +} + +static void exynos5440_gpio_irq_mask(struct irq_data *irqd) +{ + struct exynos5440_pinctrl_priv_data *d; + unsigned long gpio_int; + + d = irq_data_get_irq_chip_data(irqd); + gpio_int = readl(d->reg_base + GPIO_INT); + gpio_int &= ~(1 << irqd->hwirq); + writel(gpio_int, d->reg_base + GPIO_INT); +} + +/* irq_chip for gpio interrupts */ +static struct irq_chip exynos5440_gpio_irq_chip = { + .name = "exynos5440_gpio_irq_chip", + .irq_unmask = exynos5440_gpio_irq_unmask, + .irq_mask = exynos5440_gpio_irq_mask, +}; + +/* interrupt handler for GPIO interrupts 0..7 */ +static irqreturn_t exynos5440_gpio_irq(int irq, void *data) +{ + struct exynos5440_gpio_intr_data *intd = data; + struct exynos5440_pinctrl_priv_data *d = intd->priv; + int virq; + + virq = irq_linear_revmap(d->irq_domain, intd->gpio_int); + if (!virq) + return IRQ_NONE; + generic_handle_irq(virq); + return IRQ_HANDLED; +} + +static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct exynos5440_pinctrl_priv_data *d = h->host_data; + + irq_set_chip_data(virq, d); + irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip, + handle_level_irq); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +/* irq domain callbacks for gpio interrupt controller */ +static const struct irq_domain_ops exynos5440_gpio_irqd_ops = { + .map = exynos5440_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +/* setup handling of gpio interrupts */ +static int exynos5440_gpio_irq_init(struct platform_device *pdev, + struct exynos5440_pinctrl_priv_data *priv) +{ + struct device *dev = &pdev->dev; + struct exynos5440_gpio_intr_data *intd; + int i, irq, ret; + + intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT, + GFP_KERNEL); + if (!intd) { + dev_err(dev, "failed to allocate memory for gpio intr data\n"); + return -ENOMEM; + } + + for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) { + irq = irq_of_parse_and_map(dev->of_node, i); + if (irq <= 0) { + dev_err(dev, "irq parsing failed\n"); + return -EINVAL; + } + + intd->gpio_int = i; + intd->priv = priv; + ret = devm_request_irq(dev, irq, exynos5440_gpio_irq, + 0, dev_name(dev), intd++); + if (ret) { + dev_err(dev, "irq request failed\n"); + return -ENXIO; + } + } + + priv->irq_domain = irq_domain_add_linear(dev->of_node, + EXYNOS5440_MAX_GPIO_INT, + &exynos5440_gpio_irqd_ops, priv); + if (!priv->irq_domain) { + dev_err(dev, "failed to create irq domain\n"); + return -ENXIO; + } + + return 0; +} + +static int exynos5440_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct exynos5440_pinctrl_priv_data *priv; + struct resource *res; + int ret; + + if (!dev->of_node) { + dev_err(dev, "device tree node not found\n"); + return -ENODEV; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(dev, "could not allocate memory for private data\n"); + return -ENOMEM; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->reg_base)) + return PTR_ERR(priv->reg_base); + + ret = exynos5440_gpiolib_register(pdev, priv); + if (ret) + return ret; + + ret = exynos5440_pinctrl_register(pdev, priv); + if (ret) { + exynos5440_gpiolib_unregister(pdev, priv); + return ret; + } + + ret = exynos5440_gpio_irq_init(pdev, priv); + if (ret) { + dev_err(dev, "failed to setup gpio interrupts\n"); + return ret; + } + + platform_set_drvdata(pdev, priv); + dev_info(dev, "EXYNOS5440 pinctrl driver registered\n"); + return 0; +} + +static const struct of_device_id exynos5440_pinctrl_dt_match[] = { + { .compatible = "samsung,exynos5440-pinctrl" }, + {}, +}; +MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match); + +static struct platform_driver exynos5440_pinctrl_driver = { + .probe = exynos5440_pinctrl_probe, + .driver = { + .name = "exynos5440-pinctrl", + .owner = THIS_MODULE, + .of_match_table = exynos5440_pinctrl_dt_match, + }, +}; + +static int __init exynos5440_pinctrl_drv_register(void) +{ + return platform_driver_register(&exynos5440_pinctrl_driver); +} +postcore_initcall(exynos5440_pinctrl_drv_register); + +static void __exit exynos5440_pinctrl_drv_unregister(void) +{ + platform_driver_unregister(&exynos5440_pinctrl_driver); +} +module_exit(exynos5440_pinctrl_drv_unregister); + +MODULE_AUTHOR("Thomas Abraham "); +MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c new file mode 100644 index 000000000000..ad3eaad17001 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c @@ -0,0 +1,651 @@ +/* + * S3C24XX specific support for Samsung pinctrl/gpiolib driver. + * + * Copyright (c) 2013 Heiko Stuebner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file contains the SamsungS3C24XX specific information required by the + * Samsung pinctrl/gpiolib driver. It also includes the implementation of + * external gpio and wakeup interrupt support. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-samsung.h" + +#define NUM_EINT 24 +#define NUM_EINT_IRQ 6 +#define EINT_MAX_PER_GROUP 8 + +#define EINTPEND_REG 0xa8 +#define EINTMASK_REG 0xa4 + +#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP)) +#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88) +#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4) + +#define EINT_LEVEL_LOW 0 +#define EINT_LEVEL_HIGH 1 +#define EINT_EDGE_FALLING 2 +#define EINT_EDGE_RISING 4 +#define EINT_EDGE_BOTH 6 +#define EINT_MASK 0xf + +static struct samsung_pin_bank_type bank_type_1bit = { + .fld_width = { 1, 1, }, + .reg_offset = { 0x00, 0x04, }, +}; + +static struct samsung_pin_bank_type bank_type_2bit = { + .fld_width = { 2, 1, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, }, +}; + +#define PIN_BANK_A(pins, reg, id) \ + { \ + .type = &bank_type_1bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT(pins, reg, id) \ + { \ + .type = &bank_type_2bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\ + { \ + .type = &bank_type_2bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 2, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +/** + * struct s3c24xx_eint_data: EINT common data + * @drvdata: pin controller driver data + * @domains: IRQ domains of particular EINT interrupts + * @parents: mapped parent irqs in the main interrupt controller + */ +struct s3c24xx_eint_data { + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *domains[NUM_EINT]; + int parents[NUM_EINT_IRQ]; +}; + +/** + * struct s3c24xx_eint_domain_data: per irq-domain data + * @bank: pin bank related to the domain + * @eint_data: common data + * eint0_3_parent_only: live eints 0-3 only in the main intc + */ +struct s3c24xx_eint_domain_data { + struct samsung_pin_bank *bank; + struct s3c24xx_eint_data *eint_data; + bool eint0_3_parent_only; +}; + +static int s3c24xx_eint_get_trigger(unsigned int type) +{ + switch (type) { + case IRQ_TYPE_EDGE_RISING: + return EINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + return EINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + return EINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + return EINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + return EINT_LEVEL_LOW; + break; + default: + return -EINVAL; + } +} + +static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type) +{ + /* Edge- and level-triggered interrupts need different handlers */ + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(irq, handle_edge_irq); + else + __irq_set_handler_locked(irq, handle_level_irq); +} + +static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, + struct samsung_pin_bank *bank, int pin) +{ + struct samsung_pin_bank_type *bank_type = bank->type; + unsigned long flags; + void __iomem *reg; + u8 shift; + u32 mask; + u32 val; + + /* Make sure that pin is configured as interrupt */ + reg = d->virt_base + bank->pctl_offset; + shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + spin_lock_irqsave(&bank->slock, flags); + + val = readl(reg); + val &= ~(mask << shift); + val |= bank->eint_func << shift; + writel(val, reg); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + int index = bank->eint_offset + data->hwirq; + void __iomem *reg; + int trigger; + u8 shift; + u32 val; + + trigger = s3c24xx_eint_get_trigger(type); + if (trigger < 0) { + dev_err(d->dev, "unsupported external interrupt type\n"); + return -EINVAL; + } + + s3c24xx_eint_set_handler(data->irq, type); + + /* Set up interrupt trigger */ + reg = d->virt_base + EINT_REG(index); + shift = EINT_OFFS(index); + + val = readl(reg); + val &= ~(EINT_MASK << shift); + val |= trigger << shift; + writel(val, reg); + + s3c24xx_eint_set_function(d, bank, data->hwirq); + + return 0; +} + +/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */ + +static void s3c2410_eint0_3_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_ack(irq_get_irq_data(parent_irq)); +} + +static void s3c2410_eint0_3_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_mask(irq_get_irq_data(parent_irq)); +} + +static void s3c2410_eint0_3_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_unmask(irq_get_irq_data(parent_irq)); +} + +static struct irq_chip s3c2410_eint0_3_chip = { + .name = "s3c2410-eint0_3", + .irq_ack = s3c2410_eint0_3_ack, + .irq_mask = s3c2410_eint0_3_mask, + .irq_unmask = s3c2410_eint0_3_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_desc_get_irq_data(desc); + struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + unsigned int virq; + + /* the first 4 eints have a simple 1 to 1 mapping */ + virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); + /* Something must be really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); +} + +/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */ + +static void s3c2412_eint0_3_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + + unsigned long bitval = 1UL << data->hwirq; + writel(bitval, d->virt_base + EINTPEND_REG); +} + +static void s3c2412_eint0_3_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask |= (1UL << data->hwirq); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static void s3c2412_eint0_3_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask &= ~(1UL << data->hwirq); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static struct irq_chip s3c2412_eint0_3_chip = { + .name = "s3c2412-eint0_3", + .irq_ack = s3c2412_eint0_3_ack, + .irq_mask = s3c2412_eint0_3_mask, + .irq_unmask = s3c2412_eint0_3_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct irq_data *data = irq_desc_get_irq_data(desc); + struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + unsigned int virq; + + chained_irq_enter(chip, desc); + + /* the first 4 eints have a simple 1 to 1 mapping */ + virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); + /* Something must be really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); + + chained_irq_exit(chip, desc); +} + +/* Handling of all other eints */ + +static void s3c24xx_eint_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + + writel(1UL << index, d->virt_base + EINTPEND_REG); +} + +static void s3c24xx_eint_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask |= (1UL << index); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static void s3c24xx_eint_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask &= ~(1UL << index); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static struct irq_chip s3c24xx_eint_chip = { + .name = "s3c-eint", + .irq_ack = s3c24xx_eint_ack, + .irq_mask = s3c24xx_eint_mask, + .irq_unmask = s3c24xx_eint_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, + u32 offset, u32 range) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct s3c24xx_eint_data *data = irq_get_handler_data(irq); + struct samsung_pinctrl_drv_data *d = data->drvdata; + unsigned int pend, mask; + + chained_irq_enter(chip, desc); + + pend = readl(d->virt_base + EINTPEND_REG); + mask = readl(d->virt_base + EINTMASK_REG); + + pend &= ~mask; + pend &= range; + + while (pend) { + unsigned int virq; + + irq = __ffs(pend); + pend &= ~(1 << irq); + virq = irq_linear_revmap(data->domains[irq], irq - offset); + /* Something is really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); + } + + chained_irq_exit(chip, desc); +} + +static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc) +{ + s3c24xx_demux_eint(irq, desc, 0, 0xf0); +} + +static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc) +{ + s3c24xx_demux_eint(irq, desc, 8, 0xffff00); +} + +static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = { + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c24xx_demux_eint4_7, + s3c24xx_demux_eint8_23, +}; + +static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = { + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c24xx_demux_eint4_7, + s3c24xx_demux_eint8_23, +}; + +static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c24xx_eint_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) + return -EINVAL; + + if (hw <= 3) { + if (ddata->eint0_3_parent_only) + irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip, + handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip, + handle_edge_irq); + } else { + irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, + handle_edge_irq); + } + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +static const struct irq_domain_ops s3c24xx_gpf_irq_ops = { + .map = s3c24xx_gpf_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c24xx_eint_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) + return -EINVAL; + + irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq); + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +static const struct irq_domain_ops s3c24xx_gpg_irq_ops = { + .map = s3c24xx_gpg_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static const struct of_device_id s3c24xx_eint_irq_ids[] = { + { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 }, + { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 }, + { } +}; + +static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d) +{ + struct device *dev = d->dev; + const struct of_device_id *match; + struct device_node *eint_np = NULL; + struct device_node *np; + struct samsung_pin_bank *bank; + struct s3c24xx_eint_data *eint_data; + const struct irq_domain_ops *ops; + unsigned int i; + bool eint0_3_parent_only; + irq_flow_handler_t *handlers; + + for_each_child_of_node(dev->of_node, np) { + match = of_match_node(s3c24xx_eint_irq_ids, np); + if (match) { + eint_np = np; + eint0_3_parent_only = (bool)match->data; + break; + } + } + if (!eint_np) + return -ENODEV; + + eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL); + if (!eint_data) + return -ENOMEM; + + eint_data->drvdata = d; + + handlers = eint0_3_parent_only ? s3c2410_eint_handlers + : s3c2412_eint_handlers; + for (i = 0; i < NUM_EINT_IRQ; ++i) { + unsigned int irq; + + irq = irq_of_parse_and_map(eint_np, i); + if (!irq) { + dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); + return -ENXIO; + } + + eint_data->parents[i] = irq; + irq_set_chained_handler(irq, handlers[i]); + irq_set_handler_data(irq, eint_data); + } + + bank = d->ctrl->pin_banks; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + struct s3c24xx_eint_domain_data *ddata; + unsigned int mask; + unsigned int irq; + unsigned int pin; + + if (bank->eint_type != EINT_TYPE_WKUP) + continue; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->bank = bank; + ddata->eint_data = eint_data; + ddata->eint0_3_parent_only = eint0_3_parent_only; + + ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops + : &s3c24xx_gpg_irq_ops; + + bank->irq_domain = irq_domain_add_linear(bank->of_node, + bank->nr_pins, ops, ddata); + if (!bank->irq_domain) { + dev_err(dev, "wkup irq domain add failed\n"); + return -ENXIO; + } + + irq = bank->eint_offset; + mask = bank->eint_mask; + for (pin = 0; mask; ++pin, mask >>= 1) { + if (irq >= NUM_EINT) + break; + if (!(mask & 1)) + continue; + eint_data->domains[irq] = bank->irq_domain; + ++irq; + } + } + + return 0; +} + +static struct samsung_pin_bank s3c2412_pin_banks[] = { + PIN_BANK_A(23, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(11, 0x070, "gph"), + PIN_BANK_2BIT(13, 0x080, "gpj"), +}; + +struct samsung_pin_ctrl s3c2412_pin_ctrl[] = { + { + .pin_banks = s3c2412_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2412-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2416_pin_banks[] = { + PIN_BANK_A(27, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00), + PIN_BANK_2BIT(15, 0x070, "gph"), + PIN_BANK_2BIT(16, 0x0e0, "gpk"), + PIN_BANK_2BIT(14, 0x0f0, "gpl"), + PIN_BANK_2BIT(2, 0x100, "gpm"), +}; + +struct samsung_pin_ctrl s3c2416_pin_ctrl[] = { + { + .pin_banks = s3c2416_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2416-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2440_pin_banks[] = { + PIN_BANK_A(25, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(11, 0x070, "gph"), + PIN_BANK_2BIT(13, 0x0d0, "gpj"), +}; + +struct samsung_pin_ctrl s3c2440_pin_ctrl[] = { + { + .pin_banks = s3c2440_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2440-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2450_pin_banks[] = { + PIN_BANK_A(28, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(15, 0x070, "gph"), + PIN_BANK_2BIT(16, 0x0d0, "gpj"), + PIN_BANK_2BIT(16, 0x0e0, "gpk"), + PIN_BANK_2BIT(15, 0x0f0, "gpl"), + PIN_BANK_2BIT(2, 0x100, "gpm"), +}; + +struct samsung_pin_ctrl s3c2450_pin_ctrl[] = { + { + .pin_banks = s3c2450_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2450-GPIO", + }, +}; diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c new file mode 100644 index 000000000000..89143c903000 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c @@ -0,0 +1,816 @@ +/* + * S3C64xx specific support for pinctrl-samsung driver. + * + * Copyright (c) 2013 Tomasz Figa + * + * Based on pinctrl-exynos.c, please see the file for original copyrights. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file contains the Samsung S3C64xx specific information required by the + * the Samsung pinctrl/gpiolib driver. It also includes the implementation of + * external gpio and wakeup interrupt support. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-samsung.h" + +#define NUM_EINT0 28 +#define NUM_EINT0_IRQ 4 +#define EINT_MAX_PER_REG 16 +#define EINT_MAX_PER_GROUP 16 + +/* External GPIO and wakeup interrupt related definitions */ +#define SVC_GROUP_SHIFT 4 +#define SVC_GROUP_MASK 0xf +#define SVC_NUM_MASK 0xf +#define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \ + SVC_GROUP_MASK) + +#define EINT12CON_REG 0x200 +#define EINT12MASK_REG 0x240 +#define EINT12PEND_REG 0x260 + +#define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP)) +#define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP) +#define EINT_REG(g) (4 * ((g) / 2)) + +#define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i))) +#define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i))) +#define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i))) + +#define SERVICE_REG 0x284 +#define SERVICEPEND_REG 0x288 + +#define EINT0CON0_REG 0x900 +#define EINT0MASK_REG 0x920 +#define EINT0PEND_REG 0x924 + +/* S3C64xx specific external interrupt trigger types */ +#define EINT_LEVEL_LOW 0 +#define EINT_LEVEL_HIGH 1 +#define EINT_EDGE_FALLING 2 +#define EINT_EDGE_RISING 4 +#define EINT_EDGE_BOTH 6 +#define EINT_CON_MASK 0xF +#define EINT_CON_LEN 4 + +static struct samsung_pin_bank_type bank_type_4bit_off = { + .fld_width = { 4, 1, 2, 0, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, +}; + +static struct samsung_pin_bank_type bank_type_4bit_alive = { + .fld_width = { 4, 1, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, }, +}; + +static struct samsung_pin_bank_type bank_type_4bit2_off = { + .fld_width = { 4, 1, 2, 0, 2, 2, }, + .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, }, +}; + +static struct samsung_pin_bank_type bank_type_4bit2_alive = { + .fld_width = { 4, 1, 2, }, + .reg_offset = { 0x00, 0x08, 0x0c, }, +}; + +static struct samsung_pin_bank_type bank_type_2bit_off = { + .fld_width = { 2, 1, 2, 0, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, +}; + +static struct samsung_pin_bank_type bank_type_2bit_alive = { + .fld_width = { 2, 1, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, }, +}; + +#define PIN_BANK_4BIT(pins, reg, id) \ + { \ + .type = &bank_type_4bit_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \ + { \ + .type = &bank_type_4bit_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_func = 7, \ + .eint_mask = (1 << (pins)) - 1, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \ + { \ + .type = &bank_type_4bit_alive,\ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 3, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \ + { \ + .type = &bank_type_4bit2_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_func = 7, \ + .eint_mask = (1 << (pins)) - 1, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \ + { \ + .type = &bank_type_4bit2_alive,\ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 3, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \ + { \ + .type = &bank_type_4bit2_alive,\ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT(pins, reg, id) \ + { \ + .type = &bank_type_2bit_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \ + { \ + .type = &bank_type_2bit_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_func = 3, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \ + { \ + .type = &bank_type_2bit_alive,\ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 2, \ + .eint_mask = (1 << (pins)) - 1, \ + .eint_offset = eoffs, \ + .name = id \ + } + +/** + * struct s3c64xx_eint0_data: EINT0 common data + * @drvdata: pin controller driver data + * @domains: IRQ domains of particular EINT0 interrupts + * @pins: pin offsets inside of banks of particular EINT0 interrupts + */ +struct s3c64xx_eint0_data { + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *domains[NUM_EINT0]; + u8 pins[NUM_EINT0]; +}; + +/** + * struct s3c64xx_eint0_domain_data: EINT0 per-domain data + * @bank: pin bank related to the domain + * @eints: EINT0 interrupts related to the domain + */ +struct s3c64xx_eint0_domain_data { + struct samsung_pin_bank *bank; + u8 eints[]; +}; + +/** + * struct s3c64xx_eint_gpio_data: GPIO EINT data + * @drvdata: pin controller driver data + * @domains: array of domains related to EINT interrupt groups + */ +struct s3c64xx_eint_gpio_data { + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *domains[]; +}; + +/* + * Common functions for S3C64xx EINT configuration + */ + +static int s3c64xx_irq_get_trigger(unsigned int type) +{ + int trigger; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + trigger = EINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + trigger = EINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + trigger = EINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + trigger = EINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + trigger = EINT_LEVEL_LOW; + break; + default: + return -EINVAL; + } + + return trigger; +} + +static void s3c64xx_irq_set_handler(unsigned int irq, unsigned int type) +{ + /* Edge- and level-triggered interrupts need different handlers */ + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(irq, handle_edge_irq); + else + __irq_set_handler_locked(irq, handle_level_irq); +} + +static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, + struct samsung_pin_bank *bank, int pin) +{ + struct samsung_pin_bank_type *bank_type = bank->type; + unsigned long flags; + void __iomem *reg; + u8 shift; + u32 mask; + u32 val; + + /* Make sure that pin is configured as interrupt */ + reg = d->virt_base + bank->pctl_offset; + shift = pin; + if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) { + /* 4-bit bank type with 2 con regs */ + reg += 4; + shift -= 8; + } + + shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + spin_lock_irqsave(&bank->slock, flags); + + val = readl(reg); + val &= ~(mask << shift); + val |= bank->eint_func << shift; + writel(val, reg); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +/* + * Functions for EINT GPIO configuration (EINT groups 1-9) + */ + +static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; + void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset); + u32 val; + + val = readl(reg); + if (mask) + val |= 1 << index; + else + val &= ~(1 << index); + writel(val, reg); +} + +static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd) +{ + s3c64xx_gpio_irq_set_mask(irqd, false); +} + +static void s3c64xx_gpio_irq_mask(struct irq_data *irqd) +{ + s3c64xx_gpio_irq_set_mask(irqd, true); +} + +static void s3c64xx_gpio_irq_ack(struct irq_data *irqd) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; + void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset); + + writel(1 << index, reg); +} + +static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + void __iomem *reg; + int trigger; + u8 shift; + u32 val; + + trigger = s3c64xx_irq_get_trigger(type); + if (trigger < 0) { + pr_err("unsupported external interrupt type\n"); + return -EINVAL; + } + + s3c64xx_irq_set_handler(irqd->irq, type); + + /* Set up interrupt trigger */ + reg = d->virt_base + EINTCON_REG(bank->eint_offset); + shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq; + shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */ + + val = readl(reg); + val &= ~(EINT_CON_MASK << shift); + val |= trigger << shift; + writel(val, reg); + + s3c64xx_irq_set_function(d, bank, irqd->hwirq); + + return 0; +} + +/* + * irq_chip for gpio interrupts. + */ +static struct irq_chip s3c64xx_gpio_irq_chip = { + .name = "GPIO", + .irq_unmask = s3c64xx_gpio_irq_unmask, + .irq_mask = s3c64xx_gpio_irq_mask, + .irq_ack = s3c64xx_gpio_irq_ack, + .irq_set_type = s3c64xx_gpio_irq_set_type, +}; + +static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct samsung_pin_bank *bank = h->host_data; + + if (!(bank->eint_mask & (1 << hw))) + return -EINVAL; + + irq_set_chip_and_handler(virq, + &s3c64xx_gpio_irq_chip, handle_level_irq); + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + + return 0; +} + +/* + * irq domain callbacks for external gpio interrupt controller. + */ +static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = { + .map = s3c64xx_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static void s3c64xx_eint_gpio_irq(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct s3c64xx_eint_gpio_data *data = irq_get_handler_data(irq); + struct samsung_pinctrl_drv_data *drvdata = data->drvdata; + + chained_irq_enter(chip, desc); + + do { + unsigned int svc; + unsigned int group; + unsigned int pin; + unsigned int virq; + + svc = readl(drvdata->virt_base + SERVICE_REG); + group = SVC_GROUP(svc); + pin = svc & SVC_NUM_MASK; + + if (!group) + break; + + /* Group 1 is used for two pin banks */ + if (group == 1) { + if (pin < 8) + group = 0; + else + pin -= 8; + } + + virq = irq_linear_revmap(data->domains[group], pin); + /* + * Something must be really wrong if an unmapped EINT + * was unmasked... + */ + BUG_ON(!virq); + + generic_handle_irq(virq); + } while (1); + + chained_irq_exit(chip, desc); +} + +/** + * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts. + * @d: driver data of samsung pinctrl driver. + */ +static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d) +{ + struct s3c64xx_eint_gpio_data *data; + struct samsung_pin_bank *bank; + struct device *dev = d->dev; + unsigned int nr_domains; + unsigned int i; + + if (!d->irq) { + dev_err(dev, "irq number not available\n"); + return -EINVAL; + } + + nr_domains = 0; + bank = d->ctrl->pin_banks; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + unsigned int nr_eints; + unsigned int mask; + + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + + mask = bank->eint_mask; + nr_eints = fls(mask); + + bank->irq_domain = irq_domain_add_linear(bank->of_node, + nr_eints, &s3c64xx_gpio_irqd_ops, bank); + if (!bank->irq_domain) { + dev_err(dev, "gpio irq domain add failed\n"); + return -ENXIO; + } + + ++nr_domains; + } + + data = devm_kzalloc(dev, sizeof(*data) + + nr_domains * sizeof(*data->domains), GFP_KERNEL); + if (!data) { + dev_err(dev, "failed to allocate handler data\n"); + return -ENOMEM; + } + data->drvdata = d; + + bank = d->ctrl->pin_banks; + nr_domains = 0; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + + data->domains[nr_domains++] = bank->irq_domain; + } + + irq_set_chained_handler(d->irq, s3c64xx_eint_gpio_irq); + irq_set_handler_data(d->irq, data); + + return 0; +} + +/* + * Functions for configuration of EINT0 wake-up interrupts + */ + +static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask) +{ + struct s3c64xx_eint0_domain_data *ddata = + irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; + u32 val; + + val = readl(d->virt_base + EINT0MASK_REG); + if (mask) + val |= 1 << ddata->eints[irqd->hwirq]; + else + val &= ~(1 << ddata->eints[irqd->hwirq]); + writel(val, d->virt_base + EINT0MASK_REG); +} + +static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd) +{ + s3c64xx_eint0_irq_set_mask(irqd, false); +} + +static void s3c64xx_eint0_irq_mask(struct irq_data *irqd) +{ + s3c64xx_eint0_irq_set_mask(irqd, true); +} + +static void s3c64xx_eint0_irq_ack(struct irq_data *irqd) +{ + struct s3c64xx_eint0_domain_data *ddata = + irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; + + writel(1 << ddata->eints[irqd->hwirq], + d->virt_base + EINT0PEND_REG); +} + +static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct s3c64xx_eint0_domain_data *ddata = + irq_data_get_irq_chip_data(irqd); + struct samsung_pin_bank *bank = ddata->bank; + struct samsung_pinctrl_drv_data *d = bank->drvdata; + void __iomem *reg; + int trigger; + u8 shift; + u32 val; + + trigger = s3c64xx_irq_get_trigger(type); + if (trigger < 0) { + pr_err("unsupported external interrupt type\n"); + return -EINVAL; + } + + s3c64xx_irq_set_handler(irqd->irq, type); + + /* Set up interrupt trigger */ + reg = d->virt_base + EINT0CON0_REG; + shift = ddata->eints[irqd->hwirq]; + if (shift >= EINT_MAX_PER_REG) { + reg += 4; + shift -= EINT_MAX_PER_REG; + } + shift = EINT_CON_LEN * (shift / 2); + + val = readl(reg); + val &= ~(EINT_CON_MASK << shift); + val |= trigger << shift; + writel(val, reg); + + s3c64xx_irq_set_function(d, bank, irqd->hwirq); + + return 0; +} + +/* + * irq_chip for wakeup interrupts + */ +static struct irq_chip s3c64xx_eint0_irq_chip = { + .name = "EINT0", + .irq_unmask = s3c64xx_eint0_irq_unmask, + .irq_mask = s3c64xx_eint0_irq_mask, + .irq_ack = s3c64xx_eint0_irq_ack, + .irq_set_type = s3c64xx_eint0_irq_set_type, +}; + +static inline void s3c64xx_irq_demux_eint(unsigned int irq, + struct irq_desc *desc, u32 range) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct s3c64xx_eint0_data *data = irq_get_handler_data(irq); + struct samsung_pinctrl_drv_data *drvdata = data->drvdata; + unsigned int pend, mask; + + chained_irq_enter(chip, desc); + + pend = readl(drvdata->virt_base + EINT0PEND_REG); + mask = readl(drvdata->virt_base + EINT0MASK_REG); + + pend = pend & range & ~mask; + pend &= range; + + while (pend) { + unsigned int virq; + + irq = fls(pend) - 1; + pend &= ~(1 << irq); + + virq = irq_linear_revmap(data->domains[irq], data->pins[irq]); + /* + * Something must be really wrong if an unmapped EINT + * was unmasked... + */ + BUG_ON(!virq); + + generic_handle_irq(virq); + } + + chained_irq_exit(chip, desc); +} + +static void s3c64xx_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + s3c64xx_irq_demux_eint(irq, desc, 0xf); +} + +static void s3c64xx_demux_eint4_11(unsigned int irq, struct irq_desc *desc) +{ + s3c64xx_irq_demux_eint(irq, desc, 0xff0); +} + +static void s3c64xx_demux_eint12_19(unsigned int irq, struct irq_desc *desc) +{ + s3c64xx_irq_demux_eint(irq, desc, 0xff000); +} + +static void s3c64xx_demux_eint20_27(unsigned int irq, struct irq_desc *desc) +{ + s3c64xx_irq_demux_eint(irq, desc, 0xff00000); +} + +static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = { + s3c64xx_demux_eint0_3, + s3c64xx_demux_eint4_11, + s3c64xx_demux_eint12_19, + s3c64xx_demux_eint20_27, +}; + +static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c64xx_eint0_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << hw))) + return -EINVAL; + + irq_set_chip_and_handler(virq, + &s3c64xx_eint0_irq_chip, handle_level_irq); + irq_set_chip_data(virq, ddata); + set_irq_flags(virq, IRQF_VALID); + + return 0; +} + +/* + * irq domain callbacks for external wakeup interrupt controller. + */ +static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = { + .map = s3c64xx_eint0_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +/* list of external wakeup controllers supported */ +static const struct of_device_id s3c64xx_eint0_irq_ids[] = { + { .compatible = "samsung,s3c64xx-wakeup-eint", }, + { } +}; + +/** + * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts. + * @d: driver data of samsung pinctrl driver. + */ +static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d) +{ + struct device *dev = d->dev; + struct device_node *eint0_np = NULL; + struct device_node *np; + struct samsung_pin_bank *bank; + struct s3c64xx_eint0_data *data; + unsigned int i; + + for_each_child_of_node(dev->of_node, np) { + if (of_match_node(s3c64xx_eint0_irq_ids, np)) { + eint0_np = np; + break; + } + } + if (!eint0_np) + return -ENODEV; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) { + dev_err(dev, "could not allocate memory for wkup eint data\n"); + return -ENOMEM; + } + data->drvdata = d; + + for (i = 0; i < NUM_EINT0_IRQ; ++i) { + unsigned int irq; + + irq = irq_of_parse_and_map(eint0_np, i); + if (!irq) { + dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); + return -ENXIO; + } + + irq_set_chained_handler(irq, s3c64xx_eint0_handlers[i]); + irq_set_handler_data(irq, data); + } + + bank = d->ctrl->pin_banks; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + struct s3c64xx_eint0_domain_data *ddata; + unsigned int nr_eints; + unsigned int mask; + unsigned int irq; + unsigned int pin; + + if (bank->eint_type != EINT_TYPE_WKUP) + continue; + + mask = bank->eint_mask; + nr_eints = fls(mask); + + ddata = devm_kzalloc(dev, + sizeof(*ddata) + nr_eints, GFP_KERNEL); + if (!ddata) { + dev_err(dev, "failed to allocate domain data\n"); + return -ENOMEM; + } + ddata->bank = bank; + + bank->irq_domain = irq_domain_add_linear(bank->of_node, + nr_eints, &s3c64xx_eint0_irqd_ops, ddata); + if (!bank->irq_domain) { + dev_err(dev, "wkup irq domain add failed\n"); + return -ENXIO; + } + + irq = bank->eint_offset; + mask = bank->eint_mask; + for (pin = 0; mask; ++pin, mask >>= 1) { + if (!(mask & 1)) + continue; + data->domains[irq] = bank->irq_domain; + data->pins[irq] = pin; + ddata->eints[pin] = irq; + ++irq; + } + } + + return 0; +} + +/* pin banks of s3c64xx pin-controller 0 */ +static struct samsung_pin_bank s3c64xx_pin_banks0[] = { + PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0), + PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8), + PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16), + PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32), + PIN_BANK_4BIT(5, 0x080, "gpe"), + PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff), + PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64), + PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80), + PIN_BANK_2BIT(16, 0x100, "gpi"), + PIN_BANK_2BIT(12, 0x120, "gpj"), + PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"), + PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00), + PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f), + PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0), + PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff), + PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff), + PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff), +}; + +/* + * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes + * one gpio/pin-mux/pinconfig controller. + */ +struct samsung_pin_ctrl s3c64xx_pin_ctrl[] = { + { + /* pin-controller instance 1 data */ + .pin_banks = s3c64xx_pin_banks0, + .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0), + .eint_gpio_init = s3c64xx_eint_gpio_init, + .eint_wkup_init = s3c64xx_eint_eint0_init, + .label = "S3C64xx-GPIO", + }, +}; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c new file mode 100644 index 000000000000..b07406da333c --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -0,0 +1,1285 @@ +/* + * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * Author: Thomas Abraham + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This driver implements the Samsung pinctrl driver. It supports setting up of + * pinmux and pinconf configurations. The gpiolib interface is also included. + * External interrupt (gpio and wakeup) support are not included in this driver + * but provides extensions to which platform specific implementation of the gpio + * and wakeup interrupts can be hooked to. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "pinctrl-samsung.h" + +#define GROUP_SUFFIX "-grp" +#define GSUFFIX_LEN sizeof(GROUP_SUFFIX) +#define FUNCTION_SUFFIX "-mux" +#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX) + +/* list of all possible config options supported */ +static struct pin_config { + const char *property; + enum pincfg_type param; +} cfg_params[] = { + { "samsung,pin-pud", PINCFG_TYPE_PUD }, + { "samsung,pin-drv", PINCFG_TYPE_DRV }, + { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN }, + { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, + { "samsung,pin-val", PINCFG_TYPE_DAT }, +}; + +/* Global list of devices (struct samsung_pinctrl_drv_data) */ +static LIST_HEAD(drvdata_list); + +static unsigned int pin_base; + +static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) +{ + return container_of(gc, struct samsung_pin_bank, gpio_chip); +} + +static int samsung_get_group_count(struct pinctrl_dev *pctldev) +{ + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->nr_groups; +} + +static const char *samsung_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pin_groups[group].name; +} + +static int samsung_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); + + *pins = pmx->pin_groups[group].pins; + *num_pins = pmx->pin_groups[group].num_pins; + + return 0; +} + +static int reserve_map(struct device *dev, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps, + unsigned reserve) +{ + unsigned old_num = *reserved_maps; + unsigned new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(dev, "krealloc(map) failed\n"); + return -ENOMEM; + } + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function) +{ + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int add_map_configs(struct device *dev, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps, + const char *group, unsigned long *configs, + unsigned num_configs) +{ + unsigned long *dup_configs; + + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) { + dev_err(dev, "kmemdup(configs) failed\n"); + return -ENOMEM; + } + + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static int add_config(struct device *dev, unsigned long **configs, + unsigned *num_configs, unsigned long config) +{ + unsigned old_num = *num_configs; + unsigned new_num = old_num + 1; + unsigned long *new_configs; + + new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, + GFP_KERNEL); + if (!new_configs) { + dev_err(dev, "krealloc(configs) failed\n"); + return -ENOMEM; + } + + new_configs[old_num] = config; + + *configs = new_configs; + *num_configs = new_num; + + return 0; +} + +static void samsung_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +static int samsung_dt_subnode_to_map(struct samsung_pinctrl_drv_data *drvdata, + struct device *dev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + int ret, i; + u32 val; + unsigned long config; + unsigned long *configs = NULL; + unsigned num_configs = 0; + unsigned reserve; + struct property *prop; + const char *group; + bool has_func = false; + + ret = of_property_read_u32(np, "samsung,pin-function", &val); + if (!ret) + has_func = true; + + for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { + ret = of_property_read_u32(np, cfg_params[i].property, &val); + if (!ret) { + config = PINCFG_PACK(cfg_params[i].param, val); + ret = add_config(dev, &configs, &num_configs, config); + if (ret < 0) + goto exit; + /* EINVAL=missing, which is fine since it's optional */ + } else if (ret != -EINVAL) { + dev_err(dev, "could not parse property %s\n", + cfg_params[i].property); + } + } + + reserve = 0; + if (has_func) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "samsung,pins"); + if (ret < 0) { + dev_err(dev, "could not parse property samsung,pins\n"); + goto exit; + } + reserve *= ret; + + ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "samsung,pins", prop, group) { + if (has_func) { + ret = add_map_mux(map, reserved_maps, + num_maps, group, np->full_name); + if (ret < 0) + goto exit; + } + + if (num_configs) { + ret = add_map_configs(dev, map, reserved_maps, + num_maps, group, configs, + num_configs); + if (ret < 0) + goto exit; + } + } + + ret = 0; + +exit: + kfree(configs); + return ret; +} + +static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct samsung_pinctrl_drv_data *drvdata; + unsigned reserved_maps; + struct device_node *np; + int ret; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + if (!of_get_child_count(np_config)) + return samsung_dt_subnode_to_map(drvdata, pctldev->dev, + np_config, map, + &reserved_maps, + num_maps); + + for_each_child_of_node(np_config, np) { + ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + samsung_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +/* list of pinctrl callbacks for the pinctrl core */ +static const struct pinctrl_ops samsung_pctrl_ops = { + .get_groups_count = samsung_get_group_count, + .get_group_name = samsung_get_group_name, + .get_group_pins = samsung_get_group_pins, + .dt_node_to_map = samsung_dt_node_to_map, + .dt_free_map = samsung_dt_free_map, +}; + +/* check if the selector is a valid pin function selector */ +static int samsung_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct samsung_pinctrl_drv_data *drvdata; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + return drvdata->nr_functions; +} + +/* return the name of the pin function specified */ +static const char *samsung_pinmux_get_fname(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct samsung_pinctrl_drv_data *drvdata; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + return drvdata->pmx_functions[selector].name; +} + +/* return the groups associated for the specified function selector */ +static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **groups, + unsigned * const num_groups) +{ + struct samsung_pinctrl_drv_data *drvdata; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + *groups = drvdata->pmx_functions[selector].groups; + *num_groups = drvdata->pmx_functions[selector].num_groups; + return 0; +} + +/* + * given a pin number that is local to a pin controller, find out the pin bank + * and the register base of the pin bank. + */ +static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, + unsigned pin, void __iomem **reg, u32 *offset, + struct samsung_pin_bank **bank) +{ + struct samsung_pin_bank *b; + + b = drvdata->ctrl->pin_banks; + + while ((pin >= b->pin_base) && + ((b->pin_base + b->nr_pins - 1) < pin)) + b++; + + *reg = drvdata->virt_base + b->pctl_offset; + *offset = pin - b->pin_base; + if (bank) + *bank = b; +} + +/* enable or disable a pinmux function */ +static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group, bool enable) +{ + struct samsung_pinctrl_drv_data *drvdata; + struct samsung_pin_bank_type *type; + struct samsung_pin_bank *bank; + void __iomem *reg; + u32 mask, shift, data, pin_offset; + unsigned long flags; + const struct samsung_pmx_func *func; + const struct samsung_pin_group *grp; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + func = &drvdata->pmx_functions[selector]; + grp = &drvdata->pin_groups[group]; + + pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->ctrl->base, + ®, &pin_offset, &bank); + type = bank->type; + mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; + shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; + if (shift >= 32) { + /* Some banks have two config registers */ + shift -= 32; + reg += 4; + } + + spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); + data &= ~(mask << shift); + if (enable) + data |= func->val << shift; + writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +/* enable a specified pinmux by writing to registers */ +static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + samsung_pinmux_setup(pctldev, selector, group, true); + return 0; +} + +/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ +static const struct pinmux_ops samsung_pinmux_ops = { + .get_functions_count = samsung_get_functions_count, + .get_function_name = samsung_pinmux_get_fname, + .get_function_groups = samsung_pinmux_get_groups, + .enable = samsung_pinmux_enable, +}; + +/* set or get the pin config settings for a specified pin */ +static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config, bool set) +{ + struct samsung_pinctrl_drv_data *drvdata; + struct samsung_pin_bank_type *type; + struct samsung_pin_bank *bank; + void __iomem *reg_base; + enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); + u32 data, width, pin_offset, mask, shift; + u32 cfg_value, cfg_reg; + unsigned long flags; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + pin_to_reg_bank(drvdata, pin - drvdata->ctrl->base, ®_base, + &pin_offset, &bank); + type = bank->type; + + if (cfg_type >= PINCFG_TYPE_NUM || !type->fld_width[cfg_type]) + return -EINVAL; + + width = type->fld_width[cfg_type]; + cfg_reg = type->reg_offset[cfg_type]; + + spin_lock_irqsave(&bank->slock, flags); + + mask = (1 << width) - 1; + shift = pin_offset * width; + data = readl(reg_base + cfg_reg); + + if (set) { + cfg_value = PINCFG_UNPACK_VALUE(*config); + data &= ~(mask << shift); + data |= (cfg_value << shift); + writel(data, reg_base + cfg_reg); + } else { + data >>= shift; + data &= mask; + *config = PINCFG_PACK(cfg_type, data); + } + + spin_unlock_irqrestore(&bank->slock, flags); + + return 0; +} + +/* set the pin config settings for a specified pin */ +static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + int i, ret; + + for (i = 0; i < num_configs; i++) { + ret = samsung_pinconf_rw(pctldev, pin, &configs[i], true); + if (ret < 0) + return ret; + } /* for each config */ + + return 0; +} + +/* get the pin config settings for a specified pin */ +static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + return samsung_pinconf_rw(pctldev, pin, config, false); +} + +/* set the pin config settings for a specified pin group */ +static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *configs, + unsigned num_configs) +{ + struct samsung_pinctrl_drv_data *drvdata; + const unsigned int *pins; + unsigned int cnt; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + pins = drvdata->pin_groups[group].pins; + + for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) + samsung_pinconf_set(pctldev, pins[cnt], configs, num_configs); + + return 0; +} + +/* get the pin config settings for a specified pin group */ +static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + struct samsung_pinctrl_drv_data *drvdata; + const unsigned int *pins; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + pins = drvdata->pin_groups[group].pins; + samsung_pinconf_get(pctldev, pins[0], config); + return 0; +} + +/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ +static const struct pinconf_ops samsung_pinconf_ops = { + .pin_config_get = samsung_pinconf_get, + .pin_config_set = samsung_pinconf_set, + .pin_config_group_get = samsung_pinconf_group_get, + .pin_config_group_set = samsung_pinconf_group_set, +}; + +/* gpiolib gpio_set callback function */ +static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) +{ + struct samsung_pin_bank *bank = gc_to_pin_bank(gc); + struct samsung_pin_bank_type *type = bank->type; + unsigned long flags; + void __iomem *reg; + u32 data; + + reg = bank->drvdata->virt_base + bank->pctl_offset; + + spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); + data &= ~(1 << offset); + if (value) + data |= 1 << offset; + writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +/* gpiolib gpio_get callback function */ +static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset) +{ + void __iomem *reg; + u32 data; + struct samsung_pin_bank *bank = gc_to_pin_bank(gc); + struct samsung_pin_bank_type *type = bank->type; + + reg = bank->drvdata->virt_base + bank->pctl_offset; + + data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); + data >>= offset; + data &= 1; + return data; +} + +/* + * The calls to gpio_direction_output() and gpio_direction_input() + * leads to this function call. + */ +static int samsung_gpio_set_direction(struct gpio_chip *gc, + unsigned offset, bool input) +{ + struct samsung_pin_bank_type *type; + struct samsung_pin_bank *bank; + struct samsung_pinctrl_drv_data *drvdata; + void __iomem *reg; + u32 data, mask, shift; + unsigned long flags; + + bank = gc_to_pin_bank(gc); + type = bank->type; + drvdata = bank->drvdata; + + reg = drvdata->virt_base + bank->pctl_offset + + type->reg_offset[PINCFG_TYPE_FUNC]; + + mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; + shift = offset * type->fld_width[PINCFG_TYPE_FUNC]; + if (shift >= 32) { + /* Some banks have two config registers */ + shift -= 32; + reg += 4; + } + + spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg); + data &= ~(mask << shift); + if (!input) + data |= FUNC_OUTPUT << shift; + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); + + return 0; +} + +/* gpiolib gpio_direction_input callback function. */ +static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +{ + return samsung_gpio_set_direction(gc, offset, true); +} + +/* gpiolib gpio_direction_output callback function. */ +static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, + int value) +{ + samsung_gpio_set(gc, offset, value); + return samsung_gpio_set_direction(gc, offset, false); +} + +/* + * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin + * and a virtual IRQ, if not already present. + */ +static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct samsung_pin_bank *bank = gc_to_pin_bank(gc); + unsigned int virq; + + if (!bank->irq_domain) + return -ENXIO; + + virq = irq_create_mapping(bank->irq_domain, offset); + + return (virq) ? : -ENXIO; +} + +static struct samsung_pin_group *samsung_pinctrl_create_groups( + struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + unsigned int *cnt) +{ + struct pinctrl_desc *ctrldesc = &drvdata->pctl; + struct samsung_pin_group *groups, *grp; + const struct pinctrl_pin_desc *pdesc; + int i; + + groups = devm_kzalloc(dev, ctrldesc->npins * sizeof(*groups), + GFP_KERNEL); + if (!groups) + return ERR_PTR(-EINVAL); + grp = groups; + + pdesc = ctrldesc->pins; + for (i = 0; i < ctrldesc->npins; ++i, ++pdesc, ++grp) { + grp->name = pdesc->name; + grp->pins = &pdesc->number; + grp->num_pins = 1; + } + + *cnt = ctrldesc->npins; + return groups; +} + +static int samsung_pinctrl_create_function(struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + struct device_node *func_np, + struct samsung_pmx_func *func) +{ + int npins; + int ret; + int i; + + if (of_property_read_u32(func_np, "samsung,pin-function", &func->val)) + return 0; + + npins = of_property_count_strings(func_np, "samsung,pins"); + if (npins < 1) { + dev_err(dev, "invalid pin list in %s node", func_np->name); + return -EINVAL; + } + + func->name = func_np->full_name; + + func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + for (i = 0; i < npins; ++i) { + const char *gname; + + ret = of_property_read_string_index(func_np, "samsung,pins", + i, &gname); + if (ret) { + dev_err(dev, + "failed to read pin name %d from %s node\n", + i, func_np->name); + return ret; + } + + func->groups[i] = gname; + } + + func->num_groups = npins; + return 1; +} + +static struct samsung_pmx_func *samsung_pinctrl_create_functions( + struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + unsigned int *cnt) +{ + struct samsung_pmx_func *functions, *func; + struct device_node *dev_np = dev->of_node; + struct device_node *cfg_np; + unsigned int func_cnt = 0; + int ret; + + /* + * Iterate over all the child nodes of the pin controller node + * and create pin groups and pin function lists. + */ + for_each_child_of_node(dev_np, cfg_np) { + struct device_node *func_np; + + if (!of_get_child_count(cfg_np)) { + if (!of_find_property(cfg_np, + "samsung,pin-function", NULL)) + continue; + ++func_cnt; + continue; + } + + for_each_child_of_node(cfg_np, func_np) { + if (!of_find_property(func_np, + "samsung,pin-function", NULL)) + continue; + ++func_cnt; + } + } + + functions = devm_kzalloc(dev, func_cnt * sizeof(*functions), + GFP_KERNEL); + if (!functions) { + dev_err(dev, "failed to allocate memory for function list\n"); + return ERR_PTR(-EINVAL); + } + func = functions; + + /* + * Iterate over all the child nodes of the pin controller node + * and create pin groups and pin function lists. + */ + func_cnt = 0; + for_each_child_of_node(dev_np, cfg_np) { + struct device_node *func_np; + + if (!of_get_child_count(cfg_np)) { + ret = samsung_pinctrl_create_function(dev, drvdata, + cfg_np, func); + if (ret < 0) + return ERR_PTR(ret); + if (ret > 0) { + ++func; + ++func_cnt; + } + continue; + } + + for_each_child_of_node(cfg_np, func_np) { + ret = samsung_pinctrl_create_function(dev, drvdata, + func_np, func); + if (ret < 0) + return ERR_PTR(ret); + if (ret > 0) { + ++func; + ++func_cnt; + } + } + } + + *cnt = func_cnt; + return functions; +} + +/* + * Parse the information about all the available pin groups and pin functions + * from device node of the pin-controller. A pin group is formed with all + * the pins listed in the "samsung,pins" property. + */ + +static int samsung_pinctrl_parse_dt(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct device *dev = &pdev->dev; + struct samsung_pin_group *groups; + struct samsung_pmx_func *functions; + unsigned int grp_cnt = 0, func_cnt = 0; + + groups = samsung_pinctrl_create_groups(dev, drvdata, &grp_cnt); + if (IS_ERR(groups)) { + dev_err(dev, "failed to parse pin groups\n"); + return PTR_ERR(groups); + } + + functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt); + if (IS_ERR(functions)) { + dev_err(dev, "failed to parse pin functions\n"); + return PTR_ERR(groups); + } + + drvdata->pin_groups = groups; + drvdata->nr_groups = grp_cnt; + drvdata->pmx_functions = functions; + drvdata->nr_functions = func_cnt; + + return 0; +} + +/* register the pinctrl interface with the pinctrl subsystem */ +static int samsung_pinctrl_register(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct pinctrl_desc *ctrldesc = &drvdata->pctl; + struct pinctrl_pin_desc *pindesc, *pdesc; + struct samsung_pin_bank *pin_bank; + char *pin_names; + int pin, bank, ret; + + ctrldesc->name = "samsung-pinctrl"; + ctrldesc->owner = THIS_MODULE; + ctrldesc->pctlops = &samsung_pctrl_ops; + ctrldesc->pmxops = &samsung_pinmux_ops; + ctrldesc->confops = &samsung_pinconf_ops; + + pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * + drvdata->ctrl->nr_pins, GFP_KERNEL); + if (!pindesc) { + dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); + return -ENOMEM; + } + ctrldesc->pins = pindesc; + ctrldesc->npins = drvdata->ctrl->nr_pins; + + /* dynamically populate the pin number and pin name for pindesc */ + for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) + pdesc->number = pin + drvdata->ctrl->base; + + /* + * allocate space for storing the dynamically generated names for all + * the pins which belong to this pin-controller. + */ + pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * + drvdata->ctrl->nr_pins, GFP_KERNEL); + if (!pin_names) { + dev_err(&pdev->dev, "mem alloc for pin names failed\n"); + return -ENOMEM; + } + + /* for each pin, the name of the pin is pin-bank name + pin number */ + for (bank = 0; bank < drvdata->ctrl->nr_banks; bank++) { + pin_bank = &drvdata->ctrl->pin_banks[bank]; + for (pin = 0; pin < pin_bank->nr_pins; pin++) { + sprintf(pin_names, "%s-%d", pin_bank->name, pin); + pdesc = pindesc + pin_bank->pin_base + pin; + pdesc->name = pin_names; + pin_names += PIN_NAME_LENGTH; + } + } + + ret = samsung_pinctrl_parse_dt(pdev, drvdata); + if (ret) + return ret; + + drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata); + if (!drvdata->pctl_dev) { + dev_err(&pdev->dev, "could not register pinctrl driver\n"); + return -EINVAL; + } + + for (bank = 0; bank < drvdata->ctrl->nr_banks; ++bank) { + pin_bank = &drvdata->ctrl->pin_banks[bank]; + pin_bank->grange.name = pin_bank->name; + pin_bank->grange.id = bank; + pin_bank->grange.pin_base = drvdata->ctrl->base + + pin_bank->pin_base; + pin_bank->grange.base = pin_bank->gpio_chip.base; + pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; + pin_bank->grange.gc = &pin_bank->gpio_chip; + pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); + } + + return 0; +} + +static int samsung_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void samsung_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static const struct gpio_chip samsung_gpiolib_chip = { + .request = samsung_gpio_request, + .free = samsung_gpio_free, + .set = samsung_gpio_set, + .get = samsung_gpio_get, + .direction_input = samsung_gpio_direction_input, + .direction_output = samsung_gpio_direction_output, + .to_irq = samsung_gpio_to_irq, + .owner = THIS_MODULE, +}; + +/* register the gpiolib interface with the gpiolib subsystem */ +static int samsung_gpiolib_register(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + struct samsung_pin_bank *bank = ctrl->pin_banks; + struct gpio_chip *gc; + int ret; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + bank->gpio_chip = samsung_gpiolib_chip; + + gc = &bank->gpio_chip; + gc->base = ctrl->base + bank->pin_base; + gc->ngpio = bank->nr_pins; + gc->dev = &pdev->dev; + gc->of_node = bank->of_node; + gc->label = bank->name; + + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", + gc->label, ret); + goto fail; + } + } + + return 0; + +fail: + for (--i, --bank; i >= 0; --i, --bank) + if (gpiochip_remove(&bank->gpio_chip)) + dev_err(&pdev->dev, "gpio chip %s remove failed\n", + bank->gpio_chip.label); + return ret; +} + +/* unregister the gpiolib interface with the gpiolib subsystem */ +static int samsung_gpiolib_unregister(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + struct samsung_pin_bank *bank = ctrl->pin_banks; + int ret = 0; + int i; + + for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) + ret = gpiochip_remove(&bank->gpio_chip); + + if (ret) + dev_err(&pdev->dev, "gpio chip remove failed\n"); + + return ret; +} + +static const struct of_device_id samsung_pinctrl_dt_match[]; + +/* retrieve the soc specific data */ +static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data( + struct samsung_pinctrl_drv_data *d, + struct platform_device *pdev) +{ + int id; + const struct of_device_id *match; + struct device_node *node = pdev->dev.of_node; + struct device_node *np; + struct samsung_pin_ctrl *ctrl; + struct samsung_pin_bank *bank; + int i; + + id = of_alias_get_id(node, "pinctrl"); + if (id < 0) { + dev_err(&pdev->dev, "failed to get alias id\n"); + return NULL; + } + match = of_match_node(samsung_pinctrl_dt_match, node); + ctrl = (struct samsung_pin_ctrl *)match->data + id; + + bank = ctrl->pin_banks; + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + spin_lock_init(&bank->slock); + bank->drvdata = d; + bank->pin_base = ctrl->nr_pins; + ctrl->nr_pins += bank->nr_pins; + } + + for_each_child_of_node(node, np) { + if (!of_find_property(np, "gpio-controller", NULL)) + continue; + bank = ctrl->pin_banks; + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (!strcmp(bank->name, np->name)) { + bank->of_node = np; + break; + } + } + } + + ctrl->base = pin_base; + pin_base += ctrl->nr_pins; + + return ctrl; +} + +static int samsung_pinctrl_probe(struct platform_device *pdev) +{ + struct samsung_pinctrl_drv_data *drvdata; + struct device *dev = &pdev->dev; + struct samsung_pin_ctrl *ctrl; + struct resource *res; + int ret; + + if (!dev->of_node) { + dev_err(dev, "device tree node not found\n"); + return -ENODEV; + } + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) { + dev_err(dev, "failed to allocate memory for driver's " + "private data\n"); + return -ENOMEM; + } + + ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev); + if (!ctrl) { + dev_err(&pdev->dev, "driver data not available\n"); + return -EINVAL; + } + drvdata->ctrl = ctrl; + drvdata->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + drvdata->virt_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(drvdata->virt_base)) + return PTR_ERR(drvdata->virt_base); + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res) + drvdata->irq = res->start; + + ret = samsung_gpiolib_register(pdev, drvdata); + if (ret) + return ret; + + ret = samsung_pinctrl_register(pdev, drvdata); + if (ret) { + samsung_gpiolib_unregister(pdev, drvdata); + return ret; + } + + if (ctrl->eint_gpio_init) + ctrl->eint_gpio_init(drvdata); + if (ctrl->eint_wkup_init) + ctrl->eint_wkup_init(drvdata); + + platform_set_drvdata(pdev, drvdata); + + /* Add to the global list */ + list_add_tail(&drvdata->node, &drvdata_list); + + return 0; +} + +#ifdef CONFIG_PM + +/** + * samsung_pinctrl_suspend_dev - save pinctrl state for suspend for a device + * + * Save data for all banks handled by this device. + */ +static void samsung_pinctrl_suspend_dev( + struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + void __iomem *virt_base = drvdata->virt_base; + int i; + + for (i = 0; i < ctrl->nr_banks; i++) { + struct samsung_pin_bank *bank = &ctrl->pin_banks[i]; + void __iomem *reg = virt_base + bank->pctl_offset; + + u8 *offs = bank->type->reg_offset; + u8 *widths = bank->type->fld_width; + enum pincfg_type type; + + /* Registers without a powerdown config aren't lost */ + if (!widths[PINCFG_TYPE_CON_PDN]) + continue; + + for (type = 0; type < PINCFG_TYPE_NUM; type++) + if (widths[type]) + bank->pm_save[type] = readl(reg + offs[type]); + + if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { + /* Some banks have two config registers */ + bank->pm_save[PINCFG_TYPE_NUM] = + readl(reg + offs[PINCFG_TYPE_FUNC] + 4); + pr_debug("Save %s @ %p (con %#010x %08x)\n", + bank->name, reg, + bank->pm_save[PINCFG_TYPE_FUNC], + bank->pm_save[PINCFG_TYPE_NUM]); + } else { + pr_debug("Save %s @ %p (con %#010x)\n", bank->name, + reg, bank->pm_save[PINCFG_TYPE_FUNC]); + } + } + + if (ctrl->suspend) + ctrl->suspend(drvdata); +} + +/** + * samsung_pinctrl_resume_dev - restore pinctrl state from suspend for a device + * + * Restore one of the banks that was saved during suspend. + * + * We don't bother doing anything complicated to avoid glitching lines since + * we're called before pad retention is turned off. + */ +static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + void __iomem *virt_base = drvdata->virt_base; + int i; + + if (ctrl->resume) + ctrl->resume(drvdata); + + for (i = 0; i < ctrl->nr_banks; i++) { + struct samsung_pin_bank *bank = &ctrl->pin_banks[i]; + void __iomem *reg = virt_base + bank->pctl_offset; + + u8 *offs = bank->type->reg_offset; + u8 *widths = bank->type->fld_width; + enum pincfg_type type; + + /* Registers without a powerdown config aren't lost */ + if (!widths[PINCFG_TYPE_CON_PDN]) + continue; + + if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { + /* Some banks have two config registers */ + pr_debug("%s @ %p (con %#010x %08x => %#010x %08x)\n", + bank->name, reg, + readl(reg + offs[PINCFG_TYPE_FUNC]), + readl(reg + offs[PINCFG_TYPE_FUNC] + 4), + bank->pm_save[PINCFG_TYPE_FUNC], + bank->pm_save[PINCFG_TYPE_NUM]); + writel(bank->pm_save[PINCFG_TYPE_NUM], + reg + offs[PINCFG_TYPE_FUNC] + 4); + } else { + pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name, + reg, readl(reg + offs[PINCFG_TYPE_FUNC]), + bank->pm_save[PINCFG_TYPE_FUNC]); + } + for (type = 0; type < PINCFG_TYPE_NUM; type++) + if (widths[type]) + writel(bank->pm_save[type], reg + offs[type]); + } +} + +/** + * samsung_pinctrl_suspend - save pinctrl state for suspend + * + * Save data for all banks across all devices. + */ +static int samsung_pinctrl_suspend(void) +{ + struct samsung_pinctrl_drv_data *drvdata; + + list_for_each_entry(drvdata, &drvdata_list, node) { + samsung_pinctrl_suspend_dev(drvdata); + } + + return 0; +} + +/** + * samsung_pinctrl_resume - restore pinctrl state for suspend + * + * Restore data for all banks across all devices. + */ +static void samsung_pinctrl_resume(void) +{ + struct samsung_pinctrl_drv_data *drvdata; + + list_for_each_entry_reverse(drvdata, &drvdata_list, node) { + samsung_pinctrl_resume_dev(drvdata); + } +} + +#else +#define samsung_pinctrl_suspend NULL +#define samsung_pinctrl_resume NULL +#endif + +static struct syscore_ops samsung_pinctrl_syscore_ops = { + .suspend = samsung_pinctrl_suspend, + .resume = samsung_pinctrl_resume, +}; + +static const struct of_device_id samsung_pinctrl_dt_match[] = { +#ifdef CONFIG_PINCTRL_EXYNOS + { .compatible = "samsung,exynos3250-pinctrl", + .data = (void *)exynos3250_pin_ctrl }, + { .compatible = "samsung,exynos4210-pinctrl", + .data = (void *)exynos4210_pin_ctrl }, + { .compatible = "samsung,exynos4x12-pinctrl", + .data = (void *)exynos4x12_pin_ctrl }, + { .compatible = "samsung,exynos5250-pinctrl", + .data = (void *)exynos5250_pin_ctrl }, + { .compatible = "samsung,exynos5260-pinctrl", + .data = (void *)exynos5260_pin_ctrl }, + { .compatible = "samsung,exynos5420-pinctrl", + .data = (void *)exynos5420_pin_ctrl }, + { .compatible = "samsung,s5pv210-pinctrl", + .data = (void *)s5pv210_pin_ctrl }, +#endif +#ifdef CONFIG_PINCTRL_S3C64XX + { .compatible = "samsung,s3c64xx-pinctrl", + .data = s3c64xx_pin_ctrl }, +#endif +#ifdef CONFIG_PINCTRL_S3C24XX + { .compatible = "samsung,s3c2412-pinctrl", + .data = s3c2412_pin_ctrl }, + { .compatible = "samsung,s3c2416-pinctrl", + .data = s3c2416_pin_ctrl }, + { .compatible = "samsung,s3c2440-pinctrl", + .data = s3c2440_pin_ctrl }, + { .compatible = "samsung,s3c2450-pinctrl", + .data = s3c2450_pin_ctrl }, +#endif + {}, +}; +MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); + +static struct platform_driver samsung_pinctrl_driver = { + .probe = samsung_pinctrl_probe, + .driver = { + .name = "samsung-pinctrl", + .owner = THIS_MODULE, + .of_match_table = samsung_pinctrl_dt_match, + }, +}; + +static int __init samsung_pinctrl_drv_register(void) +{ + /* + * Register syscore ops for save/restore of registers across suspend. + * It's important to ensure that this driver is running at an earlier + * initcall level than any arch-specific init calls that install syscore + * ops that turn off pad retention (like exynos_pm_resume). + */ + register_syscore_ops(&samsung_pinctrl_syscore_ops); + + return platform_driver_register(&samsung_pinctrl_driver); +} +postcore_initcall(samsung_pinctrl_drv_register); + +static void __exit samsung_pinctrl_drv_unregister(void) +{ + platform_driver_unregister(&samsung_pinctrl_driver); +} +module_exit(samsung_pinctrl_drv_unregister); + +MODULE_AUTHOR("Thomas Abraham "); +MODULE_DESCRIPTION("Samsung pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h new file mode 100644 index 000000000000..2b882320e8e9 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -0,0 +1,251 @@ +/* + * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * Author: Thomas Abraham + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __PINCTRL_SAMSUNG_H +#define __PINCTRL_SAMSUNG_H + +#include +#include +#include +#include +#include + +#include + +/* pinmux function number for pin as gpio output line */ +#define FUNC_OUTPUT 0x1 + +/** + * enum pincfg_type - possible pin configuration types supported. + * @PINCFG_TYPE_FUNC: Function configuration. + * @PINCFG_TYPE_DAT: Pin value configuration. + * @PINCFG_TYPE_PUD: Pull up/down configuration. + * @PINCFG_TYPE_DRV: Drive strength configuration. + * @PINCFG_TYPE_CON_PDN: Pin function in power down mode. + * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode. + */ +enum pincfg_type { + PINCFG_TYPE_FUNC, + PINCFG_TYPE_DAT, + PINCFG_TYPE_PUD, + PINCFG_TYPE_DRV, + PINCFG_TYPE_CON_PDN, + PINCFG_TYPE_PUD_PDN, + + PINCFG_TYPE_NUM +}; + +/* + * pin configuration (pull up/down and drive strength) type and its value are + * packed together into a 16-bits. The upper 8-bits represent the configuration + * type and the lower 8-bits hold the value of the configuration type. + */ +#define PINCFG_TYPE_MASK 0xFF +#define PINCFG_VALUE_SHIFT 8 +#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) +#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) +#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) +#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ + PINCFG_VALUE_SHIFT) +/** + * enum eint_type - possible external interrupt types. + * @EINT_TYPE_NONE: bank does not support external interrupts + * @EINT_TYPE_GPIO: bank supportes external gpio interrupts + * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts + * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts + * + * Samsung GPIO controller groups all the available pins into banks. The pins + * in a pin bank can support external gpio interrupts or external wakeup + * interrupts or no interrupts at all. From a software perspective, the only + * difference between external gpio and external wakeup interrupts is that + * the wakeup interrupts can additionally wakeup the system if it is in + * suspended state. + */ +enum eint_type { + EINT_TYPE_NONE, + EINT_TYPE_GPIO, + EINT_TYPE_WKUP, + EINT_TYPE_WKUP_MUX, +}; + +/* maximum length of a pin in pin descriptor (example: "gpa0-0") */ +#define PIN_NAME_LENGTH 10 + +#define PIN_GROUP(n, p, f) \ + { \ + .name = n, \ + .pins = p, \ + .num_pins = ARRAY_SIZE(p), \ + .func = f \ + } + +#define PMX_FUNC(n, g) \ + { \ + .name = n, \ + .groups = g, \ + .num_groups = ARRAY_SIZE(g), \ + } + +struct samsung_pinctrl_drv_data; + +/** + * struct samsung_pin_bank_type: pin bank type description + * @fld_width: widths of configuration bitfields (0 if unavailable) + * @reg_offset: offsets of configuration registers (don't care of width is 0) + */ +struct samsung_pin_bank_type { + u8 fld_width[PINCFG_TYPE_NUM]; + u8 reg_offset[PINCFG_TYPE_NUM]; +}; + +/** + * struct samsung_pin_bank: represent a controller pin-bank. + * @type: type of the bank (register offsets and bitfield widths) + * @pctl_offset: starting offset of the pin-bank registers. + * @pin_base: starting pin number of the bank. + * @nr_pins: number of pins included in this bank. + * @eint_func: function to set in CON register to configure pin as EINT. + * @eint_type: type of the external interrupt supported by the bank. + * @eint_mask: bit mask of pins which support EINT function. + * @name: name to be prefixed for each pin in this pin bank. + * @of_node: OF node of the bank. + * @drvdata: link to controller driver data + * @irq_domain: IRQ domain of the bank. + * @gpio_chip: GPIO chip of the bank. + * @grange: linux gpio pin range supported by this bank. + * @slock: spinlock protecting bank registers + * @pm_save: saved register values during suspend + */ +struct samsung_pin_bank { + struct samsung_pin_bank_type *type; + u32 pctl_offset; + u32 pin_base; + u8 nr_pins; + u8 eint_func; + enum eint_type eint_type; + u32 eint_mask; + u32 eint_offset; + char *name; + void *soc_priv; + struct device_node *of_node; + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *irq_domain; + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range grange; + spinlock_t slock; + + u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ +}; + +/** + * struct samsung_pin_ctrl: represent a pin controller. + * @pin_banks: list of pin banks included in this controller. + * @nr_banks: number of pin banks. + * @base: starting system wide pin number. + * @nr_pins: number of pins supported by the controller. + * @eint_gpio_init: platform specific callback to setup the external gpio + * interrupts for the controller. + * @eint_wkup_init: platform specific callback to setup the external wakeup + * interrupts for the controller. + * @label: for debug information. + */ +struct samsung_pin_ctrl { + struct samsung_pin_bank *pin_banks; + u32 nr_banks; + + u32 base; + u32 nr_pins; + + int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); + int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); + void (*suspend)(struct samsung_pinctrl_drv_data *); + void (*resume)(struct samsung_pinctrl_drv_data *); + + char *label; +}; + +/** + * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. + * @node: global list node + * @virt_base: register base address of the controller. + * @dev: device instance representing the controller. + * @irq: interrpt number used by the controller to notify gpio interrupts. + * @ctrl: pin controller instance managed by the driver. + * @pctl: pin controller descriptor registered with the pinctrl subsystem. + * @pctl_dev: cookie representing pinctrl device instance. + * @pin_groups: list of pin groups available to the driver. + * @nr_groups: number of such pin groups. + * @pmx_functions: list of pin functions available to the driver. + * @nr_function: number of such pin functions. + */ +struct samsung_pinctrl_drv_data { + struct list_head node; + void __iomem *virt_base; + struct device *dev; + int irq; + + struct samsung_pin_ctrl *ctrl; + struct pinctrl_desc pctl; + struct pinctrl_dev *pctl_dev; + + const struct samsung_pin_group *pin_groups; + unsigned int nr_groups; + const struct samsung_pmx_func *pmx_functions; + unsigned int nr_functions; +}; + +/** + * struct samsung_pin_group: represent group of pins of a pinmux function. + * @name: name of the pin group, used to lookup the group. + * @pins: the pins included in this group. + * @num_pins: number of pins included in this group. + * @func: the function number to be programmed when selected. + */ +struct samsung_pin_group { + const char *name; + const unsigned int *pins; + u8 num_pins; + u8 func; +}; + +/** + * struct samsung_pmx_func: represent a pin function. + * @name: name of the pin function, used to lookup the function. + * @groups: one or more names of pin groups that provide this function. + * @num_groups: number of groups included in @groups. + */ +struct samsung_pmx_func { + const char *name; + const char **groups; + u8 num_groups; + u32 val; +}; + +/* list of all exported SoC specific data */ +extern struct samsung_pin_ctrl exynos3250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2416_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2440_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2450_pin_ctrl[]; +extern struct samsung_pin_ctrl s5pv210_pin_ctrl[]; + +#endif /* __PINCTRL_SAMSUNG_H */ -- cgit v1.2.3 From dc0a3938668706f3a63cde4ceb431e9189fb2a0a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Jun 2014 13:37:08 +0200 Subject: pinctrl: Add NVIDIA Tegra XUSB pad controller support The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads that lanes can be assigned to in order to support a variety of interface options: USB 2.0, USB 3.0, PCIe and SATA. In addition to the pin controller used to assign lanes to pads two PHYs are exposed to allow the bricks for PCIe and SATA to be powered up and down by PCIe and SATA drivers. Tested-by: Mikko Perttunen Acked-by: Linus Walleij Signed-off-by: Thierry Reding --- drivers/pinctrl/Kconfig | 6 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-tegra-xusb.c | 973 +++++++++++++++++++++++++++++++++++ 3 files changed, 980 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-tegra-xusb.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0042ccb46b9a..0fa42be8df00 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -328,6 +328,12 @@ config PINCTRL_TEGRA124 bool select PINCTRL_TEGRA +config PINCTRL_TEGRA_XUSB + def_bool y if ARCH_TEGRA + select GENERIC_PHY + select PINCONF + select PINMUX + config PINCTRL_TZ1090 bool "Toumaz Xenif TZ1090 pin control driver" depends on SOC_TZ1090 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c4b5d405b8f5..df8878839b44 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o +obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c new file mode 100644 index 000000000000..4a7daf577b49 --- /dev/null +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -0,0 +1,973 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "core.h" +#include "pinctrl-utils.h" + +#define XUSB_PADCTL_ELPG_PROGRAM 0x01c +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) + +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) + +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) + +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) + +#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 +#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) +#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) + +struct tegra_xusb_padctl_function { + const char *name; + const char * const *groups; + unsigned int num_groups; +}; + +struct tegra_xusb_padctl_group { + const unsigned int *funcs; + unsigned int num_funcs; +}; + +struct tegra_xusb_padctl_soc { + const struct pinctrl_pin_desc *pins; + unsigned int num_pins; + + const struct tegra_xusb_padctl_function *functions; + unsigned int num_functions; + + const struct tegra_xusb_padctl_lane *lanes; + unsigned int num_lanes; +}; + +struct tegra_xusb_padctl_lane { + const char *name; + + unsigned int offset; + unsigned int shift; + unsigned int mask; + unsigned int iddq; + + const unsigned int *funcs; + unsigned int num_funcs; +}; + +struct tegra_xusb_padctl { + struct device *dev; + void __iomem *regs; + struct mutex lock; + struct reset_control *rst; + + const struct tegra_xusb_padctl_soc *soc; + struct pinctrl_dev *pinctrl; + struct pinctrl_desc desc; + + struct phy_provider *provider; + struct phy *phys[2]; + + unsigned int enable; +}; + +static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value, + unsigned long offset) +{ + writel(value, padctl->regs + offset); +} + +static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, + unsigned long offset) +{ + return readl(padctl->regs + offset); +} + +static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + + return padctl->soc->num_pins; +} + +static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl, + unsigned int group) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + + return padctl->soc->pins[group].name; +} + +enum tegra_xusb_padctl_param { + TEGRA_XUSB_PADCTL_IDDQ, +}; + +static const struct tegra_xusb_padctl_property { + const char *name; + enum tegra_xusb_padctl_param param; +} properties[] = { + { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ }, +}; + +#define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value)) +#define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16) +#define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff) + +static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + unsigned int i, reserve = 0, num_configs = 0; + unsigned long config, *configs = NULL; + const char *function, *group; + struct property *prop; + int err = 0; + u32 value; + + err = of_property_read_string(np, "nvidia,function", &function); + if (err < 0) { + if (err != -EINVAL) + return err; + + function = NULL; + } + + for (i = 0; i < ARRAY_SIZE(properties); i++) { + err = of_property_read_u32(np, properties[i].name, &value); + if (err < 0) { + if (err == -EINVAL) + continue; + + return err; + } + + config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value); + + err = pinctrl_utils_add_config(padctl->pinctrl, &configs, + &num_configs, config); + if (err < 0) + return err; + } + + if (function) + reserve++; + + if (num_configs) + reserve++; + + err = of_property_count_strings(np, "nvidia,lanes"); + if (err < 0) + return err; + + reserve *= err; + + err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps, + num_maps, reserve); + if (err < 0) + return err; + + of_property_for_each_string(np, "nvidia,lanes", prop, group) { + if (function) { + err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps, + reserved_maps, num_maps, group, + function); + if (err < 0) + return err; + } + + if (num_configs) { + err = pinctrl_utils_add_map_configs(padctl->pinctrl, + maps, reserved_maps, num_maps, group, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (err < 0) + return err; + } + } + + return 0; +} + +static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl, + struct device_node *parent, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + unsigned int reserved_maps = 0; + struct device_node *np; + int err; + + *num_maps = 0; + *maps = NULL; + + for_each_child_of_node(parent, np) { + err = tegra_xusb_padctl_parse_subnode(padctl, np, maps, + &reserved_maps, + num_maps); + if (err < 0) + return err; + } + + return 0; +} + +static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = { + .get_groups_count = tegra_xusb_padctl_get_groups_count, + .get_group_name = tegra_xusb_padctl_get_group_name, + .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + + return padctl->soc->num_functions; +} + +static const char * +tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl, + unsigned int function) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + + return padctl->soc->functions[function].name; +} + +static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl, + unsigned int function, + const char * const **groups, + unsigned * const num_groups) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + + *num_groups = padctl->soc->functions[function].num_groups; + *groups = padctl->soc->functions[function].groups; + + return 0; +} + +static int tegra_xusb_padctl_pinmux_enable(struct pinctrl_dev *pinctrl, + unsigned int function, + unsigned int group) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + const struct tegra_xusb_padctl_lane *lane; + unsigned int i; + u32 value; + + lane = &padctl->soc->lanes[group]; + + for (i = 0; i < lane->num_funcs; i++) + if (lane->funcs[i] == function) + break; + + if (i >= lane->num_funcs) + return -EINVAL; + + value = padctl_readl(padctl, lane->offset); + value &= ~(lane->mask << lane->shift); + value |= i << lane->shift; + padctl_writel(padctl, value, lane->offset); + + return 0; +} + +static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = { + .get_functions_count = tegra_xusb_padctl_get_functions_count, + .get_function_name = tegra_xusb_padctl_get_function_name, + .get_function_groups = tegra_xusb_padctl_get_function_groups, + .enable = tegra_xusb_padctl_pinmux_enable, +}; + +static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl, + unsigned int group, + unsigned long *config) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + const struct tegra_xusb_padctl_lane *lane; + enum tegra_xusb_padctl_param param; + u32 value; + + param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config); + lane = &padctl->soc->lanes[group]; + + switch (param) { + case TEGRA_XUSB_PADCTL_IDDQ: + /* lanes with iddq == 0 don't support this parameter */ + if (lane->iddq == 0) + return -EINVAL; + + value = padctl_readl(padctl, lane->offset); + + if (value & BIT(lane->iddq)) + value = 0; + else + value = 1; + + *config = TEGRA_XUSB_PADCTL_PACK(param, value); + break; + + default: + dev_err(padctl->dev, "invalid configuration parameter: %04x\n", + param); + return -ENOTSUPP; + } + + return 0; +} + +static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl, + unsigned int group, + unsigned long *configs, + unsigned int num_configs) +{ + struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); + const struct tegra_xusb_padctl_lane *lane; + enum tegra_xusb_padctl_param param; + unsigned long value; + unsigned int i; + u32 regval; + + lane = &padctl->soc->lanes[group]; + + for (i = 0; i < num_configs; i++) { + param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]); + value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]); + + switch (param) { + case TEGRA_XUSB_PADCTL_IDDQ: + /* lanes with iddq == 0 don't support this parameter */ + if (lane->iddq == 0) + return -EINVAL; + + regval = padctl_readl(padctl, lane->offset); + + if (value) + regval &= ~BIT(lane->iddq); + else + regval |= BIT(lane->iddq); + + padctl_writel(padctl, regval, lane->offset); + break; + + default: + dev_err(padctl->dev, + "invalid configuration parameter: %04x\n", + param); + return -ENOTSUPP; + } + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static const char *strip_prefix(const char *s) +{ + const char *comma = strchr(s, ','); + if (!comma) + return s; + + return comma + 1; +} + +static void +tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl, + struct seq_file *s, + unsigned int group) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(properties); i++) { + unsigned long config, value; + int err; + + config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0); + + err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group, + &config); + if (err < 0) + continue; + + value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config); + + seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name), + value); + } +} + +static void +tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl, + struct seq_file *s, + unsigned long config) +{ + enum tegra_xusb_padctl_param param; + const char *name = "unknown"; + unsigned long value; + unsigned int i; + + param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config); + value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config); + + for (i = 0; i < ARRAY_SIZE(properties); i++) { + if (properties[i].param == param) { + name = properties[i].name; + break; + } + } + + seq_printf(s, "%s=%lu", strip_prefix(name), value); +} +#endif + +static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = { + .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get, + .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set, +#ifdef CONFIG_DEBUG_FS + .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show, + .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show, +#endif +}; + +static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) +{ + u32 value; + + mutex_lock(&padctl->lock); + + if (padctl->enable++ > 0) + goto out; + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + usleep_range(100, 200); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + usleep_range(100, 200); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + +out: + mutex_unlock(&padctl->lock); + return 0; +} + +static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) +{ + u32 value; + + mutex_lock(&padctl->lock); + + if (WARN_ON(padctl->enable == 0)) + goto out; + + if (--padctl->enable > 0) + goto out; + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + usleep_range(100, 200); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + usleep_range(100, 200); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + +out: + mutex_unlock(&padctl->lock); + return 0; +} + +static int tegra_xusb_phy_init(struct phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); + + return tegra_xusb_padctl_enable(padctl); +} + +static int tegra_xusb_phy_exit(struct phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); + + return tegra_xusb_padctl_disable(padctl); +} + +static int pcie_phy_power_on(struct phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); + unsigned long timeout; + int err = -ETIMEDOUT; + u32 value; + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); + value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN | + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN | + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + + timeout = jiffies + msecs_to_jiffies(50); + + while (time_before(jiffies, timeout)) { + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) { + err = 0; + break; + } + + usleep_range(100, 200); + } + + return err; +} + +static int pcie_phy_power_off(struct phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); + u32 value; + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + + return 0; +} + +static const struct phy_ops pcie_phy_ops = { + .init = tegra_xusb_phy_init, + .exit = tegra_xusb_phy_exit, + .power_on = pcie_phy_power_on, + .power_off = pcie_phy_power_off, + .owner = THIS_MODULE, +}; + +static int sata_phy_power_on(struct phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); + unsigned long timeout; + int err = -ETIMEDOUT; + u32 value; + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; + value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; + value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + timeout = jiffies + msecs_to_jiffies(50); + + while (time_before(jiffies, timeout)) { + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) { + err = 0; + break; + } + + usleep_range(100, 200); + } + + return err; +} + +static int sata_phy_power_off(struct phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); + u32 value; + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; + value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); + value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; + value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); + + return 0; +} + +static const struct phy_ops sata_phy_ops = { + .init = tegra_xusb_phy_init, + .exit = tegra_xusb_phy_exit, + .power_on = sata_phy_power_on, + .power_off = sata_phy_power_off, + .owner = THIS_MODULE, +}; + +static struct phy *tegra_xusb_padctl_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev); + unsigned int index = args->args[0]; + + if (args->args_count <= 0) + return ERR_PTR(-EINVAL); + + if (index > ARRAY_SIZE(padctl->phys)) + return ERR_PTR(-EINVAL); + + return padctl->phys[index]; +} + +#define PIN_OTG_0 0 +#define PIN_OTG_1 1 +#define PIN_OTG_2 2 +#define PIN_ULPI_0 3 +#define PIN_HSIC_0 4 +#define PIN_HSIC_1 5 +#define PIN_PCIE_0 6 +#define PIN_PCIE_1 7 +#define PIN_PCIE_2 8 +#define PIN_PCIE_3 9 +#define PIN_PCIE_4 10 +#define PIN_SATA_0 11 + +static const struct pinctrl_pin_desc tegra124_pins[] = { + PINCTRL_PIN(PIN_OTG_0, "otg-0"), + PINCTRL_PIN(PIN_OTG_1, "otg-1"), + PINCTRL_PIN(PIN_OTG_2, "otg-2"), + PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"), + PINCTRL_PIN(PIN_HSIC_0, "hsic-0"), + PINCTRL_PIN(PIN_HSIC_1, "hsic-1"), + PINCTRL_PIN(PIN_PCIE_0, "pcie-0"), + PINCTRL_PIN(PIN_PCIE_1, "pcie-1"), + PINCTRL_PIN(PIN_PCIE_2, "pcie-2"), + PINCTRL_PIN(PIN_PCIE_3, "pcie-3"), + PINCTRL_PIN(PIN_PCIE_4, "pcie-4"), + PINCTRL_PIN(PIN_SATA_0, "sata-0"), +}; + +static const char * const tegra124_snps_groups[] = { + "otg-0", + "otg-1", + "otg-2", + "ulpi-0", + "hsic-0", + "hsic-1", +}; + +static const char * const tegra124_xusb_groups[] = { + "otg-0", + "otg-1", + "otg-2", + "ulpi-0", + "hsic-0", + "hsic-1", +}; + +static const char * const tegra124_uart_groups[] = { + "otg-0", + "otg-1", + "otg-2", +}; + +static const char * const tegra124_pcie_groups[] = { + "pcie-0", + "pcie-1", + "pcie-2", + "pcie-3", + "pcie-4", + "sata-0", +}; + +static const char * const tegra124_usb3_groups[] = { + "pcie-0", + "pcie-1", + "pcie-2", + "pcie-3", + "pcie-4", + "sata-0", +}; + +static const char * const tegra124_sata_groups[] = { + "pcie-0", + "pcie-1", + "pcie-2", + "pcie-3", + "pcie-4", + "sata-0", +}; + +static const char * const tegra124_rsvd_groups[] = { + "otg-0", + "otg-1", + "otg-2", + "pcie-0", + "pcie-1", + "pcie-2", + "pcie-3", + "pcie-4", + "sata-0", +}; + +#define TEGRA124_FUNCTION(_name) \ + { \ + .name = #_name, \ + .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \ + .groups = tegra124_##_name##_groups, \ + } + +static struct tegra_xusb_padctl_function tegra124_functions[] = { + TEGRA124_FUNCTION(snps), + TEGRA124_FUNCTION(xusb), + TEGRA124_FUNCTION(uart), + TEGRA124_FUNCTION(pcie), + TEGRA124_FUNCTION(usb3), + TEGRA124_FUNCTION(sata), + TEGRA124_FUNCTION(rsvd), +}; + +enum tegra124_function { + TEGRA124_FUNC_SNPS, + TEGRA124_FUNC_XUSB, + TEGRA124_FUNC_UART, + TEGRA124_FUNC_PCIE, + TEGRA124_FUNC_USB3, + TEGRA124_FUNC_SATA, + TEGRA124_FUNC_RSVD, +}; + +static const unsigned int tegra124_otg_functions[] = { + TEGRA124_FUNC_SNPS, + TEGRA124_FUNC_XUSB, + TEGRA124_FUNC_UART, + TEGRA124_FUNC_RSVD, +}; + +static const unsigned int tegra124_usb_functions[] = { + TEGRA124_FUNC_SNPS, + TEGRA124_FUNC_XUSB, +}; + +static const unsigned int tegra124_pci_functions[] = { + TEGRA124_FUNC_PCIE, + TEGRA124_FUNC_USB3, + TEGRA124_FUNC_SATA, + TEGRA124_FUNC_RSVD, +}; + +#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ + { \ + .name = _name, \ + .offset = _offset, \ + .shift = _shift, \ + .mask = _mask, \ + .iddq = _iddq, \ + .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \ + .funcs = tegra124_##_funcs##_functions, \ + } + +static const struct tegra_xusb_padctl_lane tegra124_lanes[] = { + TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg), + TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg), + TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg), + TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb), + TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), + TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), + TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci), + TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci), + TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci), + TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci), + TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci), + TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci), +}; + +static const struct tegra_xusb_padctl_soc tegra124_soc = { + .num_pins = ARRAY_SIZE(tegra124_pins), + .pins = tegra124_pins, + .num_functions = ARRAY_SIZE(tegra124_functions), + .functions = tegra124_functions, + .num_lanes = ARRAY_SIZE(tegra124_lanes), + .lanes = tegra124_lanes, +}; + +static const struct of_device_id tegra_xusb_padctl_of_match[] = { + { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match); + +static int tegra_xusb_padctl_probe(struct platform_device *pdev) +{ + struct tegra_xusb_padctl *padctl; + const struct of_device_id *match; + struct resource *res; + struct phy *phy; + int err; + + padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL); + if (!padctl) + return -ENOMEM; + + platform_set_drvdata(pdev, padctl); + mutex_init(&padctl->lock); + padctl->dev = &pdev->dev; + + match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node); + padctl->soc = match->data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + padctl->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(padctl->regs)) + return PTR_ERR(padctl->regs); + + padctl->rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(padctl->rst)) + return PTR_ERR(padctl->rst); + + err = reset_control_deassert(padctl->rst); + if (err < 0) + return err; + + memset(&padctl->desc, 0, sizeof(padctl->desc)); + padctl->desc.name = dev_name(padctl->dev); + padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops; + padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops; + padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops; + padctl->desc.owner = THIS_MODULE; + + padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl); + if (!padctl->pinctrl) { + dev_err(&pdev->dev, "failed to register pincontrol\n"); + err = -ENODEV; + goto reset; + } + + phy = devm_phy_create(&pdev->dev, &pcie_phy_ops, NULL); + if (IS_ERR(phy)) { + err = PTR_ERR(phy); + goto unregister; + } + + padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy; + phy_set_drvdata(phy, padctl); + + phy = devm_phy_create(&pdev->dev, &sata_phy_ops, NULL); + if (IS_ERR(phy)) { + err = PTR_ERR(phy); + goto unregister; + } + + padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy; + phy_set_drvdata(phy, padctl); + + padctl->provider = devm_of_phy_provider_register(&pdev->dev, + tegra_xusb_padctl_xlate); + if (err < 0) { + dev_err(&pdev->dev, "failed to register PHYs: %d\n", err); + goto unregister; + } + + return 0; + +unregister: + pinctrl_unregister(padctl->pinctrl); +reset: + reset_control_assert(padctl->rst); + return err; +} + +static int tegra_xusb_padctl_remove(struct platform_device *pdev) +{ + struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev); + int err; + + pinctrl_unregister(padctl->pinctrl); + + err = reset_control_assert(padctl->rst); + if (err < 0) + dev_err(&pdev->dev, "failed to assert reset: %d\n", err); + + return err; +} + +static struct platform_driver tegra_xusb_padctl_driver = { + .driver = { + .name = "tegra-xusb-padctl", + .of_match_table = tegra_xusb_padctl_of_match, + }, + .probe = tegra_xusb_padctl_probe, + .remove = tegra_xusb_padctl_remove, +}; +module_platform_driver(tegra_xusb_padctl_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 3a19805920f1b07401ea8a3ca00d7568dc2ce5e9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 11 Jul 2014 14:57:06 +0200 Subject: pinctrl: nomadik: move all Nomadik drivers to subdir We have a bunch of Nomadik family pin control drivers, so let's move them into their own subdirectory. Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 45 +- drivers/pinctrl/Makefile | 10 +- drivers/pinctrl/nomadik/Kconfig | 51 + drivers/pinctrl/nomadik/Makefile | 10 + drivers/pinctrl/nomadik/pinctrl-ab8500.c | 485 +++++ drivers/pinctrl/nomadik/pinctrl-ab8505.c | 381 ++++ drivers/pinctrl/nomadik/pinctrl-ab8540.c | 408 ++++ drivers/pinctrl/nomadik/pinctrl-ab9540.c | 486 +++++ drivers/pinctrl/nomadik/pinctrl-abx500.c | 1346 +++++++++++++ drivers/pinctrl/nomadik/pinctrl-abx500.h | 246 +++ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c | 1257 ++++++++++++ drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c | 1266 +++++++++++++ drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c | 356 ++++ drivers/pinctrl/nomadik/pinctrl-nomadik.c | 2099 +++++++++++++++++++++ drivers/pinctrl/nomadik/pinctrl-nomadik.h | 192 ++ drivers/pinctrl/pinctrl-ab8500.c | 485 ----- drivers/pinctrl/pinctrl-ab8505.c | 381 ---- drivers/pinctrl/pinctrl-ab8540.c | 408 ---- drivers/pinctrl/pinctrl-ab9540.c | 486 ----- drivers/pinctrl/pinctrl-abx500.c | 1346 ------------- drivers/pinctrl/pinctrl-abx500.h | 246 --- drivers/pinctrl/pinctrl-nomadik-db8500.c | 1257 ------------ drivers/pinctrl/pinctrl-nomadik-db8540.c | 1266 ------------- drivers/pinctrl/pinctrl-nomadik-stn8815.c | 356 ---- drivers/pinctrl/pinctrl-nomadik.c | 2099 --------------------- drivers/pinctrl/pinctrl-nomadik.h | 192 -- 26 files changed, 8585 insertions(+), 8575 deletions(-) create mode 100644 drivers/pinctrl/nomadik/Kconfig create mode 100644 drivers/pinctrl/nomadik/Makefile create mode 100644 drivers/pinctrl/nomadik/pinctrl-ab8500.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-ab8505.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-ab8540.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-ab9540.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-abx500.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-abx500.h create mode 100644 drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-nomadik.c create mode 100644 drivers/pinctrl/nomadik/pinctrl-nomadik.h delete mode 100644 drivers/pinctrl/pinctrl-ab8500.c delete mode 100644 drivers/pinctrl/pinctrl-ab8505.c delete mode 100644 drivers/pinctrl/pinctrl-ab8540.c delete mode 100644 drivers/pinctrl/pinctrl-ab9540.c delete mode 100644 drivers/pinctrl/pinctrl-abx500.c delete mode 100644 drivers/pinctrl/pinctrl-abx500.h delete mode 100644 drivers/pinctrl/pinctrl-nomadik-db8500.c delete mode 100644 drivers/pinctrl/pinctrl-nomadik-db8540.c delete mode 100644 drivers/pinctrl/pinctrl-nomadik-stn8815.c delete mode 100644 drivers/pinctrl/pinctrl-nomadik.c delete mode 100644 drivers/pinctrl/pinctrl-nomadik.h (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 53e07c70951f..3d94e47546ec 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -26,29 +26,6 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. -config PINCTRL_ABX500 - bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions" - depends on AB8500_CORE - select GENERIC_PINCONF - help - Select this to enable the ABx500 family IC GPIO driver - -config PINCTRL_AB8500 - bool "AB8500 pin controller driver" - depends on PINCTRL_ABX500 && ARCH_U8500 - -config PINCTRL_AB8540 - bool "AB8540 pin controller driver" - depends on PINCTRL_ABX500 && ARCH_U8500 - -config PINCTRL_AB9540 - bool "AB9540 pin controller driver" - depends on PINCTRL_ABX500 && ARCH_U8500 - -config PINCTRL_AB8505 - bool "AB8505 pin controller driver" - depends on PINCTRL_ABX500 && ARCH_U8500 - config PINCTRL_ADI2 bool "ADI pin controller driver" depends on BLACKFIN @@ -233,27 +210,6 @@ config PINCTRL_IMX28 bool select PINCTRL_MXS -config PINCTRL_NOMADIK - bool "Nomadik pin controller driver" - depends on ARCH_U8500 || ARCH_NOMADIK - select PINMUX - select PINCONF - select GPIOLIB - select OF_GPIO - select GPIOLIB_IRQCHIP - -config PINCTRL_STN8815 - bool "STN8815 pin controller driver" - depends on PINCTRL_NOMADIK && ARCH_NOMADIK - -config PINCTRL_DB8500 - bool "DB8500 pin controller driver" - depends on PINCTRL_NOMADIK && ARCH_U8500 - -config PINCTRL_DB8540 - bool "DB8540 pin controller driver" - depends on PINCTRL_NOMADIK && ARCH_U8500 - config PINCTRL_ROCKCHIP bool select PINMUX @@ -345,6 +301,7 @@ config PINCTRL_PALMAS source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" +source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index df6099df7aad..e90817c1f584 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,11 +9,6 @@ ifeq ($(CONFIG_OF),y) obj-$(CONFIG_PINCTRL) += devicetree.o endif obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o -obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o -obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o -obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o -obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o -obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o @@ -39,10 +34,6 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o -obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o -obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o -obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o -obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o @@ -64,6 +55,7 @@ obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_PLAT_ORION) += mvebu/ +obj-y += nomadik/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ diff --git a/drivers/pinctrl/nomadik/Kconfig b/drivers/pinctrl/nomadik/Kconfig new file mode 100644 index 000000000000..d48a5aa24a29 --- /dev/null +++ b/drivers/pinctrl/nomadik/Kconfig @@ -0,0 +1,51 @@ +if ARCH_U8500 + +config PINCTRL_ABX500 + bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions" + depends on AB8500_CORE + select GENERIC_PINCONF + help + Select this to enable the ABx500 family IC GPIO driver + +config PINCTRL_AB8500 + bool "AB8500 pin controller driver" + depends on PINCTRL_ABX500 && ARCH_U8500 + +config PINCTRL_AB8540 + bool "AB8540 pin controller driver" + depends on PINCTRL_ABX500 && ARCH_U8500 + +config PINCTRL_AB9540 + bool "AB9540 pin controller driver" + depends on PINCTRL_ABX500 && ARCH_U8500 + +config PINCTRL_AB8505 + bool "AB8505 pin controller driver" + depends on PINCTRL_ABX500 && ARCH_U8500 + +endif + +if (ARCH_U8500 || ARCH_NOMADIK) + +config PINCTRL_NOMADIK + bool "Nomadik pin controller driver" + depends on ARCH_U8500 || ARCH_NOMADIK + select PINMUX + select PINCONF + select GPIOLIB + select OF_GPIO + select GPIOLIB_IRQCHIP + +config PINCTRL_STN8815 + bool "STN8815 pin controller driver" + depends on PINCTRL_NOMADIK && ARCH_NOMADIK + +config PINCTRL_DB8500 + bool "DB8500 pin controller driver" + depends on PINCTRL_NOMADIK && ARCH_U8500 + +config PINCTRL_DB8540 + bool "DB8540 pin controller driver" + depends on PINCTRL_NOMADIK && ARCH_U8500 + +endif diff --git a/drivers/pinctrl/nomadik/Makefile b/drivers/pinctrl/nomadik/Makefile new file mode 100644 index 000000000000..30b27f18cd52 --- /dev/null +++ b/drivers/pinctrl/nomadik/Makefile @@ -0,0 +1,10 @@ +# Nomadik family pin control drivers +obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o +obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o +obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o +obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o +obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o +obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o +obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o +obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o +obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8500.c b/drivers/pinctrl/nomadik/pinctrl-ab8500.c new file mode 100644 index 000000000000..2ac2d0ad3025 --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-ab8500.c @@ -0,0 +1,485 @@ +/* + * Copyright (C) ST-Ericsson SA 2012 + * + * Author: Patrice Chotard for ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include "pinctrl-abx500.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define ABX500_GPIO(offset) (offset) + +#define AB8500_PIN_T10 ABX500_GPIO(1) +#define AB8500_PIN_T9 ABX500_GPIO(2) +#define AB8500_PIN_U9 ABX500_GPIO(3) +#define AB8500_PIN_W2 ABX500_GPIO(4) +/* hole */ +#define AB8500_PIN_Y18 ABX500_GPIO(6) +#define AB8500_PIN_AA20 ABX500_GPIO(7) +#define AB8500_PIN_W18 ABX500_GPIO(8) +#define AB8500_PIN_AA19 ABX500_GPIO(9) +#define AB8500_PIN_U17 ABX500_GPIO(10) +#define AB8500_PIN_AA18 ABX500_GPIO(11) +#define AB8500_PIN_U16 ABX500_GPIO(12) +#define AB8500_PIN_W17 ABX500_GPIO(13) +#define AB8500_PIN_F14 ABX500_GPIO(14) +#define AB8500_PIN_B17 ABX500_GPIO(15) +#define AB8500_PIN_F15 ABX500_GPIO(16) +#define AB8500_PIN_P5 ABX500_GPIO(17) +#define AB8500_PIN_R5 ABX500_GPIO(18) +#define AB8500_PIN_U5 ABX500_GPIO(19) +#define AB8500_PIN_T5 ABX500_GPIO(20) +#define AB8500_PIN_H19 ABX500_GPIO(21) +#define AB8500_PIN_G20 ABX500_GPIO(22) +#define AB8500_PIN_G19 ABX500_GPIO(23) +#define AB8500_PIN_T14 ABX500_GPIO(24) +#define AB8500_PIN_R16 ABX500_GPIO(25) +#define AB8500_PIN_M16 ABX500_GPIO(26) +#define AB8500_PIN_J6 ABX500_GPIO(27) +#define AB8500_PIN_K6 ABX500_GPIO(28) +#define AB8500_PIN_G6 ABX500_GPIO(29) +#define AB8500_PIN_H6 ABX500_GPIO(30) +#define AB8500_PIN_F5 ABX500_GPIO(31) +#define AB8500_PIN_G5 ABX500_GPIO(32) +/* hole */ +#define AB8500_PIN_R17 ABX500_GPIO(34) +#define AB8500_PIN_W15 ABX500_GPIO(35) +#define AB8500_PIN_A17 ABX500_GPIO(36) +#define AB8500_PIN_E15 ABX500_GPIO(37) +#define AB8500_PIN_C17 ABX500_GPIO(38) +#define AB8500_PIN_E16 ABX500_GPIO(39) +#define AB8500_PIN_T19 ABX500_GPIO(40) +#define AB8500_PIN_U19 ABX500_GPIO(41) +#define AB8500_PIN_U2 ABX500_GPIO(42) + +/* indicates the highest GPIO number */ +#define AB8500_GPIO_MAX_NUMBER 42 + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc ab8500_pins[] = { + PINCTRL_PIN(AB8500_PIN_T10, "GPIO1_T10"), + PINCTRL_PIN(AB8500_PIN_T9, "GPIO2_T9"), + PINCTRL_PIN(AB8500_PIN_U9, "GPIO3_U9"), + PINCTRL_PIN(AB8500_PIN_W2, "GPIO4_W2"), + /* hole */ + PINCTRL_PIN(AB8500_PIN_Y18, "GPIO6_Y18"), + PINCTRL_PIN(AB8500_PIN_AA20, "GPIO7_AA20"), + PINCTRL_PIN(AB8500_PIN_W18, "GPIO8_W18"), + PINCTRL_PIN(AB8500_PIN_AA19, "GPIO9_AA19"), + PINCTRL_PIN(AB8500_PIN_U17, "GPIO10_U17"), + PINCTRL_PIN(AB8500_PIN_AA18, "GPIO11_AA18"), + PINCTRL_PIN(AB8500_PIN_U16, "GPIO12_U16"), + PINCTRL_PIN(AB8500_PIN_W17, "GPIO13_W17"), + PINCTRL_PIN(AB8500_PIN_F14, "GPIO14_F14"), + PINCTRL_PIN(AB8500_PIN_B17, "GPIO15_B17"), + PINCTRL_PIN(AB8500_PIN_F15, "GPIO16_F15"), + PINCTRL_PIN(AB8500_PIN_P5, "GPIO17_P5"), + PINCTRL_PIN(AB8500_PIN_R5, "GPIO18_R5"), + PINCTRL_PIN(AB8500_PIN_U5, "GPIO19_U5"), + PINCTRL_PIN(AB8500_PIN_T5, "GPIO20_T5"), + PINCTRL_PIN(AB8500_PIN_H19, "GPIO21_H19"), + PINCTRL_PIN(AB8500_PIN_G20, "GPIO22_G20"), + PINCTRL_PIN(AB8500_PIN_G19, "GPIO23_G19"), + PINCTRL_PIN(AB8500_PIN_T14, "GPIO24_T14"), + PINCTRL_PIN(AB8500_PIN_R16, "GPIO25_R16"), + PINCTRL_PIN(AB8500_PIN_M16, "GPIO26_M16"), + PINCTRL_PIN(AB8500_PIN_J6, "GPIO27_J6"), + PINCTRL_PIN(AB8500_PIN_K6, "GPIO28_K6"), + PINCTRL_PIN(AB8500_PIN_G6, "GPIO29_G6"), + PINCTRL_PIN(AB8500_PIN_H6, "GPIO30_H6"), + PINCTRL_PIN(AB8500_PIN_F5, "GPIO31_F5"), + PINCTRL_PIN(AB8500_PIN_G5, "GPIO32_G5"), + /* hole */ + PINCTRL_PIN(AB8500_PIN_R17, "GPIO34_R17"), + PINCTRL_PIN(AB8500_PIN_W15, "GPIO35_W15"), + PINCTRL_PIN(AB8500_PIN_A17, "GPIO36_A17"), + PINCTRL_PIN(AB8500_PIN_E15, "GPIO37_E15"), + PINCTRL_PIN(AB8500_PIN_C17, "GPIO38_C17"), + PINCTRL_PIN(AB8500_PIN_E16, "GPIO39_E16"), + PINCTRL_PIN(AB8500_PIN_T19, "GPIO40_T19"), + PINCTRL_PIN(AB8500_PIN_U19, "GPIO41_U19"), + PINCTRL_PIN(AB8500_PIN_U2, "GPIO42_U2"), +}; + +/* + * Maps local GPIO offsets to local pin numbers + */ +static const struct abx500_pinrange ab8500_pinranges[] = { + ABX500_PINRANGE(1, 4, ABX500_ALT_A), + ABX500_PINRANGE(6, 4, ABX500_ALT_A), + ABX500_PINRANGE(10, 4, ABX500_DEFAULT), + ABX500_PINRANGE(14, 12, ABX500_ALT_A), + ABX500_PINRANGE(26, 1, ABX500_DEFAULT), + ABX500_PINRANGE(27, 6, ABX500_ALT_A), + ABX500_PINRANGE(34, 1, ABX500_ALT_A), + ABX500_PINRANGE(35, 1, ABX500_DEFAULT), + ABX500_PINRANGE(36, 7, ABX500_ALT_A), +}; + +/* + * Read the pin group names like this: + * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function + * + * The groups are arranged as sets per altfunction column, so we can + * mux in one group at a time by selecting the same altfunction for them + * all. When functions require pins on different altfunctions, you need + * to combine several groups. + */ + +/* default column */ +static const unsigned sysclkreq2_d_1_pins[] = { AB8500_PIN_T10 }; +static const unsigned sysclkreq3_d_1_pins[] = { AB8500_PIN_T9 }; +static const unsigned sysclkreq4_d_1_pins[] = { AB8500_PIN_U9 }; +static const unsigned sysclkreq6_d_1_pins[] = { AB8500_PIN_W2 }; +static const unsigned ycbcr0123_d_1_pins[] = { AB8500_PIN_Y18, AB8500_PIN_AA20, + AB8500_PIN_W18, AB8500_PIN_AA19}; +static const unsigned gpio10_d_1_pins[] = { AB8500_PIN_U17 }; +static const unsigned gpio11_d_1_pins[] = { AB8500_PIN_AA18 }; +static const unsigned gpio12_d_1_pins[] = { AB8500_PIN_U16 }; +static const unsigned gpio13_d_1_pins[] = { AB8500_PIN_W17 }; +static const unsigned pwmout1_d_1_pins[] = { AB8500_PIN_F14 }; +static const unsigned pwmout2_d_1_pins[] = { AB8500_PIN_B17 }; +static const unsigned pwmout3_d_1_pins[] = { AB8500_PIN_F15 }; + +/* audio data interface 1*/ +static const unsigned adi1_d_1_pins[] = { AB8500_PIN_P5, AB8500_PIN_R5, + AB8500_PIN_U5, AB8500_PIN_T5 }; +/* USBUICC */ +static const unsigned usbuicc_d_1_pins[] = { AB8500_PIN_H19, AB8500_PIN_G20, + AB8500_PIN_G19 }; +static const unsigned sysclkreq7_d_1_pins[] = { AB8500_PIN_T14 }; +static const unsigned sysclkreq8_d_1_pins[] = { AB8500_PIN_R16 }; +static const unsigned gpio26_d_1_pins[] = { AB8500_PIN_M16 }; +/* Digital microphone 1 and 2 */ +static const unsigned dmic12_d_1_pins[] = { AB8500_PIN_J6, AB8500_PIN_K6 }; +/* Digital microphone 3 and 4 */ +static const unsigned dmic34_d_1_pins[] = { AB8500_PIN_G6, AB8500_PIN_H6 }; +/* Digital microphone 5 and 6 */ +static const unsigned dmic56_d_1_pins[] = { AB8500_PIN_F5, AB8500_PIN_G5 }; +static const unsigned extcpena_d_1_pins[] = { AB8500_PIN_R17 }; +static const unsigned gpio35_d_1_pins[] = { AB8500_PIN_W15 }; +/* APE SPI */ +static const unsigned apespi_d_1_pins[] = { AB8500_PIN_A17, AB8500_PIN_E15, + AB8500_PIN_C17, AB8500_PIN_E16}; +/* modem SDA/SCL */ +static const unsigned modsclsda_d_1_pins[] = { AB8500_PIN_T19, AB8500_PIN_U19 }; +static const unsigned sysclkreq5_d_1_pins[] = { AB8500_PIN_U2 }; + +/* Altfunction A column */ +static const unsigned gpio1_a_1_pins[] = { AB8500_PIN_T10 }; +static const unsigned gpio2_a_1_pins[] = { AB8500_PIN_T9 }; +static const unsigned gpio3_a_1_pins[] = { AB8500_PIN_U9 }; +static const unsigned gpio4_a_1_pins[] = { AB8500_PIN_W2 }; +static const unsigned gpio6_a_1_pins[] = { AB8500_PIN_Y18 }; +static const unsigned gpio7_a_1_pins[] = { AB8500_PIN_AA20 }; +static const unsigned gpio8_a_1_pins[] = { AB8500_PIN_W18 }; +static const unsigned gpio9_a_1_pins[] = { AB8500_PIN_AA19 }; +/* YCbCr4 YCbCr5 YCbCr6 YCbCr7*/ +static const unsigned ycbcr4567_a_1_pins[] = { AB8500_PIN_U17, AB8500_PIN_AA18, + AB8500_PIN_U16, AB8500_PIN_W17}; +static const unsigned gpio14_a_1_pins[] = { AB8500_PIN_F14 }; +static const unsigned gpio15_a_1_pins[] = { AB8500_PIN_B17 }; +static const unsigned gpio16_a_1_pins[] = { AB8500_PIN_F15 }; +static const unsigned gpio17_a_1_pins[] = { AB8500_PIN_P5 }; +static const unsigned gpio18_a_1_pins[] = { AB8500_PIN_R5 }; +static const unsigned gpio19_a_1_pins[] = { AB8500_PIN_U5 }; +static const unsigned gpio20_a_1_pins[] = { AB8500_PIN_T5 }; +static const unsigned gpio21_a_1_pins[] = { AB8500_PIN_H19 }; +static const unsigned gpio22_a_1_pins[] = { AB8500_PIN_G20 }; +static const unsigned gpio23_a_1_pins[] = { AB8500_PIN_G19 }; +static const unsigned gpio24_a_1_pins[] = { AB8500_PIN_T14 }; +static const unsigned gpio25_a_1_pins[] = { AB8500_PIN_R16 }; +static const unsigned gpio27_a_1_pins[] = { AB8500_PIN_J6 }; +static const unsigned gpio28_a_1_pins[] = { AB8500_PIN_K6 }; +static const unsigned gpio29_a_1_pins[] = { AB8500_PIN_G6 }; +static const unsigned gpio30_a_1_pins[] = { AB8500_PIN_H6 }; +static const unsigned gpio31_a_1_pins[] = { AB8500_PIN_F5 }; +static const unsigned gpio32_a_1_pins[] = { AB8500_PIN_G5 }; +static const unsigned gpio34_a_1_pins[] = { AB8500_PIN_R17 }; +static const unsigned gpio36_a_1_pins[] = { AB8500_PIN_A17 }; +static const unsigned gpio37_a_1_pins[] = { AB8500_PIN_E15 }; +static const unsigned gpio38_a_1_pins[] = { AB8500_PIN_C17 }; +static const unsigned gpio39_a_1_pins[] = { AB8500_PIN_E16 }; +static const unsigned gpio40_a_1_pins[] = { AB8500_PIN_T19 }; +static const unsigned gpio41_a_1_pins[] = { AB8500_PIN_U19 }; +static const unsigned gpio42_a_1_pins[] = { AB8500_PIN_U2 }; + +/* Altfunction B colum */ +static const unsigned hiqclkena_b_1_pins[] = { AB8500_PIN_U17 }; +static const unsigned usbuiccpd_b_1_pins[] = { AB8500_PIN_AA18 }; +static const unsigned i2ctrig1_b_1_pins[] = { AB8500_PIN_U16 }; +static const unsigned i2ctrig2_b_1_pins[] = { AB8500_PIN_W17 }; + +/* Altfunction C column */ +static const unsigned usbvdat_c_1_pins[] = { AB8500_PIN_W17 }; + + +#define AB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct abx500_pingroup ab8500_groups[] = { + /* default column */ + AB8500_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(ycbcr0123_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(gpio12_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(adi1_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(gpio26_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(gpio35_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(apespi_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT), + AB8500_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT), + /* Altfunction A column */ + AB8500_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio4_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio6_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio7_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio8_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio9_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(ycbcr4567_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio15_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio16_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio21_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio22_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio23_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio24_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio25_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio27_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio28_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio29_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio30_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio31_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio32_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio34_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio36_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio37_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio38_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio39_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), + AB8500_PIN_GROUP(gpio42_a_1, ABX500_ALT_A), + /* Altfunction B column */ + AB8500_PIN_GROUP(hiqclkena_b_1, ABX500_ALT_B), + AB8500_PIN_GROUP(usbuiccpd_b_1, ABX500_ALT_B), + AB8500_PIN_GROUP(i2ctrig1_b_1, ABX500_ALT_B), + AB8500_PIN_GROUP(i2ctrig2_b_1, ABX500_ALT_B), + /* Altfunction C column */ + AB8500_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C), +}; + +/* We use this macro to define the groups applicable to a function */ +#define AB8500_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +AB8500_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", + "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1", + "sysclkreq7_d_1", "sysclkreq8_d_1"); +AB8500_FUNC_GROUPS(ycbcr, "ycbcr0123_d_1", "ycbcr4567_a_1"); +AB8500_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1", + "gpio6_a_1", "gpio7_a_1", "gpio8_a_1", "gpio9_a_1", + "gpio10_d_1", "gpio11_d_1", "gpio12_d_1", "gpio13_d_1", + "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", + "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio21_a_1", + "gpio22_a_1", "gpio23_a_1", "gpio24_a_1", "gpio25_a_1", + "gpio26_d_1", "gpio27_a_1", "gpio28_a_1", "gpio29_a_1", + "gpio30_a_1", "gpio31_a_1", "gpio32_a_1", "gpio34_a_1", + "gpio35_d_1", "gpio36_a_1", "gpio37_a_1", "gpio38_a_1", + "gpio39_a_1", "gpio40_a_1", "gpio41_a_1", "gpio42_a_1"); +AB8500_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1"); +AB8500_FUNC_GROUPS(adi1, "adi1_d_1"); +AB8500_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_b_1"); +AB8500_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1"); +AB8500_FUNC_GROUPS(extcpena, "extcpena_d_1"); +AB8500_FUNC_GROUPS(apespi, "apespi_d_1"); +AB8500_FUNC_GROUPS(modsclsda, "modsclsda_d_1"); +AB8500_FUNC_GROUPS(hiqclkena, "hiqclkena_b_1"); +AB8500_FUNC_GROUPS(i2ctrig, "i2ctrig1_b_1", "i2ctrig2_b_1"); +AB8500_FUNC_GROUPS(usbvdat, "usbvdat_c_1"); + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct abx500_function ab8500_functions[] = { + FUNCTION(sysclkreq), + FUNCTION(ycbcr), + FUNCTION(gpio), + FUNCTION(pwmout), + FUNCTION(adi1), + FUNCTION(usbuicc), + FUNCTION(dmic), + FUNCTION(extcpena), + FUNCTION(apespi), + FUNCTION(modsclsda), + FUNCTION(hiqclkena), + FUNCTION(i2ctrig), + FUNCTION(usbvdat), +}; + +/* + * this table translates what's is in the AB8500 specification regarding the + * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). + * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, + * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), + * + * example : + * + * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 0, 1 ,2), + * means that pin AB8500_PIN_W17 (pin 13) supports 4 mux (default/ALT_A, + * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to + * select the mux. ALTA, ALTB and ALTC val indicates values to write in + * ALTERNATFUNC register. We need to specifies these values as SOC + * designers didn't apply the same logic on how to select mux in the + * ABx500 family. + * + * As this pins supports at least ALT_B mux, default mux is + * selected by writing 1 in GPIOSEL bit : + * + * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3 + * default | 1 | 0 | 0 + * alt_A | 0 | 0 | 0 + * alt_B | 0 | 0 | 1 + * alt_C | 0 | 1 | 0 + * + * ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED), + * means that pin AB8500_PIN_W18 (pin 8) supports 2 mux, so only GPIOSEL + * register is used to select the mux. As this pins doesn't support at + * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit : + * + * | GPIOSEL bit=7 | alternatfunc bit2= | alternatfunc bit1= + * default | 0 | 0 | 0 + * alt_A | 1 | 0 | 0 + */ + +static struct +alternate_functions ab8500_alternate_functions[AB8500_GPIO_MAX_NUMBER + 1] = { + ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ + ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ + ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/ + /* bit 4 reserved */ + ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */ + ALTERNATE_FUNCTIONS(6, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO6, altA controlled by bit 5*/ + ALTERNATE_FUNCTIONS(7, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO7, altA controlled by bit 6*/ + ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO8, altA controlled by bit 7*/ + + ALTERNATE_FUNCTIONS(9, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO9, altA controlled by bit 0*/ + ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 0, 1, 0), /* GPIO10, altA and altB controlled by bit 0 */ + ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 1, 0), /* GPIO11, altA and altB controlled by bit 1 */ + ALTERNATE_FUNCTIONS(12, 3, 2, UNUSED, 0, 1, 0), /* GPIO12, altA and altB controlled by bit 2 */ + ALTERNATE_FUNCTIONS(13, 4, 3, 4, 0, 1, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ + ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */ + /* + * pins 17 to 20 are special case, only bit 0 is used to select + * alternate function for these 4 pins. + * bits 1 to 3 are reserved + */ + ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */ + + ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */ + /* pin 26 special case, no alternate function, bit 1 reserved */ + ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO26 */ + ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */ + + ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */ + ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */ + /* pin 35 special case, no alternate function, bit 2 reserved */ + ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO35 */ + ALTERNATE_FUNCTIONS(36, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO36, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(37, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO37, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(38, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO38, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(39, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO39, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */ + + ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */ +}; + +/* + * Only some GPIOs are interrupt capable, and they are + * organized in discontiguous clusters: + * + * GPIO6 to GPIO13 + * GPIO24 and GPIO25 + * GPIO36 to GPIO41 + */ +static struct abx500_gpio_irq_cluster ab8500_gpio_irq_cluster[] = { + GPIO_IRQ_CLUSTER(6, 13, AB8500_INT_GPIO6R), + GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R), + GPIO_IRQ_CLUSTER(36, 41, AB8500_INT_GPIO36R), +}; + +static struct abx500_pinctrl_soc_data ab8500_soc = { + .gpio_ranges = ab8500_pinranges, + .gpio_num_ranges = ARRAY_SIZE(ab8500_pinranges), + .pins = ab8500_pins, + .npins = ARRAY_SIZE(ab8500_pins), + .functions = ab8500_functions, + .nfunctions = ARRAY_SIZE(ab8500_functions), + .groups = ab8500_groups, + .ngroups = ARRAY_SIZE(ab8500_groups), + .alternate_functions = ab8500_alternate_functions, + .gpio_irq_cluster = ab8500_gpio_irq_cluster, + .ngpio_irq_cluster = ARRAY_SIZE(ab8500_gpio_irq_cluster), + .irq_gpio_rising_offset = AB8500_INT_GPIO6R, + .irq_gpio_falling_offset = AB8500_INT_GPIO6F, + .irq_gpio_factor = 1, +}; + +void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc) +{ + *soc = &ab8500_soc; +} diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c new file mode 100644 index 000000000000..bf0ef4ac376f --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c @@ -0,0 +1,381 @@ +/* + * Copyright (C) ST-Ericsson SA 2012 + * + * Author: Patrice Chotard for ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include "pinctrl-abx500.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define ABX500_GPIO(offset) (offset) + +#define AB8505_PIN_N4 ABX500_GPIO(1) +#define AB8505_PIN_R5 ABX500_GPIO(2) +#define AB8505_PIN_P5 ABX500_GPIO(3) +/* hole */ +#define AB8505_PIN_B16 ABX500_GPIO(10) +#define AB8505_PIN_B17 ABX500_GPIO(11) +/* hole */ +#define AB8505_PIN_D17 ABX500_GPIO(13) +#define AB8505_PIN_C16 ABX500_GPIO(14) +/* hole */ +#define AB8505_PIN_P2 ABX500_GPIO(17) +#define AB8505_PIN_N3 ABX500_GPIO(18) +#define AB8505_PIN_T1 ABX500_GPIO(19) +#define AB8505_PIN_P3 ABX500_GPIO(20) +/* hole */ +#define AB8505_PIN_H14 ABX500_GPIO(34) +/* hole */ +#define AB8505_PIN_J15 ABX500_GPIO(40) +#define AB8505_PIN_J14 ABX500_GPIO(41) +/* hole */ +#define AB8505_PIN_L4 ABX500_GPIO(50) +/* hole */ +#define AB8505_PIN_D16 ABX500_GPIO(52) +#define AB8505_PIN_D15 ABX500_GPIO(53) + +/* indicates the higher GPIO number */ +#define AB8505_GPIO_MAX_NUMBER 53 + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc ab8505_pins[] = { + PINCTRL_PIN(AB8505_PIN_N4, "GPIO1_N4"), + PINCTRL_PIN(AB8505_PIN_R5, "GPIO2_R5"), + PINCTRL_PIN(AB8505_PIN_P5, "GPIO3_P5"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_B16, "GPIO10_B16"), + PINCTRL_PIN(AB8505_PIN_B17, "GPIO11_B17"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_D17, "GPIO13_D17"), + PINCTRL_PIN(AB8505_PIN_C16, "GPIO14_C16"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_P2, "GPIO17_P2"), + PINCTRL_PIN(AB8505_PIN_N3, "GPIO18_N3"), + PINCTRL_PIN(AB8505_PIN_T1, "GPIO19_T1"), + PINCTRL_PIN(AB8505_PIN_P3, "GPIO20_P3"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_H14, "GPIO34_H14"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_J15, "GPIO40_J15"), + PINCTRL_PIN(AB8505_PIN_J14, "GPIO41_J14"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_L4, "GPIO50_L4"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_D16, "GPIO52_D16"), + PINCTRL_PIN(AB8505_PIN_D15, "GPIO53_D15"), +}; + +/* + * Maps local GPIO offsets to local pin numbers + */ +static const struct abx500_pinrange ab8505_pinranges[] = { + ABX500_PINRANGE(1, 3, ABX500_ALT_A), + ABX500_PINRANGE(10, 2, ABX500_DEFAULT), + ABX500_PINRANGE(13, 1, ABX500_DEFAULT), + ABX500_PINRANGE(14, 1, ABX500_ALT_A), + ABX500_PINRANGE(17, 4, ABX500_ALT_A), + ABX500_PINRANGE(34, 1, ABX500_ALT_A), + ABX500_PINRANGE(40, 2, ABX500_ALT_A), + ABX500_PINRANGE(50, 1, ABX500_DEFAULT), + ABX500_PINRANGE(52, 2, ABX500_ALT_A), +}; + +/* + * Read the pin group names like this: + * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function + * + * The groups are arranged as sets per altfunction column, so we can + * mux in one group at a time by selecting the same altfunction for them + * all. When functions require pins on different altfunctions, you need + * to combine several groups. + */ + +/* default column */ +static const unsigned sysclkreq2_d_1_pins[] = { AB8505_PIN_N4 }; +static const unsigned sysclkreq3_d_1_pins[] = { AB8505_PIN_R5 }; +static const unsigned sysclkreq4_d_1_pins[] = { AB8505_PIN_P5 }; +static const unsigned gpio10_d_1_pins[] = { AB8505_PIN_B16 }; +static const unsigned gpio11_d_1_pins[] = { AB8505_PIN_B17 }; +static const unsigned gpio13_d_1_pins[] = { AB8505_PIN_D17 }; +static const unsigned pwmout1_d_1_pins[] = { AB8505_PIN_C16 }; +/* audio data interface 2*/ +static const unsigned adi2_d_1_pins[] = { AB8505_PIN_P2, AB8505_PIN_N3, + AB8505_PIN_T1, AB8505_PIN_P3 }; +static const unsigned extcpena_d_1_pins[] = { AB8505_PIN_H14 }; +/* modem SDA/SCL */ +static const unsigned modsclsda_d_1_pins[] = { AB8505_PIN_J15, AB8505_PIN_J14 }; +static const unsigned gpio50_d_1_pins[] = { AB8505_PIN_L4 }; +static const unsigned resethw_d_1_pins[] = { AB8505_PIN_D16 }; +static const unsigned service_d_1_pins[] = { AB8505_PIN_D15 }; + +/* Altfunction A column */ +static const unsigned gpio1_a_1_pins[] = { AB8505_PIN_N4 }; +static const unsigned gpio2_a_1_pins[] = { AB8505_PIN_R5 }; +static const unsigned gpio3_a_1_pins[] = { AB8505_PIN_P5 }; +static const unsigned hiqclkena_a_1_pins[] = { AB8505_PIN_B16 }; +static const unsigned pdmclk_a_1_pins[] = { AB8505_PIN_B17 }; +static const unsigned uarttxdata_a_1_pins[] = { AB8505_PIN_D17 }; +static const unsigned gpio14_a_1_pins[] = { AB8505_PIN_C16 }; +static const unsigned gpio17_a_1_pins[] = { AB8505_PIN_P2 }; +static const unsigned gpio18_a_1_pins[] = { AB8505_PIN_N3 }; +static const unsigned gpio19_a_1_pins[] = { AB8505_PIN_T1 }; +static const unsigned gpio20_a_1_pins[] = { AB8505_PIN_P3 }; +static const unsigned gpio34_a_1_pins[] = { AB8505_PIN_H14 }; +static const unsigned gpio40_a_1_pins[] = { AB8505_PIN_J15 }; +static const unsigned gpio41_a_1_pins[] = { AB8505_PIN_J14 }; +static const unsigned uartrxdata_a_1_pins[] = { AB8505_PIN_J14 }; +static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 }; +static const unsigned gpio52_a_1_pins[] = { AB8505_PIN_D16 }; +static const unsigned gpio53_a_1_pins[] = { AB8505_PIN_D15 }; + +/* Altfunction B colum */ +static const unsigned pdmdata_b_1_pins[] = { AB8505_PIN_B16 }; +static const unsigned extvibrapwm1_b_1_pins[] = { AB8505_PIN_D17 }; +static const unsigned extvibrapwm2_b_1_pins[] = { AB8505_PIN_L4 }; + +/* Altfunction C column */ +static const unsigned usbvdat_c_1_pins[] = { AB8505_PIN_D17 }; + +#define AB8505_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct abx500_pingroup ab8505_groups[] = { + AB8505_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(adi2_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(resethw_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(service_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(uarttxdata_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio34_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(uartrxdata_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B), + AB8505_PIN_GROUP(extvibrapwm1_b_1, ABX500_ALT_B), + AB8505_PIN_GROUP(extvibrapwm2_b_1, ABX500_ALT_B), + AB8505_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C), +}; + +/* We use this macro to define the groups applicable to a function */ +#define AB8505_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +AB8505_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", + "sysclkreq4_d_1"); +AB8505_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", + "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1", + "gpio17_a_1", "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", + "gpio34_a_1", "gpio40_a_1", "gpio41_a_1", "gpio50_d_1", + "gpio52_a_1", "gpio53_a_1"); +AB8505_FUNC_GROUPS(pwmout, "pwmout1_d_1"); +AB8505_FUNC_GROUPS(adi2, "adi2_d_1"); +AB8505_FUNC_GROUPS(extcpena, "extcpena_d_1"); +AB8505_FUNC_GROUPS(modsclsda, "modsclsda_d_1"); +AB8505_FUNC_GROUPS(resethw, "resethw_d_1"); +AB8505_FUNC_GROUPS(service, "service_d_1"); +AB8505_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1"); +AB8505_FUNC_GROUPS(pdm, "pdmclk_a_1", "pdmdata_b_1"); +AB8505_FUNC_GROUPS(uartdata, "uarttxdata_a_1", "uartrxdata_a_1"); +AB8505_FUNC_GROUPS(extvibra, "extvibrapwm1_b_1", "extvibrapwm2_b_1"); +AB8505_FUNC_GROUPS(usbvdat, "usbvdat_c_1"); + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct abx500_function ab8505_functions[] = { + FUNCTION(sysclkreq), + FUNCTION(gpio), + FUNCTION(pwmout), + FUNCTION(adi2), + FUNCTION(extcpena), + FUNCTION(modsclsda), + FUNCTION(resethw), + FUNCTION(service), + FUNCTION(hiqclkena), + FUNCTION(pdm), + FUNCTION(uartdata), + FUNCTION(extvibra), + FUNCTION(extvibra), + FUNCTION(usbvdat), +}; + +/* + * this table translates what's is in the AB8505 specification regarding the + * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). + * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, + * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), + * + * example : + * + * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), + * means that pin AB8505_PIN_D18 (pin 13) supports 4 mux (default/ALT_A, + * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to + * select the mux. ALTA, ALTB and ALTC val indicates values to write in + * ALTERNATFUNC register. We need to specifies these values as SOC + * designers didn't apply the same logic on how to select mux in the + * ABx500 family. + * + * As this pins supports at least ALT_B mux, default mux is + * selected by writing 1 in GPIOSEL bit : + * + * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3 + * default | 1 | 0 | 0 + * alt_A | 0 | 0 | 1 + * alt_B | 0 | 0 | 0 + * alt_C | 0 | 1 | 0 + * + * ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED), + * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL + * register is used to select the mux. As this pins doesn't support at + * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit : + * + * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1= + * default | 0 | 0 | 0 + * alt_A | 1 | 0 | 0 + */ + +static struct +alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1] = { + ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ + ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ + ALTERNATE_FUNCTIONS(4, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO4, bit 3 reserved */ + ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5, bit 4 reserved */ + ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6, bit 5 reserved */ + ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7, bit 6 reserved */ + ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8, bit 7 reserved */ + + ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */ + ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */ + ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */ + ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ + ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */ + ALTERNATE_FUNCTIONS(16, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 7 reserved */ + /* + * pins 17 to 20 are special case, only bit 0 is used to select + * alternate function for these 4 pins. + * bits 1 to 3 are reserved + */ + ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21, bit 4 reserved */ + ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22, bit 5 reserved */ + ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23, bit 6 reserved */ + ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24, bit 7 reserved */ + + ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25, bit 0 reserved */ + ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26, bit 1 reserved */ + ALTERNATE_FUNCTIONS(27, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO27, bit 2 reserved */ + ALTERNATE_FUNCTIONS(28, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO28, bit 3 reserved */ + ALTERNATE_FUNCTIONS(29, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO29, bit 4 reserved */ + ALTERNATE_FUNCTIONS(30, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO30, bit 5 reserved */ + ALTERNATE_FUNCTIONS(31, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO31, bit 6 reserved */ + ALTERNATE_FUNCTIONS(32, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO32, bit 7 reserved */ + + ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33, bit 0 reserved */ + ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35, bit 2 reserved */ + ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36, bit 2 reserved */ + ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37, bit 2 reserved */ + ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38, bit 2 reserved */ + ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39, bit 2 reserved */ + ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7*/ + + ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(42, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO42, bit 1 reserved */ + ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43, bit 2 reserved */ + ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44, bit 3 reserved */ + ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45, bit 4 reserved */ + ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46, bit 5 reserved */ + ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47, bit 6 reserved */ + ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48, bit 7 reserved */ + + ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */ + ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(51, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */ + ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */ +}; + +/* + * For AB8505 Only some GPIOs are interrupt capable, and they are + * organized in discontiguous clusters: + * + * GPIO10 to GPIO11 + * GPIO13 + * GPIO40 and GPIO41 + * GPIO50 + * GPIO52 to GPIO53 + */ +static struct abx500_gpio_irq_cluster ab8505_gpio_irq_cluster[] = { + GPIO_IRQ_CLUSTER(10, 11, AB8500_INT_GPIO10R), + GPIO_IRQ_CLUSTER(13, 13, AB8500_INT_GPIO13R), + GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R), + GPIO_IRQ_CLUSTER(50, 50, AB9540_INT_GPIO50R), + GPIO_IRQ_CLUSTER(52, 53, AB9540_INT_GPIO52R), +}; + +static struct abx500_pinctrl_soc_data ab8505_soc = { + .gpio_ranges = ab8505_pinranges, + .gpio_num_ranges = ARRAY_SIZE(ab8505_pinranges), + .pins = ab8505_pins, + .npins = ARRAY_SIZE(ab8505_pins), + .functions = ab8505_functions, + .nfunctions = ARRAY_SIZE(ab8505_functions), + .groups = ab8505_groups, + .ngroups = ARRAY_SIZE(ab8505_groups), + .alternate_functions = ab8505_alternate_functions, + .gpio_irq_cluster = ab8505_gpio_irq_cluster, + .ngpio_irq_cluster = ARRAY_SIZE(ab8505_gpio_irq_cluster), + .irq_gpio_rising_offset = AB8500_INT_GPIO6R, + .irq_gpio_falling_offset = AB8500_INT_GPIO6F, + .irq_gpio_factor = 1, +}; + +void +abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc) +{ + *soc = &ab8505_soc; +} diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8540.c b/drivers/pinctrl/nomadik/pinctrl-ab8540.c new file mode 100644 index 000000000000..9867535d49c1 --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-ab8540.c @@ -0,0 +1,408 @@ +/* + * Copyright (C) ST-Ericsson SA 2012 + * + * Author: Patrice Chotard for ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include "pinctrl-abx500.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define ABX500_GPIO(offset) (offset) + +#define AB8540_PIN_J16 ABX500_GPIO(1) +#define AB8540_PIN_D17 ABX500_GPIO(2) +#define AB8540_PIN_C12 ABX500_GPIO(3) +#define AB8540_PIN_G12 ABX500_GPIO(4) +/* hole */ +#define AB8540_PIN_D16 ABX500_GPIO(14) +#define AB8540_PIN_F15 ABX500_GPIO(15) +#define AB8540_PIN_J8 ABX500_GPIO(16) +#define AB8540_PIN_K16 ABX500_GPIO(17) +#define AB8540_PIN_G15 ABX500_GPIO(18) +#define AB8540_PIN_F17 ABX500_GPIO(19) +#define AB8540_PIN_E17 ABX500_GPIO(20) +/* hole */ +#define AB8540_PIN_AA16 ABX500_GPIO(27) +#define AB8540_PIN_W18 ABX500_GPIO(28) +#define AB8540_PIN_Y15 ABX500_GPIO(29) +#define AB8540_PIN_W16 ABX500_GPIO(30) +#define AB8540_PIN_V15 ABX500_GPIO(31) +#define AB8540_PIN_W17 ABX500_GPIO(32) +/* hole */ +#define AB8540_PIN_D12 ABX500_GPIO(42) +#define AB8540_PIN_P4 ABX500_GPIO(43) +#define AB8540_PIN_AB1 ABX500_GPIO(44) +#define AB8540_PIN_K7 ABX500_GPIO(45) +#define AB8540_PIN_L7 ABX500_GPIO(46) +#define AB8540_PIN_G10 ABX500_GPIO(47) +#define AB8540_PIN_K12 ABX500_GPIO(48) +/* hole */ +#define AB8540_PIN_N8 ABX500_GPIO(51) +#define AB8540_PIN_P12 ABX500_GPIO(52) +#define AB8540_PIN_K8 ABX500_GPIO(53) +#define AB8540_PIN_J11 ABX500_GPIO(54) +#define AB8540_PIN_AC2 ABX500_GPIO(55) +#define AB8540_PIN_AB2 ABX500_GPIO(56) + +/* indicates the highest GPIO number */ +#define AB8540_GPIO_MAX_NUMBER 56 + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc ab8540_pins[] = { + PINCTRL_PIN(AB8540_PIN_J16, "GPIO1_J16"), + PINCTRL_PIN(AB8540_PIN_D17, "GPIO2_D17"), + PINCTRL_PIN(AB8540_PIN_C12, "GPIO3_C12"), + PINCTRL_PIN(AB8540_PIN_G12, "GPIO4_G12"), + /* hole */ + PINCTRL_PIN(AB8540_PIN_D16, "GPIO14_D16"), + PINCTRL_PIN(AB8540_PIN_F15, "GPIO15_F15"), + PINCTRL_PIN(AB8540_PIN_J8, "GPIO16_J8"), + PINCTRL_PIN(AB8540_PIN_K16, "GPIO17_K16"), + PINCTRL_PIN(AB8540_PIN_G15, "GPIO18_G15"), + PINCTRL_PIN(AB8540_PIN_F17, "GPIO19_F17"), + PINCTRL_PIN(AB8540_PIN_E17, "GPIO20_E17"), + /* hole */ + PINCTRL_PIN(AB8540_PIN_AA16, "GPIO27_AA16"), + PINCTRL_PIN(AB8540_PIN_W18, "GPIO28_W18"), + PINCTRL_PIN(AB8540_PIN_Y15, "GPIO29_Y15"), + PINCTRL_PIN(AB8540_PIN_W16, "GPIO30_W16"), + PINCTRL_PIN(AB8540_PIN_V15, "GPIO31_V15"), + PINCTRL_PIN(AB8540_PIN_W17, "GPIO32_W17"), + /* hole */ + PINCTRL_PIN(AB8540_PIN_D12, "GPIO42_D12"), + PINCTRL_PIN(AB8540_PIN_P4, "GPIO43_P4"), + PINCTRL_PIN(AB8540_PIN_AB1, "GPIO44_AB1"), + PINCTRL_PIN(AB8540_PIN_K7, "GPIO45_K7"), + PINCTRL_PIN(AB8540_PIN_L7, "GPIO46_L7"), + PINCTRL_PIN(AB8540_PIN_G10, "GPIO47_G10"), + PINCTRL_PIN(AB8540_PIN_K12, "GPIO48_K12"), + /* hole */ + PINCTRL_PIN(AB8540_PIN_N8, "GPIO51_N8"), + PINCTRL_PIN(AB8540_PIN_P12, "GPIO52_P12"), + PINCTRL_PIN(AB8540_PIN_K8, "GPIO53_K8"), + PINCTRL_PIN(AB8540_PIN_J11, "GPIO54_J11"), + PINCTRL_PIN(AB8540_PIN_AC2, "GPIO55_AC2"), + PINCTRL_PIN(AB8540_PIN_AB2, "GPIO56_AB2"), +}; + +/* + * Maps local GPIO offsets to local pin numbers + */ +static const struct abx500_pinrange ab8540_pinranges[] = { + ABX500_PINRANGE(1, 4, ABX500_ALT_A), + ABX500_PINRANGE(14, 7, ABX500_ALT_A), + ABX500_PINRANGE(27, 6, ABX500_ALT_A), + ABX500_PINRANGE(42, 7, ABX500_ALT_A), + ABX500_PINRANGE(51, 6, ABX500_ALT_A), +}; + +/* + * Read the pin group names like this: + * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function + * + * The groups are arranged as sets per altfunction column, so we can + * mux in one group at a time by selecting the same altfunction for them + * all. When functions require pins on different altfunctions, you need + * to combine several groups. + */ + +/* default column */ +static const unsigned sysclkreq2_d_1_pins[] = { AB8540_PIN_J16 }; +static const unsigned sysclkreq3_d_1_pins[] = { AB8540_PIN_D17 }; +static const unsigned sysclkreq4_d_1_pins[] = { AB8540_PIN_C12 }; +static const unsigned sysclkreq6_d_1_pins[] = { AB8540_PIN_G12 }; +static const unsigned pwmout1_d_1_pins[] = { AB8540_PIN_D16 }; +static const unsigned pwmout2_d_1_pins[] = { AB8540_PIN_F15 }; +static const unsigned pwmout3_d_1_pins[] = { AB8540_PIN_J8 }; + +/* audio data interface 1*/ +static const unsigned adi1_d_1_pins[] = { AB8540_PIN_K16, AB8540_PIN_G15, + AB8540_PIN_F17, AB8540_PIN_E17 }; +/* Digital microphone 1 and 2 */ +static const unsigned dmic12_d_1_pins[] = { AB8540_PIN_AA16, AB8540_PIN_W18 }; +/* Digital microphone 3 and 4 */ +static const unsigned dmic34_d_1_pins[] = { AB8540_PIN_Y15, AB8540_PIN_W16 }; +/* Digital microphone 5 and 6 */ +static const unsigned dmic56_d_1_pins[] = { AB8540_PIN_V15, AB8540_PIN_W17 }; +static const unsigned sysclkreq5_d_1_pins[] = { AB8540_PIN_D12 }; +static const unsigned batremn_d_1_pins[] = { AB8540_PIN_P4 }; +static const unsigned service_d_1_pins[] = { AB8540_PIN_AB1 }; +static const unsigned pwrctrl0_d_1_pins[] = { AB8540_PIN_K7 }; +static const unsigned pwrctrl1_d_1_pins[] = { AB8540_PIN_L7 }; +static const unsigned pwmextvibra1_d_1_pins[] = { AB8540_PIN_G10 }; +static const unsigned pwmextvibra2_d_1_pins[] = { AB8540_PIN_K12 }; +static const unsigned gpio1_vbat_d_1_pins[] = { AB8540_PIN_N8 }; +static const unsigned gpio2_vbat_d_1_pins[] = { AB8540_PIN_P12 }; +static const unsigned gpio3_vbat_d_1_pins[] = { AB8540_PIN_K8 }; +static const unsigned gpio4_vbat_d_1_pins[] = { AB8540_PIN_J11 }; +static const unsigned pdmclkdat_d_1_pins[] = { AB8540_PIN_AC2, AB8540_PIN_AB2 }; + +/* Altfunction A column */ +static const unsigned gpio1_a_1_pins[] = { AB8540_PIN_J16 }; +static const unsigned gpio2_a_1_pins[] = { AB8540_PIN_D17 }; +static const unsigned gpio3_a_1_pins[] = { AB8540_PIN_C12 }; +static const unsigned gpio4_a_1_pins[] = { AB8540_PIN_G12 }; +static const unsigned gpio14_a_1_pins[] = { AB8540_PIN_D16 }; +static const unsigned gpio15_a_1_pins[] = { AB8540_PIN_F15 }; +static const unsigned gpio16_a_1_pins[] = { AB8540_PIN_J8 }; +static const unsigned gpio17_a_1_pins[] = { AB8540_PIN_K16 }; +static const unsigned gpio18_a_1_pins[] = { AB8540_PIN_G15 }; +static const unsigned gpio19_a_1_pins[] = { AB8540_PIN_F17 }; +static const unsigned gpio20_a_1_pins[] = { AB8540_PIN_E17 }; +static const unsigned gpio27_a_1_pins[] = { AB8540_PIN_AA16 }; +static const unsigned gpio28_a_1_pins[] = { AB8540_PIN_W18 }; +static const unsigned gpio29_a_1_pins[] = { AB8540_PIN_Y15 }; +static const unsigned gpio30_a_1_pins[] = { AB8540_PIN_W16 }; +static const unsigned gpio31_a_1_pins[] = { AB8540_PIN_V15 }; +static const unsigned gpio32_a_1_pins[] = { AB8540_PIN_W17 }; +static const unsigned gpio42_a_1_pins[] = { AB8540_PIN_D12 }; +static const unsigned gpio43_a_1_pins[] = { AB8540_PIN_P4 }; +static const unsigned gpio44_a_1_pins[] = { AB8540_PIN_AB1 }; +static const unsigned gpio45_a_1_pins[] = { AB8540_PIN_K7 }; +static const unsigned gpio46_a_1_pins[] = { AB8540_PIN_L7 }; +static const unsigned gpio47_a_1_pins[] = { AB8540_PIN_G10 }; +static const unsigned gpio48_a_1_pins[] = { AB8540_PIN_K12 }; +static const unsigned gpio51_a_1_pins[] = { AB8540_PIN_N8 }; +static const unsigned gpio52_a_1_pins[] = { AB8540_PIN_P12 }; +static const unsigned gpio53_a_1_pins[] = { AB8540_PIN_K8 }; +static const unsigned gpio54_a_1_pins[] = { AB8540_PIN_J11 }; +static const unsigned gpio55_a_1_pins[] = { AB8540_PIN_AC2 }; +static const unsigned gpio56_a_1_pins[] = { AB8540_PIN_AB2 }; + +#define AB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct abx500_pingroup ab8540_groups[] = { + /* default column */ + AB8540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(service_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(pwrctrl0_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(pwrctrl1_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(pwmextvibra1_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(pwmextvibra2_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(gpio1_vbat_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(gpio2_vbat_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(gpio3_vbat_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(gpio4_vbat_d_1, ABX500_DEFAULT), + AB8540_PIN_GROUP(pdmclkdat_d_1, ABX500_DEFAULT), + /* Altfunction A column */ + AB8540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio43_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio44_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio45_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio46_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio47_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio48_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio54_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio55_a_1, ABX500_ALT_A), + AB8540_PIN_GROUP(gpio56_a_1, ABX500_ALT_A), +}; + +/* We use this macro to define the groups applicable to a function */ +#define AB8540_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +AB8540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", + "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1"); +AB8540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1", + "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", + "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio27_a_1", + "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1", + "gpio32_a_1", "gpio42_a_1", "gpio43_a_1", "gpio44_a_1", + "gpio45_a_1", "gpio46_a_1", "gpio47_a_1", "gpio48_a_1", + "gpio51_a_1", "gpio52_a_1", "gpio53_a_1", "gpio54_a_1", + "gpio55_a_1", "gpio56_a_1"); +AB8540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1"); +AB8540_FUNC_GROUPS(adi1, "adi1_d_1"); +AB8540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1"); +AB8540_FUNC_GROUPS(batremn, "batremn_d_1"); +AB8540_FUNC_GROUPS(service, "service_d_1"); +AB8540_FUNC_GROUPS(pwrctrl, "pwrctrl0_d_1", "pwrctrl1_d_1"); +AB8540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_d_1", "pwmextvibra2_d_1"); +AB8540_FUNC_GROUPS(gpio_vbat, "gpio1_vbat_d_1", "gpio2_vbat_d_1", + "gpio3_vbat_d_1", "gpio4_vbat_d_1"); +AB8540_FUNC_GROUPS(pdm, "pdmclkdat_d_1"); + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct abx500_function ab8540_functions[] = { + FUNCTION(sysclkreq), + FUNCTION(gpio), + FUNCTION(pwmout), + FUNCTION(adi1), + FUNCTION(dmic), + FUNCTION(batremn), + FUNCTION(service), + FUNCTION(pwrctrl), + FUNCTION(pwmextvibra), + FUNCTION(gpio_vbat), + FUNCTION(pdm), +}; + +/* + * this table translates what's is in the AB8540 specification regarding the + * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). + * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, + * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), + * AB8540 only supports DEFAULT and ALTA functions, so ALTERNATFUNC + * registers is not used + * + */ + +static struct +alternate_functions ab8540_alternate_functions[AB8540_GPIO_MAX_NUMBER + 1] = { + /* GPIOSEL1 - bit 4-7 reserved */ + ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ + ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ + ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/ + ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */ + ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */ + ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */ + ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */ + /* GPIOSEL2 - bit 0-4 reserved */ + ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */ + ALTERNATE_FUNCTIONS(10, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO10 */ + ALTERNATE_FUNCTIONS(11, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO11 */ + ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */ + ALTERNATE_FUNCTIONS(13, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO13 */ + ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */ + /* GPIOSEL3 - bit 4-7 reserved */ + ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(18, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(19, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(20, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21 */ + ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22 */ + ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23 */ + ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24 */ + /* GPIOSEL4 - bit 0-1 reserved */ + ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25 */ + ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */ + ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */ + /* GPIOSEL5 - bit 0-7 reserved */ + ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */ + ALTERNATE_FUNCTIONS(34, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO34 */ + ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */ + ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */ + ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */ + ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */ + ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */ + ALTERNATE_FUNCTIONS(40, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO40 */ + /* GPIOSEL6 - bit 0 reserved */ + ALTERNATE_FUNCTIONS(41, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO41 */ + ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(43, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO43, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(44, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO44, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(45, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO45, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(46, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO46, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(47, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO47, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(48, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO48, altA controlled by bit 7 */ + /* GPIOSEL7 - bit 0-1 reserved */ + ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */ + ALTERNATE_FUNCTIONS(50, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO50 */ + ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(55, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO55, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(56, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO56, altA controlled by bit 7 */ +}; + +static struct pullud ab8540_pullud = { + .first_pin = 51, /* GPIO1_VBAT */ + .last_pin = 54, /* GPIO4_VBAT */ +}; + +/* + * For AB8540 Only some GPIOs are interrupt capable: + * GPIO43 to GPIO44 + * GPIO51 to GPIO54 + */ +static struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = { + GPIO_IRQ_CLUSTER(43, 43, AB8540_INT_GPIO43F), + GPIO_IRQ_CLUSTER(44, 44, AB8540_INT_GPIO44F), + GPIO_IRQ_CLUSTER(51, 54, AB9540_INT_GPIO51R), +}; + +static struct abx500_pinctrl_soc_data ab8540_soc = { + .gpio_ranges = ab8540_pinranges, + .gpio_num_ranges = ARRAY_SIZE(ab8540_pinranges), + .pins = ab8540_pins, + .npins = ARRAY_SIZE(ab8540_pins), + .functions = ab8540_functions, + .nfunctions = ARRAY_SIZE(ab8540_functions), + .groups = ab8540_groups, + .ngroups = ARRAY_SIZE(ab8540_groups), + .alternate_functions = ab8540_alternate_functions, + .pullud = &ab8540_pullud, + .gpio_irq_cluster = ab8540_gpio_irq_cluster, + .ngpio_irq_cluster = ARRAY_SIZE(ab8540_gpio_irq_cluster), + .irq_gpio_rising_offset = AB8540_INT_GPIO43R, + .irq_gpio_falling_offset = AB8540_INT_GPIO43F, + .irq_gpio_factor = 2, +}; + +void +abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc) +{ + *soc = &ab8540_soc; +} diff --git a/drivers/pinctrl/nomadik/pinctrl-ab9540.c b/drivers/pinctrl/nomadik/pinctrl-ab9540.c new file mode 100644 index 000000000000..1a281ca95dac --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-ab9540.c @@ -0,0 +1,486 @@ +/* + * Copyright (C) ST-Ericsson SA 2012 + * + * Author: Patrice Chotard for ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include "pinctrl-abx500.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define ABX500_GPIO(offset) (offset) + +#define AB9540_PIN_R4 ABX500_GPIO(1) +#define AB9540_PIN_V3 ABX500_GPIO(2) +#define AB9540_PIN_T4 ABX500_GPIO(3) +#define AB9540_PIN_T5 ABX500_GPIO(4) +/* hole */ +#define AB9540_PIN_B18 ABX500_GPIO(10) +#define AB9540_PIN_C18 ABX500_GPIO(11) +/* hole */ +#define AB9540_PIN_D18 ABX500_GPIO(13) +#define AB9540_PIN_B19 ABX500_GPIO(14) +#define AB9540_PIN_C19 ABX500_GPIO(15) +#define AB9540_PIN_D19 ABX500_GPIO(16) +#define AB9540_PIN_R3 ABX500_GPIO(17) +#define AB9540_PIN_T2 ABX500_GPIO(18) +#define AB9540_PIN_U2 ABX500_GPIO(19) +#define AB9540_PIN_V2 ABX500_GPIO(20) +#define AB9540_PIN_N17 ABX500_GPIO(21) +#define AB9540_PIN_N16 ABX500_GPIO(22) +#define AB9540_PIN_M19 ABX500_GPIO(23) +#define AB9540_PIN_T3 ABX500_GPIO(24) +#define AB9540_PIN_W2 ABX500_GPIO(25) +/* hole */ +#define AB9540_PIN_H4 ABX500_GPIO(27) +#define AB9540_PIN_F1 ABX500_GPIO(28) +#define AB9540_PIN_F4 ABX500_GPIO(29) +#define AB9540_PIN_F2 ABX500_GPIO(30) +#define AB9540_PIN_E4 ABX500_GPIO(31) +#define AB9540_PIN_F3 ABX500_GPIO(32) +/* hole */ +#define AB9540_PIN_J13 ABX500_GPIO(34) +/* hole */ +#define AB9540_PIN_L17 ABX500_GPIO(40) +#define AB9540_PIN_L16 ABX500_GPIO(41) +#define AB9540_PIN_W3 ABX500_GPIO(42) +#define AB9540_PIN_N4 ABX500_GPIO(50) +#define AB9540_PIN_G12 ABX500_GPIO(51) +#define AB9540_PIN_E17 ABX500_GPIO(52) +#define AB9540_PIN_D11 ABX500_GPIO(53) +#define AB9540_PIN_M18 ABX500_GPIO(54) + +/* indicates the highest GPIO number */ +#define AB9540_GPIO_MAX_NUMBER 54 + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc ab9540_pins[] = { + PINCTRL_PIN(AB9540_PIN_R4, "GPIO1_R4"), + PINCTRL_PIN(AB9540_PIN_V3, "GPIO2_V3"), + PINCTRL_PIN(AB9540_PIN_T4, "GPIO3_T4"), + PINCTRL_PIN(AB9540_PIN_T5, "GPIO4_T5"), + /* hole */ + PINCTRL_PIN(AB9540_PIN_B18, "GPIO10_B18"), + PINCTRL_PIN(AB9540_PIN_C18, "GPIO11_C18"), + /* hole */ + PINCTRL_PIN(AB9540_PIN_D18, "GPIO13_D18"), + PINCTRL_PIN(AB9540_PIN_B19, "GPIO14_B19"), + PINCTRL_PIN(AB9540_PIN_C19, "GPIO15_C19"), + PINCTRL_PIN(AB9540_PIN_D19, "GPIO16_D19"), + PINCTRL_PIN(AB9540_PIN_R3, "GPIO17_R3"), + PINCTRL_PIN(AB9540_PIN_T2, "GPIO18_T2"), + PINCTRL_PIN(AB9540_PIN_U2, "GPIO19_U2"), + PINCTRL_PIN(AB9540_PIN_V2, "GPIO20_V2"), + PINCTRL_PIN(AB9540_PIN_N17, "GPIO21_N17"), + PINCTRL_PIN(AB9540_PIN_N16, "GPIO22_N16"), + PINCTRL_PIN(AB9540_PIN_M19, "GPIO23_M19"), + PINCTRL_PIN(AB9540_PIN_T3, "GPIO24_T3"), + PINCTRL_PIN(AB9540_PIN_W2, "GPIO25_W2"), + /* hole */ + PINCTRL_PIN(AB9540_PIN_H4, "GPIO27_H4"), + PINCTRL_PIN(AB9540_PIN_F1, "GPIO28_F1"), + PINCTRL_PIN(AB9540_PIN_F4, "GPIO29_F4"), + PINCTRL_PIN(AB9540_PIN_F2, "GPIO30_F2"), + PINCTRL_PIN(AB9540_PIN_E4, "GPIO31_E4"), + PINCTRL_PIN(AB9540_PIN_F3, "GPIO32_F3"), + /* hole */ + PINCTRL_PIN(AB9540_PIN_J13, "GPIO34_J13"), + /* hole */ + PINCTRL_PIN(AB9540_PIN_L17, "GPIO40_L17"), + PINCTRL_PIN(AB9540_PIN_L16, "GPIO41_L16"), + PINCTRL_PIN(AB9540_PIN_W3, "GPIO42_W3"), + PINCTRL_PIN(AB9540_PIN_N4, "GPIO50_N4"), + PINCTRL_PIN(AB9540_PIN_G12, "GPIO51_G12"), + PINCTRL_PIN(AB9540_PIN_E17, "GPIO52_E17"), + PINCTRL_PIN(AB9540_PIN_D11, "GPIO53_D11"), + PINCTRL_PIN(AB9540_PIN_M18, "GPIO60_M18"), +}; + +/* + * Maps local GPIO offsets to local pin numbers + */ +static const struct abx500_pinrange ab9540_pinranges[] = { + ABX500_PINRANGE(1, 4, ABX500_ALT_A), + ABX500_PINRANGE(10, 2, ABX500_DEFAULT), + ABX500_PINRANGE(13, 1, ABX500_DEFAULT), + ABX500_PINRANGE(14, 12, ABX500_ALT_A), + ABX500_PINRANGE(27, 6, ABX500_ALT_A), + ABX500_PINRANGE(34, 1, ABX500_ALT_A), + ABX500_PINRANGE(40, 3, ABX500_ALT_A), + ABX500_PINRANGE(50, 1, ABX500_DEFAULT), + ABX500_PINRANGE(51, 3, ABX500_ALT_A), + ABX500_PINRANGE(54, 1, ABX500_DEFAULT), +}; + +/* + * Read the pin group names like this: + * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function + * + * The groups are arranged as sets per altfunction column, so we can + * mux in one group at a time by selecting the same altfunction for them + * all. When functions require pins on different altfunctions, you need + * to combine several groups. + */ + +/* default column */ +static const unsigned sysclkreq2_d_1_pins[] = { AB9540_PIN_R4 }; +static const unsigned sysclkreq3_d_1_pins[] = { AB9540_PIN_V3 }; +static const unsigned sysclkreq4_d_1_pins[] = { AB9540_PIN_T4 }; +static const unsigned sysclkreq6_d_1_pins[] = { AB9540_PIN_T5 }; +static const unsigned gpio10_d_1_pins[] = { AB9540_PIN_B18 }; +static const unsigned gpio11_d_1_pins[] = { AB9540_PIN_C18 }; +static const unsigned gpio13_d_1_pins[] = { AB9540_PIN_D18 }; +static const unsigned pwmout1_d_1_pins[] = { AB9540_PIN_B19 }; +static const unsigned pwmout2_d_1_pins[] = { AB9540_PIN_C19 }; +static const unsigned pwmout3_d_1_pins[] = { AB9540_PIN_D19 }; +/* audio data interface 1*/ +static const unsigned adi1_d_1_pins[] = { AB9540_PIN_R3, AB9540_PIN_T2, + AB9540_PIN_U2, AB9540_PIN_V2 }; +/* USBUICC */ +static const unsigned usbuicc_d_1_pins[] = { AB9540_PIN_N17, AB9540_PIN_N16, + AB9540_PIN_M19 }; +static const unsigned sysclkreq7_d_1_pins[] = { AB9540_PIN_T3 }; +static const unsigned sysclkreq8_d_1_pins[] = { AB9540_PIN_W2 }; +/* Digital microphone 1 and 2 */ +static const unsigned dmic12_d_1_pins[] = { AB9540_PIN_H4, AB9540_PIN_F1 }; +/* Digital microphone 3 and 4 */ +static const unsigned dmic34_d_1_pins[] = { AB9540_PIN_F4, AB9540_PIN_F2 }; +/* Digital microphone 5 and 6 */ +static const unsigned dmic56_d_1_pins[] = { AB9540_PIN_E4, AB9540_PIN_F3 }; +static const unsigned extcpena_d_1_pins[] = { AB9540_PIN_J13 }; +/* modem SDA/SCL */ +static const unsigned modsclsda_d_1_pins[] = { AB9540_PIN_L17, AB9540_PIN_L16 }; +static const unsigned sysclkreq5_d_1_pins[] = { AB9540_PIN_W3 }; +static const unsigned gpio50_d_1_pins[] = { AB9540_PIN_N4 }; +static const unsigned batremn_d_1_pins[] = { AB9540_PIN_G12 }; +static const unsigned resethw_d_1_pins[] = { AB9540_PIN_E17 }; +static const unsigned service_d_1_pins[] = { AB9540_PIN_D11 }; +static const unsigned gpio60_d_1_pins[] = { AB9540_PIN_M18 }; + +/* Altfunction A column */ +static const unsigned gpio1_a_1_pins[] = { AB9540_PIN_R4 }; +static const unsigned gpio2_a_1_pins[] = { AB9540_PIN_V3 }; +static const unsigned gpio3_a_1_pins[] = { AB9540_PIN_T4 }; +static const unsigned gpio4_a_1_pins[] = { AB9540_PIN_T5 }; +static const unsigned hiqclkena_a_1_pins[] = { AB9540_PIN_B18 }; +static const unsigned pdmclk_a_1_pins[] = { AB9540_PIN_C18 }; +static const unsigned uartdata_a_1_pins[] = { AB9540_PIN_D18, AB9540_PIN_N4 }; +static const unsigned gpio14_a_1_pins[] = { AB9540_PIN_B19 }; +static const unsigned gpio15_a_1_pins[] = { AB9540_PIN_C19 }; +static const unsigned gpio16_a_1_pins[] = { AB9540_PIN_D19 }; +static const unsigned gpio17_a_1_pins[] = { AB9540_PIN_R3 }; +static const unsigned gpio18_a_1_pins[] = { AB9540_PIN_T2 }; +static const unsigned gpio19_a_1_pins[] = { AB9540_PIN_U2 }; +static const unsigned gpio20_a_1_pins[] = { AB9540_PIN_V2 }; +static const unsigned gpio21_a_1_pins[] = { AB9540_PIN_N17 }; +static const unsigned gpio22_a_1_pins[] = { AB9540_PIN_N16 }; +static const unsigned gpio23_a_1_pins[] = { AB9540_PIN_M19 }; +static const unsigned gpio24_a_1_pins[] = { AB9540_PIN_T3 }; +static const unsigned gpio25_a_1_pins[] = { AB9540_PIN_W2 }; +static const unsigned gpio27_a_1_pins[] = { AB9540_PIN_H4 }; +static const unsigned gpio28_a_1_pins[] = { AB9540_PIN_F1 }; +static const unsigned gpio29_a_1_pins[] = { AB9540_PIN_F4 }; +static const unsigned gpio30_a_1_pins[] = { AB9540_PIN_F2 }; +static const unsigned gpio31_a_1_pins[] = { AB9540_PIN_E4 }; +static const unsigned gpio32_a_1_pins[] = { AB9540_PIN_F3 }; +static const unsigned gpio34_a_1_pins[] = { AB9540_PIN_J13 }; +static const unsigned gpio40_a_1_pins[] = { AB9540_PIN_L17 }; +static const unsigned gpio41_a_1_pins[] = { AB9540_PIN_L16 }; +static const unsigned gpio42_a_1_pins[] = { AB9540_PIN_W3 }; +static const unsigned gpio51_a_1_pins[] = { AB9540_PIN_G12 }; +static const unsigned gpio52_a_1_pins[] = { AB9540_PIN_E17 }; +static const unsigned gpio53_a_1_pins[] = { AB9540_PIN_D11 }; +static const unsigned usbuiccpd_a_1_pins[] = { AB9540_PIN_M18 }; + +/* Altfunction B colum */ +static const unsigned pdmdata_b_1_pins[] = { AB9540_PIN_B18 }; +static const unsigned pwmextvibra1_b_1_pins[] = { AB9540_PIN_D18 }; +static const unsigned pwmextvibra2_b_1_pins[] = { AB9540_PIN_N4 }; + +/* Altfunction C column */ +static const unsigned usbvdat_c_1_pins[] = { AB9540_PIN_D18 }; + +#define AB9540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct abx500_pingroup ab9540_groups[] = { + /* default column */ + AB9540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(resethw_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(service_d_1, ABX500_DEFAULT), + AB9540_PIN_GROUP(gpio60_d_1, ABX500_DEFAULT), + + /* Altfunction A column */ + AB9540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(uartdata_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio21_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio22_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio23_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio24_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio25_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio34_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), + AB9540_PIN_GROUP(usbuiccpd_a_1, ABX500_ALT_A), + + /* Altfunction B column */ + AB9540_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B), + AB9540_PIN_GROUP(pwmextvibra1_b_1, ABX500_ALT_B), + AB9540_PIN_GROUP(pwmextvibra2_b_1, ABX500_ALT_B), + + /* Altfunction C column */ + AB9540_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C), +}; + +/* We use this macro to define the groups applicable to a function */ +#define AB9540_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +AB9540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", + "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1", + "sysclkreq7_d_1", "sysclkreq8_d_1"); +AB9540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1", + "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1", + "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", "gpio18_a_1", + "gpio19_a_1", "gpio20_a_1", "gpio21_a_1", "gpio22_a_1", + "gpio23_a_1", "gpio24_a_1", "gpio25_a_1", "gpio27_a_1", + "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1", + "gpio32_a_1", "gpio34_a_1", "gpio40_a_1", "gpio41_a_1", + "gpio42_a_1", "gpio50_d_1", "gpio51_a_1", "gpio52_a_1", + "gpio53_a_1", "gpio60_d_1"); +AB9540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1"); +AB9540_FUNC_GROUPS(adi1, "adi1_d_1"); +AB9540_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_a_1"); +AB9540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1"); +AB9540_FUNC_GROUPS(extcpena, "extcpena_d_1"); +AB9540_FUNC_GROUPS(modsclsda, "modsclsda_d_1"); +AB9540_FUNC_GROUPS(batremn, "batremn_d_1"); +AB9540_FUNC_GROUPS(resethw, "resethw_d_1"); +AB9540_FUNC_GROUPS(service, "service_d_1"); +AB9540_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1"); +AB9540_FUNC_GROUPS(pdm, "pdmdata_b_1", "pdmclk_a_1"); +AB9540_FUNC_GROUPS(uartdata, "uartdata_a_1"); +AB9540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_b_1", "pwmextvibra2_b_1"); +AB9540_FUNC_GROUPS(usbvdat, "usbvdat_c_1"); + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct abx500_function ab9540_functions[] = { + FUNCTION(sysclkreq), + FUNCTION(gpio), + FUNCTION(pwmout), + FUNCTION(adi1), + FUNCTION(usbuicc), + FUNCTION(dmic), + FUNCTION(extcpena), + FUNCTION(modsclsda), + FUNCTION(batremn), + FUNCTION(resethw), + FUNCTION(service), + FUNCTION(hiqclkena), + FUNCTION(pdm), + FUNCTION(uartdata), + FUNCTION(pwmextvibra), + FUNCTION(usbvdat), +}; + +/* + * this table translates what's is in the AB9540 specification regarding the + * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). + * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, + * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), + * + * example : + * + * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), + * means that pin AB9540_PIN_D18 (pin 13) supports 4 mux (default/ALT_A, + * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to + * select the mux. ALTA, ALTB and ALTC val indicates values to write in + * ALTERNATFUNC register. We need to specifies these values as SOC + * designers didn't apply the same logic on how to select mux in the + * ABx500 family. + * + * As this pins supports at least ALT_B mux, default mux is + * selected by writing 1 in GPIOSEL bit : + * + * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3 + * default | 1 | 0 | 0 + * alt_A | 0 | 0 | 1 + * alt_B | 0 | 0 | 0 + * alt_C | 0 | 1 | 0 + * + * ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED), + * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL + * register is used to select the mux. As this pins doesn't support at + * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit : + * + * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1= + * default | 0 | 0 | 0 + * alt_A | 1 | 0 | 0 + */ + +static struct +alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] = { + /* GPIOSEL1 - bits 4-7 are reserved */ + ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ + ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ + ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/ + ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */ + ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */ + ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */ + ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */ + /* GPIOSEL2 - bits 0 and 3 are reserved */ + ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */ + ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */ + ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */ + ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ + ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */ + /* GPIOSEL3 - bit 1-3 reserved + * pins 17 to 20 are special case, only bit 0 is used to select + * alternate function for these 4 pins. + * bits 1 to 3 are reserved + */ + ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */ + /* GPIOSEL4 - bit 1 reserved */ + ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */ + ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */ + ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */ + /* GPIOSEL5 - bit 0, 2-6 are reserved */ + ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */ + ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */ + ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */ + ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */ + ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */ + ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */ + ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */ + /* GPIOSEL6 - bit 2-7 are reserved */ + ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43 */ + ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44 */ + ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45 */ + ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46 */ + ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47 */ + ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48 */ + /* + * GPIOSEL7 - bit 0 and 6-7 are reserved + * special case with GPIO60, wich is located at offset 5 of gpiosel7 + * don't know why it has been called GPIO60 in AB9540 datasheet, + * GPIO54 would be logical..., so at SOC point of view we consider + * GPIO60 = GPIO54 + */ + ALTERNATE_FUNCTIONS(49, 0, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */ + ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA and altB controlled by bit 1 */ + ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */ + ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54 = GPIO60, altA controlled by bit 5 */ +}; + +static struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = { + GPIO_IRQ_CLUSTER(10, 13, AB8500_INT_GPIO10R), + GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R), + GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R), + GPIO_IRQ_CLUSTER(50, 54, AB9540_INT_GPIO50R), +}; + +static struct abx500_pinctrl_soc_data ab9540_soc = { + .gpio_ranges = ab9540_pinranges, + .gpio_num_ranges = ARRAY_SIZE(ab9540_pinranges), + .pins = ab9540_pins, + .npins = ARRAY_SIZE(ab9540_pins), + .functions = ab9540_functions, + .nfunctions = ARRAY_SIZE(ab9540_functions), + .groups = ab9540_groups, + .ngroups = ARRAY_SIZE(ab9540_groups), + .alternate_functions = ab9540alternate_functions, + .gpio_irq_cluster = ab9540_gpio_irq_cluster, + .ngpio_irq_cluster = ARRAY_SIZE(ab9540_gpio_irq_cluster), + .irq_gpio_rising_offset = AB8500_INT_GPIO6R, + .irq_gpio_falling_offset = AB8500_INT_GPIO6F, + .irq_gpio_factor = 1, +}; + +void +abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc) +{ + *soc = &ab9540_soc; +} diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c new file mode 100644 index 000000000000..a53a689a2bfa --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -0,0 +1,1346 @@ +/* + * Copyright (C) ST-Ericsson SA 2013 + * + * Author: Patrice Chotard + * License terms: GNU General Public License (GPL) version 2 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-abx500.h" +#include "../core.h" +#include "../pinconf.h" + +/* + * The AB9540 and AB8540 GPIO support are extended versions + * of the AB8500 GPIO support. + * The AB9540 supports an additional (7th) register so that + * more GPIO may be configured and used. + * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have + * internal pull-up and pull-down capabilities. + */ + +/* + * GPIO registers offset + * Bank: 0x10 + */ +#define AB8500_GPIO_SEL1_REG 0x00 +#define AB8500_GPIO_SEL2_REG 0x01 +#define AB8500_GPIO_SEL3_REG 0x02 +#define AB8500_GPIO_SEL4_REG 0x03 +#define AB8500_GPIO_SEL5_REG 0x04 +#define AB8500_GPIO_SEL6_REG 0x05 +#define AB9540_GPIO_SEL7_REG 0x06 + +#define AB8500_GPIO_DIR1_REG 0x10 +#define AB8500_GPIO_DIR2_REG 0x11 +#define AB8500_GPIO_DIR3_REG 0x12 +#define AB8500_GPIO_DIR4_REG 0x13 +#define AB8500_GPIO_DIR5_REG 0x14 +#define AB8500_GPIO_DIR6_REG 0x15 +#define AB9540_GPIO_DIR7_REG 0x16 + +#define AB8500_GPIO_OUT1_REG 0x20 +#define AB8500_GPIO_OUT2_REG 0x21 +#define AB8500_GPIO_OUT3_REG 0x22 +#define AB8500_GPIO_OUT4_REG 0x23 +#define AB8500_GPIO_OUT5_REG 0x24 +#define AB8500_GPIO_OUT6_REG 0x25 +#define AB9540_GPIO_OUT7_REG 0x26 + +#define AB8500_GPIO_PUD1_REG 0x30 +#define AB8500_GPIO_PUD2_REG 0x31 +#define AB8500_GPIO_PUD3_REG 0x32 +#define AB8500_GPIO_PUD4_REG 0x33 +#define AB8500_GPIO_PUD5_REG 0x34 +#define AB8500_GPIO_PUD6_REG 0x35 +#define AB9540_GPIO_PUD7_REG 0x36 + +#define AB8500_GPIO_IN1_REG 0x40 +#define AB8500_GPIO_IN2_REG 0x41 +#define AB8500_GPIO_IN3_REG 0x42 +#define AB8500_GPIO_IN4_REG 0x43 +#define AB8500_GPIO_IN5_REG 0x44 +#define AB8500_GPIO_IN6_REG 0x45 +#define AB9540_GPIO_IN7_REG 0x46 +#define AB8540_GPIO_VINSEL_REG 0x47 +#define AB8540_GPIO_PULL_UPDOWN_REG 0x48 +#define AB8500_GPIO_ALTFUN_REG 0x50 +#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 +#define AB8540_GPIO_VINSEL_MASK 0x03 +#define AB8540_GPIOX_VBAT_START 51 +#define AB8540_GPIOX_VBAT_END 54 + +#define ABX500_GPIO_INPUT 0 +#define ABX500_GPIO_OUTPUT 1 + +struct abx500_pinctrl { + struct device *dev; + struct pinctrl_dev *pctldev; + struct abx500_pinctrl_soc_data *soc; + struct gpio_chip chip; + struct ab8500 *parent; + struct abx500_gpio_irq_cluster *irq_cluster; + int irq_cluster_size; +}; + +/** + * to_abx500_pinctrl() - get the pointer to abx500_pinctrl + * @chip: Member of the structure abx500_pinctrl + */ +static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) +{ + return container_of(chip, struct abx500_pinctrl, chip); +} + +static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, + unsigned offset, bool *bit) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + u8 pos = offset % 8; + u8 val; + int ret; + + reg += offset / 8; + ret = abx500_get_register_interruptible(pct->dev, + AB8500_MISC, reg, &val); + + *bit = !!(val & BIT(pos)); + + if (ret < 0) + dev_err(pct->dev, + "%s read reg =%x, offset=%x failed (%d)\n", + __func__, reg, offset, ret); + + return ret; +} + +static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, + unsigned offset, int val) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + u8 pos = offset % 8; + int ret; + + reg += offset / 8; + ret = abx500_mask_and_set_register_interruptible(pct->dev, + AB8500_MISC, reg, BIT(pos), val << pos); + if (ret < 0) + dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n", + __func__, reg, offset, ret); + + return ret; +} + +/** + * abx500_gpio_get() - Get the particular GPIO value + * @chip: Gpio device + * @offset: GPIO number to read + */ +static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + bool bit; + bool is_out; + u8 gpio_offset = offset - 1; + int ret; + + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, + gpio_offset, &is_out); + if (ret < 0) + goto out; + + if (is_out) + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG, + gpio_offset, &bit); + else + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, + gpio_offset, &bit); +out: + if (ret < 0) { + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; + } + + return bit; +} + +static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + int ret; + + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); + if (ret < 0) + dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret); +} + +static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset, + enum abx500_gpio_pull_updown *pull_updown) +{ + u8 pos; + u8 val; + int ret; + struct pullud *pullud; + + if (!pct->soc->pullud) { + dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", + __func__); + ret = -EPERM; + goto out; + } + + pullud = pct->soc->pullud; + + if ((offset < pullud->first_pin) + || (offset > pullud->last_pin)) { + ret = -EINVAL; + goto out; + } + + ret = abx500_get_register_interruptible(pct->dev, + AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val); + + pos = (offset - pullud->first_pin) << 1; + *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK; + +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + + return ret; +} + +static int abx500_set_pull_updown(struct abx500_pinctrl *pct, + int offset, enum abx500_gpio_pull_updown val) +{ + u8 pos; + int ret; + struct pullud *pullud; + + if (!pct->soc->pullud) { + dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", + __func__); + ret = -EPERM; + goto out; + } + + pullud = pct->soc->pullud; + + if ((offset < pullud->first_pin) + || (offset > pullud->last_pin)) { + ret = -EINVAL; + goto out; + } + pos = (offset - pullud->first_pin) << 1; + + ret = abx500_mask_and_set_register_interruptible(pct->dev, + AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, + AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); + +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + + return ret; +} + +static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + struct pullud *pullud = pct->soc->pullud; + + return (pullud && + gpio >= pullud->first_pin && + gpio <= pullud->last_pin); +} + +static int abx500_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int val) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + unsigned gpio; + int ret; + + /* set direction as output */ + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_DIR1_REG, + offset, + ABX500_GPIO_OUTPUT); + if (ret < 0) + goto out; + + /* disable pull down */ + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, + offset, + ABX500_GPIO_PULL_NONE); + if (ret < 0) + goto out; + + /* if supported, disable both pull down and pull up */ + gpio = offset + 1; + if (abx500_pullud_supported(chip, gpio)) { + ret = abx500_set_pull_updown(pct, + gpio, + ABX500_GPIO_PULL_NONE); + } +out: + if (ret < 0) { + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; + } + + /* set the output as 1 or 0 */ + return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); +} + +static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + /* set the register as input */ + return abx500_gpio_set_bits(chip, + AB8500_GPIO_DIR1_REG, + offset, + ABX500_GPIO_INPUT); +} + +static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + /* The AB8500 GPIO numbers are off by one */ + int gpio = offset + 1; + int hwirq; + int i; + + for (i = 0; i < pct->irq_cluster_size; i++) { + struct abx500_gpio_irq_cluster *cluster = + &pct->irq_cluster[i]; + + if (gpio >= cluster->start && gpio <= cluster->end) { + /* + * The ABx500 GPIO's associated IRQs are clustered together + * throughout the interrupt numbers at irregular intervals. + * To solve this quandry, we have placed the read-in values + * into the cluster information table. + */ + hwirq = gpio - cluster->start + cluster->to_irq; + return irq_create_mapping(pct->parent->domain, hwirq); + } + } + + return -EINVAL; +} + +static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, + unsigned gpio, int alt_setting) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + struct alternate_functions af = pct->soc->alternate_functions[gpio]; + int ret; + int val; + unsigned offset; + + const char *modes[] = { + [ABX500_DEFAULT] = "default", + [ABX500_ALT_A] = "altA", + [ABX500_ALT_B] = "altB", + [ABX500_ALT_C] = "altC", + }; + + /* sanity check */ + if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || + ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || + ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { + dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, + modes[alt_setting]); + return -EINVAL; + } + + /* on ABx5xx, there is no GPIO0, so adjust the offset */ + offset = gpio - 1; + + switch (alt_setting) { + case ABX500_DEFAULT: + /* + * for ABx5xx family, default mode is always selected by + * writing 0 to GPIOSELx register, except for pins which + * support at least ALT_B mode, default mode is selected + * by writing 1 to GPIOSELx register + */ + val = 0; + if (af.alt_bit1 != UNUSED) + val++; + + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, + offset, val); + break; + + case ABX500_ALT_A: + /* + * for ABx5xx family, alt_a mode is always selected by + * writing 1 to GPIOSELx register, except for pins which + * support at least ALT_B mode, alt_a mode is selected + * by writing 0 to GPIOSELx register and 0 in ALTFUNC + * register + */ + if (af.alt_bit1 != UNUSED) { + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, + offset, 0); + if (ret < 0) + goto out; + + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_ALTFUN_REG, + af.alt_bit1, + !!(af.alta_val & BIT(0))); + if (ret < 0) + goto out; + + if (af.alt_bit2 != UNUSED) + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_ALTFUN_REG, + af.alt_bit2, + !!(af.alta_val & BIT(1))); + } else + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, + offset, 1); + break; + + case ABX500_ALT_B: + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, + offset, 0); + if (ret < 0) + goto out; + + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, + af.alt_bit1, !!(af.altb_val & BIT(0))); + if (ret < 0) + goto out; + + if (af.alt_bit2 != UNUSED) + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_ALTFUN_REG, + af.alt_bit2, + !!(af.altb_val & BIT(1))); + break; + + case ABX500_ALT_C: + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, + offset, 0); + if (ret < 0) + goto out; + + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, + af.alt_bit2, !!(af.altc_val & BIT(0))); + if (ret < 0) + goto out; + + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, + af.alt_bit2, !!(af.altc_val & BIT(1))); + break; + + default: + dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); + + return -EINVAL; + } +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + + return ret; +} + +static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, + unsigned gpio) +{ + u8 mode; + bool bit_mode; + bool alt_bit1; + bool alt_bit2; + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + struct alternate_functions af = pct->soc->alternate_functions[gpio]; + /* on ABx5xx, there is no GPIO0, so adjust the offset */ + unsigned offset = gpio - 1; + int ret; + + /* + * if gpiosel_bit is set to unused, + * it means no GPIO or special case + */ + if (af.gpiosel_bit == UNUSED) + return ABX500_DEFAULT; + + /* read GpioSelx register */ + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), + af.gpiosel_bit, &bit_mode); + if (ret < 0) + goto out; + + mode = bit_mode; + + /* sanity check */ + if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || + (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { + dev_err(pct->dev, + "alt_bitX value not in correct range (-1 to 7)\n"); + return -EINVAL; + } + + /* if alt_bit2 is used, alt_bit1 must be used too */ + if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { + dev_err(pct->dev, + "if alt_bit2 is used, alt_bit1 can't be unused\n"); + return -EINVAL; + } + + /* check if pin use AlternateFunction register */ + if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) + return mode; + /* + * if pin GPIOSEL bit is set and pin supports alternate function, + * it means DEFAULT mode + */ + if (mode) + return ABX500_DEFAULT; + + /* + * pin use the AlternatFunction register + * read alt_bit1 value + */ + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, + af.alt_bit1, &alt_bit1); + if (ret < 0) + goto out; + + if (af.alt_bit2 != UNUSED) { + /* read alt_bit2 value */ + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, + af.alt_bit2, + &alt_bit2); + if (ret < 0) + goto out; + } else + alt_bit2 = 0; + + mode = (alt_bit2 << 1) + alt_bit1; + if (mode == af.alta_val) + return ABX500_ALT_A; + else if (mode == af.altb_val) + return ABX500_ALT_B; + else + return ABX500_ALT_C; + +out: + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; +} + +#ifdef CONFIG_DEBUG_FS + +#include + +static void abx500_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, unsigned gpio) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + const char *label = gpiochip_is_requested(chip, offset - 1); + u8 gpio_offset = offset - 1; + int mode = -1; + bool is_out; + bool pd; + enum abx500_gpio_pull_updown pud = 0; + int ret; + + const char *modes[] = { + [ABX500_DEFAULT] = "default", + [ABX500_ALT_A] = "altA", + [ABX500_ALT_B] = "altB", + [ABX500_ALT_C] = "altC", + }; + + const char *pull_up_down[] = { + [ABX500_GPIO_PULL_DOWN] = "pull down", + [ABX500_GPIO_PULL_NONE] = "pull none", + [ABX500_GPIO_PULL_NONE + 1] = "pull none", + [ABX500_GPIO_PULL_UP] = "pull up", + }; + + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, + gpio_offset, &is_out); + if (ret < 0) + goto out; + + seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", + gpio, label ?: "(none)", + is_out ? "out" : "in "); + + if (!is_out) { + if (abx500_pullud_supported(chip, offset)) { + ret = abx500_get_pull_updown(pct, offset, &pud); + if (ret < 0) + goto out; + + seq_printf(s, " %-9s", pull_up_down[pud]); + } else { + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, + gpio_offset, &pd); + if (ret < 0) + goto out; + + seq_printf(s, " %-9s", pull_up_down[pd]); + } + } else + seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); + + if (pctldev) + mode = abx500_get_mode(pctldev, chip, offset); + + seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); + +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); +} + +static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned i; + unsigned gpio = chip->base; + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + struct pinctrl_dev *pctldev = pct->pctldev; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ + abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); + seq_printf(s, "\n"); + } +} + +#else +static inline void abx500_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, unsigned gpio) +{ +} +#define abx500_gpio_dbg_show NULL +#endif + +static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + return pinctrl_request_gpio(gpio); +} + +static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + pinctrl_free_gpio(gpio); +} + +static struct gpio_chip abx500gpio_chip = { + .label = "abx500-gpio", + .owner = THIS_MODULE, + .request = abx500_gpio_request, + .free = abx500_gpio_free, + .direction_input = abx500_gpio_direction_input, + .get = abx500_gpio_get, + .direction_output = abx500_gpio_direction_output, + .set = abx500_gpio_set, + .to_irq = abx500_gpio_to_irq, + .dbg_show = abx500_gpio_dbg_show, +}; + +static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + + return pct->soc->nfunctions; +} + +static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + + return pct->soc->functions[function].name; +} + +static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + + *groups = pct->soc->functions[function].groups; + *num_groups = pct->soc->functions[function].ngroups; + + return 0; +} + +static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &pct->chip; + const struct abx500_pingroup *g; + int i; + int ret = 0; + + g = &pct->soc->groups[group]; + if (g->altsetting < 0) + return -EINVAL; + + dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); + + for (i = 0; i < g->npins; i++) { + dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", + g->pins[i], g->altsetting); + + ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); + } + + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + + return ret; +} + +static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + const struct abx500_pinrange *p; + int ret; + int i; + + /* + * Different ranges have different ways to enable GPIO function on a + * pin, so refer back to our local range type, where we handily define + * what altfunc enables GPIO for a certain pin. + */ + for (i = 0; i < pct->soc->gpio_num_ranges; i++) { + p = &pct->soc->gpio_ranges[i]; + if ((offset >= p->offset) && + (offset < (p->offset + p->npins))) + break; + } + + if (i == pct->soc->gpio_num_ranges) { + dev_err(pct->dev, "%s failed to locate range\n", __func__); + return -ENODEV; + } + + dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", + p->altfunc, offset); + + ret = abx500_set_mode(pct->pctldev, &pct->chip, + offset, p->altfunc); + if (ret < 0) + dev_err(pct->dev, "%s setting altfunc failed\n", __func__); + + return ret; +} + +static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ +} + +static const struct pinmux_ops abx500_pinmux_ops = { + .get_functions_count = abx500_pmx_get_funcs_cnt, + .get_function_name = abx500_pmx_get_func_name, + .get_function_groups = abx500_pmx_get_func_groups, + .enable = abx500_pmx_enable, + .gpio_request_enable = abx500_gpio_request_enable, + .gpio_disable_free = abx500_gpio_disable_free, +}; + +static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + + return pct->soc->ngroups; +} + +static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + + return pct->soc->groups[selector].name; +} + +static int abx500_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + + *pins = pct->soc->groups[selector].pins; + *num_pins = pct->soc->groups[selector].npins; + + return 0; +} + +static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned offset) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &pct->chip; + + abx500_gpio_dbg_show_one(s, pctldev, chip, offset, + chip->base + offset - 1); +} + +static void abx500_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + kfree(map); +} + +static int abx500_dt_reserve_map(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, + unsigned reserve) +{ + unsigned old_num = *reserved_maps; + unsigned new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int abx500_dt_add_map_mux(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int abx500_dt_add_map_configs(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, const char *group, + unsigned long *configs, unsigned num_configs) +{ + unsigned long *dup_configs; + + if (*num_maps == *reserved_maps) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) + return -ENOMEM; + + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; + + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev, + const char *pin_name) +{ + int i, pin_number; + struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) + for (i = 0; i < npct->soc->npins; i++) + if (npct->soc->pins[i].number == pin_number) + return npct->soc->pins[i].name; + return NULL; +} + +static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + int ret; + const char *function = NULL; + unsigned long *configs; + unsigned int nconfigs = 0; + bool has_config = 0; + unsigned reserve = 0; + struct property *prop; + const char *group, *gpio_name; + struct device_node *np_config; + + ret = of_property_read_string(np, "ste,function", &function); + if (ret >= 0) + reserve = 1; + + ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); + if (nconfigs) + has_config = 1; + + np_config = of_parse_phandle(np, "ste,config", 0); + if (np_config) { + ret = pinconf_generic_parse_dt_config(np_config, &configs, + &nconfigs); + if (ret) + goto exit; + has_config |= nconfigs; + } + + ret = of_property_count_strings(np, "ste,pins"); + if (ret < 0) + goto exit; + + if (has_config) + reserve++; + + reserve *= ret; + + ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "ste,pins", prop, group) { + if (function) { + ret = abx500_dt_add_map_mux(map, reserved_maps, + num_maps, group, function); + if (ret < 0) + goto exit; + } + if (has_config) { + gpio_name = abx500_find_pin_name(pctldev, group); + + ret = abx500_dt_add_map_configs(map, reserved_maps, + num_maps, gpio_name, configs, 1); + if (ret < 0) + goto exit; + } + + } +exit: + return ret; +} + +static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + unsigned reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = abx500_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + abx500_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static const struct pinctrl_ops abx500_pinctrl_ops = { + .get_groups_count = abx500_get_groups_cnt, + .get_group_name = abx500_get_group_name, + .get_group_pins = abx500_get_group_pins, + .pin_dbg_show = abx500_pin_dbg_show, + .dt_node_to_map = abx500_dt_node_to_map, + .dt_free_map = abx500_dt_free_map, +}; + +static int abx500_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + return -ENOSYS; +} + +static int abx500_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &pct->chip; + unsigned offset; + int ret = -EINVAL; + int i; + enum pin_config_param param; + enum pin_config_param argument; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + argument = pinconf_to_config_argument(configs[i]); + + dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", + pin, configs[i], + (param == PIN_CONFIG_OUTPUT) ? "output " : "input", + (param == PIN_CONFIG_OUTPUT) ? + (argument ? "high" : "low") : + (argument ? "pull up" : "pull down")); + + /* on ABx500, there is no GPIO0, so adjust the offset */ + offset = pin - 1; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, we fall back to the old bit set + * that only support pull down. + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + ABX500_GPIO_PULL_NONE); + else + /* Chip only supports pull down */ + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, offset, + ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * if argument = 1 set the pull down + * else clear the pull down + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, we fall back to the old bit set + * that only support pull down. + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + argument ? ABX500_GPIO_PULL_DOWN : + ABX500_GPIO_PULL_NONE); + else + /* Chip only supports pull down */ + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, + offset, + argument ? ABX500_GPIO_PULL_DOWN : + ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * if argument = 1 set the pull up + * else clear the pull up + */ + ret = abx500_gpio_direction_input(chip, offset); + /* + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, do nothing + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + argument ? ABX500_GPIO_PULL_UP : + ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_OUTPUT: + ret = abx500_gpio_direction_output(chip, offset, + argument); + break; + + default: + dev_err(chip->dev, "illegal configuration requested\n"); + } + } /* for each config */ +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + + return ret; +} + +static const struct pinconf_ops abx500_pinconf_ops = { + .pin_config_get = abx500_pin_config_get, + .pin_config_set = abx500_pin_config_set, +}; + +static struct pinctrl_desc abx500_pinctrl_desc = { + .name = "pinctrl-abx500", + .pctlops = &abx500_pinctrl_ops, + .pmxops = &abx500_pinmux_ops, + .confops = &abx500_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) +{ + unsigned int lowest = 0; + unsigned int highest = 0; + unsigned int npins = 0; + int i; + + /* + * Compute number of GPIOs from the last SoC gpio range descriptors + * These ranges may include "holes" but the GPIO number space shall + * still be homogeneous, so we need to detect and account for any + * such holes so that these are included in the number of GPIO pins. + */ + for (i = 0; i < soc->gpio_num_ranges; i++) { + unsigned gstart; + unsigned gend; + const struct abx500_pinrange *p; + + p = &soc->gpio_ranges[i]; + gstart = p->offset; + gend = p->offset + p->npins - 1; + + if (i == 0) { + /* First iteration, set start values */ + lowest = gstart; + highest = gend; + } else { + if (gstart < lowest) + lowest = gstart; + if (gend > highest) + highest = gend; + } + } + /* this gives the absolute number of pins */ + npins = highest - lowest + 1; + return npins; +} + +static const struct of_device_id abx500_gpio_match[] = { + { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, + { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, + { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, + { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, + { } +}; + +static int abx500_gpio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + struct abx500_pinctrl *pct; + unsigned int id = -1; + int ret, err; + int i; + + if (!np) { + dev_err(&pdev->dev, "gpio dt node missing\n"); + return -ENODEV; + } + + pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), + GFP_KERNEL); + if (pct == NULL) { + dev_err(&pdev->dev, + "failed to allocate memory for pct\n"); + return -ENOMEM; + } + + pct->dev = &pdev->dev; + pct->parent = dev_get_drvdata(pdev->dev.parent); + pct->chip = abx500gpio_chip; + pct->chip.dev = &pdev->dev; + pct->chip.base = -1; /* Dynamic allocation */ + + match = of_match_device(abx500_gpio_match, &pdev->dev); + if (!match) { + dev_err(&pdev->dev, "gpio dt not matching\n"); + return -ENODEV; + } + id = (unsigned long)match->data; + + /* Poke in other ASIC variants here */ + switch (id) { + case PINCTRL_AB8500: + abx500_pinctrl_ab8500_init(&pct->soc); + break; + case PINCTRL_AB8540: + abx500_pinctrl_ab8540_init(&pct->soc); + break; + case PINCTRL_AB9540: + abx500_pinctrl_ab9540_init(&pct->soc); + break; + case PINCTRL_AB8505: + abx500_pinctrl_ab8505_init(&pct->soc); + break; + default: + dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); + return -EINVAL; + } + + if (!pct->soc) { + dev_err(&pdev->dev, "Invalid SOC data\n"); + return -EINVAL; + } + + pct->chip.ngpio = abx500_get_gpio_num(pct->soc); + pct->irq_cluster = pct->soc->gpio_irq_cluster; + pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; + + ret = gpiochip_add(&pct->chip); + if (ret) { + dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); + return ret; + } + dev_info(&pdev->dev, "added gpiochip\n"); + + abx500_pinctrl_desc.pins = pct->soc->pins; + abx500_pinctrl_desc.npins = pct->soc->npins; + pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); + if (!pct->pctldev) { + dev_err(&pdev->dev, + "could not register abx500 pinctrl driver\n"); + ret = -EINVAL; + goto out_rem_chip; + } + dev_info(&pdev->dev, "registered pin controller\n"); + + /* We will handle a range of GPIO pins */ + for (i = 0; i < pct->soc->gpio_num_ranges; i++) { + const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; + + ret = gpiochip_add_pin_range(&pct->chip, + dev_name(&pdev->dev), + p->offset - 1, p->offset, p->npins); + if (ret < 0) + goto out_rem_chip; + } + + platform_set_drvdata(pdev, pct); + dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); + + return 0; + +out_rem_chip: + err = gpiochip_remove(&pct->chip); + if (err) + dev_info(&pdev->dev, "failed to remove gpiochip\n"); + + return ret; +} + +/** + * abx500_gpio_remove() - remove Ab8500-gpio driver + * @pdev: Platform device registered + */ +static int abx500_gpio_remove(struct platform_device *pdev) +{ + struct abx500_pinctrl *pct = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&pct->chip); + if (ret < 0) { + dev_err(pct->dev, "unable to remove gpiochip: %d\n", + ret); + return ret; + } + + return 0; +} + +static struct platform_driver abx500_gpio_driver = { + .driver = { + .name = "abx500-gpio", + .owner = THIS_MODULE, + .of_match_table = abx500_gpio_match, + }, + .probe = abx500_gpio_probe, + .remove = abx500_gpio_remove, +}; + +static int __init abx500_gpio_init(void) +{ + return platform_driver_register(&abx500_gpio_driver); +} +core_initcall(abx500_gpio_init); + +MODULE_AUTHOR("Patrice Chotard "); +MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); +MODULE_ALIAS("platform:abx500-gpio"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.h b/drivers/pinctrl/nomadik/pinctrl-abx500.h new file mode 100644 index 000000000000..2beef3bfe9ca --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.h @@ -0,0 +1,246 @@ +#ifndef PINCTRL_PINCTRL_ABx500_H +#define PINCTRL_PINCTRL_ABx500_H + +/* Package definitions */ +#define PINCTRL_AB8500 0 +#define PINCTRL_AB8540 1 +#define PINCTRL_AB9540 2 +#define PINCTRL_AB8505 3 + +/* pins alternate function */ +enum abx500_pin_func { + ABX500_DEFAULT, + ABX500_ALT_A, + ABX500_ALT_B, + ABX500_ALT_C, +}; + +enum abx500_gpio_pull_updown { + ABX500_GPIO_PULL_DOWN = 0x0, + ABX500_GPIO_PULL_NONE = 0x1, + ABX500_GPIO_PULL_UP = 0x3, +}; + +enum abx500_gpio_vinsel { + ABX500_GPIO_VINSEL_VBAT = 0x0, + ABX500_GPIO_VINSEL_VIN_1V8 = 0x1, + ABX500_GPIO_VINSEL_VDD_BIF = 0x2, +}; + +/** + * struct abx500_function - ABx500 pinctrl mux function + * @name: The name of the function, exported to pinctrl core. + * @groups: An array of pin groups that may select this function. + * @ngroups: The number of entries in @groups. + */ +struct abx500_function { + const char *name; + const char * const *groups; + unsigned ngroups; +}; + +/** + * struct abx500_pingroup - describes a ABx500 pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + * @altsetting: the altsetting to apply to all pins in this group to + * configure them to be used by a function + */ +struct abx500_pingroup { + const char *name; + const unsigned int *pins; + const unsigned npins; + int altsetting; +}; + +#define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \ +{ \ + .pin_number = pin, \ + .gpiosel_bit = sel_bit, \ + .alt_bit1 = alt1, \ + .alt_bit2 = alt2, \ + .alta_val = alta, \ + .altb_val = altb, \ + .altc_val = altc, \ +} + +#define UNUSED -1 +/** + * struct alternate_functions + * @pin_number: The pin number + * @gpiosel_bit: Control bit in GPIOSEL register, + * @alt_bit1: First AlternateFunction bit used to select the + * alternate function + * @alt_bit2: Second AlternateFunction bit used to select the + * alternate function + * + * these 3 following fields are necessary due to none + * coherency on how to select the altA, altB and altC + * function between the ABx500 SOC family when using + * alternatfunc register. + * @alta_val: value to write in alternatfunc to select altA function + * @altb_val: value to write in alternatfunc to select altB function + * @altc_val: value to write in alternatfunc to select altC function + */ +struct alternate_functions { + unsigned pin_number; + s8 gpiosel_bit; + s8 alt_bit1; + s8 alt_bit2; + u8 alta_val; + u8 altb_val; + u8 altc_val; +}; + +/** + * struct pullud - specific pull up/down feature + * @first_pin: The pin number of the first pins which support + * specific pull up/down + * @last_pin: The pin number of the last pins + */ +struct pullud { + unsigned first_pin; + unsigned last_pin; +}; + +#define GPIO_IRQ_CLUSTER(a, b, c) \ +{ \ + .start = a, \ + .end = b, \ + .to_irq = c, \ +} + +/** + * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt + * capable + * @start: The pin number of the first pin interrupt capable + * @end: The pin number of the last pin interrupt capable + * @to_irq: The ABx500 GPIO's associated IRQs are clustered + * together throughout the interrupt numbers at irregular + * intervals. To solve this quandary, we will place the + * read-in values into the cluster information table + */ + +struct abx500_gpio_irq_cluster { + int start; + int end; + int to_irq; +}; + +/** + * struct abx500_pinrange - map pin numbers to GPIO offsets + * @offset: offset into the GPIO local numberspace, incidentally + * identical to the offset into the local pin numberspace + * @npins: number of pins to map from both offsets + * @altfunc: altfunc setting to be used to enable GPIO on a pin in + * this range (may vary) + */ +struct abx500_pinrange { + unsigned int offset; + unsigned int npins; + int altfunc; +}; + +#define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c } + +/** + * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration + * @gpio_ranges: An array of GPIO ranges for this SoC + * @gpio_num_ranges: The number of GPIO ranges for this SoC + * @pins: An array describing all pins the pin controller affects. + * All pins which are also GPIOs must be listed first within the + * array, and be numbered identically to the GPIO controller's + * numbering. + * @npins: The number of entries in @pins. + * @functions: The functions supported on this SoC. + * @nfunction: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The number of entries in @groups. + * @alternate_functions: array describing pins which supports alternate and + * how to set it. + * @pullud: array describing pins which supports pull up/down + * specific registers. + * @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC + * @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC + * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific + * setting strategy of the rising interrupt line + * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific + * setting strategy of the falling interrupt line + * @irq_gpio_factor: Factor used to compute specific setting strategy of + * the interrupt line + */ + +struct abx500_pinctrl_soc_data { + const struct abx500_pinrange *gpio_ranges; + unsigned gpio_num_ranges; + const struct pinctrl_pin_desc *pins; + unsigned npins; + const struct abx500_function *functions; + unsigned nfunctions; + const struct abx500_pingroup *groups; + unsigned ngroups; + struct alternate_functions *alternate_functions; + struct pullud *pullud; + struct abx500_gpio_irq_cluster *gpio_irq_cluster; + unsigned ngpio_irq_cluster; + int irq_gpio_rising_offset; + int irq_gpio_falling_offset; + int irq_gpio_factor; +}; + +#ifdef CONFIG_PINCTRL_AB8500 + +void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc); + +#else + +static inline void +abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc) +{ +} + +#endif + +#ifdef CONFIG_PINCTRL_AB8540 + +void abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc); + +#else + +static inline void +abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc) +{ +} + +#endif + +#ifdef CONFIG_PINCTRL_AB9540 + +void abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc); + +#else + +static inline void +abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc) +{ +} + +#endif + +#ifdef CONFIG_PINCTRL_AB8505 + +void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc); + +#else + +static inline void +abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc) +{ +} + +#endif + +#endif /* PINCTRL_PINCTRL_ABx500_H */ diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c new file mode 100644 index 000000000000..c74840729648 --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c @@ -0,0 +1,1257 @@ +#include +#include +#include "pinctrl-nomadik.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define _GPIO(offset) (offset) + +#define DB8500_PIN_AJ5 _GPIO(0) +#define DB8500_PIN_AJ3 _GPIO(1) +#define DB8500_PIN_AH4 _GPIO(2) +#define DB8500_PIN_AH3 _GPIO(3) +#define DB8500_PIN_AH6 _GPIO(4) +#define DB8500_PIN_AG6 _GPIO(5) +#define DB8500_PIN_AF6 _GPIO(6) +#define DB8500_PIN_AG5 _GPIO(7) +#define DB8500_PIN_AD5 _GPIO(8) +#define DB8500_PIN_AE4 _GPIO(9) +#define DB8500_PIN_AF5 _GPIO(10) +#define DB8500_PIN_AG4 _GPIO(11) +#define DB8500_PIN_AC4 _GPIO(12) +#define DB8500_PIN_AF3 _GPIO(13) +#define DB8500_PIN_AE3 _GPIO(14) +#define DB8500_PIN_AC3 _GPIO(15) +#define DB8500_PIN_AD3 _GPIO(16) +#define DB8500_PIN_AD4 _GPIO(17) +#define DB8500_PIN_AC2 _GPIO(18) +#define DB8500_PIN_AC1 _GPIO(19) +#define DB8500_PIN_AB4 _GPIO(20) +#define DB8500_PIN_AB3 _GPIO(21) +#define DB8500_PIN_AA3 _GPIO(22) +#define DB8500_PIN_AA4 _GPIO(23) +#define DB8500_PIN_AB2 _GPIO(24) +#define DB8500_PIN_Y4 _GPIO(25) +#define DB8500_PIN_Y2 _GPIO(26) +#define DB8500_PIN_AA2 _GPIO(27) +#define DB8500_PIN_AA1 _GPIO(28) +#define DB8500_PIN_W2 _GPIO(29) +#define DB8500_PIN_W3 _GPIO(30) +#define DB8500_PIN_V3 _GPIO(31) +#define DB8500_PIN_V2 _GPIO(32) +#define DB8500_PIN_AF2 _GPIO(33) +#define DB8500_PIN_AE1 _GPIO(34) +#define DB8500_PIN_AE2 _GPIO(35) +#define DB8500_PIN_AG2 _GPIO(36) +/* Hole */ +#define DB8500_PIN_F3 _GPIO(64) +#define DB8500_PIN_F1 _GPIO(65) +#define DB8500_PIN_G3 _GPIO(66) +#define DB8500_PIN_G2 _GPIO(67) +#define DB8500_PIN_E1 _GPIO(68) +#define DB8500_PIN_E2 _GPIO(69) +#define DB8500_PIN_G5 _GPIO(70) +#define DB8500_PIN_G4 _GPIO(71) +#define DB8500_PIN_H4 _GPIO(72) +#define DB8500_PIN_H3 _GPIO(73) +#define DB8500_PIN_J3 _GPIO(74) +#define DB8500_PIN_H2 _GPIO(75) +#define DB8500_PIN_J2 _GPIO(76) +#define DB8500_PIN_H1 _GPIO(77) +#define DB8500_PIN_F4 _GPIO(78) +#define DB8500_PIN_E3 _GPIO(79) +#define DB8500_PIN_E4 _GPIO(80) +#define DB8500_PIN_D2 _GPIO(81) +#define DB8500_PIN_C1 _GPIO(82) +#define DB8500_PIN_D3 _GPIO(83) +#define DB8500_PIN_C2 _GPIO(84) +#define DB8500_PIN_D5 _GPIO(85) +#define DB8500_PIN_C6 _GPIO(86) +#define DB8500_PIN_B3 _GPIO(87) +#define DB8500_PIN_C4 _GPIO(88) +#define DB8500_PIN_E6 _GPIO(89) +#define DB8500_PIN_A3 _GPIO(90) +#define DB8500_PIN_B6 _GPIO(91) +#define DB8500_PIN_D6 _GPIO(92) +#define DB8500_PIN_B7 _GPIO(93) +#define DB8500_PIN_D7 _GPIO(94) +#define DB8500_PIN_E8 _GPIO(95) +#define DB8500_PIN_D8 _GPIO(96) +#define DB8500_PIN_D9 _GPIO(97) +/* Hole */ +#define DB8500_PIN_A5 _GPIO(128) +#define DB8500_PIN_B4 _GPIO(129) +#define DB8500_PIN_C8 _GPIO(130) +#define DB8500_PIN_A12 _GPIO(131) +#define DB8500_PIN_C10 _GPIO(132) +#define DB8500_PIN_B10 _GPIO(133) +#define DB8500_PIN_B9 _GPIO(134) +#define DB8500_PIN_A9 _GPIO(135) +#define DB8500_PIN_C7 _GPIO(136) +#define DB8500_PIN_A7 _GPIO(137) +#define DB8500_PIN_C5 _GPIO(138) +#define DB8500_PIN_C9 _GPIO(139) +#define DB8500_PIN_B11 _GPIO(140) +#define DB8500_PIN_C12 _GPIO(141) +#define DB8500_PIN_C11 _GPIO(142) +#define DB8500_PIN_D12 _GPIO(143) +#define DB8500_PIN_B13 _GPIO(144) +#define DB8500_PIN_C13 _GPIO(145) +#define DB8500_PIN_D13 _GPIO(146) +#define DB8500_PIN_C15 _GPIO(147) +#define DB8500_PIN_B16 _GPIO(148) +#define DB8500_PIN_B14 _GPIO(149) +#define DB8500_PIN_C14 _GPIO(150) +#define DB8500_PIN_D17 _GPIO(151) +#define DB8500_PIN_D16 _GPIO(152) +#define DB8500_PIN_B17 _GPIO(153) +#define DB8500_PIN_C16 _GPIO(154) +#define DB8500_PIN_C19 _GPIO(155) +#define DB8500_PIN_C17 _GPIO(156) +#define DB8500_PIN_A18 _GPIO(157) +#define DB8500_PIN_C18 _GPIO(158) +#define DB8500_PIN_B19 _GPIO(159) +#define DB8500_PIN_B20 _GPIO(160) +#define DB8500_PIN_D21 _GPIO(161) +#define DB8500_PIN_D20 _GPIO(162) +#define DB8500_PIN_C20 _GPIO(163) +#define DB8500_PIN_B21 _GPIO(164) +#define DB8500_PIN_C21 _GPIO(165) +#define DB8500_PIN_A22 _GPIO(166) +#define DB8500_PIN_B24 _GPIO(167) +#define DB8500_PIN_C22 _GPIO(168) +#define DB8500_PIN_D22 _GPIO(169) +#define DB8500_PIN_C23 _GPIO(170) +#define DB8500_PIN_D23 _GPIO(171) +/* Hole */ +#define DB8500_PIN_AJ27 _GPIO(192) +#define DB8500_PIN_AH27 _GPIO(193) +#define DB8500_PIN_AF27 _GPIO(194) +#define DB8500_PIN_AG28 _GPIO(195) +#define DB8500_PIN_AG26 _GPIO(196) +#define DB8500_PIN_AH24 _GPIO(197) +#define DB8500_PIN_AG25 _GPIO(198) +#define DB8500_PIN_AH23 _GPIO(199) +#define DB8500_PIN_AH26 _GPIO(200) +#define DB8500_PIN_AF24 _GPIO(201) +#define DB8500_PIN_AF25 _GPIO(202) +#define DB8500_PIN_AE23 _GPIO(203) +#define DB8500_PIN_AF23 _GPIO(204) +#define DB8500_PIN_AG23 _GPIO(205) +#define DB8500_PIN_AG24 _GPIO(206) +#define DB8500_PIN_AJ23 _GPIO(207) +#define DB8500_PIN_AH16 _GPIO(208) +#define DB8500_PIN_AG15 _GPIO(209) +#define DB8500_PIN_AJ15 _GPIO(210) +#define DB8500_PIN_AG14 _GPIO(211) +#define DB8500_PIN_AF13 _GPIO(212) +#define DB8500_PIN_AG13 _GPIO(213) +#define DB8500_PIN_AH15 _GPIO(214) +#define DB8500_PIN_AH13 _GPIO(215) +#define DB8500_PIN_AG12 _GPIO(216) +#define DB8500_PIN_AH12 _GPIO(217) +#define DB8500_PIN_AH11 _GPIO(218) +#define DB8500_PIN_AG10 _GPIO(219) +#define DB8500_PIN_AH10 _GPIO(220) +#define DB8500_PIN_AJ11 _GPIO(221) +#define DB8500_PIN_AJ9 _GPIO(222) +#define DB8500_PIN_AH9 _GPIO(223) +#define DB8500_PIN_AG9 _GPIO(224) +#define DB8500_PIN_AG8 _GPIO(225) +#define DB8500_PIN_AF8 _GPIO(226) +#define DB8500_PIN_AH7 _GPIO(227) +#define DB8500_PIN_AJ6 _GPIO(228) +#define DB8500_PIN_AG7 _GPIO(229) +#define DB8500_PIN_AF7 _GPIO(230) +/* Hole */ +#define DB8500_PIN_AF28 _GPIO(256) +#define DB8500_PIN_AE29 _GPIO(257) +#define DB8500_PIN_AD29 _GPIO(258) +#define DB8500_PIN_AC29 _GPIO(259) +#define DB8500_PIN_AD28 _GPIO(260) +#define DB8500_PIN_AD26 _GPIO(261) +#define DB8500_PIN_AE26 _GPIO(262) +#define DB8500_PIN_AG29 _GPIO(263) +#define DB8500_PIN_AE27 _GPIO(264) +#define DB8500_PIN_AD27 _GPIO(265) +#define DB8500_PIN_AC28 _GPIO(266) +#define DB8500_PIN_AC27 _GPIO(267) + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc nmk_db8500_pins[] = { + PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"), + PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"), + PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"), + PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"), + PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"), + PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"), + PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"), + PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"), + PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"), + PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"), + PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"), + PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"), + PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"), + PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"), + PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"), + PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"), + PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"), + PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"), + PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"), + PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"), + PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"), + PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"), + PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"), + PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"), + PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"), + PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"), + PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"), + PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"), + PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"), + PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"), + PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"), + PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"), + PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"), + PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"), + PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"), + PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"), + PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"), + /* Hole */ + PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"), + PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"), + PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"), + PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"), + PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"), + PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"), + PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"), + PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"), + PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"), + PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"), + PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"), + PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"), + PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"), + PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"), + PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"), + PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"), + PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"), + PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"), + PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"), + PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"), + PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"), + PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"), + PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"), + PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"), + PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"), + PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"), + PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"), + PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"), + PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"), + PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"), + PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"), + PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"), + PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"), + PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"), + /* Hole */ + PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"), + PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"), + PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"), + PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"), + PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"), + PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"), + PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"), + PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"), + PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"), + PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"), + PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"), + PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"), + PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"), + PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"), + PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"), + PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"), + PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"), + PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"), + PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"), + PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"), + PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"), + PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"), + PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"), + PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"), + PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"), + PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"), + PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"), + PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"), + PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"), + PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"), + PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"), + PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"), + PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"), + PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"), + PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"), + PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"), + PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"), + PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"), + PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"), + PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"), + PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"), + PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"), + PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"), + PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"), + /* Hole */ + PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"), + PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"), + PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"), + PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"), + PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"), + PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"), + PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"), + PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"), + PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"), + PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"), + PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"), + PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"), + PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"), + PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"), + PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"), + PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"), + PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"), + PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"), + PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"), + PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"), + PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"), + PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"), + PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"), + PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"), + PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"), + PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"), + PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"), + PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"), + PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"), + PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"), + PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"), + PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"), + PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"), + PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"), + PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"), + PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"), + PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"), + PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"), + PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"), + /* Hole */ + PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"), + PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"), + PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"), + PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"), + PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"), + PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"), + PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"), + PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"), + PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"), + PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"), + PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"), + PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"), +}; + +#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \ + .pin_base = b, .npins = c } + +/* + * This matches the 32-pin gpio chips registered by the GPIO portion. This + * cannot be const since we assign the struct gpio_chip * pointer at runtime. + */ +static struct pinctrl_gpio_range nmk_db8500_ranges[] = { + DB8500_GPIO_RANGE(0, 0, 32), + DB8500_GPIO_RANGE(1, 32, 5), + DB8500_GPIO_RANGE(2, 64, 32), + DB8500_GPIO_RANGE(3, 96, 2), + DB8500_GPIO_RANGE(4, 128, 32), + DB8500_GPIO_RANGE(5, 160, 12), + DB8500_GPIO_RANGE(6, 192, 32), + DB8500_GPIO_RANGE(7, 224, 7), + DB8500_GPIO_RANGE(8, 256, 12), +}; + +/* + * Read the pin group names like this: + * u0_a_1 = first groups of pins for uart0 on alt function a + * i2c2_b_2 = second group of pins for i2c2 on alt function b + * + * The groups are arranged as sets per altfunction column, so we can + * mux in one group at a time by selecting the same altfunction for them + * all. When functions require pins on different altfunctions, you need + * to combine several groups. + */ + +/* Altfunction A column */ +static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, + DB8500_PIN_AH4, DB8500_PIN_AH3 }; +static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; +static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; +/* Image processor I2C line, this is driven by image processor firmware */ +static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; +static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; +/* MSP0 can only be on these pins, but TXD and RXD can be flipped */ +static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; +static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 }; +static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; +/* Basic pins of the MMC/SD card 0 interface */ +static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, + DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, + DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; +/* Often only 4 bits are used, then these are not needed (only used for MMC) */ +static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, + DB8500_PIN_V3, DB8500_PIN_V2}; +static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 }; +/* MSP1 can only be on these pins, but TXD and RXD can be flipped */ +static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; +static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 }; +/* LCD interface */ +static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, + DB8500_PIN_G3, DB8500_PIN_G2 }; +static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 }; +static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 }; +static const unsigned lcd_d0_d7_a_1_pins[] = { + DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, + DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 }; +/* D8 thru D11 often used as TVOUT lines */ +static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4, + DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 }; +static const unsigned lcd_d12_d23_a_1_pins[] = { + DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5, + DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6, + DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 }; +static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8, + DB8500_PIN_D8, DB8500_PIN_D9 }; +static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 }; +static const unsigned kp_a_2_pins[] = { + DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, + DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; +/* MC2 has 8 data lines and no direction control, so only for (e)MMC */ +static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4, + DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, + DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, + DB8500_PIN_C5 }; +static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, + DB8500_PIN_C12, DB8500_PIN_C11 }; +static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13, + DB8500_PIN_C13, DB8500_PIN_D13 }; +static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 }; +/* + * Image processor GPIO pins are named "ipgpio" and have their own + * numberspace + */ +static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 }; +static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 }; +/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */ +static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23, + DB8500_PIN_D23 }; +/* + * This MSP cannot switch RX and TX, SCK in a separate group since this + * seems to be optional. + */ +static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 }; +static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27, + DB8500_PIN_AG28, DB8500_PIN_AG26 }; +static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25, + DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25, + DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24, + DB8500_PIN_AJ23 }; +/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */ +static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15, + DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, + DB8500_PIN_AH15 }; +static const unsigned mc1_a_2_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AJ15, + DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, DB8500_PIN_AH15 }; +static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, + DB8500_PIN_AH12, DB8500_PIN_AH11 }; +static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10, + DB8500_PIN_AJ11 }; +static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ9, DB8500_PIN_AH9, + DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 }; +static const unsigned hsit_a_2_pins[] = { DB8500_PIN_AJ9, DB8500_PIN_AH9, + DB8500_PIN_AG9, DB8500_PIN_AG8 }; +static const unsigned clkout1_a_1_pins[] = { DB8500_PIN_AH7 }; +static const unsigned clkout1_a_2_pins[] = { DB8500_PIN_AG7 }; +static const unsigned clkout2_a_1_pins[] = { DB8500_PIN_AJ6 }; +static const unsigned clkout2_a_2_pins[] = { DB8500_PIN_AF7 }; +static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29, + DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26, + DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27, + DB8500_PIN_AC28, DB8500_PIN_AC27 }; + +/* Altfunction B column */ +static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 }; +static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; +static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; +static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; +static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; +static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; +static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; +/* Just RX and TX for UART2 */ +static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 }; +static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 }; +static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 }; +static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 }; +static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4, + DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; +static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 }; +static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, + DB8500_PIN_V3, DB8500_PIN_V2 }; +static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; +static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, + DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2, + DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, + DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1, + DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2, + DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 }; +static const unsigned kp_b_2_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, + DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_F4, DB8500_PIN_E3}; +static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, + DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, + DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, + DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8, + DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9, + DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5, + DB8500_PIN_C9 }; +/* This chip select pin can be "ps0" in alt C so have it separately */ +static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 }; +/* This chip select pin can be "ps1" in alt C so have it separately */ +static const unsigned smcs1_b_1_pins[] = { DB8500_PIN_B14 }; +static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 }; +static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 }; +static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 }; +static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 }; +static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22, + DB8500_PIN_C23, DB8500_PIN_D23 }; +static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, + DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, + DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; +static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 }; +static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 }; +static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13, + DB8500_PIN_AG13, DB8500_PIN_AH15 }; +static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, + DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10, + DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9, + DB8500_PIN_AG8 }; +static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 }; +static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 }; +static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 }; + +/* Altfunction C column */ +static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, + DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 }; +static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 }; +static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 }; +static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 }; +static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 }; +static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 }; +static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; +/* Optional 4-bit Memory Stick interface */ +static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, + DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, + DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; +static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 }; +static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 }; +static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 }; +static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1, + DB8500_PIN_AE2, DB8500_PIN_AG2 }; +static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 }; +static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 }; +static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 }; +static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 }; +static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 }; +static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, + DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 }; +static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 }; +static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 }; +static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 }; +static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 }; +static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 }; +static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, + DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, + DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, + DB8500_PIN_D9 }; +static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 }; +static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, + DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16, + DB8500_PIN_C23, DB8500_PIN_D23 }; +static const unsigned smps0_c_1_pins[] = { DB8500_PIN_E8 }; +static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 }; +static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 }; +static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 }; +static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 }; +static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 }; +static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 }; +static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 }; +static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 }; +static const unsigned clkout1_c_1_pins[] = { DB8500_PIN_AH13 }; +static const unsigned clkout2_c_1_pins[] = { DB8500_PIN_AH12 }; +static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 }; +static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9, + DB8500_PIN_AG9, DB8500_PIN_AG8 }; +static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 }; +static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; + +/* Other C1 column */ +static const unsigned u2rx_oc1_1_pins[] = { DB8500_PIN_AB2 }; +static const unsigned stmape_oc1_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4, + DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; +static const unsigned remap0_oc1_1_pins[] = { DB8500_PIN_E1 }; +static const unsigned remap1_oc1_1_pins[] = { DB8500_PIN_E2 }; +static const unsigned ptma9_oc1_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, + DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H2, + DB8500_PIN_J2, DB8500_PIN_H1 }; +static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, + DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, + DB8500_PIN_D6, DB8500_PIN_B7 }; +static const unsigned rf_oc1_1_pins[] = { DB8500_PIN_D8, DB8500_PIN_D9 }; +static const unsigned hxclk_oc1_1_pins[] = { DB8500_PIN_D16 }; +static const unsigned uartmodrx_oc1_1_pins[] = { DB8500_PIN_B17 }; +static const unsigned uartmodtx_oc1_1_pins[] = { DB8500_PIN_C16 }; +static const unsigned stmmod_oc1_1_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 }; +static const unsigned hxgpio_oc1_1_pins[] = { DB8500_PIN_D21, DB8500_PIN_D20, + DB8500_PIN_C20, DB8500_PIN_B21, DB8500_PIN_C21, DB8500_PIN_A22, + DB8500_PIN_B24, DB8500_PIN_C22 }; +static const unsigned rf_oc1_2_pins[] = { DB8500_PIN_C23, DB8500_PIN_D23 }; +static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, + DB8500_PIN_AH12, DB8500_PIN_AH11 }; +static const unsigned spi2_oc1_2_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12, + DB8500_PIN_AH11 }; + +/* Other C2 column */ +static const unsigned sbag_oc2_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_AB2, + DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; +static const unsigned etmr4_oc2_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, + DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H2, + DB8500_PIN_J2, DB8500_PIN_H1 }; +static const unsigned ptma9_oc2_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, + DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, + DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; + +/* Other C3 column */ +static const unsigned stmmod_oc3_1_pins[] = { DB8500_PIN_AB2, DB8500_PIN_W2, + DB8500_PIN_W3, DB8500_PIN_V3, DB8500_PIN_V2 }; +static const unsigned stmmod_oc3_2_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, + DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 }; +static const unsigned uartmodrx_oc3_1_pins[] = { DB8500_PIN_H2 }; +static const unsigned uartmodtx_oc3_1_pins[] = { DB8500_PIN_J2 }; +static const unsigned etmr4_oc3_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, + DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, + DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; + +/* Other C4 column */ +static const unsigned sbag_oc4_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, + DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H1 }; +static const unsigned hwobs_oc4_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, + DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, + DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; + +#define DB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct nmk_pingroup nmk_db8500_groups[] = { + /* Altfunction A column */ + DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc0_dat47_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc0dat31dir_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(kp_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(clkout1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(clkout1_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(clkout2_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(clkout2_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A), + /* Altfunction B column */ + DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(kp_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B), + /* Altfunction C column */ + DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(clkout1_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(clkout2_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C), + /* Other alt C1 column */ + DB8500_PIN_GROUP(u2rx_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(ptma9_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(rf_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(hxclk_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(uartmodrx_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(uartmodtx_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(stmmod_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(hxgpio_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(rf_oc1_2, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C1), + DB8500_PIN_GROUP(spi2_oc1_2, NMK_GPIO_ALT_C1), + /* Other alt C2 column */ + DB8500_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2), + DB8500_PIN_GROUP(etmr4_oc2_1, NMK_GPIO_ALT_C2), + DB8500_PIN_GROUP(ptma9_oc2_1, NMK_GPIO_ALT_C2), + /* Other alt C3 column */ + DB8500_PIN_GROUP(stmmod_oc3_1, NMK_GPIO_ALT_C3), + DB8500_PIN_GROUP(stmmod_oc3_2, NMK_GPIO_ALT_C3), + DB8500_PIN_GROUP(uartmodrx_oc3_1, NMK_GPIO_ALT_C3), + DB8500_PIN_GROUP(uartmodtx_oc3_1, NMK_GPIO_ALT_C3), + DB8500_PIN_GROUP(etmr4_oc3_1, NMK_GPIO_ALT_C3), + /* Other alt C4 column */ + DB8500_PIN_GROUP(sbag_oc4_1, NMK_GPIO_ALT_C4), + DB8500_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4), +}; + +/* We use this macro to define the groups applicable to a function */ +#define DB8500_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1"); +DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1"); +/* + * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however + * only available on two pins in alternative function C + */ +DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1", + "u2rxtx_c_2", "u2rxtx_c_3", "u2rx_oc1_1"); +DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2"); +/* + * MSP0 can only be on a certain set of pins, but the TX/RX pins can be + * switched around by selecting the altfunction A or B. The SCK pin is + * only available on the altfunction B. + */ +DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1", + "msp0txrx_b_1", "msp0sck_b_1"); +DB8500_FUNC_GROUPS(mc0, "mc0_a_1", "mc0_dat47_a_1", "mc0dat31dir_a_1"); +/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */ +DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1"); +DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1"); +DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1", + "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1"); +DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_a_2", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1"); +DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); +DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1"); +DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1"); +DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1"); +/* The image processor has 8 GPIO pins that can be muxed out */ +DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1", + "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1", + "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1", + "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2", + "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2"); +/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */ +DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1"); +DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); +DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2", "mc1dir_a_1"); +DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2"); +DB8500_FUNC_GROUPS(clkout, "clkout1_a_1", "clkout1_a_2", "clkout1_c_1", + "clkout2_a_1", "clkout2_a_2", "clkout2_c_1"); +DB8500_FUNC_GROUPS(usb, "usb_a_1"); +DB8500_FUNC_GROUPS(trig, "trig_b_1"); +DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1"); +DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2"); +DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2"); +/* + * The modem UART can output its RX and TX pins in some different places, + * so select one of each. + */ +DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2", + "uartmodrx_c_1", "uartmod_tx_c_1", "uartmodrx_oc1_1", + "uartmodtx_oc1_1", "uartmodrx_oc3_1", "uartmodtx_oc3_1"); +DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1", "stmmod_oc1_1", + "stmmod_oc3_1", "stmmod_oc3_2"); +DB8500_FUNC_GROUPS(spi3, "spi3_b_1"); +/* Select between CS0 on alt B or PS1 on alt C */ +DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcs1_b_1", "smcleale_c_1", + "smps0_c_1", "smps1_c_1"); +DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1"); +DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1"); +DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4"); +DB8500_FUNC_GROUPS(spi1, "spi1_b_1"); +DB8500_FUNC_GROUPS(mc3, "mc3_b_1"); +DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1"); +DB8500_FUNC_GROUPS(slim0, "slim0_c_1"); +DB8500_FUNC_GROUPS(ms, "ms_c_1"); +DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1"); +DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2", "stmape_oc1_1"); +DB8500_FUNC_GROUPS(mc5, "mc5_c_1"); +DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2"); +DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2"); +DB8500_FUNC_GROUPS(spi0, "spi0_c_1"); +DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1", "spi2_oc1_2"); +DB8500_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1"); +DB8500_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc4_1"); +DB8500_FUNC_GROUPS(ptm, "ptma9_oc1_1", "ptma9_oc2_1"); +DB8500_FUNC_GROUPS(rf, "rf_oc1_1", "rf_oc1_2"); +DB8500_FUNC_GROUPS(hx, "hxclk_oc1_1", "hxgpio_oc1_1"); +DB8500_FUNC_GROUPS(etm, "etmr4_oc2_1", "etmr4_oc3_1"); +DB8500_FUNC_GROUPS(hwobs, "hwobs_oc4_1"); +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct nmk_function nmk_db8500_functions[] = { + FUNCTION(u0), + FUNCTION(u1), + FUNCTION(u2), + FUNCTION(ipi2c), + FUNCTION(msp0), + FUNCTION(mc0), + FUNCTION(msp1), + FUNCTION(lcdb), + FUNCTION(lcd), + FUNCTION(kp), + FUNCTION(mc2), + FUNCTION(ssp1), + FUNCTION(ssp0), + FUNCTION(i2c0), + FUNCTION(ipgpio), + FUNCTION(msp2), + FUNCTION(mc4), + FUNCTION(mc1), + FUNCTION(hsi), + FUNCTION(clkout), + FUNCTION(usb), + FUNCTION(trig), + FUNCTION(i2c4), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(uartmod), + FUNCTION(stmmod), + FUNCTION(spi3), + FUNCTION(sm), + FUNCTION(lcda), + FUNCTION(ddrtrig), + FUNCTION(pwl), + FUNCTION(spi1), + FUNCTION(mc3), + FUNCTION(ipjtag), + FUNCTION(slim0), + FUNCTION(ms), + FUNCTION(iptrigout), + FUNCTION(stmape), + FUNCTION(mc5), + FUNCTION(usbsim), + FUNCTION(i2c3), + FUNCTION(spi0), + FUNCTION(spi2), + FUNCTION(remap), + FUNCTION(ptm), + FUNCTION(rf), + FUNCTION(hx), + FUNCTION(etm), + FUNCTION(hwobs), +}; + +static const struct prcm_gpiocr_altcx_pin_desc db8500_altcx_pins[] = { + PRCM_GPIOCR_ALTCX(23, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_CLK_a */ + true, PRCM_IDX_GPIOCR1, 7, /* SBAG_CLK_a */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(24, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE or U2_RXD ??? */ + true, PRCM_IDX_GPIOCR1, 7, /* SBAG_VAL_a */ + true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(25, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[0] */ + true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[0] */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(26, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[1] */ + true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[1] */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(27, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[2] */ + true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[2] */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(28, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[3] */ + true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[3] */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(29, false, 0, 0, + false, 0, 0, + true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(30, false, 0, 0, + false, 0, 0, + true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(31, false, 0, 0, + false, 0, 0, + true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(32, false, 0, 0, + false, 0, 0, + true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(68, true, PRCM_IDX_GPIOCR1, 18, /* REMAP_SELECT_ON */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(69, true, PRCM_IDX_GPIOCR1, 18, /* REMAP_SELECT_ON */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(70, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D23 */ + true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ + true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ + true, PRCM_IDX_GPIOCR1, 8 /* SBAG_CLK */ + ), + PRCM_GPIOCR_ALTCX(71, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D22 */ + true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ + true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ + true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D3 */ + ), + PRCM_GPIOCR_ALTCX(72, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D21 */ + true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ + true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ + true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D2 */ + ), + PRCM_GPIOCR_ALTCX(73, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D20 */ + true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ + true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ + true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D1 */ + ), + PRCM_GPIOCR_ALTCX(74, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D19 */ + true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ + true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ + true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D0 */ + ), + PRCM_GPIOCR_ALTCX(75, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D18 */ + true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ + true, PRCM_IDX_GPIOCR1, 0, /* DBG_UARTMOD_CMD0 */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(76, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D17 */ + true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ + true, PRCM_IDX_GPIOCR1, 0, /* DBG_UARTMOD_CMD0 */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(77, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D16 */ + true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ + false, 0, 0, + true, PRCM_IDX_GPIOCR1, 8 /* SBAG_VAL */ + ), + PRCM_GPIOCR_ALTCX(86, true, PRCM_IDX_GPIOCR1, 12, /* KP_O3 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(87, true, PRCM_IDX_GPIOCR1, 12, /* KP_O2 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(88, true, PRCM_IDX_GPIOCR1, 12, /* KP_I3 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(89, true, PRCM_IDX_GPIOCR1, 12, /* KP_I2 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(90, true, PRCM_IDX_GPIOCR1, 12, /* KP_O1 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(91, true, PRCM_IDX_GPIOCR1, 12, /* KP_O0 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(92, true, PRCM_IDX_GPIOCR1, 12, /* KP_I1 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(93, true, PRCM_IDX_GPIOCR1, 12, /* KP_I0 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(96, true, PRCM_IDX_GPIOCR2, 3, /* RF_INT */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(97, true, PRCM_IDX_GPIOCR2, 1, /* RF_CTRL */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(151, false, 0, 0, + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_CTL */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS17 */ + ), + PRCM_GPIOCR_ALTCX(152, true, PRCM_IDX_GPIOCR1, 4, /* Hx_CLK */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_CLK */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS16 */ + ), + PRCM_GPIOCR_ALTCX(153, true, PRCM_IDX_GPIOCR1, 1, /* UARTMOD_CMD1 */ + true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D15 */ + true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS15 */ + ), + PRCM_GPIOCR_ALTCX(154, true, PRCM_IDX_GPIOCR1, 1, /* UARTMOD_CMD1 */ + true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D14 */ + true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS14 */ + ), + PRCM_GPIOCR_ALTCX(155, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ + true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D13 */ + true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS13 */ + ), + PRCM_GPIOCR_ALTCX(156, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ + true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D12 */ + true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS12 */ + ), + PRCM_GPIOCR_ALTCX(157, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ + true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D11 */ + true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS11 */ + ), + PRCM_GPIOCR_ALTCX(158, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ + true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D10 */ + true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS10 */ + ), + PRCM_GPIOCR_ALTCX(159, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ + true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D9 */ + true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS9 */ + ), + PRCM_GPIOCR_ALTCX(160, false, 0, 0, + true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D8 */ + true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ + true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS8 */ + ), + PRCM_GPIOCR_ALTCX(161, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO7 */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D7 */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS7 */ + ), + PRCM_GPIOCR_ALTCX(162, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO6 */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D6 */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS6 */ + ), + PRCM_GPIOCR_ALTCX(163, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO5 */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D5 */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS5 */ + ), + PRCM_GPIOCR_ALTCX(164, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO4 */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D4 */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS4 */ + ), + PRCM_GPIOCR_ALTCX(165, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO3 */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D3 */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS3 */ + ), + PRCM_GPIOCR_ALTCX(166, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO2 */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D2 */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS2 */ + ), + PRCM_GPIOCR_ALTCX(167, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO1 */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D1 */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS1 */ + ), + PRCM_GPIOCR_ALTCX(168, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO0 */ + true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D0 */ + true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ + true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS0 */ + ), + PRCM_GPIOCR_ALTCX(170, true, PRCM_IDX_GPIOCR2, 2, /* RF_INT */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(171, true, PRCM_IDX_GPIOCR2, 0, /* RF_CTRL */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(215, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_TXD */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(216, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_FRM */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(217, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_CLK */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(218, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_RXD */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), +}; + +static const u16 db8500_prcm_gpiocr_regs[] = { + [PRCM_IDX_GPIOCR1] = 0x138, + [PRCM_IDX_GPIOCR2] = 0x574, +}; + +static const struct nmk_pinctrl_soc_data nmk_db8500_soc = { + .gpio_ranges = nmk_db8500_ranges, + .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges), + .pins = nmk_db8500_pins, + .npins = ARRAY_SIZE(nmk_db8500_pins), + .functions = nmk_db8500_functions, + .nfunctions = ARRAY_SIZE(nmk_db8500_functions), + .groups = nmk_db8500_groups, + .ngroups = ARRAY_SIZE(nmk_db8500_groups), + .altcx_pins = db8500_altcx_pins, + .npins_altcx = ARRAY_SIZE(db8500_altcx_pins), + .prcm_gpiocr_registers = db8500_prcm_gpiocr_regs, +}; + +void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) +{ + *soc = &nmk_db8500_soc; +} diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c new file mode 100644 index 000000000000..d7ba5443bae0 --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c @@ -0,0 +1,1266 @@ +#include +#include +#include "pinctrl-nomadik.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define _GPIO(offset) (offset) + +#define DB8540_PIN_AH6 _GPIO(0) +#define DB8540_PIN_AG7 _GPIO(1) +#define DB8540_PIN_AF2 _GPIO(2) +#define DB8540_PIN_AD3 _GPIO(3) +#define DB8540_PIN_AF6 _GPIO(4) +#define DB8540_PIN_AG6 _GPIO(5) +#define DB8540_PIN_AD5 _GPIO(6) +#define DB8540_PIN_AF7 _GPIO(7) +#define DB8540_PIN_AG5 _GPIO(8) +#define DB8540_PIN_AH5 _GPIO(9) +#define DB8540_PIN_AE4 _GPIO(10) +#define DB8540_PIN_AD1 _GPIO(11) +#define DB8540_PIN_AD2 _GPIO(12) +#define DB8540_PIN_AC2 _GPIO(13) +#define DB8540_PIN_AC4 _GPIO(14) +#define DB8540_PIN_AC3 _GPIO(15) +#define DB8540_PIN_AH7 _GPIO(16) +#define DB8540_PIN_AE7 _GPIO(17) +/* Hole */ +#define DB8540_PIN_AF8 _GPIO(22) +#define DB8540_PIN_AH11 _GPIO(23) +#define DB8540_PIN_AG11 _GPIO(24) +#define DB8540_PIN_AF11 _GPIO(25) +#define DB8540_PIN_AH10 _GPIO(26) +#define DB8540_PIN_AG10 _GPIO(27) +#define DB8540_PIN_AF10 _GPIO(28) +/* Hole */ +#define DB8540_PIN_AD4 _GPIO(33) +#define DB8540_PIN_AF3 _GPIO(34) +#define DB8540_PIN_AF5 _GPIO(35) +#define DB8540_PIN_AG4 _GPIO(36) +#define DB8540_PIN_AF9 _GPIO(37) +#define DB8540_PIN_AE8 _GPIO(38) +/* Hole */ +#define DB8540_PIN_M26 _GPIO(64) +#define DB8540_PIN_M25 _GPIO(65) +#define DB8540_PIN_M27 _GPIO(66) +#define DB8540_PIN_N25 _GPIO(67) +/* Hole */ +#define DB8540_PIN_M28 _GPIO(70) +#define DB8540_PIN_N26 _GPIO(71) +#define DB8540_PIN_M22 _GPIO(72) +#define DB8540_PIN_N22 _GPIO(73) +#define DB8540_PIN_N27 _GPIO(74) +#define DB8540_PIN_N28 _GPIO(75) +#define DB8540_PIN_P22 _GPIO(76) +#define DB8540_PIN_P28 _GPIO(77) +#define DB8540_PIN_P26 _GPIO(78) +#define DB8540_PIN_T22 _GPIO(79) +#define DB8540_PIN_R27 _GPIO(80) +#define DB8540_PIN_P27 _GPIO(81) +#define DB8540_PIN_R26 _GPIO(82) +#define DB8540_PIN_R25 _GPIO(83) +#define DB8540_PIN_U22 _GPIO(84) +#define DB8540_PIN_T27 _GPIO(85) +#define DB8540_PIN_T25 _GPIO(86) +#define DB8540_PIN_T26 _GPIO(87) +/* Hole */ +#define DB8540_PIN_AF20 _GPIO(116) +#define DB8540_PIN_AG21 _GPIO(117) +#define DB8540_PIN_AH19 _GPIO(118) +#define DB8540_PIN_AE19 _GPIO(119) +#define DB8540_PIN_AG18 _GPIO(120) +#define DB8540_PIN_AH17 _GPIO(121) +#define DB8540_PIN_AF19 _GPIO(122) +#define DB8540_PIN_AF18 _GPIO(123) +#define DB8540_PIN_AE18 _GPIO(124) +#define DB8540_PIN_AG17 _GPIO(125) +#define DB8540_PIN_AF17 _GPIO(126) +#define DB8540_PIN_AE17 _GPIO(127) +#define DB8540_PIN_AC27 _GPIO(128) +#define DB8540_PIN_AD27 _GPIO(129) +#define DB8540_PIN_AE28 _GPIO(130) +#define DB8540_PIN_AG26 _GPIO(131) +#define DB8540_PIN_AF25 _GPIO(132) +#define DB8540_PIN_AE27 _GPIO(133) +#define DB8540_PIN_AF27 _GPIO(134) +#define DB8540_PIN_AG28 _GPIO(135) +#define DB8540_PIN_AF28 _GPIO(136) +#define DB8540_PIN_AG25 _GPIO(137) +#define DB8540_PIN_AG24 _GPIO(138) +#define DB8540_PIN_AD25 _GPIO(139) +#define DB8540_PIN_AH25 _GPIO(140) +#define DB8540_PIN_AF26 _GPIO(141) +#define DB8540_PIN_AF23 _GPIO(142) +#define DB8540_PIN_AG23 _GPIO(143) +#define DB8540_PIN_AE25 _GPIO(144) +#define DB8540_PIN_AH24 _GPIO(145) +#define DB8540_PIN_AJ25 _GPIO(146) +#define DB8540_PIN_AG27 _GPIO(147) +#define DB8540_PIN_AH23 _GPIO(148) +#define DB8540_PIN_AE26 _GPIO(149) +#define DB8540_PIN_AE24 _GPIO(150) +#define DB8540_PIN_AJ24 _GPIO(151) +#define DB8540_PIN_AE21 _GPIO(152) +#define DB8540_PIN_AG22 _GPIO(153) +#define DB8540_PIN_AF21 _GPIO(154) +#define DB8540_PIN_AF24 _GPIO(155) +#define DB8540_PIN_AH22 _GPIO(156) +#define DB8540_PIN_AJ23 _GPIO(157) +#define DB8540_PIN_AH21 _GPIO(158) +#define DB8540_PIN_AG20 _GPIO(159) +#define DB8540_PIN_AE23 _GPIO(160) +#define DB8540_PIN_AH20 _GPIO(161) +#define DB8540_PIN_AG19 _GPIO(162) +#define DB8540_PIN_AF22 _GPIO(163) +#define DB8540_PIN_AJ21 _GPIO(164) +#define DB8540_PIN_AD26 _GPIO(165) +#define DB8540_PIN_AD28 _GPIO(166) +#define DB8540_PIN_AC28 _GPIO(167) +#define DB8540_PIN_AC26 _GPIO(168) +/* Hole */ +#define DB8540_PIN_J3 _GPIO(192) +#define DB8540_PIN_H1 _GPIO(193) +#define DB8540_PIN_J2 _GPIO(194) +#define DB8540_PIN_H2 _GPIO(195) +#define DB8540_PIN_H3 _GPIO(196) +#define DB8540_PIN_H4 _GPIO(197) +#define DB8540_PIN_G2 _GPIO(198) +#define DB8540_PIN_G3 _GPIO(199) +#define DB8540_PIN_G4 _GPIO(200) +#define DB8540_PIN_F2 _GPIO(201) +#define DB8540_PIN_C6 _GPIO(202) +#define DB8540_PIN_B6 _GPIO(203) +#define DB8540_PIN_B7 _GPIO(204) +#define DB8540_PIN_A7 _GPIO(205) +#define DB8540_PIN_D7 _GPIO(206) +#define DB8540_PIN_D8 _GPIO(207) +#define DB8540_PIN_F3 _GPIO(208) +#define DB8540_PIN_E2 _GPIO(209) +#define DB8540_PIN_C7 _GPIO(210) +#define DB8540_PIN_B8 _GPIO(211) +#define DB8540_PIN_C10 _GPIO(212) +#define DB8540_PIN_C8 _GPIO(213) +#define DB8540_PIN_C9 _GPIO(214) +/* Hole */ +#define DB8540_PIN_B9 _GPIO(219) +#define DB8540_PIN_A10 _GPIO(220) +#define DB8540_PIN_D9 _GPIO(221) +#define DB8540_PIN_B11 _GPIO(222) +#define DB8540_PIN_B10 _GPIO(223) +#define DB8540_PIN_E10 _GPIO(224) +#define DB8540_PIN_B12 _GPIO(225) +#define DB8540_PIN_D10 _GPIO(226) +#define DB8540_PIN_D11 _GPIO(227) +#define DB8540_PIN_AJ6 _GPIO(228) +#define DB8540_PIN_B13 _GPIO(229) +#define DB8540_PIN_C12 _GPIO(230) +#define DB8540_PIN_B14 _GPIO(231) +#define DB8540_PIN_E11 _GPIO(232) +/* Hole */ +#define DB8540_PIN_D12 _GPIO(256) +#define DB8540_PIN_D15 _GPIO(257) +#define DB8540_PIN_C13 _GPIO(258) +#define DB8540_PIN_C14 _GPIO(259) +#define DB8540_PIN_C18 _GPIO(260) +#define DB8540_PIN_C16 _GPIO(261) +#define DB8540_PIN_B16 _GPIO(262) +#define DB8540_PIN_D18 _GPIO(263) +#define DB8540_PIN_C15 _GPIO(264) +#define DB8540_PIN_C17 _GPIO(265) +#define DB8540_PIN_B17 _GPIO(266) +#define DB8540_PIN_D17 _GPIO(267) + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc nmk_db8540_pins[] = { + PINCTRL_PIN(DB8540_PIN_AH6, "GPIO0_AH6"), + PINCTRL_PIN(DB8540_PIN_AG7, "GPIO1_AG7"), + PINCTRL_PIN(DB8540_PIN_AF2, "GPIO2_AF2"), + PINCTRL_PIN(DB8540_PIN_AD3, "GPIO3_AD3"), + PINCTRL_PIN(DB8540_PIN_AF6, "GPIO4_AF6"), + PINCTRL_PIN(DB8540_PIN_AG6, "GPIO5_AG6"), + PINCTRL_PIN(DB8540_PIN_AD5, "GPIO6_AD5"), + PINCTRL_PIN(DB8540_PIN_AF7, "GPIO7_AF7"), + PINCTRL_PIN(DB8540_PIN_AG5, "GPIO8_AG5"), + PINCTRL_PIN(DB8540_PIN_AH5, "GPIO9_AH5"), + PINCTRL_PIN(DB8540_PIN_AE4, "GPIO10_AE4"), + PINCTRL_PIN(DB8540_PIN_AD1, "GPIO11_AD1"), + PINCTRL_PIN(DB8540_PIN_AD2, "GPIO12_AD2"), + PINCTRL_PIN(DB8540_PIN_AC2, "GPIO13_AC2"), + PINCTRL_PIN(DB8540_PIN_AC4, "GPIO14_AC4"), + PINCTRL_PIN(DB8540_PIN_AC3, "GPIO15_AC3"), + PINCTRL_PIN(DB8540_PIN_AH7, "GPIO16_AH7"), + PINCTRL_PIN(DB8540_PIN_AE7, "GPIO17_AE7"), + /* Hole */ + PINCTRL_PIN(DB8540_PIN_AF8, "GPIO22_AF8"), + PINCTRL_PIN(DB8540_PIN_AH11, "GPIO23_AH11"), + PINCTRL_PIN(DB8540_PIN_AG11, "GPIO24_AG11"), + PINCTRL_PIN(DB8540_PIN_AF11, "GPIO25_AF11"), + PINCTRL_PIN(DB8540_PIN_AH10, "GPIO26_AH10"), + PINCTRL_PIN(DB8540_PIN_AG10, "GPIO27_AG10"), + PINCTRL_PIN(DB8540_PIN_AF10, "GPIO28_AF10"), + /* Hole */ + PINCTRL_PIN(DB8540_PIN_AD4, "GPIO33_AD4"), + PINCTRL_PIN(DB8540_PIN_AF3, "GPIO34_AF3"), + PINCTRL_PIN(DB8540_PIN_AF5, "GPIO35_AF5"), + PINCTRL_PIN(DB8540_PIN_AG4, "GPIO36_AG4"), + PINCTRL_PIN(DB8540_PIN_AF9, "GPIO37_AF9"), + PINCTRL_PIN(DB8540_PIN_AE8, "GPIO38_AE8"), + /* Hole */ + PINCTRL_PIN(DB8540_PIN_M26, "GPIO64_M26"), + PINCTRL_PIN(DB8540_PIN_M25, "GPIO65_M25"), + PINCTRL_PIN(DB8540_PIN_M27, "GPIO66_M27"), + PINCTRL_PIN(DB8540_PIN_N25, "GPIO67_N25"), + /* Hole */ + PINCTRL_PIN(DB8540_PIN_M28, "GPIO70_M28"), + PINCTRL_PIN(DB8540_PIN_N26, "GPIO71_N26"), + PINCTRL_PIN(DB8540_PIN_M22, "GPIO72_M22"), + PINCTRL_PIN(DB8540_PIN_N22, "GPIO73_N22"), + PINCTRL_PIN(DB8540_PIN_N27, "GPIO74_N27"), + PINCTRL_PIN(DB8540_PIN_N28, "GPIO75_N28"), + PINCTRL_PIN(DB8540_PIN_P22, "GPIO76_P22"), + PINCTRL_PIN(DB8540_PIN_P28, "GPIO77_P28"), + PINCTRL_PIN(DB8540_PIN_P26, "GPIO78_P26"), + PINCTRL_PIN(DB8540_PIN_T22, "GPIO79_T22"), + PINCTRL_PIN(DB8540_PIN_R27, "GPIO80_R27"), + PINCTRL_PIN(DB8540_PIN_P27, "GPIO81_P27"), + PINCTRL_PIN(DB8540_PIN_R26, "GPIO82_R26"), + PINCTRL_PIN(DB8540_PIN_R25, "GPIO83_R25"), + PINCTRL_PIN(DB8540_PIN_U22, "GPIO84_U22"), + PINCTRL_PIN(DB8540_PIN_T27, "GPIO85_T27"), + PINCTRL_PIN(DB8540_PIN_T25, "GPIO86_T25"), + PINCTRL_PIN(DB8540_PIN_T26, "GPIO87_T26"), + /* Hole */ + PINCTRL_PIN(DB8540_PIN_AF20, "GPIO116_AF20"), + PINCTRL_PIN(DB8540_PIN_AG21, "GPIO117_AG21"), + PINCTRL_PIN(DB8540_PIN_AH19, "GPIO118_AH19"), + PINCTRL_PIN(DB8540_PIN_AE19, "GPIO119_AE19"), + PINCTRL_PIN(DB8540_PIN_AG18, "GPIO120_AG18"), + PINCTRL_PIN(DB8540_PIN_AH17, "GPIO121_AH17"), + PINCTRL_PIN(DB8540_PIN_AF19, "GPIO122_AF19"), + PINCTRL_PIN(DB8540_PIN_AF18, "GPIO123_AF18"), + PINCTRL_PIN(DB8540_PIN_AE18, "GPIO124_AE18"), + PINCTRL_PIN(DB8540_PIN_AG17, "GPIO125_AG17"), + PINCTRL_PIN(DB8540_PIN_AF17, "GPIO126_AF17"), + PINCTRL_PIN(DB8540_PIN_AE17, "GPIO127_AE17"), + PINCTRL_PIN(DB8540_PIN_AC27, "GPIO128_AC27"), + PINCTRL_PIN(DB8540_PIN_AD27, "GPIO129_AD27"), + PINCTRL_PIN(DB8540_PIN_AE28, "GPIO130_AE28"), + PINCTRL_PIN(DB8540_PIN_AG26, "GPIO131_AG26"), + PINCTRL_PIN(DB8540_PIN_AF25, "GPIO132_AF25"), + PINCTRL_PIN(DB8540_PIN_AE27, "GPIO133_AE27"), + PINCTRL_PIN(DB8540_PIN_AF27, "GPIO134_AF27"), + PINCTRL_PIN(DB8540_PIN_AG28, "GPIO135_AG28"), + PINCTRL_PIN(DB8540_PIN_AF28, "GPIO136_AF28"), + PINCTRL_PIN(DB8540_PIN_AG25, "GPIO137_AG25"), + PINCTRL_PIN(DB8540_PIN_AG24, "GPIO138_AG24"), + PINCTRL_PIN(DB8540_PIN_AD25, "GPIO139_AD25"), + PINCTRL_PIN(DB8540_PIN_AH25, "GPIO140_AH25"), + PINCTRL_PIN(DB8540_PIN_AF26, "GPIO141_AF26"), + PINCTRL_PIN(DB8540_PIN_AF23, "GPIO142_AF23"), + PINCTRL_PIN(DB8540_PIN_AG23, "GPIO143_AG23"), + PINCTRL_PIN(DB8540_PIN_AE25, "GPIO144_AE25"), + PINCTRL_PIN(DB8540_PIN_AH24, "GPIO145_AH24"), + PINCTRL_PIN(DB8540_PIN_AJ25, "GPIO146_AJ25"), + PINCTRL_PIN(DB8540_PIN_AG27, "GPIO147_AG27"), + PINCTRL_PIN(DB8540_PIN_AH23, "GPIO148_AH23"), + PINCTRL_PIN(DB8540_PIN_AE26, "GPIO149_AE26"), + PINCTRL_PIN(DB8540_PIN_AE24, "GPIO150_AE24"), + PINCTRL_PIN(DB8540_PIN_AJ24, "GPIO151_AJ24"), + PINCTRL_PIN(DB8540_PIN_AE21, "GPIO152_AE21"), + PINCTRL_PIN(DB8540_PIN_AG22, "GPIO153_AG22"), + PINCTRL_PIN(DB8540_PIN_AF21, "GPIO154_AF21"), + PINCTRL_PIN(DB8540_PIN_AF24, "GPIO155_AF24"), + PINCTRL_PIN(DB8540_PIN_AH22, "GPIO156_AH22"), + PINCTRL_PIN(DB8540_PIN_AJ23, "GPIO157_AJ23"), + PINCTRL_PIN(DB8540_PIN_AH21, "GPIO158_AH21"), + PINCTRL_PIN(DB8540_PIN_AG20, "GPIO159_AG20"), + PINCTRL_PIN(DB8540_PIN_AE23, "GPIO160_AE23"), + PINCTRL_PIN(DB8540_PIN_AH20, "GPIO161_AH20"), + PINCTRL_PIN(DB8540_PIN_AG19, "GPIO162_AG19"), + PINCTRL_PIN(DB8540_PIN_AF22, "GPIO163_AF22"), + PINCTRL_PIN(DB8540_PIN_AJ21, "GPIO164_AJ21"), + PINCTRL_PIN(DB8540_PIN_AD26, "GPIO165_AD26"), + PINCTRL_PIN(DB8540_PIN_AD28, "GPIO166_AD28"), + PINCTRL_PIN(DB8540_PIN_AC28, "GPIO167_AC28"), + PINCTRL_PIN(DB8540_PIN_AC26, "GPIO168_AC26"), + /* Hole */ + PINCTRL_PIN(DB8540_PIN_J3, "GPIO192_J3"), + PINCTRL_PIN(DB8540_PIN_H1, "GPIO193_H1"), + PINCTRL_PIN(DB8540_PIN_J2, "GPIO194_J2"), + PINCTRL_PIN(DB8540_PIN_H2, "GPIO195_H2"), + PINCTRL_PIN(DB8540_PIN_H3, "GPIO196_H3"), + PINCTRL_PIN(DB8540_PIN_H4, "GPIO197_H4"), + PINCTRL_PIN(DB8540_PIN_G2, "GPIO198_G2"), + PINCTRL_PIN(DB8540_PIN_G3, "GPIO199_G3"), + PINCTRL_PIN(DB8540_PIN_G4, "GPIO200_G4"), + PINCTRL_PIN(DB8540_PIN_F2, "GPIO201_F2"), + PINCTRL_PIN(DB8540_PIN_C6, "GPIO202_C6"), + PINCTRL_PIN(DB8540_PIN_B6, "GPIO203_B6"), + PINCTRL_PIN(DB8540_PIN_B7, "GPIO204_B7"), + PINCTRL_PIN(DB8540_PIN_A7, "GPIO205_A7"), + PINCTRL_PIN(DB8540_PIN_D7, "GPIO206_D7"), + PINCTRL_PIN(DB8540_PIN_D8, "GPIO207_D8"), + PINCTRL_PIN(DB8540_PIN_F3, "GPIO208_F3"), + PINCTRL_PIN(DB8540_PIN_E2, "GPIO209_E2"), + PINCTRL_PIN(DB8540_PIN_C7, "GPIO210_C7"), + PINCTRL_PIN(DB8540_PIN_B8, "GPIO211_B8"), + PINCTRL_PIN(DB8540_PIN_C10, "GPIO212_C10"), + PINCTRL_PIN(DB8540_PIN_C8, "GPIO213_C8"), + PINCTRL_PIN(DB8540_PIN_C9, "GPIO214_C9"), + /* Hole */ + PINCTRL_PIN(DB8540_PIN_B9, "GPIO219_B9"), + PINCTRL_PIN(DB8540_PIN_A10, "GPIO220_A10"), + PINCTRL_PIN(DB8540_PIN_D9, "GPIO221_D9"), + PINCTRL_PIN(DB8540_PIN_B11, "GPIO222_B11"), + PINCTRL_PIN(DB8540_PIN_B10, "GPIO223_B10"), + PINCTRL_PIN(DB8540_PIN_E10, "GPIO224_E10"), + PINCTRL_PIN(DB8540_PIN_B12, "GPIO225_B12"), + PINCTRL_PIN(DB8540_PIN_D10, "GPIO226_D10"), + PINCTRL_PIN(DB8540_PIN_D11, "GPIO227_D11"), + PINCTRL_PIN(DB8540_PIN_AJ6, "GPIO228_AJ6"), + PINCTRL_PIN(DB8540_PIN_B13, "GPIO229_B13"), + PINCTRL_PIN(DB8540_PIN_C12, "GPIO230_C12"), + PINCTRL_PIN(DB8540_PIN_B14, "GPIO231_B14"), + PINCTRL_PIN(DB8540_PIN_E11, "GPIO232_E11"), + /* Hole */ + PINCTRL_PIN(DB8540_PIN_D12, "GPIO256_D12"), + PINCTRL_PIN(DB8540_PIN_D15, "GPIO257_D15"), + PINCTRL_PIN(DB8540_PIN_C13, "GPIO258_C13"), + PINCTRL_PIN(DB8540_PIN_C14, "GPIO259_C14"), + PINCTRL_PIN(DB8540_PIN_C18, "GPIO260_C18"), + PINCTRL_PIN(DB8540_PIN_C16, "GPIO261_C16"), + PINCTRL_PIN(DB8540_PIN_B16, "GPIO262_B16"), + PINCTRL_PIN(DB8540_PIN_D18, "GPIO263_D18"), + PINCTRL_PIN(DB8540_PIN_C15, "GPIO264_C15"), + PINCTRL_PIN(DB8540_PIN_C17, "GPIO265_C17"), + PINCTRL_PIN(DB8540_PIN_B17, "GPIO266_B17"), + PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"), +}; + +#define DB8540_GPIO_RANGE(a, b, c) { .name = "db8540", .id = a, .base = b, \ + .pin_base = b, .npins = c } + +/* + * This matches the 32-pin gpio chips registered by the GPIO portion. This + * cannot be const since we assign the struct gpio_chip * pointer at runtime. + */ +static struct pinctrl_gpio_range nmk_db8540_ranges[] = { + DB8540_GPIO_RANGE(0, 0, 18), + DB8540_GPIO_RANGE(0, 22, 7), + DB8540_GPIO_RANGE(1, 33, 6), + DB8540_GPIO_RANGE(2, 64, 4), + DB8540_GPIO_RANGE(2, 70, 18), + DB8540_GPIO_RANGE(3, 116, 12), + DB8540_GPIO_RANGE(4, 128, 32), + DB8540_GPIO_RANGE(5, 160, 9), + DB8540_GPIO_RANGE(6, 192, 23), + DB8540_GPIO_RANGE(6, 219, 5), + DB8540_GPIO_RANGE(7, 224, 9), + DB8540_GPIO_RANGE(8, 256, 12), +}; + +/* + * Read the pin group names like this: + * u0_a_1 = first groups of pins for uart0 on alt function a + * i2c2_b_2 = second group of pins for i2c2 on alt function b + * + * The groups are arranged as sets per altfunction column, so we can + * mux in one group at a time by selecting the same altfunction for them + * all. When functions require pins on different altfunctions, you need + * to combine several groups. + */ + +/* Altfunction A column */ +static const unsigned u0_a_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7, + DB8540_PIN_AF2, DB8540_PIN_AD3 }; +static const unsigned u1rxtx_a_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 }; +static const unsigned u1ctsrts_a_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 }; +/* Image processor I2C line, this is driven by image processor firmware */ +static const unsigned ipi2c_a_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 }; +static const unsigned ipi2c_a_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 }; +/* MSP0 can only be on these pins, but TXD and RXD can be flipped */ +static const unsigned msp0txrx_a_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 }; +static const unsigned msp0tfstck_a_1_pins[] = { DB8540_PIN_AC2, + DB8540_PIN_AC4 }; +static const unsigned msp0rfsrck_a_1_pins[] = { DB8540_PIN_AH7, + DB8540_PIN_AE7 }; +/* Basic pins of the MMC/SD card 0 interface */ +static const unsigned mc0_a_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11, + DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10}; +/* MSP1 can only be on these pins, but TXD and RXD can be flipped */ +static const unsigned msp1txrx_a_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 }; +static const unsigned msp1_a_1_pins[] = { DB8540_PIN_AF3, DB8540_PIN_AF5 }; + +static const unsigned modobsclk_a_1_pins[] = { DB8540_PIN_AF9 }; +static const unsigned clkoutreq_a_1_pins[] = { DB8540_PIN_AE8 }; +/* LCD interface */ +static const unsigned lcdb_a_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25, + DB8540_PIN_M27, DB8540_PIN_N25 }; +static const unsigned lcdvsi0_a_1_pins[] = { DB8540_PIN_AJ24 }; +static const unsigned lcdvsi1_a_1_pins[] = { DB8540_PIN_AE21 }; +static const unsigned lcd_d0_d7_a_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26, + DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28, + DB8540_PIN_P22, DB8540_PIN_P28 }; +/* D8 thru D11 often used as TVOUT lines */ +static const unsigned lcd_d8_d11_a_1_pins[] = { DB8540_PIN_P26, DB8540_PIN_T22, + DB8540_PIN_R27, DB8540_PIN_P27 }; +static const unsigned lcd_d12_d23_a_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25, + DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21, + DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, + DB8540_PIN_AG20, DB8540_PIN_AE23 }; +static const unsigned kp_a_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19, + DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 }; +/* MC2 has 8 data lines and no direction control, so only for (e)MMC */ +static const unsigned mc2_a_1_pins[] = { DB8540_PIN_AC27, DB8540_PIN_AD27, + DB8540_PIN_AE28, DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, + DB8540_PIN_AF27, DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, + DB8540_PIN_AG24 }; +static const unsigned ssp1_a_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25, + DB8540_PIN_AF26, DB8540_PIN_AF23 }; +static const unsigned ssp0_a_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25, + DB8540_PIN_AH24, DB8540_PIN_AJ25 }; +static const unsigned i2c0_a_1_pins[] = { DB8540_PIN_AG27, DB8540_PIN_AH23 }; +/* + * Image processor GPIO pins are named "ipgpio" and have their own + * numberspace + */ +static const unsigned ipgpio0_a_1_pins[] = { DB8540_PIN_AE26 }; +static const unsigned ipgpio1_a_1_pins[] = { DB8540_PIN_AE24 }; +/* modem i2s interface */ +static const unsigned modi2s_a_1_pins[] = { DB8540_PIN_AD26, DB8540_PIN_AD28, + DB8540_PIN_AC28, DB8540_PIN_AC26 }; +static const unsigned spi2_a_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21, + DB8540_PIN_AH19, DB8540_PIN_AE19 }; +static const unsigned u2txrx_a_1_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 }; +static const unsigned u2ctsrts_a_1_pins[] = { DB8540_PIN_AF19, + DB8540_PIN_AF18 }; +static const unsigned modsmb_a_1_pins[] = { DB8540_PIN_AF17, DB8540_PIN_AE17 }; +static const unsigned msp2sck_a_1_pins[] = { DB8540_PIN_J3 }; +static const unsigned msp2txdtcktfs_a_1_pins[] = { DB8540_PIN_H1, DB8540_PIN_J2, + DB8540_PIN_H2 }; +static const unsigned msp2rxd_a_1_pins[] = { DB8540_PIN_H3 }; +static const unsigned mc4_a_1_pins[] = { DB8540_PIN_H4, DB8540_PIN_G2, + DB8540_PIN_G3, DB8540_PIN_G4, DB8540_PIN_F2, DB8540_PIN_C6, + DB8540_PIN_B6, DB8540_PIN_B7, DB8540_PIN_A7, DB8540_PIN_D7, + DB8540_PIN_D8 }; +static const unsigned mc1_a_1_pins[] = { DB8540_PIN_F3, DB8540_PIN_E2, + DB8540_PIN_C7, DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8, + DB8540_PIN_C9 }; +/* mc1_a_2_pins exclude MC1_FBCLK */ +static const unsigned mc1_a_2_pins[] = { DB8540_PIN_F3, DB8540_PIN_C7, + DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8, + DB8540_PIN_C9 }; +static const unsigned hsir_a_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10, + DB8540_PIN_D9 }; +static const unsigned hsit_a_1_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10, + DB8540_PIN_E10, DB8540_PIN_B12, DB8540_PIN_D10 }; +static const unsigned hsit_a_2_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10, + DB8540_PIN_E10, DB8540_PIN_B12 }; +static const unsigned clkout1_a_1_pins[] = { DB8540_PIN_D11 }; +static const unsigned clkout1_a_2_pins[] = { DB8540_PIN_B13 }; +static const unsigned clkout2_a_1_pins[] = { DB8540_PIN_AJ6 }; +static const unsigned clkout2_a_2_pins[] = { DB8540_PIN_C12 }; +static const unsigned msp4_a_1_pins[] = { DB8540_PIN_B14, DB8540_PIN_E11 }; +static const unsigned usb_a_1_pins[] = { DB8540_PIN_D12, DB8540_PIN_D15, + DB8540_PIN_C13, DB8540_PIN_C14, DB8540_PIN_C18, DB8540_PIN_C16, + DB8540_PIN_B16, DB8540_PIN_D18, DB8540_PIN_C15, DB8540_PIN_C17, + DB8540_PIN_B17, DB8540_PIN_D17 }; +/* Altfunction B colum */ +static const unsigned apetrig_b_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7 }; +static const unsigned modtrig_b_1_pins[] = { DB8540_PIN_AF2, DB8540_PIN_AD3 }; +static const unsigned i2c4_b_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 }; +static const unsigned i2c1_b_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 }; +static const unsigned i2c2_b_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 }; +static const unsigned i2c2_b_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 }; +static const unsigned msp0txrx_b_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 }; +static const unsigned i2c1_b_2_pins[] = { DB8540_PIN_AH7, DB8540_PIN_AE7 }; +static const unsigned stmmod_b_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11, + DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 }; +static const unsigned moduartstmmux_b_1_pins[] = { DB8540_PIN_AG11 }; +static const unsigned msp1txrx_b_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 }; +static const unsigned kp_b_1_pins[] = { DB8540_PIN_AJ24, DB8540_PIN_AE21, + DB8540_PIN_M26, DB8540_PIN_M25, DB8540_PIN_M27, DB8540_PIN_N25, + DB8540_PIN_M28, DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, + DB8540_PIN_N27, DB8540_PIN_N28, DB8540_PIN_P22, DB8540_PIN_P28, + DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27, + DB8540_PIN_R26, DB8540_PIN_R25 }; +static const unsigned u2txrx_b_1_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27 }; +static const unsigned sm_b_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21, + DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, + DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22, + DB8540_PIN_AJ21, DB8540_PIN_AC27, DB8540_PIN_AD27, DB8540_PIN_AE28, + DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, DB8540_PIN_AF27, + DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, DB8540_PIN_AG24, + DB8540_PIN_AD25 }; +static const unsigned smcs0_b_1_pins[] = { DB8540_PIN_AG19 }; +static const unsigned smcs1_b_1_pins[] = { DB8540_PIN_AE26 }; +static const unsigned ipgpio7_b_1_pins[] = { DB8540_PIN_AH25 }; +static const unsigned ipgpio2_b_1_pins[] = { DB8540_PIN_AF26 }; +static const unsigned ipgpio3_b_1_pins[] = { DB8540_PIN_AF23 }; +static const unsigned i2c6_b_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25 }; +static const unsigned i2c5_b_1_pins[] = { DB8540_PIN_AH24, DB8540_PIN_AJ25 }; +static const unsigned u3txrx_b_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21 }; +static const unsigned u3ctsrts_b_1_pins[] = { DB8540_PIN_AH19, + DB8540_PIN_AE19 }; +static const unsigned i2c5_b_2_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 }; +static const unsigned i2c4_b_2_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 }; +static const unsigned u4txrx_b_1_pins[] = { DB8540_PIN_AE18, DB8540_PIN_AG17 }; +static const unsigned u4ctsrts_b_1_pins[] = { DB8540_PIN_AF17, + DB8540_PIN_AE17 }; +static const unsigned ddrtrig_b_1_pins[] = { DB8540_PIN_J3 }; +static const unsigned msp4_b_1_pins[] = { DB8540_PIN_H3 }; +static const unsigned pwl_b_1_pins[] = { DB8540_PIN_C6 }; +static const unsigned spi1_b_1_pins[] = { DB8540_PIN_E2, DB8540_PIN_C10, + DB8540_PIN_C8, DB8540_PIN_C9 }; +static const unsigned mc3_b_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10, + DB8540_PIN_D9, DB8540_PIN_B11, DB8540_PIN_B10, DB8540_PIN_E10, + DB8540_PIN_B12 }; +static const unsigned pwl_b_2_pins[] = { DB8540_PIN_D10 }; +static const unsigned pwl_b_3_pins[] = { DB8540_PIN_B13 }; +static const unsigned pwl_b_4_pins[] = { DB8540_PIN_C12 }; +static const unsigned u2txrx_b_2_pins[] = { DB8540_PIN_B17, DB8540_PIN_D17 }; + +/* Altfunction C column */ +static const unsigned ipgpio6_c_1_pins[] = { DB8540_PIN_AG6 }; +static const unsigned ipgpio0_c_1_pins[] = { DB8540_PIN_AD5 }; +static const unsigned ipgpio1_c_1_pins[] = { DB8540_PIN_AF7 }; +static const unsigned ipgpio3_c_1_pins[] = { DB8540_PIN_AE4 }; +static const unsigned ipgpio2_c_1_pins[] = { DB8540_PIN_AD1 }; +static const unsigned u0_c_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AF3, + DB8540_PIN_AF5, DB8540_PIN_AG4 }; +static const unsigned smcleale_c_1_pins[] = { DB8540_PIN_AJ24, + DB8540_PIN_AE21 }; +static const unsigned ipgpio4_c_1_pins[] = { DB8540_PIN_M26 }; +static const unsigned ipgpio5_c_1_pins[] = { DB8540_PIN_M25 }; +static const unsigned ipgpio6_c_2_pins[] = { DB8540_PIN_M27 }; +static const unsigned ipgpio7_c_1_pins[] = { DB8540_PIN_N25 }; +static const unsigned stmape_c_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26, + DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 }; +static const unsigned u2rxtx_c_1_pins[] = { DB8540_PIN_N28, DB8540_PIN_P22 }; +static const unsigned modobsresout_c_1_pins[] = { DB8540_PIN_P28 }; +static const unsigned ipgpio2_c_2_pins[] = { DB8540_PIN_P26 }; +static const unsigned ipgpio3_c_2_pins[] = { DB8540_PIN_T22 }; +static const unsigned ipgpio4_c_2_pins[] = { DB8540_PIN_R27 }; +static const unsigned ipgpio5_c_2_pins[] = { DB8540_PIN_P27 }; +static const unsigned modaccgpo_c_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25, + DB8540_PIN_U22 }; +static const unsigned modobspwrrst_c_1_pins[] = { DB8540_PIN_T27 }; +static const unsigned mc5_c_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21, + DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, + DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22, + DB8540_PIN_AJ21}; +static const unsigned smps0_c_1_pins[] = { DB8540_PIN_AG19 }; +static const unsigned moduart1_c_1_pins[] = { DB8540_PIN_T25, DB8540_PIN_T26 }; +static const unsigned mc2rstn_c_1_pins[] = { DB8540_PIN_AE28 }; +static const unsigned i2c5_c_1_pins[] = { DB8540_PIN_AG28, DB8540_PIN_AF28 }; +static const unsigned ipgpio0_c_2_pins[] = { DB8540_PIN_AG25 }; +static const unsigned ipgpio1_c_2_pins[] = { DB8540_PIN_AG24 }; +static const unsigned kp_c_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25, + DB8540_PIN_AF26, DB8540_PIN_AF23 }; +static const unsigned modrf_c_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25, + DB8540_PIN_AH24 }; +static const unsigned smps1_c_1_pins[] = { DB8540_PIN_AE26 }; +static const unsigned i2c5_c_2_pins[] = { DB8540_PIN_AH19, DB8540_PIN_AE19 }; +static const unsigned u4ctsrts_c_1_pins[] = { DB8540_PIN_AG18, + DB8540_PIN_AH17 }; +static const unsigned u3rxtx_c_1_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 }; +static const unsigned msp4_c_1_pins[] = { DB8540_PIN_J3 }; +static const unsigned mc4rstn_c_1_pins[] = { DB8540_PIN_C6 }; +static const unsigned spi0_c_1_pins[] = { DB8540_PIN_A10, DB8540_PIN_B10, + DB8540_PIN_E10, DB8540_PIN_B12 }; +static const unsigned i2c3_c_1_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 }; + +/* Other alt C1 column */ +static const unsigned spi3_oc1_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5, + DB8540_PIN_AE4, DB8540_PIN_AD1 }; +static const unsigned stmape_oc1_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11, + DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 }; +static const unsigned u2_oc1_1_pins[] = { DB8540_PIN_AG11 }; +static const unsigned remap0_oc1_1_pins[] = { DB8540_PIN_AJ24 }; +static const unsigned remap1_oc1_1_pins[] = { DB8540_PIN_AE21 }; +static const unsigned modobsrefclk_oc1_1_pins[] = { DB8540_PIN_M26 }; +static const unsigned modobspwrctrl_oc1_1_pins[] = { DB8540_PIN_M25 }; +static const unsigned modobsclkout_oc1_1_pins[] = { DB8540_PIN_M27 }; +static const unsigned moduart1_oc1_1_pins[] = { DB8540_PIN_N25 }; +static const unsigned modprcmudbg_oc1_1_pins[] = { DB8540_PIN_M28, + DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, + DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22, + DB8540_PIN_R26, DB8540_PIN_R25, DB8540_PIN_U22, DB8540_PIN_T27, + DB8540_PIN_AH20, DB8540_PIN_AG19, DB8540_PIN_AF22, DB8540_PIN_AJ21, + DB8540_PIN_T25}; +static const unsigned modobsresout_oc1_1_pins[] = { DB8540_PIN_N28 }; +static const unsigned modaccgpo_oc1_1_pins[] = { DB8540_PIN_R27, DB8540_PIN_P27, + DB8540_PIN_T26 }; +static const unsigned kp_oc1_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21, + DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, + DB8540_PIN_AG20, DB8540_PIN_AE23 }; +static const unsigned modxmip_oc1_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25, + DB8540_PIN_AG23, DB8540_PIN_AE25 }; +static const unsigned i2c6_oc1_1_pins[] = { DB8540_PIN_AE26, DB8540_PIN_AE24 }; +static const unsigned u2txrx_oc1_1_pins[] = { DB8540_PIN_B7, DB8540_PIN_A7 }; +static const unsigned u2ctsrts_oc1_1_pins[] = { DB8540_PIN_D7, DB8540_PIN_D8 }; + +/* Other alt C2 column */ +static const unsigned sbag_oc2_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11, + DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 }; +static const unsigned hxclk_oc2_1_pins[] = { DB8540_PIN_M25 }; +static const unsigned modaccuart_oc2_1_pins[] = { DB8540_PIN_N25 }; +static const unsigned stmmod_oc2_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26, + DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 }; +static const unsigned moduartstmmux_oc2_1_pins[] = { DB8540_PIN_N28 }; +static const unsigned hxgpio_oc2_1_pins[] = { DB8540_PIN_P22, DB8540_PIN_P28, + DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27, + DB8540_PIN_R26, DB8540_PIN_R25 }; +static const unsigned sbag_oc2_2_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27, + DB8540_PIN_AG22, DB8540_PIN_AF21, DB8540_PIN_AF24, DB8540_PIN_AH22 }; +static const unsigned modobsservice_oc2_1_pins[] = { DB8540_PIN_AJ23 }; +static const unsigned moduart0_oc2_1_pins[] = { DB8540_PIN_AG20, + DB8540_PIN_AE23 }; +static const unsigned stmape_oc2_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19, + DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 }; +static const unsigned u2_oc2_1_pins[] = { DB8540_PIN_T26, DB8540_PIN_AH21 }; +static const unsigned modxmip_oc2_1_pins[] = { DB8540_PIN_AE26, + DB8540_PIN_AE24 }; + +/* Other alt C3 column */ +static const unsigned modaccgpo_oc3_1_pins[] = { DB8540_PIN_AG11 }; +static const unsigned tpui_oc3_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25, + DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26, + DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28, + DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22, + DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25, + DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21, + DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, + DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AG19, + DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 }; + +/* Other alt C4 column */ +static const unsigned hwobs_oc4_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25, + DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26, + DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28, + DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22, + DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25 }; +static const unsigned moduart1txrx_oc4_1_pins[] = { DB8540_PIN_U22, + DB8540_PIN_T27 }; +static const unsigned moduart1rtscts_oc4_1_pins[] = { DB8540_PIN_AG22, + DB8540_PIN_AF21 }; +static const unsigned modaccuarttxrx_oc4_1_pins[] = { DB8540_PIN_AF24, + DB8540_PIN_AH22 }; +static const unsigned modaccuartrtscts_oc4_1_pins[] = { DB8540_PIN_AJ23, + DB8540_PIN_AH21 }; +static const unsigned stmmod_oc4_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19, + DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 }; +static const unsigned moduartstmmux_oc4_1_pins[] = { DB8540_PIN_T26 }; + +#define DB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct nmk_pingroup nmk_db8540_groups[] = { + /* Altfunction A column */ + DB8540_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(modobsclk_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(clkoutreq_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(modi2s_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(spi2_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(u2txrx_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(u2ctsrts_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(modsmb_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp2txdtcktfs_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp2rxd_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(clkout1_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(clkout1_a_2, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(clkout2_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(clkout2_a_2, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(msp4_a_1, NMK_GPIO_ALT_A), + DB8540_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A), + /* Altfunction B column */ + DB8540_PIN_GROUP(apetrig_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(modtrig_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(moduartstmmux_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(u2txrx_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c6_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c5_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(u3txrx_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(u3ctsrts_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c5_b_2, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(i2c4_b_2, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(u4txrx_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(u4ctsrts_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(msp4_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B), + DB8540_PIN_GROUP(u2txrx_b_2, NMK_GPIO_ALT_B), + /* Altfunction C column */ + DB8540_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(modobsresout_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(modaccgpo_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(modobspwrrst_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(moduart1_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(i2c5_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio0_c_2, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(ipgpio1_c_2, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(modrf_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(i2c5_c_2, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(u4ctsrts_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(u3rxtx_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(msp4_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), + DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C), + + /* Other alt C1 column */ + DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C1), + DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C1), + + /* Other alt C2 column */ + DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C2), + DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C2), + + /* Other alt C3 column */ + DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C3), + DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C3), + + /* Other alt C4 column */ + DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4), + DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C4), + DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C4), + DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C4), + DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C4), + DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C4), + DB8540_PIN_GROUP(moduartstmmux_oc4_1, NMK_GPIO_ALT_C4), + +}; + +/* We use this macro to define the groups applicable to a function */ +#define DB8540_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +DB8540_FUNC_GROUPS(apetrig, "apetrig_b_1"); +DB8540_FUNC_GROUPS(clkout, "clkoutreq_a_1", "clkout1_a_1", "clkout1_a_2", + "clkout2_a_1", "clkout2_a_2"); +DB8540_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1"); +DB8540_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2"); +DB8540_FUNC_GROUPS(hwobs, "hwobs_oc4_1"); +DB8540_FUNC_GROUPS(hx, "hxclk_oc2_1", "hxgpio_oc2_1"); +DB8540_FUNC_GROUPS(i2c0, "i2c0_a_1"); +DB8540_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2"); +DB8540_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2"); +DB8540_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c4_b_1"); +DB8540_FUNC_GROUPS(i2c4, "i2c4_b_2"); +DB8540_FUNC_GROUPS(i2c5, "i2c5_b_1", "i2c5_b_2", "i2c5_c_1", "i2c5_c_2"); +DB8540_FUNC_GROUPS(i2c6, "i2c6_b_1", "i2c6_oc1_1"); +/* The image processor has 8 GPIO pins that can be muxed out */ +DB8540_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio0_c_1", "ipgpio0_c_2", + "ipgpio1_a_1", "ipgpio1_c_1", "ipgpio1_c_2", + "ipgpio2_b_1", "ipgpio2_c_1", "ipgpio2_c_2", + "ipgpio3_b_1", "ipgpio3_c_1", "ipgpio3_c_2", + "ipgpio4_c_1", "ipgpio4_c_2", + "ipgpio5_c_1", "ipgpio5_c_2", + "ipgpio6_c_1", "ipgpio6_c_2", + "ipgpio7_b_1", "ipgpio7_c_1"); +DB8540_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2"); +DB8540_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1"); +DB8540_FUNC_GROUPS(lcd, "lcd_d0_d7_a_1", "lcd_d12_d23_a_1", "lcd_d8_d11_a_1", + "lcdvsi0_a_1", "lcdvsi1_a_1"); +DB8540_FUNC_GROUPS(lcdb, "lcdb_a_1"); +DB8540_FUNC_GROUPS(mc0, "mc0_a_1"); +DB8540_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2"); +DB8540_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); +DB8540_FUNC_GROUPS(mc3, "mc3_b_1"); +DB8540_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); +DB8540_FUNC_GROUPS(mc5, "mc5_c_1"); +DB8540_FUNC_GROUPS(modaccgpo, "modaccgpo_c_1", "modaccgpo_oc1_1", + "modaccgpo_oc3_1"); +DB8540_FUNC_GROUPS(modaccuart, "modaccuart_oc2_1", "modaccuarttxrx_oc4_1", + "modaccuartrtccts_oc4_1"); +DB8540_FUNC_GROUPS(modi2s, "modi2s_a_1"); +DB8540_FUNC_GROUPS(modobs, "modobsclk_a_1", "modobsclkout_oc1_1", + "modobspwrctrl_oc1_1", "modobspwrrst_c_1", + "modobsrefclk_oc1_1", "modobsresout_c_1", + "modobsresout_oc1_1", "modobsservice_oc2_1"); +DB8540_FUNC_GROUPS(modprcmudbg, "modprcmudbg_oc1_1"); +DB8540_FUNC_GROUPS(modrf, "modrf_c_1"); +DB8540_FUNC_GROUPS(modsmb, "modsmb_a_1"); +DB8540_FUNC_GROUPS(modtrig, "modtrig_b_1"); +DB8540_FUNC_GROUPS(moduart, "moduart1_c_1", "moduart1_oc1_1", + "moduart1txrx_oc4_1", "moduart1rtscts_oc4_1", "moduart0_oc2_1"); +DB8540_FUNC_GROUPS(moduartstmmux, "moduartstmmux_b_1", "moduartstmmux_oc2_1", + "moduartstmmux_oc4_1"); +DB8540_FUNC_GROUPS(modxmip, "modxmip_oc1_1", "modxmip_oc2_1"); +/* + * MSP0 can only be on a certain set of pins, but the TX/RX pins can be + * switched around by selecting the altfunction A or B. + */ +DB8540_FUNC_GROUPS(msp0, "msp0rfsrck_a_1", "msp0tfstck_a_1", "msp0txrx_a_1", + "msp0txrx_b_1"); +DB8540_FUNC_GROUPS(msp1, "msp1_a_1", "msp1txrx_a_1", "msp1txrx_b_1"); +DB8540_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2txdtcktfs_a_1", "msp2rxd_a_1"); +DB8540_FUNC_GROUPS(msp4, "msp4_a_1", "msp4_b_1", "msp4_c_1"); +DB8540_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4"); +DB8540_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1"); +DB8540_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc2_2"); +/* Select between CS0 on alt B or PS1 on alt C */ +DB8540_FUNC_GROUPS(sm, "sm_b_1", "smcleale_c_1", "smcs0_b_1", "smcs1_b_1", + "smps0_c_1", "smps1_c_1"); +DB8540_FUNC_GROUPS(spi0, "spi0_c_1"); +DB8540_FUNC_GROUPS(spi1, "spi1_b_1"); +DB8540_FUNC_GROUPS(spi2, "spi2_a_1"); +DB8540_FUNC_GROUPS(spi3, "spi3_oc1_1"); +DB8540_FUNC_GROUPS(ssp0, "ssp0_a_1"); +DB8540_FUNC_GROUPS(ssp1, "ssp1_a_1"); +DB8540_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_oc1_1", "stmape_oc2_1"); +DB8540_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_oc2_1", "stmmod_oc4_1"); +DB8540_FUNC_GROUPS(tpui, "tpui_oc3_1"); +DB8540_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1"); +DB8540_FUNC_GROUPS(u1, "u1ctsrts_a_1", "u1rxtx_a_1"); +DB8540_FUNC_GROUPS(u2, "u2_oc1_1", "u2_oc2_1", "u2ctsrts_a_1", "u2ctsrts_oc1_1", + "u2rxtx_c_1", "u2txrx_a_1", "u2txrx_b_1", "u2txrx_b_2", + "u2txrx_oc1_1"); +DB8540_FUNC_GROUPS(u3, "u3ctsrts_b_1", "u3rxtx_c_1", "u3txrxa_b_1"); +DB8540_FUNC_GROUPS(u4, "u4ctsrts_b_1", "u4ctsrts_c_1", "u4txrx_b_1"); +DB8540_FUNC_GROUPS(usb, "usb_a_1"); + + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct nmk_function nmk_db8540_functions[] = { + FUNCTION(apetrig), + FUNCTION(clkout), + FUNCTION(ddrtrig), + FUNCTION(hsi), + FUNCTION(hwobs), + FUNCTION(hx), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(i2c4), + FUNCTION(i2c5), + FUNCTION(i2c6), + FUNCTION(ipgpio), + FUNCTION(ipi2c), + FUNCTION(kp), + FUNCTION(lcd), + FUNCTION(lcdb), + FUNCTION(mc0), + FUNCTION(mc1), + FUNCTION(mc2), + FUNCTION(mc3), + FUNCTION(mc4), + FUNCTION(mc5), + FUNCTION(modaccgpo), + FUNCTION(modaccuart), + FUNCTION(modi2s), + FUNCTION(modobs), + FUNCTION(modprcmudbg), + FUNCTION(modrf), + FUNCTION(modsmb), + FUNCTION(modtrig), + FUNCTION(moduart), + FUNCTION(modxmip), + FUNCTION(msp0), + FUNCTION(msp1), + FUNCTION(msp2), + FUNCTION(msp4), + FUNCTION(pwl), + FUNCTION(remap), + FUNCTION(sbag), + FUNCTION(sm), + FUNCTION(spi0), + FUNCTION(spi1), + FUNCTION(spi2), + FUNCTION(spi3), + FUNCTION(ssp0), + FUNCTION(ssp1), + FUNCTION(stmape), + FUNCTION(stmmod), + FUNCTION(tpui), + FUNCTION(u0), + FUNCTION(u1), + FUNCTION(u2), + FUNCTION(u3), + FUNCTION(u4), + FUNCTION(usb) +}; + +static const struct prcm_gpiocr_altcx_pin_desc db8540_altcx_pins[] = { + PRCM_GPIOCR_ALTCX(8, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_CLK */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(9, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_RXD */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(10, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_FRM */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(11, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_TXD */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(23, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_CLK_a */ + true, PRCM_IDX_GPIOCR2, 10, /* SBAG_CLK_a */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(24, true, PRCM_IDX_GPIOCR3, 30, /* U2_RXD_g */ + true, PRCM_IDX_GPIOCR2, 10, /* SBAG_VAL_a */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(25, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[0] */ + true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[0] */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(26, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[1] */ + true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[1] */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(27, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[2] */ + true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[2] */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(28, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[3] */ + true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[3] */ + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(64, true, PRCM_IDX_GPIOCR1, 15, /* MODOBS_REFCLK_REQ */ + false, 0, 0, + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_CTL */ + true, PRCM_IDX_GPIOCR2, 23 /* HW_OBS_APE_PRCMU[17] */ + ), + PRCM_GPIOCR_ALTCX(65, true, PRCM_IDX_GPIOCR1, 19, /* MODOBS_PWRCTRL0 */ + true, PRCM_IDX_GPIOCR1, 24, /* Hx_CLK */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_CLK */ + true, PRCM_IDX_GPIOCR2, 24 /* HW_OBS_APE_PRCMU[16] */ + ), + PRCM_GPIOCR_ALTCX(66, true, PRCM_IDX_GPIOCR1, 15, /* MODOBS_CLKOUT1 */ + false, 0, 0, + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[15] */ + true, PRCM_IDX_GPIOCR2, 25 /* HW_OBS_APE_PRCMU[15] */ + ), + PRCM_GPIOCR_ALTCX(67, true, PRCM_IDX_GPIOCR1, 1, /* MODUART1_TXD_a */ + true, PRCM_IDX_GPIOCR1, 6, /* MODACCUART_TXD_a */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[14] */ + true, PRCM_IDX_GPIOCR2, 26 /* HW_OBS_APE_PRCMU[14] */ + ), + PRCM_GPIOCR_ALTCX(70, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[17] */ + true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_CLK_b */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[13] */ + true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[13] */ + ), + PRCM_GPIOCR_ALTCX(71, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[16] */ + true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[3] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[12] */ + true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[12] */ + ), + PRCM_GPIOCR_ALTCX(72, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[15] */ + true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[2] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[11] */ + true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[11] */ + ), + PRCM_GPIOCR_ALTCX(73, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[14] */ + true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[1] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[10] */ + true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[10] */ + ), + PRCM_GPIOCR_ALTCX(74, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[13] */ + true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[0] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[9] */ + true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[9] */ + ), + PRCM_GPIOCR_ALTCX(75, true, PRCM_IDX_GPIOCR1, 12, /* MODOBS_RESOUT0_N */ + true, PRCM_IDX_GPIOCR2, 1, /* MODUART_STMMUX_RXD_b */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[8] */ + true, PRCM_IDX_GPIOCR2, 28 /* HW_OBS_APE_PRCMU[8] */ + ), + PRCM_GPIOCR_ALTCX(76, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[12] */ + true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[7] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[7] */ + true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[7] */ + ), + PRCM_GPIOCR_ALTCX(77, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[11] */ + true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[6] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[6] */ + true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[6] */ + ), + PRCM_GPIOCR_ALTCX(78, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[10] */ + true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[5] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[5] */ + true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[5] */ + ), + PRCM_GPIOCR_ALTCX(79, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[9] */ + true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[4] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[4] */ + true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[4] */ + ), + PRCM_GPIOCR_ALTCX(80, true, PRCM_IDX_GPIOCR1, 26, /* MODACC_GPO[0] */ + true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[3] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[3] */ + true, PRCM_IDX_GPIOCR2, 30 /* HW_OBS_APE_PRCMU[3] */ + ), + PRCM_GPIOCR_ALTCX(81, true, PRCM_IDX_GPIOCR2, 17, /* MODACC_GPO[1] */ + true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[2] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[2] */ + true, PRCM_IDX_GPIOCR2, 30 /* HW_OBS_APE_PRCMU[2] */ + ), + PRCM_GPIOCR_ALTCX(82, true, PRCM_IDX_GPIOCR3, 8, /* MOD_PRCMU_DEBUG[8] */ + true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[1] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[1] */ + true, PRCM_IDX_GPIOCR2, 31 /* HW_OBS_APE_PRCMU[1] */ + ), + PRCM_GPIOCR_ALTCX(83, true, PRCM_IDX_GPIOCR3, 8, /* MOD_PRCMU_DEBUG[7] */ + true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[0] */ + true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[0] */ + true, PRCM_IDX_GPIOCR2, 31 /* HW_OBS_APE_PRCMU[0] */ + ), + PRCM_GPIOCR_ALTCX(84, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[6] */ + true, PRCM_IDX_GPIOCR1, 8, /* SBAG_CLK_b */ + true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[23] */ + true, PRCM_IDX_GPIOCR1, 16 /* MODUART1_RXD_b */ + ), + PRCM_GPIOCR_ALTCX(85, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[5] */ + true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[3] */ + true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[22] */ + true, PRCM_IDX_GPIOCR1, 16 /* MODUART1_TXD_b */ + ), + PRCM_GPIOCR_ALTCX(86, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[0] */ + true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[0] */ + true, PRCM_IDX_GPIOCR1, 14, /* TPIU_D[25] */ + true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[0] */ + ), + PRCM_GPIOCR_ALTCX(87, true, PRCM_IDX_GPIOCR3, 0, /* MODACC_GPO_a[5] */ + true, PRCM_IDX_GPIOCR2, 3, /* U2_RXD_c */ + true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[24] */ + true, PRCM_IDX_GPIOCR1, 21 /* MODUART_STMMUX_RXD_c */ + ), + PRCM_GPIOCR_ALTCX(151, true, PRCM_IDX_GPIOCR1, 18, /* REMAP0 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(152, true, PRCM_IDX_GPIOCR1, 18, /* REMAP1 */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(153, true, PRCM_IDX_GPIOCR3, 2, /* KP_O_b[6] */ + true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[2] */ + true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[21] */ + true, PRCM_IDX_GPIOCR1, 0 /* MODUART1_RTS */ + ), + PRCM_GPIOCR_ALTCX(154, true, PRCM_IDX_GPIOCR3, 2, /* KP_I_b[6] */ + true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[1] */ + true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[20] */ + true, PRCM_IDX_GPIOCR1, 0 /* MODUART1_CTS */ + ), + PRCM_GPIOCR_ALTCX(155, true, PRCM_IDX_GPIOCR3, 3, /* KP_O_b[5] */ + true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[0] */ + true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[19] */ + true, PRCM_IDX_GPIOCR1, 5 /* MODACCUART_RXD_c */ + ), + PRCM_GPIOCR_ALTCX(156, true, PRCM_IDX_GPIOCR3, 3, /* KP_O_b[4] */ + true, PRCM_IDX_GPIOCR1, 8, /* SBAG_VAL_b */ + true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[18] */ + true, PRCM_IDX_GPIOCR1, 5 /* MODACCUART_TXD_b */ + ), + PRCM_GPIOCR_ALTCX(157, true, PRCM_IDX_GPIOCR3, 4, /* KP_I_b[5] */ + true, PRCM_IDX_GPIOCR1, 23, /* MODOBS_SERVICE_N */ + true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[17] */ + true, PRCM_IDX_GPIOCR1, 14 /* MODACCUART_RTS */ + ), + PRCM_GPIOCR_ALTCX(158, true, PRCM_IDX_GPIOCR3, 4, /* KP_I_b[4] */ + true, PRCM_IDX_GPIOCR2, 0, /* U2_TXD_c */ + true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[16] */ + true, PRCM_IDX_GPIOCR1, 14 /* MODACCUART_CTS */ + ), + PRCM_GPIOCR_ALTCX(159, true, PRCM_IDX_GPIOCR3, 5, /* KP_O_b[3] */ + true, PRCM_IDX_GPIOCR3, 10, /* MODUART0_RXD */ + true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[31] */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(160, true, PRCM_IDX_GPIOCR3, 5, /* KP_I_b[3] */ + true, PRCM_IDX_GPIOCR3, 10, /* MODUART0_TXD */ + true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[30] */ + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(161, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[4] */ + true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_CLK_b */ + true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[29] */ + true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_CLK_c */ + ), + PRCM_GPIOCR_ALTCX(162, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[3] */ + true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[3] */ + true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[28] */ + true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[3] */ + ), + PRCM_GPIOCR_ALTCX(163, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[2] */ + true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[2] */ + true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[27] */ + true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[2] */ + ), + PRCM_GPIOCR_ALTCX(164, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[1] */ + true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[1] */ + true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[26] */ + true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[1] */ + ), + PRCM_GPIOCR_ALTCX(204, true, PRCM_IDX_GPIOCR2, 2, /* U2_RXD_f */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(205, true, PRCM_IDX_GPIOCR2, 2, /* U2_TXD_f */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(206, true, PRCM_IDX_GPIOCR2, 2, /* U2_CTSn_b */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), + PRCM_GPIOCR_ALTCX(207, true, PRCM_IDX_GPIOCR2, 2, /* U2_RTSn_b */ + false, 0, 0, + false, 0, 0, + false, 0, 0 + ), +}; + +static const u16 db8540_prcm_gpiocr_regs[] = { + [PRCM_IDX_GPIOCR1] = 0x138, + [PRCM_IDX_GPIOCR2] = 0x574, + [PRCM_IDX_GPIOCR3] = 0x2bc, +}; + +static const struct nmk_pinctrl_soc_data nmk_db8540_soc = { + .gpio_ranges = nmk_db8540_ranges, + .gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges), + .pins = nmk_db8540_pins, + .npins = ARRAY_SIZE(nmk_db8540_pins), + .functions = nmk_db8540_functions, + .nfunctions = ARRAY_SIZE(nmk_db8540_functions), + .groups = nmk_db8540_groups, + .ngroups = ARRAY_SIZE(nmk_db8540_groups), + .altcx_pins = db8540_altcx_pins, + .npins_altcx = ARRAY_SIZE(db8540_altcx_pins), + .prcm_gpiocr_registers = db8540_prcm_gpiocr_regs, +}; + +void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc) +{ + *soc = &nmk_db8540_soc; +} diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c new file mode 100644 index 000000000000..ed39dcafd4f8 --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c @@ -0,0 +1,356 @@ +#include +#include +#include "pinctrl-nomadik.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define _GPIO(offset) (offset) + +#define STN8815_PIN_B4 _GPIO(0) +#define STN8815_PIN_D5 _GPIO(1) +#define STN8815_PIN_C5 _GPIO(2) +#define STN8815_PIN_A4 _GPIO(3) +#define STN8815_PIN_B5 _GPIO(4) +#define STN8815_PIN_D6 _GPIO(5) +#define STN8815_PIN_C6 _GPIO(6) +#define STN8815_PIN_B6 _GPIO(7) +#define STN8815_PIN_B10 _GPIO(8) +#define STN8815_PIN_A10 _GPIO(9) +#define STN8815_PIN_C11 _GPIO(10) +#define STN8815_PIN_B11 _GPIO(11) +#define STN8815_PIN_A11 _GPIO(12) +#define STN8815_PIN_C12 _GPIO(13) +#define STN8815_PIN_B12 _GPIO(14) +#define STN8815_PIN_A12 _GPIO(15) +#define STN8815_PIN_C13 _GPIO(16) +#define STN8815_PIN_B13 _GPIO(17) +#define STN8815_PIN_A13 _GPIO(18) +#define STN8815_PIN_D13 _GPIO(19) +#define STN8815_PIN_C14 _GPIO(20) +#define STN8815_PIN_B14 _GPIO(21) +#define STN8815_PIN_A14 _GPIO(22) +#define STN8815_PIN_D15 _GPIO(23) +#define STN8815_PIN_C15 _GPIO(24) +#define STN8815_PIN_B15 _GPIO(25) +#define STN8815_PIN_A15 _GPIO(26) +#define STN8815_PIN_C16 _GPIO(27) +#define STN8815_PIN_B16 _GPIO(28) +#define STN8815_PIN_A16 _GPIO(29) +#define STN8815_PIN_D17 _GPIO(30) +#define STN8815_PIN_C17 _GPIO(31) +#define STN8815_PIN_AB6 _GPIO(32) +#define STN8815_PIN_AA6 _GPIO(33) +#define STN8815_PIN_Y6 _GPIO(34) +#define STN8815_PIN_Y5 _GPIO(35) +#define STN8815_PIN_AA5 _GPIO(36) +#define STN8815_PIN_AB5 _GPIO(37) +#define STN8815_PIN_AB4 _GPIO(38) +#define STN8815_PIN_Y4 _GPIO(39) +#define STN8815_PIN_R1 _GPIO(40) +#define STN8815_PIN_R2 _GPIO(41) +#define STN8815_PIN_R3 _GPIO(42) +#define STN8815_PIN_P1 _GPIO(43) +#define STN8815_PIN_P2 _GPIO(44) +#define STN8815_PIN_P3 _GPIO(45) +#define STN8815_PIN_N1 _GPIO(46) +#define STN8815_PIN_N2 _GPIO(47) +#define STN8815_PIN_N3 _GPIO(48) +#define STN8815_PIN_M1 _GPIO(49) +#define STN8815_PIN_M3 _GPIO(50) +#define STN8815_PIN_M2 _GPIO(51) +#define STN8815_PIN_L1 _GPIO(52) +#define STN8815_PIN_L4 _GPIO(53) +#define STN8815_PIN_L3 _GPIO(54) +#define STN8815_PIN_L2 _GPIO(55) +#define STN8815_PIN_F3 _GPIO(56) +#define STN8815_PIN_F2 _GPIO(57) +#define STN8815_PIN_E1 _GPIO(58) +#define STN8815_PIN_E3 _GPIO(59) +#define STN8815_PIN_E2 _GPIO(60) +#define STN8815_PIN_E4 _GPIO(61) +#define STN8815_PIN_D3 _GPIO(62) +#define STN8815_PIN_D2 _GPIO(63) +#define STN8815_PIN_F21 _GPIO(64) +#define STN8815_PIN_F20 _GPIO(65) +#define STN8815_PIN_E22 _GPIO(66) +#define STN8815_PIN_D22 _GPIO(67) +#define STN8815_PIN_E21 _GPIO(68) +#define STN8815_PIN_E20 _GPIO(69) +#define STN8815_PIN_C22 _GPIO(70) +#define STN8815_PIN_D21 _GPIO(71) +#define STN8815_PIN_D20 _GPIO(72) +#define STN8815_PIN_C21 _GPIO(73) +#define STN8815_PIN_C20 _GPIO(74) +#define STN8815_PIN_C19 _GPIO(75) +#define STN8815_PIN_B20 _GPIO(76) +#define STN8815_PIN_B8 _GPIO(77) +#define STN8815_PIN_A8 _GPIO(78) +#define STN8815_PIN_C9 _GPIO(79) +#define STN8815_PIN_B9 _GPIO(80) +#define STN8815_PIN_A9 _GPIO(81) +#define STN8815_PIN_C10 _GPIO(82) +#define STN8815_PIN_K1 _GPIO(83) +#define STN8815_PIN_K3 _GPIO(84) +#define STN8815_PIN_K2 _GPIO(85) +#define STN8815_PIN_J1 _GPIO(86) +#define STN8815_PIN_J3 _GPIO(87) +#define STN8815_PIN_J2 _GPIO(88) +#define STN8815_PIN_H1 _GPIO(89) +#define STN8815_PIN_H3 _GPIO(90) +#define STN8815_PIN_H2 _GPIO(91) +#define STN8815_PIN_G1 _GPIO(92) +#define STN8815_PIN_G3 _GPIO(93) +#define STN8815_PIN_G2 _GPIO(94) +#define STN8815_PIN_F1 _GPIO(95) +#define STN8815_PIN_T20 _GPIO(96) +#define STN8815_PIN_R21 _GPIO(97) +#define STN8815_PIN_R20 _GPIO(98) +#define STN8815_PIN_U22 _GPIO(99) +#define STN8815_PIN_N21 _GPIO(100) +#define STN8815_PIN_N20 _GPIO(101) +#define STN8815_PIN_P22 _GPIO(102) +#define STN8815_PIN_N22 _GPIO(103) +#define STN8815_PIN_V22 _GPIO(104) +#define STN8815_PIN_V21 _GPIO(105) +#define STN8815_PIN_K22 _GPIO(106) +#define STN8815_PIN_K21 _GPIO(107) +#define STN8815_PIN_H20 _GPIO(108) +#define STN8815_PIN_G20 _GPIO(109) +#define STN8815_PIN_L21 _GPIO(110) +#define STN8815_PIN_H21 _GPIO(111) +#define STN8815_PIN_J21 _GPIO(112) +#define STN8815_PIN_H22 _GPIO(113) +#define STN8815_PIN_K20 _GPIO(114) +#define STN8815_PIN_L22 _GPIO(115) +#define STN8815_PIN_G21 _GPIO(116) +#define STN8815_PIN_J20 _GPIO(117) +#define STN8815_PIN_G22 _GPIO(118) +#define STN8815_PIN_U19 _GPIO(119) +#define STN8815_PIN_G19 _GPIO(120) +#define STN8815_PIN_M22 _GPIO(121) +#define STN8815_PIN_M19 _GPIO(122) +#define STN8815_PIN_J22 _GPIO(123) +/* GPIOs 124-127 not routed to pins */ + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc nmk_stn8815_pins[] = { + PINCTRL_PIN(STN8815_PIN_B4, "GPIO0_B4"), + PINCTRL_PIN(STN8815_PIN_D5, "GPIO1_D5"), + PINCTRL_PIN(STN8815_PIN_C5, "GPIO2_C5"), + PINCTRL_PIN(STN8815_PIN_A4, "GPIO3_A4"), + PINCTRL_PIN(STN8815_PIN_B5, "GPIO4_B5"), + PINCTRL_PIN(STN8815_PIN_D6, "GPIO5_D6"), + PINCTRL_PIN(STN8815_PIN_C6, "GPIO6_C6"), + PINCTRL_PIN(STN8815_PIN_B6, "GPIO7_B6"), + PINCTRL_PIN(STN8815_PIN_B10, "GPIO8_B10"), + PINCTRL_PIN(STN8815_PIN_A10, "GPIO9_A10"), + PINCTRL_PIN(STN8815_PIN_C11, "GPIO10_C11"), + PINCTRL_PIN(STN8815_PIN_B11, "GPIO11_B11"), + PINCTRL_PIN(STN8815_PIN_A11, "GPIO12_A11"), + PINCTRL_PIN(STN8815_PIN_C12, "GPIO13_C12"), + PINCTRL_PIN(STN8815_PIN_B12, "GPIO14_B12"), + PINCTRL_PIN(STN8815_PIN_A12, "GPIO15_A12"), + PINCTRL_PIN(STN8815_PIN_C13, "GPIO16_C13"), + PINCTRL_PIN(STN8815_PIN_B13, "GPIO17_B13"), + PINCTRL_PIN(STN8815_PIN_A13, "GPIO18_A13"), + PINCTRL_PIN(STN8815_PIN_D13, "GPIO19_D13"), + PINCTRL_PIN(STN8815_PIN_C14, "GPIO20_C14"), + PINCTRL_PIN(STN8815_PIN_B14, "GPIO21_B14"), + PINCTRL_PIN(STN8815_PIN_A14, "GPIO22_A14"), + PINCTRL_PIN(STN8815_PIN_D15, "GPIO23_D15"), + PINCTRL_PIN(STN8815_PIN_C15, "GPIO24_C15"), + PINCTRL_PIN(STN8815_PIN_B15, "GPIO25_B15"), + PINCTRL_PIN(STN8815_PIN_A15, "GPIO26_A15"), + PINCTRL_PIN(STN8815_PIN_C16, "GPIO27_C16"), + PINCTRL_PIN(STN8815_PIN_B16, "GPIO28_B16"), + PINCTRL_PIN(STN8815_PIN_A16, "GPIO29_A16"), + PINCTRL_PIN(STN8815_PIN_D17, "GPIO30_D17"), + PINCTRL_PIN(STN8815_PIN_C17, "GPIO31_C17"), + PINCTRL_PIN(STN8815_PIN_AB6, "GPIO32_AB6"), + PINCTRL_PIN(STN8815_PIN_AA6, "GPIO33_AA6"), + PINCTRL_PIN(STN8815_PIN_Y6, "GPIO34_Y6"), + PINCTRL_PIN(STN8815_PIN_Y5, "GPIO35_Y5"), + PINCTRL_PIN(STN8815_PIN_AA5, "GPIO36_AA5"), + PINCTRL_PIN(STN8815_PIN_AB5, "GPIO37_AB5"), + PINCTRL_PIN(STN8815_PIN_AB4, "GPIO38_AB4"), + PINCTRL_PIN(STN8815_PIN_Y4, "GPIO39_Y4"), + PINCTRL_PIN(STN8815_PIN_R1, "GPIO40_R1"), + PINCTRL_PIN(STN8815_PIN_R2, "GPIO41_R2"), + PINCTRL_PIN(STN8815_PIN_R3, "GPIO42_R3"), + PINCTRL_PIN(STN8815_PIN_P1, "GPIO43_P1"), + PINCTRL_PIN(STN8815_PIN_P2, "GPIO44_P2"), + PINCTRL_PIN(STN8815_PIN_P3, "GPIO45_P3"), + PINCTRL_PIN(STN8815_PIN_N1, "GPIO46_N1"), + PINCTRL_PIN(STN8815_PIN_N2, "GPIO47_N2"), + PINCTRL_PIN(STN8815_PIN_N3, "GPIO48_N3"), + PINCTRL_PIN(STN8815_PIN_M1, "GPIO49_M1"), + PINCTRL_PIN(STN8815_PIN_M3, "GPIO50_M3"), + PINCTRL_PIN(STN8815_PIN_M2, "GPIO51_M2"), + PINCTRL_PIN(STN8815_PIN_L1, "GPIO52_L1"), + PINCTRL_PIN(STN8815_PIN_L4, "GPIO53_L4"), + PINCTRL_PIN(STN8815_PIN_L3, "GPIO54_L3"), + PINCTRL_PIN(STN8815_PIN_L2, "GPIO55_L2"), + PINCTRL_PIN(STN8815_PIN_F3, "GPIO56_F3"), + PINCTRL_PIN(STN8815_PIN_F2, "GPIO57_F2"), + PINCTRL_PIN(STN8815_PIN_E1, "GPIO58_E1"), + PINCTRL_PIN(STN8815_PIN_E3, "GPIO59_E3"), + PINCTRL_PIN(STN8815_PIN_E2, "GPIO60_E2"), + PINCTRL_PIN(STN8815_PIN_E4, "GPIO61_E4"), + PINCTRL_PIN(STN8815_PIN_D3, "GPIO62_D3"), + PINCTRL_PIN(STN8815_PIN_D2, "GPIO63_D2"), + PINCTRL_PIN(STN8815_PIN_F21, "GPIO64_F21"), + PINCTRL_PIN(STN8815_PIN_F20, "GPIO65_F20"), + PINCTRL_PIN(STN8815_PIN_E22, "GPIO66_E22"), + PINCTRL_PIN(STN8815_PIN_D22, "GPIO67_D22"), + PINCTRL_PIN(STN8815_PIN_E21, "GPIO68_E21"), + PINCTRL_PIN(STN8815_PIN_E20, "GPIO69_E20"), + PINCTRL_PIN(STN8815_PIN_C22, "GPIO70_C22"), + PINCTRL_PIN(STN8815_PIN_D21, "GPIO71_D21"), + PINCTRL_PIN(STN8815_PIN_D20, "GPIO72_D20"), + PINCTRL_PIN(STN8815_PIN_C21, "GPIO73_C21"), + PINCTRL_PIN(STN8815_PIN_C20, "GPIO74_C20"), + PINCTRL_PIN(STN8815_PIN_C19, "GPIO75_C19"), + PINCTRL_PIN(STN8815_PIN_B20, "GPIO76_B20"), + PINCTRL_PIN(STN8815_PIN_B8, "GPIO77_B8"), + PINCTRL_PIN(STN8815_PIN_A8, "GPIO78_A8"), + PINCTRL_PIN(STN8815_PIN_C9, "GPIO79_C9"), + PINCTRL_PIN(STN8815_PIN_B9, "GPIO80_B9"), + PINCTRL_PIN(STN8815_PIN_A9, "GPIO81_A9"), + PINCTRL_PIN(STN8815_PIN_C10, "GPIO82_C10"), + PINCTRL_PIN(STN8815_PIN_K1, "GPIO83_K1"), + PINCTRL_PIN(STN8815_PIN_K3, "GPIO84_K3"), + PINCTRL_PIN(STN8815_PIN_K2, "GPIO85_K2"), + PINCTRL_PIN(STN8815_PIN_J1, "GPIO86_J1"), + PINCTRL_PIN(STN8815_PIN_J3, "GPIO87_J3"), + PINCTRL_PIN(STN8815_PIN_J2, "GPIO88_J2"), + PINCTRL_PIN(STN8815_PIN_H1, "GPIO89_H1"), + PINCTRL_PIN(STN8815_PIN_H3, "GPIO90_H3"), + PINCTRL_PIN(STN8815_PIN_H2, "GPIO91_H2"), + PINCTRL_PIN(STN8815_PIN_G1, "GPIO92_G1"), + PINCTRL_PIN(STN8815_PIN_G3, "GPIO93_G3"), + PINCTRL_PIN(STN8815_PIN_G2, "GPIO94_G2"), + PINCTRL_PIN(STN8815_PIN_F1, "GPIO95_F1"), + PINCTRL_PIN(STN8815_PIN_T20, "GPIO96_T20"), + PINCTRL_PIN(STN8815_PIN_R21, "GPIO97_R21"), + PINCTRL_PIN(STN8815_PIN_R20, "GPIO98_R20"), + PINCTRL_PIN(STN8815_PIN_U22, "GPIO99_U22"), + PINCTRL_PIN(STN8815_PIN_N21, "GPIO100_N21"), + PINCTRL_PIN(STN8815_PIN_N20, "GPIO101_N20"), + PINCTRL_PIN(STN8815_PIN_P22, "GPIO102_P22"), + PINCTRL_PIN(STN8815_PIN_N22, "GPIO103_N22"), + PINCTRL_PIN(STN8815_PIN_V22, "GPIO104_V22"), + PINCTRL_PIN(STN8815_PIN_V21, "GPIO105_V21"), + PINCTRL_PIN(STN8815_PIN_K22, "GPIO106_K22"), + PINCTRL_PIN(STN8815_PIN_K21, "GPIO107_K21"), + PINCTRL_PIN(STN8815_PIN_H20, "GPIO108_H20"), + PINCTRL_PIN(STN8815_PIN_G20, "GPIO109_G20"), + PINCTRL_PIN(STN8815_PIN_L21, "GPIO110_L21"), + PINCTRL_PIN(STN8815_PIN_H21, "GPIO111_H21"), + PINCTRL_PIN(STN8815_PIN_J21, "GPIO112_J21"), + PINCTRL_PIN(STN8815_PIN_H22, "GPIO113_H22"), + PINCTRL_PIN(STN8815_PIN_K20, "GPIO114_K20"), + PINCTRL_PIN(STN8815_PIN_L22, "GPIO115_L22"), + PINCTRL_PIN(STN8815_PIN_G21, "GPIO116_G21"), + PINCTRL_PIN(STN8815_PIN_J20, "GPIO117_J20"), + PINCTRL_PIN(STN8815_PIN_G22, "GPIO118_G22"), + PINCTRL_PIN(STN8815_PIN_U19, "GPIO119_U19"), + PINCTRL_PIN(STN8815_PIN_G19, "GPIO120_G19"), + PINCTRL_PIN(STN8815_PIN_M22, "GPIO121_M22"), + PINCTRL_PIN(STN8815_PIN_M19, "GPIO122_M19"), + PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"), +}; + +#define STN8815_GPIO_RANGE(a, b, c) { .name = "STN8815", .id = a, .base = b, \ + .pin_base = b, .npins = c } + +/* + * This matches the 32-pin gpio chips registered by the GPIO portion. This + * cannot be const since we assign the struct gpio_chip * pointer at runtime. + */ +static struct pinctrl_gpio_range nmk_stn8815_ranges[] = { + STN8815_GPIO_RANGE(0, 0, 32), + STN8815_GPIO_RANGE(1, 32, 32), + STN8815_GPIO_RANGE(2, 64, 32), + STN8815_GPIO_RANGE(3, 96, 28), +}; + +/* + * Read the pin group names like this: + * u0_a_1 = first groups of pins for uart0 on alt function a + * i2c2_b_2 = second group of pins for i2c2 on alt function b + */ + +/* Altfunction A */ +static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5, + STN8815_PIN_C5, STN8815_PIN_A4, STN8815_PIN_B5, STN8815_PIN_D6, + STN8815_PIN_C6, STN8815_PIN_B6 }; +static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10, + STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12, + STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 }; +static const unsigned u1_a_1_pins[] = { STN8815_PIN_M2, STN8815_PIN_L1, + STN8815_PIN_F3, STN8815_PIN_F2 }; +static const unsigned i2c1_a_1_pins[] = { STN8815_PIN_L4, STN8815_PIN_L3 }; +static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 }; +/* Altfunction B */ +static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 }; +static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 }; + +#define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct nmk_pingroup nmk_stn8815_groups[] = { + STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), + STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A), + STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A), + STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A), + STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), + STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B), + STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B), +}; + +/* We use this macro to define the groups applicable to a function */ +#define STN8815_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +STN8815_FUNC_GROUPS(u0, "u0_a_1"); +STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1"); +STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1"); +STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1"); +STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1"); +STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1"); + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct nmk_function nmk_stn8815_functions[] = { + FUNCTION(u0), + FUNCTION(mmcsd), + FUNCTION(u1), + FUNCTION(i2c1), + FUNCTION(i2c0), + FUNCTION(i2cusb), +}; + +static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = { + .gpio_ranges = nmk_stn8815_ranges, + .gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges), + .pins = nmk_stn8815_pins, + .npins = ARRAY_SIZE(nmk_stn8815_pins), + .functions = nmk_stn8815_functions, + .nfunctions = ARRAY_SIZE(nmk_stn8815_functions), + .groups = nmk_stn8815_groups, + .ngroups = ARRAY_SIZE(nmk_stn8815_groups), +}; + +void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc) +{ + *soc = &nmk_stn8815_soc; +} diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c new file mode 100644 index 000000000000..e7cab07eef47 --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -0,0 +1,2099 @@ +/* + * Generic GPIO driver for logic cells found in the Nomadik SoC + * + * Copyright (C) 2008,2009 STMicroelectronics + * Copyright (C) 2009 Alessandro Rubini + * Rewritten based on work by Prafulla WADASKAR + * Copyright (C) 2011-2013 Linus Walleij + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* Since we request GPIOs from ourself */ +#include +#include "pinctrl-nomadik.h" +#include "../core.h" + +/* + * The GPIO module in the Nomadik family of Systems-on-Chip is an + * AMBA device, managing 32 pins and alternate functions. The logic block + * is currently used in the Nomadik and ux500. + * + * Symbols in this file are called "nmk_gpio" for "nomadik gpio" + */ + +/* + * pin configurations are represented by 32-bit integers: + * + * bit 0.. 8 - Pin Number (512 Pins Maximum) + * bit 9..10 - Alternate Function Selection + * bit 11..12 - Pull up/down state + * bit 13 - Sleep mode behaviour + * bit 14 - Direction + * bit 15 - Value (if output) + * bit 16..18 - SLPM pull up/down state + * bit 19..20 - SLPM direction + * bit 21..22 - SLPM Value (if output) + * bit 23..25 - PDIS value (if input) + * bit 26 - Gpio mode + * bit 27 - Sleep mode + * + * to facilitate the definition, the following macros are provided + * + * PIN_CFG_DEFAULT - default config (0): + * pull up/down = disabled + * sleep mode = input/wakeup + * direction = input + * value = low + * SLPM direction = same as normal + * SLPM pull = same as normal + * SLPM value = same as normal + * + * PIN_CFG - default config with alternate function + */ + +typedef unsigned long pin_cfg_t; + +#define PIN_NUM_MASK 0x1ff +#define PIN_NUM(x) ((x) & PIN_NUM_MASK) + +#define PIN_ALT_SHIFT 9 +#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) +#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) +#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) +#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) +#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) +#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) + +#define PIN_PULL_SHIFT 11 +#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) +#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) +#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) +#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) +#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) + +#define PIN_SLPM_SHIFT 13 +#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) +#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) +#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) +#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) +/* These two replace the above in DB8500v2+ */ +#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE + +#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ +#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ + +#define PIN_DIR_SHIFT 14 +#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) +#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) +#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) +#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) + +#define PIN_VAL_SHIFT 15 +#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) +#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) +#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) +#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) + +#define PIN_SLPM_PULL_SHIFT 16 +#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL(x) \ + (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_NONE \ + ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_UP \ + ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_DOWN \ + ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) + +#define PIN_SLPM_DIR_SHIFT 19 +#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR(x) \ + (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) + +#define PIN_SLPM_VAL_SHIFT 21 +#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL(x) \ + (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) + +#define PIN_SLPM_PDIS_SHIFT 23 +#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) +#define PIN_SLPM_PDIS(x) \ + (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) +#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) +#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) +#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) + +#define PIN_LOWEMI_SHIFT 25 +#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) + +#define PIN_GPIOMODE_SHIFT 26 +#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) +#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) +#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) +#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) + +#define PIN_SLEEPMODE_SHIFT 27 +#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) +#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) +#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) +#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) + + +/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ +#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) +#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) +#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) +#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) +#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) + +#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) +#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) +#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) +#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) +#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) + +#define PIN_CFG_DEFAULT (0) + +#define PIN_CFG(num, alt) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt)) + +#define PIN_CFG_INPUT(num, alt, pull) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) + +#define PIN_CFG_OUTPUT(num, alt, val) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) + +/* + * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving + * the "gpio" namespace for generic and cross-machine functions + */ + +#define GPIO_BLOCK_SHIFT 5 +#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) + +/* Register in the logic block */ +#define NMK_GPIO_DAT 0x00 +#define NMK_GPIO_DATS 0x04 +#define NMK_GPIO_DATC 0x08 +#define NMK_GPIO_PDIS 0x0c +#define NMK_GPIO_DIR 0x10 +#define NMK_GPIO_DIRS 0x14 +#define NMK_GPIO_DIRC 0x18 +#define NMK_GPIO_SLPC 0x1c +#define NMK_GPIO_AFSLA 0x20 +#define NMK_GPIO_AFSLB 0x24 +#define NMK_GPIO_LOWEMI 0x28 + +#define NMK_GPIO_RIMSC 0x40 +#define NMK_GPIO_FIMSC 0x44 +#define NMK_GPIO_IS 0x48 +#define NMK_GPIO_IC 0x4c +#define NMK_GPIO_RWIMSC 0x50 +#define NMK_GPIO_FWIMSC 0x54 +#define NMK_GPIO_WKS 0x58 +/* These appear in DB8540 and later ASICs */ +#define NMK_GPIO_EDGELEVEL 0x5C +#define NMK_GPIO_LEVEL 0x60 + + +/* Pull up/down values */ +enum nmk_gpio_pull { + NMK_GPIO_PULL_NONE, + NMK_GPIO_PULL_UP, + NMK_GPIO_PULL_DOWN, +}; + +/* Sleep mode */ +enum nmk_gpio_slpm { + NMK_GPIO_SLPM_INPUT, + NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, + NMK_GPIO_SLPM_NOCHANGE, + NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, +}; + +struct nmk_gpio_chip { + struct gpio_chip chip; + void __iomem *addr; + struct clk *clk; + unsigned int bank; + unsigned int parent_irq; + int latent_parent_irq; + u32 (*get_latent_status)(unsigned int bank); + void (*set_ioforce)(bool enable); + spinlock_t lock; + bool sleepmode; + /* Keep track of configured edges */ + u32 edge_rising; + u32 edge_falling; + u32 real_wake; + u32 rwimsc; + u32 fwimsc; + u32 rimsc; + u32 fimsc; + u32 pull_up; + u32 lowemi; +}; + +/** + * struct nmk_pinctrl - state container for the Nomadik pin controller + * @dev: containing device pointer + * @pctl: corresponding pin controller device + * @soc: SoC data for this specific chip + * @prcm_base: PRCM register range virtual base + */ +struct nmk_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + const struct nmk_pinctrl_soc_data *soc; + void __iomem *prcm_base; +}; + +static struct nmk_gpio_chip * +nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; + +static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); + +#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) + +static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int gpio_mode) +{ + u32 bit = 1 << offset; + u32 afunc, bfunc; + + afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; + bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; + if (gpio_mode & NMK_GPIO_ALT_A) + afunc |= bit; + if (gpio_mode & NMK_GPIO_ALT_B) + bfunc |= bit; + writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); + writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); +} + +static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, + unsigned offset, enum nmk_gpio_slpm mode) +{ + u32 bit = 1 << offset; + u32 slpm; + + slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); + if (mode == NMK_GPIO_SLPM_NOCHANGE) + slpm |= bit; + else + slpm &= ~bit; + writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); +} + +static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, + unsigned offset, enum nmk_gpio_pull pull) +{ + u32 bit = 1 << offset; + u32 pdis; + + pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); + if (pull == NMK_GPIO_PULL_NONE) { + pdis |= bit; + nmk_chip->pull_up &= ~bit; + } else { + pdis &= ~bit; + } + + writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); + + if (pull == NMK_GPIO_PULL_UP) { + nmk_chip->pull_up |= bit; + writel(bit, nmk_chip->addr + NMK_GPIO_DATS); + } else if (pull == NMK_GPIO_PULL_DOWN) { + nmk_chip->pull_up &= ~bit; + writel(bit, nmk_chip->addr + NMK_GPIO_DATC); + } +} + +static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, + unsigned offset, bool lowemi) +{ + u32 bit = BIT(offset); + bool enabled = nmk_chip->lowemi & bit; + + if (lowemi == enabled) + return; + + if (lowemi) + nmk_chip->lowemi |= bit; + else + nmk_chip->lowemi &= ~bit; + + writel_relaxed(nmk_chip->lowemi, + nmk_chip->addr + NMK_GPIO_LOWEMI); +} + +static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, + unsigned offset) +{ + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); +} + +static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int val) +{ + if (val) + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); + else + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); +} + +static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int val) +{ + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); + __nmk_gpio_set_output(nmk_chip, offset, val); +} + +static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int gpio_mode, + bool glitch) +{ + u32 rwimsc = nmk_chip->rwimsc; + u32 fwimsc = nmk_chip->fwimsc; + + if (glitch && nmk_chip->set_ioforce) { + u32 bit = BIT(offset); + + /* Prevent spurious wakeups */ + writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); + writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); + + nmk_chip->set_ioforce(true); + } + + __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); + + if (glitch && nmk_chip->set_ioforce) { + nmk_chip->set_ioforce(false); + + writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); + writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); + } +} + +static void +nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) +{ + u32 falling = nmk_chip->fimsc & BIT(offset); + u32 rising = nmk_chip->rimsc & BIT(offset); + int gpio = nmk_chip->chip.base + offset; + int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); + struct irq_data *d = irq_get_irq_data(irq); + + if (!rising && !falling) + return; + + if (!d || !irqd_irq_disabled(d)) + return; + + if (rising) { + nmk_chip->rimsc &= ~BIT(offset); + writel_relaxed(nmk_chip->rimsc, + nmk_chip->addr + NMK_GPIO_RIMSC); + } + + if (falling) { + nmk_chip->fimsc &= ~BIT(offset); + writel_relaxed(nmk_chip->fimsc, + nmk_chip->addr + NMK_GPIO_FIMSC); + } + + dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); +} + +static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) +{ + u32 val; + + val = readl(reg); + val = ((val & ~mask) | (value & mask)); + writel(val, reg); +} + +static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, + unsigned offset, unsigned alt_num) +{ + int i; + u16 reg; + u8 bit; + u8 alt_index; + const struct prcm_gpiocr_altcx_pin_desc *pin_desc; + const u16 *gpiocr_regs; + + if (!npct->prcm_base) + return; + + if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { + dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", + alt_num); + return; + } + + for (i = 0 ; i < npct->soc->npins_altcx ; i++) { + if (npct->soc->altcx_pins[i].pin == offset) + break; + } + if (i == npct->soc->npins_altcx) { + dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", + offset); + return; + } + + pin_desc = npct->soc->altcx_pins + i; + gpiocr_regs = npct->soc->prcm_gpiocr_registers; + + /* + * If alt_num is NULL, just clear current ALTCx selection + * to make sure we come back to a pure ALTC selection + */ + if (!alt_num) { + for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { + if (pin_desc->altcx[i].used == true) { + reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; + bit = pin_desc->altcx[i].control_bit; + if (readl(npct->prcm_base + reg) & BIT(bit)) { + nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); + dev_dbg(npct->dev, + "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", + offset, i+1); + } + } + } + return; + } + + alt_index = alt_num - 1; + if (pin_desc->altcx[alt_index].used == false) { + dev_warn(npct->dev, + "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", + offset, alt_num); + return; + } + + /* + * Check if any other ALTCx functions are activated on this pin + * and disable it first. + */ + for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { + if (i == alt_index) + continue; + if (pin_desc->altcx[i].used == true) { + reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; + bit = pin_desc->altcx[i].control_bit; + if (readl(npct->prcm_base + reg) & BIT(bit)) { + nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); + dev_dbg(npct->dev, + "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", + offset, i+1); + } + } + } + + reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; + bit = pin_desc->altcx[alt_index].control_bit; + dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", + offset, alt_index+1); + nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); +} + +/* + * Safe sequence used to switch IOs between GPIO and Alternate-C mode: + * - Save SLPM registers + * - Set SLPM=0 for the IOs you want to switch and others to 1 + * - Configure the GPIO registers for the IOs that are being switched + * - Set IOFORCE=1 + * - Modify the AFLSA/B registers for the IOs that are being switched + * - Set IOFORCE=0 + * - Restore SLPM registers + * - Any spurious wake up event during switch sequence to be ignored and + * cleared + */ +static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + unsigned int temp = slpm[i]; + + if (!chip) + break; + + clk_enable(chip->clk); + + slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); + writel(temp, chip->addr + NMK_GPIO_SLPC); + } +} + +static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + break; + + writel(slpm[i], chip->addr + NMK_GPIO_SLPC); + + clk_disable(chip->clk); + } +} + +static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) +{ + int i; + u16 reg; + u8 bit; + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + const struct prcm_gpiocr_altcx_pin_desc *pin_desc; + const u16 *gpiocr_regs; + + if (!npct->prcm_base) + return NMK_GPIO_ALT_C; + + for (i = 0; i < npct->soc->npins_altcx; i++) { + if (npct->soc->altcx_pins[i].pin == gpio) + break; + } + if (i == npct->soc->npins_altcx) + return NMK_GPIO_ALT_C; + + pin_desc = npct->soc->altcx_pins + i; + gpiocr_regs = npct->soc->prcm_gpiocr_registers; + for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { + if (pin_desc->altcx[i].used == true) { + reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; + bit = pin_desc->altcx[i].control_bit; + if (readl(npct->prcm_base + reg) & BIT(bit)) + return NMK_GPIO_ALT_C+i+1; + } + } + return NMK_GPIO_ALT_C; +} + +int nmk_gpio_get_mode(int gpio) +{ + struct nmk_gpio_chip *nmk_chip; + u32 afunc, bfunc, bit; + + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + if (!nmk_chip) + return -EINVAL; + + bit = 1 << (gpio % NMK_GPIO_PER_CHIP); + + clk_enable(nmk_chip->clk); + + afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; + bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; + + clk_disable(nmk_chip->clk); + + return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); +} +EXPORT_SYMBOL(nmk_gpio_get_mode); + + +/* IRQ functions */ +static inline int nmk_gpio_get_bitmask(int gpio) +{ + return 1 << (gpio % NMK_GPIO_PER_CHIP); +} + +static void nmk_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + + clk_enable(nmk_chip->clk); + writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); + clk_disable(nmk_chip->clk); +} + +enum nmk_gpio_irq_type { + NORMAL, + WAKE, +}; + +static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, + int gpio, enum nmk_gpio_irq_type which, + bool enable) +{ + u32 bitmask = nmk_gpio_get_bitmask(gpio); + u32 *rimscval; + u32 *fimscval; + u32 rimscreg; + u32 fimscreg; + + if (which == NORMAL) { + rimscreg = NMK_GPIO_RIMSC; + fimscreg = NMK_GPIO_FIMSC; + rimscval = &nmk_chip->rimsc; + fimscval = &nmk_chip->fimsc; + } else { + rimscreg = NMK_GPIO_RWIMSC; + fimscreg = NMK_GPIO_FWIMSC; + rimscval = &nmk_chip->rwimsc; + fimscval = &nmk_chip->fwimsc; + } + + /* we must individually set/clear the two edges */ + if (nmk_chip->edge_rising & bitmask) { + if (enable) + *rimscval |= bitmask; + else + *rimscval &= ~bitmask; + writel(*rimscval, nmk_chip->addr + rimscreg); + } + if (nmk_chip->edge_falling & bitmask) { + if (enable) + *fimscval |= bitmask; + else + *fimscval &= ~bitmask; + writel(*fimscval, nmk_chip->addr + fimscreg); + } +} + +static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, + int gpio, bool on) +{ + /* + * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is + * disabled, since setting SLPM to 1 increases power consumption, and + * wakeup is anyhow controlled by the RIMSC and FIMSC registers. + */ + if (nmk_chip->sleepmode && on) { + __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, + NMK_GPIO_SLPM_WAKEUP_ENABLE); + } + + __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); +} + +static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + u32 bitmask; + + nmk_chip = irq_data_get_irq_chip_data(d); + bitmask = nmk_gpio_get_bitmask(d->hwirq); + if (!nmk_chip) + return -EINVAL; + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); + spin_lock(&nmk_chip->lock); + + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); + + if (!(nmk_chip->real_wake & bitmask)) + __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); + + spin_unlock(&nmk_chip->lock); + spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} + +static void nmk_gpio_irq_mask(struct irq_data *d) +{ + nmk_gpio_irq_maskunmask(d, false); +} + +static void nmk_gpio_irq_unmask(struct irq_data *d) +{ + nmk_gpio_irq_maskunmask(d, true); +} + +static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + u32 bitmask; + + nmk_chip = irq_data_get_irq_chip_data(d); + if (!nmk_chip) + return -EINVAL; + bitmask = nmk_gpio_get_bitmask(d->hwirq); + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); + spin_lock(&nmk_chip->lock); + + if (irqd_irq_disabled(d)) + __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); + + if (on) + nmk_chip->real_wake |= bitmask; + else + nmk_chip->real_wake &= ~bitmask; + + spin_unlock(&nmk_chip->lock); + spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} + +static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + bool enabled = !irqd_irq_disabled(d); + bool wake = irqd_is_wakeup_set(d); + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + u32 bitmask; + + nmk_chip = irq_data_get_irq_chip_data(d); + bitmask = nmk_gpio_get_bitmask(d->hwirq); + if (!nmk_chip) + return -EINVAL; + if (type & IRQ_TYPE_LEVEL_HIGH) + return -EINVAL; + if (type & IRQ_TYPE_LEVEL_LOW) + return -EINVAL; + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_chip->lock, flags); + + if (enabled) + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); + + if (enabled || wake) + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); + + nmk_chip->edge_rising &= ~bitmask; + if (type & IRQ_TYPE_EDGE_RISING) + nmk_chip->edge_rising |= bitmask; + + nmk_chip->edge_falling &= ~bitmask; + if (type & IRQ_TYPE_EDGE_FALLING) + nmk_chip->edge_falling |= bitmask; + + if (enabled) + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); + + if (enabled || wake) + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); + + spin_unlock_irqrestore(&nmk_chip->lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} + +static unsigned int nmk_gpio_irq_startup(struct irq_data *d) +{ + struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); + + clk_enable(nmk_chip->clk); + nmk_gpio_irq_unmask(d); + return 0; +} + +static void nmk_gpio_irq_shutdown(struct irq_data *d) +{ + struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); + + nmk_gpio_irq_mask(d); + clk_disable(nmk_chip->clk); +} + +static struct irq_chip nmk_gpio_irq_chip = { + .name = "Nomadik-GPIO", + .irq_ack = nmk_gpio_irq_ack, + .irq_mask = nmk_gpio_irq_mask, + .irq_unmask = nmk_gpio_irq_unmask, + .irq_set_type = nmk_gpio_irq_set_type, + .irq_set_wake = nmk_gpio_irq_set_wake, + .irq_startup = nmk_gpio_irq_startup, + .irq_shutdown = nmk_gpio_irq_shutdown, + .flags = IRQCHIP_MASK_ON_SUSPEND, +}; + +static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, + u32 status) +{ + struct irq_chip *host_chip = irq_get_chip(irq); + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + + chained_irq_enter(host_chip, desc); + + while (status) { + int bit = __ffs(status); + + generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); + status &= ~BIT(bit); + } + + chained_irq_exit(host_chip, desc); +} + +static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + u32 status; + + clk_enable(nmk_chip->clk); + status = readl(nmk_chip->addr + NMK_GPIO_IS); + clk_disable(nmk_chip->clk); + + __nmk_gpio_irq_handler(irq, desc, status); +} + +static void nmk_gpio_latent_irq_handler(unsigned int irq, + struct irq_desc *desc) +{ + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + u32 status = nmk_chip->get_latent_status(nmk_chip->bank); + + __nmk_gpio_irq_handler(irq, desc, status); +} + +/* I/O Functions */ + +static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + /* + * Map back to global GPIO space and request muxing, the direction + * parameter does not matter for this controller. + */ + int gpio = chip->base + offset; + + return pinctrl_request_gpio(gpio); +} + +static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + pinctrl_free_gpio(gpio); +} + +static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + clk_enable(nmk_chip->clk); + + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); + + clk_disable(nmk_chip->clk); + + return 0; +} + +static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + u32 bit = 1 << offset; + int value; + + clk_enable(nmk_chip->clk); + + value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; + + clk_disable(nmk_chip->clk); + + return value; +} + +static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, + int val) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + clk_enable(nmk_chip->clk); + + __nmk_gpio_set_output(nmk_chip, offset, val); + + clk_disable(nmk_chip->clk); +} + +static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, + int val) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + clk_enable(nmk_chip->clk); + + __nmk_gpio_make_output(nmk_chip, offset, val); + + clk_disable(nmk_chip->clk); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS + +#include + +static void nmk_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, struct gpio_chip *chip, + unsigned offset, unsigned gpio) +{ + const char *label = gpiochip_is_requested(chip, offset); + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + int mode; + bool is_out; + bool pull; + u32 bit = 1 << offset; + const char *modes[] = { + [NMK_GPIO_ALT_GPIO] = "gpio", + [NMK_GPIO_ALT_A] = "altA", + [NMK_GPIO_ALT_B] = "altB", + [NMK_GPIO_ALT_C] = "altC", + [NMK_GPIO_ALT_C+1] = "altC1", + [NMK_GPIO_ALT_C+2] = "altC2", + [NMK_GPIO_ALT_C+3] = "altC3", + [NMK_GPIO_ALT_C+4] = "altC4", + }; + + clk_enable(nmk_chip->clk); + is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); + pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); + mode = nmk_gpio_get_mode(gpio); + if ((mode == NMK_GPIO_ALT_C) && pctldev) + mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); + + seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", + gpio, label ?: "(none)", + is_out ? "out" : "in ", + chip->get + ? (chip->get(chip, offset) ? "hi" : "lo") + : "? ", + (mode < 0) ? "unknown" : modes[mode], + pull ? "pull" : "none"); + + if (!is_out) { + int irq = gpio_to_irq(gpio); + struct irq_desc *desc = irq_to_desc(irq); + + /* This races with request_irq(), set_irq_type(), + * and set_irq_wake() ... but those are "rare". + */ + if (irq > 0 && desc && desc->action) { + char *trigger; + u32 bitmask = nmk_gpio_get_bitmask(gpio); + + if (nmk_chip->edge_rising & bitmask) + trigger = "edge-rising"; + else if (nmk_chip->edge_falling & bitmask) + trigger = "edge-falling"; + else + trigger = "edge-undefined"; + + seq_printf(s, " irq-%d %s%s", + irq, trigger, + irqd_is_wakeup_set(&desc->irq_data) + ? " wakeup" : ""); + } + } + clk_disable(nmk_chip->clk); +} + +static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned i; + unsigned gpio = chip->base; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_printf(s, "\n"); + } +} + +#else +static inline void nmk_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, unsigned gpio) +{ +} +#define nmk_gpio_dbg_show NULL +#endif + +/* This structure is replicated for each GPIO block allocated at probe time */ +static struct gpio_chip nmk_gpio_template = { + .request = nmk_gpio_request, + .free = nmk_gpio_free, + .direction_input = nmk_gpio_make_input, + .get = nmk_gpio_get_input, + .direction_output = nmk_gpio_make_output, + .set = nmk_gpio_set_output, + .dbg_show = nmk_gpio_dbg_show, + .can_sleep = false, +}; + +void nmk_gpio_clocks_enable(void) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + continue; + + clk_enable(chip->clk); + } +} + +void nmk_gpio_clocks_disable(void) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + continue; + + clk_disable(chip->clk); + } +} + +/* + * Called from the suspend/resume path to only keep the real wakeup interrupts + * (those that have had set_irq_wake() called on them) as wakeup interrupts, + * and not the rest of the interrupts which we needed to have as wakeups for + * cpuidle. + * + * PM ops are not used since this needs to be done at the end, after all the + * other drivers are done with their suspend callbacks. + */ +void nmk_gpio_wakeups_suspend(void) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + break; + + clk_enable(chip->clk); + + writel(chip->rwimsc & chip->real_wake, + chip->addr + NMK_GPIO_RWIMSC); + writel(chip->fwimsc & chip->real_wake, + chip->addr + NMK_GPIO_FWIMSC); + + clk_disable(chip->clk); + } +} + +void nmk_gpio_wakeups_resume(void) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + break; + + clk_enable(chip->clk); + + writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); + writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); + + clk_disable(chip->clk); + } +} + +/* + * Read the pull up/pull down status. + * A bit set in 'pull_up' means that pull up + * is selected if pull is enabled in PDIS register. + * Note: only pull up/down set via this driver can + * be detected due to HW limitations. + */ +void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) +{ + if (gpio_bank < NUM_BANKS) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; + + if (!chip) + return; + + *pull_up = chip->pull_up; + } +} + +static int nmk_gpio_probe(struct platform_device *dev) +{ + struct device_node *np = dev->dev.of_node; + struct nmk_gpio_chip *nmk_chip; + struct gpio_chip *chip; + struct resource *res; + struct clk *clk; + int latent_irq; + bool supports_sleepmode; + void __iomem *base; + int irq; + int ret; + + if (of_get_property(np, "st,supports-sleepmode", NULL)) + supports_sleepmode = true; + else + supports_sleepmode = false; + + if (of_property_read_u32(np, "gpio-bank", &dev->id)) { + dev_err(&dev->dev, "gpio-bank property not found\n"); + return -EINVAL; + } + + irq = platform_get_irq(dev, 0); + if (irq < 0) + return irq; + + /* It's OK for this IRQ not to be present */ + latent_irq = platform_get_irq(dev, 1); + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&dev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk = devm_clk_get(&dev->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clk_prepare(clk); + + nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); + if (!nmk_chip) + return -ENOMEM; + + /* + * The virt address in nmk_chip->addr is in the nomadik register space, + * so we can simply convert the resource address, without remapping + */ + nmk_chip->bank = dev->id; + nmk_chip->clk = clk; + nmk_chip->addr = base; + nmk_chip->chip = nmk_gpio_template; + nmk_chip->parent_irq = irq; + nmk_chip->latent_parent_irq = latent_irq; + nmk_chip->sleepmode = supports_sleepmode; + spin_lock_init(&nmk_chip->lock); + + chip = &nmk_chip->chip; + chip->base = dev->id * NMK_GPIO_PER_CHIP; + chip->ngpio = NMK_GPIO_PER_CHIP; + chip->label = dev_name(&dev->dev); + chip->dev = &dev->dev; + chip->owner = THIS_MODULE; + + clk_enable(nmk_chip->clk); + nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); + clk_disable(nmk_chip->clk); + chip->of_node = np; + + ret = gpiochip_add(&nmk_chip->chip); + if (ret) + return ret; + + BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); + + nmk_gpio_chips[nmk_chip->bank] = nmk_chip; + + platform_set_drvdata(dev, nmk_chip); + + /* + * Let the generic code handle this edge IRQ, the the chained + * handler will perform the actual work of handling the parent + * interrupt. + */ + ret = gpiochip_irqchip_add(&nmk_chip->chip, + &nmk_gpio_irq_chip, + 0, + handle_edge_irq, + IRQ_TYPE_EDGE_FALLING); + if (ret) { + dev_err(&dev->dev, "could not add irqchip\n"); + ret = gpiochip_remove(&nmk_chip->chip); + return -ENODEV; + } + /* Then register the chain on the parent IRQ */ + gpiochip_set_chained_irqchip(&nmk_chip->chip, + &nmk_gpio_irq_chip, + nmk_chip->parent_irq, + nmk_gpio_irq_handler); + if (nmk_chip->latent_parent_irq > 0) + gpiochip_set_chained_irqchip(&nmk_chip->chip, + &nmk_gpio_irq_chip, + nmk_chip->latent_parent_irq, + nmk_gpio_latent_irq_handler); + + dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); + + return 0; +} + +static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + return npct->soc->ngroups; +} + +static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + return npct->soc->groups[selector].name; +} + +static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + *pins = npct->soc->groups[selector].pins; + *num_pins = npct->soc->groups[selector].npins; + return 0; +} + +static struct pinctrl_gpio_range * +nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + int i; + + for (i = 0; i < npct->soc->gpio_num_ranges; i++) { + struct pinctrl_gpio_range *range; + + range = &npct->soc->gpio_ranges[i]; + if (offset >= range->pin_base && + offset <= (range->pin_base + range->npins - 1)) + return range; + } + return NULL; +} + +static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned offset) +{ + struct pinctrl_gpio_range *range; + struct gpio_chip *chip; + + range = nmk_match_gpio_range(pctldev, offset); + if (!range || !range->gc) { + seq_printf(s, "invalid pin offset"); + return; + } + chip = range->gc; + nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); +} + +static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + kfree(map); +} + +static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, unsigned reserve) +{ + unsigned old_num = *reserved_maps; + unsigned new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int nmk_dt_add_map_configs(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, const char *group, + unsigned long *configs, unsigned num_configs) +{ + unsigned long *dup_configs; + + if (*num_maps == *reserved_maps) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) + return -ENOMEM; + + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; + + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +#define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } +#define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ + .size = ARRAY_SIZE(y), } + +static const unsigned long nmk_pin_input_modes[] = { + PIN_INPUT_NOPULL, + PIN_INPUT_PULLUP, + PIN_INPUT_PULLDOWN, +}; + +static const unsigned long nmk_pin_output_modes[] = { + PIN_OUTPUT_LOW, + PIN_OUTPUT_HIGH, + PIN_DIR_OUTPUT, +}; + +static const unsigned long nmk_pin_sleep_modes[] = { + PIN_SLEEPMODE_DISABLED, + PIN_SLEEPMODE_ENABLED, +}; + +static const unsigned long nmk_pin_sleep_input_modes[] = { + PIN_SLPM_INPUT_NOPULL, + PIN_SLPM_INPUT_PULLUP, + PIN_SLPM_INPUT_PULLDOWN, + PIN_SLPM_DIR_INPUT, +}; + +static const unsigned long nmk_pin_sleep_output_modes[] = { + PIN_SLPM_OUTPUT_LOW, + PIN_SLPM_OUTPUT_HIGH, + PIN_SLPM_DIR_OUTPUT, +}; + +static const unsigned long nmk_pin_sleep_wakeup_modes[] = { + PIN_SLPM_WAKEUP_DISABLE, + PIN_SLPM_WAKEUP_ENABLE, +}; + +static const unsigned long nmk_pin_gpio_modes[] = { + PIN_GPIOMODE_DISABLED, + PIN_GPIOMODE_ENABLED, +}; + +static const unsigned long nmk_pin_sleep_pdis_modes[] = { + PIN_SLPM_PDIS_DISABLED, + PIN_SLPM_PDIS_ENABLED, +}; + +struct nmk_cfg_param { + const char *property; + unsigned long config; + const unsigned long *choice; + int size; +}; + +static const struct nmk_cfg_param nmk_cfg_params[] = { + NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), + NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), + NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), + NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), + NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), + NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), + NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), + NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), +}; + +static int nmk_dt_pin_config(int index, int val, unsigned long *config) +{ + int ret = 0; + + if (nmk_cfg_params[index].choice == NULL) + *config = nmk_cfg_params[index].config; + else { + /* test if out of range */ + if (val < nmk_cfg_params[index].size) { + *config = nmk_cfg_params[index].config | + nmk_cfg_params[index].choice[val]; + } + } + return ret; +} + +static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) +{ + int i, pin_number; + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) + for (i = 0; i < npct->soc->npins; i++) + if (npct->soc->pins[i].number == pin_number) + return npct->soc->pins[i].name; + return NULL; +} + +static bool nmk_pinctrl_dt_get_config(struct device_node *np, + unsigned long *configs) +{ + bool has_config = 0; + unsigned long cfg = 0; + int i, val, ret; + + for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { + ret = of_property_read_u32(np, + nmk_cfg_params[i].property, &val); + if (ret != -EINVAL) { + if (nmk_dt_pin_config(i, val, &cfg) == 0) { + *configs |= cfg; + has_config = 1; + } + } + } + + return has_config; +} + +static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + int ret; + const char *function = NULL; + unsigned long configs = 0; + bool has_config = 0; + unsigned reserve = 0; + struct property *prop; + const char *group, *gpio_name; + struct device_node *np_config; + + ret = of_property_read_string(np, "ste,function", &function); + if (ret >= 0) + reserve = 1; + + has_config = nmk_pinctrl_dt_get_config(np, &configs); + + np_config = of_parse_phandle(np, "ste,config", 0); + if (np_config) + has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); + + ret = of_property_count_strings(np, "ste,pins"); + if (ret < 0) + goto exit; + + if (has_config) + reserve++; + + reserve *= ret; + + ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "ste,pins", prop, group) { + if (function) { + ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, + group, function); + if (ret < 0) + goto exit; + } + if (has_config) { + gpio_name = nmk_find_pin_name(pctldev, group); + + ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, + gpio_name, &configs, 1); + if (ret < 0) + goto exit; + } + + } +exit: + return ret; +} + +static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + unsigned reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static const struct pinctrl_ops nmk_pinctrl_ops = { + .get_groups_count = nmk_get_groups_cnt, + .get_group_name = nmk_get_group_name, + .get_group_pins = nmk_get_group_pins, + .pin_dbg_show = nmk_pin_dbg_show, + .dt_node_to_map = nmk_pinctrl_dt_node_to_map, + .dt_free_map = nmk_pinctrl_dt_free_map, +}; + +static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + return npct->soc->nfunctions; +} + +static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + return npct->soc->functions[function].name; +} + +static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + *groups = npct->soc->functions[function].groups; + *num_groups = npct->soc->functions[function].ngroups; + + return 0; +} + +static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + const struct nmk_pingroup *g; + static unsigned int slpm[NUM_BANKS]; + unsigned long flags = 0; + bool glitch; + int ret = -EINVAL; + int i; + + g = &npct->soc->groups[group]; + + if (g->altsetting < 0) + return -EINVAL; + + dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); + + /* + * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, + * we may pass through an undesired state. In this case we take + * some extra care. + * + * Safe sequence used to switch IOs between GPIO and Alternate-C mode: + * - Save SLPM registers (since we have a shadow register in the + * nmk_chip we're using that as backup) + * - Set SLPM=0 for the IOs you want to switch and others to 1 + * - Configure the GPIO registers for the IOs that are being switched + * - Set IOFORCE=1 + * - Modify the AFLSA/B registers for the IOs that are being switched + * - Set IOFORCE=0 + * - Restore SLPM registers + * - Any spurious wake up event during switch sequence to be ignored + * and cleared + * + * We REALLY need to save ALL slpm registers, because the external + * IOFORCE will switch *all* ports to their sleepmode setting to as + * to avoid glitches. (Not just one port!) + */ + glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); + + if (glitch) { + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); + + /* Initially don't put any pins to sleep when switching */ + memset(slpm, 0xff, sizeof(slpm)); + + /* + * Then mask the pins that need to be sleeping now when we're + * switching to the ALT C function. + */ + for (i = 0; i < g->npins; i++) + slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); + nmk_gpio_glitch_slpm_init(slpm); + } + + for (i = 0; i < g->npins; i++) { + struct pinctrl_gpio_range *range; + struct nmk_gpio_chip *nmk_chip; + struct gpio_chip *chip; + unsigned bit; + + range = nmk_match_gpio_range(pctldev, g->pins[i]); + if (!range) { + dev_err(npct->dev, + "invalid pin offset %d in group %s at index %d\n", + g->pins[i], g->name, i); + goto out_glitch; + } + if (!range->gc) { + dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", + g->pins[i], g->name, i); + goto out_glitch; + } + chip = range->gc; + nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); + + clk_enable(nmk_chip->clk); + bit = g->pins[i] % NMK_GPIO_PER_CHIP; + /* + * If the pin is switching to altfunc, and there was an + * interrupt installed on it which has been lazy disabled, + * actually mask the interrupt to prevent spurious interrupts + * that would occur while the pin is under control of the + * peripheral. Only SKE does this. + */ + nmk_gpio_disable_lazy_irq(nmk_chip, bit); + + __nmk_gpio_set_mode_safe(nmk_chip, bit, + (g->altsetting & NMK_GPIO_ALT_C), glitch); + clk_disable(nmk_chip->clk); + + /* + * Call PRCM GPIOCR config function in case ALTC + * has been selected: + * - If selection is a ALTCx, some bits in PRCM GPIOCR registers + * must be set. + * - If selection is pure ALTC and previous selection was ALTCx, + * then some bits in PRCM GPIOCR registers must be cleared. + */ + if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) + nmk_prcm_altcx_set_mode(npct, g->pins[i], + g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); + } + + /* When all pins are successfully reconfigured we get here */ + ret = 0; + +out_glitch: + if (glitch) { + nmk_gpio_glitch_slpm_restore(slpm); + spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); + } + + return ret; +} + +static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + struct nmk_gpio_chip *nmk_chip; + struct gpio_chip *chip; + unsigned bit; + + if (!range) { + dev_err(npct->dev, "invalid range\n"); + return -EINVAL; + } + if (!range->gc) { + dev_err(npct->dev, "missing GPIO chip in range\n"); + return -EINVAL; + } + chip = range->gc; + nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + + dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); + + clk_enable(nmk_chip->clk); + bit = offset % NMK_GPIO_PER_CHIP; + /* There is no glitch when converting any pin to GPIO */ + __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); + clk_disable(nmk_chip->clk); + + return 0; +} + +static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); + /* Set the pin to some default state, GPIO is usually default */ +} + +static const struct pinmux_ops nmk_pinmux_ops = { + .get_functions_count = nmk_pmx_get_funcs_cnt, + .get_function_name = nmk_pmx_get_func_name, + .get_function_groups = nmk_pmx_get_func_groups, + .enable = nmk_pmx_enable, + .gpio_request_enable = nmk_gpio_request_enable, + .gpio_disable_free = nmk_gpio_disable_free, +}; + +static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + /* Not implemented */ + return -EINVAL; +} + +static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + static const char *pullnames[] = { + [NMK_GPIO_PULL_NONE] = "none", + [NMK_GPIO_PULL_UP] = "up", + [NMK_GPIO_PULL_DOWN] = "down", + [3] /* illegal */ = "??" + }; + static const char *slpmnames[] = { + [NMK_GPIO_SLPM_INPUT] = "input/wakeup", + [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", + }; + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + struct nmk_gpio_chip *nmk_chip; + struct pinctrl_gpio_range *range; + struct gpio_chip *chip; + unsigned bit; + pin_cfg_t cfg; + int pull, slpm, output, val, i; + bool lowemi, gpiomode, sleep; + + range = nmk_match_gpio_range(pctldev, pin); + if (!range) { + dev_err(npct->dev, "invalid pin offset %d\n", pin); + return -EINVAL; + } + if (!range->gc) { + dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", + pin); + return -EINVAL; + } + chip = range->gc; + nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + + for (i = 0; i < num_configs; i++) { + /* + * The pin config contains pin number and altfunction fields, + * here we just ignore that part. It's being handled by the + * framework and pinmux callback respectively. + */ + cfg = (pin_cfg_t) configs[i]; + pull = PIN_PULL(cfg); + slpm = PIN_SLPM(cfg); + output = PIN_DIR(cfg); + val = PIN_VAL(cfg); + lowemi = PIN_LOWEMI(cfg); + gpiomode = PIN_GPIOMODE(cfg); + sleep = PIN_SLEEPMODE(cfg); + + if (sleep) { + int slpm_pull = PIN_SLPM_PULL(cfg); + int slpm_output = PIN_SLPM_DIR(cfg); + int slpm_val = PIN_SLPM_VAL(cfg); + + /* All pins go into GPIO mode at sleep */ + gpiomode = true; + + /* + * The SLPM_* values are normal values + 1 to allow zero + * to mean "same as normal". + */ + if (slpm_pull) + pull = slpm_pull - 1; + if (slpm_output) + output = slpm_output - 1; + if (slpm_val) + val = slpm_val - 1; + + dev_dbg(nmk_chip->chip.dev, + "pin %d: sleep pull %s, dir %s, val %s\n", + pin, + slpm_pull ? pullnames[pull] : "same", + slpm_output ? (output ? "output" : "input") + : "same", + slpm_val ? (val ? "high" : "low") : "same"); + } + + dev_dbg(nmk_chip->chip.dev, + "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", + pin, cfg, pullnames[pull], slpmnames[slpm], + output ? "output " : "input", + output ? (val ? "high" : "low") : "", + lowemi ? "on" : "off"); + + clk_enable(nmk_chip->clk); + bit = pin % NMK_GPIO_PER_CHIP; + if (gpiomode) + /* No glitch when going to GPIO mode */ + __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); + if (output) + __nmk_gpio_make_output(nmk_chip, bit, val); + else { + __nmk_gpio_make_input(nmk_chip, bit); + __nmk_gpio_set_pull(nmk_chip, bit, pull); + } + /* TODO: isn't this only applicable on output pins? */ + __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); + + __nmk_gpio_set_slpm(nmk_chip, bit, slpm); + clk_disable(nmk_chip->clk); + } /* for each config */ + + return 0; +} + +static const struct pinconf_ops nmk_pinconf_ops = { + .pin_config_get = nmk_pin_config_get, + .pin_config_set = nmk_pin_config_set, +}; + +static struct pinctrl_desc nmk_pinctrl_desc = { + .name = "pinctrl-nomadik", + .pctlops = &nmk_pinctrl_ops, + .pmxops = &nmk_pinmux_ops, + .confops = &nmk_pinconf_ops, + .owner = THIS_MODULE, +}; + +static const struct of_device_id nmk_pinctrl_match[] = { + { + .compatible = "stericsson,stn8815-pinctrl", + .data = (void *)PINCTRL_NMK_STN8815, + }, + { + .compatible = "stericsson,db8500-pinctrl", + .data = (void *)PINCTRL_NMK_DB8500, + }, + { + .compatible = "stericsson,db8540-pinctrl", + .data = (void *)PINCTRL_NMK_DB8540, + }, + {}, +}; + +#ifdef CONFIG_PM_SLEEP +static int nmk_pinctrl_suspend(struct device *dev) +{ + struct nmk_pinctrl *npct; + + npct = dev_get_drvdata(dev); + if (!npct) + return -EINVAL; + + return pinctrl_force_sleep(npct->pctl); +} + +static int nmk_pinctrl_resume(struct device *dev) +{ + struct nmk_pinctrl *npct; + + npct = dev_get_drvdata(dev); + if (!npct) + return -EINVAL; + + return pinctrl_force_default(npct->pctl); +} +#endif + +static int nmk_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct device_node *np = pdev->dev.of_node; + struct device_node *prcm_np; + struct nmk_pinctrl *npct; + unsigned int version = 0; + int i; + + npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); + if (!npct) + return -ENOMEM; + + match = of_match_device(nmk_pinctrl_match, &pdev->dev); + if (!match) + return -ENODEV; + version = (unsigned int) match->data; + + /* Poke in other ASIC variants here */ + if (version == PINCTRL_NMK_STN8815) + nmk_pinctrl_stn8815_init(&npct->soc); + if (version == PINCTRL_NMK_DB8500) + nmk_pinctrl_db8500_init(&npct->soc); + if (version == PINCTRL_NMK_DB8540) + nmk_pinctrl_db8540_init(&npct->soc); + + prcm_np = of_parse_phandle(np, "prcm", 0); + if (prcm_np) + npct->prcm_base = of_iomap(prcm_np, 0); + if (!npct->prcm_base) { + if (version == PINCTRL_NMK_STN8815) { + dev_info(&pdev->dev, + "No PRCM base, " + "assuming no ALT-Cx control is available\n"); + } else { + dev_err(&pdev->dev, "missing PRCM base address\n"); + return -EINVAL; + } + } + + /* + * We need all the GPIO drivers to probe FIRST, or we will not be able + * to obtain references to the struct gpio_chip * for them, and we + * need this to proceed. + */ + for (i = 0; i < npct->soc->gpio_num_ranges; i++) { + if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { + dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); + return -EPROBE_DEFER; + } + npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; + } + + nmk_pinctrl_desc.pins = npct->soc->pins; + nmk_pinctrl_desc.npins = npct->soc->npins; + npct->dev = &pdev->dev; + + npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); + if (!npct->pctl) { + dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); + return -EINVAL; + } + + /* We will handle a range of GPIO pins */ + for (i = 0; i < npct->soc->gpio_num_ranges; i++) + pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); + + platform_set_drvdata(pdev, npct); + dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); + + return 0; +} + +static const struct of_device_id nmk_gpio_match[] = { + { .compatible = "st,nomadik-gpio", }, + {} +}; + +static struct platform_driver nmk_gpio_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "gpio", + .of_match_table = nmk_gpio_match, + }, + .probe = nmk_gpio_probe, +}; + +static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, + nmk_pinctrl_suspend, + nmk_pinctrl_resume); + +static struct platform_driver nmk_pinctrl_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "pinctrl-nomadik", + .of_match_table = nmk_pinctrl_match, + .pm = &nmk_pinctrl_pm_ops, + }, + .probe = nmk_pinctrl_probe, +}; + +static int __init nmk_gpio_init(void) +{ + int ret; + + ret = platform_driver_register(&nmk_gpio_driver); + if (ret) + return ret; + return platform_driver_register(&nmk_pinctrl_driver); +} + +core_initcall(nmk_gpio_init); + +MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); +MODULE_DESCRIPTION("Nomadik GPIO Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.h b/drivers/pinctrl/nomadik/pinctrl-nomadik.h new file mode 100644 index 000000000000..d8215f1e70c7 --- /dev/null +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.h @@ -0,0 +1,192 @@ +#ifndef PINCTRL_PINCTRL_NOMADIK_H +#define PINCTRL_PINCTRL_NOMADIK_H + +/* Package definitions */ +#define PINCTRL_NMK_STN8815 0 +#define PINCTRL_NMK_DB8500 1 +#define PINCTRL_NMK_DB8540 2 + +/* Alternate functions: function C is set in hw by setting both A and B */ +#define NMK_GPIO_ALT_GPIO 0 +#define NMK_GPIO_ALT_A 1 +#define NMK_GPIO_ALT_B 2 +#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) + +#define NMK_GPIO_ALT_CX_SHIFT 2 +#define NMK_GPIO_ALT_C1 ((1< for ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include "pinctrl-abx500.h" - -/* All the pins that can be used for GPIO and some other functions */ -#define ABX500_GPIO(offset) (offset) - -#define AB8500_PIN_T10 ABX500_GPIO(1) -#define AB8500_PIN_T9 ABX500_GPIO(2) -#define AB8500_PIN_U9 ABX500_GPIO(3) -#define AB8500_PIN_W2 ABX500_GPIO(4) -/* hole */ -#define AB8500_PIN_Y18 ABX500_GPIO(6) -#define AB8500_PIN_AA20 ABX500_GPIO(7) -#define AB8500_PIN_W18 ABX500_GPIO(8) -#define AB8500_PIN_AA19 ABX500_GPIO(9) -#define AB8500_PIN_U17 ABX500_GPIO(10) -#define AB8500_PIN_AA18 ABX500_GPIO(11) -#define AB8500_PIN_U16 ABX500_GPIO(12) -#define AB8500_PIN_W17 ABX500_GPIO(13) -#define AB8500_PIN_F14 ABX500_GPIO(14) -#define AB8500_PIN_B17 ABX500_GPIO(15) -#define AB8500_PIN_F15 ABX500_GPIO(16) -#define AB8500_PIN_P5 ABX500_GPIO(17) -#define AB8500_PIN_R5 ABX500_GPIO(18) -#define AB8500_PIN_U5 ABX500_GPIO(19) -#define AB8500_PIN_T5 ABX500_GPIO(20) -#define AB8500_PIN_H19 ABX500_GPIO(21) -#define AB8500_PIN_G20 ABX500_GPIO(22) -#define AB8500_PIN_G19 ABX500_GPIO(23) -#define AB8500_PIN_T14 ABX500_GPIO(24) -#define AB8500_PIN_R16 ABX500_GPIO(25) -#define AB8500_PIN_M16 ABX500_GPIO(26) -#define AB8500_PIN_J6 ABX500_GPIO(27) -#define AB8500_PIN_K6 ABX500_GPIO(28) -#define AB8500_PIN_G6 ABX500_GPIO(29) -#define AB8500_PIN_H6 ABX500_GPIO(30) -#define AB8500_PIN_F5 ABX500_GPIO(31) -#define AB8500_PIN_G5 ABX500_GPIO(32) -/* hole */ -#define AB8500_PIN_R17 ABX500_GPIO(34) -#define AB8500_PIN_W15 ABX500_GPIO(35) -#define AB8500_PIN_A17 ABX500_GPIO(36) -#define AB8500_PIN_E15 ABX500_GPIO(37) -#define AB8500_PIN_C17 ABX500_GPIO(38) -#define AB8500_PIN_E16 ABX500_GPIO(39) -#define AB8500_PIN_T19 ABX500_GPIO(40) -#define AB8500_PIN_U19 ABX500_GPIO(41) -#define AB8500_PIN_U2 ABX500_GPIO(42) - -/* indicates the highest GPIO number */ -#define AB8500_GPIO_MAX_NUMBER 42 - -/* - * The names of the pins are denoted by GPIO number and ball name, even - * though they can be used for other things than GPIO, this is the first - * column in the table of the data sheet and often used on schematics and - * such. - */ -static const struct pinctrl_pin_desc ab8500_pins[] = { - PINCTRL_PIN(AB8500_PIN_T10, "GPIO1_T10"), - PINCTRL_PIN(AB8500_PIN_T9, "GPIO2_T9"), - PINCTRL_PIN(AB8500_PIN_U9, "GPIO3_U9"), - PINCTRL_PIN(AB8500_PIN_W2, "GPIO4_W2"), - /* hole */ - PINCTRL_PIN(AB8500_PIN_Y18, "GPIO6_Y18"), - PINCTRL_PIN(AB8500_PIN_AA20, "GPIO7_AA20"), - PINCTRL_PIN(AB8500_PIN_W18, "GPIO8_W18"), - PINCTRL_PIN(AB8500_PIN_AA19, "GPIO9_AA19"), - PINCTRL_PIN(AB8500_PIN_U17, "GPIO10_U17"), - PINCTRL_PIN(AB8500_PIN_AA18, "GPIO11_AA18"), - PINCTRL_PIN(AB8500_PIN_U16, "GPIO12_U16"), - PINCTRL_PIN(AB8500_PIN_W17, "GPIO13_W17"), - PINCTRL_PIN(AB8500_PIN_F14, "GPIO14_F14"), - PINCTRL_PIN(AB8500_PIN_B17, "GPIO15_B17"), - PINCTRL_PIN(AB8500_PIN_F15, "GPIO16_F15"), - PINCTRL_PIN(AB8500_PIN_P5, "GPIO17_P5"), - PINCTRL_PIN(AB8500_PIN_R5, "GPIO18_R5"), - PINCTRL_PIN(AB8500_PIN_U5, "GPIO19_U5"), - PINCTRL_PIN(AB8500_PIN_T5, "GPIO20_T5"), - PINCTRL_PIN(AB8500_PIN_H19, "GPIO21_H19"), - PINCTRL_PIN(AB8500_PIN_G20, "GPIO22_G20"), - PINCTRL_PIN(AB8500_PIN_G19, "GPIO23_G19"), - PINCTRL_PIN(AB8500_PIN_T14, "GPIO24_T14"), - PINCTRL_PIN(AB8500_PIN_R16, "GPIO25_R16"), - PINCTRL_PIN(AB8500_PIN_M16, "GPIO26_M16"), - PINCTRL_PIN(AB8500_PIN_J6, "GPIO27_J6"), - PINCTRL_PIN(AB8500_PIN_K6, "GPIO28_K6"), - PINCTRL_PIN(AB8500_PIN_G6, "GPIO29_G6"), - PINCTRL_PIN(AB8500_PIN_H6, "GPIO30_H6"), - PINCTRL_PIN(AB8500_PIN_F5, "GPIO31_F5"), - PINCTRL_PIN(AB8500_PIN_G5, "GPIO32_G5"), - /* hole */ - PINCTRL_PIN(AB8500_PIN_R17, "GPIO34_R17"), - PINCTRL_PIN(AB8500_PIN_W15, "GPIO35_W15"), - PINCTRL_PIN(AB8500_PIN_A17, "GPIO36_A17"), - PINCTRL_PIN(AB8500_PIN_E15, "GPIO37_E15"), - PINCTRL_PIN(AB8500_PIN_C17, "GPIO38_C17"), - PINCTRL_PIN(AB8500_PIN_E16, "GPIO39_E16"), - PINCTRL_PIN(AB8500_PIN_T19, "GPIO40_T19"), - PINCTRL_PIN(AB8500_PIN_U19, "GPIO41_U19"), - PINCTRL_PIN(AB8500_PIN_U2, "GPIO42_U2"), -}; - -/* - * Maps local GPIO offsets to local pin numbers - */ -static const struct abx500_pinrange ab8500_pinranges[] = { - ABX500_PINRANGE(1, 4, ABX500_ALT_A), - ABX500_PINRANGE(6, 4, ABX500_ALT_A), - ABX500_PINRANGE(10, 4, ABX500_DEFAULT), - ABX500_PINRANGE(14, 12, ABX500_ALT_A), - ABX500_PINRANGE(26, 1, ABX500_DEFAULT), - ABX500_PINRANGE(27, 6, ABX500_ALT_A), - ABX500_PINRANGE(34, 1, ABX500_ALT_A), - ABX500_PINRANGE(35, 1, ABX500_DEFAULT), - ABX500_PINRANGE(36, 7, ABX500_ALT_A), -}; - -/* - * Read the pin group names like this: - * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function - * - * The groups are arranged as sets per altfunction column, so we can - * mux in one group at a time by selecting the same altfunction for them - * all. When functions require pins on different altfunctions, you need - * to combine several groups. - */ - -/* default column */ -static const unsigned sysclkreq2_d_1_pins[] = { AB8500_PIN_T10 }; -static const unsigned sysclkreq3_d_1_pins[] = { AB8500_PIN_T9 }; -static const unsigned sysclkreq4_d_1_pins[] = { AB8500_PIN_U9 }; -static const unsigned sysclkreq6_d_1_pins[] = { AB8500_PIN_W2 }; -static const unsigned ycbcr0123_d_1_pins[] = { AB8500_PIN_Y18, AB8500_PIN_AA20, - AB8500_PIN_W18, AB8500_PIN_AA19}; -static const unsigned gpio10_d_1_pins[] = { AB8500_PIN_U17 }; -static const unsigned gpio11_d_1_pins[] = { AB8500_PIN_AA18 }; -static const unsigned gpio12_d_1_pins[] = { AB8500_PIN_U16 }; -static const unsigned gpio13_d_1_pins[] = { AB8500_PIN_W17 }; -static const unsigned pwmout1_d_1_pins[] = { AB8500_PIN_F14 }; -static const unsigned pwmout2_d_1_pins[] = { AB8500_PIN_B17 }; -static const unsigned pwmout3_d_1_pins[] = { AB8500_PIN_F15 }; - -/* audio data interface 1*/ -static const unsigned adi1_d_1_pins[] = { AB8500_PIN_P5, AB8500_PIN_R5, - AB8500_PIN_U5, AB8500_PIN_T5 }; -/* USBUICC */ -static const unsigned usbuicc_d_1_pins[] = { AB8500_PIN_H19, AB8500_PIN_G20, - AB8500_PIN_G19 }; -static const unsigned sysclkreq7_d_1_pins[] = { AB8500_PIN_T14 }; -static const unsigned sysclkreq8_d_1_pins[] = { AB8500_PIN_R16 }; -static const unsigned gpio26_d_1_pins[] = { AB8500_PIN_M16 }; -/* Digital microphone 1 and 2 */ -static const unsigned dmic12_d_1_pins[] = { AB8500_PIN_J6, AB8500_PIN_K6 }; -/* Digital microphone 3 and 4 */ -static const unsigned dmic34_d_1_pins[] = { AB8500_PIN_G6, AB8500_PIN_H6 }; -/* Digital microphone 5 and 6 */ -static const unsigned dmic56_d_1_pins[] = { AB8500_PIN_F5, AB8500_PIN_G5 }; -static const unsigned extcpena_d_1_pins[] = { AB8500_PIN_R17 }; -static const unsigned gpio35_d_1_pins[] = { AB8500_PIN_W15 }; -/* APE SPI */ -static const unsigned apespi_d_1_pins[] = { AB8500_PIN_A17, AB8500_PIN_E15, - AB8500_PIN_C17, AB8500_PIN_E16}; -/* modem SDA/SCL */ -static const unsigned modsclsda_d_1_pins[] = { AB8500_PIN_T19, AB8500_PIN_U19 }; -static const unsigned sysclkreq5_d_1_pins[] = { AB8500_PIN_U2 }; - -/* Altfunction A column */ -static const unsigned gpio1_a_1_pins[] = { AB8500_PIN_T10 }; -static const unsigned gpio2_a_1_pins[] = { AB8500_PIN_T9 }; -static const unsigned gpio3_a_1_pins[] = { AB8500_PIN_U9 }; -static const unsigned gpio4_a_1_pins[] = { AB8500_PIN_W2 }; -static const unsigned gpio6_a_1_pins[] = { AB8500_PIN_Y18 }; -static const unsigned gpio7_a_1_pins[] = { AB8500_PIN_AA20 }; -static const unsigned gpio8_a_1_pins[] = { AB8500_PIN_W18 }; -static const unsigned gpio9_a_1_pins[] = { AB8500_PIN_AA19 }; -/* YCbCr4 YCbCr5 YCbCr6 YCbCr7*/ -static const unsigned ycbcr4567_a_1_pins[] = { AB8500_PIN_U17, AB8500_PIN_AA18, - AB8500_PIN_U16, AB8500_PIN_W17}; -static const unsigned gpio14_a_1_pins[] = { AB8500_PIN_F14 }; -static const unsigned gpio15_a_1_pins[] = { AB8500_PIN_B17 }; -static const unsigned gpio16_a_1_pins[] = { AB8500_PIN_F15 }; -static const unsigned gpio17_a_1_pins[] = { AB8500_PIN_P5 }; -static const unsigned gpio18_a_1_pins[] = { AB8500_PIN_R5 }; -static const unsigned gpio19_a_1_pins[] = { AB8500_PIN_U5 }; -static const unsigned gpio20_a_1_pins[] = { AB8500_PIN_T5 }; -static const unsigned gpio21_a_1_pins[] = { AB8500_PIN_H19 }; -static const unsigned gpio22_a_1_pins[] = { AB8500_PIN_G20 }; -static const unsigned gpio23_a_1_pins[] = { AB8500_PIN_G19 }; -static const unsigned gpio24_a_1_pins[] = { AB8500_PIN_T14 }; -static const unsigned gpio25_a_1_pins[] = { AB8500_PIN_R16 }; -static const unsigned gpio27_a_1_pins[] = { AB8500_PIN_J6 }; -static const unsigned gpio28_a_1_pins[] = { AB8500_PIN_K6 }; -static const unsigned gpio29_a_1_pins[] = { AB8500_PIN_G6 }; -static const unsigned gpio30_a_1_pins[] = { AB8500_PIN_H6 }; -static const unsigned gpio31_a_1_pins[] = { AB8500_PIN_F5 }; -static const unsigned gpio32_a_1_pins[] = { AB8500_PIN_G5 }; -static const unsigned gpio34_a_1_pins[] = { AB8500_PIN_R17 }; -static const unsigned gpio36_a_1_pins[] = { AB8500_PIN_A17 }; -static const unsigned gpio37_a_1_pins[] = { AB8500_PIN_E15 }; -static const unsigned gpio38_a_1_pins[] = { AB8500_PIN_C17 }; -static const unsigned gpio39_a_1_pins[] = { AB8500_PIN_E16 }; -static const unsigned gpio40_a_1_pins[] = { AB8500_PIN_T19 }; -static const unsigned gpio41_a_1_pins[] = { AB8500_PIN_U19 }; -static const unsigned gpio42_a_1_pins[] = { AB8500_PIN_U2 }; - -/* Altfunction B colum */ -static const unsigned hiqclkena_b_1_pins[] = { AB8500_PIN_U17 }; -static const unsigned usbuiccpd_b_1_pins[] = { AB8500_PIN_AA18 }; -static const unsigned i2ctrig1_b_1_pins[] = { AB8500_PIN_U16 }; -static const unsigned i2ctrig2_b_1_pins[] = { AB8500_PIN_W17 }; - -/* Altfunction C column */ -static const unsigned usbvdat_c_1_pins[] = { AB8500_PIN_W17 }; - - -#define AB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ - .npins = ARRAY_SIZE(a##_pins), .altsetting = b } - -static const struct abx500_pingroup ab8500_groups[] = { - /* default column */ - AB8500_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(ycbcr0123_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(gpio12_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(adi1_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(gpio26_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(gpio35_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(apespi_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT), - AB8500_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT), - /* Altfunction A column */ - AB8500_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio4_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio6_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio7_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio8_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio9_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(ycbcr4567_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio15_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio16_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio21_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio22_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio23_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio24_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio25_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio27_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio28_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio29_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio30_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio31_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio32_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio34_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio36_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio37_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio38_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio39_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), - AB8500_PIN_GROUP(gpio42_a_1, ABX500_ALT_A), - /* Altfunction B column */ - AB8500_PIN_GROUP(hiqclkena_b_1, ABX500_ALT_B), - AB8500_PIN_GROUP(usbuiccpd_b_1, ABX500_ALT_B), - AB8500_PIN_GROUP(i2ctrig1_b_1, ABX500_ALT_B), - AB8500_PIN_GROUP(i2ctrig2_b_1, ABX500_ALT_B), - /* Altfunction C column */ - AB8500_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C), -}; - -/* We use this macro to define the groups applicable to a function */ -#define AB8500_FUNC_GROUPS(a, b...) \ -static const char * const a##_groups[] = { b }; - -AB8500_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", - "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1", - "sysclkreq7_d_1", "sysclkreq8_d_1"); -AB8500_FUNC_GROUPS(ycbcr, "ycbcr0123_d_1", "ycbcr4567_a_1"); -AB8500_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1", - "gpio6_a_1", "gpio7_a_1", "gpio8_a_1", "gpio9_a_1", - "gpio10_d_1", "gpio11_d_1", "gpio12_d_1", "gpio13_d_1", - "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", - "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio21_a_1", - "gpio22_a_1", "gpio23_a_1", "gpio24_a_1", "gpio25_a_1", - "gpio26_d_1", "gpio27_a_1", "gpio28_a_1", "gpio29_a_1", - "gpio30_a_1", "gpio31_a_1", "gpio32_a_1", "gpio34_a_1", - "gpio35_d_1", "gpio36_a_1", "gpio37_a_1", "gpio38_a_1", - "gpio39_a_1", "gpio40_a_1", "gpio41_a_1", "gpio42_a_1"); -AB8500_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1"); -AB8500_FUNC_GROUPS(adi1, "adi1_d_1"); -AB8500_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_b_1"); -AB8500_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1"); -AB8500_FUNC_GROUPS(extcpena, "extcpena_d_1"); -AB8500_FUNC_GROUPS(apespi, "apespi_d_1"); -AB8500_FUNC_GROUPS(modsclsda, "modsclsda_d_1"); -AB8500_FUNC_GROUPS(hiqclkena, "hiqclkena_b_1"); -AB8500_FUNC_GROUPS(i2ctrig, "i2ctrig1_b_1", "i2ctrig2_b_1"); -AB8500_FUNC_GROUPS(usbvdat, "usbvdat_c_1"); - -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -static const struct abx500_function ab8500_functions[] = { - FUNCTION(sysclkreq), - FUNCTION(ycbcr), - FUNCTION(gpio), - FUNCTION(pwmout), - FUNCTION(adi1), - FUNCTION(usbuicc), - FUNCTION(dmic), - FUNCTION(extcpena), - FUNCTION(apespi), - FUNCTION(modsclsda), - FUNCTION(hiqclkena), - FUNCTION(i2ctrig), - FUNCTION(usbvdat), -}; - -/* - * this table translates what's is in the AB8500 specification regarding the - * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). - * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, - * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), - * - * example : - * - * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 0, 1 ,2), - * means that pin AB8500_PIN_W17 (pin 13) supports 4 mux (default/ALT_A, - * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to - * select the mux. ALTA, ALTB and ALTC val indicates values to write in - * ALTERNATFUNC register. We need to specifies these values as SOC - * designers didn't apply the same logic on how to select mux in the - * ABx500 family. - * - * As this pins supports at least ALT_B mux, default mux is - * selected by writing 1 in GPIOSEL bit : - * - * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3 - * default | 1 | 0 | 0 - * alt_A | 0 | 0 | 0 - * alt_B | 0 | 0 | 1 - * alt_C | 0 | 1 | 0 - * - * ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED), - * means that pin AB8500_PIN_W18 (pin 8) supports 2 mux, so only GPIOSEL - * register is used to select the mux. As this pins doesn't support at - * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit : - * - * | GPIOSEL bit=7 | alternatfunc bit2= | alternatfunc bit1= - * default | 0 | 0 | 0 - * alt_A | 1 | 0 | 0 - */ - -static struct -alternate_functions ab8500_alternate_functions[AB8500_GPIO_MAX_NUMBER + 1] = { - ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ - ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ - ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/ - /* bit 4 reserved */ - ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */ - ALTERNATE_FUNCTIONS(6, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO6, altA controlled by bit 5*/ - ALTERNATE_FUNCTIONS(7, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO7, altA controlled by bit 6*/ - ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO8, altA controlled by bit 7*/ - - ALTERNATE_FUNCTIONS(9, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO9, altA controlled by bit 0*/ - ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 0, 1, 0), /* GPIO10, altA and altB controlled by bit 0 */ - ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 1, 0), /* GPIO11, altA and altB controlled by bit 1 */ - ALTERNATE_FUNCTIONS(12, 3, 2, UNUSED, 0, 1, 0), /* GPIO12, altA and altB controlled by bit 2 */ - ALTERNATE_FUNCTIONS(13, 4, 3, 4, 0, 1, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ - ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */ - /* - * pins 17 to 20 are special case, only bit 0 is used to select - * alternate function for these 4 pins. - * bits 1 to 3 are reserved - */ - ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */ - - ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */ - /* pin 26 special case, no alternate function, bit 1 reserved */ - ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO26 */ - ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */ - - ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */ - ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */ - /* pin 35 special case, no alternate function, bit 2 reserved */ - ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO35 */ - ALTERNATE_FUNCTIONS(36, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO36, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(37, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO37, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(38, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO38, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(39, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO39, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */ - - ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */ -}; - -/* - * Only some GPIOs are interrupt capable, and they are - * organized in discontiguous clusters: - * - * GPIO6 to GPIO13 - * GPIO24 and GPIO25 - * GPIO36 to GPIO41 - */ -static struct abx500_gpio_irq_cluster ab8500_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(6, 13, AB8500_INT_GPIO6R), - GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R), - GPIO_IRQ_CLUSTER(36, 41, AB8500_INT_GPIO36R), -}; - -static struct abx500_pinctrl_soc_data ab8500_soc = { - .gpio_ranges = ab8500_pinranges, - .gpio_num_ranges = ARRAY_SIZE(ab8500_pinranges), - .pins = ab8500_pins, - .npins = ARRAY_SIZE(ab8500_pins), - .functions = ab8500_functions, - .nfunctions = ARRAY_SIZE(ab8500_functions), - .groups = ab8500_groups, - .ngroups = ARRAY_SIZE(ab8500_groups), - .alternate_functions = ab8500_alternate_functions, - .gpio_irq_cluster = ab8500_gpio_irq_cluster, - .ngpio_irq_cluster = ARRAY_SIZE(ab8500_gpio_irq_cluster), - .irq_gpio_rising_offset = AB8500_INT_GPIO6R, - .irq_gpio_falling_offset = AB8500_INT_GPIO6F, - .irq_gpio_factor = 1, -}; - -void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc) -{ - *soc = &ab8500_soc; -} diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/pinctrl-ab8505.c deleted file mode 100644 index bf0ef4ac376f..000000000000 --- a/drivers/pinctrl/pinctrl-ab8505.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2012 - * - * Author: Patrice Chotard for ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include "pinctrl-abx500.h" - -/* All the pins that can be used for GPIO and some other functions */ -#define ABX500_GPIO(offset) (offset) - -#define AB8505_PIN_N4 ABX500_GPIO(1) -#define AB8505_PIN_R5 ABX500_GPIO(2) -#define AB8505_PIN_P5 ABX500_GPIO(3) -/* hole */ -#define AB8505_PIN_B16 ABX500_GPIO(10) -#define AB8505_PIN_B17 ABX500_GPIO(11) -/* hole */ -#define AB8505_PIN_D17 ABX500_GPIO(13) -#define AB8505_PIN_C16 ABX500_GPIO(14) -/* hole */ -#define AB8505_PIN_P2 ABX500_GPIO(17) -#define AB8505_PIN_N3 ABX500_GPIO(18) -#define AB8505_PIN_T1 ABX500_GPIO(19) -#define AB8505_PIN_P3 ABX500_GPIO(20) -/* hole */ -#define AB8505_PIN_H14 ABX500_GPIO(34) -/* hole */ -#define AB8505_PIN_J15 ABX500_GPIO(40) -#define AB8505_PIN_J14 ABX500_GPIO(41) -/* hole */ -#define AB8505_PIN_L4 ABX500_GPIO(50) -/* hole */ -#define AB8505_PIN_D16 ABX500_GPIO(52) -#define AB8505_PIN_D15 ABX500_GPIO(53) - -/* indicates the higher GPIO number */ -#define AB8505_GPIO_MAX_NUMBER 53 - -/* - * The names of the pins are denoted by GPIO number and ball name, even - * though they can be used for other things than GPIO, this is the first - * column in the table of the data sheet and often used on schematics and - * such. - */ -static const struct pinctrl_pin_desc ab8505_pins[] = { - PINCTRL_PIN(AB8505_PIN_N4, "GPIO1_N4"), - PINCTRL_PIN(AB8505_PIN_R5, "GPIO2_R5"), - PINCTRL_PIN(AB8505_PIN_P5, "GPIO3_P5"), -/* hole */ - PINCTRL_PIN(AB8505_PIN_B16, "GPIO10_B16"), - PINCTRL_PIN(AB8505_PIN_B17, "GPIO11_B17"), -/* hole */ - PINCTRL_PIN(AB8505_PIN_D17, "GPIO13_D17"), - PINCTRL_PIN(AB8505_PIN_C16, "GPIO14_C16"), -/* hole */ - PINCTRL_PIN(AB8505_PIN_P2, "GPIO17_P2"), - PINCTRL_PIN(AB8505_PIN_N3, "GPIO18_N3"), - PINCTRL_PIN(AB8505_PIN_T1, "GPIO19_T1"), - PINCTRL_PIN(AB8505_PIN_P3, "GPIO20_P3"), -/* hole */ - PINCTRL_PIN(AB8505_PIN_H14, "GPIO34_H14"), -/* hole */ - PINCTRL_PIN(AB8505_PIN_J15, "GPIO40_J15"), - PINCTRL_PIN(AB8505_PIN_J14, "GPIO41_J14"), -/* hole */ - PINCTRL_PIN(AB8505_PIN_L4, "GPIO50_L4"), -/* hole */ - PINCTRL_PIN(AB8505_PIN_D16, "GPIO52_D16"), - PINCTRL_PIN(AB8505_PIN_D15, "GPIO53_D15"), -}; - -/* - * Maps local GPIO offsets to local pin numbers - */ -static const struct abx500_pinrange ab8505_pinranges[] = { - ABX500_PINRANGE(1, 3, ABX500_ALT_A), - ABX500_PINRANGE(10, 2, ABX500_DEFAULT), - ABX500_PINRANGE(13, 1, ABX500_DEFAULT), - ABX500_PINRANGE(14, 1, ABX500_ALT_A), - ABX500_PINRANGE(17, 4, ABX500_ALT_A), - ABX500_PINRANGE(34, 1, ABX500_ALT_A), - ABX500_PINRANGE(40, 2, ABX500_ALT_A), - ABX500_PINRANGE(50, 1, ABX500_DEFAULT), - ABX500_PINRANGE(52, 2, ABX500_ALT_A), -}; - -/* - * Read the pin group names like this: - * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function - * - * The groups are arranged as sets per altfunction column, so we can - * mux in one group at a time by selecting the same altfunction for them - * all. When functions require pins on different altfunctions, you need - * to combine several groups. - */ - -/* default column */ -static const unsigned sysclkreq2_d_1_pins[] = { AB8505_PIN_N4 }; -static const unsigned sysclkreq3_d_1_pins[] = { AB8505_PIN_R5 }; -static const unsigned sysclkreq4_d_1_pins[] = { AB8505_PIN_P5 }; -static const unsigned gpio10_d_1_pins[] = { AB8505_PIN_B16 }; -static const unsigned gpio11_d_1_pins[] = { AB8505_PIN_B17 }; -static const unsigned gpio13_d_1_pins[] = { AB8505_PIN_D17 }; -static const unsigned pwmout1_d_1_pins[] = { AB8505_PIN_C16 }; -/* audio data interface 2*/ -static const unsigned adi2_d_1_pins[] = { AB8505_PIN_P2, AB8505_PIN_N3, - AB8505_PIN_T1, AB8505_PIN_P3 }; -static const unsigned extcpena_d_1_pins[] = { AB8505_PIN_H14 }; -/* modem SDA/SCL */ -static const unsigned modsclsda_d_1_pins[] = { AB8505_PIN_J15, AB8505_PIN_J14 }; -static const unsigned gpio50_d_1_pins[] = { AB8505_PIN_L4 }; -static const unsigned resethw_d_1_pins[] = { AB8505_PIN_D16 }; -static const unsigned service_d_1_pins[] = { AB8505_PIN_D15 }; - -/* Altfunction A column */ -static const unsigned gpio1_a_1_pins[] = { AB8505_PIN_N4 }; -static const unsigned gpio2_a_1_pins[] = { AB8505_PIN_R5 }; -static const unsigned gpio3_a_1_pins[] = { AB8505_PIN_P5 }; -static const unsigned hiqclkena_a_1_pins[] = { AB8505_PIN_B16 }; -static const unsigned pdmclk_a_1_pins[] = { AB8505_PIN_B17 }; -static const unsigned uarttxdata_a_1_pins[] = { AB8505_PIN_D17 }; -static const unsigned gpio14_a_1_pins[] = { AB8505_PIN_C16 }; -static const unsigned gpio17_a_1_pins[] = { AB8505_PIN_P2 }; -static const unsigned gpio18_a_1_pins[] = { AB8505_PIN_N3 }; -static const unsigned gpio19_a_1_pins[] = { AB8505_PIN_T1 }; -static const unsigned gpio20_a_1_pins[] = { AB8505_PIN_P3 }; -static const unsigned gpio34_a_1_pins[] = { AB8505_PIN_H14 }; -static const unsigned gpio40_a_1_pins[] = { AB8505_PIN_J15 }; -static const unsigned gpio41_a_1_pins[] = { AB8505_PIN_J14 }; -static const unsigned uartrxdata_a_1_pins[] = { AB8505_PIN_J14 }; -static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 }; -static const unsigned gpio52_a_1_pins[] = { AB8505_PIN_D16 }; -static const unsigned gpio53_a_1_pins[] = { AB8505_PIN_D15 }; - -/* Altfunction B colum */ -static const unsigned pdmdata_b_1_pins[] = { AB8505_PIN_B16 }; -static const unsigned extvibrapwm1_b_1_pins[] = { AB8505_PIN_D17 }; -static const unsigned extvibrapwm2_b_1_pins[] = { AB8505_PIN_L4 }; - -/* Altfunction C column */ -static const unsigned usbvdat_c_1_pins[] = { AB8505_PIN_D17 }; - -#define AB8505_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ - .npins = ARRAY_SIZE(a##_pins), .altsetting = b } - -static const struct abx500_pingroup ab8505_groups[] = { - AB8505_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(adi2_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(resethw_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(service_d_1, ABX500_DEFAULT), - AB8505_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(uarttxdata_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio34_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(uartrxdata_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), - AB8505_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B), - AB8505_PIN_GROUP(extvibrapwm1_b_1, ABX500_ALT_B), - AB8505_PIN_GROUP(extvibrapwm2_b_1, ABX500_ALT_B), - AB8505_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C), -}; - -/* We use this macro to define the groups applicable to a function */ -#define AB8505_FUNC_GROUPS(a, b...) \ -static const char * const a##_groups[] = { b }; - -AB8505_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", - "sysclkreq4_d_1"); -AB8505_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", - "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1", - "gpio17_a_1", "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", - "gpio34_a_1", "gpio40_a_1", "gpio41_a_1", "gpio50_d_1", - "gpio52_a_1", "gpio53_a_1"); -AB8505_FUNC_GROUPS(pwmout, "pwmout1_d_1"); -AB8505_FUNC_GROUPS(adi2, "adi2_d_1"); -AB8505_FUNC_GROUPS(extcpena, "extcpena_d_1"); -AB8505_FUNC_GROUPS(modsclsda, "modsclsda_d_1"); -AB8505_FUNC_GROUPS(resethw, "resethw_d_1"); -AB8505_FUNC_GROUPS(service, "service_d_1"); -AB8505_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1"); -AB8505_FUNC_GROUPS(pdm, "pdmclk_a_1", "pdmdata_b_1"); -AB8505_FUNC_GROUPS(uartdata, "uarttxdata_a_1", "uartrxdata_a_1"); -AB8505_FUNC_GROUPS(extvibra, "extvibrapwm1_b_1", "extvibrapwm2_b_1"); -AB8505_FUNC_GROUPS(usbvdat, "usbvdat_c_1"); - -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -static const struct abx500_function ab8505_functions[] = { - FUNCTION(sysclkreq), - FUNCTION(gpio), - FUNCTION(pwmout), - FUNCTION(adi2), - FUNCTION(extcpena), - FUNCTION(modsclsda), - FUNCTION(resethw), - FUNCTION(service), - FUNCTION(hiqclkena), - FUNCTION(pdm), - FUNCTION(uartdata), - FUNCTION(extvibra), - FUNCTION(extvibra), - FUNCTION(usbvdat), -}; - -/* - * this table translates what's is in the AB8505 specification regarding the - * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). - * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, - * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), - * - * example : - * - * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), - * means that pin AB8505_PIN_D18 (pin 13) supports 4 mux (default/ALT_A, - * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to - * select the mux. ALTA, ALTB and ALTC val indicates values to write in - * ALTERNATFUNC register. We need to specifies these values as SOC - * designers didn't apply the same logic on how to select mux in the - * ABx500 family. - * - * As this pins supports at least ALT_B mux, default mux is - * selected by writing 1 in GPIOSEL bit : - * - * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3 - * default | 1 | 0 | 0 - * alt_A | 0 | 0 | 1 - * alt_B | 0 | 0 | 0 - * alt_C | 0 | 1 | 0 - * - * ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED), - * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL - * register is used to select the mux. As this pins doesn't support at - * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit : - * - * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1= - * default | 0 | 0 | 0 - * alt_A | 1 | 0 | 0 - */ - -static struct -alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1] = { - ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ - ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ - ALTERNATE_FUNCTIONS(4, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO4, bit 3 reserved */ - ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5, bit 4 reserved */ - ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6, bit 5 reserved */ - ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7, bit 6 reserved */ - ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8, bit 7 reserved */ - - ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */ - ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */ - ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */ - ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ - ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */ - ALTERNATE_FUNCTIONS(16, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 7 reserved */ - /* - * pins 17 to 20 are special case, only bit 0 is used to select - * alternate function for these 4 pins. - * bits 1 to 3 are reserved - */ - ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21, bit 4 reserved */ - ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22, bit 5 reserved */ - ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23, bit 6 reserved */ - ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24, bit 7 reserved */ - - ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25, bit 0 reserved */ - ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26, bit 1 reserved */ - ALTERNATE_FUNCTIONS(27, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO27, bit 2 reserved */ - ALTERNATE_FUNCTIONS(28, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO28, bit 3 reserved */ - ALTERNATE_FUNCTIONS(29, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO29, bit 4 reserved */ - ALTERNATE_FUNCTIONS(30, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO30, bit 5 reserved */ - ALTERNATE_FUNCTIONS(31, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO31, bit 6 reserved */ - ALTERNATE_FUNCTIONS(32, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO32, bit 7 reserved */ - - ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33, bit 0 reserved */ - ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35, bit 2 reserved */ - ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36, bit 2 reserved */ - ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37, bit 2 reserved */ - ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38, bit 2 reserved */ - ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39, bit 2 reserved */ - ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7*/ - - ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(42, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO42, bit 1 reserved */ - ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43, bit 2 reserved */ - ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44, bit 3 reserved */ - ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45, bit 4 reserved */ - ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46, bit 5 reserved */ - ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47, bit 6 reserved */ - ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48, bit 7 reserved */ - - ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */ - ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(51, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */ - ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */ -}; - -/* - * For AB8505 Only some GPIOs are interrupt capable, and they are - * organized in discontiguous clusters: - * - * GPIO10 to GPIO11 - * GPIO13 - * GPIO40 and GPIO41 - * GPIO50 - * GPIO52 to GPIO53 - */ -static struct abx500_gpio_irq_cluster ab8505_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(10, 11, AB8500_INT_GPIO10R), - GPIO_IRQ_CLUSTER(13, 13, AB8500_INT_GPIO13R), - GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R), - GPIO_IRQ_CLUSTER(50, 50, AB9540_INT_GPIO50R), - GPIO_IRQ_CLUSTER(52, 53, AB9540_INT_GPIO52R), -}; - -static struct abx500_pinctrl_soc_data ab8505_soc = { - .gpio_ranges = ab8505_pinranges, - .gpio_num_ranges = ARRAY_SIZE(ab8505_pinranges), - .pins = ab8505_pins, - .npins = ARRAY_SIZE(ab8505_pins), - .functions = ab8505_functions, - .nfunctions = ARRAY_SIZE(ab8505_functions), - .groups = ab8505_groups, - .ngroups = ARRAY_SIZE(ab8505_groups), - .alternate_functions = ab8505_alternate_functions, - .gpio_irq_cluster = ab8505_gpio_irq_cluster, - .ngpio_irq_cluster = ARRAY_SIZE(ab8505_gpio_irq_cluster), - .irq_gpio_rising_offset = AB8500_INT_GPIO6R, - .irq_gpio_falling_offset = AB8500_INT_GPIO6F, - .irq_gpio_factor = 1, -}; - -void -abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc) -{ - *soc = &ab8505_soc; -} diff --git a/drivers/pinctrl/pinctrl-ab8540.c b/drivers/pinctrl/pinctrl-ab8540.c deleted file mode 100644 index 9867535d49c1..000000000000 --- a/drivers/pinctrl/pinctrl-ab8540.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2012 - * - * Author: Patrice Chotard for ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include "pinctrl-abx500.h" - -/* All the pins that can be used for GPIO and some other functions */ -#define ABX500_GPIO(offset) (offset) - -#define AB8540_PIN_J16 ABX500_GPIO(1) -#define AB8540_PIN_D17 ABX500_GPIO(2) -#define AB8540_PIN_C12 ABX500_GPIO(3) -#define AB8540_PIN_G12 ABX500_GPIO(4) -/* hole */ -#define AB8540_PIN_D16 ABX500_GPIO(14) -#define AB8540_PIN_F15 ABX500_GPIO(15) -#define AB8540_PIN_J8 ABX500_GPIO(16) -#define AB8540_PIN_K16 ABX500_GPIO(17) -#define AB8540_PIN_G15 ABX500_GPIO(18) -#define AB8540_PIN_F17 ABX500_GPIO(19) -#define AB8540_PIN_E17 ABX500_GPIO(20) -/* hole */ -#define AB8540_PIN_AA16 ABX500_GPIO(27) -#define AB8540_PIN_W18 ABX500_GPIO(28) -#define AB8540_PIN_Y15 ABX500_GPIO(29) -#define AB8540_PIN_W16 ABX500_GPIO(30) -#define AB8540_PIN_V15 ABX500_GPIO(31) -#define AB8540_PIN_W17 ABX500_GPIO(32) -/* hole */ -#define AB8540_PIN_D12 ABX500_GPIO(42) -#define AB8540_PIN_P4 ABX500_GPIO(43) -#define AB8540_PIN_AB1 ABX500_GPIO(44) -#define AB8540_PIN_K7 ABX500_GPIO(45) -#define AB8540_PIN_L7 ABX500_GPIO(46) -#define AB8540_PIN_G10 ABX500_GPIO(47) -#define AB8540_PIN_K12 ABX500_GPIO(48) -/* hole */ -#define AB8540_PIN_N8 ABX500_GPIO(51) -#define AB8540_PIN_P12 ABX500_GPIO(52) -#define AB8540_PIN_K8 ABX500_GPIO(53) -#define AB8540_PIN_J11 ABX500_GPIO(54) -#define AB8540_PIN_AC2 ABX500_GPIO(55) -#define AB8540_PIN_AB2 ABX500_GPIO(56) - -/* indicates the highest GPIO number */ -#define AB8540_GPIO_MAX_NUMBER 56 - -/* - * The names of the pins are denoted by GPIO number and ball name, even - * though they can be used for other things than GPIO, this is the first - * column in the table of the data sheet and often used on schematics and - * such. - */ -static const struct pinctrl_pin_desc ab8540_pins[] = { - PINCTRL_PIN(AB8540_PIN_J16, "GPIO1_J16"), - PINCTRL_PIN(AB8540_PIN_D17, "GPIO2_D17"), - PINCTRL_PIN(AB8540_PIN_C12, "GPIO3_C12"), - PINCTRL_PIN(AB8540_PIN_G12, "GPIO4_G12"), - /* hole */ - PINCTRL_PIN(AB8540_PIN_D16, "GPIO14_D16"), - PINCTRL_PIN(AB8540_PIN_F15, "GPIO15_F15"), - PINCTRL_PIN(AB8540_PIN_J8, "GPIO16_J8"), - PINCTRL_PIN(AB8540_PIN_K16, "GPIO17_K16"), - PINCTRL_PIN(AB8540_PIN_G15, "GPIO18_G15"), - PINCTRL_PIN(AB8540_PIN_F17, "GPIO19_F17"), - PINCTRL_PIN(AB8540_PIN_E17, "GPIO20_E17"), - /* hole */ - PINCTRL_PIN(AB8540_PIN_AA16, "GPIO27_AA16"), - PINCTRL_PIN(AB8540_PIN_W18, "GPIO28_W18"), - PINCTRL_PIN(AB8540_PIN_Y15, "GPIO29_Y15"), - PINCTRL_PIN(AB8540_PIN_W16, "GPIO30_W16"), - PINCTRL_PIN(AB8540_PIN_V15, "GPIO31_V15"), - PINCTRL_PIN(AB8540_PIN_W17, "GPIO32_W17"), - /* hole */ - PINCTRL_PIN(AB8540_PIN_D12, "GPIO42_D12"), - PINCTRL_PIN(AB8540_PIN_P4, "GPIO43_P4"), - PINCTRL_PIN(AB8540_PIN_AB1, "GPIO44_AB1"), - PINCTRL_PIN(AB8540_PIN_K7, "GPIO45_K7"), - PINCTRL_PIN(AB8540_PIN_L7, "GPIO46_L7"), - PINCTRL_PIN(AB8540_PIN_G10, "GPIO47_G10"), - PINCTRL_PIN(AB8540_PIN_K12, "GPIO48_K12"), - /* hole */ - PINCTRL_PIN(AB8540_PIN_N8, "GPIO51_N8"), - PINCTRL_PIN(AB8540_PIN_P12, "GPIO52_P12"), - PINCTRL_PIN(AB8540_PIN_K8, "GPIO53_K8"), - PINCTRL_PIN(AB8540_PIN_J11, "GPIO54_J11"), - PINCTRL_PIN(AB8540_PIN_AC2, "GPIO55_AC2"), - PINCTRL_PIN(AB8540_PIN_AB2, "GPIO56_AB2"), -}; - -/* - * Maps local GPIO offsets to local pin numbers - */ -static const struct abx500_pinrange ab8540_pinranges[] = { - ABX500_PINRANGE(1, 4, ABX500_ALT_A), - ABX500_PINRANGE(14, 7, ABX500_ALT_A), - ABX500_PINRANGE(27, 6, ABX500_ALT_A), - ABX500_PINRANGE(42, 7, ABX500_ALT_A), - ABX500_PINRANGE(51, 6, ABX500_ALT_A), -}; - -/* - * Read the pin group names like this: - * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function - * - * The groups are arranged as sets per altfunction column, so we can - * mux in one group at a time by selecting the same altfunction for them - * all. When functions require pins on different altfunctions, you need - * to combine several groups. - */ - -/* default column */ -static const unsigned sysclkreq2_d_1_pins[] = { AB8540_PIN_J16 }; -static const unsigned sysclkreq3_d_1_pins[] = { AB8540_PIN_D17 }; -static const unsigned sysclkreq4_d_1_pins[] = { AB8540_PIN_C12 }; -static const unsigned sysclkreq6_d_1_pins[] = { AB8540_PIN_G12 }; -static const unsigned pwmout1_d_1_pins[] = { AB8540_PIN_D16 }; -static const unsigned pwmout2_d_1_pins[] = { AB8540_PIN_F15 }; -static const unsigned pwmout3_d_1_pins[] = { AB8540_PIN_J8 }; - -/* audio data interface 1*/ -static const unsigned adi1_d_1_pins[] = { AB8540_PIN_K16, AB8540_PIN_G15, - AB8540_PIN_F17, AB8540_PIN_E17 }; -/* Digital microphone 1 and 2 */ -static const unsigned dmic12_d_1_pins[] = { AB8540_PIN_AA16, AB8540_PIN_W18 }; -/* Digital microphone 3 and 4 */ -static const unsigned dmic34_d_1_pins[] = { AB8540_PIN_Y15, AB8540_PIN_W16 }; -/* Digital microphone 5 and 6 */ -static const unsigned dmic56_d_1_pins[] = { AB8540_PIN_V15, AB8540_PIN_W17 }; -static const unsigned sysclkreq5_d_1_pins[] = { AB8540_PIN_D12 }; -static const unsigned batremn_d_1_pins[] = { AB8540_PIN_P4 }; -static const unsigned service_d_1_pins[] = { AB8540_PIN_AB1 }; -static const unsigned pwrctrl0_d_1_pins[] = { AB8540_PIN_K7 }; -static const unsigned pwrctrl1_d_1_pins[] = { AB8540_PIN_L7 }; -static const unsigned pwmextvibra1_d_1_pins[] = { AB8540_PIN_G10 }; -static const unsigned pwmextvibra2_d_1_pins[] = { AB8540_PIN_K12 }; -static const unsigned gpio1_vbat_d_1_pins[] = { AB8540_PIN_N8 }; -static const unsigned gpio2_vbat_d_1_pins[] = { AB8540_PIN_P12 }; -static const unsigned gpio3_vbat_d_1_pins[] = { AB8540_PIN_K8 }; -static const unsigned gpio4_vbat_d_1_pins[] = { AB8540_PIN_J11 }; -static const unsigned pdmclkdat_d_1_pins[] = { AB8540_PIN_AC2, AB8540_PIN_AB2 }; - -/* Altfunction A column */ -static const unsigned gpio1_a_1_pins[] = { AB8540_PIN_J16 }; -static const unsigned gpio2_a_1_pins[] = { AB8540_PIN_D17 }; -static const unsigned gpio3_a_1_pins[] = { AB8540_PIN_C12 }; -static const unsigned gpio4_a_1_pins[] = { AB8540_PIN_G12 }; -static const unsigned gpio14_a_1_pins[] = { AB8540_PIN_D16 }; -static const unsigned gpio15_a_1_pins[] = { AB8540_PIN_F15 }; -static const unsigned gpio16_a_1_pins[] = { AB8540_PIN_J8 }; -static const unsigned gpio17_a_1_pins[] = { AB8540_PIN_K16 }; -static const unsigned gpio18_a_1_pins[] = { AB8540_PIN_G15 }; -static const unsigned gpio19_a_1_pins[] = { AB8540_PIN_F17 }; -static const unsigned gpio20_a_1_pins[] = { AB8540_PIN_E17 }; -static const unsigned gpio27_a_1_pins[] = { AB8540_PIN_AA16 }; -static const unsigned gpio28_a_1_pins[] = { AB8540_PIN_W18 }; -static const unsigned gpio29_a_1_pins[] = { AB8540_PIN_Y15 }; -static const unsigned gpio30_a_1_pins[] = { AB8540_PIN_W16 }; -static const unsigned gpio31_a_1_pins[] = { AB8540_PIN_V15 }; -static const unsigned gpio32_a_1_pins[] = { AB8540_PIN_W17 }; -static const unsigned gpio42_a_1_pins[] = { AB8540_PIN_D12 }; -static const unsigned gpio43_a_1_pins[] = { AB8540_PIN_P4 }; -static const unsigned gpio44_a_1_pins[] = { AB8540_PIN_AB1 }; -static const unsigned gpio45_a_1_pins[] = { AB8540_PIN_K7 }; -static const unsigned gpio46_a_1_pins[] = { AB8540_PIN_L7 }; -static const unsigned gpio47_a_1_pins[] = { AB8540_PIN_G10 }; -static const unsigned gpio48_a_1_pins[] = { AB8540_PIN_K12 }; -static const unsigned gpio51_a_1_pins[] = { AB8540_PIN_N8 }; -static const unsigned gpio52_a_1_pins[] = { AB8540_PIN_P12 }; -static const unsigned gpio53_a_1_pins[] = { AB8540_PIN_K8 }; -static const unsigned gpio54_a_1_pins[] = { AB8540_PIN_J11 }; -static const unsigned gpio55_a_1_pins[] = { AB8540_PIN_AC2 }; -static const unsigned gpio56_a_1_pins[] = { AB8540_PIN_AB2 }; - -#define AB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ - .npins = ARRAY_SIZE(a##_pins), .altsetting = b } - -static const struct abx500_pingroup ab8540_groups[] = { - /* default column */ - AB8540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(service_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(pwrctrl0_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(pwrctrl1_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(pwmextvibra1_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(pwmextvibra2_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(gpio1_vbat_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(gpio2_vbat_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(gpio3_vbat_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(gpio4_vbat_d_1, ABX500_DEFAULT), - AB8540_PIN_GROUP(pdmclkdat_d_1, ABX500_DEFAULT), - /* Altfunction A column */ - AB8540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio43_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio44_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio45_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio46_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio47_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio48_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio54_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio55_a_1, ABX500_ALT_A), - AB8540_PIN_GROUP(gpio56_a_1, ABX500_ALT_A), -}; - -/* We use this macro to define the groups applicable to a function */ -#define AB8540_FUNC_GROUPS(a, b...) \ -static const char * const a##_groups[] = { b }; - -AB8540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", - "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1"); -AB8540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1", - "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", - "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio27_a_1", - "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1", - "gpio32_a_1", "gpio42_a_1", "gpio43_a_1", "gpio44_a_1", - "gpio45_a_1", "gpio46_a_1", "gpio47_a_1", "gpio48_a_1", - "gpio51_a_1", "gpio52_a_1", "gpio53_a_1", "gpio54_a_1", - "gpio55_a_1", "gpio56_a_1"); -AB8540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1"); -AB8540_FUNC_GROUPS(adi1, "adi1_d_1"); -AB8540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1"); -AB8540_FUNC_GROUPS(batremn, "batremn_d_1"); -AB8540_FUNC_GROUPS(service, "service_d_1"); -AB8540_FUNC_GROUPS(pwrctrl, "pwrctrl0_d_1", "pwrctrl1_d_1"); -AB8540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_d_1", "pwmextvibra2_d_1"); -AB8540_FUNC_GROUPS(gpio_vbat, "gpio1_vbat_d_1", "gpio2_vbat_d_1", - "gpio3_vbat_d_1", "gpio4_vbat_d_1"); -AB8540_FUNC_GROUPS(pdm, "pdmclkdat_d_1"); - -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -static const struct abx500_function ab8540_functions[] = { - FUNCTION(sysclkreq), - FUNCTION(gpio), - FUNCTION(pwmout), - FUNCTION(adi1), - FUNCTION(dmic), - FUNCTION(batremn), - FUNCTION(service), - FUNCTION(pwrctrl), - FUNCTION(pwmextvibra), - FUNCTION(gpio_vbat), - FUNCTION(pdm), -}; - -/* - * this table translates what's is in the AB8540 specification regarding the - * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). - * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, - * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), - * AB8540 only supports DEFAULT and ALTA functions, so ALTERNATFUNC - * registers is not used - * - */ - -static struct -alternate_functions ab8540_alternate_functions[AB8540_GPIO_MAX_NUMBER + 1] = { - /* GPIOSEL1 - bit 4-7 reserved */ - ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ - ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ - ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/ - ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */ - ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */ - ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */ - ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */ - /* GPIOSEL2 - bit 0-4 reserved */ - ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */ - ALTERNATE_FUNCTIONS(10, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO10 */ - ALTERNATE_FUNCTIONS(11, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO11 */ - ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */ - ALTERNATE_FUNCTIONS(13, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO13 */ - ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */ - /* GPIOSEL3 - bit 4-7 reserved */ - ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(18, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(19, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(20, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21 */ - ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22 */ - ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23 */ - ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24 */ - /* GPIOSEL4 - bit 0-1 reserved */ - ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25 */ - ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */ - ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */ - /* GPIOSEL5 - bit 0-7 reserved */ - ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */ - ALTERNATE_FUNCTIONS(34, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO34 */ - ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */ - ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */ - ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */ - ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */ - ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */ - ALTERNATE_FUNCTIONS(40, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO40 */ - /* GPIOSEL6 - bit 0 reserved */ - ALTERNATE_FUNCTIONS(41, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO41 */ - ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(43, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO43, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(44, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO44, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(45, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO45, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(46, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO46, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(47, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO47, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(48, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO48, altA controlled by bit 7 */ - /* GPIOSEL7 - bit 0-1 reserved */ - ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */ - ALTERNATE_FUNCTIONS(50, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO50 */ - ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(55, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO55, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(56, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO56, altA controlled by bit 7 */ -}; - -static struct pullud ab8540_pullud = { - .first_pin = 51, /* GPIO1_VBAT */ - .last_pin = 54, /* GPIO4_VBAT */ -}; - -/* - * For AB8540 Only some GPIOs are interrupt capable: - * GPIO43 to GPIO44 - * GPIO51 to GPIO54 - */ -static struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(43, 43, AB8540_INT_GPIO43F), - GPIO_IRQ_CLUSTER(44, 44, AB8540_INT_GPIO44F), - GPIO_IRQ_CLUSTER(51, 54, AB9540_INT_GPIO51R), -}; - -static struct abx500_pinctrl_soc_data ab8540_soc = { - .gpio_ranges = ab8540_pinranges, - .gpio_num_ranges = ARRAY_SIZE(ab8540_pinranges), - .pins = ab8540_pins, - .npins = ARRAY_SIZE(ab8540_pins), - .functions = ab8540_functions, - .nfunctions = ARRAY_SIZE(ab8540_functions), - .groups = ab8540_groups, - .ngroups = ARRAY_SIZE(ab8540_groups), - .alternate_functions = ab8540_alternate_functions, - .pullud = &ab8540_pullud, - .gpio_irq_cluster = ab8540_gpio_irq_cluster, - .ngpio_irq_cluster = ARRAY_SIZE(ab8540_gpio_irq_cluster), - .irq_gpio_rising_offset = AB8540_INT_GPIO43R, - .irq_gpio_falling_offset = AB8540_INT_GPIO43F, - .irq_gpio_factor = 2, -}; - -void -abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc) -{ - *soc = &ab8540_soc; -} diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/pinctrl-ab9540.c deleted file mode 100644 index 1a281ca95dac..000000000000 --- a/drivers/pinctrl/pinctrl-ab9540.c +++ /dev/null @@ -1,486 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2012 - * - * Author: Patrice Chotard for ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include "pinctrl-abx500.h" - -/* All the pins that can be used for GPIO and some other functions */ -#define ABX500_GPIO(offset) (offset) - -#define AB9540_PIN_R4 ABX500_GPIO(1) -#define AB9540_PIN_V3 ABX500_GPIO(2) -#define AB9540_PIN_T4 ABX500_GPIO(3) -#define AB9540_PIN_T5 ABX500_GPIO(4) -/* hole */ -#define AB9540_PIN_B18 ABX500_GPIO(10) -#define AB9540_PIN_C18 ABX500_GPIO(11) -/* hole */ -#define AB9540_PIN_D18 ABX500_GPIO(13) -#define AB9540_PIN_B19 ABX500_GPIO(14) -#define AB9540_PIN_C19 ABX500_GPIO(15) -#define AB9540_PIN_D19 ABX500_GPIO(16) -#define AB9540_PIN_R3 ABX500_GPIO(17) -#define AB9540_PIN_T2 ABX500_GPIO(18) -#define AB9540_PIN_U2 ABX500_GPIO(19) -#define AB9540_PIN_V2 ABX500_GPIO(20) -#define AB9540_PIN_N17 ABX500_GPIO(21) -#define AB9540_PIN_N16 ABX500_GPIO(22) -#define AB9540_PIN_M19 ABX500_GPIO(23) -#define AB9540_PIN_T3 ABX500_GPIO(24) -#define AB9540_PIN_W2 ABX500_GPIO(25) -/* hole */ -#define AB9540_PIN_H4 ABX500_GPIO(27) -#define AB9540_PIN_F1 ABX500_GPIO(28) -#define AB9540_PIN_F4 ABX500_GPIO(29) -#define AB9540_PIN_F2 ABX500_GPIO(30) -#define AB9540_PIN_E4 ABX500_GPIO(31) -#define AB9540_PIN_F3 ABX500_GPIO(32) -/* hole */ -#define AB9540_PIN_J13 ABX500_GPIO(34) -/* hole */ -#define AB9540_PIN_L17 ABX500_GPIO(40) -#define AB9540_PIN_L16 ABX500_GPIO(41) -#define AB9540_PIN_W3 ABX500_GPIO(42) -#define AB9540_PIN_N4 ABX500_GPIO(50) -#define AB9540_PIN_G12 ABX500_GPIO(51) -#define AB9540_PIN_E17 ABX500_GPIO(52) -#define AB9540_PIN_D11 ABX500_GPIO(53) -#define AB9540_PIN_M18 ABX500_GPIO(54) - -/* indicates the highest GPIO number */ -#define AB9540_GPIO_MAX_NUMBER 54 - -/* - * The names of the pins are denoted by GPIO number and ball name, even - * though they can be used for other things than GPIO, this is the first - * column in the table of the data sheet and often used on schematics and - * such. - */ -static const struct pinctrl_pin_desc ab9540_pins[] = { - PINCTRL_PIN(AB9540_PIN_R4, "GPIO1_R4"), - PINCTRL_PIN(AB9540_PIN_V3, "GPIO2_V3"), - PINCTRL_PIN(AB9540_PIN_T4, "GPIO3_T4"), - PINCTRL_PIN(AB9540_PIN_T5, "GPIO4_T5"), - /* hole */ - PINCTRL_PIN(AB9540_PIN_B18, "GPIO10_B18"), - PINCTRL_PIN(AB9540_PIN_C18, "GPIO11_C18"), - /* hole */ - PINCTRL_PIN(AB9540_PIN_D18, "GPIO13_D18"), - PINCTRL_PIN(AB9540_PIN_B19, "GPIO14_B19"), - PINCTRL_PIN(AB9540_PIN_C19, "GPIO15_C19"), - PINCTRL_PIN(AB9540_PIN_D19, "GPIO16_D19"), - PINCTRL_PIN(AB9540_PIN_R3, "GPIO17_R3"), - PINCTRL_PIN(AB9540_PIN_T2, "GPIO18_T2"), - PINCTRL_PIN(AB9540_PIN_U2, "GPIO19_U2"), - PINCTRL_PIN(AB9540_PIN_V2, "GPIO20_V2"), - PINCTRL_PIN(AB9540_PIN_N17, "GPIO21_N17"), - PINCTRL_PIN(AB9540_PIN_N16, "GPIO22_N16"), - PINCTRL_PIN(AB9540_PIN_M19, "GPIO23_M19"), - PINCTRL_PIN(AB9540_PIN_T3, "GPIO24_T3"), - PINCTRL_PIN(AB9540_PIN_W2, "GPIO25_W2"), - /* hole */ - PINCTRL_PIN(AB9540_PIN_H4, "GPIO27_H4"), - PINCTRL_PIN(AB9540_PIN_F1, "GPIO28_F1"), - PINCTRL_PIN(AB9540_PIN_F4, "GPIO29_F4"), - PINCTRL_PIN(AB9540_PIN_F2, "GPIO30_F2"), - PINCTRL_PIN(AB9540_PIN_E4, "GPIO31_E4"), - PINCTRL_PIN(AB9540_PIN_F3, "GPIO32_F3"), - /* hole */ - PINCTRL_PIN(AB9540_PIN_J13, "GPIO34_J13"), - /* hole */ - PINCTRL_PIN(AB9540_PIN_L17, "GPIO40_L17"), - PINCTRL_PIN(AB9540_PIN_L16, "GPIO41_L16"), - PINCTRL_PIN(AB9540_PIN_W3, "GPIO42_W3"), - PINCTRL_PIN(AB9540_PIN_N4, "GPIO50_N4"), - PINCTRL_PIN(AB9540_PIN_G12, "GPIO51_G12"), - PINCTRL_PIN(AB9540_PIN_E17, "GPIO52_E17"), - PINCTRL_PIN(AB9540_PIN_D11, "GPIO53_D11"), - PINCTRL_PIN(AB9540_PIN_M18, "GPIO60_M18"), -}; - -/* - * Maps local GPIO offsets to local pin numbers - */ -static const struct abx500_pinrange ab9540_pinranges[] = { - ABX500_PINRANGE(1, 4, ABX500_ALT_A), - ABX500_PINRANGE(10, 2, ABX500_DEFAULT), - ABX500_PINRANGE(13, 1, ABX500_DEFAULT), - ABX500_PINRANGE(14, 12, ABX500_ALT_A), - ABX500_PINRANGE(27, 6, ABX500_ALT_A), - ABX500_PINRANGE(34, 1, ABX500_ALT_A), - ABX500_PINRANGE(40, 3, ABX500_ALT_A), - ABX500_PINRANGE(50, 1, ABX500_DEFAULT), - ABX500_PINRANGE(51, 3, ABX500_ALT_A), - ABX500_PINRANGE(54, 1, ABX500_DEFAULT), -}; - -/* - * Read the pin group names like this: - * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function - * - * The groups are arranged as sets per altfunction column, so we can - * mux in one group at a time by selecting the same altfunction for them - * all. When functions require pins on different altfunctions, you need - * to combine several groups. - */ - -/* default column */ -static const unsigned sysclkreq2_d_1_pins[] = { AB9540_PIN_R4 }; -static const unsigned sysclkreq3_d_1_pins[] = { AB9540_PIN_V3 }; -static const unsigned sysclkreq4_d_1_pins[] = { AB9540_PIN_T4 }; -static const unsigned sysclkreq6_d_1_pins[] = { AB9540_PIN_T5 }; -static const unsigned gpio10_d_1_pins[] = { AB9540_PIN_B18 }; -static const unsigned gpio11_d_1_pins[] = { AB9540_PIN_C18 }; -static const unsigned gpio13_d_1_pins[] = { AB9540_PIN_D18 }; -static const unsigned pwmout1_d_1_pins[] = { AB9540_PIN_B19 }; -static const unsigned pwmout2_d_1_pins[] = { AB9540_PIN_C19 }; -static const unsigned pwmout3_d_1_pins[] = { AB9540_PIN_D19 }; -/* audio data interface 1*/ -static const unsigned adi1_d_1_pins[] = { AB9540_PIN_R3, AB9540_PIN_T2, - AB9540_PIN_U2, AB9540_PIN_V2 }; -/* USBUICC */ -static const unsigned usbuicc_d_1_pins[] = { AB9540_PIN_N17, AB9540_PIN_N16, - AB9540_PIN_M19 }; -static const unsigned sysclkreq7_d_1_pins[] = { AB9540_PIN_T3 }; -static const unsigned sysclkreq8_d_1_pins[] = { AB9540_PIN_W2 }; -/* Digital microphone 1 and 2 */ -static const unsigned dmic12_d_1_pins[] = { AB9540_PIN_H4, AB9540_PIN_F1 }; -/* Digital microphone 3 and 4 */ -static const unsigned dmic34_d_1_pins[] = { AB9540_PIN_F4, AB9540_PIN_F2 }; -/* Digital microphone 5 and 6 */ -static const unsigned dmic56_d_1_pins[] = { AB9540_PIN_E4, AB9540_PIN_F3 }; -static const unsigned extcpena_d_1_pins[] = { AB9540_PIN_J13 }; -/* modem SDA/SCL */ -static const unsigned modsclsda_d_1_pins[] = { AB9540_PIN_L17, AB9540_PIN_L16 }; -static const unsigned sysclkreq5_d_1_pins[] = { AB9540_PIN_W3 }; -static const unsigned gpio50_d_1_pins[] = { AB9540_PIN_N4 }; -static const unsigned batremn_d_1_pins[] = { AB9540_PIN_G12 }; -static const unsigned resethw_d_1_pins[] = { AB9540_PIN_E17 }; -static const unsigned service_d_1_pins[] = { AB9540_PIN_D11 }; -static const unsigned gpio60_d_1_pins[] = { AB9540_PIN_M18 }; - -/* Altfunction A column */ -static const unsigned gpio1_a_1_pins[] = { AB9540_PIN_R4 }; -static const unsigned gpio2_a_1_pins[] = { AB9540_PIN_V3 }; -static const unsigned gpio3_a_1_pins[] = { AB9540_PIN_T4 }; -static const unsigned gpio4_a_1_pins[] = { AB9540_PIN_T5 }; -static const unsigned hiqclkena_a_1_pins[] = { AB9540_PIN_B18 }; -static const unsigned pdmclk_a_1_pins[] = { AB9540_PIN_C18 }; -static const unsigned uartdata_a_1_pins[] = { AB9540_PIN_D18, AB9540_PIN_N4 }; -static const unsigned gpio14_a_1_pins[] = { AB9540_PIN_B19 }; -static const unsigned gpio15_a_1_pins[] = { AB9540_PIN_C19 }; -static const unsigned gpio16_a_1_pins[] = { AB9540_PIN_D19 }; -static const unsigned gpio17_a_1_pins[] = { AB9540_PIN_R3 }; -static const unsigned gpio18_a_1_pins[] = { AB9540_PIN_T2 }; -static const unsigned gpio19_a_1_pins[] = { AB9540_PIN_U2 }; -static const unsigned gpio20_a_1_pins[] = { AB9540_PIN_V2 }; -static const unsigned gpio21_a_1_pins[] = { AB9540_PIN_N17 }; -static const unsigned gpio22_a_1_pins[] = { AB9540_PIN_N16 }; -static const unsigned gpio23_a_1_pins[] = { AB9540_PIN_M19 }; -static const unsigned gpio24_a_1_pins[] = { AB9540_PIN_T3 }; -static const unsigned gpio25_a_1_pins[] = { AB9540_PIN_W2 }; -static const unsigned gpio27_a_1_pins[] = { AB9540_PIN_H4 }; -static const unsigned gpio28_a_1_pins[] = { AB9540_PIN_F1 }; -static const unsigned gpio29_a_1_pins[] = { AB9540_PIN_F4 }; -static const unsigned gpio30_a_1_pins[] = { AB9540_PIN_F2 }; -static const unsigned gpio31_a_1_pins[] = { AB9540_PIN_E4 }; -static const unsigned gpio32_a_1_pins[] = { AB9540_PIN_F3 }; -static const unsigned gpio34_a_1_pins[] = { AB9540_PIN_J13 }; -static const unsigned gpio40_a_1_pins[] = { AB9540_PIN_L17 }; -static const unsigned gpio41_a_1_pins[] = { AB9540_PIN_L16 }; -static const unsigned gpio42_a_1_pins[] = { AB9540_PIN_W3 }; -static const unsigned gpio51_a_1_pins[] = { AB9540_PIN_G12 }; -static const unsigned gpio52_a_1_pins[] = { AB9540_PIN_E17 }; -static const unsigned gpio53_a_1_pins[] = { AB9540_PIN_D11 }; -static const unsigned usbuiccpd_a_1_pins[] = { AB9540_PIN_M18 }; - -/* Altfunction B colum */ -static const unsigned pdmdata_b_1_pins[] = { AB9540_PIN_B18 }; -static const unsigned pwmextvibra1_b_1_pins[] = { AB9540_PIN_D18 }; -static const unsigned pwmextvibra2_b_1_pins[] = { AB9540_PIN_N4 }; - -/* Altfunction C column */ -static const unsigned usbvdat_c_1_pins[] = { AB9540_PIN_D18 }; - -#define AB9540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ - .npins = ARRAY_SIZE(a##_pins), .altsetting = b } - -static const struct abx500_pingroup ab9540_groups[] = { - /* default column */ - AB9540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(resethw_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(service_d_1, ABX500_DEFAULT), - AB9540_PIN_GROUP(gpio60_d_1, ABX500_DEFAULT), - - /* Altfunction A column */ - AB9540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(uartdata_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio21_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio22_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio23_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio24_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio25_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio34_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), - AB9540_PIN_GROUP(usbuiccpd_a_1, ABX500_ALT_A), - - /* Altfunction B column */ - AB9540_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B), - AB9540_PIN_GROUP(pwmextvibra1_b_1, ABX500_ALT_B), - AB9540_PIN_GROUP(pwmextvibra2_b_1, ABX500_ALT_B), - - /* Altfunction C column */ - AB9540_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C), -}; - -/* We use this macro to define the groups applicable to a function */ -#define AB9540_FUNC_GROUPS(a, b...) \ -static const char * const a##_groups[] = { b }; - -AB9540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", - "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1", - "sysclkreq7_d_1", "sysclkreq8_d_1"); -AB9540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1", - "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1", - "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", "gpio18_a_1", - "gpio19_a_1", "gpio20_a_1", "gpio21_a_1", "gpio22_a_1", - "gpio23_a_1", "gpio24_a_1", "gpio25_a_1", "gpio27_a_1", - "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1", - "gpio32_a_1", "gpio34_a_1", "gpio40_a_1", "gpio41_a_1", - "gpio42_a_1", "gpio50_d_1", "gpio51_a_1", "gpio52_a_1", - "gpio53_a_1", "gpio60_d_1"); -AB9540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1"); -AB9540_FUNC_GROUPS(adi1, "adi1_d_1"); -AB9540_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_a_1"); -AB9540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1"); -AB9540_FUNC_GROUPS(extcpena, "extcpena_d_1"); -AB9540_FUNC_GROUPS(modsclsda, "modsclsda_d_1"); -AB9540_FUNC_GROUPS(batremn, "batremn_d_1"); -AB9540_FUNC_GROUPS(resethw, "resethw_d_1"); -AB9540_FUNC_GROUPS(service, "service_d_1"); -AB9540_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1"); -AB9540_FUNC_GROUPS(pdm, "pdmdata_b_1", "pdmclk_a_1"); -AB9540_FUNC_GROUPS(uartdata, "uartdata_a_1"); -AB9540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_b_1", "pwmextvibra2_b_1"); -AB9540_FUNC_GROUPS(usbvdat, "usbvdat_c_1"); - -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -static const struct abx500_function ab9540_functions[] = { - FUNCTION(sysclkreq), - FUNCTION(gpio), - FUNCTION(pwmout), - FUNCTION(adi1), - FUNCTION(usbuicc), - FUNCTION(dmic), - FUNCTION(extcpena), - FUNCTION(modsclsda), - FUNCTION(batremn), - FUNCTION(resethw), - FUNCTION(service), - FUNCTION(hiqclkena), - FUNCTION(pdm), - FUNCTION(uartdata), - FUNCTION(pwmextvibra), - FUNCTION(usbvdat), -}; - -/* - * this table translates what's is in the AB9540 specification regarding the - * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). - * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, - * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), - * - * example : - * - * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), - * means that pin AB9540_PIN_D18 (pin 13) supports 4 mux (default/ALT_A, - * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to - * select the mux. ALTA, ALTB and ALTC val indicates values to write in - * ALTERNATFUNC register. We need to specifies these values as SOC - * designers didn't apply the same logic on how to select mux in the - * ABx500 family. - * - * As this pins supports at least ALT_B mux, default mux is - * selected by writing 1 in GPIOSEL bit : - * - * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3 - * default | 1 | 0 | 0 - * alt_A | 0 | 0 | 1 - * alt_B | 0 | 0 | 0 - * alt_C | 0 | 1 | 0 - * - * ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED), - * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL - * register is used to select the mux. As this pins doesn't support at - * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit : - * - * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1= - * default | 0 | 0 | 0 - * alt_A | 1 | 0 | 0 - */ - -static struct -alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] = { - /* GPIOSEL1 - bits 4-7 are reserved */ - ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ - ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ - ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/ - ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */ - ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */ - ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */ - ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */ - /* GPIOSEL2 - bits 0 and 3 are reserved */ - ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */ - ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */ - ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */ - ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ - ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */ - /* GPIOSEL3 - bit 1-3 reserved - * pins 17 to 20 are special case, only bit 0 is used to select - * alternate function for these 4 pins. - * bits 1 to 3 are reserved - */ - ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */ - /* GPIOSEL4 - bit 1 reserved */ - ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */ - ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */ - ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */ - ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */ - /* GPIOSEL5 - bit 0, 2-6 are reserved */ - ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */ - ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */ - ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */ - ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */ - ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */ - ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */ - ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */ - /* GPIOSEL6 - bit 2-7 are reserved */ - ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */ - ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */ - ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43 */ - ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44 */ - ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45 */ - ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46 */ - ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47 */ - ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48 */ - /* - * GPIOSEL7 - bit 0 and 6-7 are reserved - * special case with GPIO60, wich is located at offset 5 of gpiosel7 - * don't know why it has been called GPIO60 in AB9540 datasheet, - * GPIO54 would be logical..., so at SOC point of view we consider - * GPIO60 = GPIO54 - */ - ALTERNATE_FUNCTIONS(49, 0, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */ - ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA and altB controlled by bit 1 */ - ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */ - ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */ - ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54 = GPIO60, altA controlled by bit 5 */ -}; - -static struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(10, 13, AB8500_INT_GPIO10R), - GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R), - GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R), - GPIO_IRQ_CLUSTER(50, 54, AB9540_INT_GPIO50R), -}; - -static struct abx500_pinctrl_soc_data ab9540_soc = { - .gpio_ranges = ab9540_pinranges, - .gpio_num_ranges = ARRAY_SIZE(ab9540_pinranges), - .pins = ab9540_pins, - .npins = ARRAY_SIZE(ab9540_pins), - .functions = ab9540_functions, - .nfunctions = ARRAY_SIZE(ab9540_functions), - .groups = ab9540_groups, - .ngroups = ARRAY_SIZE(ab9540_groups), - .alternate_functions = ab9540alternate_functions, - .gpio_irq_cluster = ab9540_gpio_irq_cluster, - .ngpio_irq_cluster = ARRAY_SIZE(ab9540_gpio_irq_cluster), - .irq_gpio_rising_offset = AB8500_INT_GPIO6R, - .irq_gpio_falling_offset = AB8500_INT_GPIO6F, - .irq_gpio_factor = 1, -}; - -void -abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc) -{ - *soc = &ab9540_soc; -} diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c deleted file mode 100644 index f3f8b24efe54..000000000000 --- a/drivers/pinctrl/pinctrl-abx500.c +++ /dev/null @@ -1,1346 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2013 - * - * Author: Patrice Chotard - * License terms: GNU General Public License (GPL) version 2 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-abx500.h" -#include "core.h" -#include "pinconf.h" - -/* - * The AB9540 and AB8540 GPIO support are extended versions - * of the AB8500 GPIO support. - * The AB9540 supports an additional (7th) register so that - * more GPIO may be configured and used. - * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have - * internal pull-up and pull-down capabilities. - */ - -/* - * GPIO registers offset - * Bank: 0x10 - */ -#define AB8500_GPIO_SEL1_REG 0x00 -#define AB8500_GPIO_SEL2_REG 0x01 -#define AB8500_GPIO_SEL3_REG 0x02 -#define AB8500_GPIO_SEL4_REG 0x03 -#define AB8500_GPIO_SEL5_REG 0x04 -#define AB8500_GPIO_SEL6_REG 0x05 -#define AB9540_GPIO_SEL7_REG 0x06 - -#define AB8500_GPIO_DIR1_REG 0x10 -#define AB8500_GPIO_DIR2_REG 0x11 -#define AB8500_GPIO_DIR3_REG 0x12 -#define AB8500_GPIO_DIR4_REG 0x13 -#define AB8500_GPIO_DIR5_REG 0x14 -#define AB8500_GPIO_DIR6_REG 0x15 -#define AB9540_GPIO_DIR7_REG 0x16 - -#define AB8500_GPIO_OUT1_REG 0x20 -#define AB8500_GPIO_OUT2_REG 0x21 -#define AB8500_GPIO_OUT3_REG 0x22 -#define AB8500_GPIO_OUT4_REG 0x23 -#define AB8500_GPIO_OUT5_REG 0x24 -#define AB8500_GPIO_OUT6_REG 0x25 -#define AB9540_GPIO_OUT7_REG 0x26 - -#define AB8500_GPIO_PUD1_REG 0x30 -#define AB8500_GPIO_PUD2_REG 0x31 -#define AB8500_GPIO_PUD3_REG 0x32 -#define AB8500_GPIO_PUD4_REG 0x33 -#define AB8500_GPIO_PUD5_REG 0x34 -#define AB8500_GPIO_PUD6_REG 0x35 -#define AB9540_GPIO_PUD7_REG 0x36 - -#define AB8500_GPIO_IN1_REG 0x40 -#define AB8500_GPIO_IN2_REG 0x41 -#define AB8500_GPIO_IN3_REG 0x42 -#define AB8500_GPIO_IN4_REG 0x43 -#define AB8500_GPIO_IN5_REG 0x44 -#define AB8500_GPIO_IN6_REG 0x45 -#define AB9540_GPIO_IN7_REG 0x46 -#define AB8540_GPIO_VINSEL_REG 0x47 -#define AB8540_GPIO_PULL_UPDOWN_REG 0x48 -#define AB8500_GPIO_ALTFUN_REG 0x50 -#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 -#define AB8540_GPIO_VINSEL_MASK 0x03 -#define AB8540_GPIOX_VBAT_START 51 -#define AB8540_GPIOX_VBAT_END 54 - -#define ABX500_GPIO_INPUT 0 -#define ABX500_GPIO_OUTPUT 1 - -struct abx500_pinctrl { - struct device *dev; - struct pinctrl_dev *pctldev; - struct abx500_pinctrl_soc_data *soc; - struct gpio_chip chip; - struct ab8500 *parent; - struct abx500_gpio_irq_cluster *irq_cluster; - int irq_cluster_size; -}; - -/** - * to_abx500_pinctrl() - get the pointer to abx500_pinctrl - * @chip: Member of the structure abx500_pinctrl - */ -static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) -{ - return container_of(chip, struct abx500_pinctrl, chip); -} - -static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, - unsigned offset, bool *bit) -{ - struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - u8 pos = offset % 8; - u8 val; - int ret; - - reg += offset / 8; - ret = abx500_get_register_interruptible(pct->dev, - AB8500_MISC, reg, &val); - - *bit = !!(val & BIT(pos)); - - if (ret < 0) - dev_err(pct->dev, - "%s read reg =%x, offset=%x failed (%d)\n", - __func__, reg, offset, ret); - - return ret; -} - -static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, - unsigned offset, int val) -{ - struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - u8 pos = offset % 8; - int ret; - - reg += offset / 8; - ret = abx500_mask_and_set_register_interruptible(pct->dev, - AB8500_MISC, reg, BIT(pos), val << pos); - if (ret < 0) - dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n", - __func__, reg, offset, ret); - - return ret; -} - -/** - * abx500_gpio_get() - Get the particular GPIO value - * @chip: Gpio device - * @offset: GPIO number to read - */ -static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - bool bit; - bool is_out; - u8 gpio_offset = offset - 1; - int ret; - - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, - gpio_offset, &is_out); - if (ret < 0) - goto out; - - if (is_out) - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG, - gpio_offset, &bit); - else - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, - gpio_offset, &bit); -out: - if (ret < 0) { - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); - return ret; - } - - return bit; -} - -static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) -{ - struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - int ret; - - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); - if (ret < 0) - dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret); -} - -static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset, - enum abx500_gpio_pull_updown *pull_updown) -{ - u8 pos; - u8 val; - int ret; - struct pullud *pullud; - - if (!pct->soc->pullud) { - dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", - __func__); - ret = -EPERM; - goto out; - } - - pullud = pct->soc->pullud; - - if ((offset < pullud->first_pin) - || (offset > pullud->last_pin)) { - ret = -EINVAL; - goto out; - } - - ret = abx500_get_register_interruptible(pct->dev, - AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val); - - pos = (offset - pullud->first_pin) << 1; - *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK; - -out: - if (ret < 0) - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); - - return ret; -} - -static int abx500_set_pull_updown(struct abx500_pinctrl *pct, - int offset, enum abx500_gpio_pull_updown val) -{ - u8 pos; - int ret; - struct pullud *pullud; - - if (!pct->soc->pullud) { - dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", - __func__); - ret = -EPERM; - goto out; - } - - pullud = pct->soc->pullud; - - if ((offset < pullud->first_pin) - || (offset > pullud->last_pin)) { - ret = -EINVAL; - goto out; - } - pos = (offset - pullud->first_pin) << 1; - - ret = abx500_mask_and_set_register_interruptible(pct->dev, - AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, - AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); - -out: - if (ret < 0) - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); - - return ret; -} - -static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio) -{ - struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - struct pullud *pullud = pct->soc->pullud; - - return (pullud && - gpio >= pullud->first_pin && - gpio <= pullud->last_pin); -} - -static int abx500_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, - int val) -{ - struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - unsigned gpio; - int ret; - - /* set direction as output */ - ret = abx500_gpio_set_bits(chip, - AB8500_GPIO_DIR1_REG, - offset, - ABX500_GPIO_OUTPUT); - if (ret < 0) - goto out; - - /* disable pull down */ - ret = abx500_gpio_set_bits(chip, - AB8500_GPIO_PUD1_REG, - offset, - ABX500_GPIO_PULL_NONE); - if (ret < 0) - goto out; - - /* if supported, disable both pull down and pull up */ - gpio = offset + 1; - if (abx500_pullud_supported(chip, gpio)) { - ret = abx500_set_pull_updown(pct, - gpio, - ABX500_GPIO_PULL_NONE); - } -out: - if (ret < 0) { - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); - return ret; - } - - /* set the output as 1 or 0 */ - return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); -} - -static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - /* set the register as input */ - return abx500_gpio_set_bits(chip, - AB8500_GPIO_DIR1_REG, - offset, - ABX500_GPIO_INPUT); -} - -static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - /* The AB8500 GPIO numbers are off by one */ - int gpio = offset + 1; - int hwirq; - int i; - - for (i = 0; i < pct->irq_cluster_size; i++) { - struct abx500_gpio_irq_cluster *cluster = - &pct->irq_cluster[i]; - - if (gpio >= cluster->start && gpio <= cluster->end) { - /* - * The ABx500 GPIO's associated IRQs are clustered together - * throughout the interrupt numbers at irregular intervals. - * To solve this quandry, we have placed the read-in values - * into the cluster information table. - */ - hwirq = gpio - cluster->start + cluster->to_irq; - return irq_create_mapping(pct->parent->domain, hwirq); - } - } - - return -EINVAL; -} - -static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, - unsigned gpio, int alt_setting) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - struct alternate_functions af = pct->soc->alternate_functions[gpio]; - int ret; - int val; - unsigned offset; - - const char *modes[] = { - [ABX500_DEFAULT] = "default", - [ABX500_ALT_A] = "altA", - [ABX500_ALT_B] = "altB", - [ABX500_ALT_C] = "altC", - }; - - /* sanity check */ - if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || - ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || - ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { - dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, - modes[alt_setting]); - return -EINVAL; - } - - /* on ABx5xx, there is no GPIO0, so adjust the offset */ - offset = gpio - 1; - - switch (alt_setting) { - case ABX500_DEFAULT: - /* - * for ABx5xx family, default mode is always selected by - * writing 0 to GPIOSELx register, except for pins which - * support at least ALT_B mode, default mode is selected - * by writing 1 to GPIOSELx register - */ - val = 0; - if (af.alt_bit1 != UNUSED) - val++; - - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, - offset, val); - break; - - case ABX500_ALT_A: - /* - * for ABx5xx family, alt_a mode is always selected by - * writing 1 to GPIOSELx register, except for pins which - * support at least ALT_B mode, alt_a mode is selected - * by writing 0 to GPIOSELx register and 0 in ALTFUNC - * register - */ - if (af.alt_bit1 != UNUSED) { - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, - offset, 0); - if (ret < 0) - goto out; - - ret = abx500_gpio_set_bits(chip, - AB8500_GPIO_ALTFUN_REG, - af.alt_bit1, - !!(af.alta_val & BIT(0))); - if (ret < 0) - goto out; - - if (af.alt_bit2 != UNUSED) - ret = abx500_gpio_set_bits(chip, - AB8500_GPIO_ALTFUN_REG, - af.alt_bit2, - !!(af.alta_val & BIT(1))); - } else - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, - offset, 1); - break; - - case ABX500_ALT_B: - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, - offset, 0); - if (ret < 0) - goto out; - - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, - af.alt_bit1, !!(af.altb_val & BIT(0))); - if (ret < 0) - goto out; - - if (af.alt_bit2 != UNUSED) - ret = abx500_gpio_set_bits(chip, - AB8500_GPIO_ALTFUN_REG, - af.alt_bit2, - !!(af.altb_val & BIT(1))); - break; - - case ABX500_ALT_C: - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, - offset, 0); - if (ret < 0) - goto out; - - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, - af.alt_bit2, !!(af.altc_val & BIT(0))); - if (ret < 0) - goto out; - - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, - af.alt_bit2, !!(af.altc_val & BIT(1))); - break; - - default: - dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); - - return -EINVAL; - } -out: - if (ret < 0) - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); - - return ret; -} - -static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, - unsigned gpio) -{ - u8 mode; - bool bit_mode; - bool alt_bit1; - bool alt_bit2; - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - struct alternate_functions af = pct->soc->alternate_functions[gpio]; - /* on ABx5xx, there is no GPIO0, so adjust the offset */ - unsigned offset = gpio - 1; - int ret; - - /* - * if gpiosel_bit is set to unused, - * it means no GPIO or special case - */ - if (af.gpiosel_bit == UNUSED) - return ABX500_DEFAULT; - - /* read GpioSelx register */ - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), - af.gpiosel_bit, &bit_mode); - if (ret < 0) - goto out; - - mode = bit_mode; - - /* sanity check */ - if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || - (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { - dev_err(pct->dev, - "alt_bitX value not in correct range (-1 to 7)\n"); - return -EINVAL; - } - - /* if alt_bit2 is used, alt_bit1 must be used too */ - if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { - dev_err(pct->dev, - "if alt_bit2 is used, alt_bit1 can't be unused\n"); - return -EINVAL; - } - - /* check if pin use AlternateFunction register */ - if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) - return mode; - /* - * if pin GPIOSEL bit is set and pin supports alternate function, - * it means DEFAULT mode - */ - if (mode) - return ABX500_DEFAULT; - - /* - * pin use the AlternatFunction register - * read alt_bit1 value - */ - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, - af.alt_bit1, &alt_bit1); - if (ret < 0) - goto out; - - if (af.alt_bit2 != UNUSED) { - /* read alt_bit2 value */ - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, - af.alt_bit2, - &alt_bit2); - if (ret < 0) - goto out; - } else - alt_bit2 = 0; - - mode = (alt_bit2 << 1) + alt_bit1; - if (mode == af.alta_val) - return ABX500_ALT_A; - else if (mode == af.altb_val) - return ABX500_ALT_B; - else - return ABX500_ALT_C; - -out: - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); - return ret; -} - -#ifdef CONFIG_DEBUG_FS - -#include - -static void abx500_gpio_dbg_show_one(struct seq_file *s, - struct pinctrl_dev *pctldev, - struct gpio_chip *chip, - unsigned offset, unsigned gpio) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - const char *label = gpiochip_is_requested(chip, offset - 1); - u8 gpio_offset = offset - 1; - int mode = -1; - bool is_out; - bool pd; - enum abx500_gpio_pull_updown pud = 0; - int ret; - - const char *modes[] = { - [ABX500_DEFAULT] = "default", - [ABX500_ALT_A] = "altA", - [ABX500_ALT_B] = "altB", - [ABX500_ALT_C] = "altC", - }; - - const char *pull_up_down[] = { - [ABX500_GPIO_PULL_DOWN] = "pull down", - [ABX500_GPIO_PULL_NONE] = "pull none", - [ABX500_GPIO_PULL_NONE + 1] = "pull none", - [ABX500_GPIO_PULL_UP] = "pull up", - }; - - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, - gpio_offset, &is_out); - if (ret < 0) - goto out; - - seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", - gpio, label ?: "(none)", - is_out ? "out" : "in "); - - if (!is_out) { - if (abx500_pullud_supported(chip, offset)) { - ret = abx500_get_pull_updown(pct, offset, &pud); - if (ret < 0) - goto out; - - seq_printf(s, " %-9s", pull_up_down[pud]); - } else { - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, - gpio_offset, &pd); - if (ret < 0) - goto out; - - seq_printf(s, " %-9s", pull_up_down[pd]); - } - } else - seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); - - if (pctldev) - mode = abx500_get_mode(pctldev, chip, offset); - - seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); - -out: - if (ret < 0) - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); -} - -static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - unsigned i; - unsigned gpio = chip->base; - struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - struct pinctrl_dev *pctldev = pct->pctldev; - - for (i = 0; i < chip->ngpio; i++, gpio++) { - /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ - abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); - seq_printf(s, "\n"); - } -} - -#else -static inline void abx500_gpio_dbg_show_one(struct seq_file *s, - struct pinctrl_dev *pctldev, - struct gpio_chip *chip, - unsigned offset, unsigned gpio) -{ -} -#define abx500_gpio_dbg_show NULL -#endif - -static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - - return pinctrl_request_gpio(gpio); -} - -static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - - pinctrl_free_gpio(gpio); -} - -static struct gpio_chip abx500gpio_chip = { - .label = "abx500-gpio", - .owner = THIS_MODULE, - .request = abx500_gpio_request, - .free = abx500_gpio_free, - .direction_input = abx500_gpio_direction_input, - .get = abx500_gpio_get, - .direction_output = abx500_gpio_direction_output, - .set = abx500_gpio_set, - .to_irq = abx500_gpio_to_irq, - .dbg_show = abx500_gpio_dbg_show, -}; - -static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - - return pct->soc->nfunctions; -} - -static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - - return pct->soc->functions[function].name; -} - -static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, - unsigned function, - const char * const **groups, - unsigned * const num_groups) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - - *groups = pct->soc->functions[function].groups; - *num_groups = pct->soc->functions[function].ngroups; - - return 0; -} - -static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - struct gpio_chip *chip = &pct->chip; - const struct abx500_pingroup *g; - int i; - int ret = 0; - - g = &pct->soc->groups[group]; - if (g->altsetting < 0) - return -EINVAL; - - dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); - - for (i = 0; i < g->npins; i++) { - dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", - g->pins[i], g->altsetting); - - ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); - } - - if (ret < 0) - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); - - return ret; -} - -static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - const struct abx500_pinrange *p; - int ret; - int i; - - /* - * Different ranges have different ways to enable GPIO function on a - * pin, so refer back to our local range type, where we handily define - * what altfunc enables GPIO for a certain pin. - */ - for (i = 0; i < pct->soc->gpio_num_ranges; i++) { - p = &pct->soc->gpio_ranges[i]; - if ((offset >= p->offset) && - (offset < (p->offset + p->npins))) - break; - } - - if (i == pct->soc->gpio_num_ranges) { - dev_err(pct->dev, "%s failed to locate range\n", __func__); - return -ENODEV; - } - - dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", - p->altfunc, offset); - - ret = abx500_set_mode(pct->pctldev, &pct->chip, - offset, p->altfunc); - if (ret < 0) - dev_err(pct->dev, "%s setting altfunc failed\n", __func__); - - return ret; -} - -static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ -} - -static const struct pinmux_ops abx500_pinmux_ops = { - .get_functions_count = abx500_pmx_get_funcs_cnt, - .get_function_name = abx500_pmx_get_func_name, - .get_function_groups = abx500_pmx_get_func_groups, - .enable = abx500_pmx_enable, - .gpio_request_enable = abx500_gpio_request_enable, - .gpio_disable_free = abx500_gpio_disable_free, -}; - -static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - - return pct->soc->ngroups; -} - -static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - - return pct->soc->groups[selector].name; -} - -static int abx500_get_group_pins(struct pinctrl_dev *pctldev, - unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - - *pins = pct->soc->groups[selector].pins; - *num_pins = pct->soc->groups[selector].npins; - - return 0; -} - -static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned offset) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - struct gpio_chip *chip = &pct->chip; - - abx500_gpio_dbg_show_one(s, pctldev, chip, offset, - chip->base + offset - 1); -} - -static void abx500_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) - kfree(map[i].data.configs.configs); - kfree(map); -} - -static int abx500_dt_reserve_map(struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps, - unsigned reserve) -{ - unsigned old_num = *reserved_maps; - unsigned new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int abx500_dt_add_map_mux(struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps, const char *group, - const char *function) -{ - if (*num_maps == *reserved_maps) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -static int abx500_dt_add_map_configs(struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps, const char *group, - unsigned long *configs, unsigned num_configs) -{ - unsigned long *dup_configs; - - if (*num_maps == *reserved_maps) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) - return -ENOMEM; - - (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; - - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev, - const char *pin_name) -{ - int i, pin_number; - struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) - for (i = 0; i < npct->soc->npins; i++) - if (npct->soc->pins[i].number == pin_number) - return npct->soc->pins[i].name; - return NULL; -} - -static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps) -{ - int ret; - const char *function = NULL; - unsigned long *configs; - unsigned int nconfigs = 0; - bool has_config = 0; - unsigned reserve = 0; - struct property *prop; - const char *group, *gpio_name; - struct device_node *np_config; - - ret = of_property_read_string(np, "ste,function", &function); - if (ret >= 0) - reserve = 1; - - ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); - if (nconfigs) - has_config = 1; - - np_config = of_parse_phandle(np, "ste,config", 0); - if (np_config) { - ret = pinconf_generic_parse_dt_config(np_config, &configs, - &nconfigs); - if (ret) - goto exit; - has_config |= nconfigs; - } - - ret = of_property_count_strings(np, "ste,pins"); - if (ret < 0) - goto exit; - - if (has_config) - reserve++; - - reserve *= ret; - - ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "ste,pins", prop, group) { - if (function) { - ret = abx500_dt_add_map_mux(map, reserved_maps, - num_maps, group, function); - if (ret < 0) - goto exit; - } - if (has_config) { - gpio_name = abx500_find_pin_name(pctldev, group); - - ret = abx500_dt_add_map_configs(map, reserved_maps, - num_maps, gpio_name, configs, 1); - if (ret < 0) - goto exit; - } - - } -exit: - return ret; -} - -static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - unsigned reserved_maps; - struct device_node *np; - int ret; - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = abx500_dt_subnode_to_map(pctldev, np, map, - &reserved_maps, num_maps); - if (ret < 0) { - abx500_dt_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; -} - -static const struct pinctrl_ops abx500_pinctrl_ops = { - .get_groups_count = abx500_get_groups_cnt, - .get_group_name = abx500_get_group_name, - .get_group_pins = abx500_get_group_pins, - .pin_dbg_show = abx500_pin_dbg_show, - .dt_node_to_map = abx500_dt_node_to_map, - .dt_free_map = abx500_dt_free_map, -}; - -static int abx500_pin_config_get(struct pinctrl_dev *pctldev, - unsigned pin, - unsigned long *config) -{ - return -ENOSYS; -} - -static int abx500_pin_config_set(struct pinctrl_dev *pctldev, - unsigned pin, - unsigned long *configs, - unsigned num_configs) -{ - struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - struct gpio_chip *chip = &pct->chip; - unsigned offset; - int ret = -EINVAL; - int i; - enum pin_config_param param; - enum pin_config_param argument; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - argument = pinconf_to_config_argument(configs[i]); - - dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", - pin, configs[i], - (param == PIN_CONFIG_OUTPUT) ? "output " : "input", - (param == PIN_CONFIG_OUTPUT) ? - (argument ? "high" : "low") : - (argument ? "pull up" : "pull down")); - - /* on ABx500, there is no GPIO0, so adjust the offset */ - offset = pin - 1; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - ret = abx500_gpio_direction_input(chip, offset); - if (ret < 0) - goto out; - /* - * Some chips only support pull down, while some - * actually support both pull up and pull down. Such - * chips have a "pullud" range specified for the pins - * that support both features. If the pin is not - * within that range, we fall back to the old bit set - * that only support pull down. - */ - if (abx500_pullud_supported(chip, pin)) - ret = abx500_set_pull_updown(pct, - pin, - ABX500_GPIO_PULL_NONE); - else - /* Chip only supports pull down */ - ret = abx500_gpio_set_bits(chip, - AB8500_GPIO_PUD1_REG, offset, - ABX500_GPIO_PULL_NONE); - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - ret = abx500_gpio_direction_input(chip, offset); - if (ret < 0) - goto out; - /* - * if argument = 1 set the pull down - * else clear the pull down - * Some chips only support pull down, while some - * actually support both pull up and pull down. Such - * chips have a "pullud" range specified for the pins - * that support both features. If the pin is not - * within that range, we fall back to the old bit set - * that only support pull down. - */ - if (abx500_pullud_supported(chip, pin)) - ret = abx500_set_pull_updown(pct, - pin, - argument ? ABX500_GPIO_PULL_DOWN : - ABX500_GPIO_PULL_NONE); - else - /* Chip only supports pull down */ - ret = abx500_gpio_set_bits(chip, - AB8500_GPIO_PUD1_REG, - offset, - argument ? ABX500_GPIO_PULL_DOWN : - ABX500_GPIO_PULL_NONE); - break; - - case PIN_CONFIG_BIAS_PULL_UP: - ret = abx500_gpio_direction_input(chip, offset); - if (ret < 0) - goto out; - /* - * if argument = 1 set the pull up - * else clear the pull up - */ - ret = abx500_gpio_direction_input(chip, offset); - /* - * Some chips only support pull down, while some - * actually support both pull up and pull down. Such - * chips have a "pullud" range specified for the pins - * that support both features. If the pin is not - * within that range, do nothing - */ - if (abx500_pullud_supported(chip, pin)) - ret = abx500_set_pull_updown(pct, - pin, - argument ? ABX500_GPIO_PULL_UP : - ABX500_GPIO_PULL_NONE); - break; - - case PIN_CONFIG_OUTPUT: - ret = abx500_gpio_direction_output(chip, offset, - argument); - break; - - default: - dev_err(chip->dev, "illegal configuration requested\n"); - } - } /* for each config */ -out: - if (ret < 0) - dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); - - return ret; -} - -static const struct pinconf_ops abx500_pinconf_ops = { - .pin_config_get = abx500_pin_config_get, - .pin_config_set = abx500_pin_config_set, -}; - -static struct pinctrl_desc abx500_pinctrl_desc = { - .name = "pinctrl-abx500", - .pctlops = &abx500_pinctrl_ops, - .pmxops = &abx500_pinmux_ops, - .confops = &abx500_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) -{ - unsigned int lowest = 0; - unsigned int highest = 0; - unsigned int npins = 0; - int i; - - /* - * Compute number of GPIOs from the last SoC gpio range descriptors - * These ranges may include "holes" but the GPIO number space shall - * still be homogeneous, so we need to detect and account for any - * such holes so that these are included in the number of GPIO pins. - */ - for (i = 0; i < soc->gpio_num_ranges; i++) { - unsigned gstart; - unsigned gend; - const struct abx500_pinrange *p; - - p = &soc->gpio_ranges[i]; - gstart = p->offset; - gend = p->offset + p->npins - 1; - - if (i == 0) { - /* First iteration, set start values */ - lowest = gstart; - highest = gend; - } else { - if (gstart < lowest) - lowest = gstart; - if (gend > highest) - highest = gend; - } - } - /* this gives the absolute number of pins */ - npins = highest - lowest + 1; - return npins; -} - -static const struct of_device_id abx500_gpio_match[] = { - { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, - { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, - { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, - { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, - { } -}; - -static int abx500_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - const struct of_device_id *match; - struct abx500_pinctrl *pct; - unsigned int id = -1; - int ret, err; - int i; - - if (!np) { - dev_err(&pdev->dev, "gpio dt node missing\n"); - return -ENODEV; - } - - pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), - GFP_KERNEL); - if (pct == NULL) { - dev_err(&pdev->dev, - "failed to allocate memory for pct\n"); - return -ENOMEM; - } - - pct->dev = &pdev->dev; - pct->parent = dev_get_drvdata(pdev->dev.parent); - pct->chip = abx500gpio_chip; - pct->chip.dev = &pdev->dev; - pct->chip.base = -1; /* Dynamic allocation */ - - match = of_match_device(abx500_gpio_match, &pdev->dev); - if (!match) { - dev_err(&pdev->dev, "gpio dt not matching\n"); - return -ENODEV; - } - id = (unsigned long)match->data; - - /* Poke in other ASIC variants here */ - switch (id) { - case PINCTRL_AB8500: - abx500_pinctrl_ab8500_init(&pct->soc); - break; - case PINCTRL_AB8540: - abx500_pinctrl_ab8540_init(&pct->soc); - break; - case PINCTRL_AB9540: - abx500_pinctrl_ab9540_init(&pct->soc); - break; - case PINCTRL_AB8505: - abx500_pinctrl_ab8505_init(&pct->soc); - break; - default: - dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); - return -EINVAL; - } - - if (!pct->soc) { - dev_err(&pdev->dev, "Invalid SOC data\n"); - return -EINVAL; - } - - pct->chip.ngpio = abx500_get_gpio_num(pct->soc); - pct->irq_cluster = pct->soc->gpio_irq_cluster; - pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; - - ret = gpiochip_add(&pct->chip); - if (ret) { - dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); - return ret; - } - dev_info(&pdev->dev, "added gpiochip\n"); - - abx500_pinctrl_desc.pins = pct->soc->pins; - abx500_pinctrl_desc.npins = pct->soc->npins; - pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); - if (!pct->pctldev) { - dev_err(&pdev->dev, - "could not register abx500 pinctrl driver\n"); - ret = -EINVAL; - goto out_rem_chip; - } - dev_info(&pdev->dev, "registered pin controller\n"); - - /* We will handle a range of GPIO pins */ - for (i = 0; i < pct->soc->gpio_num_ranges; i++) { - const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; - - ret = gpiochip_add_pin_range(&pct->chip, - dev_name(&pdev->dev), - p->offset - 1, p->offset, p->npins); - if (ret < 0) - goto out_rem_chip; - } - - platform_set_drvdata(pdev, pct); - dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); - - return 0; - -out_rem_chip: - err = gpiochip_remove(&pct->chip); - if (err) - dev_info(&pdev->dev, "failed to remove gpiochip\n"); - - return ret; -} - -/** - * abx500_gpio_remove() - remove Ab8500-gpio driver - * @pdev: Platform device registered - */ -static int abx500_gpio_remove(struct platform_device *pdev) -{ - struct abx500_pinctrl *pct = platform_get_drvdata(pdev); - int ret; - - ret = gpiochip_remove(&pct->chip); - if (ret < 0) { - dev_err(pct->dev, "unable to remove gpiochip: %d\n", - ret); - return ret; - } - - return 0; -} - -static struct platform_driver abx500_gpio_driver = { - .driver = { - .name = "abx500-gpio", - .owner = THIS_MODULE, - .of_match_table = abx500_gpio_match, - }, - .probe = abx500_gpio_probe, - .remove = abx500_gpio_remove, -}; - -static int __init abx500_gpio_init(void) -{ - return platform_driver_register(&abx500_gpio_driver); -} -core_initcall(abx500_gpio_init); - -MODULE_AUTHOR("Patrice Chotard "); -MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); -MODULE_ALIAS("platform:abx500-gpio"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/pinctrl-abx500.h deleted file mode 100644 index 2beef3bfe9ca..000000000000 --- a/drivers/pinctrl/pinctrl-abx500.h +++ /dev/null @@ -1,246 +0,0 @@ -#ifndef PINCTRL_PINCTRL_ABx500_H -#define PINCTRL_PINCTRL_ABx500_H - -/* Package definitions */ -#define PINCTRL_AB8500 0 -#define PINCTRL_AB8540 1 -#define PINCTRL_AB9540 2 -#define PINCTRL_AB8505 3 - -/* pins alternate function */ -enum abx500_pin_func { - ABX500_DEFAULT, - ABX500_ALT_A, - ABX500_ALT_B, - ABX500_ALT_C, -}; - -enum abx500_gpio_pull_updown { - ABX500_GPIO_PULL_DOWN = 0x0, - ABX500_GPIO_PULL_NONE = 0x1, - ABX500_GPIO_PULL_UP = 0x3, -}; - -enum abx500_gpio_vinsel { - ABX500_GPIO_VINSEL_VBAT = 0x0, - ABX500_GPIO_VINSEL_VIN_1V8 = 0x1, - ABX500_GPIO_VINSEL_VDD_BIF = 0x2, -}; - -/** - * struct abx500_function - ABx500 pinctrl mux function - * @name: The name of the function, exported to pinctrl core. - * @groups: An array of pin groups that may select this function. - * @ngroups: The number of entries in @groups. - */ -struct abx500_function { - const char *name; - const char * const *groups; - unsigned ngroups; -}; - -/** - * struct abx500_pingroup - describes a ABx500 pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @num_pins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - * @altsetting: the altsetting to apply to all pins in this group to - * configure them to be used by a function - */ -struct abx500_pingroup { - const char *name; - const unsigned int *pins; - const unsigned npins; - int altsetting; -}; - -#define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \ -{ \ - .pin_number = pin, \ - .gpiosel_bit = sel_bit, \ - .alt_bit1 = alt1, \ - .alt_bit2 = alt2, \ - .alta_val = alta, \ - .altb_val = altb, \ - .altc_val = altc, \ -} - -#define UNUSED -1 -/** - * struct alternate_functions - * @pin_number: The pin number - * @gpiosel_bit: Control bit in GPIOSEL register, - * @alt_bit1: First AlternateFunction bit used to select the - * alternate function - * @alt_bit2: Second AlternateFunction bit used to select the - * alternate function - * - * these 3 following fields are necessary due to none - * coherency on how to select the altA, altB and altC - * function between the ABx500 SOC family when using - * alternatfunc register. - * @alta_val: value to write in alternatfunc to select altA function - * @altb_val: value to write in alternatfunc to select altB function - * @altc_val: value to write in alternatfunc to select altC function - */ -struct alternate_functions { - unsigned pin_number; - s8 gpiosel_bit; - s8 alt_bit1; - s8 alt_bit2; - u8 alta_val; - u8 altb_val; - u8 altc_val; -}; - -/** - * struct pullud - specific pull up/down feature - * @first_pin: The pin number of the first pins which support - * specific pull up/down - * @last_pin: The pin number of the last pins - */ -struct pullud { - unsigned first_pin; - unsigned last_pin; -}; - -#define GPIO_IRQ_CLUSTER(a, b, c) \ -{ \ - .start = a, \ - .end = b, \ - .to_irq = c, \ -} - -/** - * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt - * capable - * @start: The pin number of the first pin interrupt capable - * @end: The pin number of the last pin interrupt capable - * @to_irq: The ABx500 GPIO's associated IRQs are clustered - * together throughout the interrupt numbers at irregular - * intervals. To solve this quandary, we will place the - * read-in values into the cluster information table - */ - -struct abx500_gpio_irq_cluster { - int start; - int end; - int to_irq; -}; - -/** - * struct abx500_pinrange - map pin numbers to GPIO offsets - * @offset: offset into the GPIO local numberspace, incidentally - * identical to the offset into the local pin numberspace - * @npins: number of pins to map from both offsets - * @altfunc: altfunc setting to be used to enable GPIO on a pin in - * this range (may vary) - */ -struct abx500_pinrange { - unsigned int offset; - unsigned int npins; - int altfunc; -}; - -#define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c } - -/** - * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration - * @gpio_ranges: An array of GPIO ranges for this SoC - * @gpio_num_ranges: The number of GPIO ranges for this SoC - * @pins: An array describing all pins the pin controller affects. - * All pins which are also GPIOs must be listed first within the - * array, and be numbered identically to the GPIO controller's - * numbering. - * @npins: The number of entries in @pins. - * @functions: The functions supported on this SoC. - * @nfunction: The number of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The number of entries in @groups. - * @alternate_functions: array describing pins which supports alternate and - * how to set it. - * @pullud: array describing pins which supports pull up/down - * specific registers. - * @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC - * @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC - * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific - * setting strategy of the rising interrupt line - * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific - * setting strategy of the falling interrupt line - * @irq_gpio_factor: Factor used to compute specific setting strategy of - * the interrupt line - */ - -struct abx500_pinctrl_soc_data { - const struct abx500_pinrange *gpio_ranges; - unsigned gpio_num_ranges; - const struct pinctrl_pin_desc *pins; - unsigned npins; - const struct abx500_function *functions; - unsigned nfunctions; - const struct abx500_pingroup *groups; - unsigned ngroups; - struct alternate_functions *alternate_functions; - struct pullud *pullud; - struct abx500_gpio_irq_cluster *gpio_irq_cluster; - unsigned ngpio_irq_cluster; - int irq_gpio_rising_offset; - int irq_gpio_falling_offset; - int irq_gpio_factor; -}; - -#ifdef CONFIG_PINCTRL_AB8500 - -void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc); - -#else - -static inline void -abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc) -{ -} - -#endif - -#ifdef CONFIG_PINCTRL_AB8540 - -void abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc); - -#else - -static inline void -abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc) -{ -} - -#endif - -#ifdef CONFIG_PINCTRL_AB9540 - -void abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc); - -#else - -static inline void -abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc) -{ -} - -#endif - -#ifdef CONFIG_PINCTRL_AB8505 - -void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc); - -#else - -static inline void -abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc) -{ -} - -#endif - -#endif /* PINCTRL_PINCTRL_ABx500_H */ diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c deleted file mode 100644 index c74840729648..000000000000 --- a/drivers/pinctrl/pinctrl-nomadik-db8500.c +++ /dev/null @@ -1,1257 +0,0 @@ -#include -#include -#include "pinctrl-nomadik.h" - -/* All the pins that can be used for GPIO and some other functions */ -#define _GPIO(offset) (offset) - -#define DB8500_PIN_AJ5 _GPIO(0) -#define DB8500_PIN_AJ3 _GPIO(1) -#define DB8500_PIN_AH4 _GPIO(2) -#define DB8500_PIN_AH3 _GPIO(3) -#define DB8500_PIN_AH6 _GPIO(4) -#define DB8500_PIN_AG6 _GPIO(5) -#define DB8500_PIN_AF6 _GPIO(6) -#define DB8500_PIN_AG5 _GPIO(7) -#define DB8500_PIN_AD5 _GPIO(8) -#define DB8500_PIN_AE4 _GPIO(9) -#define DB8500_PIN_AF5 _GPIO(10) -#define DB8500_PIN_AG4 _GPIO(11) -#define DB8500_PIN_AC4 _GPIO(12) -#define DB8500_PIN_AF3 _GPIO(13) -#define DB8500_PIN_AE3 _GPIO(14) -#define DB8500_PIN_AC3 _GPIO(15) -#define DB8500_PIN_AD3 _GPIO(16) -#define DB8500_PIN_AD4 _GPIO(17) -#define DB8500_PIN_AC2 _GPIO(18) -#define DB8500_PIN_AC1 _GPIO(19) -#define DB8500_PIN_AB4 _GPIO(20) -#define DB8500_PIN_AB3 _GPIO(21) -#define DB8500_PIN_AA3 _GPIO(22) -#define DB8500_PIN_AA4 _GPIO(23) -#define DB8500_PIN_AB2 _GPIO(24) -#define DB8500_PIN_Y4 _GPIO(25) -#define DB8500_PIN_Y2 _GPIO(26) -#define DB8500_PIN_AA2 _GPIO(27) -#define DB8500_PIN_AA1 _GPIO(28) -#define DB8500_PIN_W2 _GPIO(29) -#define DB8500_PIN_W3 _GPIO(30) -#define DB8500_PIN_V3 _GPIO(31) -#define DB8500_PIN_V2 _GPIO(32) -#define DB8500_PIN_AF2 _GPIO(33) -#define DB8500_PIN_AE1 _GPIO(34) -#define DB8500_PIN_AE2 _GPIO(35) -#define DB8500_PIN_AG2 _GPIO(36) -/* Hole */ -#define DB8500_PIN_F3 _GPIO(64) -#define DB8500_PIN_F1 _GPIO(65) -#define DB8500_PIN_G3 _GPIO(66) -#define DB8500_PIN_G2 _GPIO(67) -#define DB8500_PIN_E1 _GPIO(68) -#define DB8500_PIN_E2 _GPIO(69) -#define DB8500_PIN_G5 _GPIO(70) -#define DB8500_PIN_G4 _GPIO(71) -#define DB8500_PIN_H4 _GPIO(72) -#define DB8500_PIN_H3 _GPIO(73) -#define DB8500_PIN_J3 _GPIO(74) -#define DB8500_PIN_H2 _GPIO(75) -#define DB8500_PIN_J2 _GPIO(76) -#define DB8500_PIN_H1 _GPIO(77) -#define DB8500_PIN_F4 _GPIO(78) -#define DB8500_PIN_E3 _GPIO(79) -#define DB8500_PIN_E4 _GPIO(80) -#define DB8500_PIN_D2 _GPIO(81) -#define DB8500_PIN_C1 _GPIO(82) -#define DB8500_PIN_D3 _GPIO(83) -#define DB8500_PIN_C2 _GPIO(84) -#define DB8500_PIN_D5 _GPIO(85) -#define DB8500_PIN_C6 _GPIO(86) -#define DB8500_PIN_B3 _GPIO(87) -#define DB8500_PIN_C4 _GPIO(88) -#define DB8500_PIN_E6 _GPIO(89) -#define DB8500_PIN_A3 _GPIO(90) -#define DB8500_PIN_B6 _GPIO(91) -#define DB8500_PIN_D6 _GPIO(92) -#define DB8500_PIN_B7 _GPIO(93) -#define DB8500_PIN_D7 _GPIO(94) -#define DB8500_PIN_E8 _GPIO(95) -#define DB8500_PIN_D8 _GPIO(96) -#define DB8500_PIN_D9 _GPIO(97) -/* Hole */ -#define DB8500_PIN_A5 _GPIO(128) -#define DB8500_PIN_B4 _GPIO(129) -#define DB8500_PIN_C8 _GPIO(130) -#define DB8500_PIN_A12 _GPIO(131) -#define DB8500_PIN_C10 _GPIO(132) -#define DB8500_PIN_B10 _GPIO(133) -#define DB8500_PIN_B9 _GPIO(134) -#define DB8500_PIN_A9 _GPIO(135) -#define DB8500_PIN_C7 _GPIO(136) -#define DB8500_PIN_A7 _GPIO(137) -#define DB8500_PIN_C5 _GPIO(138) -#define DB8500_PIN_C9 _GPIO(139) -#define DB8500_PIN_B11 _GPIO(140) -#define DB8500_PIN_C12 _GPIO(141) -#define DB8500_PIN_C11 _GPIO(142) -#define DB8500_PIN_D12 _GPIO(143) -#define DB8500_PIN_B13 _GPIO(144) -#define DB8500_PIN_C13 _GPIO(145) -#define DB8500_PIN_D13 _GPIO(146) -#define DB8500_PIN_C15 _GPIO(147) -#define DB8500_PIN_B16 _GPIO(148) -#define DB8500_PIN_B14 _GPIO(149) -#define DB8500_PIN_C14 _GPIO(150) -#define DB8500_PIN_D17 _GPIO(151) -#define DB8500_PIN_D16 _GPIO(152) -#define DB8500_PIN_B17 _GPIO(153) -#define DB8500_PIN_C16 _GPIO(154) -#define DB8500_PIN_C19 _GPIO(155) -#define DB8500_PIN_C17 _GPIO(156) -#define DB8500_PIN_A18 _GPIO(157) -#define DB8500_PIN_C18 _GPIO(158) -#define DB8500_PIN_B19 _GPIO(159) -#define DB8500_PIN_B20 _GPIO(160) -#define DB8500_PIN_D21 _GPIO(161) -#define DB8500_PIN_D20 _GPIO(162) -#define DB8500_PIN_C20 _GPIO(163) -#define DB8500_PIN_B21 _GPIO(164) -#define DB8500_PIN_C21 _GPIO(165) -#define DB8500_PIN_A22 _GPIO(166) -#define DB8500_PIN_B24 _GPIO(167) -#define DB8500_PIN_C22 _GPIO(168) -#define DB8500_PIN_D22 _GPIO(169) -#define DB8500_PIN_C23 _GPIO(170) -#define DB8500_PIN_D23 _GPIO(171) -/* Hole */ -#define DB8500_PIN_AJ27 _GPIO(192) -#define DB8500_PIN_AH27 _GPIO(193) -#define DB8500_PIN_AF27 _GPIO(194) -#define DB8500_PIN_AG28 _GPIO(195) -#define DB8500_PIN_AG26 _GPIO(196) -#define DB8500_PIN_AH24 _GPIO(197) -#define DB8500_PIN_AG25 _GPIO(198) -#define DB8500_PIN_AH23 _GPIO(199) -#define DB8500_PIN_AH26 _GPIO(200) -#define DB8500_PIN_AF24 _GPIO(201) -#define DB8500_PIN_AF25 _GPIO(202) -#define DB8500_PIN_AE23 _GPIO(203) -#define DB8500_PIN_AF23 _GPIO(204) -#define DB8500_PIN_AG23 _GPIO(205) -#define DB8500_PIN_AG24 _GPIO(206) -#define DB8500_PIN_AJ23 _GPIO(207) -#define DB8500_PIN_AH16 _GPIO(208) -#define DB8500_PIN_AG15 _GPIO(209) -#define DB8500_PIN_AJ15 _GPIO(210) -#define DB8500_PIN_AG14 _GPIO(211) -#define DB8500_PIN_AF13 _GPIO(212) -#define DB8500_PIN_AG13 _GPIO(213) -#define DB8500_PIN_AH15 _GPIO(214) -#define DB8500_PIN_AH13 _GPIO(215) -#define DB8500_PIN_AG12 _GPIO(216) -#define DB8500_PIN_AH12 _GPIO(217) -#define DB8500_PIN_AH11 _GPIO(218) -#define DB8500_PIN_AG10 _GPIO(219) -#define DB8500_PIN_AH10 _GPIO(220) -#define DB8500_PIN_AJ11 _GPIO(221) -#define DB8500_PIN_AJ9 _GPIO(222) -#define DB8500_PIN_AH9 _GPIO(223) -#define DB8500_PIN_AG9 _GPIO(224) -#define DB8500_PIN_AG8 _GPIO(225) -#define DB8500_PIN_AF8 _GPIO(226) -#define DB8500_PIN_AH7 _GPIO(227) -#define DB8500_PIN_AJ6 _GPIO(228) -#define DB8500_PIN_AG7 _GPIO(229) -#define DB8500_PIN_AF7 _GPIO(230) -/* Hole */ -#define DB8500_PIN_AF28 _GPIO(256) -#define DB8500_PIN_AE29 _GPIO(257) -#define DB8500_PIN_AD29 _GPIO(258) -#define DB8500_PIN_AC29 _GPIO(259) -#define DB8500_PIN_AD28 _GPIO(260) -#define DB8500_PIN_AD26 _GPIO(261) -#define DB8500_PIN_AE26 _GPIO(262) -#define DB8500_PIN_AG29 _GPIO(263) -#define DB8500_PIN_AE27 _GPIO(264) -#define DB8500_PIN_AD27 _GPIO(265) -#define DB8500_PIN_AC28 _GPIO(266) -#define DB8500_PIN_AC27 _GPIO(267) - -/* - * The names of the pins are denoted by GPIO number and ball name, even - * though they can be used for other things than GPIO, this is the first - * column in the table of the data sheet and often used on schematics and - * such. - */ -static const struct pinctrl_pin_desc nmk_db8500_pins[] = { - PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"), - PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"), - PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"), - PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"), - PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"), - PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"), - PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"), - PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"), - PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"), - PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"), - PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"), - PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"), - PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"), - PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"), - PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"), - PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"), - PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"), - PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"), - PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"), - PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"), - PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"), - PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"), - PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"), - PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"), - PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"), - PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"), - PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"), - PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"), - PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"), - PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"), - PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"), - PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"), - PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"), - PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"), - PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"), - PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"), - PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"), - /* Hole */ - PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"), - PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"), - PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"), - PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"), - PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"), - PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"), - PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"), - PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"), - PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"), - PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"), - PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"), - PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"), - PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"), - PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"), - PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"), - PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"), - PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"), - PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"), - PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"), - PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"), - PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"), - PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"), - PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"), - PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"), - PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"), - PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"), - PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"), - PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"), - PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"), - PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"), - PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"), - PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"), - PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"), - PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"), - /* Hole */ - PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"), - PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"), - PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"), - PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"), - PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"), - PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"), - PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"), - PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"), - PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"), - PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"), - PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"), - PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"), - PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"), - PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"), - PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"), - PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"), - PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"), - PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"), - PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"), - PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"), - PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"), - PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"), - PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"), - PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"), - PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"), - PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"), - PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"), - PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"), - PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"), - PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"), - PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"), - PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"), - PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"), - PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"), - PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"), - PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"), - PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"), - PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"), - PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"), - PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"), - PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"), - PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"), - PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"), - PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"), - /* Hole */ - PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"), - PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"), - PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"), - PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"), - PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"), - PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"), - PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"), - PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"), - PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"), - PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"), - PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"), - PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"), - PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"), - PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"), - PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"), - PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"), - PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"), - PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"), - PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"), - PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"), - PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"), - PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"), - PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"), - PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"), - PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"), - PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"), - PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"), - PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"), - PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"), - PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"), - PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"), - PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"), - PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"), - PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"), - PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"), - PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"), - PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"), - PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"), - PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"), - /* Hole */ - PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"), - PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"), - PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"), - PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"), - PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"), - PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"), - PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"), - PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"), - PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"), - PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"), - PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"), - PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"), -}; - -#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \ - .pin_base = b, .npins = c } - -/* - * This matches the 32-pin gpio chips registered by the GPIO portion. This - * cannot be const since we assign the struct gpio_chip * pointer at runtime. - */ -static struct pinctrl_gpio_range nmk_db8500_ranges[] = { - DB8500_GPIO_RANGE(0, 0, 32), - DB8500_GPIO_RANGE(1, 32, 5), - DB8500_GPIO_RANGE(2, 64, 32), - DB8500_GPIO_RANGE(3, 96, 2), - DB8500_GPIO_RANGE(4, 128, 32), - DB8500_GPIO_RANGE(5, 160, 12), - DB8500_GPIO_RANGE(6, 192, 32), - DB8500_GPIO_RANGE(7, 224, 7), - DB8500_GPIO_RANGE(8, 256, 12), -}; - -/* - * Read the pin group names like this: - * u0_a_1 = first groups of pins for uart0 on alt function a - * i2c2_b_2 = second group of pins for i2c2 on alt function b - * - * The groups are arranged as sets per altfunction column, so we can - * mux in one group at a time by selecting the same altfunction for them - * all. When functions require pins on different altfunctions, you need - * to combine several groups. - */ - -/* Altfunction A column */ -static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, - DB8500_PIN_AH4, DB8500_PIN_AH3 }; -static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; -static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; -/* Image processor I2C line, this is driven by image processor firmware */ -static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; -static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; -/* MSP0 can only be on these pins, but TXD and RXD can be flipped */ -static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; -static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 }; -static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; -/* Basic pins of the MMC/SD card 0 interface */ -static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, - DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, - DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; -/* Often only 4 bits are used, then these are not needed (only used for MMC) */ -static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, - DB8500_PIN_V3, DB8500_PIN_V2}; -static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 }; -/* MSP1 can only be on these pins, but TXD and RXD can be flipped */ -static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; -static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 }; -/* LCD interface */ -static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, - DB8500_PIN_G3, DB8500_PIN_G2 }; -static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 }; -static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 }; -static const unsigned lcd_d0_d7_a_1_pins[] = { - DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, - DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 }; -/* D8 thru D11 often used as TVOUT lines */ -static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4, - DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 }; -static const unsigned lcd_d12_d23_a_1_pins[] = { - DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5, - DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6, - DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 }; -static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8, - DB8500_PIN_D8, DB8500_PIN_D9 }; -static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 }; -static const unsigned kp_a_2_pins[] = { - DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, - DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; -/* MC2 has 8 data lines and no direction control, so only for (e)MMC */ -static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4, - DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, - DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, - DB8500_PIN_C5 }; -static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, - DB8500_PIN_C12, DB8500_PIN_C11 }; -static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13, - DB8500_PIN_C13, DB8500_PIN_D13 }; -static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 }; -/* - * Image processor GPIO pins are named "ipgpio" and have their own - * numberspace - */ -static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 }; -static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 }; -/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */ -static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23, - DB8500_PIN_D23 }; -/* - * This MSP cannot switch RX and TX, SCK in a separate group since this - * seems to be optional. - */ -static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 }; -static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27, - DB8500_PIN_AG28, DB8500_PIN_AG26 }; -static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25, - DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25, - DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24, - DB8500_PIN_AJ23 }; -/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */ -static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15, - DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, - DB8500_PIN_AH15 }; -static const unsigned mc1_a_2_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AJ15, - DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, DB8500_PIN_AH15 }; -static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, - DB8500_PIN_AH12, DB8500_PIN_AH11 }; -static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10, - DB8500_PIN_AJ11 }; -static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ9, DB8500_PIN_AH9, - DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 }; -static const unsigned hsit_a_2_pins[] = { DB8500_PIN_AJ9, DB8500_PIN_AH9, - DB8500_PIN_AG9, DB8500_PIN_AG8 }; -static const unsigned clkout1_a_1_pins[] = { DB8500_PIN_AH7 }; -static const unsigned clkout1_a_2_pins[] = { DB8500_PIN_AG7 }; -static const unsigned clkout2_a_1_pins[] = { DB8500_PIN_AJ6 }; -static const unsigned clkout2_a_2_pins[] = { DB8500_PIN_AF7 }; -static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29, - DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26, - DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27, - DB8500_PIN_AC28, DB8500_PIN_AC27 }; - -/* Altfunction B column */ -static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 }; -static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; -static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; -static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; -static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; -static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; -static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; -/* Just RX and TX for UART2 */ -static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 }; -static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 }; -static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 }; -static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 }; -static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4, - DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; -static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 }; -static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, - DB8500_PIN_V3, DB8500_PIN_V2 }; -static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; -static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, - DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2, - DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, - DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1, - DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2, - DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 }; -static const unsigned kp_b_2_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, - DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_F4, DB8500_PIN_E3}; -static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, - DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, - DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, - DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8, - DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9, - DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5, - DB8500_PIN_C9 }; -/* This chip select pin can be "ps0" in alt C so have it separately */ -static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 }; -/* This chip select pin can be "ps1" in alt C so have it separately */ -static const unsigned smcs1_b_1_pins[] = { DB8500_PIN_B14 }; -static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 }; -static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 }; -static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 }; -static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 }; -static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22, - DB8500_PIN_C23, DB8500_PIN_D23 }; -static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, - DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, - DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; -static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 }; -static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 }; -static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13, - DB8500_PIN_AG13, DB8500_PIN_AH15 }; -static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, - DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10, - DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9, - DB8500_PIN_AG8 }; -static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 }; -static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 }; -static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 }; - -/* Altfunction C column */ -static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, - DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 }; -static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 }; -static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 }; -static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 }; -static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 }; -static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 }; -static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; -/* Optional 4-bit Memory Stick interface */ -static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, - DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, - DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; -static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 }; -static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 }; -static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 }; -static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1, - DB8500_PIN_AE2, DB8500_PIN_AG2 }; -static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 }; -static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 }; -static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 }; -static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 }; -static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 }; -static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, - DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 }; -static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 }; -static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 }; -static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 }; -static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 }; -static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 }; -static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, - DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, - DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, - DB8500_PIN_D9 }; -static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 }; -static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, - DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16, - DB8500_PIN_C23, DB8500_PIN_D23 }; -static const unsigned smps0_c_1_pins[] = { DB8500_PIN_E8 }; -static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 }; -static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 }; -static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 }; -static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 }; -static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 }; -static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 }; -static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 }; -static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 }; -static const unsigned clkout1_c_1_pins[] = { DB8500_PIN_AH13 }; -static const unsigned clkout2_c_1_pins[] = { DB8500_PIN_AH12 }; -static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 }; -static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9, - DB8500_PIN_AG9, DB8500_PIN_AG8 }; -static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 }; -static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; - -/* Other C1 column */ -static const unsigned u2rx_oc1_1_pins[] = { DB8500_PIN_AB2 }; -static const unsigned stmape_oc1_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4, - DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; -static const unsigned remap0_oc1_1_pins[] = { DB8500_PIN_E1 }; -static const unsigned remap1_oc1_1_pins[] = { DB8500_PIN_E2 }; -static const unsigned ptma9_oc1_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, - DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H2, - DB8500_PIN_J2, DB8500_PIN_H1 }; -static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, - DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, - DB8500_PIN_D6, DB8500_PIN_B7 }; -static const unsigned rf_oc1_1_pins[] = { DB8500_PIN_D8, DB8500_PIN_D9 }; -static const unsigned hxclk_oc1_1_pins[] = { DB8500_PIN_D16 }; -static const unsigned uartmodrx_oc1_1_pins[] = { DB8500_PIN_B17 }; -static const unsigned uartmodtx_oc1_1_pins[] = { DB8500_PIN_C16 }; -static const unsigned stmmod_oc1_1_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 }; -static const unsigned hxgpio_oc1_1_pins[] = { DB8500_PIN_D21, DB8500_PIN_D20, - DB8500_PIN_C20, DB8500_PIN_B21, DB8500_PIN_C21, DB8500_PIN_A22, - DB8500_PIN_B24, DB8500_PIN_C22 }; -static const unsigned rf_oc1_2_pins[] = { DB8500_PIN_C23, DB8500_PIN_D23 }; -static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, - DB8500_PIN_AH12, DB8500_PIN_AH11 }; -static const unsigned spi2_oc1_2_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12, - DB8500_PIN_AH11 }; - -/* Other C2 column */ -static const unsigned sbag_oc2_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_AB2, - DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; -static const unsigned etmr4_oc2_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, - DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H2, - DB8500_PIN_J2, DB8500_PIN_H1 }; -static const unsigned ptma9_oc2_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, - DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, - DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; - -/* Other C3 column */ -static const unsigned stmmod_oc3_1_pins[] = { DB8500_PIN_AB2, DB8500_PIN_W2, - DB8500_PIN_W3, DB8500_PIN_V3, DB8500_PIN_V2 }; -static const unsigned stmmod_oc3_2_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, - DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 }; -static const unsigned uartmodrx_oc3_1_pins[] = { DB8500_PIN_H2 }; -static const unsigned uartmodtx_oc3_1_pins[] = { DB8500_PIN_J2 }; -static const unsigned etmr4_oc3_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, - DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, - DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; - -/* Other C4 column */ -static const unsigned sbag_oc4_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, - DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3, DB8500_PIN_H1 }; -static const unsigned hwobs_oc4_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, - DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, - DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, - DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, - DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; - -#define DB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ - .npins = ARRAY_SIZE(a##_pins), .altsetting = b } - -static const struct nmk_pingroup nmk_db8500_groups[] = { - /* Altfunction A column */ - DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc0_dat47_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc0dat31dir_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(kp_a_2, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(clkout1_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(clkout1_a_2, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(clkout2_a_1, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(clkout2_a_2, NMK_GPIO_ALT_A), - DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A), - /* Altfunction B column */ - DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(kp_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B), - DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B), - /* Altfunction C column */ - DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(clkout1_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(clkout2_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C), - /* Other alt C1 column */ - DB8500_PIN_GROUP(u2rx_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(ptma9_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(rf_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(hxclk_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(uartmodrx_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(uartmodtx_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(stmmod_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(hxgpio_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(rf_oc1_2, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C1), - DB8500_PIN_GROUP(spi2_oc1_2, NMK_GPIO_ALT_C1), - /* Other alt C2 column */ - DB8500_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2), - DB8500_PIN_GROUP(etmr4_oc2_1, NMK_GPIO_ALT_C2), - DB8500_PIN_GROUP(ptma9_oc2_1, NMK_GPIO_ALT_C2), - /* Other alt C3 column */ - DB8500_PIN_GROUP(stmmod_oc3_1, NMK_GPIO_ALT_C3), - DB8500_PIN_GROUP(stmmod_oc3_2, NMK_GPIO_ALT_C3), - DB8500_PIN_GROUP(uartmodrx_oc3_1, NMK_GPIO_ALT_C3), - DB8500_PIN_GROUP(uartmodtx_oc3_1, NMK_GPIO_ALT_C3), - DB8500_PIN_GROUP(etmr4_oc3_1, NMK_GPIO_ALT_C3), - /* Other alt C4 column */ - DB8500_PIN_GROUP(sbag_oc4_1, NMK_GPIO_ALT_C4), - DB8500_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4), -}; - -/* We use this macro to define the groups applicable to a function */ -#define DB8500_FUNC_GROUPS(a, b...) \ -static const char * const a##_groups[] = { b }; - -DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1"); -DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1"); -/* - * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however - * only available on two pins in alternative function C - */ -DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1", - "u2rxtx_c_2", "u2rxtx_c_3", "u2rx_oc1_1"); -DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2"); -/* - * MSP0 can only be on a certain set of pins, but the TX/RX pins can be - * switched around by selecting the altfunction A or B. The SCK pin is - * only available on the altfunction B. - */ -DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1", - "msp0txrx_b_1", "msp0sck_b_1"); -DB8500_FUNC_GROUPS(mc0, "mc0_a_1", "mc0_dat47_a_1", "mc0dat31dir_a_1"); -/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */ -DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1"); -DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1"); -DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1", - "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1"); -DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_a_2", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1"); -DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); -DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1"); -DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1"); -DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1"); -/* The image processor has 8 GPIO pins that can be muxed out */ -DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1", - "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1", - "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1", - "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2", - "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2"); -/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */ -DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1"); -DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); -DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2", "mc1dir_a_1"); -DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2"); -DB8500_FUNC_GROUPS(clkout, "clkout1_a_1", "clkout1_a_2", "clkout1_c_1", - "clkout2_a_1", "clkout2_a_2", "clkout2_c_1"); -DB8500_FUNC_GROUPS(usb, "usb_a_1"); -DB8500_FUNC_GROUPS(trig, "trig_b_1"); -DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1"); -DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2"); -DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2"); -/* - * The modem UART can output its RX and TX pins in some different places, - * so select one of each. - */ -DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2", - "uartmodrx_c_1", "uartmod_tx_c_1", "uartmodrx_oc1_1", - "uartmodtx_oc1_1", "uartmodrx_oc3_1", "uartmodtx_oc3_1"); -DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1", "stmmod_oc1_1", - "stmmod_oc3_1", "stmmod_oc3_2"); -DB8500_FUNC_GROUPS(spi3, "spi3_b_1"); -/* Select between CS0 on alt B or PS1 on alt C */ -DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcs1_b_1", "smcleale_c_1", - "smps0_c_1", "smps1_c_1"); -DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1"); -DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1"); -DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4"); -DB8500_FUNC_GROUPS(spi1, "spi1_b_1"); -DB8500_FUNC_GROUPS(mc3, "mc3_b_1"); -DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1"); -DB8500_FUNC_GROUPS(slim0, "slim0_c_1"); -DB8500_FUNC_GROUPS(ms, "ms_c_1"); -DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1"); -DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2", "stmape_oc1_1"); -DB8500_FUNC_GROUPS(mc5, "mc5_c_1"); -DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2"); -DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2"); -DB8500_FUNC_GROUPS(spi0, "spi0_c_1"); -DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1", "spi2_oc1_2"); -DB8500_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1"); -DB8500_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc4_1"); -DB8500_FUNC_GROUPS(ptm, "ptma9_oc1_1", "ptma9_oc2_1"); -DB8500_FUNC_GROUPS(rf, "rf_oc1_1", "rf_oc1_2"); -DB8500_FUNC_GROUPS(hx, "hxclk_oc1_1", "hxgpio_oc1_1"); -DB8500_FUNC_GROUPS(etm, "etmr4_oc2_1", "etmr4_oc3_1"); -DB8500_FUNC_GROUPS(hwobs, "hwobs_oc4_1"); -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -static const struct nmk_function nmk_db8500_functions[] = { - FUNCTION(u0), - FUNCTION(u1), - FUNCTION(u2), - FUNCTION(ipi2c), - FUNCTION(msp0), - FUNCTION(mc0), - FUNCTION(msp1), - FUNCTION(lcdb), - FUNCTION(lcd), - FUNCTION(kp), - FUNCTION(mc2), - FUNCTION(ssp1), - FUNCTION(ssp0), - FUNCTION(i2c0), - FUNCTION(ipgpio), - FUNCTION(msp2), - FUNCTION(mc4), - FUNCTION(mc1), - FUNCTION(hsi), - FUNCTION(clkout), - FUNCTION(usb), - FUNCTION(trig), - FUNCTION(i2c4), - FUNCTION(i2c1), - FUNCTION(i2c2), - FUNCTION(uartmod), - FUNCTION(stmmod), - FUNCTION(spi3), - FUNCTION(sm), - FUNCTION(lcda), - FUNCTION(ddrtrig), - FUNCTION(pwl), - FUNCTION(spi1), - FUNCTION(mc3), - FUNCTION(ipjtag), - FUNCTION(slim0), - FUNCTION(ms), - FUNCTION(iptrigout), - FUNCTION(stmape), - FUNCTION(mc5), - FUNCTION(usbsim), - FUNCTION(i2c3), - FUNCTION(spi0), - FUNCTION(spi2), - FUNCTION(remap), - FUNCTION(ptm), - FUNCTION(rf), - FUNCTION(hx), - FUNCTION(etm), - FUNCTION(hwobs), -}; - -static const struct prcm_gpiocr_altcx_pin_desc db8500_altcx_pins[] = { - PRCM_GPIOCR_ALTCX(23, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_CLK_a */ - true, PRCM_IDX_GPIOCR1, 7, /* SBAG_CLK_a */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(24, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE or U2_RXD ??? */ - true, PRCM_IDX_GPIOCR1, 7, /* SBAG_VAL_a */ - true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(25, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[0] */ - true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[0] */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(26, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[1] */ - true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[1] */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(27, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[2] */ - true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[2] */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(28, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[3] */ - true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[3] */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(29, false, 0, 0, - false, 0, 0, - true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(30, false, 0, 0, - false, 0, 0, - true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(31, false, 0, 0, - false, 0, 0, - true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(32, false, 0, 0, - false, 0, 0, - true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(68, true, PRCM_IDX_GPIOCR1, 18, /* REMAP_SELECT_ON */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(69, true, PRCM_IDX_GPIOCR1, 18, /* REMAP_SELECT_ON */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(70, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D23 */ - true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ - true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ - true, PRCM_IDX_GPIOCR1, 8 /* SBAG_CLK */ - ), - PRCM_GPIOCR_ALTCX(71, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D22 */ - true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ - true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ - true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D3 */ - ), - PRCM_GPIOCR_ALTCX(72, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D21 */ - true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ - true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ - true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D2 */ - ), - PRCM_GPIOCR_ALTCX(73, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D20 */ - true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ - true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ - true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D1 */ - ), - PRCM_GPIOCR_ALTCX(74, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D19 */ - true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ - true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */ - true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D0 */ - ), - PRCM_GPIOCR_ALTCX(75, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D18 */ - true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ - true, PRCM_IDX_GPIOCR1, 0, /* DBG_UARTMOD_CMD0 */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(76, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D17 */ - true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ - true, PRCM_IDX_GPIOCR1, 0, /* DBG_UARTMOD_CMD0 */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(77, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D16 */ - true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */ - false, 0, 0, - true, PRCM_IDX_GPIOCR1, 8 /* SBAG_VAL */ - ), - PRCM_GPIOCR_ALTCX(86, true, PRCM_IDX_GPIOCR1, 12, /* KP_O3 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(87, true, PRCM_IDX_GPIOCR1, 12, /* KP_O2 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(88, true, PRCM_IDX_GPIOCR1, 12, /* KP_I3 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(89, true, PRCM_IDX_GPIOCR1, 12, /* KP_I2 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(90, true, PRCM_IDX_GPIOCR1, 12, /* KP_O1 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(91, true, PRCM_IDX_GPIOCR1, 12, /* KP_O0 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(92, true, PRCM_IDX_GPIOCR1, 12, /* KP_I1 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(93, true, PRCM_IDX_GPIOCR1, 12, /* KP_I0 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(96, true, PRCM_IDX_GPIOCR2, 3, /* RF_INT */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(97, true, PRCM_IDX_GPIOCR2, 1, /* RF_CTRL */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(151, false, 0, 0, - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_CTL */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS17 */ - ), - PRCM_GPIOCR_ALTCX(152, true, PRCM_IDX_GPIOCR1, 4, /* Hx_CLK */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_CLK */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS16 */ - ), - PRCM_GPIOCR_ALTCX(153, true, PRCM_IDX_GPIOCR1, 1, /* UARTMOD_CMD1 */ - true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D15 */ - true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS15 */ - ), - PRCM_GPIOCR_ALTCX(154, true, PRCM_IDX_GPIOCR1, 1, /* UARTMOD_CMD1 */ - true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D14 */ - true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS14 */ - ), - PRCM_GPIOCR_ALTCX(155, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ - true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D13 */ - true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS13 */ - ), - PRCM_GPIOCR_ALTCX(156, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ - true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D12 */ - true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS12 */ - ), - PRCM_GPIOCR_ALTCX(157, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ - true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D11 */ - true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS11 */ - ), - PRCM_GPIOCR_ALTCX(158, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ - true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D10 */ - true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS10 */ - ), - PRCM_GPIOCR_ALTCX(159, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */ - true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D9 */ - true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS9 */ - ), - PRCM_GPIOCR_ALTCX(160, false, 0, 0, - true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D8 */ - true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */ - true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS8 */ - ), - PRCM_GPIOCR_ALTCX(161, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO7 */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D7 */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS7 */ - ), - PRCM_GPIOCR_ALTCX(162, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO6 */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D6 */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS6 */ - ), - PRCM_GPIOCR_ALTCX(163, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO5 */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D5 */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS5 */ - ), - PRCM_GPIOCR_ALTCX(164, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO4 */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D4 */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS4 */ - ), - PRCM_GPIOCR_ALTCX(165, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO3 */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D3 */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS3 */ - ), - PRCM_GPIOCR_ALTCX(166, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO2 */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D2 */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS2 */ - ), - PRCM_GPIOCR_ALTCX(167, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO1 */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D1 */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS1 */ - ), - PRCM_GPIOCR_ALTCX(168, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO0 */ - true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D0 */ - true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/ - true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS0 */ - ), - PRCM_GPIOCR_ALTCX(170, true, PRCM_IDX_GPIOCR2, 2, /* RF_INT */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(171, true, PRCM_IDX_GPIOCR2, 0, /* RF_CTRL */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(215, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_TXD */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(216, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_FRM */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(217, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_CLK */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(218, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_RXD */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), -}; - -static const u16 db8500_prcm_gpiocr_regs[] = { - [PRCM_IDX_GPIOCR1] = 0x138, - [PRCM_IDX_GPIOCR2] = 0x574, -}; - -static const struct nmk_pinctrl_soc_data nmk_db8500_soc = { - .gpio_ranges = nmk_db8500_ranges, - .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges), - .pins = nmk_db8500_pins, - .npins = ARRAY_SIZE(nmk_db8500_pins), - .functions = nmk_db8500_functions, - .nfunctions = ARRAY_SIZE(nmk_db8500_functions), - .groups = nmk_db8500_groups, - .ngroups = ARRAY_SIZE(nmk_db8500_groups), - .altcx_pins = db8500_altcx_pins, - .npins_altcx = ARRAY_SIZE(db8500_altcx_pins), - .prcm_gpiocr_registers = db8500_prcm_gpiocr_regs, -}; - -void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) -{ - *soc = &nmk_db8500_soc; -} diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/pinctrl-nomadik-db8540.c deleted file mode 100644 index d7ba5443bae0..000000000000 --- a/drivers/pinctrl/pinctrl-nomadik-db8540.c +++ /dev/null @@ -1,1266 +0,0 @@ -#include -#include -#include "pinctrl-nomadik.h" - -/* All the pins that can be used for GPIO and some other functions */ -#define _GPIO(offset) (offset) - -#define DB8540_PIN_AH6 _GPIO(0) -#define DB8540_PIN_AG7 _GPIO(1) -#define DB8540_PIN_AF2 _GPIO(2) -#define DB8540_PIN_AD3 _GPIO(3) -#define DB8540_PIN_AF6 _GPIO(4) -#define DB8540_PIN_AG6 _GPIO(5) -#define DB8540_PIN_AD5 _GPIO(6) -#define DB8540_PIN_AF7 _GPIO(7) -#define DB8540_PIN_AG5 _GPIO(8) -#define DB8540_PIN_AH5 _GPIO(9) -#define DB8540_PIN_AE4 _GPIO(10) -#define DB8540_PIN_AD1 _GPIO(11) -#define DB8540_PIN_AD2 _GPIO(12) -#define DB8540_PIN_AC2 _GPIO(13) -#define DB8540_PIN_AC4 _GPIO(14) -#define DB8540_PIN_AC3 _GPIO(15) -#define DB8540_PIN_AH7 _GPIO(16) -#define DB8540_PIN_AE7 _GPIO(17) -/* Hole */ -#define DB8540_PIN_AF8 _GPIO(22) -#define DB8540_PIN_AH11 _GPIO(23) -#define DB8540_PIN_AG11 _GPIO(24) -#define DB8540_PIN_AF11 _GPIO(25) -#define DB8540_PIN_AH10 _GPIO(26) -#define DB8540_PIN_AG10 _GPIO(27) -#define DB8540_PIN_AF10 _GPIO(28) -/* Hole */ -#define DB8540_PIN_AD4 _GPIO(33) -#define DB8540_PIN_AF3 _GPIO(34) -#define DB8540_PIN_AF5 _GPIO(35) -#define DB8540_PIN_AG4 _GPIO(36) -#define DB8540_PIN_AF9 _GPIO(37) -#define DB8540_PIN_AE8 _GPIO(38) -/* Hole */ -#define DB8540_PIN_M26 _GPIO(64) -#define DB8540_PIN_M25 _GPIO(65) -#define DB8540_PIN_M27 _GPIO(66) -#define DB8540_PIN_N25 _GPIO(67) -/* Hole */ -#define DB8540_PIN_M28 _GPIO(70) -#define DB8540_PIN_N26 _GPIO(71) -#define DB8540_PIN_M22 _GPIO(72) -#define DB8540_PIN_N22 _GPIO(73) -#define DB8540_PIN_N27 _GPIO(74) -#define DB8540_PIN_N28 _GPIO(75) -#define DB8540_PIN_P22 _GPIO(76) -#define DB8540_PIN_P28 _GPIO(77) -#define DB8540_PIN_P26 _GPIO(78) -#define DB8540_PIN_T22 _GPIO(79) -#define DB8540_PIN_R27 _GPIO(80) -#define DB8540_PIN_P27 _GPIO(81) -#define DB8540_PIN_R26 _GPIO(82) -#define DB8540_PIN_R25 _GPIO(83) -#define DB8540_PIN_U22 _GPIO(84) -#define DB8540_PIN_T27 _GPIO(85) -#define DB8540_PIN_T25 _GPIO(86) -#define DB8540_PIN_T26 _GPIO(87) -/* Hole */ -#define DB8540_PIN_AF20 _GPIO(116) -#define DB8540_PIN_AG21 _GPIO(117) -#define DB8540_PIN_AH19 _GPIO(118) -#define DB8540_PIN_AE19 _GPIO(119) -#define DB8540_PIN_AG18 _GPIO(120) -#define DB8540_PIN_AH17 _GPIO(121) -#define DB8540_PIN_AF19 _GPIO(122) -#define DB8540_PIN_AF18 _GPIO(123) -#define DB8540_PIN_AE18 _GPIO(124) -#define DB8540_PIN_AG17 _GPIO(125) -#define DB8540_PIN_AF17 _GPIO(126) -#define DB8540_PIN_AE17 _GPIO(127) -#define DB8540_PIN_AC27 _GPIO(128) -#define DB8540_PIN_AD27 _GPIO(129) -#define DB8540_PIN_AE28 _GPIO(130) -#define DB8540_PIN_AG26 _GPIO(131) -#define DB8540_PIN_AF25 _GPIO(132) -#define DB8540_PIN_AE27 _GPIO(133) -#define DB8540_PIN_AF27 _GPIO(134) -#define DB8540_PIN_AG28 _GPIO(135) -#define DB8540_PIN_AF28 _GPIO(136) -#define DB8540_PIN_AG25 _GPIO(137) -#define DB8540_PIN_AG24 _GPIO(138) -#define DB8540_PIN_AD25 _GPIO(139) -#define DB8540_PIN_AH25 _GPIO(140) -#define DB8540_PIN_AF26 _GPIO(141) -#define DB8540_PIN_AF23 _GPIO(142) -#define DB8540_PIN_AG23 _GPIO(143) -#define DB8540_PIN_AE25 _GPIO(144) -#define DB8540_PIN_AH24 _GPIO(145) -#define DB8540_PIN_AJ25 _GPIO(146) -#define DB8540_PIN_AG27 _GPIO(147) -#define DB8540_PIN_AH23 _GPIO(148) -#define DB8540_PIN_AE26 _GPIO(149) -#define DB8540_PIN_AE24 _GPIO(150) -#define DB8540_PIN_AJ24 _GPIO(151) -#define DB8540_PIN_AE21 _GPIO(152) -#define DB8540_PIN_AG22 _GPIO(153) -#define DB8540_PIN_AF21 _GPIO(154) -#define DB8540_PIN_AF24 _GPIO(155) -#define DB8540_PIN_AH22 _GPIO(156) -#define DB8540_PIN_AJ23 _GPIO(157) -#define DB8540_PIN_AH21 _GPIO(158) -#define DB8540_PIN_AG20 _GPIO(159) -#define DB8540_PIN_AE23 _GPIO(160) -#define DB8540_PIN_AH20 _GPIO(161) -#define DB8540_PIN_AG19 _GPIO(162) -#define DB8540_PIN_AF22 _GPIO(163) -#define DB8540_PIN_AJ21 _GPIO(164) -#define DB8540_PIN_AD26 _GPIO(165) -#define DB8540_PIN_AD28 _GPIO(166) -#define DB8540_PIN_AC28 _GPIO(167) -#define DB8540_PIN_AC26 _GPIO(168) -/* Hole */ -#define DB8540_PIN_J3 _GPIO(192) -#define DB8540_PIN_H1 _GPIO(193) -#define DB8540_PIN_J2 _GPIO(194) -#define DB8540_PIN_H2 _GPIO(195) -#define DB8540_PIN_H3 _GPIO(196) -#define DB8540_PIN_H4 _GPIO(197) -#define DB8540_PIN_G2 _GPIO(198) -#define DB8540_PIN_G3 _GPIO(199) -#define DB8540_PIN_G4 _GPIO(200) -#define DB8540_PIN_F2 _GPIO(201) -#define DB8540_PIN_C6 _GPIO(202) -#define DB8540_PIN_B6 _GPIO(203) -#define DB8540_PIN_B7 _GPIO(204) -#define DB8540_PIN_A7 _GPIO(205) -#define DB8540_PIN_D7 _GPIO(206) -#define DB8540_PIN_D8 _GPIO(207) -#define DB8540_PIN_F3 _GPIO(208) -#define DB8540_PIN_E2 _GPIO(209) -#define DB8540_PIN_C7 _GPIO(210) -#define DB8540_PIN_B8 _GPIO(211) -#define DB8540_PIN_C10 _GPIO(212) -#define DB8540_PIN_C8 _GPIO(213) -#define DB8540_PIN_C9 _GPIO(214) -/* Hole */ -#define DB8540_PIN_B9 _GPIO(219) -#define DB8540_PIN_A10 _GPIO(220) -#define DB8540_PIN_D9 _GPIO(221) -#define DB8540_PIN_B11 _GPIO(222) -#define DB8540_PIN_B10 _GPIO(223) -#define DB8540_PIN_E10 _GPIO(224) -#define DB8540_PIN_B12 _GPIO(225) -#define DB8540_PIN_D10 _GPIO(226) -#define DB8540_PIN_D11 _GPIO(227) -#define DB8540_PIN_AJ6 _GPIO(228) -#define DB8540_PIN_B13 _GPIO(229) -#define DB8540_PIN_C12 _GPIO(230) -#define DB8540_PIN_B14 _GPIO(231) -#define DB8540_PIN_E11 _GPIO(232) -/* Hole */ -#define DB8540_PIN_D12 _GPIO(256) -#define DB8540_PIN_D15 _GPIO(257) -#define DB8540_PIN_C13 _GPIO(258) -#define DB8540_PIN_C14 _GPIO(259) -#define DB8540_PIN_C18 _GPIO(260) -#define DB8540_PIN_C16 _GPIO(261) -#define DB8540_PIN_B16 _GPIO(262) -#define DB8540_PIN_D18 _GPIO(263) -#define DB8540_PIN_C15 _GPIO(264) -#define DB8540_PIN_C17 _GPIO(265) -#define DB8540_PIN_B17 _GPIO(266) -#define DB8540_PIN_D17 _GPIO(267) - -/* - * The names of the pins are denoted by GPIO number and ball name, even - * though they can be used for other things than GPIO, this is the first - * column in the table of the data sheet and often used on schematics and - * such. - */ -static const struct pinctrl_pin_desc nmk_db8540_pins[] = { - PINCTRL_PIN(DB8540_PIN_AH6, "GPIO0_AH6"), - PINCTRL_PIN(DB8540_PIN_AG7, "GPIO1_AG7"), - PINCTRL_PIN(DB8540_PIN_AF2, "GPIO2_AF2"), - PINCTRL_PIN(DB8540_PIN_AD3, "GPIO3_AD3"), - PINCTRL_PIN(DB8540_PIN_AF6, "GPIO4_AF6"), - PINCTRL_PIN(DB8540_PIN_AG6, "GPIO5_AG6"), - PINCTRL_PIN(DB8540_PIN_AD5, "GPIO6_AD5"), - PINCTRL_PIN(DB8540_PIN_AF7, "GPIO7_AF7"), - PINCTRL_PIN(DB8540_PIN_AG5, "GPIO8_AG5"), - PINCTRL_PIN(DB8540_PIN_AH5, "GPIO9_AH5"), - PINCTRL_PIN(DB8540_PIN_AE4, "GPIO10_AE4"), - PINCTRL_PIN(DB8540_PIN_AD1, "GPIO11_AD1"), - PINCTRL_PIN(DB8540_PIN_AD2, "GPIO12_AD2"), - PINCTRL_PIN(DB8540_PIN_AC2, "GPIO13_AC2"), - PINCTRL_PIN(DB8540_PIN_AC4, "GPIO14_AC4"), - PINCTRL_PIN(DB8540_PIN_AC3, "GPIO15_AC3"), - PINCTRL_PIN(DB8540_PIN_AH7, "GPIO16_AH7"), - PINCTRL_PIN(DB8540_PIN_AE7, "GPIO17_AE7"), - /* Hole */ - PINCTRL_PIN(DB8540_PIN_AF8, "GPIO22_AF8"), - PINCTRL_PIN(DB8540_PIN_AH11, "GPIO23_AH11"), - PINCTRL_PIN(DB8540_PIN_AG11, "GPIO24_AG11"), - PINCTRL_PIN(DB8540_PIN_AF11, "GPIO25_AF11"), - PINCTRL_PIN(DB8540_PIN_AH10, "GPIO26_AH10"), - PINCTRL_PIN(DB8540_PIN_AG10, "GPIO27_AG10"), - PINCTRL_PIN(DB8540_PIN_AF10, "GPIO28_AF10"), - /* Hole */ - PINCTRL_PIN(DB8540_PIN_AD4, "GPIO33_AD4"), - PINCTRL_PIN(DB8540_PIN_AF3, "GPIO34_AF3"), - PINCTRL_PIN(DB8540_PIN_AF5, "GPIO35_AF5"), - PINCTRL_PIN(DB8540_PIN_AG4, "GPIO36_AG4"), - PINCTRL_PIN(DB8540_PIN_AF9, "GPIO37_AF9"), - PINCTRL_PIN(DB8540_PIN_AE8, "GPIO38_AE8"), - /* Hole */ - PINCTRL_PIN(DB8540_PIN_M26, "GPIO64_M26"), - PINCTRL_PIN(DB8540_PIN_M25, "GPIO65_M25"), - PINCTRL_PIN(DB8540_PIN_M27, "GPIO66_M27"), - PINCTRL_PIN(DB8540_PIN_N25, "GPIO67_N25"), - /* Hole */ - PINCTRL_PIN(DB8540_PIN_M28, "GPIO70_M28"), - PINCTRL_PIN(DB8540_PIN_N26, "GPIO71_N26"), - PINCTRL_PIN(DB8540_PIN_M22, "GPIO72_M22"), - PINCTRL_PIN(DB8540_PIN_N22, "GPIO73_N22"), - PINCTRL_PIN(DB8540_PIN_N27, "GPIO74_N27"), - PINCTRL_PIN(DB8540_PIN_N28, "GPIO75_N28"), - PINCTRL_PIN(DB8540_PIN_P22, "GPIO76_P22"), - PINCTRL_PIN(DB8540_PIN_P28, "GPIO77_P28"), - PINCTRL_PIN(DB8540_PIN_P26, "GPIO78_P26"), - PINCTRL_PIN(DB8540_PIN_T22, "GPIO79_T22"), - PINCTRL_PIN(DB8540_PIN_R27, "GPIO80_R27"), - PINCTRL_PIN(DB8540_PIN_P27, "GPIO81_P27"), - PINCTRL_PIN(DB8540_PIN_R26, "GPIO82_R26"), - PINCTRL_PIN(DB8540_PIN_R25, "GPIO83_R25"), - PINCTRL_PIN(DB8540_PIN_U22, "GPIO84_U22"), - PINCTRL_PIN(DB8540_PIN_T27, "GPIO85_T27"), - PINCTRL_PIN(DB8540_PIN_T25, "GPIO86_T25"), - PINCTRL_PIN(DB8540_PIN_T26, "GPIO87_T26"), - /* Hole */ - PINCTRL_PIN(DB8540_PIN_AF20, "GPIO116_AF20"), - PINCTRL_PIN(DB8540_PIN_AG21, "GPIO117_AG21"), - PINCTRL_PIN(DB8540_PIN_AH19, "GPIO118_AH19"), - PINCTRL_PIN(DB8540_PIN_AE19, "GPIO119_AE19"), - PINCTRL_PIN(DB8540_PIN_AG18, "GPIO120_AG18"), - PINCTRL_PIN(DB8540_PIN_AH17, "GPIO121_AH17"), - PINCTRL_PIN(DB8540_PIN_AF19, "GPIO122_AF19"), - PINCTRL_PIN(DB8540_PIN_AF18, "GPIO123_AF18"), - PINCTRL_PIN(DB8540_PIN_AE18, "GPIO124_AE18"), - PINCTRL_PIN(DB8540_PIN_AG17, "GPIO125_AG17"), - PINCTRL_PIN(DB8540_PIN_AF17, "GPIO126_AF17"), - PINCTRL_PIN(DB8540_PIN_AE17, "GPIO127_AE17"), - PINCTRL_PIN(DB8540_PIN_AC27, "GPIO128_AC27"), - PINCTRL_PIN(DB8540_PIN_AD27, "GPIO129_AD27"), - PINCTRL_PIN(DB8540_PIN_AE28, "GPIO130_AE28"), - PINCTRL_PIN(DB8540_PIN_AG26, "GPIO131_AG26"), - PINCTRL_PIN(DB8540_PIN_AF25, "GPIO132_AF25"), - PINCTRL_PIN(DB8540_PIN_AE27, "GPIO133_AE27"), - PINCTRL_PIN(DB8540_PIN_AF27, "GPIO134_AF27"), - PINCTRL_PIN(DB8540_PIN_AG28, "GPIO135_AG28"), - PINCTRL_PIN(DB8540_PIN_AF28, "GPIO136_AF28"), - PINCTRL_PIN(DB8540_PIN_AG25, "GPIO137_AG25"), - PINCTRL_PIN(DB8540_PIN_AG24, "GPIO138_AG24"), - PINCTRL_PIN(DB8540_PIN_AD25, "GPIO139_AD25"), - PINCTRL_PIN(DB8540_PIN_AH25, "GPIO140_AH25"), - PINCTRL_PIN(DB8540_PIN_AF26, "GPIO141_AF26"), - PINCTRL_PIN(DB8540_PIN_AF23, "GPIO142_AF23"), - PINCTRL_PIN(DB8540_PIN_AG23, "GPIO143_AG23"), - PINCTRL_PIN(DB8540_PIN_AE25, "GPIO144_AE25"), - PINCTRL_PIN(DB8540_PIN_AH24, "GPIO145_AH24"), - PINCTRL_PIN(DB8540_PIN_AJ25, "GPIO146_AJ25"), - PINCTRL_PIN(DB8540_PIN_AG27, "GPIO147_AG27"), - PINCTRL_PIN(DB8540_PIN_AH23, "GPIO148_AH23"), - PINCTRL_PIN(DB8540_PIN_AE26, "GPIO149_AE26"), - PINCTRL_PIN(DB8540_PIN_AE24, "GPIO150_AE24"), - PINCTRL_PIN(DB8540_PIN_AJ24, "GPIO151_AJ24"), - PINCTRL_PIN(DB8540_PIN_AE21, "GPIO152_AE21"), - PINCTRL_PIN(DB8540_PIN_AG22, "GPIO153_AG22"), - PINCTRL_PIN(DB8540_PIN_AF21, "GPIO154_AF21"), - PINCTRL_PIN(DB8540_PIN_AF24, "GPIO155_AF24"), - PINCTRL_PIN(DB8540_PIN_AH22, "GPIO156_AH22"), - PINCTRL_PIN(DB8540_PIN_AJ23, "GPIO157_AJ23"), - PINCTRL_PIN(DB8540_PIN_AH21, "GPIO158_AH21"), - PINCTRL_PIN(DB8540_PIN_AG20, "GPIO159_AG20"), - PINCTRL_PIN(DB8540_PIN_AE23, "GPIO160_AE23"), - PINCTRL_PIN(DB8540_PIN_AH20, "GPIO161_AH20"), - PINCTRL_PIN(DB8540_PIN_AG19, "GPIO162_AG19"), - PINCTRL_PIN(DB8540_PIN_AF22, "GPIO163_AF22"), - PINCTRL_PIN(DB8540_PIN_AJ21, "GPIO164_AJ21"), - PINCTRL_PIN(DB8540_PIN_AD26, "GPIO165_AD26"), - PINCTRL_PIN(DB8540_PIN_AD28, "GPIO166_AD28"), - PINCTRL_PIN(DB8540_PIN_AC28, "GPIO167_AC28"), - PINCTRL_PIN(DB8540_PIN_AC26, "GPIO168_AC26"), - /* Hole */ - PINCTRL_PIN(DB8540_PIN_J3, "GPIO192_J3"), - PINCTRL_PIN(DB8540_PIN_H1, "GPIO193_H1"), - PINCTRL_PIN(DB8540_PIN_J2, "GPIO194_J2"), - PINCTRL_PIN(DB8540_PIN_H2, "GPIO195_H2"), - PINCTRL_PIN(DB8540_PIN_H3, "GPIO196_H3"), - PINCTRL_PIN(DB8540_PIN_H4, "GPIO197_H4"), - PINCTRL_PIN(DB8540_PIN_G2, "GPIO198_G2"), - PINCTRL_PIN(DB8540_PIN_G3, "GPIO199_G3"), - PINCTRL_PIN(DB8540_PIN_G4, "GPIO200_G4"), - PINCTRL_PIN(DB8540_PIN_F2, "GPIO201_F2"), - PINCTRL_PIN(DB8540_PIN_C6, "GPIO202_C6"), - PINCTRL_PIN(DB8540_PIN_B6, "GPIO203_B6"), - PINCTRL_PIN(DB8540_PIN_B7, "GPIO204_B7"), - PINCTRL_PIN(DB8540_PIN_A7, "GPIO205_A7"), - PINCTRL_PIN(DB8540_PIN_D7, "GPIO206_D7"), - PINCTRL_PIN(DB8540_PIN_D8, "GPIO207_D8"), - PINCTRL_PIN(DB8540_PIN_F3, "GPIO208_F3"), - PINCTRL_PIN(DB8540_PIN_E2, "GPIO209_E2"), - PINCTRL_PIN(DB8540_PIN_C7, "GPIO210_C7"), - PINCTRL_PIN(DB8540_PIN_B8, "GPIO211_B8"), - PINCTRL_PIN(DB8540_PIN_C10, "GPIO212_C10"), - PINCTRL_PIN(DB8540_PIN_C8, "GPIO213_C8"), - PINCTRL_PIN(DB8540_PIN_C9, "GPIO214_C9"), - /* Hole */ - PINCTRL_PIN(DB8540_PIN_B9, "GPIO219_B9"), - PINCTRL_PIN(DB8540_PIN_A10, "GPIO220_A10"), - PINCTRL_PIN(DB8540_PIN_D9, "GPIO221_D9"), - PINCTRL_PIN(DB8540_PIN_B11, "GPIO222_B11"), - PINCTRL_PIN(DB8540_PIN_B10, "GPIO223_B10"), - PINCTRL_PIN(DB8540_PIN_E10, "GPIO224_E10"), - PINCTRL_PIN(DB8540_PIN_B12, "GPIO225_B12"), - PINCTRL_PIN(DB8540_PIN_D10, "GPIO226_D10"), - PINCTRL_PIN(DB8540_PIN_D11, "GPIO227_D11"), - PINCTRL_PIN(DB8540_PIN_AJ6, "GPIO228_AJ6"), - PINCTRL_PIN(DB8540_PIN_B13, "GPIO229_B13"), - PINCTRL_PIN(DB8540_PIN_C12, "GPIO230_C12"), - PINCTRL_PIN(DB8540_PIN_B14, "GPIO231_B14"), - PINCTRL_PIN(DB8540_PIN_E11, "GPIO232_E11"), - /* Hole */ - PINCTRL_PIN(DB8540_PIN_D12, "GPIO256_D12"), - PINCTRL_PIN(DB8540_PIN_D15, "GPIO257_D15"), - PINCTRL_PIN(DB8540_PIN_C13, "GPIO258_C13"), - PINCTRL_PIN(DB8540_PIN_C14, "GPIO259_C14"), - PINCTRL_PIN(DB8540_PIN_C18, "GPIO260_C18"), - PINCTRL_PIN(DB8540_PIN_C16, "GPIO261_C16"), - PINCTRL_PIN(DB8540_PIN_B16, "GPIO262_B16"), - PINCTRL_PIN(DB8540_PIN_D18, "GPIO263_D18"), - PINCTRL_PIN(DB8540_PIN_C15, "GPIO264_C15"), - PINCTRL_PIN(DB8540_PIN_C17, "GPIO265_C17"), - PINCTRL_PIN(DB8540_PIN_B17, "GPIO266_B17"), - PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"), -}; - -#define DB8540_GPIO_RANGE(a, b, c) { .name = "db8540", .id = a, .base = b, \ - .pin_base = b, .npins = c } - -/* - * This matches the 32-pin gpio chips registered by the GPIO portion. This - * cannot be const since we assign the struct gpio_chip * pointer at runtime. - */ -static struct pinctrl_gpio_range nmk_db8540_ranges[] = { - DB8540_GPIO_RANGE(0, 0, 18), - DB8540_GPIO_RANGE(0, 22, 7), - DB8540_GPIO_RANGE(1, 33, 6), - DB8540_GPIO_RANGE(2, 64, 4), - DB8540_GPIO_RANGE(2, 70, 18), - DB8540_GPIO_RANGE(3, 116, 12), - DB8540_GPIO_RANGE(4, 128, 32), - DB8540_GPIO_RANGE(5, 160, 9), - DB8540_GPIO_RANGE(6, 192, 23), - DB8540_GPIO_RANGE(6, 219, 5), - DB8540_GPIO_RANGE(7, 224, 9), - DB8540_GPIO_RANGE(8, 256, 12), -}; - -/* - * Read the pin group names like this: - * u0_a_1 = first groups of pins for uart0 on alt function a - * i2c2_b_2 = second group of pins for i2c2 on alt function b - * - * The groups are arranged as sets per altfunction column, so we can - * mux in one group at a time by selecting the same altfunction for them - * all. When functions require pins on different altfunctions, you need - * to combine several groups. - */ - -/* Altfunction A column */ -static const unsigned u0_a_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7, - DB8540_PIN_AF2, DB8540_PIN_AD3 }; -static const unsigned u1rxtx_a_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 }; -static const unsigned u1ctsrts_a_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 }; -/* Image processor I2C line, this is driven by image processor firmware */ -static const unsigned ipi2c_a_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 }; -static const unsigned ipi2c_a_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 }; -/* MSP0 can only be on these pins, but TXD and RXD can be flipped */ -static const unsigned msp0txrx_a_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 }; -static const unsigned msp0tfstck_a_1_pins[] = { DB8540_PIN_AC2, - DB8540_PIN_AC4 }; -static const unsigned msp0rfsrck_a_1_pins[] = { DB8540_PIN_AH7, - DB8540_PIN_AE7 }; -/* Basic pins of the MMC/SD card 0 interface */ -static const unsigned mc0_a_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11, - DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10}; -/* MSP1 can only be on these pins, but TXD and RXD can be flipped */ -static const unsigned msp1txrx_a_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 }; -static const unsigned msp1_a_1_pins[] = { DB8540_PIN_AF3, DB8540_PIN_AF5 }; - -static const unsigned modobsclk_a_1_pins[] = { DB8540_PIN_AF9 }; -static const unsigned clkoutreq_a_1_pins[] = { DB8540_PIN_AE8 }; -/* LCD interface */ -static const unsigned lcdb_a_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25, - DB8540_PIN_M27, DB8540_PIN_N25 }; -static const unsigned lcdvsi0_a_1_pins[] = { DB8540_PIN_AJ24 }; -static const unsigned lcdvsi1_a_1_pins[] = { DB8540_PIN_AE21 }; -static const unsigned lcd_d0_d7_a_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26, - DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28, - DB8540_PIN_P22, DB8540_PIN_P28 }; -/* D8 thru D11 often used as TVOUT lines */ -static const unsigned lcd_d8_d11_a_1_pins[] = { DB8540_PIN_P26, DB8540_PIN_T22, - DB8540_PIN_R27, DB8540_PIN_P27 }; -static const unsigned lcd_d12_d23_a_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25, - DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21, - DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, - DB8540_PIN_AG20, DB8540_PIN_AE23 }; -static const unsigned kp_a_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19, - DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 }; -/* MC2 has 8 data lines and no direction control, so only for (e)MMC */ -static const unsigned mc2_a_1_pins[] = { DB8540_PIN_AC27, DB8540_PIN_AD27, - DB8540_PIN_AE28, DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, - DB8540_PIN_AF27, DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, - DB8540_PIN_AG24 }; -static const unsigned ssp1_a_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25, - DB8540_PIN_AF26, DB8540_PIN_AF23 }; -static const unsigned ssp0_a_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25, - DB8540_PIN_AH24, DB8540_PIN_AJ25 }; -static const unsigned i2c0_a_1_pins[] = { DB8540_PIN_AG27, DB8540_PIN_AH23 }; -/* - * Image processor GPIO pins are named "ipgpio" and have their own - * numberspace - */ -static const unsigned ipgpio0_a_1_pins[] = { DB8540_PIN_AE26 }; -static const unsigned ipgpio1_a_1_pins[] = { DB8540_PIN_AE24 }; -/* modem i2s interface */ -static const unsigned modi2s_a_1_pins[] = { DB8540_PIN_AD26, DB8540_PIN_AD28, - DB8540_PIN_AC28, DB8540_PIN_AC26 }; -static const unsigned spi2_a_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21, - DB8540_PIN_AH19, DB8540_PIN_AE19 }; -static const unsigned u2txrx_a_1_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 }; -static const unsigned u2ctsrts_a_1_pins[] = { DB8540_PIN_AF19, - DB8540_PIN_AF18 }; -static const unsigned modsmb_a_1_pins[] = { DB8540_PIN_AF17, DB8540_PIN_AE17 }; -static const unsigned msp2sck_a_1_pins[] = { DB8540_PIN_J3 }; -static const unsigned msp2txdtcktfs_a_1_pins[] = { DB8540_PIN_H1, DB8540_PIN_J2, - DB8540_PIN_H2 }; -static const unsigned msp2rxd_a_1_pins[] = { DB8540_PIN_H3 }; -static const unsigned mc4_a_1_pins[] = { DB8540_PIN_H4, DB8540_PIN_G2, - DB8540_PIN_G3, DB8540_PIN_G4, DB8540_PIN_F2, DB8540_PIN_C6, - DB8540_PIN_B6, DB8540_PIN_B7, DB8540_PIN_A7, DB8540_PIN_D7, - DB8540_PIN_D8 }; -static const unsigned mc1_a_1_pins[] = { DB8540_PIN_F3, DB8540_PIN_E2, - DB8540_PIN_C7, DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8, - DB8540_PIN_C9 }; -/* mc1_a_2_pins exclude MC1_FBCLK */ -static const unsigned mc1_a_2_pins[] = { DB8540_PIN_F3, DB8540_PIN_C7, - DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8, - DB8540_PIN_C9 }; -static const unsigned hsir_a_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10, - DB8540_PIN_D9 }; -static const unsigned hsit_a_1_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10, - DB8540_PIN_E10, DB8540_PIN_B12, DB8540_PIN_D10 }; -static const unsigned hsit_a_2_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10, - DB8540_PIN_E10, DB8540_PIN_B12 }; -static const unsigned clkout1_a_1_pins[] = { DB8540_PIN_D11 }; -static const unsigned clkout1_a_2_pins[] = { DB8540_PIN_B13 }; -static const unsigned clkout2_a_1_pins[] = { DB8540_PIN_AJ6 }; -static const unsigned clkout2_a_2_pins[] = { DB8540_PIN_C12 }; -static const unsigned msp4_a_1_pins[] = { DB8540_PIN_B14, DB8540_PIN_E11 }; -static const unsigned usb_a_1_pins[] = { DB8540_PIN_D12, DB8540_PIN_D15, - DB8540_PIN_C13, DB8540_PIN_C14, DB8540_PIN_C18, DB8540_PIN_C16, - DB8540_PIN_B16, DB8540_PIN_D18, DB8540_PIN_C15, DB8540_PIN_C17, - DB8540_PIN_B17, DB8540_PIN_D17 }; -/* Altfunction B colum */ -static const unsigned apetrig_b_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7 }; -static const unsigned modtrig_b_1_pins[] = { DB8540_PIN_AF2, DB8540_PIN_AD3 }; -static const unsigned i2c4_b_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 }; -static const unsigned i2c1_b_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 }; -static const unsigned i2c2_b_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 }; -static const unsigned i2c2_b_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 }; -static const unsigned msp0txrx_b_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 }; -static const unsigned i2c1_b_2_pins[] = { DB8540_PIN_AH7, DB8540_PIN_AE7 }; -static const unsigned stmmod_b_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11, - DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 }; -static const unsigned moduartstmmux_b_1_pins[] = { DB8540_PIN_AG11 }; -static const unsigned msp1txrx_b_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 }; -static const unsigned kp_b_1_pins[] = { DB8540_PIN_AJ24, DB8540_PIN_AE21, - DB8540_PIN_M26, DB8540_PIN_M25, DB8540_PIN_M27, DB8540_PIN_N25, - DB8540_PIN_M28, DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, - DB8540_PIN_N27, DB8540_PIN_N28, DB8540_PIN_P22, DB8540_PIN_P28, - DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27, - DB8540_PIN_R26, DB8540_PIN_R25 }; -static const unsigned u2txrx_b_1_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27 }; -static const unsigned sm_b_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21, - DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, - DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22, - DB8540_PIN_AJ21, DB8540_PIN_AC27, DB8540_PIN_AD27, DB8540_PIN_AE28, - DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, DB8540_PIN_AF27, - DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, DB8540_PIN_AG24, - DB8540_PIN_AD25 }; -static const unsigned smcs0_b_1_pins[] = { DB8540_PIN_AG19 }; -static const unsigned smcs1_b_1_pins[] = { DB8540_PIN_AE26 }; -static const unsigned ipgpio7_b_1_pins[] = { DB8540_PIN_AH25 }; -static const unsigned ipgpio2_b_1_pins[] = { DB8540_PIN_AF26 }; -static const unsigned ipgpio3_b_1_pins[] = { DB8540_PIN_AF23 }; -static const unsigned i2c6_b_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25 }; -static const unsigned i2c5_b_1_pins[] = { DB8540_PIN_AH24, DB8540_PIN_AJ25 }; -static const unsigned u3txrx_b_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21 }; -static const unsigned u3ctsrts_b_1_pins[] = { DB8540_PIN_AH19, - DB8540_PIN_AE19 }; -static const unsigned i2c5_b_2_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 }; -static const unsigned i2c4_b_2_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 }; -static const unsigned u4txrx_b_1_pins[] = { DB8540_PIN_AE18, DB8540_PIN_AG17 }; -static const unsigned u4ctsrts_b_1_pins[] = { DB8540_PIN_AF17, - DB8540_PIN_AE17 }; -static const unsigned ddrtrig_b_1_pins[] = { DB8540_PIN_J3 }; -static const unsigned msp4_b_1_pins[] = { DB8540_PIN_H3 }; -static const unsigned pwl_b_1_pins[] = { DB8540_PIN_C6 }; -static const unsigned spi1_b_1_pins[] = { DB8540_PIN_E2, DB8540_PIN_C10, - DB8540_PIN_C8, DB8540_PIN_C9 }; -static const unsigned mc3_b_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10, - DB8540_PIN_D9, DB8540_PIN_B11, DB8540_PIN_B10, DB8540_PIN_E10, - DB8540_PIN_B12 }; -static const unsigned pwl_b_2_pins[] = { DB8540_PIN_D10 }; -static const unsigned pwl_b_3_pins[] = { DB8540_PIN_B13 }; -static const unsigned pwl_b_4_pins[] = { DB8540_PIN_C12 }; -static const unsigned u2txrx_b_2_pins[] = { DB8540_PIN_B17, DB8540_PIN_D17 }; - -/* Altfunction C column */ -static const unsigned ipgpio6_c_1_pins[] = { DB8540_PIN_AG6 }; -static const unsigned ipgpio0_c_1_pins[] = { DB8540_PIN_AD5 }; -static const unsigned ipgpio1_c_1_pins[] = { DB8540_PIN_AF7 }; -static const unsigned ipgpio3_c_1_pins[] = { DB8540_PIN_AE4 }; -static const unsigned ipgpio2_c_1_pins[] = { DB8540_PIN_AD1 }; -static const unsigned u0_c_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AF3, - DB8540_PIN_AF5, DB8540_PIN_AG4 }; -static const unsigned smcleale_c_1_pins[] = { DB8540_PIN_AJ24, - DB8540_PIN_AE21 }; -static const unsigned ipgpio4_c_1_pins[] = { DB8540_PIN_M26 }; -static const unsigned ipgpio5_c_1_pins[] = { DB8540_PIN_M25 }; -static const unsigned ipgpio6_c_2_pins[] = { DB8540_PIN_M27 }; -static const unsigned ipgpio7_c_1_pins[] = { DB8540_PIN_N25 }; -static const unsigned stmape_c_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26, - DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 }; -static const unsigned u2rxtx_c_1_pins[] = { DB8540_PIN_N28, DB8540_PIN_P22 }; -static const unsigned modobsresout_c_1_pins[] = { DB8540_PIN_P28 }; -static const unsigned ipgpio2_c_2_pins[] = { DB8540_PIN_P26 }; -static const unsigned ipgpio3_c_2_pins[] = { DB8540_PIN_T22 }; -static const unsigned ipgpio4_c_2_pins[] = { DB8540_PIN_R27 }; -static const unsigned ipgpio5_c_2_pins[] = { DB8540_PIN_P27 }; -static const unsigned modaccgpo_c_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25, - DB8540_PIN_U22 }; -static const unsigned modobspwrrst_c_1_pins[] = { DB8540_PIN_T27 }; -static const unsigned mc5_c_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21, - DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, - DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22, - DB8540_PIN_AJ21}; -static const unsigned smps0_c_1_pins[] = { DB8540_PIN_AG19 }; -static const unsigned moduart1_c_1_pins[] = { DB8540_PIN_T25, DB8540_PIN_T26 }; -static const unsigned mc2rstn_c_1_pins[] = { DB8540_PIN_AE28 }; -static const unsigned i2c5_c_1_pins[] = { DB8540_PIN_AG28, DB8540_PIN_AF28 }; -static const unsigned ipgpio0_c_2_pins[] = { DB8540_PIN_AG25 }; -static const unsigned ipgpio1_c_2_pins[] = { DB8540_PIN_AG24 }; -static const unsigned kp_c_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25, - DB8540_PIN_AF26, DB8540_PIN_AF23 }; -static const unsigned modrf_c_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25, - DB8540_PIN_AH24 }; -static const unsigned smps1_c_1_pins[] = { DB8540_PIN_AE26 }; -static const unsigned i2c5_c_2_pins[] = { DB8540_PIN_AH19, DB8540_PIN_AE19 }; -static const unsigned u4ctsrts_c_1_pins[] = { DB8540_PIN_AG18, - DB8540_PIN_AH17 }; -static const unsigned u3rxtx_c_1_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 }; -static const unsigned msp4_c_1_pins[] = { DB8540_PIN_J3 }; -static const unsigned mc4rstn_c_1_pins[] = { DB8540_PIN_C6 }; -static const unsigned spi0_c_1_pins[] = { DB8540_PIN_A10, DB8540_PIN_B10, - DB8540_PIN_E10, DB8540_PIN_B12 }; -static const unsigned i2c3_c_1_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 }; - -/* Other alt C1 column */ -static const unsigned spi3_oc1_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5, - DB8540_PIN_AE4, DB8540_PIN_AD1 }; -static const unsigned stmape_oc1_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11, - DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 }; -static const unsigned u2_oc1_1_pins[] = { DB8540_PIN_AG11 }; -static const unsigned remap0_oc1_1_pins[] = { DB8540_PIN_AJ24 }; -static const unsigned remap1_oc1_1_pins[] = { DB8540_PIN_AE21 }; -static const unsigned modobsrefclk_oc1_1_pins[] = { DB8540_PIN_M26 }; -static const unsigned modobspwrctrl_oc1_1_pins[] = { DB8540_PIN_M25 }; -static const unsigned modobsclkout_oc1_1_pins[] = { DB8540_PIN_M27 }; -static const unsigned moduart1_oc1_1_pins[] = { DB8540_PIN_N25 }; -static const unsigned modprcmudbg_oc1_1_pins[] = { DB8540_PIN_M28, - DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, - DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22, - DB8540_PIN_R26, DB8540_PIN_R25, DB8540_PIN_U22, DB8540_PIN_T27, - DB8540_PIN_AH20, DB8540_PIN_AG19, DB8540_PIN_AF22, DB8540_PIN_AJ21, - DB8540_PIN_T25}; -static const unsigned modobsresout_oc1_1_pins[] = { DB8540_PIN_N28 }; -static const unsigned modaccgpo_oc1_1_pins[] = { DB8540_PIN_R27, DB8540_PIN_P27, - DB8540_PIN_T26 }; -static const unsigned kp_oc1_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21, - DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, - DB8540_PIN_AG20, DB8540_PIN_AE23 }; -static const unsigned modxmip_oc1_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25, - DB8540_PIN_AG23, DB8540_PIN_AE25 }; -static const unsigned i2c6_oc1_1_pins[] = { DB8540_PIN_AE26, DB8540_PIN_AE24 }; -static const unsigned u2txrx_oc1_1_pins[] = { DB8540_PIN_B7, DB8540_PIN_A7 }; -static const unsigned u2ctsrts_oc1_1_pins[] = { DB8540_PIN_D7, DB8540_PIN_D8 }; - -/* Other alt C2 column */ -static const unsigned sbag_oc2_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11, - DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 }; -static const unsigned hxclk_oc2_1_pins[] = { DB8540_PIN_M25 }; -static const unsigned modaccuart_oc2_1_pins[] = { DB8540_PIN_N25 }; -static const unsigned stmmod_oc2_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26, - DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 }; -static const unsigned moduartstmmux_oc2_1_pins[] = { DB8540_PIN_N28 }; -static const unsigned hxgpio_oc2_1_pins[] = { DB8540_PIN_P22, DB8540_PIN_P28, - DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27, - DB8540_PIN_R26, DB8540_PIN_R25 }; -static const unsigned sbag_oc2_2_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27, - DB8540_PIN_AG22, DB8540_PIN_AF21, DB8540_PIN_AF24, DB8540_PIN_AH22 }; -static const unsigned modobsservice_oc2_1_pins[] = { DB8540_PIN_AJ23 }; -static const unsigned moduart0_oc2_1_pins[] = { DB8540_PIN_AG20, - DB8540_PIN_AE23 }; -static const unsigned stmape_oc2_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19, - DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 }; -static const unsigned u2_oc2_1_pins[] = { DB8540_PIN_T26, DB8540_PIN_AH21 }; -static const unsigned modxmip_oc2_1_pins[] = { DB8540_PIN_AE26, - DB8540_PIN_AE24 }; - -/* Other alt C3 column */ -static const unsigned modaccgpo_oc3_1_pins[] = { DB8540_PIN_AG11 }; -static const unsigned tpui_oc3_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25, - DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26, - DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28, - DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22, - DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25, - DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21, - DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21, - DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AG19, - DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 }; - -/* Other alt C4 column */ -static const unsigned hwobs_oc4_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25, - DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26, - DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28, - DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22, - DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25 }; -static const unsigned moduart1txrx_oc4_1_pins[] = { DB8540_PIN_U22, - DB8540_PIN_T27 }; -static const unsigned moduart1rtscts_oc4_1_pins[] = { DB8540_PIN_AG22, - DB8540_PIN_AF21 }; -static const unsigned modaccuarttxrx_oc4_1_pins[] = { DB8540_PIN_AF24, - DB8540_PIN_AH22 }; -static const unsigned modaccuartrtscts_oc4_1_pins[] = { DB8540_PIN_AJ23, - DB8540_PIN_AH21 }; -static const unsigned stmmod_oc4_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19, - DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 }; -static const unsigned moduartstmmux_oc4_1_pins[] = { DB8540_PIN_T26 }; - -#define DB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ - .npins = ARRAY_SIZE(a##_pins), .altsetting = b } - -static const struct nmk_pingroup nmk_db8540_groups[] = { - /* Altfunction A column */ - DB8540_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(modobsclk_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(clkoutreq_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(modi2s_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(spi2_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(u2txrx_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(u2ctsrts_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(modsmb_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp2txdtcktfs_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp2rxd_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(clkout1_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(clkout1_a_2, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(clkout2_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(clkout2_a_2, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(msp4_a_1, NMK_GPIO_ALT_A), - DB8540_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A), - /* Altfunction B column */ - DB8540_PIN_GROUP(apetrig_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(modtrig_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(moduartstmmux_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(u2txrx_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c6_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c5_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(u3txrx_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(u3ctsrts_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c5_b_2, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(i2c4_b_2, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(u4txrx_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(u4ctsrts_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(msp4_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B), - DB8540_PIN_GROUP(u2txrx_b_2, NMK_GPIO_ALT_B), - /* Altfunction C column */ - DB8540_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(modobsresout_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(modaccgpo_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(modobspwrrst_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(moduart1_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(i2c5_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio0_c_2, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(ipgpio1_c_2, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(modrf_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(i2c5_c_2, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(u4ctsrts_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(u3rxtx_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(msp4_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), - DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C), - - /* Other alt C1 column */ - DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C1), - DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C1), - - /* Other alt C2 column */ - DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C2), - DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C2), - - /* Other alt C3 column */ - DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C3), - DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C3), - - /* Other alt C4 column */ - DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4), - DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C4), - DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C4), - DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C4), - DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C4), - DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C4), - DB8540_PIN_GROUP(moduartstmmux_oc4_1, NMK_GPIO_ALT_C4), - -}; - -/* We use this macro to define the groups applicable to a function */ -#define DB8540_FUNC_GROUPS(a, b...) \ -static const char * const a##_groups[] = { b }; - -DB8540_FUNC_GROUPS(apetrig, "apetrig_b_1"); -DB8540_FUNC_GROUPS(clkout, "clkoutreq_a_1", "clkout1_a_1", "clkout1_a_2", - "clkout2_a_1", "clkout2_a_2"); -DB8540_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1"); -DB8540_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2"); -DB8540_FUNC_GROUPS(hwobs, "hwobs_oc4_1"); -DB8540_FUNC_GROUPS(hx, "hxclk_oc2_1", "hxgpio_oc2_1"); -DB8540_FUNC_GROUPS(i2c0, "i2c0_a_1"); -DB8540_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2"); -DB8540_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2"); -DB8540_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c4_b_1"); -DB8540_FUNC_GROUPS(i2c4, "i2c4_b_2"); -DB8540_FUNC_GROUPS(i2c5, "i2c5_b_1", "i2c5_b_2", "i2c5_c_1", "i2c5_c_2"); -DB8540_FUNC_GROUPS(i2c6, "i2c6_b_1", "i2c6_oc1_1"); -/* The image processor has 8 GPIO pins that can be muxed out */ -DB8540_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio0_c_1", "ipgpio0_c_2", - "ipgpio1_a_1", "ipgpio1_c_1", "ipgpio1_c_2", - "ipgpio2_b_1", "ipgpio2_c_1", "ipgpio2_c_2", - "ipgpio3_b_1", "ipgpio3_c_1", "ipgpio3_c_2", - "ipgpio4_c_1", "ipgpio4_c_2", - "ipgpio5_c_1", "ipgpio5_c_2", - "ipgpio6_c_1", "ipgpio6_c_2", - "ipgpio7_b_1", "ipgpio7_c_1"); -DB8540_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2"); -DB8540_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1"); -DB8540_FUNC_GROUPS(lcd, "lcd_d0_d7_a_1", "lcd_d12_d23_a_1", "lcd_d8_d11_a_1", - "lcdvsi0_a_1", "lcdvsi1_a_1"); -DB8540_FUNC_GROUPS(lcdb, "lcdb_a_1"); -DB8540_FUNC_GROUPS(mc0, "mc0_a_1"); -DB8540_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2"); -DB8540_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); -DB8540_FUNC_GROUPS(mc3, "mc3_b_1"); -DB8540_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); -DB8540_FUNC_GROUPS(mc5, "mc5_c_1"); -DB8540_FUNC_GROUPS(modaccgpo, "modaccgpo_c_1", "modaccgpo_oc1_1", - "modaccgpo_oc3_1"); -DB8540_FUNC_GROUPS(modaccuart, "modaccuart_oc2_1", "modaccuarttxrx_oc4_1", - "modaccuartrtccts_oc4_1"); -DB8540_FUNC_GROUPS(modi2s, "modi2s_a_1"); -DB8540_FUNC_GROUPS(modobs, "modobsclk_a_1", "modobsclkout_oc1_1", - "modobspwrctrl_oc1_1", "modobspwrrst_c_1", - "modobsrefclk_oc1_1", "modobsresout_c_1", - "modobsresout_oc1_1", "modobsservice_oc2_1"); -DB8540_FUNC_GROUPS(modprcmudbg, "modprcmudbg_oc1_1"); -DB8540_FUNC_GROUPS(modrf, "modrf_c_1"); -DB8540_FUNC_GROUPS(modsmb, "modsmb_a_1"); -DB8540_FUNC_GROUPS(modtrig, "modtrig_b_1"); -DB8540_FUNC_GROUPS(moduart, "moduart1_c_1", "moduart1_oc1_1", - "moduart1txrx_oc4_1", "moduart1rtscts_oc4_1", "moduart0_oc2_1"); -DB8540_FUNC_GROUPS(moduartstmmux, "moduartstmmux_b_1", "moduartstmmux_oc2_1", - "moduartstmmux_oc4_1"); -DB8540_FUNC_GROUPS(modxmip, "modxmip_oc1_1", "modxmip_oc2_1"); -/* - * MSP0 can only be on a certain set of pins, but the TX/RX pins can be - * switched around by selecting the altfunction A or B. - */ -DB8540_FUNC_GROUPS(msp0, "msp0rfsrck_a_1", "msp0tfstck_a_1", "msp0txrx_a_1", - "msp0txrx_b_1"); -DB8540_FUNC_GROUPS(msp1, "msp1_a_1", "msp1txrx_a_1", "msp1txrx_b_1"); -DB8540_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2txdtcktfs_a_1", "msp2rxd_a_1"); -DB8540_FUNC_GROUPS(msp4, "msp4_a_1", "msp4_b_1", "msp4_c_1"); -DB8540_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4"); -DB8540_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1"); -DB8540_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc2_2"); -/* Select between CS0 on alt B or PS1 on alt C */ -DB8540_FUNC_GROUPS(sm, "sm_b_1", "smcleale_c_1", "smcs0_b_1", "smcs1_b_1", - "smps0_c_1", "smps1_c_1"); -DB8540_FUNC_GROUPS(spi0, "spi0_c_1"); -DB8540_FUNC_GROUPS(spi1, "spi1_b_1"); -DB8540_FUNC_GROUPS(spi2, "spi2_a_1"); -DB8540_FUNC_GROUPS(spi3, "spi3_oc1_1"); -DB8540_FUNC_GROUPS(ssp0, "ssp0_a_1"); -DB8540_FUNC_GROUPS(ssp1, "ssp1_a_1"); -DB8540_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_oc1_1", "stmape_oc2_1"); -DB8540_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_oc2_1", "stmmod_oc4_1"); -DB8540_FUNC_GROUPS(tpui, "tpui_oc3_1"); -DB8540_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1"); -DB8540_FUNC_GROUPS(u1, "u1ctsrts_a_1", "u1rxtx_a_1"); -DB8540_FUNC_GROUPS(u2, "u2_oc1_1", "u2_oc2_1", "u2ctsrts_a_1", "u2ctsrts_oc1_1", - "u2rxtx_c_1", "u2txrx_a_1", "u2txrx_b_1", "u2txrx_b_2", - "u2txrx_oc1_1"); -DB8540_FUNC_GROUPS(u3, "u3ctsrts_b_1", "u3rxtx_c_1", "u3txrxa_b_1"); -DB8540_FUNC_GROUPS(u4, "u4ctsrts_b_1", "u4ctsrts_c_1", "u4txrx_b_1"); -DB8540_FUNC_GROUPS(usb, "usb_a_1"); - - -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -static const struct nmk_function nmk_db8540_functions[] = { - FUNCTION(apetrig), - FUNCTION(clkout), - FUNCTION(ddrtrig), - FUNCTION(hsi), - FUNCTION(hwobs), - FUNCTION(hx), - FUNCTION(i2c0), - FUNCTION(i2c1), - FUNCTION(i2c2), - FUNCTION(i2c3), - FUNCTION(i2c4), - FUNCTION(i2c5), - FUNCTION(i2c6), - FUNCTION(ipgpio), - FUNCTION(ipi2c), - FUNCTION(kp), - FUNCTION(lcd), - FUNCTION(lcdb), - FUNCTION(mc0), - FUNCTION(mc1), - FUNCTION(mc2), - FUNCTION(mc3), - FUNCTION(mc4), - FUNCTION(mc5), - FUNCTION(modaccgpo), - FUNCTION(modaccuart), - FUNCTION(modi2s), - FUNCTION(modobs), - FUNCTION(modprcmudbg), - FUNCTION(modrf), - FUNCTION(modsmb), - FUNCTION(modtrig), - FUNCTION(moduart), - FUNCTION(modxmip), - FUNCTION(msp0), - FUNCTION(msp1), - FUNCTION(msp2), - FUNCTION(msp4), - FUNCTION(pwl), - FUNCTION(remap), - FUNCTION(sbag), - FUNCTION(sm), - FUNCTION(spi0), - FUNCTION(spi1), - FUNCTION(spi2), - FUNCTION(spi3), - FUNCTION(ssp0), - FUNCTION(ssp1), - FUNCTION(stmape), - FUNCTION(stmmod), - FUNCTION(tpui), - FUNCTION(u0), - FUNCTION(u1), - FUNCTION(u2), - FUNCTION(u3), - FUNCTION(u4), - FUNCTION(usb) -}; - -static const struct prcm_gpiocr_altcx_pin_desc db8540_altcx_pins[] = { - PRCM_GPIOCR_ALTCX(8, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_CLK */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(9, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_RXD */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(10, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_FRM */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(11, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_TXD */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(23, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_CLK_a */ - true, PRCM_IDX_GPIOCR2, 10, /* SBAG_CLK_a */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(24, true, PRCM_IDX_GPIOCR3, 30, /* U2_RXD_g */ - true, PRCM_IDX_GPIOCR2, 10, /* SBAG_VAL_a */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(25, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[0] */ - true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[0] */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(26, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[1] */ - true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[1] */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(27, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[2] */ - true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[2] */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(28, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[3] */ - true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[3] */ - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(64, true, PRCM_IDX_GPIOCR1, 15, /* MODOBS_REFCLK_REQ */ - false, 0, 0, - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_CTL */ - true, PRCM_IDX_GPIOCR2, 23 /* HW_OBS_APE_PRCMU[17] */ - ), - PRCM_GPIOCR_ALTCX(65, true, PRCM_IDX_GPIOCR1, 19, /* MODOBS_PWRCTRL0 */ - true, PRCM_IDX_GPIOCR1, 24, /* Hx_CLK */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_CLK */ - true, PRCM_IDX_GPIOCR2, 24 /* HW_OBS_APE_PRCMU[16] */ - ), - PRCM_GPIOCR_ALTCX(66, true, PRCM_IDX_GPIOCR1, 15, /* MODOBS_CLKOUT1 */ - false, 0, 0, - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[15] */ - true, PRCM_IDX_GPIOCR2, 25 /* HW_OBS_APE_PRCMU[15] */ - ), - PRCM_GPIOCR_ALTCX(67, true, PRCM_IDX_GPIOCR1, 1, /* MODUART1_TXD_a */ - true, PRCM_IDX_GPIOCR1, 6, /* MODACCUART_TXD_a */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[14] */ - true, PRCM_IDX_GPIOCR2, 26 /* HW_OBS_APE_PRCMU[14] */ - ), - PRCM_GPIOCR_ALTCX(70, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[17] */ - true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_CLK_b */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[13] */ - true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[13] */ - ), - PRCM_GPIOCR_ALTCX(71, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[16] */ - true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[3] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[12] */ - true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[12] */ - ), - PRCM_GPIOCR_ALTCX(72, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[15] */ - true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[2] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[11] */ - true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[11] */ - ), - PRCM_GPIOCR_ALTCX(73, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[14] */ - true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[1] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[10] */ - true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[10] */ - ), - PRCM_GPIOCR_ALTCX(74, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[13] */ - true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[0] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[9] */ - true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[9] */ - ), - PRCM_GPIOCR_ALTCX(75, true, PRCM_IDX_GPIOCR1, 12, /* MODOBS_RESOUT0_N */ - true, PRCM_IDX_GPIOCR2, 1, /* MODUART_STMMUX_RXD_b */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[8] */ - true, PRCM_IDX_GPIOCR2, 28 /* HW_OBS_APE_PRCMU[8] */ - ), - PRCM_GPIOCR_ALTCX(76, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[12] */ - true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[7] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[7] */ - true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[7] */ - ), - PRCM_GPIOCR_ALTCX(77, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[11] */ - true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[6] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[6] */ - true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[6] */ - ), - PRCM_GPIOCR_ALTCX(78, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[10] */ - true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[5] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[5] */ - true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[5] */ - ), - PRCM_GPIOCR_ALTCX(79, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[9] */ - true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[4] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[4] */ - true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[4] */ - ), - PRCM_GPIOCR_ALTCX(80, true, PRCM_IDX_GPIOCR1, 26, /* MODACC_GPO[0] */ - true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[3] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[3] */ - true, PRCM_IDX_GPIOCR2, 30 /* HW_OBS_APE_PRCMU[3] */ - ), - PRCM_GPIOCR_ALTCX(81, true, PRCM_IDX_GPIOCR2, 17, /* MODACC_GPO[1] */ - true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[2] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[2] */ - true, PRCM_IDX_GPIOCR2, 30 /* HW_OBS_APE_PRCMU[2] */ - ), - PRCM_GPIOCR_ALTCX(82, true, PRCM_IDX_GPIOCR3, 8, /* MOD_PRCMU_DEBUG[8] */ - true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[1] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[1] */ - true, PRCM_IDX_GPIOCR2, 31 /* HW_OBS_APE_PRCMU[1] */ - ), - PRCM_GPIOCR_ALTCX(83, true, PRCM_IDX_GPIOCR3, 8, /* MOD_PRCMU_DEBUG[7] */ - true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[0] */ - true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[0] */ - true, PRCM_IDX_GPIOCR2, 31 /* HW_OBS_APE_PRCMU[0] */ - ), - PRCM_GPIOCR_ALTCX(84, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[6] */ - true, PRCM_IDX_GPIOCR1, 8, /* SBAG_CLK_b */ - true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[23] */ - true, PRCM_IDX_GPIOCR1, 16 /* MODUART1_RXD_b */ - ), - PRCM_GPIOCR_ALTCX(85, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[5] */ - true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[3] */ - true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[22] */ - true, PRCM_IDX_GPIOCR1, 16 /* MODUART1_TXD_b */ - ), - PRCM_GPIOCR_ALTCX(86, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[0] */ - true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[0] */ - true, PRCM_IDX_GPIOCR1, 14, /* TPIU_D[25] */ - true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[0] */ - ), - PRCM_GPIOCR_ALTCX(87, true, PRCM_IDX_GPIOCR3, 0, /* MODACC_GPO_a[5] */ - true, PRCM_IDX_GPIOCR2, 3, /* U2_RXD_c */ - true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[24] */ - true, PRCM_IDX_GPIOCR1, 21 /* MODUART_STMMUX_RXD_c */ - ), - PRCM_GPIOCR_ALTCX(151, true, PRCM_IDX_GPIOCR1, 18, /* REMAP0 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(152, true, PRCM_IDX_GPIOCR1, 18, /* REMAP1 */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(153, true, PRCM_IDX_GPIOCR3, 2, /* KP_O_b[6] */ - true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[2] */ - true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[21] */ - true, PRCM_IDX_GPIOCR1, 0 /* MODUART1_RTS */ - ), - PRCM_GPIOCR_ALTCX(154, true, PRCM_IDX_GPIOCR3, 2, /* KP_I_b[6] */ - true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[1] */ - true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[20] */ - true, PRCM_IDX_GPIOCR1, 0 /* MODUART1_CTS */ - ), - PRCM_GPIOCR_ALTCX(155, true, PRCM_IDX_GPIOCR3, 3, /* KP_O_b[5] */ - true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[0] */ - true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[19] */ - true, PRCM_IDX_GPIOCR1, 5 /* MODACCUART_RXD_c */ - ), - PRCM_GPIOCR_ALTCX(156, true, PRCM_IDX_GPIOCR3, 3, /* KP_O_b[4] */ - true, PRCM_IDX_GPIOCR1, 8, /* SBAG_VAL_b */ - true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[18] */ - true, PRCM_IDX_GPIOCR1, 5 /* MODACCUART_TXD_b */ - ), - PRCM_GPIOCR_ALTCX(157, true, PRCM_IDX_GPIOCR3, 4, /* KP_I_b[5] */ - true, PRCM_IDX_GPIOCR1, 23, /* MODOBS_SERVICE_N */ - true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[17] */ - true, PRCM_IDX_GPIOCR1, 14 /* MODACCUART_RTS */ - ), - PRCM_GPIOCR_ALTCX(158, true, PRCM_IDX_GPIOCR3, 4, /* KP_I_b[4] */ - true, PRCM_IDX_GPIOCR2, 0, /* U2_TXD_c */ - true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[16] */ - true, PRCM_IDX_GPIOCR1, 14 /* MODACCUART_CTS */ - ), - PRCM_GPIOCR_ALTCX(159, true, PRCM_IDX_GPIOCR3, 5, /* KP_O_b[3] */ - true, PRCM_IDX_GPIOCR3, 10, /* MODUART0_RXD */ - true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[31] */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(160, true, PRCM_IDX_GPIOCR3, 5, /* KP_I_b[3] */ - true, PRCM_IDX_GPIOCR3, 10, /* MODUART0_TXD */ - true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[30] */ - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(161, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[4] */ - true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_CLK_b */ - true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[29] */ - true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_CLK_c */ - ), - PRCM_GPIOCR_ALTCX(162, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[3] */ - true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[3] */ - true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[28] */ - true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[3] */ - ), - PRCM_GPIOCR_ALTCX(163, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[2] */ - true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[2] */ - true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[27] */ - true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[2] */ - ), - PRCM_GPIOCR_ALTCX(164, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[1] */ - true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[1] */ - true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[26] */ - true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[1] */ - ), - PRCM_GPIOCR_ALTCX(204, true, PRCM_IDX_GPIOCR2, 2, /* U2_RXD_f */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(205, true, PRCM_IDX_GPIOCR2, 2, /* U2_TXD_f */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(206, true, PRCM_IDX_GPIOCR2, 2, /* U2_CTSn_b */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), - PRCM_GPIOCR_ALTCX(207, true, PRCM_IDX_GPIOCR2, 2, /* U2_RTSn_b */ - false, 0, 0, - false, 0, 0, - false, 0, 0 - ), -}; - -static const u16 db8540_prcm_gpiocr_regs[] = { - [PRCM_IDX_GPIOCR1] = 0x138, - [PRCM_IDX_GPIOCR2] = 0x574, - [PRCM_IDX_GPIOCR3] = 0x2bc, -}; - -static const struct nmk_pinctrl_soc_data nmk_db8540_soc = { - .gpio_ranges = nmk_db8540_ranges, - .gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges), - .pins = nmk_db8540_pins, - .npins = ARRAY_SIZE(nmk_db8540_pins), - .functions = nmk_db8540_functions, - .nfunctions = ARRAY_SIZE(nmk_db8540_functions), - .groups = nmk_db8540_groups, - .ngroups = ARRAY_SIZE(nmk_db8540_groups), - .altcx_pins = db8540_altcx_pins, - .npins_altcx = ARRAY_SIZE(db8540_altcx_pins), - .prcm_gpiocr_registers = db8540_prcm_gpiocr_regs, -}; - -void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc) -{ - *soc = &nmk_db8540_soc; -} diff --git a/drivers/pinctrl/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/pinctrl-nomadik-stn8815.c deleted file mode 100644 index ed39dcafd4f8..000000000000 --- a/drivers/pinctrl/pinctrl-nomadik-stn8815.c +++ /dev/null @@ -1,356 +0,0 @@ -#include -#include -#include "pinctrl-nomadik.h" - -/* All the pins that can be used for GPIO and some other functions */ -#define _GPIO(offset) (offset) - -#define STN8815_PIN_B4 _GPIO(0) -#define STN8815_PIN_D5 _GPIO(1) -#define STN8815_PIN_C5 _GPIO(2) -#define STN8815_PIN_A4 _GPIO(3) -#define STN8815_PIN_B5 _GPIO(4) -#define STN8815_PIN_D6 _GPIO(5) -#define STN8815_PIN_C6 _GPIO(6) -#define STN8815_PIN_B6 _GPIO(7) -#define STN8815_PIN_B10 _GPIO(8) -#define STN8815_PIN_A10 _GPIO(9) -#define STN8815_PIN_C11 _GPIO(10) -#define STN8815_PIN_B11 _GPIO(11) -#define STN8815_PIN_A11 _GPIO(12) -#define STN8815_PIN_C12 _GPIO(13) -#define STN8815_PIN_B12 _GPIO(14) -#define STN8815_PIN_A12 _GPIO(15) -#define STN8815_PIN_C13 _GPIO(16) -#define STN8815_PIN_B13 _GPIO(17) -#define STN8815_PIN_A13 _GPIO(18) -#define STN8815_PIN_D13 _GPIO(19) -#define STN8815_PIN_C14 _GPIO(20) -#define STN8815_PIN_B14 _GPIO(21) -#define STN8815_PIN_A14 _GPIO(22) -#define STN8815_PIN_D15 _GPIO(23) -#define STN8815_PIN_C15 _GPIO(24) -#define STN8815_PIN_B15 _GPIO(25) -#define STN8815_PIN_A15 _GPIO(26) -#define STN8815_PIN_C16 _GPIO(27) -#define STN8815_PIN_B16 _GPIO(28) -#define STN8815_PIN_A16 _GPIO(29) -#define STN8815_PIN_D17 _GPIO(30) -#define STN8815_PIN_C17 _GPIO(31) -#define STN8815_PIN_AB6 _GPIO(32) -#define STN8815_PIN_AA6 _GPIO(33) -#define STN8815_PIN_Y6 _GPIO(34) -#define STN8815_PIN_Y5 _GPIO(35) -#define STN8815_PIN_AA5 _GPIO(36) -#define STN8815_PIN_AB5 _GPIO(37) -#define STN8815_PIN_AB4 _GPIO(38) -#define STN8815_PIN_Y4 _GPIO(39) -#define STN8815_PIN_R1 _GPIO(40) -#define STN8815_PIN_R2 _GPIO(41) -#define STN8815_PIN_R3 _GPIO(42) -#define STN8815_PIN_P1 _GPIO(43) -#define STN8815_PIN_P2 _GPIO(44) -#define STN8815_PIN_P3 _GPIO(45) -#define STN8815_PIN_N1 _GPIO(46) -#define STN8815_PIN_N2 _GPIO(47) -#define STN8815_PIN_N3 _GPIO(48) -#define STN8815_PIN_M1 _GPIO(49) -#define STN8815_PIN_M3 _GPIO(50) -#define STN8815_PIN_M2 _GPIO(51) -#define STN8815_PIN_L1 _GPIO(52) -#define STN8815_PIN_L4 _GPIO(53) -#define STN8815_PIN_L3 _GPIO(54) -#define STN8815_PIN_L2 _GPIO(55) -#define STN8815_PIN_F3 _GPIO(56) -#define STN8815_PIN_F2 _GPIO(57) -#define STN8815_PIN_E1 _GPIO(58) -#define STN8815_PIN_E3 _GPIO(59) -#define STN8815_PIN_E2 _GPIO(60) -#define STN8815_PIN_E4 _GPIO(61) -#define STN8815_PIN_D3 _GPIO(62) -#define STN8815_PIN_D2 _GPIO(63) -#define STN8815_PIN_F21 _GPIO(64) -#define STN8815_PIN_F20 _GPIO(65) -#define STN8815_PIN_E22 _GPIO(66) -#define STN8815_PIN_D22 _GPIO(67) -#define STN8815_PIN_E21 _GPIO(68) -#define STN8815_PIN_E20 _GPIO(69) -#define STN8815_PIN_C22 _GPIO(70) -#define STN8815_PIN_D21 _GPIO(71) -#define STN8815_PIN_D20 _GPIO(72) -#define STN8815_PIN_C21 _GPIO(73) -#define STN8815_PIN_C20 _GPIO(74) -#define STN8815_PIN_C19 _GPIO(75) -#define STN8815_PIN_B20 _GPIO(76) -#define STN8815_PIN_B8 _GPIO(77) -#define STN8815_PIN_A8 _GPIO(78) -#define STN8815_PIN_C9 _GPIO(79) -#define STN8815_PIN_B9 _GPIO(80) -#define STN8815_PIN_A9 _GPIO(81) -#define STN8815_PIN_C10 _GPIO(82) -#define STN8815_PIN_K1 _GPIO(83) -#define STN8815_PIN_K3 _GPIO(84) -#define STN8815_PIN_K2 _GPIO(85) -#define STN8815_PIN_J1 _GPIO(86) -#define STN8815_PIN_J3 _GPIO(87) -#define STN8815_PIN_J2 _GPIO(88) -#define STN8815_PIN_H1 _GPIO(89) -#define STN8815_PIN_H3 _GPIO(90) -#define STN8815_PIN_H2 _GPIO(91) -#define STN8815_PIN_G1 _GPIO(92) -#define STN8815_PIN_G3 _GPIO(93) -#define STN8815_PIN_G2 _GPIO(94) -#define STN8815_PIN_F1 _GPIO(95) -#define STN8815_PIN_T20 _GPIO(96) -#define STN8815_PIN_R21 _GPIO(97) -#define STN8815_PIN_R20 _GPIO(98) -#define STN8815_PIN_U22 _GPIO(99) -#define STN8815_PIN_N21 _GPIO(100) -#define STN8815_PIN_N20 _GPIO(101) -#define STN8815_PIN_P22 _GPIO(102) -#define STN8815_PIN_N22 _GPIO(103) -#define STN8815_PIN_V22 _GPIO(104) -#define STN8815_PIN_V21 _GPIO(105) -#define STN8815_PIN_K22 _GPIO(106) -#define STN8815_PIN_K21 _GPIO(107) -#define STN8815_PIN_H20 _GPIO(108) -#define STN8815_PIN_G20 _GPIO(109) -#define STN8815_PIN_L21 _GPIO(110) -#define STN8815_PIN_H21 _GPIO(111) -#define STN8815_PIN_J21 _GPIO(112) -#define STN8815_PIN_H22 _GPIO(113) -#define STN8815_PIN_K20 _GPIO(114) -#define STN8815_PIN_L22 _GPIO(115) -#define STN8815_PIN_G21 _GPIO(116) -#define STN8815_PIN_J20 _GPIO(117) -#define STN8815_PIN_G22 _GPIO(118) -#define STN8815_PIN_U19 _GPIO(119) -#define STN8815_PIN_G19 _GPIO(120) -#define STN8815_PIN_M22 _GPIO(121) -#define STN8815_PIN_M19 _GPIO(122) -#define STN8815_PIN_J22 _GPIO(123) -/* GPIOs 124-127 not routed to pins */ - -/* - * The names of the pins are denoted by GPIO number and ball name, even - * though they can be used for other things than GPIO, this is the first - * column in the table of the data sheet and often used on schematics and - * such. - */ -static const struct pinctrl_pin_desc nmk_stn8815_pins[] = { - PINCTRL_PIN(STN8815_PIN_B4, "GPIO0_B4"), - PINCTRL_PIN(STN8815_PIN_D5, "GPIO1_D5"), - PINCTRL_PIN(STN8815_PIN_C5, "GPIO2_C5"), - PINCTRL_PIN(STN8815_PIN_A4, "GPIO3_A4"), - PINCTRL_PIN(STN8815_PIN_B5, "GPIO4_B5"), - PINCTRL_PIN(STN8815_PIN_D6, "GPIO5_D6"), - PINCTRL_PIN(STN8815_PIN_C6, "GPIO6_C6"), - PINCTRL_PIN(STN8815_PIN_B6, "GPIO7_B6"), - PINCTRL_PIN(STN8815_PIN_B10, "GPIO8_B10"), - PINCTRL_PIN(STN8815_PIN_A10, "GPIO9_A10"), - PINCTRL_PIN(STN8815_PIN_C11, "GPIO10_C11"), - PINCTRL_PIN(STN8815_PIN_B11, "GPIO11_B11"), - PINCTRL_PIN(STN8815_PIN_A11, "GPIO12_A11"), - PINCTRL_PIN(STN8815_PIN_C12, "GPIO13_C12"), - PINCTRL_PIN(STN8815_PIN_B12, "GPIO14_B12"), - PINCTRL_PIN(STN8815_PIN_A12, "GPIO15_A12"), - PINCTRL_PIN(STN8815_PIN_C13, "GPIO16_C13"), - PINCTRL_PIN(STN8815_PIN_B13, "GPIO17_B13"), - PINCTRL_PIN(STN8815_PIN_A13, "GPIO18_A13"), - PINCTRL_PIN(STN8815_PIN_D13, "GPIO19_D13"), - PINCTRL_PIN(STN8815_PIN_C14, "GPIO20_C14"), - PINCTRL_PIN(STN8815_PIN_B14, "GPIO21_B14"), - PINCTRL_PIN(STN8815_PIN_A14, "GPIO22_A14"), - PINCTRL_PIN(STN8815_PIN_D15, "GPIO23_D15"), - PINCTRL_PIN(STN8815_PIN_C15, "GPIO24_C15"), - PINCTRL_PIN(STN8815_PIN_B15, "GPIO25_B15"), - PINCTRL_PIN(STN8815_PIN_A15, "GPIO26_A15"), - PINCTRL_PIN(STN8815_PIN_C16, "GPIO27_C16"), - PINCTRL_PIN(STN8815_PIN_B16, "GPIO28_B16"), - PINCTRL_PIN(STN8815_PIN_A16, "GPIO29_A16"), - PINCTRL_PIN(STN8815_PIN_D17, "GPIO30_D17"), - PINCTRL_PIN(STN8815_PIN_C17, "GPIO31_C17"), - PINCTRL_PIN(STN8815_PIN_AB6, "GPIO32_AB6"), - PINCTRL_PIN(STN8815_PIN_AA6, "GPIO33_AA6"), - PINCTRL_PIN(STN8815_PIN_Y6, "GPIO34_Y6"), - PINCTRL_PIN(STN8815_PIN_Y5, "GPIO35_Y5"), - PINCTRL_PIN(STN8815_PIN_AA5, "GPIO36_AA5"), - PINCTRL_PIN(STN8815_PIN_AB5, "GPIO37_AB5"), - PINCTRL_PIN(STN8815_PIN_AB4, "GPIO38_AB4"), - PINCTRL_PIN(STN8815_PIN_Y4, "GPIO39_Y4"), - PINCTRL_PIN(STN8815_PIN_R1, "GPIO40_R1"), - PINCTRL_PIN(STN8815_PIN_R2, "GPIO41_R2"), - PINCTRL_PIN(STN8815_PIN_R3, "GPIO42_R3"), - PINCTRL_PIN(STN8815_PIN_P1, "GPIO43_P1"), - PINCTRL_PIN(STN8815_PIN_P2, "GPIO44_P2"), - PINCTRL_PIN(STN8815_PIN_P3, "GPIO45_P3"), - PINCTRL_PIN(STN8815_PIN_N1, "GPIO46_N1"), - PINCTRL_PIN(STN8815_PIN_N2, "GPIO47_N2"), - PINCTRL_PIN(STN8815_PIN_N3, "GPIO48_N3"), - PINCTRL_PIN(STN8815_PIN_M1, "GPIO49_M1"), - PINCTRL_PIN(STN8815_PIN_M3, "GPIO50_M3"), - PINCTRL_PIN(STN8815_PIN_M2, "GPIO51_M2"), - PINCTRL_PIN(STN8815_PIN_L1, "GPIO52_L1"), - PINCTRL_PIN(STN8815_PIN_L4, "GPIO53_L4"), - PINCTRL_PIN(STN8815_PIN_L3, "GPIO54_L3"), - PINCTRL_PIN(STN8815_PIN_L2, "GPIO55_L2"), - PINCTRL_PIN(STN8815_PIN_F3, "GPIO56_F3"), - PINCTRL_PIN(STN8815_PIN_F2, "GPIO57_F2"), - PINCTRL_PIN(STN8815_PIN_E1, "GPIO58_E1"), - PINCTRL_PIN(STN8815_PIN_E3, "GPIO59_E3"), - PINCTRL_PIN(STN8815_PIN_E2, "GPIO60_E2"), - PINCTRL_PIN(STN8815_PIN_E4, "GPIO61_E4"), - PINCTRL_PIN(STN8815_PIN_D3, "GPIO62_D3"), - PINCTRL_PIN(STN8815_PIN_D2, "GPIO63_D2"), - PINCTRL_PIN(STN8815_PIN_F21, "GPIO64_F21"), - PINCTRL_PIN(STN8815_PIN_F20, "GPIO65_F20"), - PINCTRL_PIN(STN8815_PIN_E22, "GPIO66_E22"), - PINCTRL_PIN(STN8815_PIN_D22, "GPIO67_D22"), - PINCTRL_PIN(STN8815_PIN_E21, "GPIO68_E21"), - PINCTRL_PIN(STN8815_PIN_E20, "GPIO69_E20"), - PINCTRL_PIN(STN8815_PIN_C22, "GPIO70_C22"), - PINCTRL_PIN(STN8815_PIN_D21, "GPIO71_D21"), - PINCTRL_PIN(STN8815_PIN_D20, "GPIO72_D20"), - PINCTRL_PIN(STN8815_PIN_C21, "GPIO73_C21"), - PINCTRL_PIN(STN8815_PIN_C20, "GPIO74_C20"), - PINCTRL_PIN(STN8815_PIN_C19, "GPIO75_C19"), - PINCTRL_PIN(STN8815_PIN_B20, "GPIO76_B20"), - PINCTRL_PIN(STN8815_PIN_B8, "GPIO77_B8"), - PINCTRL_PIN(STN8815_PIN_A8, "GPIO78_A8"), - PINCTRL_PIN(STN8815_PIN_C9, "GPIO79_C9"), - PINCTRL_PIN(STN8815_PIN_B9, "GPIO80_B9"), - PINCTRL_PIN(STN8815_PIN_A9, "GPIO81_A9"), - PINCTRL_PIN(STN8815_PIN_C10, "GPIO82_C10"), - PINCTRL_PIN(STN8815_PIN_K1, "GPIO83_K1"), - PINCTRL_PIN(STN8815_PIN_K3, "GPIO84_K3"), - PINCTRL_PIN(STN8815_PIN_K2, "GPIO85_K2"), - PINCTRL_PIN(STN8815_PIN_J1, "GPIO86_J1"), - PINCTRL_PIN(STN8815_PIN_J3, "GPIO87_J3"), - PINCTRL_PIN(STN8815_PIN_J2, "GPIO88_J2"), - PINCTRL_PIN(STN8815_PIN_H1, "GPIO89_H1"), - PINCTRL_PIN(STN8815_PIN_H3, "GPIO90_H3"), - PINCTRL_PIN(STN8815_PIN_H2, "GPIO91_H2"), - PINCTRL_PIN(STN8815_PIN_G1, "GPIO92_G1"), - PINCTRL_PIN(STN8815_PIN_G3, "GPIO93_G3"), - PINCTRL_PIN(STN8815_PIN_G2, "GPIO94_G2"), - PINCTRL_PIN(STN8815_PIN_F1, "GPIO95_F1"), - PINCTRL_PIN(STN8815_PIN_T20, "GPIO96_T20"), - PINCTRL_PIN(STN8815_PIN_R21, "GPIO97_R21"), - PINCTRL_PIN(STN8815_PIN_R20, "GPIO98_R20"), - PINCTRL_PIN(STN8815_PIN_U22, "GPIO99_U22"), - PINCTRL_PIN(STN8815_PIN_N21, "GPIO100_N21"), - PINCTRL_PIN(STN8815_PIN_N20, "GPIO101_N20"), - PINCTRL_PIN(STN8815_PIN_P22, "GPIO102_P22"), - PINCTRL_PIN(STN8815_PIN_N22, "GPIO103_N22"), - PINCTRL_PIN(STN8815_PIN_V22, "GPIO104_V22"), - PINCTRL_PIN(STN8815_PIN_V21, "GPIO105_V21"), - PINCTRL_PIN(STN8815_PIN_K22, "GPIO106_K22"), - PINCTRL_PIN(STN8815_PIN_K21, "GPIO107_K21"), - PINCTRL_PIN(STN8815_PIN_H20, "GPIO108_H20"), - PINCTRL_PIN(STN8815_PIN_G20, "GPIO109_G20"), - PINCTRL_PIN(STN8815_PIN_L21, "GPIO110_L21"), - PINCTRL_PIN(STN8815_PIN_H21, "GPIO111_H21"), - PINCTRL_PIN(STN8815_PIN_J21, "GPIO112_J21"), - PINCTRL_PIN(STN8815_PIN_H22, "GPIO113_H22"), - PINCTRL_PIN(STN8815_PIN_K20, "GPIO114_K20"), - PINCTRL_PIN(STN8815_PIN_L22, "GPIO115_L22"), - PINCTRL_PIN(STN8815_PIN_G21, "GPIO116_G21"), - PINCTRL_PIN(STN8815_PIN_J20, "GPIO117_J20"), - PINCTRL_PIN(STN8815_PIN_G22, "GPIO118_G22"), - PINCTRL_PIN(STN8815_PIN_U19, "GPIO119_U19"), - PINCTRL_PIN(STN8815_PIN_G19, "GPIO120_G19"), - PINCTRL_PIN(STN8815_PIN_M22, "GPIO121_M22"), - PINCTRL_PIN(STN8815_PIN_M19, "GPIO122_M19"), - PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"), -}; - -#define STN8815_GPIO_RANGE(a, b, c) { .name = "STN8815", .id = a, .base = b, \ - .pin_base = b, .npins = c } - -/* - * This matches the 32-pin gpio chips registered by the GPIO portion. This - * cannot be const since we assign the struct gpio_chip * pointer at runtime. - */ -static struct pinctrl_gpio_range nmk_stn8815_ranges[] = { - STN8815_GPIO_RANGE(0, 0, 32), - STN8815_GPIO_RANGE(1, 32, 32), - STN8815_GPIO_RANGE(2, 64, 32), - STN8815_GPIO_RANGE(3, 96, 28), -}; - -/* - * Read the pin group names like this: - * u0_a_1 = first groups of pins for uart0 on alt function a - * i2c2_b_2 = second group of pins for i2c2 on alt function b - */ - -/* Altfunction A */ -static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5, - STN8815_PIN_C5, STN8815_PIN_A4, STN8815_PIN_B5, STN8815_PIN_D6, - STN8815_PIN_C6, STN8815_PIN_B6 }; -static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10, - STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12, - STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 }; -static const unsigned u1_a_1_pins[] = { STN8815_PIN_M2, STN8815_PIN_L1, - STN8815_PIN_F3, STN8815_PIN_F2 }; -static const unsigned i2c1_a_1_pins[] = { STN8815_PIN_L4, STN8815_PIN_L3 }; -static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 }; -/* Altfunction B */ -static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 }; -static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 }; - -#define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ - .npins = ARRAY_SIZE(a##_pins), .altsetting = b } - -static const struct nmk_pingroup nmk_stn8815_groups[] = { - STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), - STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A), - STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A), - STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A), - STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), - STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B), - STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B), -}; - -/* We use this macro to define the groups applicable to a function */ -#define STN8815_FUNC_GROUPS(a, b...) \ -static const char * const a##_groups[] = { b }; - -STN8815_FUNC_GROUPS(u0, "u0_a_1"); -STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1"); -STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1"); -STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1"); -STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1"); -STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1"); - -#define FUNCTION(fname) \ - { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -static const struct nmk_function nmk_stn8815_functions[] = { - FUNCTION(u0), - FUNCTION(mmcsd), - FUNCTION(u1), - FUNCTION(i2c1), - FUNCTION(i2c0), - FUNCTION(i2cusb), -}; - -static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = { - .gpio_ranges = nmk_stn8815_ranges, - .gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges), - .pins = nmk_stn8815_pins, - .npins = ARRAY_SIZE(nmk_stn8815_pins), - .functions = nmk_stn8815_functions, - .nfunctions = ARRAY_SIZE(nmk_stn8815_functions), - .groups = nmk_stn8815_groups, - .ngroups = ARRAY_SIZE(nmk_stn8815_groups), -}; - -void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc) -{ - *soc = &nmk_stn8815_soc; -} diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c deleted file mode 100644 index a564251fe093..000000000000 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ /dev/null @@ -1,2099 +0,0 @@ -/* - * Generic GPIO driver for logic cells found in the Nomadik SoC - * - * Copyright (C) 2008,2009 STMicroelectronics - * Copyright (C) 2009 Alessandro Rubini - * Rewritten based on work by Prafulla WADASKAR - * Copyright (C) 2011-2013 Linus Walleij - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -/* Since we request GPIOs from ourself */ -#include -#include "pinctrl-nomadik.h" -#include "core.h" - -/* - * The GPIO module in the Nomadik family of Systems-on-Chip is an - * AMBA device, managing 32 pins and alternate functions. The logic block - * is currently used in the Nomadik and ux500. - * - * Symbols in this file are called "nmk_gpio" for "nomadik gpio" - */ - -/* - * pin configurations are represented by 32-bit integers: - * - * bit 0.. 8 - Pin Number (512 Pins Maximum) - * bit 9..10 - Alternate Function Selection - * bit 11..12 - Pull up/down state - * bit 13 - Sleep mode behaviour - * bit 14 - Direction - * bit 15 - Value (if output) - * bit 16..18 - SLPM pull up/down state - * bit 19..20 - SLPM direction - * bit 21..22 - SLPM Value (if output) - * bit 23..25 - PDIS value (if input) - * bit 26 - Gpio mode - * bit 27 - Sleep mode - * - * to facilitate the definition, the following macros are provided - * - * PIN_CFG_DEFAULT - default config (0): - * pull up/down = disabled - * sleep mode = input/wakeup - * direction = input - * value = low - * SLPM direction = same as normal - * SLPM pull = same as normal - * SLPM value = same as normal - * - * PIN_CFG - default config with alternate function - */ - -typedef unsigned long pin_cfg_t; - -#define PIN_NUM_MASK 0x1ff -#define PIN_NUM(x) ((x) & PIN_NUM_MASK) - -#define PIN_ALT_SHIFT 9 -#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) -#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) -#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) -#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) -#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) -#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) - -#define PIN_PULL_SHIFT 11 -#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) -#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) -#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) -#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) -#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) - -#define PIN_SLPM_SHIFT 13 -#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) -#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) -#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) -#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) -/* These two replace the above in DB8500v2+ */ -#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) -#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) -#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE - -#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ -#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ - -#define PIN_DIR_SHIFT 14 -#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) -#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) -#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) -#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) - -#define PIN_VAL_SHIFT 15 -#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) -#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) -#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) -#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) - -#define PIN_SLPM_PULL_SHIFT 16 -#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL(x) \ - (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_NONE \ - ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_UP \ - ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_DOWN \ - ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) - -#define PIN_SLPM_DIR_SHIFT 19 -#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR(x) \ - (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) - -#define PIN_SLPM_VAL_SHIFT 21 -#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL(x) \ - (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) - -#define PIN_SLPM_PDIS_SHIFT 23 -#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) -#define PIN_SLPM_PDIS(x) \ - (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) -#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) -#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) -#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) - -#define PIN_LOWEMI_SHIFT 25 -#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) -#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) -#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) -#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) - -#define PIN_GPIOMODE_SHIFT 26 -#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) -#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) -#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) -#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) - -#define PIN_SLEEPMODE_SHIFT 27 -#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) -#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) -#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) -#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) - - -/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ -#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) -#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) -#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) -#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) -#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) - -#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) -#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) -#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) -#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) -#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) - -#define PIN_CFG_DEFAULT (0) - -#define PIN_CFG(num, alt) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt)) - -#define PIN_CFG_INPUT(num, alt, pull) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) - -#define PIN_CFG_OUTPUT(num, alt, val) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) - -/* - * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving - * the "gpio" namespace for generic and cross-machine functions - */ - -#define GPIO_BLOCK_SHIFT 5 -#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) - -/* Register in the logic block */ -#define NMK_GPIO_DAT 0x00 -#define NMK_GPIO_DATS 0x04 -#define NMK_GPIO_DATC 0x08 -#define NMK_GPIO_PDIS 0x0c -#define NMK_GPIO_DIR 0x10 -#define NMK_GPIO_DIRS 0x14 -#define NMK_GPIO_DIRC 0x18 -#define NMK_GPIO_SLPC 0x1c -#define NMK_GPIO_AFSLA 0x20 -#define NMK_GPIO_AFSLB 0x24 -#define NMK_GPIO_LOWEMI 0x28 - -#define NMK_GPIO_RIMSC 0x40 -#define NMK_GPIO_FIMSC 0x44 -#define NMK_GPIO_IS 0x48 -#define NMK_GPIO_IC 0x4c -#define NMK_GPIO_RWIMSC 0x50 -#define NMK_GPIO_FWIMSC 0x54 -#define NMK_GPIO_WKS 0x58 -/* These appear in DB8540 and later ASICs */ -#define NMK_GPIO_EDGELEVEL 0x5C -#define NMK_GPIO_LEVEL 0x60 - - -/* Pull up/down values */ -enum nmk_gpio_pull { - NMK_GPIO_PULL_NONE, - NMK_GPIO_PULL_UP, - NMK_GPIO_PULL_DOWN, -}; - -/* Sleep mode */ -enum nmk_gpio_slpm { - NMK_GPIO_SLPM_INPUT, - NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, - NMK_GPIO_SLPM_NOCHANGE, - NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, -}; - -struct nmk_gpio_chip { - struct gpio_chip chip; - void __iomem *addr; - struct clk *clk; - unsigned int bank; - unsigned int parent_irq; - int latent_parent_irq; - u32 (*get_latent_status)(unsigned int bank); - void (*set_ioforce)(bool enable); - spinlock_t lock; - bool sleepmode; - /* Keep track of configured edges */ - u32 edge_rising; - u32 edge_falling; - u32 real_wake; - u32 rwimsc; - u32 fwimsc; - u32 rimsc; - u32 fimsc; - u32 pull_up; - u32 lowemi; -}; - -/** - * struct nmk_pinctrl - state container for the Nomadik pin controller - * @dev: containing device pointer - * @pctl: corresponding pin controller device - * @soc: SoC data for this specific chip - * @prcm_base: PRCM register range virtual base - */ -struct nmk_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - const struct nmk_pinctrl_soc_data *soc; - void __iomem *prcm_base; -}; - -static struct nmk_gpio_chip * -nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; - -static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); - -#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) - -static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, - unsigned offset, int gpio_mode) -{ - u32 bit = 1 << offset; - u32 afunc, bfunc; - - afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; - bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; - if (gpio_mode & NMK_GPIO_ALT_A) - afunc |= bit; - if (gpio_mode & NMK_GPIO_ALT_B) - bfunc |= bit; - writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); - writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); -} - -static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, - unsigned offset, enum nmk_gpio_slpm mode) -{ - u32 bit = 1 << offset; - u32 slpm; - - slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); - if (mode == NMK_GPIO_SLPM_NOCHANGE) - slpm |= bit; - else - slpm &= ~bit; - writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); -} - -static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, - unsigned offset, enum nmk_gpio_pull pull) -{ - u32 bit = 1 << offset; - u32 pdis; - - pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); - if (pull == NMK_GPIO_PULL_NONE) { - pdis |= bit; - nmk_chip->pull_up &= ~bit; - } else { - pdis &= ~bit; - } - - writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); - - if (pull == NMK_GPIO_PULL_UP) { - nmk_chip->pull_up |= bit; - writel(bit, nmk_chip->addr + NMK_GPIO_DATS); - } else if (pull == NMK_GPIO_PULL_DOWN) { - nmk_chip->pull_up &= ~bit; - writel(bit, nmk_chip->addr + NMK_GPIO_DATC); - } -} - -static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, - unsigned offset, bool lowemi) -{ - u32 bit = BIT(offset); - bool enabled = nmk_chip->lowemi & bit; - - if (lowemi == enabled) - return; - - if (lowemi) - nmk_chip->lowemi |= bit; - else - nmk_chip->lowemi &= ~bit; - - writel_relaxed(nmk_chip->lowemi, - nmk_chip->addr + NMK_GPIO_LOWEMI); -} - -static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, - unsigned offset) -{ - writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); -} - -static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, - unsigned offset, int val) -{ - if (val) - writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); - else - writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); -} - -static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, - unsigned offset, int val) -{ - writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); - __nmk_gpio_set_output(nmk_chip, offset, val); -} - -static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, - unsigned offset, int gpio_mode, - bool glitch) -{ - u32 rwimsc = nmk_chip->rwimsc; - u32 fwimsc = nmk_chip->fwimsc; - - if (glitch && nmk_chip->set_ioforce) { - u32 bit = BIT(offset); - - /* Prevent spurious wakeups */ - writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); - writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); - - nmk_chip->set_ioforce(true); - } - - __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); - - if (glitch && nmk_chip->set_ioforce) { - nmk_chip->set_ioforce(false); - - writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); - writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); - } -} - -static void -nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) -{ - u32 falling = nmk_chip->fimsc & BIT(offset); - u32 rising = nmk_chip->rimsc & BIT(offset); - int gpio = nmk_chip->chip.base + offset; - int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); - struct irq_data *d = irq_get_irq_data(irq); - - if (!rising && !falling) - return; - - if (!d || !irqd_irq_disabled(d)) - return; - - if (rising) { - nmk_chip->rimsc &= ~BIT(offset); - writel_relaxed(nmk_chip->rimsc, - nmk_chip->addr + NMK_GPIO_RIMSC); - } - - if (falling) { - nmk_chip->fimsc &= ~BIT(offset); - writel_relaxed(nmk_chip->fimsc, - nmk_chip->addr + NMK_GPIO_FIMSC); - } - - dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); -} - -static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) -{ - u32 val; - - val = readl(reg); - val = ((val & ~mask) | (value & mask)); - writel(val, reg); -} - -static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, - unsigned offset, unsigned alt_num) -{ - int i; - u16 reg; - u8 bit; - u8 alt_index; - const struct prcm_gpiocr_altcx_pin_desc *pin_desc; - const u16 *gpiocr_regs; - - if (!npct->prcm_base) - return; - - if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { - dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", - alt_num); - return; - } - - for (i = 0 ; i < npct->soc->npins_altcx ; i++) { - if (npct->soc->altcx_pins[i].pin == offset) - break; - } - if (i == npct->soc->npins_altcx) { - dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", - offset); - return; - } - - pin_desc = npct->soc->altcx_pins + i; - gpiocr_regs = npct->soc->prcm_gpiocr_registers; - - /* - * If alt_num is NULL, just clear current ALTCx selection - * to make sure we come back to a pure ALTC selection - */ - if (!alt_num) { - for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { - if (pin_desc->altcx[i].used == true) { - reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; - bit = pin_desc->altcx[i].control_bit; - if (readl(npct->prcm_base + reg) & BIT(bit)) { - nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); - dev_dbg(npct->dev, - "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", - offset, i+1); - } - } - } - return; - } - - alt_index = alt_num - 1; - if (pin_desc->altcx[alt_index].used == false) { - dev_warn(npct->dev, - "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", - offset, alt_num); - return; - } - - /* - * Check if any other ALTCx functions are activated on this pin - * and disable it first. - */ - for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { - if (i == alt_index) - continue; - if (pin_desc->altcx[i].used == true) { - reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; - bit = pin_desc->altcx[i].control_bit; - if (readl(npct->prcm_base + reg) & BIT(bit)) { - nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); - dev_dbg(npct->dev, - "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", - offset, i+1); - } - } - } - - reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; - bit = pin_desc->altcx[alt_index].control_bit; - dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", - offset, alt_index+1); - nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); -} - -/* - * Safe sequence used to switch IOs between GPIO and Alternate-C mode: - * - Save SLPM registers - * - Set SLPM=0 for the IOs you want to switch and others to 1 - * - Configure the GPIO registers for the IOs that are being switched - * - Set IOFORCE=1 - * - Modify the AFLSA/B registers for the IOs that are being switched - * - Set IOFORCE=0 - * - Restore SLPM registers - * - Any spurious wake up event during switch sequence to be ignored and - * cleared - */ -static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) -{ - int i; - - for (i = 0; i < NUM_BANKS; i++) { - struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; - unsigned int temp = slpm[i]; - - if (!chip) - break; - - clk_enable(chip->clk); - - slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); - writel(temp, chip->addr + NMK_GPIO_SLPC); - } -} - -static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) -{ - int i; - - for (i = 0; i < NUM_BANKS; i++) { - struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; - - if (!chip) - break; - - writel(slpm[i], chip->addr + NMK_GPIO_SLPC); - - clk_disable(chip->clk); - } -} - -static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) -{ - int i; - u16 reg; - u8 bit; - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - const struct prcm_gpiocr_altcx_pin_desc *pin_desc; - const u16 *gpiocr_regs; - - if (!npct->prcm_base) - return NMK_GPIO_ALT_C; - - for (i = 0; i < npct->soc->npins_altcx; i++) { - if (npct->soc->altcx_pins[i].pin == gpio) - break; - } - if (i == npct->soc->npins_altcx) - return NMK_GPIO_ALT_C; - - pin_desc = npct->soc->altcx_pins + i; - gpiocr_regs = npct->soc->prcm_gpiocr_registers; - for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { - if (pin_desc->altcx[i].used == true) { - reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; - bit = pin_desc->altcx[i].control_bit; - if (readl(npct->prcm_base + reg) & BIT(bit)) - return NMK_GPIO_ALT_C+i+1; - } - } - return NMK_GPIO_ALT_C; -} - -int nmk_gpio_get_mode(int gpio) -{ - struct nmk_gpio_chip *nmk_chip; - u32 afunc, bfunc, bit; - - nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; - if (!nmk_chip) - return -EINVAL; - - bit = 1 << (gpio % NMK_GPIO_PER_CHIP); - - clk_enable(nmk_chip->clk); - - afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; - bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; - - clk_disable(nmk_chip->clk); - - return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); -} -EXPORT_SYMBOL(nmk_gpio_get_mode); - - -/* IRQ functions */ -static inline int nmk_gpio_get_bitmask(int gpio) -{ - return 1 << (gpio % NMK_GPIO_PER_CHIP); -} - -static void nmk_gpio_irq_ack(struct irq_data *d) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(d); - struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - - clk_enable(nmk_chip->clk); - writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); - clk_disable(nmk_chip->clk); -} - -enum nmk_gpio_irq_type { - NORMAL, - WAKE, -}; - -static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, - int gpio, enum nmk_gpio_irq_type which, - bool enable) -{ - u32 bitmask = nmk_gpio_get_bitmask(gpio); - u32 *rimscval; - u32 *fimscval; - u32 rimscreg; - u32 fimscreg; - - if (which == NORMAL) { - rimscreg = NMK_GPIO_RIMSC; - fimscreg = NMK_GPIO_FIMSC; - rimscval = &nmk_chip->rimsc; - fimscval = &nmk_chip->fimsc; - } else { - rimscreg = NMK_GPIO_RWIMSC; - fimscreg = NMK_GPIO_FWIMSC; - rimscval = &nmk_chip->rwimsc; - fimscval = &nmk_chip->fwimsc; - } - - /* we must individually set/clear the two edges */ - if (nmk_chip->edge_rising & bitmask) { - if (enable) - *rimscval |= bitmask; - else - *rimscval &= ~bitmask; - writel(*rimscval, nmk_chip->addr + rimscreg); - } - if (nmk_chip->edge_falling & bitmask) { - if (enable) - *fimscval |= bitmask; - else - *fimscval &= ~bitmask; - writel(*fimscval, nmk_chip->addr + fimscreg); - } -} - -static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, - int gpio, bool on) -{ - /* - * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is - * disabled, since setting SLPM to 1 increases power consumption, and - * wakeup is anyhow controlled by the RIMSC and FIMSC registers. - */ - if (nmk_chip->sleepmode && on) { - __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, - NMK_GPIO_SLPM_WAKEUP_ENABLE); - } - - __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); -} - -static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) -{ - struct nmk_gpio_chip *nmk_chip; - unsigned long flags; - u32 bitmask; - - nmk_chip = irq_data_get_irq_chip_data(d); - bitmask = nmk_gpio_get_bitmask(d->hwirq); - if (!nmk_chip) - return -EINVAL; - - clk_enable(nmk_chip->clk); - spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); - spin_lock(&nmk_chip->lock); - - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); - - if (!(nmk_chip->real_wake & bitmask)) - __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); - - spin_unlock(&nmk_chip->lock); - spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); - clk_disable(nmk_chip->clk); - - return 0; -} - -static void nmk_gpio_irq_mask(struct irq_data *d) -{ - nmk_gpio_irq_maskunmask(d, false); -} - -static void nmk_gpio_irq_unmask(struct irq_data *d) -{ - nmk_gpio_irq_maskunmask(d, true); -} - -static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) -{ - struct nmk_gpio_chip *nmk_chip; - unsigned long flags; - u32 bitmask; - - nmk_chip = irq_data_get_irq_chip_data(d); - if (!nmk_chip) - return -EINVAL; - bitmask = nmk_gpio_get_bitmask(d->hwirq); - - clk_enable(nmk_chip->clk); - spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); - spin_lock(&nmk_chip->lock); - - if (irqd_irq_disabled(d)) - __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); - - if (on) - nmk_chip->real_wake |= bitmask; - else - nmk_chip->real_wake &= ~bitmask; - - spin_unlock(&nmk_chip->lock); - spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); - clk_disable(nmk_chip->clk); - - return 0; -} - -static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) -{ - bool enabled = !irqd_irq_disabled(d); - bool wake = irqd_is_wakeup_set(d); - struct nmk_gpio_chip *nmk_chip; - unsigned long flags; - u32 bitmask; - - nmk_chip = irq_data_get_irq_chip_data(d); - bitmask = nmk_gpio_get_bitmask(d->hwirq); - if (!nmk_chip) - return -EINVAL; - if (type & IRQ_TYPE_LEVEL_HIGH) - return -EINVAL; - if (type & IRQ_TYPE_LEVEL_LOW) - return -EINVAL; - - clk_enable(nmk_chip->clk); - spin_lock_irqsave(&nmk_chip->lock, flags); - - if (enabled) - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); - - if (enabled || wake) - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); - - nmk_chip->edge_rising &= ~bitmask; - if (type & IRQ_TYPE_EDGE_RISING) - nmk_chip->edge_rising |= bitmask; - - nmk_chip->edge_falling &= ~bitmask; - if (type & IRQ_TYPE_EDGE_FALLING) - nmk_chip->edge_falling |= bitmask; - - if (enabled) - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); - - if (enabled || wake) - __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); - - spin_unlock_irqrestore(&nmk_chip->lock, flags); - clk_disable(nmk_chip->clk); - - return 0; -} - -static unsigned int nmk_gpio_irq_startup(struct irq_data *d) -{ - struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); - - clk_enable(nmk_chip->clk); - nmk_gpio_irq_unmask(d); - return 0; -} - -static void nmk_gpio_irq_shutdown(struct irq_data *d) -{ - struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); - - nmk_gpio_irq_mask(d); - clk_disable(nmk_chip->clk); -} - -static struct irq_chip nmk_gpio_irq_chip = { - .name = "Nomadik-GPIO", - .irq_ack = nmk_gpio_irq_ack, - .irq_mask = nmk_gpio_irq_mask, - .irq_unmask = nmk_gpio_irq_unmask, - .irq_set_type = nmk_gpio_irq_set_type, - .irq_set_wake = nmk_gpio_irq_set_wake, - .irq_startup = nmk_gpio_irq_startup, - .irq_shutdown = nmk_gpio_irq_shutdown, - .flags = IRQCHIP_MASK_ON_SUSPEND, -}; - -static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, - u32 status) -{ - struct irq_chip *host_chip = irq_get_chip(irq); - struct gpio_chip *chip = irq_desc_get_handler_data(desc); - - chained_irq_enter(host_chip, desc); - - while (status) { - int bit = __ffs(status); - - generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); - status &= ~BIT(bit); - } - - chained_irq_exit(host_chip, desc); -} - -static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - struct gpio_chip *chip = irq_desc_get_handler_data(desc); - struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - u32 status; - - clk_enable(nmk_chip->clk); - status = readl(nmk_chip->addr + NMK_GPIO_IS); - clk_disable(nmk_chip->clk); - - __nmk_gpio_irq_handler(irq, desc, status); -} - -static void nmk_gpio_latent_irq_handler(unsigned int irq, - struct irq_desc *desc) -{ - struct gpio_chip *chip = irq_desc_get_handler_data(desc); - struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - u32 status = nmk_chip->get_latent_status(nmk_chip->bank); - - __nmk_gpio_irq_handler(irq, desc, status); -} - -/* I/O Functions */ - -static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - /* - * Map back to global GPIO space and request muxing, the direction - * parameter does not matter for this controller. - */ - int gpio = chip->base + offset; - - return pinctrl_request_gpio(gpio); -} - -static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - - pinctrl_free_gpio(gpio); -} - -static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) -{ - struct nmk_gpio_chip *nmk_chip = - container_of(chip, struct nmk_gpio_chip, chip); - - clk_enable(nmk_chip->clk); - - writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); - - clk_disable(nmk_chip->clk); - - return 0; -} - -static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) -{ - struct nmk_gpio_chip *nmk_chip = - container_of(chip, struct nmk_gpio_chip, chip); - u32 bit = 1 << offset; - int value; - - clk_enable(nmk_chip->clk); - - value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; - - clk_disable(nmk_chip->clk); - - return value; -} - -static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, - int val) -{ - struct nmk_gpio_chip *nmk_chip = - container_of(chip, struct nmk_gpio_chip, chip); - - clk_enable(nmk_chip->clk); - - __nmk_gpio_set_output(nmk_chip, offset, val); - - clk_disable(nmk_chip->clk); -} - -static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, - int val) -{ - struct nmk_gpio_chip *nmk_chip = - container_of(chip, struct nmk_gpio_chip, chip); - - clk_enable(nmk_chip->clk); - - __nmk_gpio_make_output(nmk_chip, offset, val); - - clk_disable(nmk_chip->clk); - - return 0; -} - -#ifdef CONFIG_DEBUG_FS - -#include - -static void nmk_gpio_dbg_show_one(struct seq_file *s, - struct pinctrl_dev *pctldev, struct gpio_chip *chip, - unsigned offset, unsigned gpio) -{ - const char *label = gpiochip_is_requested(chip, offset); - struct nmk_gpio_chip *nmk_chip = - container_of(chip, struct nmk_gpio_chip, chip); - int mode; - bool is_out; - bool pull; - u32 bit = 1 << offset; - const char *modes[] = { - [NMK_GPIO_ALT_GPIO] = "gpio", - [NMK_GPIO_ALT_A] = "altA", - [NMK_GPIO_ALT_B] = "altB", - [NMK_GPIO_ALT_C] = "altC", - [NMK_GPIO_ALT_C+1] = "altC1", - [NMK_GPIO_ALT_C+2] = "altC2", - [NMK_GPIO_ALT_C+3] = "altC3", - [NMK_GPIO_ALT_C+4] = "altC4", - }; - - clk_enable(nmk_chip->clk); - is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); - pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); - mode = nmk_gpio_get_mode(gpio); - if ((mode == NMK_GPIO_ALT_C) && pctldev) - mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); - - seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", - gpio, label ?: "(none)", - is_out ? "out" : "in ", - chip->get - ? (chip->get(chip, offset) ? "hi" : "lo") - : "? ", - (mode < 0) ? "unknown" : modes[mode], - pull ? "pull" : "none"); - - if (!is_out) { - int irq = gpio_to_irq(gpio); - struct irq_desc *desc = irq_to_desc(irq); - - /* This races with request_irq(), set_irq_type(), - * and set_irq_wake() ... but those are "rare". - */ - if (irq > 0 && desc && desc->action) { - char *trigger; - u32 bitmask = nmk_gpio_get_bitmask(gpio); - - if (nmk_chip->edge_rising & bitmask) - trigger = "edge-rising"; - else if (nmk_chip->edge_falling & bitmask) - trigger = "edge-falling"; - else - trigger = "edge-undefined"; - - seq_printf(s, " irq-%d %s%s", - irq, trigger, - irqd_is_wakeup_set(&desc->irq_data) - ? " wakeup" : ""); - } - } - clk_disable(nmk_chip->clk); -} - -static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - unsigned i; - unsigned gpio = chip->base; - - for (i = 0; i < chip->ngpio; i++, gpio++) { - nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); - seq_printf(s, "\n"); - } -} - -#else -static inline void nmk_gpio_dbg_show_one(struct seq_file *s, - struct pinctrl_dev *pctldev, - struct gpio_chip *chip, - unsigned offset, unsigned gpio) -{ -} -#define nmk_gpio_dbg_show NULL -#endif - -/* This structure is replicated for each GPIO block allocated at probe time */ -static struct gpio_chip nmk_gpio_template = { - .request = nmk_gpio_request, - .free = nmk_gpio_free, - .direction_input = nmk_gpio_make_input, - .get = nmk_gpio_get_input, - .direction_output = nmk_gpio_make_output, - .set = nmk_gpio_set_output, - .dbg_show = nmk_gpio_dbg_show, - .can_sleep = false, -}; - -void nmk_gpio_clocks_enable(void) -{ - int i; - - for (i = 0; i < NUM_BANKS; i++) { - struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; - - if (!chip) - continue; - - clk_enable(chip->clk); - } -} - -void nmk_gpio_clocks_disable(void) -{ - int i; - - for (i = 0; i < NUM_BANKS; i++) { - struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; - - if (!chip) - continue; - - clk_disable(chip->clk); - } -} - -/* - * Called from the suspend/resume path to only keep the real wakeup interrupts - * (those that have had set_irq_wake() called on them) as wakeup interrupts, - * and not the rest of the interrupts which we needed to have as wakeups for - * cpuidle. - * - * PM ops are not used since this needs to be done at the end, after all the - * other drivers are done with their suspend callbacks. - */ -void nmk_gpio_wakeups_suspend(void) -{ - int i; - - for (i = 0; i < NUM_BANKS; i++) { - struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; - - if (!chip) - break; - - clk_enable(chip->clk); - - writel(chip->rwimsc & chip->real_wake, - chip->addr + NMK_GPIO_RWIMSC); - writel(chip->fwimsc & chip->real_wake, - chip->addr + NMK_GPIO_FWIMSC); - - clk_disable(chip->clk); - } -} - -void nmk_gpio_wakeups_resume(void) -{ - int i; - - for (i = 0; i < NUM_BANKS; i++) { - struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; - - if (!chip) - break; - - clk_enable(chip->clk); - - writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); - writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); - - clk_disable(chip->clk); - } -} - -/* - * Read the pull up/pull down status. - * A bit set in 'pull_up' means that pull up - * is selected if pull is enabled in PDIS register. - * Note: only pull up/down set via this driver can - * be detected due to HW limitations. - */ -void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) -{ - if (gpio_bank < NUM_BANKS) { - struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; - - if (!chip) - return; - - *pull_up = chip->pull_up; - } -} - -static int nmk_gpio_probe(struct platform_device *dev) -{ - struct device_node *np = dev->dev.of_node; - struct nmk_gpio_chip *nmk_chip; - struct gpio_chip *chip; - struct resource *res; - struct clk *clk; - int latent_irq; - bool supports_sleepmode; - void __iomem *base; - int irq; - int ret; - - if (of_get_property(np, "st,supports-sleepmode", NULL)) - supports_sleepmode = true; - else - supports_sleepmode = false; - - if (of_property_read_u32(np, "gpio-bank", &dev->id)) { - dev_err(&dev->dev, "gpio-bank property not found\n"); - return -EINVAL; - } - - irq = platform_get_irq(dev, 0); - if (irq < 0) - return irq; - - /* It's OK for this IRQ not to be present */ - latent_irq = platform_get_irq(dev, 1); - - res = platform_get_resource(dev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&dev->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk = devm_clk_get(&dev->dev, NULL); - if (IS_ERR(clk)) - return PTR_ERR(clk); - clk_prepare(clk); - - nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); - if (!nmk_chip) - return -ENOMEM; - - /* - * The virt address in nmk_chip->addr is in the nomadik register space, - * so we can simply convert the resource address, without remapping - */ - nmk_chip->bank = dev->id; - nmk_chip->clk = clk; - nmk_chip->addr = base; - nmk_chip->chip = nmk_gpio_template; - nmk_chip->parent_irq = irq; - nmk_chip->latent_parent_irq = latent_irq; - nmk_chip->sleepmode = supports_sleepmode; - spin_lock_init(&nmk_chip->lock); - - chip = &nmk_chip->chip; - chip->base = dev->id * NMK_GPIO_PER_CHIP; - chip->ngpio = NMK_GPIO_PER_CHIP; - chip->label = dev_name(&dev->dev); - chip->dev = &dev->dev; - chip->owner = THIS_MODULE; - - clk_enable(nmk_chip->clk); - nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); - clk_disable(nmk_chip->clk); - chip->of_node = np; - - ret = gpiochip_add(&nmk_chip->chip); - if (ret) - return ret; - - BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); - - nmk_gpio_chips[nmk_chip->bank] = nmk_chip; - - platform_set_drvdata(dev, nmk_chip); - - /* - * Let the generic code handle this edge IRQ, the the chained - * handler will perform the actual work of handling the parent - * interrupt. - */ - ret = gpiochip_irqchip_add(&nmk_chip->chip, - &nmk_gpio_irq_chip, - 0, - handle_edge_irq, - IRQ_TYPE_EDGE_FALLING); - if (ret) { - dev_err(&dev->dev, "could not add irqchip\n"); - ret = gpiochip_remove(&nmk_chip->chip); - return -ENODEV; - } - /* Then register the chain on the parent IRQ */ - gpiochip_set_chained_irqchip(&nmk_chip->chip, - &nmk_gpio_irq_chip, - nmk_chip->parent_irq, - nmk_gpio_irq_handler); - if (nmk_chip->latent_parent_irq > 0) - gpiochip_set_chained_irqchip(&nmk_chip->chip, - &nmk_gpio_irq_chip, - nmk_chip->latent_parent_irq, - nmk_gpio_latent_irq_handler); - - dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); - - return 0; -} - -static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - return npct->soc->ngroups; -} - -static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - return npct->soc->groups[selector].name; -} - -static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - *pins = npct->soc->groups[selector].pins; - *num_pins = npct->soc->groups[selector].npins; - return 0; -} - -static struct pinctrl_gpio_range * -nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - int i; - - for (i = 0; i < npct->soc->gpio_num_ranges; i++) { - struct pinctrl_gpio_range *range; - - range = &npct->soc->gpio_ranges[i]; - if (offset >= range->pin_base && - offset <= (range->pin_base + range->npins - 1)) - return range; - } - return NULL; -} - -static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - struct pinctrl_gpio_range *range; - struct gpio_chip *chip; - - range = nmk_match_gpio_range(pctldev, offset); - if (!range || !range->gc) { - seq_printf(s, "invalid pin offset"); - return; - } - chip = range->gc; - nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); -} - -static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) - kfree(map[i].data.configs.configs); - kfree(map); -} - -static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, unsigned reserve) -{ - unsigned old_num = *reserved_maps; - unsigned new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, const char *group, - const char *function) -{ - if (*num_maps == *reserved_maps) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -static int nmk_dt_add_map_configs(struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps, const char *group, - unsigned long *configs, unsigned num_configs) -{ - unsigned long *dup_configs; - - if (*num_maps == *reserved_maps) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) - return -ENOMEM; - - (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; - - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -#define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } -#define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ - .size = ARRAY_SIZE(y), } - -static const unsigned long nmk_pin_input_modes[] = { - PIN_INPUT_NOPULL, - PIN_INPUT_PULLUP, - PIN_INPUT_PULLDOWN, -}; - -static const unsigned long nmk_pin_output_modes[] = { - PIN_OUTPUT_LOW, - PIN_OUTPUT_HIGH, - PIN_DIR_OUTPUT, -}; - -static const unsigned long nmk_pin_sleep_modes[] = { - PIN_SLEEPMODE_DISABLED, - PIN_SLEEPMODE_ENABLED, -}; - -static const unsigned long nmk_pin_sleep_input_modes[] = { - PIN_SLPM_INPUT_NOPULL, - PIN_SLPM_INPUT_PULLUP, - PIN_SLPM_INPUT_PULLDOWN, - PIN_SLPM_DIR_INPUT, -}; - -static const unsigned long nmk_pin_sleep_output_modes[] = { - PIN_SLPM_OUTPUT_LOW, - PIN_SLPM_OUTPUT_HIGH, - PIN_SLPM_DIR_OUTPUT, -}; - -static const unsigned long nmk_pin_sleep_wakeup_modes[] = { - PIN_SLPM_WAKEUP_DISABLE, - PIN_SLPM_WAKEUP_ENABLE, -}; - -static const unsigned long nmk_pin_gpio_modes[] = { - PIN_GPIOMODE_DISABLED, - PIN_GPIOMODE_ENABLED, -}; - -static const unsigned long nmk_pin_sleep_pdis_modes[] = { - PIN_SLPM_PDIS_DISABLED, - PIN_SLPM_PDIS_ENABLED, -}; - -struct nmk_cfg_param { - const char *property; - unsigned long config; - const unsigned long *choice; - int size; -}; - -static const struct nmk_cfg_param nmk_cfg_params[] = { - NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), - NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), - NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), - NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), - NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), - NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), - NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), - NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), -}; - -static int nmk_dt_pin_config(int index, int val, unsigned long *config) -{ - int ret = 0; - - if (nmk_cfg_params[index].choice == NULL) - *config = nmk_cfg_params[index].config; - else { - /* test if out of range */ - if (val < nmk_cfg_params[index].size) { - *config = nmk_cfg_params[index].config | - nmk_cfg_params[index].choice[val]; - } - } - return ret; -} - -static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) -{ - int i, pin_number; - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) - for (i = 0; i < npct->soc->npins; i++) - if (npct->soc->pins[i].number == pin_number) - return npct->soc->pins[i].name; - return NULL; -} - -static bool nmk_pinctrl_dt_get_config(struct device_node *np, - unsigned long *configs) -{ - bool has_config = 0; - unsigned long cfg = 0; - int i, val, ret; - - for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { - ret = of_property_read_u32(np, - nmk_cfg_params[i].property, &val); - if (ret != -EINVAL) { - if (nmk_dt_pin_config(i, val, &cfg) == 0) { - *configs |= cfg; - has_config = 1; - } - } - } - - return has_config; -} - -static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps) -{ - int ret; - const char *function = NULL; - unsigned long configs = 0; - bool has_config = 0; - unsigned reserve = 0; - struct property *prop; - const char *group, *gpio_name; - struct device_node *np_config; - - ret = of_property_read_string(np, "ste,function", &function); - if (ret >= 0) - reserve = 1; - - has_config = nmk_pinctrl_dt_get_config(np, &configs); - - np_config = of_parse_phandle(np, "ste,config", 0); - if (np_config) - has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); - - ret = of_property_count_strings(np, "ste,pins"); - if (ret < 0) - goto exit; - - if (has_config) - reserve++; - - reserve *= ret; - - ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "ste,pins", prop, group) { - if (function) { - ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, - group, function); - if (ret < 0) - goto exit; - } - if (has_config) { - gpio_name = nmk_find_pin_name(pctldev, group); - - ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, - gpio_name, &configs, 1); - if (ret < 0) - goto exit; - } - - } -exit: - return ret; -} - -static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - unsigned reserved_maps; - struct device_node *np; - int ret; - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, - &reserved_maps, num_maps); - if (ret < 0) { - nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; -} - -static const struct pinctrl_ops nmk_pinctrl_ops = { - .get_groups_count = nmk_get_groups_cnt, - .get_group_name = nmk_get_group_name, - .get_group_pins = nmk_get_group_pins, - .pin_dbg_show = nmk_pin_dbg_show, - .dt_node_to_map = nmk_pinctrl_dt_node_to_map, - .dt_free_map = nmk_pinctrl_dt_free_map, -}; - -static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - return npct->soc->nfunctions; -} - -static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - return npct->soc->functions[function].name; -} - -static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, - unsigned function, - const char * const **groups, - unsigned * const num_groups) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - *groups = npct->soc->functions[function].groups; - *num_groups = npct->soc->functions[function].ngroups; - - return 0; -} - -static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - const struct nmk_pingroup *g; - static unsigned int slpm[NUM_BANKS]; - unsigned long flags = 0; - bool glitch; - int ret = -EINVAL; - int i; - - g = &npct->soc->groups[group]; - - if (g->altsetting < 0) - return -EINVAL; - - dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); - - /* - * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, - * we may pass through an undesired state. In this case we take - * some extra care. - * - * Safe sequence used to switch IOs between GPIO and Alternate-C mode: - * - Save SLPM registers (since we have a shadow register in the - * nmk_chip we're using that as backup) - * - Set SLPM=0 for the IOs you want to switch and others to 1 - * - Configure the GPIO registers for the IOs that are being switched - * - Set IOFORCE=1 - * - Modify the AFLSA/B registers for the IOs that are being switched - * - Set IOFORCE=0 - * - Restore SLPM registers - * - Any spurious wake up event during switch sequence to be ignored - * and cleared - * - * We REALLY need to save ALL slpm registers, because the external - * IOFORCE will switch *all* ports to their sleepmode setting to as - * to avoid glitches. (Not just one port!) - */ - glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); - - if (glitch) { - spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); - - /* Initially don't put any pins to sleep when switching */ - memset(slpm, 0xff, sizeof(slpm)); - - /* - * Then mask the pins that need to be sleeping now when we're - * switching to the ALT C function. - */ - for (i = 0; i < g->npins; i++) - slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); - nmk_gpio_glitch_slpm_init(slpm); - } - - for (i = 0; i < g->npins; i++) { - struct pinctrl_gpio_range *range; - struct nmk_gpio_chip *nmk_chip; - struct gpio_chip *chip; - unsigned bit; - - range = nmk_match_gpio_range(pctldev, g->pins[i]); - if (!range) { - dev_err(npct->dev, - "invalid pin offset %d in group %s at index %d\n", - g->pins[i], g->name, i); - goto out_glitch; - } - if (!range->gc) { - dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", - g->pins[i], g->name, i); - goto out_glitch; - } - chip = range->gc; - nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); - - clk_enable(nmk_chip->clk); - bit = g->pins[i] % NMK_GPIO_PER_CHIP; - /* - * If the pin is switching to altfunc, and there was an - * interrupt installed on it which has been lazy disabled, - * actually mask the interrupt to prevent spurious interrupts - * that would occur while the pin is under control of the - * peripheral. Only SKE does this. - */ - nmk_gpio_disable_lazy_irq(nmk_chip, bit); - - __nmk_gpio_set_mode_safe(nmk_chip, bit, - (g->altsetting & NMK_GPIO_ALT_C), glitch); - clk_disable(nmk_chip->clk); - - /* - * Call PRCM GPIOCR config function in case ALTC - * has been selected: - * - If selection is a ALTCx, some bits in PRCM GPIOCR registers - * must be set. - * - If selection is pure ALTC and previous selection was ALTCx, - * then some bits in PRCM GPIOCR registers must be cleared. - */ - if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) - nmk_prcm_altcx_set_mode(npct, g->pins[i], - g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); - } - - /* When all pins are successfully reconfigured we get here */ - ret = 0; - -out_glitch: - if (glitch) { - nmk_gpio_glitch_slpm_restore(slpm); - spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); - } - - return ret; -} - -static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - struct nmk_gpio_chip *nmk_chip; - struct gpio_chip *chip; - unsigned bit; - - if (!range) { - dev_err(npct->dev, "invalid range\n"); - return -EINVAL; - } - if (!range->gc) { - dev_err(npct->dev, "missing GPIO chip in range\n"); - return -EINVAL; - } - chip = range->gc; - nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - - dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); - - clk_enable(nmk_chip->clk); - bit = offset % NMK_GPIO_PER_CHIP; - /* There is no glitch when converting any pin to GPIO */ - __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); - clk_disable(nmk_chip->clk); - - return 0; -} - -static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); - /* Set the pin to some default state, GPIO is usually default */ -} - -static const struct pinmux_ops nmk_pinmux_ops = { - .get_functions_count = nmk_pmx_get_funcs_cnt, - .get_function_name = nmk_pmx_get_func_name, - .get_function_groups = nmk_pmx_get_func_groups, - .enable = nmk_pmx_enable, - .gpio_request_enable = nmk_gpio_request_enable, - .gpio_disable_free = nmk_gpio_disable_free, -}; - -static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *config) -{ - /* Not implemented */ - return -EINVAL; -} - -static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *configs, unsigned num_configs) -{ - static const char *pullnames[] = { - [NMK_GPIO_PULL_NONE] = "none", - [NMK_GPIO_PULL_UP] = "up", - [NMK_GPIO_PULL_DOWN] = "down", - [3] /* illegal */ = "??" - }; - static const char *slpmnames[] = { - [NMK_GPIO_SLPM_INPUT] = "input/wakeup", - [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", - }; - struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - struct nmk_gpio_chip *nmk_chip; - struct pinctrl_gpio_range *range; - struct gpio_chip *chip; - unsigned bit; - pin_cfg_t cfg; - int pull, slpm, output, val, i; - bool lowemi, gpiomode, sleep; - - range = nmk_match_gpio_range(pctldev, pin); - if (!range) { - dev_err(npct->dev, "invalid pin offset %d\n", pin); - return -EINVAL; - } - if (!range->gc) { - dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", - pin); - return -EINVAL; - } - chip = range->gc; - nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - - for (i = 0; i < num_configs; i++) { - /* - * The pin config contains pin number and altfunction fields, - * here we just ignore that part. It's being handled by the - * framework and pinmux callback respectively. - */ - cfg = (pin_cfg_t) configs[i]; - pull = PIN_PULL(cfg); - slpm = PIN_SLPM(cfg); - output = PIN_DIR(cfg); - val = PIN_VAL(cfg); - lowemi = PIN_LOWEMI(cfg); - gpiomode = PIN_GPIOMODE(cfg); - sleep = PIN_SLEEPMODE(cfg); - - if (sleep) { - int slpm_pull = PIN_SLPM_PULL(cfg); - int slpm_output = PIN_SLPM_DIR(cfg); - int slpm_val = PIN_SLPM_VAL(cfg); - - /* All pins go into GPIO mode at sleep */ - gpiomode = true; - - /* - * The SLPM_* values are normal values + 1 to allow zero - * to mean "same as normal". - */ - if (slpm_pull) - pull = slpm_pull - 1; - if (slpm_output) - output = slpm_output - 1; - if (slpm_val) - val = slpm_val - 1; - - dev_dbg(nmk_chip->chip.dev, - "pin %d: sleep pull %s, dir %s, val %s\n", - pin, - slpm_pull ? pullnames[pull] : "same", - slpm_output ? (output ? "output" : "input") - : "same", - slpm_val ? (val ? "high" : "low") : "same"); - } - - dev_dbg(nmk_chip->chip.dev, - "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", - pin, cfg, pullnames[pull], slpmnames[slpm], - output ? "output " : "input", - output ? (val ? "high" : "low") : "", - lowemi ? "on" : "off"); - - clk_enable(nmk_chip->clk); - bit = pin % NMK_GPIO_PER_CHIP; - if (gpiomode) - /* No glitch when going to GPIO mode */ - __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); - if (output) - __nmk_gpio_make_output(nmk_chip, bit, val); - else { - __nmk_gpio_make_input(nmk_chip, bit); - __nmk_gpio_set_pull(nmk_chip, bit, pull); - } - /* TODO: isn't this only applicable on output pins? */ - __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); - - __nmk_gpio_set_slpm(nmk_chip, bit, slpm); - clk_disable(nmk_chip->clk); - } /* for each config */ - - return 0; -} - -static const struct pinconf_ops nmk_pinconf_ops = { - .pin_config_get = nmk_pin_config_get, - .pin_config_set = nmk_pin_config_set, -}; - -static struct pinctrl_desc nmk_pinctrl_desc = { - .name = "pinctrl-nomadik", - .pctlops = &nmk_pinctrl_ops, - .pmxops = &nmk_pinmux_ops, - .confops = &nmk_pinconf_ops, - .owner = THIS_MODULE, -}; - -static const struct of_device_id nmk_pinctrl_match[] = { - { - .compatible = "stericsson,stn8815-pinctrl", - .data = (void *)PINCTRL_NMK_STN8815, - }, - { - .compatible = "stericsson,db8500-pinctrl", - .data = (void *)PINCTRL_NMK_DB8500, - }, - { - .compatible = "stericsson,db8540-pinctrl", - .data = (void *)PINCTRL_NMK_DB8540, - }, - {}, -}; - -#ifdef CONFIG_PM_SLEEP -static int nmk_pinctrl_suspend(struct device *dev) -{ - struct nmk_pinctrl *npct; - - npct = dev_get_drvdata(dev); - if (!npct) - return -EINVAL; - - return pinctrl_force_sleep(npct->pctl); -} - -static int nmk_pinctrl_resume(struct device *dev) -{ - struct nmk_pinctrl *npct; - - npct = dev_get_drvdata(dev); - if (!npct) - return -EINVAL; - - return pinctrl_force_default(npct->pctl); -} -#endif - -static int nmk_pinctrl_probe(struct platform_device *pdev) -{ - const struct of_device_id *match; - struct device_node *np = pdev->dev.of_node; - struct device_node *prcm_np; - struct nmk_pinctrl *npct; - unsigned int version = 0; - int i; - - npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); - if (!npct) - return -ENOMEM; - - match = of_match_device(nmk_pinctrl_match, &pdev->dev); - if (!match) - return -ENODEV; - version = (unsigned int) match->data; - - /* Poke in other ASIC variants here */ - if (version == PINCTRL_NMK_STN8815) - nmk_pinctrl_stn8815_init(&npct->soc); - if (version == PINCTRL_NMK_DB8500) - nmk_pinctrl_db8500_init(&npct->soc); - if (version == PINCTRL_NMK_DB8540) - nmk_pinctrl_db8540_init(&npct->soc); - - prcm_np = of_parse_phandle(np, "prcm", 0); - if (prcm_np) - npct->prcm_base = of_iomap(prcm_np, 0); - if (!npct->prcm_base) { - if (version == PINCTRL_NMK_STN8815) { - dev_info(&pdev->dev, - "No PRCM base, " - "assuming no ALT-Cx control is available\n"); - } else { - dev_err(&pdev->dev, "missing PRCM base address\n"); - return -EINVAL; - } - } - - /* - * We need all the GPIO drivers to probe FIRST, or we will not be able - * to obtain references to the struct gpio_chip * for them, and we - * need this to proceed. - */ - for (i = 0; i < npct->soc->gpio_num_ranges; i++) { - if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { - dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); - return -EPROBE_DEFER; - } - npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; - } - - nmk_pinctrl_desc.pins = npct->soc->pins; - nmk_pinctrl_desc.npins = npct->soc->npins; - npct->dev = &pdev->dev; - - npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); - if (!npct->pctl) { - dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); - return -EINVAL; - } - - /* We will handle a range of GPIO pins */ - for (i = 0; i < npct->soc->gpio_num_ranges; i++) - pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); - - platform_set_drvdata(pdev, npct); - dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); - - return 0; -} - -static const struct of_device_id nmk_gpio_match[] = { - { .compatible = "st,nomadik-gpio", }, - {} -}; - -static struct platform_driver nmk_gpio_driver = { - .driver = { - .owner = THIS_MODULE, - .name = "gpio", - .of_match_table = nmk_gpio_match, - }, - .probe = nmk_gpio_probe, -}; - -static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, - nmk_pinctrl_suspend, - nmk_pinctrl_resume); - -static struct platform_driver nmk_pinctrl_driver = { - .driver = { - .owner = THIS_MODULE, - .name = "pinctrl-nomadik", - .of_match_table = nmk_pinctrl_match, - .pm = &nmk_pinctrl_pm_ops, - }, - .probe = nmk_pinctrl_probe, -}; - -static int __init nmk_gpio_init(void) -{ - int ret; - - ret = platform_driver_register(&nmk_gpio_driver); - if (ret) - return ret; - return platform_driver_register(&nmk_pinctrl_driver); -} - -core_initcall(nmk_gpio_init); - -MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); -MODULE_DESCRIPTION("Nomadik GPIO Driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h deleted file mode 100644 index d8215f1e70c7..000000000000 --- a/drivers/pinctrl/pinctrl-nomadik.h +++ /dev/null @@ -1,192 +0,0 @@ -#ifndef PINCTRL_PINCTRL_NOMADIK_H -#define PINCTRL_PINCTRL_NOMADIK_H - -/* Package definitions */ -#define PINCTRL_NMK_STN8815 0 -#define PINCTRL_NMK_DB8500 1 -#define PINCTRL_NMK_DB8540 2 - -/* Alternate functions: function C is set in hw by setting both A and B */ -#define NMK_GPIO_ALT_GPIO 0 -#define NMK_GPIO_ALT_A 1 -#define NMK_GPIO_ALT_B 2 -#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) - -#define NMK_GPIO_ALT_CX_SHIFT 2 -#define NMK_GPIO_ALT_C1 ((1< Date: Fri, 11 Jul 2014 18:21:24 -0700 Subject: pinctrl: qcom: Make muxing of gpio function explicit Instead of relying on pinmux->disable(), make the gpio function an explicit function for all pins that supports it. Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-apq8064.c | 19 ++++++++++++++++++- drivers/pinctrl/qcom/pinctrl-ipq8064.c | 17 ++++++++++++++++- drivers/pinctrl/qcom/pinctrl-msm8960.c | 30 +++++++++++++++++++++++++++++- drivers/pinctrl/qcom/pinctrl-msm8x74.c | 29 ++++++++++++++++++++++++++++- 4 files changed, 91 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index 519f7886b0f1..feb6f152f9b7 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -230,7 +230,7 @@ static const unsigned int sdc3_data_pins[] = { 95 }; .pins = gpio##id##_pins, \ .npins = ARRAY_SIZE(gpio##id##_pins), \ .funcs = (int[]){ \ - APQ_MUX_NA, /* gpio mode */ \ + APQ_MUX_gpio, \ APQ_MUX_##f1, \ APQ_MUX_##f2, \ APQ_MUX_##f3, \ @@ -293,6 +293,7 @@ enum apq8064_functions { APQ_MUX_cam_mclk, APQ_MUX_codec_mic_i2s, APQ_MUX_codec_spkr_i2s, + APQ_MUX_gpio, APQ_MUX_gsbi1, APQ_MUX_gsbi2, APQ_MUX_gsbi3, @@ -335,6 +336,21 @@ static const char * const codec_mic_i2s_groups[] = { static const char * const codec_spkr_i2s_groups[] = { "gpio39", "gpio40", "gpio41", "gpio42" }; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89" +}; static const char * const gsbi1_groups[] = { "gpio18", "gpio19", "gpio20", "gpio21" }; @@ -430,6 +446,7 @@ static const struct msm_function apq8064_functions[] = { FUNCTION(cam_mclk), FUNCTION(codec_mic_i2s), FUNCTION(codec_spkr_i2s), + FUNCTION(gpio), FUNCTION(gsbi1), FUNCTION(gsbi2), FUNCTION(gsbi3), diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c index acafea4c3a33..767cf1120b20 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -183,7 +183,7 @@ static const unsigned int sdc3_data_pins[] = { 71 }; .pins = gpio##id##_pins, \ .npins = ARRAY_SIZE(gpio##id##_pins), \ .funcs = (int[]){ \ - IPQ_MUX_NA, /* gpio mode */ \ + IPQ_MUX_gpio, \ IPQ_MUX_##f1, \ IPQ_MUX_##f2, \ IPQ_MUX_##f3, \ @@ -243,6 +243,7 @@ static const unsigned int sdc3_data_pins[] = { 71 }; } enum ipq8064_functions { + IPQ_MUX_gpio, IPQ_MUX_mdio, IPQ_MUX_mi2s, IPQ_MUX_pdm, @@ -291,6 +292,19 @@ enum ipq8064_functions { IPQ_MUX_NA, }; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; + static const char * const mdio_groups[] = { "gpio0", "gpio1", "gpio10", "gpio11", }; @@ -481,6 +495,7 @@ static const char * const ps_hold_groups[] = { }; static const struct msm_function ipq8064_functions[] = { + FUNCTION(gpio), FUNCTION(mdio), FUNCTION(ssbi), FUNCTION(spmi), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c index 564543bb2c1c..35047036a053 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -355,7 +355,7 @@ static const unsigned int sdc3_data_pins[] = { 157 }; .pins = gpio##id##_pins, \ .npins = ARRAY_SIZE(gpio##id##_pins), \ .funcs = (int[]){ \ - MSM_MUX_NA, /* gpio mode */ \ + MSM_MUX_gpio, \ MSM_MUX_##f1, \ MSM_MUX_##f2, \ MSM_MUX_##f3, \ @@ -441,6 +441,7 @@ enum msm8960_functions { MSM_MUX_gp_pdm_1b, MSM_MUX_gp_pdm_2a, MSM_MUX_gp_pdm_2b, + MSM_MUX_gpio, MSM_MUX_gsbi1, MSM_MUX_gsbi1_spi_cs1_n, MSM_MUX_gsbi1_spi_cs2a_n, @@ -622,6 +623,32 @@ static const char * const gp_pdm_2b_groups[] = { "gpio53" }; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151" +}; + static const char * const gsbi1_groups[] = { "gpio6", "gpio7", "gpio8", "gpio9" }; @@ -961,6 +988,7 @@ static const struct msm_function msm8960_functions[] = { FUNCTION(gp_pdm_1b), FUNCTION(gp_pdm_2a), FUNCTION(gp_pdm_2b), + FUNCTION(gpio), FUNCTION(gsbi1), FUNCTION(gsbi1_spi_cs1_n), FUNCTION(gsbi1_spi_cs2a_n), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index 418306911a6f..8c9720154d1e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -342,7 +342,7 @@ static const unsigned int sdc2_data_pins[] = { 151 }; .pins = gpio##id##_pins, \ .npins = ARRAY_SIZE(gpio##id##_pins), \ .funcs = (int[]){ \ - MSM_MUX_NA, /* gpio mode */ \ + MSM_MUX_gpio, \ MSM_MUX_##f1, \ MSM_MUX_##f2, \ MSM_MUX_##f3, \ @@ -402,6 +402,7 @@ static const unsigned int sdc2_data_pins[] = { 151 }; * the pingroup table below. */ enum msm8x74_functions { + MSM_MUX_gpio, MSM_MUX_cci_i2c0, MSM_MUX_cci_i2c1, MSM_MUX_blsp_i2c1, @@ -509,6 +510,31 @@ enum msm8x74_functions { MSM_MUX_NA, }; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145" +}; + static const char * const blsp_uart1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" }; @@ -728,6 +754,7 @@ static const char * const wlan_groups[] = { static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; static const struct msm_function msm8x74_functions[] = { + FUNCTION(gpio), FUNCTION(cci_i2c0), FUNCTION(cci_i2c1), FUNCTION(uim1), -- cgit v1.2.3 From b4e7c55dabf611cf5cccd1554fec06f72e1c9faf Mon Sep 17 00:00:00 2001 From: abdoulaye berthe Date: Sat, 12 Jul 2014 22:30:13 +0200 Subject: pinctrl: remove all usage of gpio_remove ret val in driver/pinctl Signed-off-by: abdoulaye berthe Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-adi2.c | 9 ++++----- drivers/pinctrl/pinctrl-as3722.c | 11 ++--------- drivers/pinctrl/pinctrl-baytrail.c | 5 +---- drivers/pinctrl/pinctrl-coh901.c | 10 ++-------- drivers/pinctrl/pinctrl-rockchip.c | 16 ++++------------ drivers/pinctrl/sh-pfc/gpio.c | 9 +++------ drivers/pinctrl/spear/pinctrl-plgpio.c | 3 +-- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +-- drivers/pinctrl/vt8500/pinctrl-wmt.c | 9 ++------- 9 files changed, 20 insertions(+), 55 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 46413e93d850..b092b93c67a1 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -949,7 +949,7 @@ static int adi_gpio_probe(struct platform_device *pdev) struct gpio_port *port; char pinctrl_devname[DEVNAME_SIZE]; static int gpio; - int ret = 0, ret1; + int ret = 0; pdata = dev->platform_data; if (!pdata) @@ -1027,7 +1027,7 @@ static int adi_gpio_probe(struct platform_device *pdev) return 0; out_remove_gpiochip: - ret1 = gpiochip_remove(&port->chip); + gpiochip_remove(&port->chip); out_remove_domain: if (port->pint) irq_domain_remove(port->domain); @@ -1038,12 +1038,11 @@ out_remove_domain: static int adi_gpio_remove(struct platform_device *pdev) { struct gpio_port *port = platform_get_drvdata(pdev); - int ret; u8 offset; list_del(&port->node); gpiochip_remove_pin_ranges(&port->chip); - ret = gpiochip_remove(&port->chip); + gpiochip_remove(&port->chip); if (port->pint) { for (offset = 0; offset < port->width; offset++) irq_dispose_mapping(irq_find_mapping(port->domain, @@ -1051,7 +1050,7 @@ static int adi_gpio_remove(struct platform_device *pdev) irq_domain_remove(port->domain); } - return ret; + return 0; } static int adi_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c index c862f9c0e9ce..0e4ec91f4d49 100644 --- a/drivers/pinctrl/pinctrl-as3722.c +++ b/drivers/pinctrl/pinctrl-as3722.c @@ -565,7 +565,6 @@ static int as3722_pinctrl_probe(struct platform_device *pdev) { struct as3722_pctrl_info *as_pci; int ret; - int tret; as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL); if (!as_pci) @@ -611,10 +610,7 @@ static int as3722_pinctrl_probe(struct platform_device *pdev) return 0; fail_range_add: - tret = gpiochip_remove(&as_pci->gpio_chip); - if (tret < 0) - dev_warn(&pdev->dev, "Couldn't remove gpio chip, %d\n", tret); - + gpiochip_remove(&as_pci->gpio_chip); fail_chip_add: pinctrl_unregister(as_pci->pctl); return ret; @@ -623,11 +619,8 @@ fail_chip_add: static int as3722_pinctrl_remove(struct platform_device *pdev) { struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev); - int ret; - ret = gpiochip_remove(&as_pci->gpio_chip); - if (ret < 0) - return ret; + gpiochip_remove(&as_pci->gpio_chip); pinctrl_unregister(as_pci->pctl); return 0; } diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c index 701a646a3d10..d8e946992323 100644 --- a/drivers/pinctrl/pinctrl-baytrail.c +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -638,12 +638,9 @@ MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); static int byt_gpio_remove(struct platform_device *pdev) { struct byt_gpio *vg = platform_get_drvdata(pdev); - int err; pm_runtime_disable(&pdev->dev); - err = gpiochip_remove(&vg->chip); - if (err) - dev_warn(&pdev->dev, "failed to remove gpio_chip.\n"); + gpiochip_remove(&vg->chip); return 0; } diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index d182fdd2e715..29cbbab8c3a6 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -756,8 +756,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev) err_no_range: err_no_irqchip: - if (gpiochip_remove(&gpio->chip)) - dev_err(&pdev->dev, "failed to remove gpio chip\n"); + gpiochip_remove(&gpio->chip); err_no_chip: clk_disable_unprepare(gpio->clk); dev_err(&pdev->dev, "module ERROR:%d\n", err); @@ -767,16 +766,11 @@ err_no_chip: static int __exit u300_gpio_remove(struct platform_device *pdev) { struct u300_gpio *gpio = platform_get_drvdata(pdev); - int err; /* Turn off the GPIO block */ writel(0x00000000U, gpio->base + U300_GPIO_CR); - err = gpiochip_remove(&gpio->chip); - if (err < 0) { - dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err); - return err; - } + gpiochip_remove(&gpio->chip); clk_disable_unprepare(gpio->clk); return 0; } diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 192aaee8de07..e2e66c8ccf03 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1492,10 +1492,7 @@ fail: for (--i, --bank; i >= 0; --i, --bank) { if (!bank->valid) continue; - - if (gpiochip_remove(&bank->gpio_chip)) - dev_err(&pdev->dev, "gpio chip %s remove failed\n", - bank->gpio_chip.label); + gpiochip_remove(&bank->gpio_chip); } return ret; } @@ -1505,20 +1502,15 @@ static int rockchip_gpiolib_unregister(struct platform_device *pdev, { struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_pin_bank *bank = ctrl->pin_banks; - int ret = 0; int i; - for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { if (!bank->valid) continue; - - ret = gpiochip_remove(&bank->gpio_chip); + gpiochip_remove(&bank->gpio_chip); } - if (ret) - dev_err(&pdev->dev, "gpio chip remove failed\n"); - - return ret; + return 0; } static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index a9288ab01f7b..80f641ee4dea 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -409,11 +409,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) { - int err; - int ret; - - ret = gpiochip_remove(&pfc->gpio->gpio_chip); - err = gpiochip_remove(&pfc->func->gpio_chip); + gpiochip_remove(&pfc->gpio->gpio_chip); + gpiochip_remove(&pfc->func->gpio_chip); - return ret < 0 ? ret : err; + return 0; } diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 3a20cdc65810..bddb79105d67 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -606,8 +606,7 @@ static int plgpio_probe(struct platform_device *pdev) remove_gpiochip: dev_info(&pdev->dev, "Remove gpiochip\n"); - if (gpiochip_remove(&plgpio->chip)) - dev_err(&pdev->dev, "unable to remove gpiochip\n"); + gpiochip_remove(&plgpio->chip); unprepare_clk: if (!IS_ERR(plgpio->clk)) clk_unprepare(plgpio->clk); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 47f5e1bc50d0..96ee6bb0fad5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -983,8 +983,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, clk_error: clk_disable_unprepare(clk); gpiochip_error: - if (gpiochip_remove(pctl->chip)) - dev_err(&pdev->dev, "failed to remove gpio chip\n"); + gpiochip_remove(pctl->chip); pinctrl_error: pinctrl_unregister(pctl->pctl_dev); return ret; diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index 8c976c21eeee..8cea355f9a81 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -615,8 +615,7 @@ int wmt_pinctrl_probe(struct platform_device *pdev, return 0; fail_range: - if (gpiochip_remove(&data->gpio_chip)) - dev_err(&pdev->dev, "failed to remove gpio chip\n"); + gpiochip_remove(&data->gpio_chip); fail_gpio: pinctrl_unregister(data->pctl_dev); return err; @@ -625,12 +624,8 @@ fail_gpio: int wmt_pinctrl_remove(struct platform_device *pdev) { struct wmt_pinctrl_data *data = platform_get_drvdata(pdev); - int err; - - err = gpiochip_remove(&data->gpio_chip); - if (err) - dev_err(&pdev->dev, "failed to remove gpio chip\n"); + gpiochip_remove(&data->gpio_chip); pinctrl_unregister(data->pctl_dev); return 0; -- cgit v1.2.3 From 1c349551027fadc9cfe1ec01068f6f8ac5b9331d Mon Sep 17 00:00:00 2001 From: Andrey Utkin Date: Thu, 17 Jul 2014 19:29:39 +0300 Subject: pinctrl: msm: drop negativity check on unsigned value [linux-3.16-rc5/drivers/pinctrl/pinctrl-msm.c:145]: (style) Checking if unsigned variable 'mux_bit' is less than zero. if (WARN_ON(g->mux_bit < 0)) return -EINVAL; Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=80491 Reported-by: David Binderman Signed-off-by: Andrey Utkin Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 90d383d3ce17..2738108caff2 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -142,9 +142,6 @@ static int msm_pinmux_enable(struct pinctrl_dev *pctldev, g = &pctrl->soc->groups[group]; - if (WARN_ON(g->mux_bit < 0)) - return -EINVAL; - for (i = 0; i < g->nfuncs; i++) { if (g->funcs[i] == function) break; -- cgit v1.2.3 From ed62f2f25547ea9a25394087470a5816ee4db71b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Sun, 20 Jul 2014 01:48:45 +0200 Subject: pinctrl: rockchip: set is_generic in pinconf_ops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rockchip pinctrl driver implements the generic pinconfig, therefore also state this, so that the default pinconf dump functions work. Signed-off-by: Heiko Stübner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index e2e66c8ccf03..337c1844f276 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -928,6 +928,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, static const struct pinconf_ops rockchip_pinconf_ops = { .pin_config_get = rockchip_pinconf_get, .pin_config_set = rockchip_pinconf_set, + .is_generic = true, }; static const struct of_device_id rockchip_bank_match[] = { -- cgit v1.2.3 From 66d750e1d03875512dec38993b4cac3640a85e54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Sun, 20 Jul 2014 01:49:17 +0200 Subject: pinctrl: rockchip: add separate type for rk3288 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit An upcoming pinctrl function of the rk3288 differs again from everything else, so we'll need a separate type for it. Signed-off-by: Heiko Stübner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 337c1844f276..3e239c75f52c 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -62,6 +62,7 @@ enum rockchip_pinctrl_type { RK2928, RK3066B, RK3188, + RK3288, }; /** @@ -597,6 +598,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT : PIN_CONFIG_BIAS_DISABLE; case RK3188: + case RK3288: data >>= bit; data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; @@ -651,6 +653,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, spin_unlock_irqrestore(&bank->slock, flags); break; case RK3188: + case RK3288: spin_lock_irqsave(&bank->slock, flags); /* enable the write to the equivalent lower bits */ @@ -812,6 +815,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3066B: return pull ? false : true; case RK3188: + case RK3288: return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); } @@ -1838,7 +1842,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pin_banks = rk3288_pin_banks, .nr_banks = ARRAY_SIZE(rk3288_pin_banks), .label = "RK3288-GPIO", - .type = RK3188, + .type = RK3288, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x84, .pull_calc_reg = rk3288_calc_pull_reg_and_bit, -- cgit v1.2.3 From b547c8007e83a476b946237d09227668fe286a57 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Sun, 20 Jul 2014 01:50:11 +0200 Subject: pinctrl: rockchip: add drive-strength control for rk3288 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rk3288 is the first Rockchip soc handling the drive strength on a per-pin basis, while the older ones can set the drive-strength only for specific pin-groups. Therefore limit setting the drive-strength to this soc for now. Signed-off-by: Heiko Stübner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 112 +++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 3e239c75f52c..5e8b2e04cd7a 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -573,6 +573,98 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, } } +#define RK3288_DRV_PMU_OFFSET 0x70 +#define RK3288_DRV_GRF_OFFSET 0x1c0 +#define RK3288_DRV_BITS_PER_PIN 2 +#define RK3288_DRV_PINS_PER_REG 8 +#define RK3288_DRV_BANK_STRIDE 16 +static int rk3288_drv_list[] = { 2, 4, 8, 12 }; + +static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3288_DRV_PMU_OFFSET; + + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3288_DRV_PINS_PER_REG; + *bit *= RK3288_DRV_BITS_PER_PIN; + } else { + *regmap = info->regmap_base; + *reg = RK3288_DRV_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); + *bit *= RK3288_DRV_BITS_PER_PIN; + } +} + +static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + + rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + + data >>= bit; + data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1; + + return rk3288_drv_list[data]; +} + +static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num, + int strength) +{ + struct rockchip_pinctrl *info = bank->drvdata; + struct regmap *regmap; + unsigned long flags; + int reg, ret, i; + u32 data; + u8 bit; + + rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) { + if (rk3288_drv_list[i] == strength) { + ret = i; + break; + } + } + + if (ret < 0) { + dev_err(info->dev, "unsupported driver strength %d\n", + strength); + return ret; + } + + spin_lock_irqsave(&bank->slock, flags); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + + ret = regmap_write(regmap, reg, data); + spin_unlock_irqrestore(&bank->slock, flags); + + return ret; +} + static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; @@ -870,6 +962,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, if (rc) return rc; break; + case PIN_CONFIG_DRIVE_STRENGTH: + /* rk3288 is the first with per-pin drive-strength */ + if (info->ctrl->type != RK3288) + return -ENOTSUPP; + + rc = rk3288_set_drive(bank, pin - bank->pin_base, arg); + if (rc < 0) + return rc; + break; default: return -ENOTSUPP; break; @@ -919,6 +1020,17 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, arg = rc ? 1 : 0; break; + case PIN_CONFIG_DRIVE_STRENGTH: + /* rk3288 is the first with per-pin drive-strength */ + if (info->ctrl->type != RK3288) + return -ENOTSUPP; + + rc = rk3288_get_drive(bank, pin - bank->pin_base); + if (rc < 0) + return rc; + + arg = rc; + break; default: return -ENOTSUPP; break; -- cgit v1.2.3 From f83549d61d6de28ea8cbbef9f8d12b697c6ed1dd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 15 Jul 2014 01:24:36 +0800 Subject: pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 96ee6bb0fad5..9dba7afe94d6 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -541,18 +541,33 @@ static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); struct sunxi_desc_function *func; + int ret; func = sunxi_pinctrl_desc_find_function_by_pin(pctl, pctl->irq_array[d->hwirq], "irq"); if (!func) return -EINVAL; + ret = gpio_lock_as_irq(pctl->chip, pctl->irq_array[d->hwirq]); + if (ret) { + dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", + irqd_to_hwirq(d)); + return ret; + } + /* Change muxing to INT mode */ sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); return 0; } +static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + + gpio_unlock_as_irq(pctl->chip, pctl->irq_array[d->hwirq]); +} + static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); @@ -657,6 +672,7 @@ static struct irq_chip sunxi_pinctrl_edge_irq_chip = { .irq_mask = sunxi_pinctrl_irq_mask, .irq_unmask = sunxi_pinctrl_irq_unmask, .irq_request_resources = sunxi_pinctrl_irq_request_resources, + .irq_release_resources = sunxi_pinctrl_irq_release_resources, .irq_set_type = sunxi_pinctrl_irq_set_type, .flags = IRQCHIP_SKIP_SET_WAKE, }; @@ -670,6 +686,7 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip = { .irq_enable = sunxi_pinctrl_irq_ack_unmask, .irq_disable = sunxi_pinctrl_irq_mask, .irq_request_resources = sunxi_pinctrl_irq_request_resources, + .irq_release_resources = sunxi_pinctrl_irq_release_resources, .irq_set_type = sunxi_pinctrl_irq_set_type, .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, -- cgit v1.2.3 From 343f132752bede1dc3a740ba469b665ffb111500 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 15 Jul 2014 01:24:37 +0800 Subject: pinctrl: sunxi: number gpio ranges starting from 0 The pinctrl-sunxi driver originally used the pin number as the gpio range offset. This resulted in large, bogus gpio numbers for the new sun6i-a31-r pinctrl devices. This patch makes the driver number the gpios ranges starting from an offset of 0, by subtracting the pin_base number from the pin number. This also makes the system-wide gpio number match the pin number. Tested on sun8i with sysfs exported gpios. This patch also changes the GPIO bindings for R_PIO: gpios = <&r_pio B N flag>; Where B originally was the pinbank label (L or M) counted from A, with this patch it becomes (L or M) counted from its pinbank base (L). Thus gpios = <&r_pio 10 11 0>; /* PL11 */ becomes gpios = <&r_pio 0 11 0>; /* PL11 */ IMO this is correct, as the binding shows the bank offset and pin offset within the bank for the GPIO controller. But I'm worried it might be a bit confusing. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9dba7afe94d6..b24b5ecbe290 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -507,7 +507,7 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, base = PINS_PER_BANK * gpiospec->args[0]; pin = base + gpiospec->args[1]; - if (pin > (gc->base + gc->ngpio)) + if (pin > gc->ngpio) return -EINVAL; if (flags) @@ -520,12 +520,13 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); struct sunxi_desc_function *desc; + unsigned pinnum = pctl->desc->pin_base + offset; unsigned irqnum; if (offset >= chip->ngpio) return -ENXIO; - desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); + desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); if (!desc) return -EINVAL; @@ -548,7 +549,8 @@ static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) if (!func) return -EINVAL; - ret = gpio_lock_as_irq(pctl->chip, pctl->irq_array[d->hwirq]); + ret = gpio_lock_as_irq(pctl->chip, + pctl->irq_array[d->hwirq] - pctl->desc->pin_base); if (ret) { dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", irqd_to_hwirq(d)); @@ -565,7 +567,8 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - gpio_unlock_as_irq(pctl->chip, pctl->irq_array[d->hwirq]); + gpio_unlock_as_irq(pctl->chip, + pctl->irq_array[d->hwirq] - pctl->desc->pin_base); } static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) @@ -931,7 +934,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, const struct sunxi_desc_pin *pin = pctl->desc->pins + i; ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), - pin->pin.number, + pin->pin.number - pctl->desc->pin_base, pin->pin.number, 1); if (ret) goto gpiochip_error; -- cgit v1.2.3 From e1ee5c578fb1fa24b7ccaf1a11237a2bd70b6f9a Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Fri, 25 Jul 2014 09:54:47 +0300 Subject: pinctrl: baytrail: Convert to use gpiolib irqchip Instead of open-coding irqchip handling in the driver we can take advantage of the new irqchip helpers provided by the gpiolib core. While doing this we also make sure that we call gpiochip_irqchip_add() after the gpiochip itself is registered as required. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/pinctrl-baytrail.c | 87 +++++++++----------------------------- 2 files changed, 20 insertions(+), 69 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 3d94e47546ec..4e3231ad03cd 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -70,7 +70,7 @@ config PINCTRL_AT91 config PINCTRL_BAYTRAIL bool "Intel Baytrail GPIO pin control" depends on GPIOLIB && ACPI && X86 - select IRQ_DOMAIN + select GPIOLIB_IRQCHIP help driver for memory mapped GPIO functionality on Intel Baytrail platforms. Supports 3 banks with 102, 28 and 44 gpios. diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c index d8e946992323..9ca59a018743 100644 --- a/drivers/pinctrl/pinctrl-baytrail.c +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -25,9 +25,7 @@ #include #include #include -#include #include -#include #include #include #include @@ -138,7 +136,6 @@ static struct pinctrl_gpio_range byt_ranges[] = { struct byt_gpio { struct gpio_chip chip; - struct irq_domain *domain; struct platform_device *pdev; spinlock_t lock; void __iomem *reg_base; @@ -218,7 +215,7 @@ static void byt_gpio_free(struct gpio_chip *chip, unsigned offset) static int byt_irq_type(struct irq_data *d, unsigned type) { - struct byt_gpio *vg = irq_data_get_irq_chip_data(d); + struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d)); u32 offset = irqd_to_hwirq(d); u32 value; unsigned long flags; @@ -404,16 +401,10 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) spin_unlock_irqrestore(&vg->lock, flags); } -static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct byt_gpio *vg = to_byt_gpio(chip); - return irq_create_mapping(vg->domain, offset); -} - static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); - struct byt_gpio *vg = irq_data_get_irq_handler_data(data); + struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc)); struct irq_chip *chip = irq_data_get_irq_chip(data); u32 base, pin, mask; void __iomem *reg; @@ -432,7 +423,7 @@ static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) /* Clear before handling so we can't lose an edge */ writel(mask, reg); - virq = irq_find_mapping(vg->domain, base + pin); + virq = irq_find_mapping(vg->chip.irqdomain, base + pin); generic_handle_irq(virq); /* In case bios or user sets triggering incorretly a pin @@ -465,33 +456,11 @@ static void byt_irq_mask(struct irq_data *d) { } -static int byt_irq_reqres(struct irq_data *d) -{ - struct byt_gpio *vg = irq_data_get_irq_chip_data(d); - - if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) { - dev_err(vg->chip.dev, - "unable to lock HW IRQ %lu for IRQ\n", - irqd_to_hwirq(d)); - return -EINVAL; - } - return 0; -} - -static void byt_irq_relres(struct irq_data *d) -{ - struct byt_gpio *vg = irq_data_get_irq_chip_data(d); - - gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d)); -} - static struct irq_chip byt_irqchip = { .name = "BYT-GPIO", .irq_mask = byt_irq_mask, .irq_unmask = byt_irq_unmask, .irq_set_type = byt_irq_type, - .irq_request_resources = byt_irq_reqres, - .irq_release_resources = byt_irq_relres, }; static void byt_gpio_irq_init_hw(struct byt_gpio *vg) @@ -512,23 +481,6 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg) } } -static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq, - irq_hw_number_t hw) -{ - struct byt_gpio *vg = d->host_data; - - irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq, - "demux"); - irq_set_chip_data(virq, vg); - irq_set_irq_type(virq, IRQ_TYPE_NONE); - - return 0; -} - -static const struct irq_domain_ops byt_gpio_irq_ops = { - .map = byt_gpio_irq_map, -}; - static int byt_gpio_probe(struct platform_device *pdev) { struct byt_gpio *vg; @@ -538,7 +490,6 @@ static int byt_gpio_probe(struct platform_device *pdev) struct acpi_device *acpi_dev; struct pinctrl_gpio_range *range; acpi_handle handle = ACPI_HANDLE(dev); - unsigned hwirq; int ret; if (acpi_bus_get_device(handle, &acpi_dev)) @@ -585,27 +536,27 @@ static int byt_gpio_probe(struct platform_device *pdev) gc->can_sleep = false; gc->dev = dev; + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); + return ret; + } + /* set up interrupts */ irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (irq_rc && irq_rc->start) { - hwirq = irq_rc->start; - gc->to_irq = byt_gpio_to_irq; - - vg->domain = irq_domain_add_linear(NULL, gc->ngpio, - &byt_gpio_irq_ops, vg); - if (!vg->domain) - return -ENXIO; - byt_gpio_irq_init_hw(vg); + ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0, + handle_simple_irq, IRQ_TYPE_NONE); + if (ret) { + dev_err(dev, "failed to add irqchip\n"); + gpiochip_remove(gc); + return ret; + } - irq_set_handler_data(hwirq, vg); - irq_set_chained_handler(hwirq, byt_gpio_irq_handler); - } - - ret = gpiochip_add(gc); - if (ret) { - dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); - return ret; + gpiochip_set_chained_irqchip(gc, &byt_irqchip, + (unsigned)irq_rc->start, + byt_gpio_irq_handler); } pm_runtime_enable(dev); -- cgit v1.2.3 From 302fb1781783ded370f515e8e649b8285ee29cdc Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 29 Jul 2014 02:12:55 +0400 Subject: sh-pfc: r8a7791: fix CAN pin groups I had made last-minute changes before submitting the patch "sh-pfc: r8a7791: add CAN pin groups"; now I'm seeing that they weren't complete: I had missed update to the pin group names in pin[01]_groups[]. Drop the "_a" suffixes there. Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 576d41b459e9..c6e5deba238e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -4509,24 +4509,24 @@ static const char * const audio_clk_groups[] = { }; static const char * const can0_groups[] = { - "can0_data_a", + "can0_data", "can0_data_b", "can0_data_c", "can0_data_d", "can0_data_e", "can0_data_f", - "can_clk_a", + "can_clk", "can_clk_b", "can_clk_c", "can_clk_d", }; static const char * const can1_groups[] = { - "can1_data_a", + "can1_data", "can1_data_b", "can1_data_c", "can1_data_d", - "can_clk_a", + "can_clk", "can_clk_b", "can_clk_c", "can_clk_d", -- cgit v1.2.3 From 99e872d953fb4484029c12dce909f514ae095d8d Mon Sep 17 00:00:00 2001 From: Sonny Rao Date: Thu, 31 Jul 2014 22:58:00 -0700 Subject: pinctrl: rockchip: fix rk3288 gpio0 configuration On rk3288, for gpio bank 0, the registers which configure pull-up, iomux, and drive strength don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio in that bank. The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of bank0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered. Signed-off-by: Sonny Rao Reviewed-by: Heiko Stuebner Reviewed-by: Doug Anderson Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 5e8b2e04cd7a..0c372a300cb8 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -438,7 +438,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) int reg, ret, mask; unsigned long flags; u8 bit; - u32 data; + u32 data, rmask; if (iomux_num > 3) return -EINVAL; @@ -478,8 +478,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) spin_lock_irqsave(&bank->slock, flags); data = (mask << (bit + 16)); + rmask = data | (data >> 16); data |= (mux & mask) << bit; - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, rmask, data); spin_unlock_irqrestore(&bank->slock, flags); @@ -634,7 +635,7 @@ static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num, struct regmap *regmap; unsigned long flags; int reg, ret, i; - u32 data; + u32 data, rmask; u8 bit; rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); @@ -657,9 +658,10 @@ static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num, /* enable the write to the equivalent lower bits */ data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); data |= (ret << bit); - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, rmask, data); spin_unlock_irqrestore(&bank->slock, flags); return ret; @@ -722,7 +724,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, int reg, ret; unsigned long flags; u8 bit; - u32 data; + u32 data, rmask; dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); @@ -750,6 +752,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, /* enable the write to the equivalent lower bits */ data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); switch (pull) { case PIN_CONFIG_BIAS_DISABLE: @@ -770,7 +773,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, return -EINVAL; } - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, rmask, data); spin_unlock_irqrestore(&bank->slock, flags); break; -- cgit v1.2.3 From 8e1594db7e43eaf4ea88b870e97fa3ab9f8f98e0 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 31 Jul 2014 18:22:17 +0300 Subject: pinctrl: tegra-xusb: fix an off by one test This shoudld be ">= ARRAY_SIZE()" instead of "> ARRAY_SIZE()". Fixes: dc0a39386687 ('pinctrl: Add NVIDIA Tegra XUSB pad controller support') Signed-off-by: Dan Carpenter Acked-by: Stephen Warren Acked-by: Thierry Reding Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-tegra-xusb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index a06620474845..419a047b9150 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -680,7 +680,7 @@ static struct phy *tegra_xusb_padctl_xlate(struct device *dev, if (args->args_count <= 0) return ERR_PTR(-EINVAL); - if (index > ARRAY_SIZE(padctl->phys)) + if (index >= ARRAY_SIZE(padctl->phys)) return ERR_PTR(-EINVAL); return padctl->phys[index]; -- cgit v1.2.3 From 8a3cfb7c1700732df9fc13439b313bf8db39fefd Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 31 Jul 2014 18:23:08 +0300 Subject: pinctrl: tegra-xusb: testing wrong variable in probe() There is a cut and paste bug so we test the wrong variable. "err" is never less than zero at this point. Signed-off-by: Dan Carpenter Acked-by: Stephen Warren Acked-by: Thierry Reding Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-tegra-xusb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index 419a047b9150..e641b4226c42 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -930,7 +930,8 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev) padctl->provider = devm_of_phy_provider_register(&pdev->dev, tegra_xusb_padctl_xlate); - if (err < 0) { + if (IS_ERR(padctl->provider)) { + err = PTR_ERR(padctl->provider); dev_err(&pdev->dev, "failed to register PHYs: %d\n", err); goto unregister; } -- cgit v1.2.3 From 1d54f0fd58314d5b197f6d16338263c00908daab Mon Sep 17 00:00:00 2001 From: Patrice CHOTARD Date: Fri, 1 Aug 2014 09:38:43 +0200 Subject: pinctrl: abx500: remove useless check pctldev can't be NULL at this stage so remove the check Reported-by: Dan Carpenter Signed-off-by: Patrice Chotard Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index a53a689a2bfa..8c6fd8d4dd3c 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -620,8 +620,7 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s, } else seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); - if (pctldev) - mode = abx500_get_mode(pctldev, chip, offset); + mode = abx500_get_mode(pctldev, chip, offset); seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); -- cgit v1.2.3 From 4b6fe45a79a9ca2429eaf8713be7bdc936c211c3 Mon Sep 17 00:00:00 2001 From: Hans Wennborg Date: Tue, 5 Aug 2014 21:43:16 -0700 Subject: pinctrl: pinctrl-at91.c: fix decimal printf format specifiers prefixed with 0x The prefix suggests the number should be printed in hex, so use the %x specifier to do that. Found by using regex suggested by Joe Perches. Signed-off-by: Hans Wennborg Acked-by: Alexandre Belloni Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index af1ba4fc150d..60464a2648aa 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -497,10 +497,10 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = { static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) { if (pin->mux) { - dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", + dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); } else { - dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", + dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", pin->bank + 'A', pin->pin, pin->conf); } } -- cgit v1.2.3 From f6a8249f9e55d45a47777d2a3cc69defa23c87bb Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Sat, 9 Aug 2014 01:48:05 +0200 Subject: pinctrl: exynos: Lock GPIOs as interrupts when used as EINTs Currently after configuring a GPIO pin as an interrupt related pinmux registers are changed, but there is no protection from calling gpio_direction_*() in a badly written driver, which would cause the same pinmux register to be reconfigured for regular input/output and this disabling interrupt capability of the pin. This patch addresses this issue by moving pinmux reconfiguration to .irq_{request,release}_resources() callback of irq_chip and calling gpio_lock_as_irq() helper to prevent reconfiguration of pin direction. Setting up a GPIO interrupt on Samsung SoCs is a two-step operation - in addition to trigger configuration in a dedicated register, the pinmux must be also reconfigured to GPIO interrupt, which is a different function than normal GPIO input, although I/O-wise they both behave in the same way and gpio_get_value() can be used on a pin configured as IRQ as well. Such design implies subtleties such as gpio_direction_input() not having to fail if a pin is already configured as an interrupt nor change the configuration to normal input. But the FLAG_USED_AS_IRQ set in gpiolib by gpio_lock_as_irq() is only used to check that gpio_direction_output() is not called, it's not used to prevent gpio_direction_input() to be called. So this is not a complete solution for Samsung SoCs but it's definitely a move in the right direction. Signed-off-by: Tomasz Figa [javier: use request resources instead of startup and expand commit message] Signed-off-by: Javier Martinez Canillas Signed-off-by: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-exynos.c | 69 ++++++++++++++++++++++++++++--- drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 2 files changed, 64 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 003bfd874a61..d7154ed0b0eb 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -127,14 +127,10 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) struct irq_chip *chip = irq_data_get_irq_chip(irqd); struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - struct samsung_pin_bank_type *bank_type = bank->type; struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned int pin = irqd->hwirq; - unsigned int shift = EXYNOS_EINT_CON_LEN * pin; + unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; unsigned int con, trig_type; unsigned long reg_con = our_chip->eint_con + bank->eint_offset; - unsigned long flags; - unsigned int mask; switch (type) { case IRQ_TYPE_EDGE_RISING: @@ -167,8 +163,32 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) con |= trig_type << shift; writel(con, d->virt_base + reg_con); + return 0; +} + +static int exynos_irq_request_resources(struct irq_data *irqd) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pin_bank_type *bank_type = bank->type; + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; + unsigned long reg_con = our_chip->eint_con + bank->eint_offset; + unsigned long flags; + unsigned int mask; + unsigned int con; + int ret; + + ret = gpio_lock_as_irq(&bank->gpio_chip, irqd->hwirq); + if (ret) { + dev_err(bank->gpio_chip.dev, "unable to lock pin %s-%lu IRQ\n", + bank->name, irqd->hwirq); + return ret; + } + reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; - shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; + shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; spin_lock_irqsave(&bank->slock, flags); @@ -180,9 +200,42 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) spin_unlock_irqrestore(&bank->slock, flags); + exynos_irq_unmask(irqd); + return 0; } +static void exynos_irq_release_resources(struct irq_data *irqd) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pin_bank_type *bank_type = bank->type; + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; + unsigned long reg_con = our_chip->eint_con + bank->eint_offset; + unsigned long flags; + unsigned int mask; + unsigned int con; + + reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; + shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + exynos_irq_mask(irqd); + + spin_lock_irqsave(&bank->slock, flags); + + con = readl(d->virt_base + reg_con); + con &= ~(mask << shift); + con |= FUNC_INPUT << shift; + writel(con, d->virt_base + reg_con); + + spin_unlock_irqrestore(&bank->slock, flags); + + gpio_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); +} + /* * irq_chip for gpio interrupts. */ @@ -193,6 +246,8 @@ static struct exynos_irq_chip exynos_gpio_irq_chip = { .irq_mask = exynos_irq_mask, .irq_ack = exynos_irq_ack, .irq_set_type = exynos_irq_set_type, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, }, .eint_con = EXYNOS_GPIO_ECON_OFFSET, .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, @@ -336,6 +391,8 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = { .irq_ack = exynos_irq_ack, .irq_set_type = exynos_irq_set_type, .irq_set_wake = exynos_wkup_irq_set_wake, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, }, .eint_con = EXYNOS_WKUP_ECON_OFFSET, .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 2b882320e8e9..5cedc9d26390 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -26,6 +26,7 @@ #include /* pinmux function number for pin as gpio output line */ +#define FUNC_INPUT 0x0 #define FUNC_OUTPUT 0x1 /** -- cgit v1.2.3 From 4f671cb25e0a1d2b903d9a19e66fa193572424cf Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 27 Jul 2014 09:52:51 +0400 Subject: pinctrl: Add i.MX21 pincontrol driver This patch adds pincontrol driver for Freescale i.MX21 SOCs. Signed-off-by: Alexander Shiyan Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-imx21.c | 342 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 350 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-imx21.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index bfd2c2e9f6cd..e1c5a87c80cd 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -114,6 +114,13 @@ config PINCTRL_IMX1 help Say Y here to enable the imx1 pinctrl driver +config PINCTRL_IMX21 + bool "i.MX21 pinctrl driver" + depends on SOC_IMX21 + select PINCTRL_IMX1_CORE + help + Say Y here to enable the i.MX21 pinctrl driver + config PINCTRL_IMX27 bool "IMX27 pinctrl driver" depends on SOC_IMX27 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 05d227508c95..b906ef184409 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o +obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o diff --git a/drivers/pinctrl/pinctrl-imx21.c b/drivers/pinctrl/pinctrl-imx21.c new file mode 100644 index 000000000000..1b3b2311b033 --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx21.c @@ -0,0 +1,342 @@ +/* + * i.MX21 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2014 Alexander Shiyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +#include "pinctrl-imx1.h" + +#define PAD_ID(port, pin) ((port) * 32 + (pin)) +#define PA 0 +#define PB 1 +#define PC 2 +#define PD 3 +#define PE 4 +#define PF 5 + +enum imx21_pads { + MX21_PAD_LSCLK = PAD_ID(PA, 5), + MX21_PAD_LD0 = PAD_ID(PA, 6), + MX21_PAD_LD1 = PAD_ID(PA, 7), + MX21_PAD_LD2 = PAD_ID(PA, 8), + MX21_PAD_LD3 = PAD_ID(PA, 9), + MX21_PAD_LD4 = PAD_ID(PA, 10), + MX21_PAD_LD5 = PAD_ID(PA, 11), + MX21_PAD_LD6 = PAD_ID(PA, 12), + MX21_PAD_LD7 = PAD_ID(PA, 13), + MX21_PAD_LD8 = PAD_ID(PA, 14), + MX21_PAD_LD9 = PAD_ID(PA, 15), + MX21_PAD_LD10 = PAD_ID(PA, 16), + MX21_PAD_LD11 = PAD_ID(PA, 17), + MX21_PAD_LD12 = PAD_ID(PA, 18), + MX21_PAD_LD13 = PAD_ID(PA, 19), + MX21_PAD_LD14 = PAD_ID(PA, 20), + MX21_PAD_LD15 = PAD_ID(PA, 21), + MX21_PAD_LD16 = PAD_ID(PA, 22), + MX21_PAD_LD17 = PAD_ID(PA, 23), + MX21_PAD_REV = PAD_ID(PA, 24), + MX21_PAD_CLS = PAD_ID(PA, 25), + MX21_PAD_PS = PAD_ID(PA, 26), + MX21_PAD_SPL_SPR = PAD_ID(PA, 27), + MX21_PAD_HSYNC = PAD_ID(PA, 28), + MX21_PAD_VSYNC = PAD_ID(PA, 29), + MX21_PAD_CONTRAST = PAD_ID(PA, 30), + MX21_PAD_OE_ACD = PAD_ID(PA, 31), + MX21_PAD_SD2_D0 = PAD_ID(PB, 4), + MX21_PAD_SD2_D1 = PAD_ID(PB, 5), + MX21_PAD_SD2_D2 = PAD_ID(PB, 6), + MX21_PAD_SD2_D3 = PAD_ID(PB, 7), + MX21_PAD_SD2_CMD = PAD_ID(PB, 8), + MX21_PAD_SD2_CLK = PAD_ID(PB, 9), + MX21_PAD_CSI_D0 = PAD_ID(PB, 10), + MX21_PAD_CSI_D1 = PAD_ID(PB, 11), + MX21_PAD_CSI_D2 = PAD_ID(PB, 12), + MX21_PAD_CSI_D3 = PAD_ID(PB, 13), + MX21_PAD_CSI_D4 = PAD_ID(PB, 14), + MX21_PAD_CSI_MCLK = PAD_ID(PB, 15), + MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16), + MX21_PAD_CSI_D5 = PAD_ID(PB, 17), + MX21_PAD_CSI_D6 = PAD_ID(PB, 18), + MX21_PAD_CSI_D7 = PAD_ID(PB, 19), + MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20), + MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21), + MX21_PAD_USB_BYP = PAD_ID(PB, 22), + MX21_PAD_USB_PWR = PAD_ID(PB, 23), + MX21_PAD_USB_OC = PAD_ID(PB, 24), + MX21_PAD_USBH_ON = PAD_ID(PB, 25), + MX21_PAD_USBH1_FS = PAD_ID(PB, 26), + MX21_PAD_USBH1_OE = PAD_ID(PB, 27), + MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28), + MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29), + MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30), + MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31), + MX21_PAD_USBG_SDA = PAD_ID(PC, 5), + MX21_PAD_USBG_SCL = PAD_ID(PC, 6), + MX21_PAD_USBG_ON = PAD_ID(PC, 7), + MX21_PAD_USBG_FS = PAD_ID(PC, 8), + MX21_PAD_USBG_OE = PAD_ID(PC, 9), + MX21_PAD_USBG_TXDM = PAD_ID(PC, 10), + MX21_PAD_USBG_TXDP = PAD_ID(PC, 11), + MX21_PAD_USBG_RXDM = PAD_ID(PC, 12), + MX21_PAD_USBG_RXDP = PAD_ID(PC, 13), + MX21_PAD_TOUT = PAD_ID(PC, 14), + MX21_PAD_TIN = PAD_ID(PC, 15), + MX21_PAD_SAP_FS = PAD_ID(PC, 16), + MX21_PAD_SAP_RXD = PAD_ID(PC, 17), + MX21_PAD_SAP_TXD = PAD_ID(PC, 18), + MX21_PAD_SAP_CLK = PAD_ID(PC, 19), + MX21_PAD_SSI1_FS = PAD_ID(PC, 20), + MX21_PAD_SSI1_RXD = PAD_ID(PC, 21), + MX21_PAD_SSI1_TXD = PAD_ID(PC, 22), + MX21_PAD_SSI1_CLK = PAD_ID(PC, 23), + MX21_PAD_SSI2_FS = PAD_ID(PC, 24), + MX21_PAD_SSI2_RXD = PAD_ID(PC, 25), + MX21_PAD_SSI2_TXD = PAD_ID(PC, 26), + MX21_PAD_SSI2_CLK = PAD_ID(PC, 27), + MX21_PAD_SSI3_FS = PAD_ID(PC, 28), + MX21_PAD_SSI3_RXD = PAD_ID(PC, 29), + MX21_PAD_SSI3_TXD = PAD_ID(PC, 30), + MX21_PAD_SSI3_CLK = PAD_ID(PC, 31), + MX21_PAD_I2C_DATA = PAD_ID(PD, 17), + MX21_PAD_I2C_CLK = PAD_ID(PD, 18), + MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19), + MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20), + MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21), + MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22), + MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23), + MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24), + MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25), + MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26), + MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27), + MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28), + MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29), + MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30), + MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31), + MX21_PAD_TEST_WB2 = PAD_ID(PE, 0), + MX21_PAD_TEST_WB1 = PAD_ID(PE, 1), + MX21_PAD_TEST_WB0 = PAD_ID(PE, 2), + MX21_PAD_UART2_CTS = PAD_ID(PE, 3), + MX21_PAD_UART2_RTS = PAD_ID(PE, 4), + MX21_PAD_PWMO = PAD_ID(PE, 5), + MX21_PAD_UART2_TXD = PAD_ID(PE, 6), + MX21_PAD_UART2_RXD = PAD_ID(PE, 7), + MX21_PAD_UART3_TXD = PAD_ID(PE, 8), + MX21_PAD_UART3_RXD = PAD_ID(PE, 9), + MX21_PAD_UART3_CTS = PAD_ID(PE, 10), + MX21_PAD_UART3_RTS = PAD_ID(PE, 11), + MX21_PAD_UART1_TXD = PAD_ID(PE, 12), + MX21_PAD_UART1_RXD = PAD_ID(PE, 13), + MX21_PAD_UART1_CTS = PAD_ID(PE, 14), + MX21_PAD_UART1_RTS = PAD_ID(PE, 15), + MX21_PAD_RTCK = PAD_ID(PE, 16), + MX21_PAD_RESET_OUT = PAD_ID(PE, 17), + MX21_PAD_SD1_D0 = PAD_ID(PE, 18), + MX21_PAD_SD1_D1 = PAD_ID(PE, 19), + MX21_PAD_SD1_D2 = PAD_ID(PE, 20), + MX21_PAD_SD1_D3 = PAD_ID(PE, 21), + MX21_PAD_SD1_CMD = PAD_ID(PE, 22), + MX21_PAD_SD1_CLK = PAD_ID(PE, 23), + MX21_PAD_NFRB = PAD_ID(PF, 0), + MX21_PAD_NFCE = PAD_ID(PF, 1), + MX21_PAD_NFWP = PAD_ID(PF, 2), + MX21_PAD_NFCLE = PAD_ID(PF, 3), + MX21_PAD_NFALE = PAD_ID(PF, 4), + MX21_PAD_NFRE = PAD_ID(PF, 5), + MX21_PAD_NFWE = PAD_ID(PF, 6), + MX21_PAD_NFIO0 = PAD_ID(PF, 7), + MX21_PAD_NFIO1 = PAD_ID(PF, 8), + MX21_PAD_NFIO2 = PAD_ID(PF, 9), + MX21_PAD_NFIO3 = PAD_ID(PF, 10), + MX21_PAD_NFIO4 = PAD_ID(PF, 11), + MX21_PAD_NFIO5 = PAD_ID(PF, 12), + MX21_PAD_NFIO6 = PAD_ID(PF, 13), + MX21_PAD_NFIO7 = PAD_ID(PF, 14), + MX21_PAD_CLKO = PAD_ID(PF, 15), + MX21_PAD_RESERVED = PAD_ID(PF, 16), + MX21_PAD_CS4 = PAD_ID(PF, 21), + MX21_PAD_CS5 = PAD_ID(PF, 22), +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX21_PAD_LSCLK), + IMX_PINCTRL_PIN(MX21_PAD_LD0), + IMX_PINCTRL_PIN(MX21_PAD_LD1), + IMX_PINCTRL_PIN(MX21_PAD_LD2), + IMX_PINCTRL_PIN(MX21_PAD_LD3), + IMX_PINCTRL_PIN(MX21_PAD_LD4), + IMX_PINCTRL_PIN(MX21_PAD_LD5), + IMX_PINCTRL_PIN(MX21_PAD_LD6), + IMX_PINCTRL_PIN(MX21_PAD_LD7), + IMX_PINCTRL_PIN(MX21_PAD_LD8), + IMX_PINCTRL_PIN(MX21_PAD_LD9), + IMX_PINCTRL_PIN(MX21_PAD_LD10), + IMX_PINCTRL_PIN(MX21_PAD_LD11), + IMX_PINCTRL_PIN(MX21_PAD_LD12), + IMX_PINCTRL_PIN(MX21_PAD_LD13), + IMX_PINCTRL_PIN(MX21_PAD_LD14), + IMX_PINCTRL_PIN(MX21_PAD_LD15), + IMX_PINCTRL_PIN(MX21_PAD_LD16), + IMX_PINCTRL_PIN(MX21_PAD_LD17), + IMX_PINCTRL_PIN(MX21_PAD_REV), + IMX_PINCTRL_PIN(MX21_PAD_CLS), + IMX_PINCTRL_PIN(MX21_PAD_PS), + IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR), + IMX_PINCTRL_PIN(MX21_PAD_HSYNC), + IMX_PINCTRL_PIN(MX21_PAD_VSYNC), + IMX_PINCTRL_PIN(MX21_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX21_PAD_OE_ACD), + IMX_PINCTRL_PIN(MX21_PAD_SD2_D0), + IMX_PINCTRL_PIN(MX21_PAD_SD2_D1), + IMX_PINCTRL_PIN(MX21_PAD_SD2_D2), + IMX_PINCTRL_PIN(MX21_PAD_SD2_D3), + IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D0), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D1), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX21_PAD_USB_BYP), + IMX_PINCTRL_PIN(MX21_PAD_USB_PWR), + IMX_PINCTRL_PIN(MX21_PAD_USB_OC), + IMX_PINCTRL_PIN(MX21_PAD_USBH_ON), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP), + IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA), + IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL), + IMX_PINCTRL_PIN(MX21_PAD_USBG_ON), + IMX_PINCTRL_PIN(MX21_PAD_USBG_FS), + IMX_PINCTRL_PIN(MX21_PAD_USBG_OE), + IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM), + IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP), + IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM), + IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP), + IMX_PINCTRL_PIN(MX21_PAD_TOUT), + IMX_PINCTRL_PIN(MX21_PAD_TIN), + IMX_PINCTRL_PIN(MX21_PAD_SAP_FS), + IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD), + IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD), + IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK), + IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS), + IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK), + IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS), + IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK), + IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS), + IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK), + IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA), + IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI), + IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2), + IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1), + IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0), + IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX21_PAD_PWMO), + IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD), + IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD), + IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS), + IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS), + IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX21_PAD_RTCK), + IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT), + IMX_PINCTRL_PIN(MX21_PAD_SD1_D0), + IMX_PINCTRL_PIN(MX21_PAD_SD1_D1), + IMX_PINCTRL_PIN(MX21_PAD_SD1_D2), + IMX_PINCTRL_PIN(MX21_PAD_SD1_D3), + IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX21_PAD_NFRB), + IMX_PINCTRL_PIN(MX21_PAD_NFCE), + IMX_PINCTRL_PIN(MX21_PAD_NFWP), + IMX_PINCTRL_PIN(MX21_PAD_NFCLE), + IMX_PINCTRL_PIN(MX21_PAD_NFALE), + IMX_PINCTRL_PIN(MX21_PAD_NFRE), + IMX_PINCTRL_PIN(MX21_PAD_NFWE), + IMX_PINCTRL_PIN(MX21_PAD_NFIO0), + IMX_PINCTRL_PIN(MX21_PAD_NFIO1), + IMX_PINCTRL_PIN(MX21_PAD_NFIO2), + IMX_PINCTRL_PIN(MX21_PAD_NFIO3), + IMX_PINCTRL_PIN(MX21_PAD_NFIO4), + IMX_PINCTRL_PIN(MX21_PAD_NFIO5), + IMX_PINCTRL_PIN(MX21_PAD_NFIO6), + IMX_PINCTRL_PIN(MX21_PAD_NFIO7), + IMX_PINCTRL_PIN(MX21_PAD_CLKO), + IMX_PINCTRL_PIN(MX21_PAD_RESERVED), + IMX_PINCTRL_PIN(MX21_PAD_CS4), + IMX_PINCTRL_PIN(MX21_PAD_CS5), +}; + +static struct imx1_pinctrl_soc_info imx21_pinctrl_info = { + .pins = imx21_pinctrl_pads, + .npins = ARRAY_SIZE(imx21_pinctrl_pads), +}; + +static int __init imx21_pinctrl_probe(struct platform_device *pdev) +{ + return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info); +} + +static const struct of_device_id imx21_pinctrl_of_match[] = { + { .compatible = "fsl,imx21-iomuxc", }, + { } +}; +MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match); + +static struct platform_driver imx21_pinctrl_driver = { + .driver = { + .name = "imx21-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx21_pinctrl_of_match, + }, + .remove = imx1_pinctrl_core_remove, +}; +module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe); + +MODULE_AUTHOR("Alexander Shiyan "); +MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 5dfe10b43a91642845dcf281e02ca43ffde0d750 Mon Sep 17 00:00:00 2001 From: Kiran Padwal Date: Mon, 11 Aug 2014 16:47:50 +0530 Subject: pinctrl: Make of_device_id array const Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Kiran Padwal Acked-by: Thierry Reding Acked-by: Stephen Warren Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-imx23.c | 2 +- drivers/pinctrl/pinctrl-imx25.c | 2 +- drivers/pinctrl/pinctrl-imx27.c | 2 +- drivers/pinctrl/pinctrl-imx28.c | 2 +- drivers/pinctrl/pinctrl-imx35.c | 2 +- drivers/pinctrl/pinctrl-imx50.c | 2 +- drivers/pinctrl/pinctrl-imx51.c | 2 +- drivers/pinctrl/pinctrl-imx53.c | 2 +- drivers/pinctrl/pinctrl-imx6dl.c | 2 +- drivers/pinctrl/pinctrl-imx6q.c | 2 +- drivers/pinctrl/pinctrl-imx6sl.c | 2 +- drivers/pinctrl/pinctrl-imx6sx.c | 2 +- drivers/pinctrl/pinctrl-tegra114.c | 2 +- drivers/pinctrl/pinctrl-tegra124.c | 2 +- drivers/pinctrl/pinctrl-tegra20.c | 2 +- drivers/pinctrl/pinctrl-tegra30.c | 2 +- drivers/pinctrl/spear/pinctrl-spear1310.c | 2 +- drivers/pinctrl/spear/pinctrl-spear1340.c | 2 +- drivers/pinctrl/spear/pinctrl-spear300.c | 2 +- drivers/pinctrl/spear/pinctrl-spear310.c | 2 +- drivers/pinctrl/spear/pinctrl-spear320.c | 2 +- 21 files changed, 21 insertions(+), 21 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c index e76d75c9d1ba..df79096becb0 100644 --- a/drivers/pinctrl/pinctrl-imx23.c +++ b/drivers/pinctrl/pinctrl-imx23.c @@ -272,7 +272,7 @@ static int imx23_pinctrl_probe(struct platform_device *pdev) return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data); } -static struct of_device_id imx23_pinctrl_of_match[] = { +static const struct of_device_id imx23_pinctrl_of_match[] = { { .compatible = "fsl,imx23-pinctrl", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx25.c b/drivers/pinctrl/pinctrl-imx25.c index 1aae1b61c4dc..550e6d77ac2b 100644 --- a/drivers/pinctrl/pinctrl-imx25.c +++ b/drivers/pinctrl/pinctrl-imx25.c @@ -315,7 +315,7 @@ static struct imx_pinctrl_soc_info imx25_pinctrl_info = { .npins = ARRAY_SIZE(imx25_pinctrl_pads), }; -static struct of_device_id imx25_pinctrl_of_match[] = { +static const struct of_device_id imx25_pinctrl_of_match[] = { { .compatible = "fsl,imx25-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c index f8dfefb69968..945eccadea74 100644 --- a/drivers/pinctrl/pinctrl-imx27.c +++ b/drivers/pinctrl/pinctrl-imx27.c @@ -389,7 +389,7 @@ static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { .npins = ARRAY_SIZE(imx27_pinctrl_pads), }; -static struct of_device_id imx27_pinctrl_of_match[] = { +static const struct of_device_id imx27_pinctrl_of_match[] = { { .compatible = "fsl,imx27-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c index 79c9c8d296af..3bd45da21229 100644 --- a/drivers/pinctrl/pinctrl-imx28.c +++ b/drivers/pinctrl/pinctrl-imx28.c @@ -388,7 +388,7 @@ static int imx28_pinctrl_probe(struct platform_device *pdev) return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data); } -static struct of_device_id imx28_pinctrl_of_match[] = { +static const struct of_device_id imx28_pinctrl_of_match[] = { { .compatible = "fsl,imx28-pinctrl", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c index 278a04ae8940..6bfbcd0112c1 100644 --- a/drivers/pinctrl/pinctrl-imx35.c +++ b/drivers/pinctrl/pinctrl-imx35.c @@ -1005,7 +1005,7 @@ static struct imx_pinctrl_soc_info imx35_pinctrl_info = { .npins = ARRAY_SIZE(imx35_pinctrl_pads), }; -static struct of_device_id imx35_pinctrl_of_match[] = { +static const struct of_device_id imx35_pinctrl_of_match[] = { { .compatible = "fsl,imx35-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx50.c b/drivers/pinctrl/pinctrl-imx50.c index b06feed1b038..e8bd604ab147 100644 --- a/drivers/pinctrl/pinctrl-imx50.c +++ b/drivers/pinctrl/pinctrl-imx50.c @@ -391,7 +391,7 @@ static struct imx_pinctrl_soc_info imx50_pinctrl_info = { .npins = ARRAY_SIZE(imx50_pinctrl_pads), }; -static struct of_device_id imx50_pinctrl_of_match[] = { +static const struct of_device_id imx50_pinctrl_of_match[] = { { .compatible = "fsl,imx50-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c index 19ab182bef61..b818051db7c9 100644 --- a/drivers/pinctrl/pinctrl-imx51.c +++ b/drivers/pinctrl/pinctrl-imx51.c @@ -768,7 +768,7 @@ static struct imx_pinctrl_soc_info imx51_pinctrl_info = { .npins = ARRAY_SIZE(imx51_pinctrl_pads), }; -static struct of_device_id imx51_pinctrl_of_match[] = { +static const struct of_device_id imx51_pinctrl_of_match[] = { { .compatible = "fsl,imx51-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c index f8d45c4cfde7..1884d53cf750 100644 --- a/drivers/pinctrl/pinctrl-imx53.c +++ b/drivers/pinctrl/pinctrl-imx53.c @@ -454,7 +454,7 @@ static struct imx_pinctrl_soc_info imx53_pinctrl_info = { .npins = ARRAY_SIZE(imx53_pinctrl_pads), }; -static struct of_device_id imx53_pinctrl_of_match[] = { +static const struct of_device_id imx53_pinctrl_of_match[] = { { .compatible = "fsl,imx53-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/pinctrl-imx6dl.c index db2a1489bd99..656c4b08cc2e 100644 --- a/drivers/pinctrl/pinctrl-imx6dl.c +++ b/drivers/pinctrl/pinctrl-imx6dl.c @@ -460,7 +460,7 @@ static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = { .npins = ARRAY_SIZE(imx6dl_pinctrl_pads), }; -static struct of_device_id imx6dl_pinctrl_of_match[] = { +static const struct of_device_id imx6dl_pinctrl_of_match[] = { { .compatible = "fsl,imx6dl-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c index 8eb5ac1bd5f6..59bb5b4ec0f6 100644 --- a/drivers/pinctrl/pinctrl-imx6q.c +++ b/drivers/pinctrl/pinctrl-imx6q.c @@ -466,7 +466,7 @@ static struct imx_pinctrl_soc_info imx6q_pinctrl_info = { .npins = ARRAY_SIZE(imx6q_pinctrl_pads), }; -static struct of_device_id imx6q_pinctrl_of_match[] = { +static const struct of_device_id imx6q_pinctrl_of_match[] = { { .compatible = "fsl,imx6q-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/pinctrl-imx6sl.c index f21b7389df3c..fa76d6cb15cf 100644 --- a/drivers/pinctrl/pinctrl-imx6sl.c +++ b/drivers/pinctrl/pinctrl-imx6sl.c @@ -366,7 +366,7 @@ static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = { .npins = ARRAY_SIZE(imx6sl_pinctrl_pads), }; -static struct of_device_id imx6sl_pinctrl_of_match[] = { +static const struct of_device_id imx6sl_pinctrl_of_match[] = { { .compatible = "fsl,imx6sl-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/pinctrl-imx6sx.c index 09758a56b9df..840344c8580d 100644 --- a/drivers/pinctrl/pinctrl-imx6sx.c +++ b/drivers/pinctrl/pinctrl-imx6sx.c @@ -370,7 +370,7 @@ static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = { .npins = ARRAY_SIZE(imx6sx_pinctrl_pads), }; -static struct of_device_id imx6sx_pinctrl_of_match[] = { +static const struct of_device_id imx6sx_pinctrl_of_match[] = { { .compatible = "fsl,imx6sx-iomuxc", }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c index 33614baab4c0..a3db85b0b75f 100644 --- a/drivers/pinctrl/pinctrl-tegra114.c +++ b/drivers/pinctrl/pinctrl-tegra114.c @@ -1850,7 +1850,7 @@ static int tegra114_pinctrl_probe(struct platform_device *pdev) return tegra_pinctrl_probe(pdev, &tegra114_pinctrl); } -static struct of_device_id tegra114_pinctrl_of_match[] = { +static const struct of_device_id tegra114_pinctrl_of_match[] = { { .compatible = "nvidia,tegra114-pinmux", }, { }, }; diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c index e80797e20017..cb3e596cade1 100644 --- a/drivers/pinctrl/pinctrl-tegra124.c +++ b/drivers/pinctrl/pinctrl-tegra124.c @@ -1996,7 +1996,7 @@ static int tegra124_pinctrl_probe(struct platform_device *pdev) return tegra_pinctrl_probe(pdev, &tegra124_pinctrl); } -static struct of_device_id tegra124_pinctrl_of_match[] = { +static const struct of_device_id tegra124_pinctrl_of_match[] = { { .compatible = "nvidia,tegra124-pinmux", }, { }, }; diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c index 7563ebc9c791..c9805d2e71b0 100644 --- a/drivers/pinctrl/pinctrl-tegra20.c +++ b/drivers/pinctrl/pinctrl-tegra20.c @@ -2228,7 +2228,7 @@ static int tegra20_pinctrl_probe(struct platform_device *pdev) return tegra_pinctrl_probe(pdev, &tegra20_pinctrl); } -static struct of_device_id tegra20_pinctrl_of_match[] = { +static const struct of_device_id tegra20_pinctrl_of_match[] = { { .compatible = "nvidia,tegra20-pinmux", }, { }, }; diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c index fe2d2cf78ad9..e7b72e916558 100644 --- a/drivers/pinctrl/pinctrl-tegra30.c +++ b/drivers/pinctrl/pinctrl-tegra30.c @@ -2484,7 +2484,7 @@ static int tegra30_pinctrl_probe(struct platform_device *pdev) return tegra_pinctrl_probe(pdev, &tegra30_pinctrl); } -static struct of_device_id tegra30_pinctrl_of_match[] = { +static const struct of_device_id tegra30_pinctrl_of_match[] = { { .compatible = "nvidia,tegra30-pinmux", }, { }, }; diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c index 1a8bbfec60ca..6d57d43ab640 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1310.c +++ b/drivers/pinctrl/spear/pinctrl-spear1310.c @@ -2692,7 +2692,7 @@ static struct spear_pinctrl_machdata spear1310_machdata = { .modes_supported = false, }; -static struct of_device_id spear1310_pinctrl_of_match[] = { +static const struct of_device_id spear1310_pinctrl_of_match[] = { { .compatible = "st,spear1310-pinmux", }, diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c index 873966e2b99f..d243e43e7f6d 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1340.c +++ b/drivers/pinctrl/spear/pinctrl-spear1340.c @@ -2008,7 +2008,7 @@ static struct spear_pinctrl_machdata spear1340_machdata = { .modes_supported = false, }; -static struct of_device_id spear1340_pinctrl_of_match[] = { +static const struct of_device_id spear1340_pinctrl_of_match[] = { { .compatible = "st,spear1340-pinmux", }, diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c index 4777c0d0e730..9db83e9ee18c 100644 --- a/drivers/pinctrl/spear/pinctrl-spear300.c +++ b/drivers/pinctrl/spear/pinctrl-spear300.c @@ -646,7 +646,7 @@ static struct spear_function *spear300_functions[] = { &gpio1_function, }; -static struct of_device_id spear300_pinctrl_of_match[] = { +static const struct of_device_id spear300_pinctrl_of_match[] = { { .compatible = "st,spear300-pinmux", }, diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c index ed1d3608f486..db775a414b7a 100644 --- a/drivers/pinctrl/spear/pinctrl-spear310.c +++ b/drivers/pinctrl/spear/pinctrl-spear310.c @@ -371,7 +371,7 @@ static struct spear_function *spear310_functions[] = { &tdm_function, }; -static struct of_device_id spear310_pinctrl_of_match[] = { +static const struct of_device_id spear310_pinctrl_of_match[] = { { .compatible = "st,spear310-pinmux", }, diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c index b8e290a8c8c9..80fbd68e17bc 100644 --- a/drivers/pinctrl/spear/pinctrl-spear320.c +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -3410,7 +3410,7 @@ static struct spear_function *spear320_functions[] = { &i2c2_function, }; -static struct of_device_id spear320_pinctrl_of_match[] = { +static const struct of_device_id spear320_pinctrl_of_match[] = { { .compatible = "st,spear320-pinmux", }, -- cgit v1.2.3 From ad3d7f1e8f0160b12ad8eb69f78015930645a166 Mon Sep 17 00:00:00 2001 From: Kiran Padwal Date: Mon, 11 Aug 2014 20:24:57 +0530 Subject: pinctrl: imx6sl: introduce MODULE_DEVICE_TABLE for module autoloading Enable autoloading of pinctrl-imx6sl module when a corresponing DT entry is present. Signed-off-by: Kiran Padwal Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-imx6sl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/pinctrl-imx6sl.c index fa76d6cb15cf..e0924bd7b98c 100644 --- a/drivers/pinctrl/pinctrl-imx6sl.c +++ b/drivers/pinctrl/pinctrl-imx6sl.c @@ -370,6 +370,7 @@ static const struct of_device_id imx6sl_pinctrl_of_match[] = { { .compatible = "fsl,imx6sl-iomuxc", }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match); static int imx6sl_pinctrl_probe(struct platform_device *pdev) { -- cgit v1.2.3 From 4bee325cd9bc06c5e7b3cc4398f101ed3fa5cc0e Mon Sep 17 00:00:00 2001 From: Bin Shi Date: Mon, 18 Aug 2014 16:49:20 +0800 Subject: pinctrl: sirf: fix "quoted string split across lines" this patch fixes: WARNING: quoted string split across lines 902: FILE: drivers/pinctrl/sirf/pinctrl-sirf.c:902: +MODULE_AUTHOR("Rongjun Ying , " + "Yuping Luo , " WARNING: quoted string split across lines 903: FILE: drivers/pinctrl/sirf/pinctrl-sirf.c:903: + "Yuping Luo , " + "Barry Song "); Signed-off-by: Bin Shi Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-sirf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 4c1d7c68666d..08d1f5a9601a 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -898,8 +898,8 @@ static int __init sirfsoc_gpio_init(void) } subsys_initcall(sirfsoc_gpio_init); -MODULE_AUTHOR("Rongjun Ying , " - "Yuping Luo , " - "Barry Song "); +MODULE_AUTHOR("Rongjun Ying "); +MODULE_AUTHOR("Yuping Luo "); +MODULE_AUTHOR("Barry Song "); MODULE_DESCRIPTION("SIRFSOC pin control driver"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From c09f80db583c72f9c6198842cd7e6f71105fdc46 Mon Sep 17 00:00:00 2001 From: Bin Shi Date: Mon, 18 Aug 2014 16:49:21 +0800 Subject: pinctrl: sirf: fix lots of "line over 80 characters" According to key customer's requirement, fix "line over 80 characters". Signed-off-by: Bin Shi Signed-off-by: Qipan Li Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-atlas6.c | 67 ++++++++++++++++----------- drivers/pinctrl/sirf/pinctrl-prima2.c | 85 +++++++++++++++++++++-------------- drivers/pinctrl/sirf/pinctrl-sirf.c | 57 ++++++++++++++--------- 3 files changed, 128 insertions(+), 81 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c index c4dd3d5cf9c3..b0bd2c4034c5 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -134,8 +134,9 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { .mask = BIT(30) | BIT(31), }, { .group = 2, - .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | - BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | + BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | + BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(31), }, }; @@ -148,14 +149,15 @@ static const struct sirfsoc_padmux lcd_16bits_padmux = { .funcval = 0, }; -static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, - 84, 85, 86, 95 }; +static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, + 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 }; static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { { .group = 2, - .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | - BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | + BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | + BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(31), }, { .group = 1, @@ -174,21 +176,23 @@ static const struct sirfsoc_padmux lcd_18bits_padmux = { .funcval = 0, }; -static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, - 84, 85, 86, 95 }; +static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, + 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 }; static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { { .group = 2, - .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | - BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | + BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | + BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(31), }, { .group = 1, .mask = BIT(30) | BIT(31), }, { .group = 0, - .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), + .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | + BIT(21) | BIT(22) | BIT(23), }, }; @@ -200,14 +204,16 @@ static const struct sirfsoc_padmux lcd_24bits_padmux = { .funcval = 0, }; -static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, - 80, 81, 82, 83, 84, 85, 86, 95}; +static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, + 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, + 85, 86, 95}; static const struct sirfsoc_muxmask lcdrom_muxmask[] = { { .group = 2, - .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | - BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | + BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) | + BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(31), }, { .group = 1, @@ -226,8 +232,8 @@ static const struct sirfsoc_padmux lcdrom_padmux = { .funcval = BIT(4), }; -static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, - 84, 85, 86, 95}; +static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, + 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95}; static const struct sirfsoc_muxmask uart0_muxmask[] = { { @@ -716,7 +722,8 @@ static const struct sirfsoc_padmux vip_padmux = { .funcval = BIT(18), }; -static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 }; +static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, + 60, 61 }; static const struct sirfsoc_muxmask vip_noupli_muxmask[] = { { @@ -737,7 +744,8 @@ static const struct sirfsoc_padmux vip_noupli_padmux = { .funcval = BIT(15), }; -static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 }; +static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, + 87, 88, 89 }; static const struct sirfsoc_muxmask i2c0_muxmask[] = { { @@ -876,7 +884,8 @@ static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = { .funcval = 0, }; -static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 }; +static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, + 41, 56, 57, 58, 59, 60, 61 }; static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { { @@ -1017,7 +1026,8 @@ static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" }; static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; -static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; +static const char * const + uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; static const char * const pulse_countgrp[] = { "pulse_countgrp" }; static const char * const i2sgrp[] = { "i2sgrp" }; static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; @@ -1038,7 +1048,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { uart0_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), - SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", + uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", usp0_uart_nostreamctrl_grp, @@ -1068,11 +1079,15 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), - SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux), - SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), - SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", + sdmmc2_nowpgrp, sdmmc2_nowp_padmux), + SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", + usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", + usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), - SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), + SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", + uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c index 8aa76f0776d7..fda2547f205e 100644 --- a/drivers/pinctrl/sirf/pinctrl-prima2.c +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -135,8 +135,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = { static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { { .group = 3, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | - BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | + BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18), }, { .group = 2, @@ -152,14 +153,15 @@ static const struct sirfsoc_padmux lcd_16bits_padmux = { .funcval = 0, }; -static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; +static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, + 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { { .group = 3, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | - BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | + BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18), }, { .group = 2, @@ -178,21 +180,23 @@ static const struct sirfsoc_padmux lcd_18bits_padmux = { .funcval = 0, }; -static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; +static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, + 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { { .group = 3, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | - BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | + BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18), }, { .group = 2, .mask = BIT(31), }, { .group = 0, - .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), + .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | + BIT(21) | BIT(22) | BIT(23), }, }; @@ -204,14 +208,16 @@ static const struct sirfsoc_padmux lcd_24bits_padmux = { .funcval = 0, }; -static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; +static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, + 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, + 110, 111, 112, 113, 114 }; static const struct sirfsoc_muxmask lcdrom_muxmask[] = { { .group = 3, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | - BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | + BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18), }, { .group = 2, @@ -230,8 +236,8 @@ static const struct sirfsoc_padmux lcdrom_padmux = { .funcval = BIT(4), }; -static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; +static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, + 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; static const struct sirfsoc_muxmask uart0_muxmask[] = { { @@ -685,7 +691,8 @@ static const struct sirfsoc_padmux vip_padmux = { .funcval = 0, }; -static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; +static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89 }; static const struct sirfsoc_muxmask i2c0_muxmask[] = { { @@ -735,7 +742,8 @@ static const struct sirfsoc_padmux viprom_padmux = { .funcval = BIT(0), }; -static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; +static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, + 87, 88, 89 }; static const struct sirfsoc_muxmask pwm0_muxmask[] = { { @@ -936,16 +944,19 @@ static const char * const uart1grp[] = { "uart1grp" }; static const char * const uart2grp[] = { "uart2grp" }; static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; static const char * const usp0grp[] = { "usp0grp" }; -static const char * const usp0_uart_nostreamctrl_grp[] = - { "usp0_uart_nostreamctrl_grp" }; +static const char * const usp0_uart_nostreamctrl_grp[] = { + "usp0_uart_nostreamctrl_grp" +}; static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; static const char * const usp1grp[] = { "usp1grp" }; -static const char * const usp1_uart_nostreamctrl_grp[] = - { "usp1_uart_nostreamctrl_grp" }; +static const char * const usp1_uart_nostreamctrl_grp[] = { + "usp1_uart_nostreamctrl_grp" +}; static const char * const usp2grp[] = { "usp2grp" }; -static const char * const usp2_uart_nostreamctrl_grp[] = - { "usp2_uart_nostreamctrl_grp" }; +static const char * const usp2_uart_nostreamctrl_grp[] = { + "usp2_uart_nostreamctrl_grp" +}; static const char * const i2c0grp[] = { "i2c0grp" }; static const char * const i2c1grp[] = { "i2c1grp" }; static const char * const pwm0grp[] = { "pwm0grp" }; @@ -966,7 +977,8 @@ static const char * const sdmmc5grp[] = { "sdmmc5grp" }; static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; -static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; +static const char * const + uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; static const char * const pulse_countgrp[] = { "pulse_countgrp" }; static const char * const i2sgrp[] = { "i2sgrp" }; static const char * const ac97grp[] = { "ac97grp" }; @@ -981,15 +993,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), - SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", + uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), - SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", + uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), - SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux), - SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_utfs", + usp0_only_utfs_grp, usp0_only_utfs_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_urfs", + usp0_only_urfs_grp, usp0_only_urfs_padmux), SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux), @@ -1013,10 +1029,13 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux), SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), - SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), - SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", + usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", + usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), - SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), + SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", + uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 08d1f5a9601a..45f93f952a39 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -58,17 +58,18 @@ static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, return sirfsoc_pin_groups[selector].name; } -static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) +static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) { *pins = sirfsoc_pin_groups[selector].pins; *num_pins = sirfsoc_pin_groups[selector].num_pins; return 0; } -static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) +static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned offset) { seq_printf(s, " " DRIVER_NAME); } @@ -138,22 +139,25 @@ static struct pinctrl_ops sirfsoc_pctrl_ops = { static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; static int sirfsoc_pmxfunc_cnt; -static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, - bool enable) +static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, + unsigned selector, bool enable) { int i; - const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; + const struct sirfsoc_padmux *mux = + sirfsoc_pmx_functions[selector].padmux; const struct sirfsoc_muxmask *mask = mux->muxmask; for (i = 0; i < mux->muxmask_counts; i++) { u32 muxval; if (!spmx->is_marco) { - muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + muxval = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(mask[i].group)); if (enable) muxval = muxval & ~mask[i].mask; else muxval = muxval | mask[i].mask; - writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + writel(muxval, spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(mask[i].group)); } else { if (enable) writel(mask[i].mask, spmx->gpio_virtbase + @@ -197,9 +201,10 @@ static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, return sirfsoc_pmx_functions[selector].name; } -static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) +static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) { *groups = sirfsoc_pmx_functions[selector].groups; *num_groups = sirfsoc_pmx_functions[selector].num_groups; @@ -218,9 +223,11 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, spmx = pinctrl_dev_get_drvdata(pmxdev); if (!spmx->is_marco) { - muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); + muxval = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(group)); muxval = muxval | (1 << (offset - range->pin_base)); - writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); + writel(muxval, spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(group)); } else { writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); @@ -518,24 +525,29 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) case IRQ_TYPE_NONE: break; case IRQ_TYPE_EDGE_RISING: - val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | + SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; break; case IRQ_TYPE_EDGE_FALLING: val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; - val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | + SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; break; case IRQ_TYPE_EDGE_BOTH: - val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | - SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | + SIRFSOC_GPIO_CTL_INTR_LOW_MASK | + SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; break; case IRQ_TYPE_LEVEL_LOW: - val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); + val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | + SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; break; case IRQ_TYPE_LEVEL_HIGH: val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; - val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); + val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | + SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); break; } @@ -694,7 +706,8 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, spin_unlock_irqrestore(&bank->lock, flags); } -static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) +static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, + unsigned gpio, int value) { struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); -- cgit v1.2.3 From ed36c1a06fc73cab289f66cc60b935951f4a1fa0 Mon Sep 17 00:00:00 2001 From: Rongjun Ying Date: Mon, 18 Aug 2014 16:49:22 +0800 Subject: pinctrl: atlas6: take mclk pin out of i2s pingroup The I2S controller can output mclk to external audio codec. But by hardware design, some codecs need mclk and some codecs do not need mclk. So the mclk pin can be an independent pinctrl group, and the card driver can get it or not based on boards. Signed-off-by: Rongjun Ying Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-atlas6.c | 41 ++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 17 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c index b0bd2c4034c5..9cc8faf56a6e 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -377,11 +377,25 @@ static const struct sirfsoc_padmux cko1_padmux = { static const unsigned cko1_pins[] = { 42 }; -static const struct sirfsoc_muxmask i2s_muxmask[] = { +static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = { { .group = 1, .mask = BIT(10), - }, { + }, +}; + +static const struct sirfsoc_padmux i2s_mclk_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask), + .muxmask = i2s_mclk_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(3), + .funcval = BIT(3), +}; + +static const unsigned i2s_mclk_pins[] = { 42 }; + +static const struct sirfsoc_muxmask i2s_muxmask[] = { + { .group = 3, .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), }, @@ -391,17 +405,12 @@ static const struct sirfsoc_padmux i2s_padmux = { .muxmask_counts = ARRAY_SIZE(i2s_muxmask), .muxmask = i2s_muxmask, .ctrlreg = SIRFSOC_RSC_PIN_MUX, - .funcmask = BIT(3), - .funcval = BIT(3), }; -static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 }; +static const unsigned i2s_pins[] = { 98, 99, 100, 101 }; static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { { - .group = 1, - .mask = BIT(10), - }, { .group = 3, .mask = BIT(2) | BIT(3) | BIT(4), }, @@ -411,17 +420,12 @@ static const struct sirfsoc_padmux i2s_no_din_padmux = { .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), .muxmask = i2s_no_din_muxmask, .ctrlreg = SIRFSOC_RSC_PIN_MUX, - .funcmask = BIT(3), - .funcval = BIT(3), }; -static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 }; +static const unsigned i2s_no_din_pins[] = { 98, 99, 100 }; static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { { - .group = 1, - .mask = BIT(10) | BIT(20) | BIT(23), - }, { .group = 3, .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), }, @@ -431,11 +435,11 @@ static const struct sirfsoc_padmux i2s_6chn_padmux = { .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), .muxmask = i2s_6chn_muxmask, .ctrlreg = SIRFSOC_RSC_PIN_MUX, - .funcmask = BIT(1) | BIT(3) | BIT(9), - .funcval = BIT(1) | BIT(3) | BIT(9), + .funcmask = BIT(1) | BIT(9), + .funcval = BIT(1) | BIT(9), }; -static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 }; +static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 }; static const struct sirfsoc_muxmask ac97_muxmask[] = { { @@ -977,6 +981,7 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), + SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins), SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), @@ -1029,6 +1034,7 @@ static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; static const char * const pulse_countgrp[] = { "pulse_countgrp" }; +static const char * const i2smclkgrp[] = { "i2smclkgrp" }; static const char * const i2sgrp[] = { "i2sgrp" }; static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; @@ -1089,6 +1095,7 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), + SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux), SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), -- cgit v1.2.3 From 086b8904b42a20983757fc21895d692f84e0af32 Mon Sep 17 00:00:00 2001 From: Rongjun Ying Date: Mon, 18 Aug 2014 16:49:24 +0800 Subject: pinctrl: atlas6: Add I2S external clock input pingroup The I2S controller can use the external clock as reference clock with master mode. But based on different hardware or software design, this external clock might be needed or not needed. So the external input pin can be an independent pinctrl group, and the card driver can decice to get it or not. Signed-off-by: Rongjun Ying Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-atlas6.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c index 9cc8faf56a6e..45f8391ddb34 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -394,6 +394,23 @@ static const struct sirfsoc_padmux i2s_mclk_padmux = { static const unsigned i2s_mclk_pins[] = { 42 }; +static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = { + { + .group = 1, + .mask = BIT(19), + }, +}; + +static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask), + .muxmask = i2s_ext_clk_input_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(2), + .funcval = BIT(2), +}; + +static const unsigned i2s_ext_clk_input_pins[] = { 51 }; + static const struct sirfsoc_muxmask i2s_muxmask[] = { { .group = 3, @@ -982,6 +999,7 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins), + SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins), SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), @@ -1035,6 +1053,7 @@ static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; static const char * const pulse_countgrp[] = { "pulse_countgrp" }; static const char * const i2smclkgrp[] = { "i2smclkgrp" }; +static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" }; static const char * const i2sgrp[] = { "i2sgrp" }; static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; @@ -1096,6 +1115,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux), + SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp, + i2s_ext_clk_input_padmux), SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), -- cgit v1.2.3 From 31320beaa3d3c5190e7db08144f37a2d519f6d6d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 22 Aug 2014 09:01:01 -0500 Subject: pinctrl: single: Add DRA7 pinctrl compatibility DRA7 pinctrl definitions now differ from traditional 16 bit OMAP pin ctrl definitions, in that all 32 bits are used to describe a single pin Also the location of wakeupenable and event bits have changed. Signed-off-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 95dd9cf55cb3..598d600ac7e4 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1981,6 +1981,12 @@ static const struct pcs_soc_data pinctrl_single_omap_wkup = { .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ }; +static const struct pcs_soc_data pinctrl_single_dra7 = { + .flags = PCS_QUIRK_SHARED_IRQ, + .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ + .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ +}; + static const struct pcs_soc_data pinctrl_single = { }; @@ -1992,6 +1998,7 @@ static struct of_device_id pcs_of_match[] = { { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, + { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, { .compatible = "pinctrl-single", .data = &pinctrl_single }, { .compatible = "pinconf-single", .data = &pinconf_single }, { }, -- cgit v1.2.3 From aa2293d82c29309d8399d41941add7af606a4fea Mon Sep 17 00:00:00 2001 From: Keerthy Date: Fri, 22 Aug 2014 09:01:02 -0500 Subject: pinctrl: single: AM437x: Add pinctrl compatibility AM437x pinctrl definitions now differ from traditional 16 bit OMAP pin ctrl definitions, in that all 32 bits are used to describe a single pin Also the location of wakeupenable and event bits have changed. Signed-off-by: Keerthy [nm@ti.com: minor updates] Signed-off-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 598d600ac7e4..784de13facf3 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1987,6 +1987,12 @@ static const struct pcs_soc_data pinctrl_single_dra7 = { .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ }; +static const struct pcs_soc_data pinctrl_single_am437x = { + .flags = PCS_QUIRK_SHARED_IRQ, + .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */ + .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ +}; + static const struct pcs_soc_data pinctrl_single = { }; @@ -1999,6 +2005,7 @@ static struct of_device_id pcs_of_match[] = { { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, + { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, { .compatible = "pinctrl-single", .data = &pinctrl_single }, { .compatible = "pinconf-single", .data = &pinconf_single }, { }, -- cgit v1.2.3 From 08e5a1feaed6877325c6146cbd3559b23fb4938f Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Wed, 27 Aug 2014 15:18:09 +0530 Subject: pinctrl: samsung: use CONFIG_PINCTRL_SAMSUNG symbol in makefile Samsung Exynos7 is a ARM64bit processor. Which does not select the CONFIG_PLAT_SAMSUNG symbol. CONFIG_PINCTRL_SAMSUNG is being selected for both PLAT_SAMSUNG and ARCH_EXYNOS7 symbols. This patch modifes the pinctrl/Makefile to use CONFIG_PINCTRL_SAMSUNG symbol to compile the pinctrl/samsung/*.c Signed-off-by: Naveen Krishna Chatradhi Cc: Tomasz Figa Cc: linus.walleij@linaro.org Cc: Thomas Abraham Signed-off-by: Linus Walleij --- drivers/pinctrl/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index b906ef184409..7ebb3c5a9c30 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -59,7 +59,7 @@ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-y += nomadik/ obj-$(CONFIG_ARCH_QCOM) += qcom/ -obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ +obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ obj-$(CONFIG_SUPERH) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ -- cgit v1.2.3 From a198420028bb6ddb1930dddc3602a3e9b4803ed5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 29 Aug 2014 14:39:19 +0200 Subject: pinctrl: sh-pfc: use a saner Kconfig symbol There is currently a kludge to get the Makefile to move down to sh-pfc:s drivers: the arch definitions are used twice to get it done. However we can very well use the Kconfig symbol for the SH PFC pin control feature itself: it doesn't matter that it comes from a lower leaf in the Kconfig hierarchy which is completely orthogonal. Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 7ebb3c5a9c30..0ffe1f608c67 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -60,8 +60,7 @@ obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-y += nomadik/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ -obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ -obj-$(CONFIG_SUPERH) += sh-pfc/ +obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ -- cgit v1.2.3 From c6e927a27498bf9314ba8e313d15d1b3f6046d7f Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Fri, 29 Aug 2014 13:41:48 +0530 Subject: pinctrl: qcom: remove gpiochip in failure cases This patch releases gpiochip related resources by calling gpiochip_remove when either of gpiochip_add_pin_range and gpiochip_irqchip_add fails. CC: Linus Walleij CC: "Ivan T. Ivanov" Acked-by: Bjorn Andersson Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 2738108caff2..9175bbc298c7 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -829,6 +829,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); if (ret) { dev_err(pctrl->dev, "Failed to add pin range\n"); + gpiochip_remove(&pctrl->chip); return ret; } @@ -839,6 +840,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) IRQ_TYPE_NONE); if (ret) { dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); + gpiochip_remove(&pctrl->chip); return -ENOSYS; } -- cgit v1.2.3 From 327455817a92522e669d2d11367e42af5956a8ed Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Fri, 29 Aug 2014 20:00:59 +0530 Subject: pinctrl: qcom: Add support for reset for apq8064 This patch adds support for reset functions to reboot the boards with soc apq8064. Cc: Linus Walleij Cc: "Ivan T. Ivanov" Cc: Stephen Boyd Cc: Andy Gross Acked-by: Bjorn Andersson Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-apq8064.c | 7 ++++++- drivers/pinctrl/qcom/pinctrl-msm.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index feb6f152f9b7..ef1263c7bdde 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -324,6 +324,7 @@ enum apq8064_functions { APQ_MUX_tsif1, APQ_MUX_tsif2, APQ_MUX_usb2_hsic, + APQ_MUX_ps_hold, APQ_MUX_NA, }; @@ -351,6 +352,9 @@ static const char * const gpio_groups[] = { "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89" }; +static const char * const ps_hold_groups[] = { + "gpio78" +}; static const char * const gsbi1_groups[] = { "gpio18", "gpio19", "gpio20", "gpio21" }; @@ -477,6 +481,7 @@ static const struct msm_function apq8064_functions[] = { FUNCTION(tsif1), FUNCTION(tsif2), FUNCTION(usb2_hsic), + FUNCTION(ps_hold), }; static const struct msm_pingroup apq8064_groups[] = { @@ -558,7 +563,7 @@ static const struct msm_pingroup apq8064_groups[] = { PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 9175bbc298c7..80a64cad907d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -12,6 +12,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -27,12 +28,15 @@ #include #include +#include + #include "../core.h" #include "../pinconf.h" #include "pinctrl-msm.h" #include "../pinctrl-utils.h" #define MAX_NR_GPIO 300 +#define PS_HOLD_OFFSET 0x820 /** * struct msm_pinctrl - state for a pinctrl-msm device @@ -850,6 +854,30 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) return 0; } +#ifdef CONFIG_ARM +static void __iomem *msm_ps_hold; + +static void msm_reset(enum reboot_mode reboot_mode, const char *cmd) +{ + writel(0, msm_ps_hold); + mdelay(10000); +} + +static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) +{ + int i = 0; + const struct msm_function *func = pctrl->soc->functions; + + for (; i <= pctrl->soc->nfunctions; i++) + if (!strcmp(func[i].name, "ps_hold")) { + msm_ps_hold = pctrl->regs + PS_HOLD_OFFSET; + arm_pm_restart = msm_reset; + } +} +#else +static void msm_pinctrl_setup_pm_reset(const struct msm_pinctrl *pctrl) {} +#endif + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { @@ -873,6 +901,8 @@ int msm_pinctrl_probe(struct platform_device *pdev, if (IS_ERR(pctrl->regs)) return PTR_ERR(pctrl->regs); + msm_pinctrl_setup_pm_reset(pctrl); + pctrl->irq = platform_get_irq(pdev, 0); if (pctrl->irq < 0) { dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); -- cgit v1.2.3 From 03e9f0cac5da6af85758276cb4624caf5911f2b9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 3 Sep 2014 13:02:56 +0200 Subject: pinctrl: clean up after enable refactoring commit 2243a87d90b42eb38bc281957df3e57c712b5e56 "pinctrl: avoid duplicated calling enable_pinmux_setting for a pin" removed the .disable callback from the struct pinmux_ops, making the .enable() callback the only remaining callback. However .enable() is a bad name as it seems to imply that a muxing can also be disabled. Rename the callback to .set_mux() and also take this opportunity to clean out any remaining mentions of .disable() from the documentation. Acked-by: Stephen Warren Acked-by: Bjorn Andersson Acked-by: Fan Wu Signed-off-by: Linus Walleij --- drivers/pinctrl/berlin/berlin.c | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-mvebu.c | 6 +++--- drivers/pinctrl/nomadik/pinctrl-abx500.c | 6 +++--- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 6 +++--- drivers/pinctrl/pinctrl-adi2.c | 6 +++--- drivers/pinctrl/pinctrl-as3722.c | 4 ++-- drivers/pinctrl/pinctrl-at91.c | 6 +++--- drivers/pinctrl/pinctrl-bcm281xx.c | 8 ++++---- drivers/pinctrl/pinctrl-bcm2835.c | 4 ++-- drivers/pinctrl/pinctrl-imx.c | 6 +++--- drivers/pinctrl/pinctrl-imx1-core.c | 6 +++--- drivers/pinctrl/pinctrl-lantiq.c | 8 ++++---- drivers/pinctrl/pinctrl-mxs.c | 6 +++--- drivers/pinctrl/pinctrl-palmas.c | 5 +++-- drivers/pinctrl/pinctrl-rockchip.c | 6 +++--- drivers/pinctrl/pinctrl-single.c | 4 ++-- drivers/pinctrl/pinctrl-st.c | 6 +++--- drivers/pinctrl/pinctrl-tb10x.c | 4 ++-- drivers/pinctrl/pinctrl-tegra-xusb.c | 8 ++++---- drivers/pinctrl/pinctrl-tegra.c | 7 ++++--- drivers/pinctrl/pinctrl-tz1090-pdc.c | 7 ++++--- drivers/pinctrl/pinctrl-tz1090.c | 6 +++--- drivers/pinctrl/pinctrl-u300.c | 6 +++--- drivers/pinctrl/pinmux.c | 10 +++++----- drivers/pinctrl/qcom/pinctrl-msm.c | 8 ++++---- drivers/pinctrl/samsung/pinctrl-exynos5440.c | 7 ++++--- drivers/pinctrl/samsung/pinctrl-samsung.c | 7 ++++--- drivers/pinctrl/sh-pfc/pinctrl.c | 6 +++--- drivers/pinctrl/sirf/pinctrl-sirf.c | 7 ++++--- drivers/pinctrl/spear/pinctrl-spear.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 8 ++++---- drivers/pinctrl/vt8500/pinctrl-wmt.c | 8 ++++---- 32 files changed, 105 insertions(+), 99 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index 86db2235ab00..61f1bf0e60ba 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -170,9 +170,9 @@ berlin_pinctrl_find_function_by_name(struct berlin_pinctrl *pctrl, return NULL; } -static int berlin_pinmux_enable(struct pinctrl_dev *pctrl_dev, - unsigned function, - unsigned group) +static int berlin_pinmux_set(struct pinctrl_dev *pctrl_dev, + unsigned function, + unsigned group) { struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); const struct berlin_desc_group *group_desc = pctrl->desc->groups + group; @@ -197,7 +197,7 @@ static const struct pinmux_ops berlin_pinmux_ops = { .get_functions_count = &berlin_pinmux_get_functions_count, .get_function_name = &berlin_pinmux_get_function_name, .get_function_groups = &berlin_pinmux_get_function_groups, - .enable = &berlin_pinmux_enable, + .set_mux = &berlin_pinmux_set, }; static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl, diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 9908374f8f92..f3b426cdaf8f 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -259,8 +259,8 @@ static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid, return 0; } -static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid, - unsigned gid) +static int mvebu_pinmux_set(struct pinctrl_dev *pctldev, unsigned fid, + unsigned gid) { struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct mvebu_pinctrl_function *func = &pctl->functions[fid]; @@ -344,7 +344,7 @@ static const struct pinmux_ops mvebu_pinmux_ops = { .get_function_groups = mvebu_pinmux_get_groups, .gpio_request_enable = mvebu_pinmux_gpio_request_enable, .gpio_set_direction = mvebu_pinmux_gpio_set_direction, - .enable = mvebu_pinmux_enable, + .set_mux = mvebu_pinmux_set, }; static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index a53a689a2bfa..b0289824cf73 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -709,8 +709,8 @@ static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, return 0; } -static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) +static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) { struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); struct gpio_chip *chip = &pct->chip; @@ -784,7 +784,7 @@ static const struct pinmux_ops abx500_pinmux_ops = { .get_functions_count = abx500_pmx_get_funcs_cnt, .get_function_name = abx500_pmx_get_func_name, .get_function_groups = abx500_pmx_get_func_groups, - .enable = abx500_pmx_enable, + .set_mux = abx500_pmx_set, .gpio_request_enable = abx500_gpio_request_enable, .gpio_disable_free = abx500_gpio_disable_free, }; diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index e7cab07eef47..c093d75a022a 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1647,8 +1647,8 @@ static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, return 0; } -static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) +static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) { struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); const struct nmk_pingroup *g; @@ -1810,7 +1810,7 @@ static const struct pinmux_ops nmk_pinmux_ops = { .get_functions_count = nmk_pmx_get_funcs_cnt, .get_function_name = nmk_pmx_get_func_name, .get_function_groups = nmk_pmx_get_func_groups, - .enable = nmk_pmx_enable, + .set_mux = nmk_pmx_set, .gpio_request_enable = nmk_gpio_request_enable, .gpio_disable_free = nmk_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index b092b93c67a1..e02943b0285d 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -619,8 +619,8 @@ static struct pinctrl_ops adi_pctrl_ops = { .get_group_pins = adi_get_group_pins, }; -static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id, - unsigned group_id) +static int adi_pinmux_set(struct pinctrl_dev *pctldev, unsigned func_id, + unsigned group_id) { struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); struct gpio_port *port; @@ -698,7 +698,7 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev, } static struct pinmux_ops adi_pinmux_ops = { - .enable = adi_pinmux_enable, + .set_mux = adi_pinmux_set, .get_functions_count = adi_pinmux_get_funcs_count, .get_function_name = adi_pinmux_get_func_name, .get_function_groups = adi_pinmux_get_groups, diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c index 0e4ec91f4d49..1f790a4b83fe 100644 --- a/drivers/pinctrl/pinctrl-as3722.c +++ b/drivers/pinctrl/pinctrl-as3722.c @@ -230,7 +230,7 @@ static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, return 0; } -static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, +static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function, unsigned group) { struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); @@ -327,7 +327,7 @@ static const struct pinmux_ops as3722_pinmux_ops = { .get_functions_count = as3722_pinctrl_get_funcs_count, .get_function_name = as3722_pinctrl_get_func_name, .get_function_groups = as3722_pinctrl_get_func_groups, - .enable = as3722_pinctrl_enable, + .set_mux = as3722_pinctrl_set, .gpio_request_enable = as3722_pinctrl_gpio_request_enable, .gpio_set_direction = as3722_pinctrl_gpio_set_direction, }; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index af1ba4fc150d..4839c36a3a1c 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -554,8 +554,8 @@ static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); } -static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; @@ -684,7 +684,7 @@ static const struct pinmux_ops at91_pmx_ops = { .get_functions_count = at91_pmx_get_funcs_count, .get_function_name = at91_pmx_get_func_name, .get_function_groups = at91_pmx_get_groups, - .enable = at91_pmx_enable, + .set_mux = at91_pmx_set, .gpio_request_enable = at91_gpio_request_enable, .gpio_disable_free = at91_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/pinctrl-bcm281xx.c index c5ca9e633fff..a26e0c2ba33e 100644 --- a/drivers/pinctrl/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/pinctrl-bcm281xx.c @@ -1055,9 +1055,9 @@ static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, return 0; } -static int bcm281xx_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) +static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); const struct bcm281xx_pin_function *f = &pdata->functions[function]; @@ -1084,7 +1084,7 @@ static struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = { .get_functions_count = bcm281xx_pinctrl_get_fcns_count, .get_function_name = bcm281xx_pinctrl_get_fcn_name, .get_function_groups = bcm281xx_pinctrl_get_fcn_groups, - .enable = bcm281xx_pinmux_enable, + .set_mux = bcm281xx_pinmux_set, }; static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c index 5bcfd7ace0cd..eabba02f71f9 100644 --- a/drivers/pinctrl/pinctrl-bcm2835.c +++ b/drivers/pinctrl/pinctrl-bcm2835.c @@ -830,7 +830,7 @@ static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, return 0; } -static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev, +static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, unsigned func_selector, unsigned group_selector) { @@ -869,7 +869,7 @@ static const struct pinmux_ops bcm2835_pmx_ops = { .get_functions_count = bcm2835_pmx_get_functions_count, .get_function_name = bcm2835_pmx_get_function_name, .get_function_groups = bcm2835_pmx_get_function_groups, - .enable = bcm2835_pmx_enable, + .set_mux = bcm2835_pmx_set, .gpio_disable_free = bcm2835_pmx_gpio_disable_free, .gpio_set_direction = bcm2835_pmx_gpio_set_direction, }; diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index 946d594a64dd..570e5acb4a6a 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -179,8 +179,8 @@ static const struct pinctrl_ops imx_pctrl_ops = { }; -static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; @@ -298,7 +298,7 @@ static const struct pinmux_ops imx_pmx_ops = { .get_functions_count = imx_pmx_get_funcs_count, .get_function_name = imx_pmx_get_func_name, .get_function_groups = imx_pmx_get_groups, - .enable = imx_pmx_enable, + .set_mux = imx_pmx_set, }; static int imx_pinconf_get(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c index 483420757c9f..176a3e62f1cf 100644 --- a/drivers/pinctrl/pinctrl-imx1-core.c +++ b/drivers/pinctrl/pinctrl-imx1-core.c @@ -298,8 +298,8 @@ static const struct pinctrl_ops imx1_pctrl_ops = { }; -static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx1_pinctrl_soc_info *info = ipctl->info; @@ -385,7 +385,7 @@ static const struct pinmux_ops imx1_pmx_ops = { .get_functions_count = imx1_pmx_get_funcs_count, .get_function_name = imx1_pmx_get_func_name, .get_function_groups = imx1_pmx_get_groups, - .enable = imx1_pmx_enable, + .set_mux = imx1_pmx_set, }; static int imx1_pinconf_get(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index d22ca252b80d..296e5b37f768 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -257,9 +257,9 @@ static int match_group_mux(const struct ltq_pin_group *grp, return ret; } -static int ltq_pmx_enable(struct pinctrl_dev *pctrldev, - unsigned func, - unsigned group) +static int ltq_pmx_set(struct pinctrl_dev *pctrldev, + unsigned func, + unsigned group) { struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); const struct ltq_pin_group *pin_grp = &info->grps[group]; @@ -316,7 +316,7 @@ static const struct pinmux_ops ltq_pmx_ops = { .get_functions_count = ltq_pmx_func_count, .get_function_name = ltq_pmx_func_name, .get_function_groups = ltq_pmx_get_groups, - .enable = ltq_pmx_enable, + .set_mux = ltq_pmx_set, .gpio_request_enable = ltq_pmx_gpio_request_enable, }; diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c index 40c76f26998c..67035091f8fd 100644 --- a/drivers/pinctrl/pinctrl-mxs.c +++ b/drivers/pinctrl/pinctrl-mxs.c @@ -195,8 +195,8 @@ static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, return 0; } -static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); struct mxs_group *g = &d->soc->groups[group]; @@ -223,7 +223,7 @@ static const struct pinmux_ops mxs_pinmux_ops = { .get_functions_count = mxs_pinctrl_get_funcs_count, .get_function_name = mxs_pinctrl_get_func_name, .get_function_groups = mxs_pinctrl_get_func_groups, - .enable = mxs_pinctrl_enable, + .set_mux = mxs_pinctrl_set_mux, }; static int mxs_pinconf_get(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index f13d0e78a41c..e3079d3d19fe 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -685,7 +685,8 @@ static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, return 0; } -static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, +static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned function, unsigned group) { struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); @@ -742,7 +743,7 @@ static const struct pinmux_ops palmas_pinmux_ops = { .get_functions_count = palmas_pinctrl_get_funcs_count, .get_function_name = palmas_pinctrl_get_func_name, .get_function_groups = palmas_pinctrl_get_func_groups, - .enable = palmas_pinctrl_enable, + .set_mux = palmas_pinctrl_set_mux, }; static int palmas_pinconf_get(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 5e8b2e04cd7a..b91b966add8f 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -813,8 +813,8 @@ static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, return 0; } -static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const unsigned int *pins = info->groups[group].pins; @@ -889,7 +889,7 @@ static const struct pinmux_ops rockchip_pmx_ops = { .get_functions_count = rockchip_pmx_get_funcs_count, .get_function_name = rockchip_pmx_get_func_name, .get_function_groups = rockchip_pmx_get_groups, - .enable = rockchip_pmx_enable, + .set_mux = rockchip_pmx_set, .gpio_set_direction = rockchip_pmx_gpio_set_direction, }; diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 784de13facf3..9032422ad18f 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -447,7 +447,7 @@ static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, +static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, unsigned group) { struct pcs_device *pcs; @@ -519,7 +519,7 @@ static const struct pinmux_ops pcs_pinmux_ops = { .get_functions_count = pcs_get_functions_count, .get_function_name = pcs_get_function_name, .get_function_groups = pcs_get_function_groups, - .enable = pcs_enable, + .set_mux = pcs_sex_mux, .gpio_request_enable = pcs_request_gpio, }; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 5475374d803f..6c4c41bed1e3 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -914,8 +914,8 @@ static struct st_pio_control *st_get_pio_control( return &bank->pc; } -static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector, - unsigned group) +static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, + unsigned group) { struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); struct st_pinconf *conf = info->groups[group].pin_conf; @@ -951,7 +951,7 @@ static struct pinmux_ops st_pmxops = { .get_functions_count = st_pmx_get_funcs_count, .get_function_name = st_pmx_get_fname, .get_function_groups = st_pmx_get_groups, - .enable = st_pmx_enable, + .set_mux = st_pmx_set_mux, .gpio_set_direction = st_pmx_set_gpio_direction, }; diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index 71c5d4f0c538..3b9bfcf717ac 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -697,7 +697,7 @@ static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl, mutex_unlock(&state->mutex); } -static int tb10x_pctl_enable(struct pinctrl_dev *pctl, +static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl, unsigned func_selector, unsigned group_selector) { struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); @@ -744,7 +744,7 @@ static struct pinmux_ops tb10x_pinmux_ops = { .get_function_groups = tb10x_get_function_groups, .gpio_request_enable = tb10x_gpio_request_enable, .gpio_disable_free = tb10x_gpio_disable_free, - .enable = tb10x_pctl_enable, + .set_mux = tb10x_pctl_set_mux, }; static struct pinctrl_desc tb10x_pindesc = { diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index a06620474845..4648c9e5c582 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -281,9 +281,9 @@ static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl, return 0; } -static int tegra_xusb_padctl_pinmux_enable(struct pinctrl_dev *pinctrl, - unsigned int function, - unsigned int group) +static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl, + unsigned int function, + unsigned int group) { struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); const struct tegra_xusb_padctl_lane *lane; @@ -311,7 +311,7 @@ static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = { .get_functions_count = tegra_xusb_padctl_get_functions_count, .get_function_name = tegra_xusb_padctl_get_function_name, .get_function_groups = tegra_xusb_padctl_get_function_groups, - .enable = tegra_xusb_padctl_pinmux_enable, + .set_mux = tegra_xusb_padctl_pinmux_set, }; static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl, diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index 150af5503c09..e5949d51bc52 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -262,8 +262,9 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, return 0; } -static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) +static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); const struct tegra_pingroup *g; @@ -294,7 +295,7 @@ static const struct pinmux_ops tegra_pinmux_ops = { .get_functions_count = tegra_pinctrl_get_funcs_count, .get_function_name = tegra_pinctrl_get_func_name, .get_function_groups = tegra_pinctrl_get_func_groups, - .enable = tegra_pinctrl_enable, + .set_mux = tegra_pinctrl_set_mux, }; static int tegra_pinconf_reg(struct tegra_pmx *pmx, diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index 41e81a35cabb..3bb6a3b78864 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -547,8 +547,9 @@ static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx, __global_unlock2(flags); } -static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev, - unsigned int function, unsigned int group) +static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) { struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; @@ -634,7 +635,7 @@ static struct pinmux_ops tz1090_pdc_pinmux_ops = { .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, .get_function_name = tz1090_pdc_pinctrl_get_func_name, .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, - .enable = tz1090_pdc_pinctrl_enable, + .set_mux = tz1090_pdc_pinctrl_set_mux, .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index 24082216842e..48d36413b99f 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1415,8 +1415,8 @@ found_mux: * the effect is the same as enabling the function on each individual pin in the * group. */ -static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev, - unsigned int function, unsigned int group) +static int tz1090_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) { struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); struct tz1090_pingroup *grp; @@ -1517,7 +1517,7 @@ static struct pinmux_ops tz1090_pinmux_ops = { .get_functions_count = tz1090_pinctrl_get_funcs_count, .get_function_name = tz1090_pinctrl_get_func_name, .get_function_groups = tz1090_pinctrl_get_func_groups, - .enable = tz1090_pinctrl_enable, + .set_mux = tz1090_pinctrl_set_mux, .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, }; diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 0959bb36450f..e9c7113d81f2 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -955,8 +955,8 @@ static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector, } } -static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { struct u300_pmx *upmx; @@ -994,7 +994,7 @@ static const struct pinmux_ops u300_pmx_ops = { .get_functions_count = u300_pmx_get_funcs_count, .get_function_name = u300_pmx_get_func_name, .get_function_groups = u300_pmx_get_groups, - .enable = u300_pmx_enable, + .set_mux = u300_pmx_set_mux, }; static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index c055daf9a80f..b874458dcb88 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -41,7 +41,7 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev) !ops->get_functions_count || !ops->get_function_name || !ops->get_function_groups || - !ops->enable) { + !ops->set_mux) { dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); return -EINVAL; } @@ -445,15 +445,15 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting) desc->mux_setting = &(setting->data.mux); } - ret = ops->enable(pctldev, setting->data.mux.func, - setting->data.mux.group); + ret = ops->set_mux(pctldev, setting->data.mux.func, + setting->data.mux.group); if (ret) - goto err_enable; + goto err_set_mux; return 0; -err_enable: +err_set_mux: for (i = 0; i < num_pins; i++) { desc = pin_desc_get(pctldev, pins[i]); if (desc) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 80a64cad907d..01eab47a746f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -134,9 +134,9 @@ static int msm_get_function_groups(struct pinctrl_dev *pctldev, return 0; } -static int msm_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) +static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) { struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct msm_pingroup *g; @@ -170,7 +170,7 @@ static const struct pinmux_ops msm_pinmux_ops = { .get_functions_count = msm_get_functions_count, .get_function_name = msm_get_function_name, .get_function_groups = msm_get_function_groups, - .enable = msm_pinmux_enable, + .set_mux = msm_pinmux_set_mux, }; static int msm_config_reg(struct msm_pinctrl *pctrl, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c index 603da2f9dd95..b995ec2c5d16 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -364,8 +364,9 @@ static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned select } /* enable a specified pinmux by writing to registers */ -static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, + unsigned group) { exynos5440_pinmux_setup(pctldev, selector, group, true); return 0; @@ -387,7 +388,7 @@ static const struct pinmux_ops exynos5440_pinmux_ops = { .get_functions_count = exynos5440_get_functions_count, .get_function_name = exynos5440_pinmux_get_fname, .get_function_groups = exynos5440_pinmux_get_groups, - .enable = exynos5440_pinmux_enable, + .set_mux = exynos5440_pinmux_set_mux, .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, }; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index b07406da333c..4a47691c32b1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -401,8 +401,9 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, } /* enable a specified pinmux by writing to registers */ -static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, + unsigned group) { samsung_pinmux_setup(pctldev, selector, group, true); return 0; @@ -413,7 +414,7 @@ static const struct pinmux_ops samsung_pinmux_ops = { .get_functions_count = samsung_get_functions_count, .get_function_name = samsung_pinmux_get_fname, .get_function_groups = samsung_pinmux_get_groups, - .enable = samsung_pinmux_enable, + .set_mux = samsung_pinmux_set_mux, }; /* set or get the pin config settings for a specified pin */ diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 11db3ee39d40..910deaefa0ac 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -312,8 +312,8 @@ static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, return 0; } -static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; @@ -442,7 +442,7 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = { .get_functions_count = sh_pfc_get_functions_count, .get_function_name = sh_pfc_get_function_name, .get_function_groups = sh_pfc_get_function_groups, - .enable = sh_pfc_func_enable, + .set_mux = sh_pfc_func_set_mux, .gpio_request_enable = sh_pfc_gpio_request_enable, .gpio_disable_free = sh_pfc_gpio_disable_free, .gpio_set_direction = sh_pfc_gpio_set_direction, diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 45f93f952a39..6f252fd7cb0c 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -179,8 +179,9 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, } } -static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, - unsigned group) +static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev, + unsigned selector, + unsigned group) { struct sirfsoc_pmx *spmx; @@ -237,7 +238,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, } static struct pinmux_ops sirfsoc_pinmux_ops = { - .enable = sirfsoc_pinmux_enable, + .set_mux = sirfsoc_pinmux_set_mux, .get_functions_count = sirfsoc_pinmux_get_funcs_count, .get_function_name = sirfsoc_pinmux_get_func_name, .get_function_groups = sirfsoc_pinmux_get_groups, diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index f72cc4e192bd..abdb05ac43dc 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -268,7 +268,7 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, return 0; } -static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, +static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function, unsigned group) { return spear_pinctrl_endisable(pctldev, function, group, true); @@ -338,7 +338,7 @@ static const struct pinmux_ops spear_pinmux_ops = { .get_functions_count = spear_pinctrl_get_funcs_count, .get_function_name = spear_pinctrl_get_func_name, .get_function_groups = spear_pinctrl_get_func_groups, - .enable = spear_pinctrl_enable, + .set_mux = spear_pinctrl_set_mux, .gpio_request_enable = gpio_request_enable, .gpio_disable_free = gpio_disable_free, }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 3df66e366c87..ef9d804e55de 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -393,9 +393,9 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev, spin_unlock_irqrestore(&pctl->lock, flags); } -static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) +static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) { struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct sunxi_pinctrl_group *g = pctl->groups + group; @@ -441,7 +441,7 @@ static const struct pinmux_ops sunxi_pmx_ops = { .get_functions_count = sunxi_pmx_get_funcs_cnt, .get_function_name = sunxi_pmx_get_func_name, .get_function_groups = sunxi_pmx_get_func_groups, - .enable = sunxi_pmx_enable, + .set_mux = sunxi_pmx_set_mux, .gpio_set_direction = sunxi_pmx_gpio_set_direction, }; diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index 8cea355f9a81..d055d63309e4 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -131,9 +131,9 @@ static int wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func, return 0; } -static int wmt_pmx_enable(struct pinctrl_dev *pctldev, - unsigned func_selector, - unsigned group_selector) +static int wmt_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned func_selector, + unsigned group_selector) { struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); u32 pinnum = data->pins[group_selector].number; @@ -168,7 +168,7 @@ static struct pinmux_ops wmt_pinmux_ops = { .get_functions_count = wmt_pmx_get_functions_count, .get_function_name = wmt_pmx_get_function_name, .get_function_groups = wmt_pmx_get_function_groups, - .enable = wmt_pmx_enable, + .set_mux = wmt_pmx_set_mux, .gpio_disable_free = wmt_pmx_gpio_disable_free, .gpio_set_direction = wmt_pmx_gpio_set_direction, }; -- cgit v1.2.3 From edad3b2a57082f6166b4f13445f70e8d3fc415fb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 3 Sep 2014 13:37:38 +0200 Subject: pinctrl: imx/mxs: move freescale drivers to subdir This moves all the Freescale-related drivers (i.MX and MXS) to its own subdirectory to clear the view. Cc: Alexander Shiyan Cc: Anson Huang Cc: Fabio Estevam Cc: Denis Carikli Cc: Markus Pargmann Cc: Greg Ungerer Cc: Sascha Hauer Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 110 +-- drivers/pinctrl/Makefile | 19 +- drivers/pinctrl/freescale/Kconfig | 108 +++ drivers/pinctrl/freescale/Makefile | 19 + drivers/pinctrl/freescale/pinctrl-imx.c | 630 +++++++++++++++ drivers/pinctrl/freescale/pinctrl-imx.h | 101 +++ drivers/pinctrl/freescale/pinctrl-imx1-core.c | 660 ++++++++++++++++ drivers/pinctrl/freescale/pinctrl-imx1.c | 279 +++++++ drivers/pinctrl/freescale/pinctrl-imx1.h | 73 ++ drivers/pinctrl/freescale/pinctrl-imx21.c | 342 ++++++++ drivers/pinctrl/freescale/pinctrl-imx23.c | 305 ++++++++ drivers/pinctrl/freescale/pinctrl-imx25.c | 351 +++++++++ drivers/pinctrl/freescale/pinctrl-imx27.c | 425 ++++++++++ drivers/pinctrl/freescale/pinctrl-imx28.c | 421 ++++++++++ drivers/pinctrl/freescale/pinctrl-imx35.c | 1041 +++++++++++++++++++++++++ drivers/pinctrl/freescale/pinctrl-imx50.c | 426 ++++++++++ drivers/pinctrl/freescale/pinctrl-imx51.c | 804 +++++++++++++++++++ drivers/pinctrl/freescale/pinctrl-imx53.c | 490 ++++++++++++ drivers/pinctrl/freescale/pinctrl-imx6dl.c | 497 ++++++++++++ drivers/pinctrl/freescale/pinctrl-imx6q.c | 502 ++++++++++++ drivers/pinctrl/freescale/pinctrl-imx6sl.c | 404 ++++++++++ drivers/pinctrl/freescale/pinctrl-imx6sx.c | 407 ++++++++++ drivers/pinctrl/freescale/pinctrl-mxs.c | 541 +++++++++++++ drivers/pinctrl/freescale/pinctrl-mxs.h | 91 +++ drivers/pinctrl/freescale/pinctrl-vf610.c | 338 ++++++++ drivers/pinctrl/pinctrl-imx.c | 630 --------------- drivers/pinctrl/pinctrl-imx.h | 101 --- drivers/pinctrl/pinctrl-imx1-core.c | 660 ---------------- drivers/pinctrl/pinctrl-imx1.c | 279 ------- drivers/pinctrl/pinctrl-imx1.h | 73 -- drivers/pinctrl/pinctrl-imx21.c | 342 -------- drivers/pinctrl/pinctrl-imx23.c | 305 -------- drivers/pinctrl/pinctrl-imx25.c | 351 --------- drivers/pinctrl/pinctrl-imx27.c | 425 ---------- drivers/pinctrl/pinctrl-imx28.c | 421 ---------- drivers/pinctrl/pinctrl-imx35.c | 1041 ------------------------- drivers/pinctrl/pinctrl-imx50.c | 426 ---------- drivers/pinctrl/pinctrl-imx51.c | 804 ------------------- drivers/pinctrl/pinctrl-imx53.c | 490 ------------ drivers/pinctrl/pinctrl-imx6dl.c | 497 ------------ drivers/pinctrl/pinctrl-imx6q.c | 502 ------------ drivers/pinctrl/pinctrl-imx6sl.c | 404 ---------- drivers/pinctrl/pinctrl-imx6sx.c | 407 ---------- drivers/pinctrl/pinctrl-mxs.c | 541 ------------- drivers/pinctrl/pinctrl-mxs.h | 91 --- drivers/pinctrl/pinctrl-vf610.c | 338 -------- 46 files changed, 9257 insertions(+), 9255 deletions(-) create mode 100644 drivers/pinctrl/freescale/Kconfig create mode 100644 drivers/pinctrl/freescale/Makefile create mode 100644 drivers/pinctrl/freescale/pinctrl-imx.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx.h create mode 100644 drivers/pinctrl/freescale/pinctrl-imx1-core.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx1.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx1.h create mode 100644 drivers/pinctrl/freescale/pinctrl-imx21.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx23.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx25.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx27.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx28.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx35.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx50.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx51.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx53.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6dl.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6q.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6sl.c create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6sx.c create mode 100644 drivers/pinctrl/freescale/pinctrl-mxs.c create mode 100644 drivers/pinctrl/freescale/pinctrl-mxs.h create mode 100644 drivers/pinctrl/freescale/pinctrl-vf610.c delete mode 100644 drivers/pinctrl/pinctrl-imx.c delete mode 100644 drivers/pinctrl/pinctrl-imx.h delete mode 100644 drivers/pinctrl/pinctrl-imx1-core.c delete mode 100644 drivers/pinctrl/pinctrl-imx1.c delete mode 100644 drivers/pinctrl/pinctrl-imx1.h delete mode 100644 drivers/pinctrl/pinctrl-imx21.c delete mode 100644 drivers/pinctrl/pinctrl-imx23.c delete mode 100644 drivers/pinctrl/pinctrl-imx25.c delete mode 100644 drivers/pinctrl/pinctrl-imx27.c delete mode 100644 drivers/pinctrl/pinctrl-imx28.c delete mode 100644 drivers/pinctrl/pinctrl-imx35.c delete mode 100644 drivers/pinctrl/pinctrl-imx50.c delete mode 100644 drivers/pinctrl/pinctrl-imx51.c delete mode 100644 drivers/pinctrl/pinctrl-imx53.c delete mode 100644 drivers/pinctrl/pinctrl-imx6dl.c delete mode 100644 drivers/pinctrl/pinctrl-imx6q.c delete mode 100644 drivers/pinctrl/pinctrl-imx6sl.c delete mode 100644 drivers/pinctrl/pinctrl-imx6sx.c delete mode 100644 drivers/pinctrl/pinctrl-mxs.c delete mode 100644 drivers/pinctrl/pinctrl-mxs.h delete mode 100644 drivers/pinctrl/pinctrl-vf610.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e1c5a87c80cd..64d06b52f98a 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -97,102 +97,6 @@ config PINCTRL_BCM281XX BCM28145, and BCM28155 SoCs. This driver requires the pinctrl framework. GPIO is provided by a separate GPIO driver. -config PINCTRL_IMX - bool - select PINMUX - select PINCONF - -config PINCTRL_IMX1_CORE - bool - select PINMUX - select PINCONF - -config PINCTRL_IMX1 - bool "IMX1 pinctrl driver" - depends on SOC_IMX1 - select PINCTRL_IMX1_CORE - help - Say Y here to enable the imx1 pinctrl driver - -config PINCTRL_IMX21 - bool "i.MX21 pinctrl driver" - depends on SOC_IMX21 - select PINCTRL_IMX1_CORE - help - Say Y here to enable the i.MX21 pinctrl driver - -config PINCTRL_IMX27 - bool "IMX27 pinctrl driver" - depends on SOC_IMX27 - select PINCTRL_IMX1_CORE - help - Say Y here to enable the imx27 pinctrl driver - - -config PINCTRL_IMX25 - bool "IMX25 pinctrl driver" - depends on OF - depends on SOC_IMX25 - select PINCTRL_IMX - help - Say Y here to enable the imx25 pinctrl driver - -config PINCTRL_IMX35 - bool "IMX35 pinctrl driver" - depends on SOC_IMX35 - select PINCTRL_IMX - help - Say Y here to enable the imx35 pinctrl driver - -config PINCTRL_IMX50 - bool "IMX50 pinctrl driver" - depends on SOC_IMX50 - select PINCTRL_IMX - help - Say Y here to enable the imx50 pinctrl driver - -config PINCTRL_IMX51 - bool "IMX51 pinctrl driver" - depends on SOC_IMX51 - select PINCTRL_IMX - help - Say Y here to enable the imx51 pinctrl driver - -config PINCTRL_IMX53 - bool "IMX53 pinctrl driver" - depends on SOC_IMX53 - select PINCTRL_IMX - help - Say Y here to enable the imx53 pinctrl driver - -config PINCTRL_IMX6Q - bool "IMX6Q/DL pinctrl driver" - depends on SOC_IMX6Q - select PINCTRL_IMX - help - Say Y here to enable the imx6q/dl pinctrl driver - -config PINCTRL_IMX6SL - bool "IMX6SL pinctrl driver" - depends on SOC_IMX6SL - select PINCTRL_IMX - help - Say Y here to enable the imx6sl pinctrl driver - -config PINCTRL_IMX6SX - bool "IMX6SX pinctrl driver" - depends on SOC_IMX6SX - select PINCTRL_IMX - help - Say Y here to enable the imx6sx pinctrl driver - -config PINCTRL_VF610 - bool "Freescale Vybrid VF610 pinctrl driver" - depends on SOC_VF610 - select PINCTRL_IMX - help - Say Y here to enable the Freescale Vybrid VF610 pinctrl driver - config PINCTRL_LANTIQ bool depends on LANTIQ @@ -204,19 +108,6 @@ config PINCTRL_FALCON depends on SOC_FALCON depends on PINCTRL_LANTIQ -config PINCTRL_MXS - bool - select PINMUX - select PINCONF - -config PINCTRL_IMX23 - bool - select PINCTRL_MXS - -config PINCTRL_IMX28 - bool - select PINCTRL_MXS - config PINCTRL_ROCKCHIP bool select PINMUX @@ -313,6 +204,7 @@ config PINCTRL_PALMAS TPS65913, TPS80036 etc. source "drivers/pinctrl/berlin/Kconfig" +source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/qcom/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0ffe1f608c67..51f52d32859e 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,24 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o -obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o -obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o -obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o -obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o -obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o -obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o -obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o -obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o -obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o -obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o -obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o -obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o -obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o -obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o -obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o -obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o -obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o @@ -53,9 +36,9 @@ obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o -obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_ARCH_BERLIN) += berlin/ +obj-y += freescale/ obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-y += nomadik/ obj-$(CONFIG_ARCH_QCOM) += qcom/ diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig new file mode 100644 index 000000000000..16aac38793fe --- /dev/null +++ b/drivers/pinctrl/freescale/Kconfig @@ -0,0 +1,108 @@ +config PINCTRL_IMX + bool + select PINMUX + select PINCONF + +config PINCTRL_IMX1_CORE + bool + select PINMUX + select PINCONF + +config PINCTRL_IMX1 + bool "IMX1 pinctrl driver" + depends on SOC_IMX1 + select PINCTRL_IMX1_CORE + help + Say Y here to enable the imx1 pinctrl driver + +config PINCTRL_IMX21 + bool "i.MX21 pinctrl driver" + depends on SOC_IMX21 + select PINCTRL_IMX1_CORE + help + Say Y here to enable the i.MX21 pinctrl driver + +config PINCTRL_IMX27 + bool "IMX27 pinctrl driver" + depends on SOC_IMX27 + select PINCTRL_IMX1_CORE + help + Say Y here to enable the imx27 pinctrl driver + + +config PINCTRL_IMX25 + bool "IMX25 pinctrl driver" + depends on OF + depends on SOC_IMX25 + select PINCTRL_IMX + help + Say Y here to enable the imx25 pinctrl driver + +config PINCTRL_IMX35 + bool "IMX35 pinctrl driver" + depends on SOC_IMX35 + select PINCTRL_IMX + help + Say Y here to enable the imx35 pinctrl driver + +config PINCTRL_IMX50 + bool "IMX50 pinctrl driver" + depends on SOC_IMX50 + select PINCTRL_IMX + help + Say Y here to enable the imx50 pinctrl driver + +config PINCTRL_IMX51 + bool "IMX51 pinctrl driver" + depends on SOC_IMX51 + select PINCTRL_IMX + help + Say Y here to enable the imx51 pinctrl driver + +config PINCTRL_IMX53 + bool "IMX53 pinctrl driver" + depends on SOC_IMX53 + select PINCTRL_IMX + help + Say Y here to enable the imx53 pinctrl driver + +config PINCTRL_IMX6Q + bool "IMX6Q/DL pinctrl driver" + depends on SOC_IMX6Q + select PINCTRL_IMX + help + Say Y here to enable the imx6q/dl pinctrl driver + +config PINCTRL_IMX6SL + bool "IMX6SL pinctrl driver" + depends on SOC_IMX6SL + select PINCTRL_IMX + help + Say Y here to enable the imx6sl pinctrl driver + +config PINCTRL_IMX6SX + bool "IMX6SX pinctrl driver" + depends on SOC_IMX6SX + select PINCTRL_IMX + help + Say Y here to enable the imx6sx pinctrl driver + +config PINCTRL_VF610 + bool "Freescale Vybrid VF610 pinctrl driver" + depends on SOC_VF610 + select PINCTRL_IMX + help + Say Y here to enable the Freescale Vybrid VF610 pinctrl driver + +config PINCTRL_MXS + bool + select PINMUX + select PINCONF + +config PINCTRL_IMX23 + bool + select PINCTRL_MXS + +config PINCTRL_IMX28 + bool + select PINCTRL_MXS diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile new file mode 100644 index 000000000000..bba73c22f043 --- /dev/null +++ b/drivers/pinctrl/freescale/Makefile @@ -0,0 +1,19 @@ +# Freescale pin control drivers +obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o +obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o +obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o +obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o +obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o +obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o +obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o +obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o +obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o +obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o +obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o +obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o +obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o +obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o +obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o +obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o +obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o +obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c new file mode 100644 index 000000000000..e89268c09e4c --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -0,0 +1,630 @@ +/* + * Core driver for the imx pin controller + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + * + * Author: Dong Aisheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "pinctrl-imx.h" + +/* The bits in CONFIG cell defined in binding doc*/ +#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ +#define IMX_PAD_SION 0x40000000 /* set SION */ + +/** + * @dev: a pointer back to containing device + * @base: the offset to the controller in virtual memory + */ +struct imx_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *base; + const struct imx_pinctrl_soc_info *info; +}; + +static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( + const struct imx_pinctrl_soc_info *info, + const char *name) +{ + const struct imx_pin_group *grp = NULL; + int i; + + for (i = 0; i < info->ngroups; i++) { + if (!strcmp(info->groups[i].name, name)) { + grp = &info->groups[i]; + break; + } + } + + return grp; +} + +static int imx_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + return info->ngroups; +} + +static const char *imx_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + return info->groups[selector].name; +} + +static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned **pins, + unsigned *npins) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pin_ids; + *npins = info->groups[selector].npins; + + return 0; +} + +static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned offset) +{ + seq_printf(s, "%s", dev_name(pctldev->dev)); +} + +static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_group *grp; + struct pinctrl_map *new_map; + struct device_node *parent; + int map_num = 1; + int i, j; + + /* + * first find the group of this node and check if we need create + * config maps for pins + */ + grp = imx_pinctrl_find_group_by_name(info, np->name); + if (!grp) { + dev_err(info->dev, "unable to find group for node %s\n", + np->name); + return -EINVAL; + } + + for (i = 0; i < grp->npins; i++) { + if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) + map_num++; + } + + new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + *map = new_map; + *num_maps = map_num; + + /* create mux map */ + parent = of_get_parent(np); + if (!parent) { + kfree(new_map); + return -EINVAL; + } + new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[0].data.mux.function = parent->name; + new_map[0].data.mux.group = np->name; + of_node_put(parent); + + /* create config map */ + new_map++; + for (i = j = 0; i < grp->npins; i++) { + if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) { + new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[j].data.configs.group_or_pin = + pin_get_name(pctldev, grp->pins[i].pin); + new_map[j].data.configs.configs = &grp->pins[i].config; + new_map[j].data.configs.num_configs = 1; + j++; + } + } + + dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", + (*map)->data.mux.function, (*map)->data.mux.group, map_num); + + return 0; +} + +static void imx_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops imx_pctrl_ops = { + .get_groups_count = imx_get_groups_count, + .get_group_name = imx_get_group_name, + .get_group_pins = imx_get_group_pins, + .pin_dbg_show = imx_pin_dbg_show, + .dt_node_to_map = imx_dt_node_to_map, + .dt_free_map = imx_dt_free_map, + +}; + +static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg; + unsigned int npins, pin_id; + int i; + struct imx_pin_group *grp; + + /* + * Configure the mux mode for each pin in the group for a specific + * function. + */ + grp = &info->groups[group]; + npins = grp->npins; + + dev_dbg(ipctl->dev, "enable function %s group %s\n", + info->functions[selector].name, grp->name); + + for (i = 0; i < npins; i++) { + struct imx_pin *pin = &grp->pins[i]; + pin_id = pin->pin; + pin_reg = &info->pin_regs[pin_id]; + + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) { + dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", + info->pins[pin_id].name); + return -EINVAL; + } + + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + reg = readl(ipctl->base + pin_reg->mux_reg); + reg &= ~(0x7 << 20); + reg |= (pin->mux_mode << 20); + writel(reg, ipctl->base + pin_reg->mux_reg); + } else { + writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); + } + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, pin->mux_mode); + + /* + * If the select input value begins with 0xff, it's a quirky + * select input and the value should be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the select + * input for some pin is not implemented in the select + * input register but in some general purpose register. + * We encode the select input value, width and shift of + * the bit field into input_val cell of pin function ID + * in device tree, and then decode them here for setting + * up the select input bits in general purpose register. + */ + if (pin->input_val >> 24 == 0xff) { + u32 val = pin->input_val; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some IOMUXC general + * purpose register, not regular select input register. + */ + val = readl(ipctl->base + pin->input_reg); + val &= ~mask; + val |= select << shift; + writel(val, ipctl->base + pin->input_reg); + } else if (pin->input_reg) { + /* + * Regular select input register can never be at offset + * 0, and we only print register value for regular case. + */ + writel(pin->input_val, ipctl->base + pin->input_reg); + dev_dbg(ipctl->dev, + "==>select_input: offset 0x%x val 0x%x\n", + pin->input_reg, pin->input_val); + } + } + + return 0; +} + +static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + return info->nfunctions; +} + +static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + return info->functions[selector].name; +} + +static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + *groups = info->functions[selector].groups; + *num_groups = info->functions[selector].num_groups; + + return 0; +} + +static const struct pinmux_ops imx_pmx_ops = { + .get_functions_count = imx_pmx_get_funcs_count, + .get_function_name = imx_pmx_get_func_name, + .get_function_groups = imx_pmx_get_groups, + .set_mux = imx_pmx_set, +}; + +static int imx_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; + + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { + dev_err(info->dev, "Pin(%s) does not support config function\n", + info->pins[pin_id].name); + return -EINVAL; + } + + *config = readl(ipctl->base + pin_reg->conf_reg); + + if (info->flags & SHARE_MUX_CONF_REG) + *config &= 0xffff; + + return 0; +} + +static int imx_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; + int i; + + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { + dev_err(info->dev, "Pin(%s) does not support config function\n", + info->pins[pin_id].name); + return -EINVAL; + } + + dev_dbg(ipctl->dev, "pinconf set pin %s\n", + info->pins[pin_id].name); + + for (i = 0; i < num_configs; i++) { + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + reg = readl(ipctl->base + pin_reg->conf_reg); + reg &= ~0xffff; + reg |= configs[i]; + writel(reg, ipctl->base + pin_reg->conf_reg); + } else { + writel(configs[i], ipctl->base + pin_reg->conf_reg); + } + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", + pin_reg->conf_reg, configs[i]); + } /* for each config */ + + return 0; +} + +static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin_id) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; + unsigned long config; + + if (!pin_reg || !pin_reg->conf_reg) { + seq_printf(s, "N/A"); + return; + } + + config = readl(ipctl->base + pin_reg->conf_reg); + seq_printf(s, "0x%lx", config); +} + +static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned group) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin_group *grp; + unsigned long config; + const char *name; + int i, ret; + + if (group > info->ngroups) + return; + + seq_printf(s, "\n"); + grp = &info->groups[group]; + for (i = 0; i < grp->npins; i++) { + struct imx_pin *pin = &grp->pins[i]; + name = pin_get_name(pctldev, pin->pin); + ret = imx_pinconf_get(pctldev, pin->pin, &config); + if (ret) + return; + seq_printf(s, "%s: 0x%lx", name, config); + } +} + +static const struct pinconf_ops imx_pinconf_ops = { + .pin_config_get = imx_pinconf_get, + .pin_config_set = imx_pinconf_set, + .pin_config_dbg_show = imx_pinconf_dbg_show, + .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, +}; + +static struct pinctrl_desc imx_pinctrl_desc = { + .pctlops = &imx_pctrl_ops, + .pmxops = &imx_pmx_ops, + .confops = &imx_pinconf_ops, + .owner = THIS_MODULE, +}; + +/* + * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and + * 1 u32 CONFIG, so 24 types in total for each pin. + */ +#define FSL_PIN_SIZE 24 +#define SHARE_FSL_PIN_SIZE 20 + +static int imx_pinctrl_parse_groups(struct device_node *np, + struct imx_pin_group *grp, + struct imx_pinctrl_soc_info *info, + u32 index) +{ + int size, pin_size; + const __be32 *list; + int i; + u32 config; + + dev_dbg(info->dev, "group(%d): %s\n", index, np->name); + + if (info->flags & SHARE_MUX_CONF_REG) + pin_size = SHARE_FSL_PIN_SIZE; + else + pin_size = FSL_PIN_SIZE; + /* Initialise group */ + grp->name = np->name; + + /* + * the binding format is fsl,pins = , + * do sanity check and calculate pins number + */ + list = of_get_property(np, "fsl,pins", &size); + if (!list) { + dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); + return -EINVAL; + } + + /* we do not check return since it's safe node passed down */ + if (!size || size % pin_size) { + dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); + return -EINVAL; + } + + grp->npins = size / pin_size; + grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin), + GFP_KERNEL); + grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), + GFP_KERNEL); + if (!grp->pins || ! grp->pin_ids) + return -ENOMEM; + + for (i = 0; i < grp->npins; i++) { + u32 mux_reg = be32_to_cpu(*list++); + u32 conf_reg; + unsigned int pin_id; + struct imx_pin_reg *pin_reg; + struct imx_pin *pin = &grp->pins[i]; + + if (info->flags & SHARE_MUX_CONF_REG) + conf_reg = mux_reg; + else + conf_reg = be32_to_cpu(*list++); + + pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + pin_reg = &info->pin_regs[pin_id]; + pin->pin = pin_id; + grp->pin_ids[i] = pin_id; + pin_reg->mux_reg = mux_reg; + pin_reg->conf_reg = conf_reg; + pin->input_reg = be32_to_cpu(*list++); + pin->mux_mode = be32_to_cpu(*list++); + pin->input_val = be32_to_cpu(*list++); + + /* SION bit is in mux register */ + config = be32_to_cpu(*list++); + if (config & IMX_PAD_SION) + pin->mux_mode |= IOMUXC_CONFIG_SION; + pin->config = config & ~IMX_PAD_SION; + + dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, + pin->mux_mode, pin->config); + } + + return 0; +} + +static int imx_pinctrl_parse_functions(struct device_node *np, + struct imx_pinctrl_soc_info *info, + u32 index) +{ + struct device_node *child; + struct imx_pmx_func *func; + struct imx_pin_group *grp; + static u32 grp_index; + u32 i = 0; + + dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); + + func = &info->functions[index]; + + /* Initialise function */ + func->name = np->name; + func->num_groups = of_get_child_count(np); + if (func->num_groups == 0) { + dev_err(info->dev, "no groups defined in %s\n", np->full_name); + return -EINVAL; + } + func->groups = devm_kzalloc(info->dev, + func->num_groups * sizeof(char *), GFP_KERNEL); + + for_each_child_of_node(np, child) { + func->groups[i] = child->name; + grp = &info->groups[grp_index++]; + imx_pinctrl_parse_groups(child, grp, info, i++); + } + + return 0; +} + +static int imx_pinctrl_probe_dt(struct platform_device *pdev, + struct imx_pinctrl_soc_info *info) +{ + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + u32 nfuncs = 0; + u32 i = 0; + + if (!np) + return -ENODEV; + + nfuncs = of_get_child_count(np); + if (nfuncs <= 0) { + dev_err(&pdev->dev, "no functions defined\n"); + return -EINVAL; + } + + info->nfunctions = nfuncs; + info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), + GFP_KERNEL); + if (!info->functions) + return -ENOMEM; + + info->ngroups = 0; + for_each_child_of_node(np, child) + info->ngroups += of_get_child_count(child); + info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), + GFP_KERNEL); + if (!info->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) + imx_pinctrl_parse_functions(child, info, i++); + + return 0; +} + +int imx_pinctrl_probe(struct platform_device *pdev, + struct imx_pinctrl_soc_info *info) +{ + struct imx_pinctrl *ipctl; + struct resource *res; + int ret; + + if (!info || !info->pins || !info->npins) { + dev_err(&pdev->dev, "wrong pinctrl info\n"); + return -EINVAL; + } + info->dev = &pdev->dev; + + /* Create state holders etc for this driver */ + ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); + if (!ipctl) + return -ENOMEM; + + info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) * + info->npins, GFP_KERNEL); + if (!info->pin_regs) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ipctl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ipctl->base)) + return PTR_ERR(ipctl->base); + + imx_pinctrl_desc.name = dev_name(&pdev->dev); + imx_pinctrl_desc.pins = info->pins; + imx_pinctrl_desc.npins = info->npins; + + ret = imx_pinctrl_probe_dt(pdev, info); + if (ret) { + dev_err(&pdev->dev, "fail to probe dt properties\n"); + return ret; + } + + ipctl->info = info; + ipctl->dev = info->dev; + platform_set_drvdata(pdev, ipctl); + ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); + if (!ipctl->pctl) { + dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); + return -EINVAL; + } + + dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); + + return 0; +} + +int imx_pinctrl_remove(struct platform_device *pdev) +{ + struct imx_pinctrl *ipctl = platform_get_drvdata(pdev); + + pinctrl_unregister(ipctl->pctl); + + return 0; +} diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h new file mode 100644 index 000000000000..db408b057000 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -0,0 +1,101 @@ +/* + * IMX pinmux core definitions + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + * + * Author: Dong Aisheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DRIVERS_PINCTRL_IMX_H +#define __DRIVERS_PINCTRL_IMX_H + +struct platform_device; + +/** + * struct imx_pin_group - describes a single i.MX pin + * @pin: the pin_id of this pin + * @mux_mode: the mux mode for this pin. + * @input_reg: the select input register offset for this pin if any + * 0 if no select input setting needed. + * @input_val: the select input value for this pin. + * @configs: the config for this pin. + */ +struct imx_pin { + unsigned int pin; + unsigned int mux_mode; + u16 input_reg; + unsigned int input_val; + unsigned long config; +}; + +/** + * struct imx_pin_group - describes an IMX pin group + * @name: the name of this specific pin group + * @npins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array + * @pins: array of pins + */ +struct imx_pin_group { + const char *name; + unsigned npins; + unsigned int *pin_ids; + struct imx_pin *pins; +}; + +/** + * struct imx_pmx_func - describes IMX pinmux functions + * @name: the name of this specific function + * @groups: corresponding pin groups + * @num_groups: the number of groups + */ +struct imx_pmx_func { + const char *name; + const char **groups; + unsigned num_groups; +}; + +/** + * struct imx_pin_reg - describe a pin reg map + * @mux_reg: mux register offset + * @conf_reg: config register offset + */ +struct imx_pin_reg { + u16 mux_reg; + u16 conf_reg; +}; + +struct imx_pinctrl_soc_info { + struct device *dev; + const struct pinctrl_pin_desc *pins; + unsigned int npins; + struct imx_pin_reg *pin_regs; + struct imx_pin_group *groups; + unsigned int ngroups; + struct imx_pmx_func *functions; + unsigned int nfunctions; + unsigned int flags; +}; + +#define ZERO_OFFSET_VALID 0x1 +#define SHARE_MUX_CONF_REG 0x2 + +#define NO_MUX 0x0 +#define NO_PAD 0x0 + +#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) + +#define PAD_CTL_MASK(len) ((1 << len) - 1) +#define IMX_MUX_MASK 0x7 +#define IOMUXC_CONFIG_SION (0x1 << 4) + +int imx_pinctrl_probe(struct platform_device *pdev, + struct imx_pinctrl_soc_info *info); +int imx_pinctrl_remove(struct platform_device *pdev); +#endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c new file mode 100644 index 000000000000..5ac59fbb2440 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -0,0 +1,660 @@ +/* + * Core driver for the imx pin controller in imx1/21/27 + * + * Copyright (C) 2013 Pengutronix + * Author: Markus Pargmann + * + * Based on pinctrl-imx.c: + * Author: Dong Aisheng + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "pinctrl-imx1.h" + +struct imx1_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *base; + const struct imx1_pinctrl_soc_info *info; +}; + +/* + * MX1 register offsets + */ + +#define MX1_DDIR 0x00 +#define MX1_OCR 0x04 +#define MX1_ICONFA 0x0c +#define MX1_ICONFB 0x14 +#define MX1_GIUS 0x20 +#define MX1_GPR 0x38 +#define MX1_PUEN 0x40 + +#define MX1_PORT_STRIDE 0x100 + + +/* + * MUX_ID format defines + */ +#define MX1_MUX_FUNCTION(val) (BIT(0) & val) +#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1) +#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2) +#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4) +#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8) +#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10) + + +/* + * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX + * control register are seperated into function, output configuration, input + * configuration A, input configuration B, GPIO in use and data direction. + * + * Those controls that are represented by 1 bit have a direct mapping between + * bit position and pin id. If they are represented by 2 bit, the lower 16 pins + * are in the first register and the upper 16 pins in the second (next) + * register. pin_id is stored in bit (pin_id%16)*2 and the bit above. + */ + +/* + * Calculates the register offset from a pin_id + */ +static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id) +{ + unsigned int port = pin_id / 32; + return ipctl->base + port * MX1_PORT_STRIDE; +} + +/* + * Write to a register with 2 bits per pin. The function will automatically + * use the next register if the pin is managed in the second register. + */ +static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, + u32 value, u32 reg_offset) +{ + void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; + int offset = (pin_id % 16) * 2; /* offset, regardless of register used */ + int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */ + u32 old_val; + u32 new_val; + + /* Use the next register if the pin's port pin number is >=16 */ + if (pin_id % 32 >= 16) + reg += 0x04; + + dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", + reg, offset, value); + + /* Get current state of pins */ + old_val = readl(reg); + old_val &= mask; + + new_val = value & 0x3; /* Make sure value is really 2 bit */ + new_val <<= offset; + new_val |= old_val;/* Set new state for pin_id */ + + writel(new_val, reg); +} + +static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, + u32 value, u32 reg_offset) +{ + void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; + int offset = pin_id % 32; + int mask = ~BIT_MASK(offset); + u32 old_val; + u32 new_val; + + /* Get current state of pins */ + old_val = readl(reg); + old_val &= mask; + + new_val = value & 0x1; /* Make sure value is really 1 bit */ + new_val <<= offset; + new_val |= old_val;/* Set new state for pin_id */ + + writel(new_val, reg); +} + +static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, + u32 reg_offset) +{ + void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; + int offset = (pin_id % 16) * 2; + + /* Use the next register if the pin's port pin number is >=16 */ + if (pin_id % 32 >= 16) + reg += 0x04; + + return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset; +} + +static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, + u32 reg_offset) +{ + void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; + int offset = pin_id % 32; + + return !!(readl(reg) & BIT(offset)); +} + +static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name( + const struct imx1_pinctrl_soc_info *info, + const char *name) +{ + const struct imx1_pin_group *grp = NULL; + int i; + + for (i = 0; i < info->ngroups; i++) { + if (!strcmp(info->groups[i].name, name)) { + grp = &info->groups[i]; + break; + } + } + + return grp; +} + +static int imx1_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + return info->ngroups; +} + +static const char *imx1_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + return info->groups[selector].name; +} + +static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned int **pins, + unsigned *npins) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pin_ids; + *npins = info->groups[selector].npins; + + return 0; +} + +static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned offset) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + + seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d", + imx1_read_bit(ipctl, offset, MX1_GIUS), + imx1_read_bit(ipctl, offset, MX1_GPR), + imx1_read_bit(ipctl, offset, MX1_DDIR), + imx1_read_2bit(ipctl, offset, MX1_OCR), + imx1_read_2bit(ipctl, offset, MX1_ICONFA), + imx1_read_2bit(ipctl, offset, MX1_ICONFB)); +} + +static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + const struct imx1_pin_group *grp; + struct pinctrl_map *new_map; + struct device_node *parent; + int map_num = 1; + int i, j; + + /* + * first find the group of this node and check if we need create + * config maps for pins + */ + grp = imx1_pinctrl_find_group_by_name(info, np->name); + if (!grp) { + dev_err(info->dev, "unable to find group for node %s\n", + np->name); + return -EINVAL; + } + + for (i = 0; i < grp->npins; i++) + map_num++; + + new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + *map = new_map; + *num_maps = map_num; + + /* create mux map */ + parent = of_get_parent(np); + if (!parent) { + kfree(new_map); + return -EINVAL; + } + new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[0].data.mux.function = parent->name; + new_map[0].data.mux.group = np->name; + of_node_put(parent); + + /* create config map */ + new_map++; + for (i = j = 0; i < grp->npins; i++) { + new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[j].data.configs.group_or_pin = + pin_get_name(pctldev, grp->pins[i].pin_id); + new_map[j].data.configs.configs = &grp->pins[i].config; + new_map[j].data.configs.num_configs = 1; + j++; + } + + dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", + (*map)->data.mux.function, (*map)->data.mux.group, map_num); + + return 0; +} + +static void imx1_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops imx1_pctrl_ops = { + .get_groups_count = imx1_get_groups_count, + .get_group_name = imx1_get_group_name, + .get_group_pins = imx1_get_group_pins, + .pin_dbg_show = imx1_pin_dbg_show, + .dt_node_to_map = imx1_dt_node_to_map, + .dt_free_map = imx1_dt_free_map, + +}; + +static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + const struct imx1_pin *pins; + unsigned int npins; + int i; + + /* + * Configure the mux mode for each pin in the group for a specific + * function. + */ + pins = info->groups[group].pins; + npins = info->groups[group].npins; + + WARN_ON(!pins || !npins); + + dev_dbg(ipctl->dev, "enable function %s group %s\n", + info->functions[selector].name, info->groups[group].name); + + for (i = 0; i < npins; i++) { + unsigned int mux = pins[i].mux_id; + unsigned int pin_id = pins[i].pin_id; + unsigned int afunction = MX1_MUX_FUNCTION(mux); + unsigned int gpio_in_use = MX1_MUX_GPIO(mux); + unsigned int direction = MX1_MUX_DIR(mux); + unsigned int gpio_oconf = MX1_MUX_OCONF(mux); + unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux); + unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux); + + dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n", + __func__, pin_id, afunction, gpio_in_use, + direction, gpio_oconf, gpio_iconfa, + gpio_iconfb); + + imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS); + imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR); + + if (gpio_in_use) { + imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR); + imx1_write_2bit(ipctl, pin_id, gpio_iconfa, + MX1_ICONFA); + imx1_write_2bit(ipctl, pin_id, gpio_iconfb, + MX1_ICONFB); + } else { + imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR); + } + } + + return 0; +} + +static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + return info->nfunctions; +} + +static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + return info->functions[selector].name; +} + +static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + *groups = info->functions[selector].groups; + *num_groups = info->functions[selector].num_groups; + + return 0; +} + +static const struct pinmux_ops imx1_pmx_ops = { + .get_functions_count = imx1_pmx_get_funcs_count, + .get_function_name = imx1_pmx_get_func_name, + .get_function_groups = imx1_pmx_get_groups, + .set_mux = imx1_pmx_set, +}; + +static int imx1_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + + *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN); + + return 0; +} + +static int imx1_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + int i; + + for (i = 0; i != num_configs; ++i) { + imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN); + + dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n", + info->pins[pin_id].name); + } + + return 0; +} + +static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin_id) +{ + unsigned long config; + + imx1_pinconf_get(pctldev, pin_id, &config); + seq_printf(s, "0x%lx", config); +} + +static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned group) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + struct imx1_pin_group *grp; + unsigned long config; + const char *name; + int i, ret; + + if (group > info->ngroups) + return; + + seq_puts(s, "\n"); + grp = &info->groups[group]; + for (i = 0; i < grp->npins; i++) { + name = pin_get_name(pctldev, grp->pins[i].pin_id); + ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config); + if (ret) + return; + seq_printf(s, "%s: 0x%lx", name, config); + } +} + +static const struct pinconf_ops imx1_pinconf_ops = { + .pin_config_get = imx1_pinconf_get, + .pin_config_set = imx1_pinconf_set, + .pin_config_dbg_show = imx1_pinconf_dbg_show, + .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show, +}; + +static struct pinctrl_desc imx1_pinctrl_desc = { + .pctlops = &imx1_pctrl_ops, + .pmxops = &imx1_pmx_ops, + .confops = &imx1_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int imx1_pinctrl_parse_groups(struct device_node *np, + struct imx1_pin_group *grp, + struct imx1_pinctrl_soc_info *info, + u32 index) +{ + int size; + const __be32 *list; + int i; + + dev_dbg(info->dev, "group(%d): %s\n", index, np->name); + + /* Initialise group */ + grp->name = np->name; + + /* + * the binding format is fsl,pins = + */ + list = of_get_property(np, "fsl,pins", &size); + /* we do not check return since it's safe node passed down */ + if (!size || size % 12) { + dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n", + np->name); + return -EINVAL; + } + + grp->npins = size / 12; + grp->pins = devm_kzalloc(info->dev, + grp->npins * sizeof(struct imx1_pin), GFP_KERNEL); + grp->pin_ids = devm_kzalloc(info->dev, + grp->npins * sizeof(unsigned int), GFP_KERNEL); + + if (!grp->pins || !grp->pin_ids) + return -ENOMEM; + + for (i = 0; i < grp->npins; i++) { + grp->pins[i].pin_id = be32_to_cpu(*list++); + grp->pins[i].mux_id = be32_to_cpu(*list++); + grp->pins[i].config = be32_to_cpu(*list++); + + grp->pin_ids[i] = grp->pins[i].pin_id; + } + + return 0; +} + +static int imx1_pinctrl_parse_functions(struct device_node *np, + struct imx1_pinctrl_soc_info *info, + u32 index) +{ + struct device_node *child; + struct imx1_pmx_func *func; + struct imx1_pin_group *grp; + int ret; + static u32 grp_index; + u32 i = 0; + + dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); + + func = &info->functions[index]; + + /* Initialise function */ + func->name = np->name; + func->num_groups = of_get_child_count(np); + if (func->num_groups == 0) + return -EINVAL; + + func->groups = devm_kzalloc(info->dev, + func->num_groups * sizeof(char *), GFP_KERNEL); + + if (!func->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) { + func->groups[i] = child->name; + grp = &info->groups[grp_index++]; + ret = imx1_pinctrl_parse_groups(child, grp, info, i++); + if (ret == -ENOMEM) + return ret; + } + + return 0; +} + +static int imx1_pinctrl_parse_dt(struct platform_device *pdev, + struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info) +{ + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + int ret; + u32 nfuncs = 0; + u32 ngroups = 0; + u32 ifunc = 0; + + if (!np) + return -ENODEV; + + for_each_child_of_node(np, child) { + ++nfuncs; + ngroups += of_get_child_count(child); + } + + if (!nfuncs) { + dev_err(&pdev->dev, "No pin functions defined\n"); + return -EINVAL; + } + + info->nfunctions = nfuncs; + info->functions = devm_kzalloc(&pdev->dev, + nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL); + + info->ngroups = ngroups; + info->groups = devm_kzalloc(&pdev->dev, + ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL); + + + if (!info->functions || !info->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) { + ret = imx1_pinctrl_parse_functions(child, info, ifunc++); + if (ret == -ENOMEM) + return -ENOMEM; + } + + return 0; +} + +int imx1_pinctrl_core_probe(struct platform_device *pdev, + struct imx1_pinctrl_soc_info *info) +{ + struct imx1_pinctrl *ipctl; + struct resource *res; + struct pinctrl_desc *pctl_desc; + int ret; + + if (!info || !info->pins || !info->npins) { + dev_err(&pdev->dev, "wrong pinctrl info\n"); + return -EINVAL; + } + info->dev = &pdev->dev; + + /* Create state holders etc for this driver */ + ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); + if (!ipctl) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOENT; + + ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ipctl->base) + return -ENOMEM; + + pctl_desc = &imx1_pinctrl_desc; + pctl_desc->name = dev_name(&pdev->dev); + pctl_desc->pins = info->pins; + pctl_desc->npins = info->npins; + + ret = imx1_pinctrl_parse_dt(pdev, ipctl, info); + if (ret) { + dev_err(&pdev->dev, "fail to probe dt properties\n"); + return ret; + } + + ipctl->info = info; + ipctl->dev = info->dev; + platform_set_drvdata(pdev, ipctl); + ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl); + if (!ipctl->pctl) { + dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); + return -EINVAL; + } + + ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (ret) { + pinctrl_unregister(ipctl->pctl); + dev_err(&pdev->dev, "Failed to populate subdevices\n"); + return ret; + } + + dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); + + return 0; +} + +int imx1_pinctrl_core_remove(struct platform_device *pdev) +{ + struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev); + + pinctrl_unregister(ipctl->pctl); + + return 0; +} diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.c b/drivers/pinctrl/freescale/pinctrl-imx1.c new file mode 100644 index 000000000000..533a6e519648 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx1.c @@ -0,0 +1,279 @@ +/* + * i.MX1 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2014 Alexander Shiyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +#include "pinctrl-imx1.h" + +#define PAD_ID(port, pin) ((port) * 32 + (pin)) +#define PA 0 +#define PB 1 +#define PC 2 +#define PD 3 + +enum imx1_pads { + MX1_PAD_A24 = PAD_ID(PA, 0), + MX1_PAD_TIN = PAD_ID(PA, 1), + MX1_PAD_PWMO = PAD_ID(PA, 2), + MX1_PAD_CSI_MCLK = PAD_ID(PA, 3), + MX1_PAD_CSI_D0 = PAD_ID(PA, 4), + MX1_PAD_CSI_D1 = PAD_ID(PA, 5), + MX1_PAD_CSI_D2 = PAD_ID(PA, 6), + MX1_PAD_CSI_D3 = PAD_ID(PA, 7), + MX1_PAD_CSI_D4 = PAD_ID(PA, 8), + MX1_PAD_CSI_D5 = PAD_ID(PA, 9), + MX1_PAD_CSI_D6 = PAD_ID(PA, 10), + MX1_PAD_CSI_D7 = PAD_ID(PA, 11), + MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12), + MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13), + MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14), + MX1_PAD_I2C_SDA = PAD_ID(PA, 15), + MX1_PAD_I2C_SCL = PAD_ID(PA, 16), + MX1_PAD_DTACK = PAD_ID(PA, 17), + MX1_PAD_BCLK = PAD_ID(PA, 18), + MX1_PAD_LBA = PAD_ID(PA, 19), + MX1_PAD_ECB = PAD_ID(PA, 20), + MX1_PAD_A0 = PAD_ID(PA, 21), + MX1_PAD_CS4 = PAD_ID(PA, 22), + MX1_PAD_CS5 = PAD_ID(PA, 23), + MX1_PAD_A16 = PAD_ID(PA, 24), + MX1_PAD_A17 = PAD_ID(PA, 25), + MX1_PAD_A18 = PAD_ID(PA, 26), + MX1_PAD_A19 = PAD_ID(PA, 27), + MX1_PAD_A20 = PAD_ID(PA, 28), + MX1_PAD_A21 = PAD_ID(PA, 29), + MX1_PAD_A22 = PAD_ID(PA, 30), + MX1_PAD_A23 = PAD_ID(PA, 31), + MX1_PAD_SD_DAT0 = PAD_ID(PB, 8), + MX1_PAD_SD_DAT1 = PAD_ID(PB, 9), + MX1_PAD_SD_DAT2 = PAD_ID(PB, 10), + MX1_PAD_SD_DAT3 = PAD_ID(PB, 11), + MX1_PAD_SD_SCLK = PAD_ID(PB, 12), + MX1_PAD_SD_CMD = PAD_ID(PB, 13), + MX1_PAD_SIM_SVEN = PAD_ID(PB, 14), + MX1_PAD_SIM_PD = PAD_ID(PB, 15), + MX1_PAD_SIM_TX = PAD_ID(PB, 16), + MX1_PAD_SIM_RX = PAD_ID(PB, 17), + MX1_PAD_SIM_RST = PAD_ID(PB, 18), + MX1_PAD_SIM_CLK = PAD_ID(PB, 19), + MX1_PAD_USBD_AFE = PAD_ID(PB, 20), + MX1_PAD_USBD_OE = PAD_ID(PB, 21), + MX1_PAD_USBD_RCV = PAD_ID(PB, 22), + MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23), + MX1_PAD_USBD_VP = PAD_ID(PB, 24), + MX1_PAD_USBD_VM = PAD_ID(PB, 25), + MX1_PAD_USBD_VPO = PAD_ID(PB, 26), + MX1_PAD_USBD_VMO = PAD_ID(PB, 27), + MX1_PAD_UART2_CTS = PAD_ID(PB, 28), + MX1_PAD_UART2_RTS = PAD_ID(PB, 29), + MX1_PAD_UART2_TXD = PAD_ID(PB, 30), + MX1_PAD_UART2_RXD = PAD_ID(PB, 31), + MX1_PAD_SSI_RXFS = PAD_ID(PC, 3), + MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4), + MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5), + MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6), + MX1_PAD_SSI_TXFS = PAD_ID(PC, 7), + MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8), + MX1_PAD_UART1_CTS = PAD_ID(PC, 9), + MX1_PAD_UART1_RTS = PAD_ID(PC, 10), + MX1_PAD_UART1_TXD = PAD_ID(PC, 11), + MX1_PAD_UART1_RXD = PAD_ID(PC, 12), + MX1_PAD_SPI1_RDY = PAD_ID(PC, 13), + MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14), + MX1_PAD_SPI1_SS = PAD_ID(PC, 15), + MX1_PAD_SPI1_MISO = PAD_ID(PC, 16), + MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17), + MX1_PAD_BT13 = PAD_ID(PC, 19), + MX1_PAD_BT12 = PAD_ID(PC, 20), + MX1_PAD_BT11 = PAD_ID(PC, 21), + MX1_PAD_BT10 = PAD_ID(PC, 22), + MX1_PAD_BT9 = PAD_ID(PC, 23), + MX1_PAD_BT8 = PAD_ID(PC, 24), + MX1_PAD_BT7 = PAD_ID(PC, 25), + MX1_PAD_BT6 = PAD_ID(PC, 26), + MX1_PAD_BT5 = PAD_ID(PC, 27), + MX1_PAD_BT4 = PAD_ID(PC, 28), + MX1_PAD_BT3 = PAD_ID(PC, 29), + MX1_PAD_BT2 = PAD_ID(PC, 30), + MX1_PAD_BT1 = PAD_ID(PC, 31), + MX1_PAD_LSCLK = PAD_ID(PD, 6), + MX1_PAD_REV = PAD_ID(PD, 7), + MX1_PAD_CLS = PAD_ID(PD, 8), + MX1_PAD_PS = PAD_ID(PD, 9), + MX1_PAD_SPL_SPR = PAD_ID(PD, 10), + MX1_PAD_CONTRAST = PAD_ID(PD, 11), + MX1_PAD_ACD_OE = PAD_ID(PD, 12), + MX1_PAD_LP_HSYNC = PAD_ID(PD, 13), + MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14), + MX1_PAD_LD0 = PAD_ID(PD, 15), + MX1_PAD_LD1 = PAD_ID(PD, 16), + MX1_PAD_LD2 = PAD_ID(PD, 17), + MX1_PAD_LD3 = PAD_ID(PD, 18), + MX1_PAD_LD4 = PAD_ID(PD, 19), + MX1_PAD_LD5 = PAD_ID(PD, 20), + MX1_PAD_LD6 = PAD_ID(PD, 21), + MX1_PAD_LD7 = PAD_ID(PD, 22), + MX1_PAD_LD8 = PAD_ID(PD, 23), + MX1_PAD_LD9 = PAD_ID(PD, 24), + MX1_PAD_LD10 = PAD_ID(PD, 25), + MX1_PAD_LD11 = PAD_ID(PD, 26), + MX1_PAD_LD12 = PAD_ID(PD, 27), + MX1_PAD_LD13 = PAD_ID(PD, 28), + MX1_PAD_LD14 = PAD_ID(PD, 29), + MX1_PAD_LD15 = PAD_ID(PD, 30), + MX1_PAD_TMR2OUT = PAD_ID(PD, 31), +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX1_PAD_A24), + IMX_PINCTRL_PIN(MX1_PAD_TIN), + IMX_PINCTRL_PIN(MX1_PAD_PWMO), + IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D0), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D1), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX1_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA), + IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL), + IMX_PINCTRL_PIN(MX1_PAD_DTACK), + IMX_PINCTRL_PIN(MX1_PAD_BCLK), + IMX_PINCTRL_PIN(MX1_PAD_LBA), + IMX_PINCTRL_PIN(MX1_PAD_ECB), + IMX_PINCTRL_PIN(MX1_PAD_A0), + IMX_PINCTRL_PIN(MX1_PAD_CS4), + IMX_PINCTRL_PIN(MX1_PAD_CS5), + IMX_PINCTRL_PIN(MX1_PAD_A16), + IMX_PINCTRL_PIN(MX1_PAD_A17), + IMX_PINCTRL_PIN(MX1_PAD_A18), + IMX_PINCTRL_PIN(MX1_PAD_A19), + IMX_PINCTRL_PIN(MX1_PAD_A20), + IMX_PINCTRL_PIN(MX1_PAD_A21), + IMX_PINCTRL_PIN(MX1_PAD_A22), + IMX_PINCTRL_PIN(MX1_PAD_A23), + IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0), + IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1), + IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2), + IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3), + IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK), + IMX_PINCTRL_PIN(MX1_PAD_SD_CMD), + IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN), + IMX_PINCTRL_PIN(MX1_PAD_SIM_PD), + IMX_PINCTRL_PIN(MX1_PAD_SIM_TX), + IMX_PINCTRL_PIN(MX1_PAD_SIM_RX), + IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK), + IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE), + IMX_PINCTRL_PIN(MX1_PAD_USBD_OE), + IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV), + IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND), + IMX_PINCTRL_PIN(MX1_PAD_USBD_VP), + IMX_PINCTRL_PIN(MX1_PAD_USBD_VM), + IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO), + IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO), + IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS), + IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK), + IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT), + IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT), + IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS), + IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK), + IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO), + IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI), + IMX_PINCTRL_PIN(MX1_PAD_BT13), + IMX_PINCTRL_PIN(MX1_PAD_BT12), + IMX_PINCTRL_PIN(MX1_PAD_BT11), + IMX_PINCTRL_PIN(MX1_PAD_BT10), + IMX_PINCTRL_PIN(MX1_PAD_BT9), + IMX_PINCTRL_PIN(MX1_PAD_BT8), + IMX_PINCTRL_PIN(MX1_PAD_BT7), + IMX_PINCTRL_PIN(MX1_PAD_BT6), + IMX_PINCTRL_PIN(MX1_PAD_BT5), + IMX_PINCTRL_PIN(MX1_PAD_BT4), + IMX_PINCTRL_PIN(MX1_PAD_BT3), + IMX_PINCTRL_PIN(MX1_PAD_BT2), + IMX_PINCTRL_PIN(MX1_PAD_BT1), + IMX_PINCTRL_PIN(MX1_PAD_LSCLK), + IMX_PINCTRL_PIN(MX1_PAD_REV), + IMX_PINCTRL_PIN(MX1_PAD_CLS), + IMX_PINCTRL_PIN(MX1_PAD_PS), + IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR), + IMX_PINCTRL_PIN(MX1_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX1_PAD_ACD_OE), + IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC), + IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC), + IMX_PINCTRL_PIN(MX1_PAD_LD0), + IMX_PINCTRL_PIN(MX1_PAD_LD1), + IMX_PINCTRL_PIN(MX1_PAD_LD2), + IMX_PINCTRL_PIN(MX1_PAD_LD3), + IMX_PINCTRL_PIN(MX1_PAD_LD4), + IMX_PINCTRL_PIN(MX1_PAD_LD5), + IMX_PINCTRL_PIN(MX1_PAD_LD6), + IMX_PINCTRL_PIN(MX1_PAD_LD7), + IMX_PINCTRL_PIN(MX1_PAD_LD8), + IMX_PINCTRL_PIN(MX1_PAD_LD9), + IMX_PINCTRL_PIN(MX1_PAD_LD10), + IMX_PINCTRL_PIN(MX1_PAD_LD11), + IMX_PINCTRL_PIN(MX1_PAD_LD12), + IMX_PINCTRL_PIN(MX1_PAD_LD13), + IMX_PINCTRL_PIN(MX1_PAD_LD14), + IMX_PINCTRL_PIN(MX1_PAD_LD15), + IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT), +}; + +static struct imx1_pinctrl_soc_info imx1_pinctrl_info = { + .pins = imx1_pinctrl_pads, + .npins = ARRAY_SIZE(imx1_pinctrl_pads), +}; + +static int __init imx1_pinctrl_probe(struct platform_device *pdev) +{ + return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info); +} + +static const struct of_device_id imx1_pinctrl_of_match[] = { + { .compatible = "fsl,imx1-iomuxc", }, + { } +}; +MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match); + +static struct platform_driver imx1_pinctrl_driver = { + .driver = { + .name = "imx1-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx1_pinctrl_of_match, + }, + .remove = imx1_pinctrl_core_remove, +}; +module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe); + +MODULE_AUTHOR("Alexander Shiyan "); +MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.h b/drivers/pinctrl/freescale/pinctrl-imx1.h new file mode 100644 index 000000000000..692a54c15cda --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx1.h @@ -0,0 +1,73 @@ +/* + * IMX pinmux core definitions + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + * + * Author: Dong Aisheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DRIVERS_PINCTRL_IMX1_H +#define __DRIVERS_PINCTRL_IMX1_H + +struct platform_device; + +/** + * struct imx1_pin - describes an IMX1/21/27 pin. + * @pin_id: ID of the described pin. + * @mux_id: ID of the mux setup. + * @config: Configuration of the pin (currently only pullup-enable). + */ +struct imx1_pin { + unsigned int pin_id; + unsigned int mux_id; + unsigned long config; +}; + +/** + * struct imx1_pin_group - describes an IMX pin group + * @name: the name of this specific pin group + * @pins: an array of imx1_pin structs used in this group + * @npins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + */ +struct imx1_pin_group { + const char *name; + unsigned int *pin_ids; + struct imx1_pin *pins; + unsigned npins; +}; + +/** + * struct imx1_pmx_func - describes IMX pinmux functions + * @name: the name of this specific function + * @groups: corresponding pin groups + * @num_groups: the number of groups + */ +struct imx1_pmx_func { + const char *name; + const char **groups; + unsigned num_groups; +}; + +struct imx1_pinctrl_soc_info { + struct device *dev; + const struct pinctrl_pin_desc *pins; + unsigned int npins; + struct imx1_pin_group *groups; + unsigned int ngroups; + struct imx1_pmx_func *functions; + unsigned int nfunctions; +}; + +#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) + +int imx1_pinctrl_core_probe(struct platform_device *pdev, + struct imx1_pinctrl_soc_info *info); +int imx1_pinctrl_core_remove(struct platform_device *pdev); +#endif /* __DRIVERS_PINCTRL_IMX1_H */ diff --git a/drivers/pinctrl/freescale/pinctrl-imx21.c b/drivers/pinctrl/freescale/pinctrl-imx21.c new file mode 100644 index 000000000000..1b3b2311b033 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx21.c @@ -0,0 +1,342 @@ +/* + * i.MX21 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2014 Alexander Shiyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +#include "pinctrl-imx1.h" + +#define PAD_ID(port, pin) ((port) * 32 + (pin)) +#define PA 0 +#define PB 1 +#define PC 2 +#define PD 3 +#define PE 4 +#define PF 5 + +enum imx21_pads { + MX21_PAD_LSCLK = PAD_ID(PA, 5), + MX21_PAD_LD0 = PAD_ID(PA, 6), + MX21_PAD_LD1 = PAD_ID(PA, 7), + MX21_PAD_LD2 = PAD_ID(PA, 8), + MX21_PAD_LD3 = PAD_ID(PA, 9), + MX21_PAD_LD4 = PAD_ID(PA, 10), + MX21_PAD_LD5 = PAD_ID(PA, 11), + MX21_PAD_LD6 = PAD_ID(PA, 12), + MX21_PAD_LD7 = PAD_ID(PA, 13), + MX21_PAD_LD8 = PAD_ID(PA, 14), + MX21_PAD_LD9 = PAD_ID(PA, 15), + MX21_PAD_LD10 = PAD_ID(PA, 16), + MX21_PAD_LD11 = PAD_ID(PA, 17), + MX21_PAD_LD12 = PAD_ID(PA, 18), + MX21_PAD_LD13 = PAD_ID(PA, 19), + MX21_PAD_LD14 = PAD_ID(PA, 20), + MX21_PAD_LD15 = PAD_ID(PA, 21), + MX21_PAD_LD16 = PAD_ID(PA, 22), + MX21_PAD_LD17 = PAD_ID(PA, 23), + MX21_PAD_REV = PAD_ID(PA, 24), + MX21_PAD_CLS = PAD_ID(PA, 25), + MX21_PAD_PS = PAD_ID(PA, 26), + MX21_PAD_SPL_SPR = PAD_ID(PA, 27), + MX21_PAD_HSYNC = PAD_ID(PA, 28), + MX21_PAD_VSYNC = PAD_ID(PA, 29), + MX21_PAD_CONTRAST = PAD_ID(PA, 30), + MX21_PAD_OE_ACD = PAD_ID(PA, 31), + MX21_PAD_SD2_D0 = PAD_ID(PB, 4), + MX21_PAD_SD2_D1 = PAD_ID(PB, 5), + MX21_PAD_SD2_D2 = PAD_ID(PB, 6), + MX21_PAD_SD2_D3 = PAD_ID(PB, 7), + MX21_PAD_SD2_CMD = PAD_ID(PB, 8), + MX21_PAD_SD2_CLK = PAD_ID(PB, 9), + MX21_PAD_CSI_D0 = PAD_ID(PB, 10), + MX21_PAD_CSI_D1 = PAD_ID(PB, 11), + MX21_PAD_CSI_D2 = PAD_ID(PB, 12), + MX21_PAD_CSI_D3 = PAD_ID(PB, 13), + MX21_PAD_CSI_D4 = PAD_ID(PB, 14), + MX21_PAD_CSI_MCLK = PAD_ID(PB, 15), + MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16), + MX21_PAD_CSI_D5 = PAD_ID(PB, 17), + MX21_PAD_CSI_D6 = PAD_ID(PB, 18), + MX21_PAD_CSI_D7 = PAD_ID(PB, 19), + MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20), + MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21), + MX21_PAD_USB_BYP = PAD_ID(PB, 22), + MX21_PAD_USB_PWR = PAD_ID(PB, 23), + MX21_PAD_USB_OC = PAD_ID(PB, 24), + MX21_PAD_USBH_ON = PAD_ID(PB, 25), + MX21_PAD_USBH1_FS = PAD_ID(PB, 26), + MX21_PAD_USBH1_OE = PAD_ID(PB, 27), + MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28), + MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29), + MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30), + MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31), + MX21_PAD_USBG_SDA = PAD_ID(PC, 5), + MX21_PAD_USBG_SCL = PAD_ID(PC, 6), + MX21_PAD_USBG_ON = PAD_ID(PC, 7), + MX21_PAD_USBG_FS = PAD_ID(PC, 8), + MX21_PAD_USBG_OE = PAD_ID(PC, 9), + MX21_PAD_USBG_TXDM = PAD_ID(PC, 10), + MX21_PAD_USBG_TXDP = PAD_ID(PC, 11), + MX21_PAD_USBG_RXDM = PAD_ID(PC, 12), + MX21_PAD_USBG_RXDP = PAD_ID(PC, 13), + MX21_PAD_TOUT = PAD_ID(PC, 14), + MX21_PAD_TIN = PAD_ID(PC, 15), + MX21_PAD_SAP_FS = PAD_ID(PC, 16), + MX21_PAD_SAP_RXD = PAD_ID(PC, 17), + MX21_PAD_SAP_TXD = PAD_ID(PC, 18), + MX21_PAD_SAP_CLK = PAD_ID(PC, 19), + MX21_PAD_SSI1_FS = PAD_ID(PC, 20), + MX21_PAD_SSI1_RXD = PAD_ID(PC, 21), + MX21_PAD_SSI1_TXD = PAD_ID(PC, 22), + MX21_PAD_SSI1_CLK = PAD_ID(PC, 23), + MX21_PAD_SSI2_FS = PAD_ID(PC, 24), + MX21_PAD_SSI2_RXD = PAD_ID(PC, 25), + MX21_PAD_SSI2_TXD = PAD_ID(PC, 26), + MX21_PAD_SSI2_CLK = PAD_ID(PC, 27), + MX21_PAD_SSI3_FS = PAD_ID(PC, 28), + MX21_PAD_SSI3_RXD = PAD_ID(PC, 29), + MX21_PAD_SSI3_TXD = PAD_ID(PC, 30), + MX21_PAD_SSI3_CLK = PAD_ID(PC, 31), + MX21_PAD_I2C_DATA = PAD_ID(PD, 17), + MX21_PAD_I2C_CLK = PAD_ID(PD, 18), + MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19), + MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20), + MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21), + MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22), + MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23), + MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24), + MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25), + MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26), + MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27), + MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28), + MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29), + MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30), + MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31), + MX21_PAD_TEST_WB2 = PAD_ID(PE, 0), + MX21_PAD_TEST_WB1 = PAD_ID(PE, 1), + MX21_PAD_TEST_WB0 = PAD_ID(PE, 2), + MX21_PAD_UART2_CTS = PAD_ID(PE, 3), + MX21_PAD_UART2_RTS = PAD_ID(PE, 4), + MX21_PAD_PWMO = PAD_ID(PE, 5), + MX21_PAD_UART2_TXD = PAD_ID(PE, 6), + MX21_PAD_UART2_RXD = PAD_ID(PE, 7), + MX21_PAD_UART3_TXD = PAD_ID(PE, 8), + MX21_PAD_UART3_RXD = PAD_ID(PE, 9), + MX21_PAD_UART3_CTS = PAD_ID(PE, 10), + MX21_PAD_UART3_RTS = PAD_ID(PE, 11), + MX21_PAD_UART1_TXD = PAD_ID(PE, 12), + MX21_PAD_UART1_RXD = PAD_ID(PE, 13), + MX21_PAD_UART1_CTS = PAD_ID(PE, 14), + MX21_PAD_UART1_RTS = PAD_ID(PE, 15), + MX21_PAD_RTCK = PAD_ID(PE, 16), + MX21_PAD_RESET_OUT = PAD_ID(PE, 17), + MX21_PAD_SD1_D0 = PAD_ID(PE, 18), + MX21_PAD_SD1_D1 = PAD_ID(PE, 19), + MX21_PAD_SD1_D2 = PAD_ID(PE, 20), + MX21_PAD_SD1_D3 = PAD_ID(PE, 21), + MX21_PAD_SD1_CMD = PAD_ID(PE, 22), + MX21_PAD_SD1_CLK = PAD_ID(PE, 23), + MX21_PAD_NFRB = PAD_ID(PF, 0), + MX21_PAD_NFCE = PAD_ID(PF, 1), + MX21_PAD_NFWP = PAD_ID(PF, 2), + MX21_PAD_NFCLE = PAD_ID(PF, 3), + MX21_PAD_NFALE = PAD_ID(PF, 4), + MX21_PAD_NFRE = PAD_ID(PF, 5), + MX21_PAD_NFWE = PAD_ID(PF, 6), + MX21_PAD_NFIO0 = PAD_ID(PF, 7), + MX21_PAD_NFIO1 = PAD_ID(PF, 8), + MX21_PAD_NFIO2 = PAD_ID(PF, 9), + MX21_PAD_NFIO3 = PAD_ID(PF, 10), + MX21_PAD_NFIO4 = PAD_ID(PF, 11), + MX21_PAD_NFIO5 = PAD_ID(PF, 12), + MX21_PAD_NFIO6 = PAD_ID(PF, 13), + MX21_PAD_NFIO7 = PAD_ID(PF, 14), + MX21_PAD_CLKO = PAD_ID(PF, 15), + MX21_PAD_RESERVED = PAD_ID(PF, 16), + MX21_PAD_CS4 = PAD_ID(PF, 21), + MX21_PAD_CS5 = PAD_ID(PF, 22), +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX21_PAD_LSCLK), + IMX_PINCTRL_PIN(MX21_PAD_LD0), + IMX_PINCTRL_PIN(MX21_PAD_LD1), + IMX_PINCTRL_PIN(MX21_PAD_LD2), + IMX_PINCTRL_PIN(MX21_PAD_LD3), + IMX_PINCTRL_PIN(MX21_PAD_LD4), + IMX_PINCTRL_PIN(MX21_PAD_LD5), + IMX_PINCTRL_PIN(MX21_PAD_LD6), + IMX_PINCTRL_PIN(MX21_PAD_LD7), + IMX_PINCTRL_PIN(MX21_PAD_LD8), + IMX_PINCTRL_PIN(MX21_PAD_LD9), + IMX_PINCTRL_PIN(MX21_PAD_LD10), + IMX_PINCTRL_PIN(MX21_PAD_LD11), + IMX_PINCTRL_PIN(MX21_PAD_LD12), + IMX_PINCTRL_PIN(MX21_PAD_LD13), + IMX_PINCTRL_PIN(MX21_PAD_LD14), + IMX_PINCTRL_PIN(MX21_PAD_LD15), + IMX_PINCTRL_PIN(MX21_PAD_LD16), + IMX_PINCTRL_PIN(MX21_PAD_LD17), + IMX_PINCTRL_PIN(MX21_PAD_REV), + IMX_PINCTRL_PIN(MX21_PAD_CLS), + IMX_PINCTRL_PIN(MX21_PAD_PS), + IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR), + IMX_PINCTRL_PIN(MX21_PAD_HSYNC), + IMX_PINCTRL_PIN(MX21_PAD_VSYNC), + IMX_PINCTRL_PIN(MX21_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX21_PAD_OE_ACD), + IMX_PINCTRL_PIN(MX21_PAD_SD2_D0), + IMX_PINCTRL_PIN(MX21_PAD_SD2_D1), + IMX_PINCTRL_PIN(MX21_PAD_SD2_D2), + IMX_PINCTRL_PIN(MX21_PAD_SD2_D3), + IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D0), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D1), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX21_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX21_PAD_USB_BYP), + IMX_PINCTRL_PIN(MX21_PAD_USB_PWR), + IMX_PINCTRL_PIN(MX21_PAD_USB_OC), + IMX_PINCTRL_PIN(MX21_PAD_USBH_ON), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM), + IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP), + IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA), + IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL), + IMX_PINCTRL_PIN(MX21_PAD_USBG_ON), + IMX_PINCTRL_PIN(MX21_PAD_USBG_FS), + IMX_PINCTRL_PIN(MX21_PAD_USBG_OE), + IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM), + IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP), + IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM), + IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP), + IMX_PINCTRL_PIN(MX21_PAD_TOUT), + IMX_PINCTRL_PIN(MX21_PAD_TIN), + IMX_PINCTRL_PIN(MX21_PAD_SAP_FS), + IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD), + IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD), + IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK), + IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS), + IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK), + IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS), + IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK), + IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS), + IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD), + IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK), + IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA), + IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO), + IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI), + IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2), + IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1), + IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0), + IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX21_PAD_PWMO), + IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD), + IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD), + IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS), + IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS), + IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX21_PAD_RTCK), + IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT), + IMX_PINCTRL_PIN(MX21_PAD_SD1_D0), + IMX_PINCTRL_PIN(MX21_PAD_SD1_D1), + IMX_PINCTRL_PIN(MX21_PAD_SD1_D2), + IMX_PINCTRL_PIN(MX21_PAD_SD1_D3), + IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX21_PAD_NFRB), + IMX_PINCTRL_PIN(MX21_PAD_NFCE), + IMX_PINCTRL_PIN(MX21_PAD_NFWP), + IMX_PINCTRL_PIN(MX21_PAD_NFCLE), + IMX_PINCTRL_PIN(MX21_PAD_NFALE), + IMX_PINCTRL_PIN(MX21_PAD_NFRE), + IMX_PINCTRL_PIN(MX21_PAD_NFWE), + IMX_PINCTRL_PIN(MX21_PAD_NFIO0), + IMX_PINCTRL_PIN(MX21_PAD_NFIO1), + IMX_PINCTRL_PIN(MX21_PAD_NFIO2), + IMX_PINCTRL_PIN(MX21_PAD_NFIO3), + IMX_PINCTRL_PIN(MX21_PAD_NFIO4), + IMX_PINCTRL_PIN(MX21_PAD_NFIO5), + IMX_PINCTRL_PIN(MX21_PAD_NFIO6), + IMX_PINCTRL_PIN(MX21_PAD_NFIO7), + IMX_PINCTRL_PIN(MX21_PAD_CLKO), + IMX_PINCTRL_PIN(MX21_PAD_RESERVED), + IMX_PINCTRL_PIN(MX21_PAD_CS4), + IMX_PINCTRL_PIN(MX21_PAD_CS5), +}; + +static struct imx1_pinctrl_soc_info imx21_pinctrl_info = { + .pins = imx21_pinctrl_pads, + .npins = ARRAY_SIZE(imx21_pinctrl_pads), +}; + +static int __init imx21_pinctrl_probe(struct platform_device *pdev) +{ + return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info); +} + +static const struct of_device_id imx21_pinctrl_of_match[] = { + { .compatible = "fsl,imx21-iomuxc", }, + { } +}; +MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match); + +static struct platform_driver imx21_pinctrl_driver = { + .driver = { + .name = "imx21-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx21_pinctrl_of_match, + }, + .remove = imx1_pinctrl_core_remove, +}; +module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe); + +MODULE_AUTHOR("Alexander Shiyan "); +MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c new file mode 100644 index 000000000000..df79096becb0 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx23.c @@ -0,0 +1,305 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include "pinctrl-mxs.h" + +enum imx23_pin_enum { + GPMI_D00 = PINID(0, 0), + GPMI_D01 = PINID(0, 1), + GPMI_D02 = PINID(0, 2), + GPMI_D03 = PINID(0, 3), + GPMI_D04 = PINID(0, 4), + GPMI_D05 = PINID(0, 5), + GPMI_D06 = PINID(0, 6), + GPMI_D07 = PINID(0, 7), + GPMI_D08 = PINID(0, 8), + GPMI_D09 = PINID(0, 9), + GPMI_D10 = PINID(0, 10), + GPMI_D11 = PINID(0, 11), + GPMI_D12 = PINID(0, 12), + GPMI_D13 = PINID(0, 13), + GPMI_D14 = PINID(0, 14), + GPMI_D15 = PINID(0, 15), + GPMI_CLE = PINID(0, 16), + GPMI_ALE = PINID(0, 17), + GPMI_CE2N = PINID(0, 18), + GPMI_RDY0 = PINID(0, 19), + GPMI_RDY1 = PINID(0, 20), + GPMI_RDY2 = PINID(0, 21), + GPMI_RDY3 = PINID(0, 22), + GPMI_WPN = PINID(0, 23), + GPMI_WRN = PINID(0, 24), + GPMI_RDN = PINID(0, 25), + AUART1_CTS = PINID(0, 26), + AUART1_RTS = PINID(0, 27), + AUART1_RX = PINID(0, 28), + AUART1_TX = PINID(0, 29), + I2C_SCL = PINID(0, 30), + I2C_SDA = PINID(0, 31), + LCD_D00 = PINID(1, 0), + LCD_D01 = PINID(1, 1), + LCD_D02 = PINID(1, 2), + LCD_D03 = PINID(1, 3), + LCD_D04 = PINID(1, 4), + LCD_D05 = PINID(1, 5), + LCD_D06 = PINID(1, 6), + LCD_D07 = PINID(1, 7), + LCD_D08 = PINID(1, 8), + LCD_D09 = PINID(1, 9), + LCD_D10 = PINID(1, 10), + LCD_D11 = PINID(1, 11), + LCD_D12 = PINID(1, 12), + LCD_D13 = PINID(1, 13), + LCD_D14 = PINID(1, 14), + LCD_D15 = PINID(1, 15), + LCD_D16 = PINID(1, 16), + LCD_D17 = PINID(1, 17), + LCD_RESET = PINID(1, 18), + LCD_RS = PINID(1, 19), + LCD_WR = PINID(1, 20), + LCD_CS = PINID(1, 21), + LCD_DOTCK = PINID(1, 22), + LCD_ENABLE = PINID(1, 23), + LCD_HSYNC = PINID(1, 24), + LCD_VSYNC = PINID(1, 25), + PWM0 = PINID(1, 26), + PWM1 = PINID(1, 27), + PWM2 = PINID(1, 28), + PWM3 = PINID(1, 29), + PWM4 = PINID(1, 30), + SSP1_CMD = PINID(2, 0), + SSP1_DETECT = PINID(2, 1), + SSP1_DATA0 = PINID(2, 2), + SSP1_DATA1 = PINID(2, 3), + SSP1_DATA2 = PINID(2, 4), + SSP1_DATA3 = PINID(2, 5), + SSP1_SCK = PINID(2, 6), + ROTARYA = PINID(2, 7), + ROTARYB = PINID(2, 8), + EMI_A00 = PINID(2, 9), + EMI_A01 = PINID(2, 10), + EMI_A02 = PINID(2, 11), + EMI_A03 = PINID(2, 12), + EMI_A04 = PINID(2, 13), + EMI_A05 = PINID(2, 14), + EMI_A06 = PINID(2, 15), + EMI_A07 = PINID(2, 16), + EMI_A08 = PINID(2, 17), + EMI_A09 = PINID(2, 18), + EMI_A10 = PINID(2, 19), + EMI_A11 = PINID(2, 20), + EMI_A12 = PINID(2, 21), + EMI_BA0 = PINID(2, 22), + EMI_BA1 = PINID(2, 23), + EMI_CASN = PINID(2, 24), + EMI_CE0N = PINID(2, 25), + EMI_CE1N = PINID(2, 26), + GPMI_CE1N = PINID(2, 27), + GPMI_CE0N = PINID(2, 28), + EMI_CKE = PINID(2, 29), + EMI_RASN = PINID(2, 30), + EMI_WEN = PINID(2, 31), + EMI_D00 = PINID(3, 0), + EMI_D01 = PINID(3, 1), + EMI_D02 = PINID(3, 2), + EMI_D03 = PINID(3, 3), + EMI_D04 = PINID(3, 4), + EMI_D05 = PINID(3, 5), + EMI_D06 = PINID(3, 6), + EMI_D07 = PINID(3, 7), + EMI_D08 = PINID(3, 8), + EMI_D09 = PINID(3, 9), + EMI_D10 = PINID(3, 10), + EMI_D11 = PINID(3, 11), + EMI_D12 = PINID(3, 12), + EMI_D13 = PINID(3, 13), + EMI_D14 = PINID(3, 14), + EMI_D15 = PINID(3, 15), + EMI_DQM0 = PINID(3, 16), + EMI_DQM1 = PINID(3, 17), + EMI_DQS0 = PINID(3, 18), + EMI_DQS1 = PINID(3, 19), + EMI_CLK = PINID(3, 20), + EMI_CLKN = PINID(3, 21), +}; + +static const struct pinctrl_pin_desc imx23_pins[] = { + MXS_PINCTRL_PIN(GPMI_D00), + MXS_PINCTRL_PIN(GPMI_D01), + MXS_PINCTRL_PIN(GPMI_D02), + MXS_PINCTRL_PIN(GPMI_D03), + MXS_PINCTRL_PIN(GPMI_D04), + MXS_PINCTRL_PIN(GPMI_D05), + MXS_PINCTRL_PIN(GPMI_D06), + MXS_PINCTRL_PIN(GPMI_D07), + MXS_PINCTRL_PIN(GPMI_D08), + MXS_PINCTRL_PIN(GPMI_D09), + MXS_PINCTRL_PIN(GPMI_D10), + MXS_PINCTRL_PIN(GPMI_D11), + MXS_PINCTRL_PIN(GPMI_D12), + MXS_PINCTRL_PIN(GPMI_D13), + MXS_PINCTRL_PIN(GPMI_D14), + MXS_PINCTRL_PIN(GPMI_D15), + MXS_PINCTRL_PIN(GPMI_CLE), + MXS_PINCTRL_PIN(GPMI_ALE), + MXS_PINCTRL_PIN(GPMI_CE2N), + MXS_PINCTRL_PIN(GPMI_RDY0), + MXS_PINCTRL_PIN(GPMI_RDY1), + MXS_PINCTRL_PIN(GPMI_RDY2), + MXS_PINCTRL_PIN(GPMI_RDY3), + MXS_PINCTRL_PIN(GPMI_WPN), + MXS_PINCTRL_PIN(GPMI_WRN), + MXS_PINCTRL_PIN(GPMI_RDN), + MXS_PINCTRL_PIN(AUART1_CTS), + MXS_PINCTRL_PIN(AUART1_RTS), + MXS_PINCTRL_PIN(AUART1_RX), + MXS_PINCTRL_PIN(AUART1_TX), + MXS_PINCTRL_PIN(I2C_SCL), + MXS_PINCTRL_PIN(I2C_SDA), + MXS_PINCTRL_PIN(LCD_D00), + MXS_PINCTRL_PIN(LCD_D01), + MXS_PINCTRL_PIN(LCD_D02), + MXS_PINCTRL_PIN(LCD_D03), + MXS_PINCTRL_PIN(LCD_D04), + MXS_PINCTRL_PIN(LCD_D05), + MXS_PINCTRL_PIN(LCD_D06), + MXS_PINCTRL_PIN(LCD_D07), + MXS_PINCTRL_PIN(LCD_D08), + MXS_PINCTRL_PIN(LCD_D09), + MXS_PINCTRL_PIN(LCD_D10), + MXS_PINCTRL_PIN(LCD_D11), + MXS_PINCTRL_PIN(LCD_D12), + MXS_PINCTRL_PIN(LCD_D13), + MXS_PINCTRL_PIN(LCD_D14), + MXS_PINCTRL_PIN(LCD_D15), + MXS_PINCTRL_PIN(LCD_D16), + MXS_PINCTRL_PIN(LCD_D17), + MXS_PINCTRL_PIN(LCD_RESET), + MXS_PINCTRL_PIN(LCD_RS), + MXS_PINCTRL_PIN(LCD_WR), + MXS_PINCTRL_PIN(LCD_CS), + MXS_PINCTRL_PIN(LCD_DOTCK), + MXS_PINCTRL_PIN(LCD_ENABLE), + MXS_PINCTRL_PIN(LCD_HSYNC), + MXS_PINCTRL_PIN(LCD_VSYNC), + MXS_PINCTRL_PIN(PWM0), + MXS_PINCTRL_PIN(PWM1), + MXS_PINCTRL_PIN(PWM2), + MXS_PINCTRL_PIN(PWM3), + MXS_PINCTRL_PIN(PWM4), + MXS_PINCTRL_PIN(SSP1_CMD), + MXS_PINCTRL_PIN(SSP1_DETECT), + MXS_PINCTRL_PIN(SSP1_DATA0), + MXS_PINCTRL_PIN(SSP1_DATA1), + MXS_PINCTRL_PIN(SSP1_DATA2), + MXS_PINCTRL_PIN(SSP1_DATA3), + MXS_PINCTRL_PIN(SSP1_SCK), + MXS_PINCTRL_PIN(ROTARYA), + MXS_PINCTRL_PIN(ROTARYB), + MXS_PINCTRL_PIN(EMI_A00), + MXS_PINCTRL_PIN(EMI_A01), + MXS_PINCTRL_PIN(EMI_A02), + MXS_PINCTRL_PIN(EMI_A03), + MXS_PINCTRL_PIN(EMI_A04), + MXS_PINCTRL_PIN(EMI_A05), + MXS_PINCTRL_PIN(EMI_A06), + MXS_PINCTRL_PIN(EMI_A07), + MXS_PINCTRL_PIN(EMI_A08), + MXS_PINCTRL_PIN(EMI_A09), + MXS_PINCTRL_PIN(EMI_A10), + MXS_PINCTRL_PIN(EMI_A11), + MXS_PINCTRL_PIN(EMI_A12), + MXS_PINCTRL_PIN(EMI_BA0), + MXS_PINCTRL_PIN(EMI_BA1), + MXS_PINCTRL_PIN(EMI_CASN), + MXS_PINCTRL_PIN(EMI_CE0N), + MXS_PINCTRL_PIN(EMI_CE1N), + MXS_PINCTRL_PIN(GPMI_CE1N), + MXS_PINCTRL_PIN(GPMI_CE0N), + MXS_PINCTRL_PIN(EMI_CKE), + MXS_PINCTRL_PIN(EMI_RASN), + MXS_PINCTRL_PIN(EMI_WEN), + MXS_PINCTRL_PIN(EMI_D00), + MXS_PINCTRL_PIN(EMI_D01), + MXS_PINCTRL_PIN(EMI_D02), + MXS_PINCTRL_PIN(EMI_D03), + MXS_PINCTRL_PIN(EMI_D04), + MXS_PINCTRL_PIN(EMI_D05), + MXS_PINCTRL_PIN(EMI_D06), + MXS_PINCTRL_PIN(EMI_D07), + MXS_PINCTRL_PIN(EMI_D08), + MXS_PINCTRL_PIN(EMI_D09), + MXS_PINCTRL_PIN(EMI_D10), + MXS_PINCTRL_PIN(EMI_D11), + MXS_PINCTRL_PIN(EMI_D12), + MXS_PINCTRL_PIN(EMI_D13), + MXS_PINCTRL_PIN(EMI_D14), + MXS_PINCTRL_PIN(EMI_D15), + MXS_PINCTRL_PIN(EMI_DQM0), + MXS_PINCTRL_PIN(EMI_DQM1), + MXS_PINCTRL_PIN(EMI_DQS0), + MXS_PINCTRL_PIN(EMI_DQS1), + MXS_PINCTRL_PIN(EMI_CLK), + MXS_PINCTRL_PIN(EMI_CLKN), +}; + +static struct mxs_regs imx23_regs = { + .muxsel = 0x100, + .drive = 0x200, + .pull = 0x400, +}; + +static struct mxs_pinctrl_soc_data imx23_pinctrl_data = { + .regs = &imx23_regs, + .pins = imx23_pins, + .npins = ARRAY_SIZE(imx23_pins), +}; + +static int imx23_pinctrl_probe(struct platform_device *pdev) +{ + return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data); +} + +static const struct of_device_id imx23_pinctrl_of_match[] = { + { .compatible = "fsl,imx23-pinctrl", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match); + +static struct platform_driver imx23_pinctrl_driver = { + .driver = { + .name = "imx23-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx23_pinctrl_of_match, + }, + .probe = imx23_pinctrl_probe, + .remove = mxs_pinctrl_remove, +}; + +static int __init imx23_pinctrl_init(void) +{ + return platform_driver_register(&imx23_pinctrl_driver); +} +postcore_initcall(imx23_pinctrl_init); + +static void __exit imx23_pinctrl_exit(void) +{ + platform_driver_unregister(&imx23_pinctrl_driver); +} +module_exit(imx23_pinctrl_exit); + +MODULE_AUTHOR("Shawn Guo "); +MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c new file mode 100644 index 000000000000..550e6d77ac2b --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx25.c @@ -0,0 +1,351 @@ +/* + * imx25 pinctrl driver. + * + * Copyright 2013 Eukréa Electromatique + * + * This driver was mostly copied from the imx51 pinctrl driver which has: + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro, Inc. + * + * Author: Denis Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx25_pads { + MX25_PAD_RESERVE0 = 1, + MX25_PAD_RESERVE1 = 2, + MX25_PAD_A10 = 3, + MX25_PAD_A13 = 4, + MX25_PAD_A14 = 5, + MX25_PAD_A15 = 6, + MX25_PAD_A16 = 7, + MX25_PAD_A17 = 8, + MX25_PAD_A18 = 9, + MX25_PAD_A19 = 10, + MX25_PAD_A20 = 11, + MX25_PAD_A21 = 12, + MX25_PAD_A22 = 13, + MX25_PAD_A23 = 14, + MX25_PAD_A24 = 15, + MX25_PAD_A25 = 16, + MX25_PAD_EB0 = 17, + MX25_PAD_EB1 = 18, + MX25_PAD_OE = 19, + MX25_PAD_CS0 = 20, + MX25_PAD_CS1 = 21, + MX25_PAD_CS4 = 22, + MX25_PAD_CS5 = 23, + MX25_PAD_NF_CE0 = 24, + MX25_PAD_ECB = 25, + MX25_PAD_LBA = 26, + MX25_PAD_BCLK = 27, + MX25_PAD_RW = 28, + MX25_PAD_NFWE_B = 29, + MX25_PAD_NFRE_B = 30, + MX25_PAD_NFALE = 31, + MX25_PAD_NFCLE = 32, + MX25_PAD_NFWP_B = 33, + MX25_PAD_NFRB = 34, + MX25_PAD_D15 = 35, + MX25_PAD_D14 = 36, + MX25_PAD_D13 = 37, + MX25_PAD_D12 = 38, + MX25_PAD_D11 = 39, + MX25_PAD_D10 = 40, + MX25_PAD_D9 = 41, + MX25_PAD_D8 = 42, + MX25_PAD_D7 = 43, + MX25_PAD_D6 = 44, + MX25_PAD_D5 = 45, + MX25_PAD_D4 = 46, + MX25_PAD_D3 = 47, + MX25_PAD_D2 = 48, + MX25_PAD_D1 = 49, + MX25_PAD_D0 = 50, + MX25_PAD_LD0 = 51, + MX25_PAD_LD1 = 52, + MX25_PAD_LD2 = 53, + MX25_PAD_LD3 = 54, + MX25_PAD_LD4 = 55, + MX25_PAD_LD5 = 56, + MX25_PAD_LD6 = 57, + MX25_PAD_LD7 = 58, + MX25_PAD_LD8 = 59, + MX25_PAD_LD9 = 60, + MX25_PAD_LD10 = 61, + MX25_PAD_LD11 = 62, + MX25_PAD_LD12 = 63, + MX25_PAD_LD13 = 64, + MX25_PAD_LD14 = 65, + MX25_PAD_LD15 = 66, + MX25_PAD_HSYNC = 67, + MX25_PAD_VSYNC = 68, + MX25_PAD_LSCLK = 69, + MX25_PAD_OE_ACD = 70, + MX25_PAD_CONTRAST = 71, + MX25_PAD_PWM = 72, + MX25_PAD_CSI_D2 = 73, + MX25_PAD_CSI_D3 = 74, + MX25_PAD_CSI_D4 = 75, + MX25_PAD_CSI_D5 = 76, + MX25_PAD_CSI_D6 = 77, + MX25_PAD_CSI_D7 = 78, + MX25_PAD_CSI_D8 = 79, + MX25_PAD_CSI_D9 = 80, + MX25_PAD_CSI_MCLK = 81, + MX25_PAD_CSI_VSYNC = 82, + MX25_PAD_CSI_HSYNC = 83, + MX25_PAD_CSI_PIXCLK = 84, + MX25_PAD_I2C1_CLK = 85, + MX25_PAD_I2C1_DAT = 86, + MX25_PAD_CSPI1_MOSI = 87, + MX25_PAD_CSPI1_MISO = 88, + MX25_PAD_CSPI1_SS0 = 89, + MX25_PAD_CSPI1_SS1 = 90, + MX25_PAD_CSPI1_SCLK = 91, + MX25_PAD_CSPI1_RDY = 92, + MX25_PAD_UART1_RXD = 93, + MX25_PAD_UART1_TXD = 94, + MX25_PAD_UART1_RTS = 95, + MX25_PAD_UART1_CTS = 96, + MX25_PAD_UART2_RXD = 97, + MX25_PAD_UART2_TXD = 98, + MX25_PAD_UART2_RTS = 99, + MX25_PAD_UART2_CTS = 100, + MX25_PAD_SD1_CMD = 101, + MX25_PAD_SD1_CLK = 102, + MX25_PAD_SD1_DATA0 = 103, + MX25_PAD_SD1_DATA1 = 104, + MX25_PAD_SD1_DATA2 = 105, + MX25_PAD_SD1_DATA3 = 106, + MX25_PAD_KPP_ROW0 = 107, + MX25_PAD_KPP_ROW1 = 108, + MX25_PAD_KPP_ROW2 = 109, + MX25_PAD_KPP_ROW3 = 110, + MX25_PAD_KPP_COL0 = 111, + MX25_PAD_KPP_COL1 = 112, + MX25_PAD_KPP_COL2 = 113, + MX25_PAD_KPP_COL3 = 114, + MX25_PAD_FEC_MDC = 115, + MX25_PAD_FEC_MDIO = 116, + MX25_PAD_FEC_TDATA0 = 117, + MX25_PAD_FEC_TDATA1 = 118, + MX25_PAD_FEC_TX_EN = 119, + MX25_PAD_FEC_RDATA0 = 120, + MX25_PAD_FEC_RDATA1 = 121, + MX25_PAD_FEC_RX_DV = 122, + MX25_PAD_FEC_TX_CLK = 123, + MX25_PAD_RTCK = 124, + MX25_PAD_DE_B = 125, + MX25_PAD_GPIO_A = 126, + MX25_PAD_GPIO_B = 127, + MX25_PAD_GPIO_C = 128, + MX25_PAD_GPIO_D = 129, + MX25_PAD_GPIO_E = 130, + MX25_PAD_GPIO_F = 131, + MX25_PAD_EXT_ARMCLK = 132, + MX25_PAD_UPLL_BYPCLK = 133, + MX25_PAD_VSTBY_REQ = 134, + MX25_PAD_VSTBY_ACK = 135, + MX25_PAD_POWER_FAIL = 136, + MX25_PAD_CLKO = 137, + MX25_PAD_BOOT_MODE0 = 138, + MX25_PAD_BOOT_MODE1 = 139, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX25_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX25_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX25_PAD_A10), + IMX_PINCTRL_PIN(MX25_PAD_A13), + IMX_PINCTRL_PIN(MX25_PAD_A14), + IMX_PINCTRL_PIN(MX25_PAD_A15), + IMX_PINCTRL_PIN(MX25_PAD_A16), + IMX_PINCTRL_PIN(MX25_PAD_A17), + IMX_PINCTRL_PIN(MX25_PAD_A18), + IMX_PINCTRL_PIN(MX25_PAD_A19), + IMX_PINCTRL_PIN(MX25_PAD_A20), + IMX_PINCTRL_PIN(MX25_PAD_A21), + IMX_PINCTRL_PIN(MX25_PAD_A22), + IMX_PINCTRL_PIN(MX25_PAD_A23), + IMX_PINCTRL_PIN(MX25_PAD_A24), + IMX_PINCTRL_PIN(MX25_PAD_A25), + IMX_PINCTRL_PIN(MX25_PAD_EB0), + IMX_PINCTRL_PIN(MX25_PAD_EB1), + IMX_PINCTRL_PIN(MX25_PAD_OE), + IMX_PINCTRL_PIN(MX25_PAD_CS0), + IMX_PINCTRL_PIN(MX25_PAD_CS1), + IMX_PINCTRL_PIN(MX25_PAD_CS4), + IMX_PINCTRL_PIN(MX25_PAD_CS5), + IMX_PINCTRL_PIN(MX25_PAD_NF_CE0), + IMX_PINCTRL_PIN(MX25_PAD_ECB), + IMX_PINCTRL_PIN(MX25_PAD_LBA), + IMX_PINCTRL_PIN(MX25_PAD_BCLK), + IMX_PINCTRL_PIN(MX25_PAD_RW), + IMX_PINCTRL_PIN(MX25_PAD_NFWE_B), + IMX_PINCTRL_PIN(MX25_PAD_NFRE_B), + IMX_PINCTRL_PIN(MX25_PAD_NFALE), + IMX_PINCTRL_PIN(MX25_PAD_NFCLE), + IMX_PINCTRL_PIN(MX25_PAD_NFWP_B), + IMX_PINCTRL_PIN(MX25_PAD_NFRB), + IMX_PINCTRL_PIN(MX25_PAD_D15), + IMX_PINCTRL_PIN(MX25_PAD_D14), + IMX_PINCTRL_PIN(MX25_PAD_D13), + IMX_PINCTRL_PIN(MX25_PAD_D12), + IMX_PINCTRL_PIN(MX25_PAD_D11), + IMX_PINCTRL_PIN(MX25_PAD_D10), + IMX_PINCTRL_PIN(MX25_PAD_D9), + IMX_PINCTRL_PIN(MX25_PAD_D8), + IMX_PINCTRL_PIN(MX25_PAD_D7), + IMX_PINCTRL_PIN(MX25_PAD_D6), + IMX_PINCTRL_PIN(MX25_PAD_D5), + IMX_PINCTRL_PIN(MX25_PAD_D4), + IMX_PINCTRL_PIN(MX25_PAD_D3), + IMX_PINCTRL_PIN(MX25_PAD_D2), + IMX_PINCTRL_PIN(MX25_PAD_D1), + IMX_PINCTRL_PIN(MX25_PAD_D0), + IMX_PINCTRL_PIN(MX25_PAD_LD0), + IMX_PINCTRL_PIN(MX25_PAD_LD1), + IMX_PINCTRL_PIN(MX25_PAD_LD2), + IMX_PINCTRL_PIN(MX25_PAD_LD3), + IMX_PINCTRL_PIN(MX25_PAD_LD4), + IMX_PINCTRL_PIN(MX25_PAD_LD5), + IMX_PINCTRL_PIN(MX25_PAD_LD6), + IMX_PINCTRL_PIN(MX25_PAD_LD7), + IMX_PINCTRL_PIN(MX25_PAD_LD8), + IMX_PINCTRL_PIN(MX25_PAD_LD9), + IMX_PINCTRL_PIN(MX25_PAD_LD10), + IMX_PINCTRL_PIN(MX25_PAD_LD11), + IMX_PINCTRL_PIN(MX25_PAD_LD12), + IMX_PINCTRL_PIN(MX25_PAD_LD13), + IMX_PINCTRL_PIN(MX25_PAD_LD14), + IMX_PINCTRL_PIN(MX25_PAD_LD15), + IMX_PINCTRL_PIN(MX25_PAD_HSYNC), + IMX_PINCTRL_PIN(MX25_PAD_VSYNC), + IMX_PINCTRL_PIN(MX25_PAD_LSCLK), + IMX_PINCTRL_PIN(MX25_PAD_OE_ACD), + IMX_PINCTRL_PIN(MX25_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX25_PAD_PWM), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D8), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D9), + IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK), + IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY), + IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0), + IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1), + IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2), + IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3), + IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0), + IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1), + IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2), + IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3), + IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC), + IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO), + IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0), + IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1), + IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN), + IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0), + IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1), + IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV), + IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK), + IMX_PINCTRL_PIN(MX25_PAD_RTCK), + IMX_PINCTRL_PIN(MX25_PAD_DE_B), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_A), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_B), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_C), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_D), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_E), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_F), + IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK), + IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK), + IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ), + IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK), + IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL), + IMX_PINCTRL_PIN(MX25_PAD_CLKO), + IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0), + IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1), +}; + +static struct imx_pinctrl_soc_info imx25_pinctrl_info = { + .pins = imx25_pinctrl_pads, + .npins = ARRAY_SIZE(imx25_pinctrl_pads), +}; + +static const struct of_device_id imx25_pinctrl_of_match[] = { + { .compatible = "fsl,imx25-iomuxc", }, + { /* sentinel */ } +}; + +static int imx25_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx25_pinctrl_info); +} + +static struct platform_driver imx25_pinctrl_driver = { + .driver = { + .name = "imx25-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx25_pinctrl_of_match), + }, + .probe = imx25_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx25_pinctrl_init(void) +{ + return platform_driver_register(&imx25_pinctrl_driver); +} +arch_initcall(imx25_pinctrl_init); + +static void __exit imx25_pinctrl_exit(void) +{ + platform_driver_unregister(&imx25_pinctrl_driver); +} +module_exit(imx25_pinctrl_exit); +MODULE_AUTHOR("Denis Carikli "); +MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c new file mode 100644 index 000000000000..945eccadea74 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx27.c @@ -0,0 +1,425 @@ +/* + * imx27 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2013 Pengutronix + * + * Author: Markus Pargmann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx1.h" + +#define PAD_ID(port, pin) (port*32 + pin) +#define PA 0 +#define PB 1 +#define PC 2 +#define PD 3 +#define PE 4 +#define PF 5 + +enum imx27_pads { + MX27_PAD_USBH2_CLK = PAD_ID(PA, 0), + MX27_PAD_USBH2_DIR = PAD_ID(PA, 1), + MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2), + MX27_PAD_USBH2_NXT = PAD_ID(PA, 3), + MX27_PAD_USBH2_STP = PAD_ID(PA, 4), + MX27_PAD_LSCLK = PAD_ID(PA, 5), + MX27_PAD_LD0 = PAD_ID(PA, 6), + MX27_PAD_LD1 = PAD_ID(PA, 7), + MX27_PAD_LD2 = PAD_ID(PA, 8), + MX27_PAD_LD3 = PAD_ID(PA, 9), + MX27_PAD_LD4 = PAD_ID(PA, 10), + MX27_PAD_LD5 = PAD_ID(PA, 11), + MX27_PAD_LD6 = PAD_ID(PA, 12), + MX27_PAD_LD7 = PAD_ID(PA, 13), + MX27_PAD_LD8 = PAD_ID(PA, 14), + MX27_PAD_LD9 = PAD_ID(PA, 15), + MX27_PAD_LD10 = PAD_ID(PA, 16), + MX27_PAD_LD11 = PAD_ID(PA, 17), + MX27_PAD_LD12 = PAD_ID(PA, 18), + MX27_PAD_LD13 = PAD_ID(PA, 19), + MX27_PAD_LD14 = PAD_ID(PA, 20), + MX27_PAD_LD15 = PAD_ID(PA, 21), + MX27_PAD_LD16 = PAD_ID(PA, 22), + MX27_PAD_LD17 = PAD_ID(PA, 23), + MX27_PAD_REV = PAD_ID(PA, 24), + MX27_PAD_CLS = PAD_ID(PA, 25), + MX27_PAD_PS = PAD_ID(PA, 26), + MX27_PAD_SPL_SPR = PAD_ID(PA, 27), + MX27_PAD_HSYNC = PAD_ID(PA, 28), + MX27_PAD_VSYNC = PAD_ID(PA, 29), + MX27_PAD_CONTRAST = PAD_ID(PA, 30), + MX27_PAD_OE_ACD = PAD_ID(PA, 31), + + MX27_PAD_SD2_D0 = PAD_ID(PB, 4), + MX27_PAD_SD2_D1 = PAD_ID(PB, 5), + MX27_PAD_SD2_D2 = PAD_ID(PB, 6), + MX27_PAD_SD2_D3 = PAD_ID(PB, 7), + MX27_PAD_SD2_CMD = PAD_ID(PB, 8), + MX27_PAD_SD2_CLK = PAD_ID(PB, 9), + MX27_PAD_CSI_D0 = PAD_ID(PB, 10), + MX27_PAD_CSI_D1 = PAD_ID(PB, 11), + MX27_PAD_CSI_D2 = PAD_ID(PB, 12), + MX27_PAD_CSI_D3 = PAD_ID(PB, 13), + MX27_PAD_CSI_D4 = PAD_ID(PB, 14), + MX27_PAD_CSI_MCLK = PAD_ID(PB, 15), + MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16), + MX27_PAD_CSI_D5 = PAD_ID(PB, 17), + MX27_PAD_CSI_D6 = PAD_ID(PB, 18), + MX27_PAD_CSI_D7 = PAD_ID(PB, 19), + MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20), + MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21), + MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22), + MX27_PAD_USB_PWR = PAD_ID(PB, 23), + MX27_PAD_USB_OC_B = PAD_ID(PB, 24), + MX27_PAD_USBH1_RCV = PAD_ID(PB, 25), + MX27_PAD_USBH1_FS = PAD_ID(PB, 26), + MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27), + MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28), + MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29), + MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), + MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), + + MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), + MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), + MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), + MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8), + MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9), + MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10), + MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11), + MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12), + MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13), + MX27_PAD_TOUT = PAD_ID(PC, 14), + MX27_PAD_TIN = PAD_ID(PC, 15), + MX27_PAD_SSI4_FS = PAD_ID(PC, 16), + MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17), + MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18), + MX27_PAD_SSI4_CLK = PAD_ID(PC, 19), + MX27_PAD_SSI1_FS = PAD_ID(PC, 20), + MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21), + MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22), + MX27_PAD_SSI1_CLK = PAD_ID(PC, 23), + MX27_PAD_SSI2_FS = PAD_ID(PC, 24), + MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25), + MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26), + MX27_PAD_SSI2_CLK = PAD_ID(PC, 27), + MX27_PAD_SSI3_FS = PAD_ID(PC, 28), + MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29), + MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30), + MX27_PAD_SSI3_CLK = PAD_ID(PC, 31), + + MX27_PAD_SD3_CMD = PAD_ID(PD, 0), + MX27_PAD_SD3_CLK = PAD_ID(PD, 1), + MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2), + MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3), + MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4), + MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5), + MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6), + MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7), + MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8), + MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9), + MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10), + MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11), + MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12), + MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13), + MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14), + MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15), + MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16), + MX27_PAD_I2C_DATA = PAD_ID(PD, 17), + MX27_PAD_I2C_CLK = PAD_ID(PD, 18), + MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19), + MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20), + MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21), + MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22), + MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23), + MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24), + MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25), + MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26), + MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27), + MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28), + MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29), + MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30), + MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31), + + MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0), + MX27_PAD_USBOTG_STP = PAD_ID(PE, 1), + MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2), + MX27_PAD_UART2_CTS = PAD_ID(PE, 3), + MX27_PAD_UART2_RTS = PAD_ID(PE, 4), + MX27_PAD_PWMO = PAD_ID(PE, 5), + MX27_PAD_UART2_TXD = PAD_ID(PE, 6), + MX27_PAD_UART2_RXD = PAD_ID(PE, 7), + MX27_PAD_UART3_TXD = PAD_ID(PE, 8), + MX27_PAD_UART3_RXD = PAD_ID(PE, 9), + MX27_PAD_UART3_CTS = PAD_ID(PE, 10), + MX27_PAD_UART3_RTS = PAD_ID(PE, 11), + MX27_PAD_UART1_TXD = PAD_ID(PE, 12), + MX27_PAD_UART1_RXD = PAD_ID(PE, 13), + MX27_PAD_UART1_CTS = PAD_ID(PE, 14), + MX27_PAD_UART1_RTS = PAD_ID(PE, 15), + MX27_PAD_RTCK = PAD_ID(PE, 16), + MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17), + MX27_PAD_SD1_D0 = PAD_ID(PE, 18), + MX27_PAD_SD1_D1 = PAD_ID(PE, 19), + MX27_PAD_SD1_D2 = PAD_ID(PE, 20), + MX27_PAD_SD1_D3 = PAD_ID(PE, 21), + MX27_PAD_SD1_CMD = PAD_ID(PE, 22), + MX27_PAD_SD1_CLK = PAD_ID(PE, 23), + MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), + MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), + + MX27_PAD_NFRB = PAD_ID(PF, 0), + MX27_PAD_NFCLE = PAD_ID(PF, 1), + MX27_PAD_NFWP_B = PAD_ID(PF, 2), + MX27_PAD_NFCE_B = PAD_ID(PF, 3), + MX27_PAD_NFALE = PAD_ID(PF, 4), + MX27_PAD_NFRE_B = PAD_ID(PF, 5), + MX27_PAD_NFWE_B = PAD_ID(PF, 6), + MX27_PAD_PC_POE = PAD_ID(PF, 7), + MX27_PAD_PC_RW_B = PAD_ID(PF, 8), + MX27_PAD_IOIS16 = PAD_ID(PF, 9), + MX27_PAD_PC_RST = PAD_ID(PF, 10), + MX27_PAD_PC_BVD2 = PAD_ID(PF, 11), + MX27_PAD_PC_BVD1 = PAD_ID(PF, 12), + MX27_PAD_PC_VS2 = PAD_ID(PF, 13), + MX27_PAD_PC_VS1 = PAD_ID(PF, 14), + MX27_PAD_CLKO = PAD_ID(PF, 15), + MX27_PAD_PC_PWRON = PAD_ID(PF, 16), + MX27_PAD_PC_READY = PAD_ID(PF, 17), + MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18), + MX27_PAD_PC_CD2_B = PAD_ID(PF, 19), + MX27_PAD_PC_CD1_B = PAD_ID(PF, 20), + MX27_PAD_CS4_B = PAD_ID(PF, 21), + MX27_PAD_CS5_B = PAD_ID(PF, 22), + MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP), + IMX_PINCTRL_PIN(MX27_PAD_LSCLK), + IMX_PINCTRL_PIN(MX27_PAD_LD0), + IMX_PINCTRL_PIN(MX27_PAD_LD1), + IMX_PINCTRL_PIN(MX27_PAD_LD2), + IMX_PINCTRL_PIN(MX27_PAD_LD3), + IMX_PINCTRL_PIN(MX27_PAD_LD4), + IMX_PINCTRL_PIN(MX27_PAD_LD5), + IMX_PINCTRL_PIN(MX27_PAD_LD6), + IMX_PINCTRL_PIN(MX27_PAD_LD7), + IMX_PINCTRL_PIN(MX27_PAD_LD8), + IMX_PINCTRL_PIN(MX27_PAD_LD9), + IMX_PINCTRL_PIN(MX27_PAD_LD10), + IMX_PINCTRL_PIN(MX27_PAD_LD11), + IMX_PINCTRL_PIN(MX27_PAD_LD12), + IMX_PINCTRL_PIN(MX27_PAD_LD13), + IMX_PINCTRL_PIN(MX27_PAD_LD14), + IMX_PINCTRL_PIN(MX27_PAD_LD15), + IMX_PINCTRL_PIN(MX27_PAD_LD16), + IMX_PINCTRL_PIN(MX27_PAD_LD17), + IMX_PINCTRL_PIN(MX27_PAD_REV), + IMX_PINCTRL_PIN(MX27_PAD_CLS), + IMX_PINCTRL_PIN(MX27_PAD_PS), + IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR), + IMX_PINCTRL_PIN(MX27_PAD_HSYNC), + IMX_PINCTRL_PIN(MX27_PAD_VSYNC), + IMX_PINCTRL_PIN(MX27_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX27_PAD_OE_ACD), + + IMX_PINCTRL_PIN(MX27_PAD_SD2_D0), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D1), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D2), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D3), + IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D0), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D1), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP), + IMX_PINCTRL_PIN(MX27_PAD_USB_PWR), + IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP), + + IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA), + IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3), + IMX_PINCTRL_PIN(MX27_PAD_TOUT), + IMX_PINCTRL_PIN(MX27_PAD_TIN), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK), + + IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14), + IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA), + IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI), + + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR), + IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX27_PAD_PWMO), + IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS), + IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX27_PAD_RTCK), + IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D0), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D1), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D2), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D3), + IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7), + + IMX_PINCTRL_PIN(MX27_PAD_NFRB), + IMX_PINCTRL_PIN(MX27_PAD_NFCLE), + IMX_PINCTRL_PIN(MX27_PAD_NFWP_B), + IMX_PINCTRL_PIN(MX27_PAD_NFCE_B), + IMX_PINCTRL_PIN(MX27_PAD_NFALE), + IMX_PINCTRL_PIN(MX27_PAD_NFRE_B), + IMX_PINCTRL_PIN(MX27_PAD_NFWE_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_POE), + IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B), + IMX_PINCTRL_PIN(MX27_PAD_IOIS16), + IMX_PINCTRL_PIN(MX27_PAD_PC_RST), + IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2), + IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1), + IMX_PINCTRL_PIN(MX27_PAD_PC_VS2), + IMX_PINCTRL_PIN(MX27_PAD_PC_VS1), + IMX_PINCTRL_PIN(MX27_PAD_CLKO), + IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON), + IMX_PINCTRL_PIN(MX27_PAD_PC_READY), + IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B), + IMX_PINCTRL_PIN(MX27_PAD_CS4_B), + IMX_PINCTRL_PIN(MX27_PAD_CS5_B), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15), +}; + +static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { + .pins = imx27_pinctrl_pads, + .npins = ARRAY_SIZE(imx27_pinctrl_pads), +}; + +static const struct of_device_id imx27_pinctrl_of_match[] = { + { .compatible = "fsl,imx27-iomuxc", }, + { /* sentinel */ } +}; + +static int imx27_pinctrl_probe(struct platform_device *pdev) +{ + return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info); +} + +static struct platform_driver imx27_pinctrl_driver = { + .driver = { + .name = "imx27-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx27_pinctrl_of_match), + }, + .probe = imx27_pinctrl_probe, + .remove = imx1_pinctrl_core_remove, +}; + +static int __init imx27_pinctrl_init(void) +{ + return platform_driver_register(&imx27_pinctrl_driver); +} +arch_initcall(imx27_pinctrl_init); + +static void __exit imx27_pinctrl_exit(void) +{ + platform_driver_unregister(&imx27_pinctrl_driver); +} +module_exit(imx27_pinctrl_exit); +MODULE_AUTHOR("Markus Pargmann "); +MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c new file mode 100644 index 000000000000..3bd45da21229 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx28.c @@ -0,0 +1,421 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include "pinctrl-mxs.h" + +enum imx28_pin_enum { + GPMI_D00 = PINID(0, 0), + GPMI_D01 = PINID(0, 1), + GPMI_D02 = PINID(0, 2), + GPMI_D03 = PINID(0, 3), + GPMI_D04 = PINID(0, 4), + GPMI_D05 = PINID(0, 5), + GPMI_D06 = PINID(0, 6), + GPMI_D07 = PINID(0, 7), + GPMI_CE0N = PINID(0, 16), + GPMI_CE1N = PINID(0, 17), + GPMI_CE2N = PINID(0, 18), + GPMI_CE3N = PINID(0, 19), + GPMI_RDY0 = PINID(0, 20), + GPMI_RDY1 = PINID(0, 21), + GPMI_RDY2 = PINID(0, 22), + GPMI_RDY3 = PINID(0, 23), + GPMI_RDN = PINID(0, 24), + GPMI_WRN = PINID(0, 25), + GPMI_ALE = PINID(0, 26), + GPMI_CLE = PINID(0, 27), + GPMI_RESETN = PINID(0, 28), + LCD_D00 = PINID(1, 0), + LCD_D01 = PINID(1, 1), + LCD_D02 = PINID(1, 2), + LCD_D03 = PINID(1, 3), + LCD_D04 = PINID(1, 4), + LCD_D05 = PINID(1, 5), + LCD_D06 = PINID(1, 6), + LCD_D07 = PINID(1, 7), + LCD_D08 = PINID(1, 8), + LCD_D09 = PINID(1, 9), + LCD_D10 = PINID(1, 10), + LCD_D11 = PINID(1, 11), + LCD_D12 = PINID(1, 12), + LCD_D13 = PINID(1, 13), + LCD_D14 = PINID(1, 14), + LCD_D15 = PINID(1, 15), + LCD_D16 = PINID(1, 16), + LCD_D17 = PINID(1, 17), + LCD_D18 = PINID(1, 18), + LCD_D19 = PINID(1, 19), + LCD_D20 = PINID(1, 20), + LCD_D21 = PINID(1, 21), + LCD_D22 = PINID(1, 22), + LCD_D23 = PINID(1, 23), + LCD_RD_E = PINID(1, 24), + LCD_WR_RWN = PINID(1, 25), + LCD_RS = PINID(1, 26), + LCD_CS = PINID(1, 27), + LCD_VSYNC = PINID(1, 28), + LCD_HSYNC = PINID(1, 29), + LCD_DOTCLK = PINID(1, 30), + LCD_ENABLE = PINID(1, 31), + SSP0_DATA0 = PINID(2, 0), + SSP0_DATA1 = PINID(2, 1), + SSP0_DATA2 = PINID(2, 2), + SSP0_DATA3 = PINID(2, 3), + SSP0_DATA4 = PINID(2, 4), + SSP0_DATA5 = PINID(2, 5), + SSP0_DATA6 = PINID(2, 6), + SSP0_DATA7 = PINID(2, 7), + SSP0_CMD = PINID(2, 8), + SSP0_DETECT = PINID(2, 9), + SSP0_SCK = PINID(2, 10), + SSP1_SCK = PINID(2, 12), + SSP1_CMD = PINID(2, 13), + SSP1_DATA0 = PINID(2, 14), + SSP1_DATA3 = PINID(2, 15), + SSP2_SCK = PINID(2, 16), + SSP2_MOSI = PINID(2, 17), + SSP2_MISO = PINID(2, 18), + SSP2_SS0 = PINID(2, 19), + SSP2_SS1 = PINID(2, 20), + SSP2_SS2 = PINID(2, 21), + SSP3_SCK = PINID(2, 24), + SSP3_MOSI = PINID(2, 25), + SSP3_MISO = PINID(2, 26), + SSP3_SS0 = PINID(2, 27), + AUART0_RX = PINID(3, 0), + AUART0_TX = PINID(3, 1), + AUART0_CTS = PINID(3, 2), + AUART0_RTS = PINID(3, 3), + AUART1_RX = PINID(3, 4), + AUART1_TX = PINID(3, 5), + AUART1_CTS = PINID(3, 6), + AUART1_RTS = PINID(3, 7), + AUART2_RX = PINID(3, 8), + AUART2_TX = PINID(3, 9), + AUART2_CTS = PINID(3, 10), + AUART2_RTS = PINID(3, 11), + AUART3_RX = PINID(3, 12), + AUART3_TX = PINID(3, 13), + AUART3_CTS = PINID(3, 14), + AUART3_RTS = PINID(3, 15), + PWM0 = PINID(3, 16), + PWM1 = PINID(3, 17), + PWM2 = PINID(3, 18), + SAIF0_MCLK = PINID(3, 20), + SAIF0_LRCLK = PINID(3, 21), + SAIF0_BITCLK = PINID(3, 22), + SAIF0_SDATA0 = PINID(3, 23), + I2C0_SCL = PINID(3, 24), + I2C0_SDA = PINID(3, 25), + SAIF1_SDATA0 = PINID(3, 26), + SPDIF = PINID(3, 27), + PWM3 = PINID(3, 28), + PWM4 = PINID(3, 29), + LCD_RESET = PINID(3, 30), + ENET0_MDC = PINID(4, 0), + ENET0_MDIO = PINID(4, 1), + ENET0_RX_EN = PINID(4, 2), + ENET0_RXD0 = PINID(4, 3), + ENET0_RXD1 = PINID(4, 4), + ENET0_TX_CLK = PINID(4, 5), + ENET0_TX_EN = PINID(4, 6), + ENET0_TXD0 = PINID(4, 7), + ENET0_TXD1 = PINID(4, 8), + ENET0_RXD2 = PINID(4, 9), + ENET0_RXD3 = PINID(4, 10), + ENET0_TXD2 = PINID(4, 11), + ENET0_TXD3 = PINID(4, 12), + ENET0_RX_CLK = PINID(4, 13), + ENET0_COL = PINID(4, 14), + ENET0_CRS = PINID(4, 15), + ENET_CLK = PINID(4, 16), + JTAG_RTCK = PINID(4, 20), + EMI_D00 = PINID(5, 0), + EMI_D01 = PINID(5, 1), + EMI_D02 = PINID(5, 2), + EMI_D03 = PINID(5, 3), + EMI_D04 = PINID(5, 4), + EMI_D05 = PINID(5, 5), + EMI_D06 = PINID(5, 6), + EMI_D07 = PINID(5, 7), + EMI_D08 = PINID(5, 8), + EMI_D09 = PINID(5, 9), + EMI_D10 = PINID(5, 10), + EMI_D11 = PINID(5, 11), + EMI_D12 = PINID(5, 12), + EMI_D13 = PINID(5, 13), + EMI_D14 = PINID(5, 14), + EMI_D15 = PINID(5, 15), + EMI_ODT0 = PINID(5, 16), + EMI_DQM0 = PINID(5, 17), + EMI_ODT1 = PINID(5, 18), + EMI_DQM1 = PINID(5, 19), + EMI_DDR_OPEN_FB = PINID(5, 20), + EMI_CLK = PINID(5, 21), + EMI_DQS0 = PINID(5, 22), + EMI_DQS1 = PINID(5, 23), + EMI_DDR_OPEN = PINID(5, 26), + EMI_A00 = PINID(6, 0), + EMI_A01 = PINID(6, 1), + EMI_A02 = PINID(6, 2), + EMI_A03 = PINID(6, 3), + EMI_A04 = PINID(6, 4), + EMI_A05 = PINID(6, 5), + EMI_A06 = PINID(6, 6), + EMI_A07 = PINID(6, 7), + EMI_A08 = PINID(6, 8), + EMI_A09 = PINID(6, 9), + EMI_A10 = PINID(6, 10), + EMI_A11 = PINID(6, 11), + EMI_A12 = PINID(6, 12), + EMI_A13 = PINID(6, 13), + EMI_A14 = PINID(6, 14), + EMI_BA0 = PINID(6, 16), + EMI_BA1 = PINID(6, 17), + EMI_BA2 = PINID(6, 18), + EMI_CASN = PINID(6, 19), + EMI_RASN = PINID(6, 20), + EMI_WEN = PINID(6, 21), + EMI_CE0N = PINID(6, 22), + EMI_CE1N = PINID(6, 23), + EMI_CKE = PINID(6, 24), +}; + +static const struct pinctrl_pin_desc imx28_pins[] = { + MXS_PINCTRL_PIN(GPMI_D00), + MXS_PINCTRL_PIN(GPMI_D01), + MXS_PINCTRL_PIN(GPMI_D02), + MXS_PINCTRL_PIN(GPMI_D03), + MXS_PINCTRL_PIN(GPMI_D04), + MXS_PINCTRL_PIN(GPMI_D05), + MXS_PINCTRL_PIN(GPMI_D06), + MXS_PINCTRL_PIN(GPMI_D07), + MXS_PINCTRL_PIN(GPMI_CE0N), + MXS_PINCTRL_PIN(GPMI_CE1N), + MXS_PINCTRL_PIN(GPMI_CE2N), + MXS_PINCTRL_PIN(GPMI_CE3N), + MXS_PINCTRL_PIN(GPMI_RDY0), + MXS_PINCTRL_PIN(GPMI_RDY1), + MXS_PINCTRL_PIN(GPMI_RDY2), + MXS_PINCTRL_PIN(GPMI_RDY3), + MXS_PINCTRL_PIN(GPMI_RDN), + MXS_PINCTRL_PIN(GPMI_WRN), + MXS_PINCTRL_PIN(GPMI_ALE), + MXS_PINCTRL_PIN(GPMI_CLE), + MXS_PINCTRL_PIN(GPMI_RESETN), + MXS_PINCTRL_PIN(LCD_D00), + MXS_PINCTRL_PIN(LCD_D01), + MXS_PINCTRL_PIN(LCD_D02), + MXS_PINCTRL_PIN(LCD_D03), + MXS_PINCTRL_PIN(LCD_D04), + MXS_PINCTRL_PIN(LCD_D05), + MXS_PINCTRL_PIN(LCD_D06), + MXS_PINCTRL_PIN(LCD_D07), + MXS_PINCTRL_PIN(LCD_D08), + MXS_PINCTRL_PIN(LCD_D09), + MXS_PINCTRL_PIN(LCD_D10), + MXS_PINCTRL_PIN(LCD_D11), + MXS_PINCTRL_PIN(LCD_D12), + MXS_PINCTRL_PIN(LCD_D13), + MXS_PINCTRL_PIN(LCD_D14), + MXS_PINCTRL_PIN(LCD_D15), + MXS_PINCTRL_PIN(LCD_D16), + MXS_PINCTRL_PIN(LCD_D17), + MXS_PINCTRL_PIN(LCD_D18), + MXS_PINCTRL_PIN(LCD_D19), + MXS_PINCTRL_PIN(LCD_D20), + MXS_PINCTRL_PIN(LCD_D21), + MXS_PINCTRL_PIN(LCD_D22), + MXS_PINCTRL_PIN(LCD_D23), + MXS_PINCTRL_PIN(LCD_RD_E), + MXS_PINCTRL_PIN(LCD_WR_RWN), + MXS_PINCTRL_PIN(LCD_RS), + MXS_PINCTRL_PIN(LCD_CS), + MXS_PINCTRL_PIN(LCD_VSYNC), + MXS_PINCTRL_PIN(LCD_HSYNC), + MXS_PINCTRL_PIN(LCD_DOTCLK), + MXS_PINCTRL_PIN(LCD_ENABLE), + MXS_PINCTRL_PIN(SSP0_DATA0), + MXS_PINCTRL_PIN(SSP0_DATA1), + MXS_PINCTRL_PIN(SSP0_DATA2), + MXS_PINCTRL_PIN(SSP0_DATA3), + MXS_PINCTRL_PIN(SSP0_DATA4), + MXS_PINCTRL_PIN(SSP0_DATA5), + MXS_PINCTRL_PIN(SSP0_DATA6), + MXS_PINCTRL_PIN(SSP0_DATA7), + MXS_PINCTRL_PIN(SSP0_CMD), + MXS_PINCTRL_PIN(SSP0_DETECT), + MXS_PINCTRL_PIN(SSP0_SCK), + MXS_PINCTRL_PIN(SSP1_SCK), + MXS_PINCTRL_PIN(SSP1_CMD), + MXS_PINCTRL_PIN(SSP1_DATA0), + MXS_PINCTRL_PIN(SSP1_DATA3), + MXS_PINCTRL_PIN(SSP2_SCK), + MXS_PINCTRL_PIN(SSP2_MOSI), + MXS_PINCTRL_PIN(SSP2_MISO), + MXS_PINCTRL_PIN(SSP2_SS0), + MXS_PINCTRL_PIN(SSP2_SS1), + MXS_PINCTRL_PIN(SSP2_SS2), + MXS_PINCTRL_PIN(SSP3_SCK), + MXS_PINCTRL_PIN(SSP3_MOSI), + MXS_PINCTRL_PIN(SSP3_MISO), + MXS_PINCTRL_PIN(SSP3_SS0), + MXS_PINCTRL_PIN(AUART0_RX), + MXS_PINCTRL_PIN(AUART0_TX), + MXS_PINCTRL_PIN(AUART0_CTS), + MXS_PINCTRL_PIN(AUART0_RTS), + MXS_PINCTRL_PIN(AUART1_RX), + MXS_PINCTRL_PIN(AUART1_TX), + MXS_PINCTRL_PIN(AUART1_CTS), + MXS_PINCTRL_PIN(AUART1_RTS), + MXS_PINCTRL_PIN(AUART2_RX), + MXS_PINCTRL_PIN(AUART2_TX), + MXS_PINCTRL_PIN(AUART2_CTS), + MXS_PINCTRL_PIN(AUART2_RTS), + MXS_PINCTRL_PIN(AUART3_RX), + MXS_PINCTRL_PIN(AUART3_TX), + MXS_PINCTRL_PIN(AUART3_CTS), + MXS_PINCTRL_PIN(AUART3_RTS), + MXS_PINCTRL_PIN(PWM0), + MXS_PINCTRL_PIN(PWM1), + MXS_PINCTRL_PIN(PWM2), + MXS_PINCTRL_PIN(SAIF0_MCLK), + MXS_PINCTRL_PIN(SAIF0_LRCLK), + MXS_PINCTRL_PIN(SAIF0_BITCLK), + MXS_PINCTRL_PIN(SAIF0_SDATA0), + MXS_PINCTRL_PIN(I2C0_SCL), + MXS_PINCTRL_PIN(I2C0_SDA), + MXS_PINCTRL_PIN(SAIF1_SDATA0), + MXS_PINCTRL_PIN(SPDIF), + MXS_PINCTRL_PIN(PWM3), + MXS_PINCTRL_PIN(PWM4), + MXS_PINCTRL_PIN(LCD_RESET), + MXS_PINCTRL_PIN(ENET0_MDC), + MXS_PINCTRL_PIN(ENET0_MDIO), + MXS_PINCTRL_PIN(ENET0_RX_EN), + MXS_PINCTRL_PIN(ENET0_RXD0), + MXS_PINCTRL_PIN(ENET0_RXD1), + MXS_PINCTRL_PIN(ENET0_TX_CLK), + MXS_PINCTRL_PIN(ENET0_TX_EN), + MXS_PINCTRL_PIN(ENET0_TXD0), + MXS_PINCTRL_PIN(ENET0_TXD1), + MXS_PINCTRL_PIN(ENET0_RXD2), + MXS_PINCTRL_PIN(ENET0_RXD3), + MXS_PINCTRL_PIN(ENET0_TXD2), + MXS_PINCTRL_PIN(ENET0_TXD3), + MXS_PINCTRL_PIN(ENET0_RX_CLK), + MXS_PINCTRL_PIN(ENET0_COL), + MXS_PINCTRL_PIN(ENET0_CRS), + MXS_PINCTRL_PIN(ENET_CLK), + MXS_PINCTRL_PIN(JTAG_RTCK), + MXS_PINCTRL_PIN(EMI_D00), + MXS_PINCTRL_PIN(EMI_D01), + MXS_PINCTRL_PIN(EMI_D02), + MXS_PINCTRL_PIN(EMI_D03), + MXS_PINCTRL_PIN(EMI_D04), + MXS_PINCTRL_PIN(EMI_D05), + MXS_PINCTRL_PIN(EMI_D06), + MXS_PINCTRL_PIN(EMI_D07), + MXS_PINCTRL_PIN(EMI_D08), + MXS_PINCTRL_PIN(EMI_D09), + MXS_PINCTRL_PIN(EMI_D10), + MXS_PINCTRL_PIN(EMI_D11), + MXS_PINCTRL_PIN(EMI_D12), + MXS_PINCTRL_PIN(EMI_D13), + MXS_PINCTRL_PIN(EMI_D14), + MXS_PINCTRL_PIN(EMI_D15), + MXS_PINCTRL_PIN(EMI_ODT0), + MXS_PINCTRL_PIN(EMI_DQM0), + MXS_PINCTRL_PIN(EMI_ODT1), + MXS_PINCTRL_PIN(EMI_DQM1), + MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB), + MXS_PINCTRL_PIN(EMI_CLK), + MXS_PINCTRL_PIN(EMI_DQS0), + MXS_PINCTRL_PIN(EMI_DQS1), + MXS_PINCTRL_PIN(EMI_DDR_OPEN), + MXS_PINCTRL_PIN(EMI_A00), + MXS_PINCTRL_PIN(EMI_A01), + MXS_PINCTRL_PIN(EMI_A02), + MXS_PINCTRL_PIN(EMI_A03), + MXS_PINCTRL_PIN(EMI_A04), + MXS_PINCTRL_PIN(EMI_A05), + MXS_PINCTRL_PIN(EMI_A06), + MXS_PINCTRL_PIN(EMI_A07), + MXS_PINCTRL_PIN(EMI_A08), + MXS_PINCTRL_PIN(EMI_A09), + MXS_PINCTRL_PIN(EMI_A10), + MXS_PINCTRL_PIN(EMI_A11), + MXS_PINCTRL_PIN(EMI_A12), + MXS_PINCTRL_PIN(EMI_A13), + MXS_PINCTRL_PIN(EMI_A14), + MXS_PINCTRL_PIN(EMI_BA0), + MXS_PINCTRL_PIN(EMI_BA1), + MXS_PINCTRL_PIN(EMI_BA2), + MXS_PINCTRL_PIN(EMI_CASN), + MXS_PINCTRL_PIN(EMI_RASN), + MXS_PINCTRL_PIN(EMI_WEN), + MXS_PINCTRL_PIN(EMI_CE0N), + MXS_PINCTRL_PIN(EMI_CE1N), + MXS_PINCTRL_PIN(EMI_CKE), +}; + +static struct mxs_regs imx28_regs = { + .muxsel = 0x100, + .drive = 0x300, + .pull = 0x600, +}; + +static struct mxs_pinctrl_soc_data imx28_pinctrl_data = { + .regs = &imx28_regs, + .pins = imx28_pins, + .npins = ARRAY_SIZE(imx28_pins), +}; + +static int imx28_pinctrl_probe(struct platform_device *pdev) +{ + return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data); +} + +static const struct of_device_id imx28_pinctrl_of_match[] = { + { .compatible = "fsl,imx28-pinctrl", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match); + +static struct platform_driver imx28_pinctrl_driver = { + .driver = { + .name = "imx28-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx28_pinctrl_of_match, + }, + .probe = imx28_pinctrl_probe, + .remove = mxs_pinctrl_remove, +}; + +static int __init imx28_pinctrl_init(void) +{ + return platform_driver_register(&imx28_pinctrl_driver); +} +postcore_initcall(imx28_pinctrl_init); + +static void __exit imx28_pinctrl_exit(void) +{ + platform_driver_unregister(&imx28_pinctrl_driver); +} +module_exit(imx28_pinctrl_exit); + +MODULE_AUTHOR("Shawn Guo "); +MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c new file mode 100644 index 000000000000..6bfbcd0112c1 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx35.c @@ -0,0 +1,1041 @@ +/* + * imx35 pinctrl driver. + * + * This driver was mostly copied from the imx51 pinctrl driver which has: + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro, Inc. + * + * Author: Dong Aisheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx35_pads { + MX35_PAD_RESERVE0 = 0, + MX35_PAD_CAPTURE = 1, + MX35_PAD_COMPARE = 2, + MX35_PAD_WDOG_RST = 3, + MX35_PAD_GPIO1_0 = 4, + MX35_PAD_GPIO1_1 = 5, + MX35_PAD_GPIO2_0 = 6, + MX35_PAD_GPIO3_0 = 7, + MX35_PAD_CLKO = 8, + MX35_PAD_VSTBY = 9, + MX35_PAD_A0 = 10, + MX35_PAD_A1 = 11, + MX35_PAD_A2 = 12, + MX35_PAD_A3 = 13, + MX35_PAD_A4 = 14, + MX35_PAD_A5 = 15, + MX35_PAD_A6 = 16, + MX35_PAD_A7 = 17, + MX35_PAD_A8 = 18, + MX35_PAD_A9 = 19, + MX35_PAD_A10 = 20, + MX35_PAD_MA10 = 21, + MX35_PAD_A11 = 22, + MX35_PAD_A12 = 23, + MX35_PAD_A13 = 24, + MX35_PAD_A14 = 25, + MX35_PAD_A15 = 26, + MX35_PAD_A16 = 27, + MX35_PAD_A17 = 28, + MX35_PAD_A18 = 29, + MX35_PAD_A19 = 30, + MX35_PAD_A20 = 31, + MX35_PAD_A21 = 32, + MX35_PAD_A22 = 33, + MX35_PAD_A23 = 34, + MX35_PAD_A24 = 35, + MX35_PAD_A25 = 36, + MX35_PAD_EB0 = 37, + MX35_PAD_EB1 = 38, + MX35_PAD_OE = 39, + MX35_PAD_CS0 = 40, + MX35_PAD_CS1 = 41, + MX35_PAD_CS2 = 42, + MX35_PAD_CS3 = 43, + MX35_PAD_CS4 = 44, + MX35_PAD_CS5 = 45, + MX35_PAD_NF_CE0 = 46, + MX35_PAD_LBA = 47, + MX35_PAD_BCLK = 48, + MX35_PAD_RW = 49, + MX35_PAD_NFWE_B = 50, + MX35_PAD_NFRE_B = 51, + MX35_PAD_NFALE = 52, + MX35_PAD_NFCLE = 53, + MX35_PAD_NFWP_B = 54, + MX35_PAD_NFRB = 55, + MX35_PAD_CSI_D8 = 56, + MX35_PAD_CSI_D9 = 57, + MX35_PAD_CSI_D10 = 58, + MX35_PAD_CSI_D11 = 59, + MX35_PAD_CSI_D12 = 60, + MX35_PAD_CSI_D13 = 61, + MX35_PAD_CSI_D14 = 62, + MX35_PAD_CSI_D15 = 63, + MX35_PAD_CSI_MCLK = 64, + MX35_PAD_CSI_VSYNC = 65, + MX35_PAD_CSI_HSYNC = 66, + MX35_PAD_CSI_PIXCLK = 67, + MX35_PAD_I2C1_CLK = 68, + MX35_PAD_I2C1_DAT = 69, + MX35_PAD_I2C2_CLK = 70, + MX35_PAD_I2C2_DAT = 71, + MX35_PAD_STXD4 = 72, + MX35_PAD_SRXD4 = 73, + MX35_PAD_SCK4 = 74, + MX35_PAD_STXFS4 = 75, + MX35_PAD_STXD5 = 76, + MX35_PAD_SRXD5 = 77, + MX35_PAD_SCK5 = 78, + MX35_PAD_STXFS5 = 79, + MX35_PAD_SCKR = 80, + MX35_PAD_FSR = 81, + MX35_PAD_HCKR = 82, + MX35_PAD_SCKT = 83, + MX35_PAD_FST = 84, + MX35_PAD_HCKT = 85, + MX35_PAD_TX5_RX0 = 86, + MX35_PAD_TX4_RX1 = 87, + MX35_PAD_TX3_RX2 = 88, + MX35_PAD_TX2_RX3 = 89, + MX35_PAD_TX1 = 90, + MX35_PAD_TX0 = 91, + MX35_PAD_CSPI1_MOSI = 92, + MX35_PAD_CSPI1_MISO = 93, + MX35_PAD_CSPI1_SS0 = 94, + MX35_PAD_CSPI1_SS1 = 95, + MX35_PAD_CSPI1_SCLK = 96, + MX35_PAD_CSPI1_SPI_RDY = 97, + MX35_PAD_RXD1 = 98, + MX35_PAD_TXD1 = 99, + MX35_PAD_RTS1 = 100, + MX35_PAD_CTS1 = 101, + MX35_PAD_RXD2 = 102, + MX35_PAD_TXD2 = 103, + MX35_PAD_RTS2 = 104, + MX35_PAD_CTS2 = 105, + MX35_PAD_USBOTG_PWR = 106, + MX35_PAD_USBOTG_OC = 107, + MX35_PAD_LD0 = 108, + MX35_PAD_LD1 = 109, + MX35_PAD_LD2 = 110, + MX35_PAD_LD3 = 111, + MX35_PAD_LD4 = 112, + MX35_PAD_LD5 = 113, + MX35_PAD_LD6 = 114, + MX35_PAD_LD7 = 115, + MX35_PAD_LD8 = 116, + MX35_PAD_LD9 = 117, + MX35_PAD_LD10 = 118, + MX35_PAD_LD11 = 119, + MX35_PAD_LD12 = 120, + MX35_PAD_LD13 = 121, + MX35_PAD_LD14 = 122, + MX35_PAD_LD15 = 123, + MX35_PAD_LD16 = 124, + MX35_PAD_LD17 = 125, + MX35_PAD_LD18 = 126, + MX35_PAD_LD19 = 127, + MX35_PAD_LD20 = 128, + MX35_PAD_LD21 = 129, + MX35_PAD_LD22 = 130, + MX35_PAD_LD23 = 131, + MX35_PAD_D3_HSYNC = 132, + MX35_PAD_D3_FPSHIFT = 133, + MX35_PAD_D3_DRDY = 134, + MX35_PAD_CONTRAST = 135, + MX35_PAD_D3_VSYNC = 136, + MX35_PAD_D3_REV = 137, + MX35_PAD_D3_CLS = 138, + MX35_PAD_D3_SPL = 139, + MX35_PAD_SD1_CMD = 140, + MX35_PAD_SD1_CLK = 141, + MX35_PAD_SD1_DATA0 = 142, + MX35_PAD_SD1_DATA1 = 143, + MX35_PAD_SD1_DATA2 = 144, + MX35_PAD_SD1_DATA3 = 145, + MX35_PAD_SD2_CMD = 146, + MX35_PAD_SD2_CLK = 147, + MX35_PAD_SD2_DATA0 = 148, + MX35_PAD_SD2_DATA1 = 149, + MX35_PAD_SD2_DATA2 = 150, + MX35_PAD_SD2_DATA3 = 151, + MX35_PAD_ATA_CS0 = 152, + MX35_PAD_ATA_CS1 = 153, + MX35_PAD_ATA_DIOR = 154, + MX35_PAD_ATA_DIOW = 155, + MX35_PAD_ATA_DMACK = 156, + MX35_PAD_ATA_RESET_B = 157, + MX35_PAD_ATA_IORDY = 158, + MX35_PAD_ATA_DATA0 = 159, + MX35_PAD_ATA_DATA1 = 160, + MX35_PAD_ATA_DATA2 = 161, + MX35_PAD_ATA_DATA3 = 162, + MX35_PAD_ATA_DATA4 = 163, + MX35_PAD_ATA_DATA5 = 164, + MX35_PAD_ATA_DATA6 = 165, + MX35_PAD_ATA_DATA7 = 166, + MX35_PAD_ATA_DATA8 = 167, + MX35_PAD_ATA_DATA9 = 168, + MX35_PAD_ATA_DATA10 = 169, + MX35_PAD_ATA_DATA11 = 170, + MX35_PAD_ATA_DATA12 = 171, + MX35_PAD_ATA_DATA13 = 172, + MX35_PAD_ATA_DATA14 = 173, + MX35_PAD_ATA_DATA15 = 174, + MX35_PAD_ATA_INTRQ = 175, + MX35_PAD_ATA_BUFF_EN = 176, + MX35_PAD_ATA_DMARQ = 177, + MX35_PAD_ATA_DA0 = 178, + MX35_PAD_ATA_DA1 = 179, + MX35_PAD_ATA_DA2 = 180, + MX35_PAD_MLB_CLK = 181, + MX35_PAD_MLB_DAT = 182, + MX35_PAD_MLB_SIG = 183, + MX35_PAD_FEC_TX_CLK = 184, + MX35_PAD_FEC_RX_CLK = 185, + MX35_PAD_FEC_RX_DV = 186, + MX35_PAD_FEC_COL = 187, + MX35_PAD_FEC_RDATA0 = 188, + MX35_PAD_FEC_TDATA0 = 189, + MX35_PAD_FEC_TX_EN = 190, + MX35_PAD_FEC_MDC = 191, + MX35_PAD_FEC_MDIO = 192, + MX35_PAD_FEC_TX_ERR = 193, + MX35_PAD_FEC_RX_ERR = 194, + MX35_PAD_FEC_CRS = 195, + MX35_PAD_FEC_RDATA1 = 196, + MX35_PAD_FEC_TDATA1 = 197, + MX35_PAD_FEC_RDATA2 = 198, + MX35_PAD_FEC_TDATA2 = 199, + MX35_PAD_FEC_RDATA3 = 200, + MX35_PAD_FEC_TDATA3 = 201, + MX35_PAD_RESERVE1 = 202, + MX35_PAD_RESERVE2 = 203, + MX35_PAD_RESERVE3 = 204, + MX35_PAD_RESERVE4 = 205, + MX35_PAD_RESERVE5 = 206, + MX35_PAD_RESERVE6 = 207, + MX35_PAD_RESERVE7 = 208, + MX35_PAD_RESET_IN_B = 209, + MX35_PAD_POR_B = 210, + MX35_PAD_RESERVE8 = 211, + MX35_PAD_BOOT_MODE0 = 212, + MX35_PAD_BOOT_MODE1 = 213, + MX35_PAD_CLK_MODE0 = 214, + MX35_PAD_CLK_MODE1 = 215, + MX35_PAD_POWER_FAIL = 216, + MX35_PAD_RESERVE9 = 217, + MX35_PAD_RESERVE10 = 218, + MX35_PAD_RESERVE11 = 219, + MX35_PAD_RESERVE12 = 220, + MX35_PAD_RESERVE13 = 221, + MX35_PAD_RESERVE14 = 222, + MX35_PAD_RESERVE15 = 223, + MX35_PAD_RESERVE16 = 224, + MX35_PAD_RESERVE17 = 225, + MX35_PAD_RESERVE18 = 226, + MX35_PAD_RESERVE19 = 227, + MX35_PAD_RESERVE20 = 228, + MX35_PAD_RESERVE21 = 229, + MX35_PAD_RESERVE22 = 230, + MX35_PAD_RESERVE23 = 231, + MX35_PAD_RESERVE24 = 232, + MX35_PAD_RESERVE25 = 233, + MX35_PAD_RESERVE26 = 234, + MX35_PAD_RESERVE27 = 235, + MX35_PAD_RESERVE28 = 236, + MX35_PAD_RESERVE29 = 237, + MX35_PAD_RESERVE30 = 238, + MX35_PAD_RESERVE31 = 239, + MX35_PAD_RESERVE32 = 240, + MX35_PAD_RESERVE33 = 241, + MX35_PAD_RESERVE34 = 242, + MX35_PAD_RESERVE35 = 243, + MX35_PAD_RESERVE36 = 244, + MX35_PAD_SDBA1 = 245, + MX35_PAD_SDBA0 = 246, + MX35_PAD_SD0 = 247, + MX35_PAD_SD1 = 248, + MX35_PAD_SD2 = 249, + MX35_PAD_SD3 = 250, + MX35_PAD_SD4 = 251, + MX35_PAD_SD5 = 252, + MX35_PAD_SD6 = 253, + MX35_PAD_SD7 = 254, + MX35_PAD_SD8 = 255, + MX35_PAD_SD9 = 256, + MX35_PAD_SD10 = 257, + MX35_PAD_SD11 = 258, + MX35_PAD_SD12 = 259, + MX35_PAD_SD13 = 260, + MX35_PAD_SD14 = 261, + MX35_PAD_SD15 = 262, + MX35_PAD_SD16 = 263, + MX35_PAD_SD17 = 264, + MX35_PAD_SD18 = 265, + MX35_PAD_SD19 = 266, + MX35_PAD_SD20 = 267, + MX35_PAD_SD21 = 268, + MX35_PAD_SD22 = 269, + MX35_PAD_SD23 = 270, + MX35_PAD_SD24 = 271, + MX35_PAD_SD25 = 272, + MX35_PAD_SD26 = 273, + MX35_PAD_SD27 = 274, + MX35_PAD_SD28 = 275, + MX35_PAD_SD29 = 276, + MX35_PAD_SD30 = 277, + MX35_PAD_SD31 = 278, + MX35_PAD_DQM0 = 279, + MX35_PAD_DQM1 = 280, + MX35_PAD_DQM2 = 281, + MX35_PAD_DQM3 = 282, + MX35_PAD_RESERVE37 = 283, + MX35_PAD_RESERVE38 = 284, + MX35_PAD_RESERVE39 = 285, + MX35_PAD_RESERVE40 = 286, + MX35_PAD_RESERVE41 = 287, + MX35_PAD_RESERVE42 = 288, + MX35_PAD_RESERVE43 = 289, + MX35_PAD_RESERVE44 = 290, + MX35_PAD_RESERVE45 = 291, + MX35_PAD_RESERVE46 = 292, + MX35_PAD_ECB = 293, + MX35_PAD_RESERVE47 = 294, + MX35_PAD_RESERVE48 = 295, + MX35_PAD_RESERVE49 = 296, + MX35_PAD_RAS = 297, + MX35_PAD_CAS = 298, + MX35_PAD_SDWE = 299, + MX35_PAD_SDCKE0 = 300, + MX35_PAD_SDCKE1 = 301, + MX35_PAD_SDCLK = 302, + MX35_PAD_SDQS0 = 303, + MX35_PAD_SDQS1 = 304, + MX35_PAD_SDQS2 = 305, + MX35_PAD_SDQS3 = 306, + MX35_PAD_RESERVE50 = 307, + MX35_PAD_RESERVE51 = 308, + MX35_PAD_RESERVE52 = 309, + MX35_PAD_RESERVE53 = 310, + MX35_PAD_RESERVE54 = 311, + MX35_PAD_RESERVE55 = 312, + MX35_PAD_D15 = 313, + MX35_PAD_D14 = 314, + MX35_PAD_D13 = 315, + MX35_PAD_D12 = 316, + MX35_PAD_D11 = 317, + MX35_PAD_D10 = 318, + MX35_PAD_D9 = 319, + MX35_PAD_D8 = 320, + MX35_PAD_D7 = 321, + MX35_PAD_D6 = 322, + MX35_PAD_D5 = 323, + MX35_PAD_D4 = 324, + MX35_PAD_D3 = 325, + MX35_PAD_D2 = 326, + MX35_PAD_D1 = 327, + MX35_PAD_D0 = 328, + MX35_PAD_RESERVE56 = 329, + MX35_PAD_RESERVE57 = 330, + MX35_PAD_RESERVE58 = 331, + MX35_PAD_RESERVE59 = 332, + MX35_PAD_RESERVE60 = 333, + MX35_PAD_RESERVE61 = 334, + MX35_PAD_RESERVE62 = 335, + MX35_PAD_RESERVE63 = 336, + MX35_PAD_RESERVE64 = 337, + MX35_PAD_RESERVE65 = 338, + MX35_PAD_RESERVE66 = 339, + MX35_PAD_RESERVE67 = 340, + MX35_PAD_RESERVE68 = 341, + MX35_PAD_RESERVE69 = 342, + MX35_PAD_RESERVE70 = 343, + MX35_PAD_RESERVE71 = 344, + MX35_PAD_RESERVE72 = 345, + MX35_PAD_RESERVE73 = 346, + MX35_PAD_RESERVE74 = 347, + MX35_PAD_RESERVE75 = 348, + MX35_PAD_RESERVE76 = 349, + MX35_PAD_RESERVE77 = 350, + MX35_PAD_RESERVE78 = 351, + MX35_PAD_RESERVE79 = 352, + MX35_PAD_RESERVE80 = 353, + MX35_PAD_RESERVE81 = 354, + MX35_PAD_RESERVE82 = 355, + MX35_PAD_RESERVE83 = 356, + MX35_PAD_RESERVE84 = 357, + MX35_PAD_RESERVE85 = 358, + MX35_PAD_RESERVE86 = 359, + MX35_PAD_RESERVE87 = 360, + MX35_PAD_RESERVE88 = 361, + MX35_PAD_RESERVE89 = 362, + MX35_PAD_RESERVE90 = 363, + MX35_PAD_RESERVE91 = 364, + MX35_PAD_RESERVE92 = 365, + MX35_PAD_RESERVE93 = 366, + MX35_PAD_RESERVE94 = 367, + MX35_PAD_RESERVE95 = 368, + MX35_PAD_RESERVE96 = 369, + MX35_PAD_RESERVE97 = 370, + MX35_PAD_RESERVE98 = 371, + MX35_PAD_RESERVE99 = 372, + MX35_PAD_RESERVE100 = 373, + MX35_PAD_RESERVE101 = 374, + MX35_PAD_RESERVE102 = 375, + MX35_PAD_RESERVE103 = 376, + MX35_PAD_RESERVE104 = 377, + MX35_PAD_RESERVE105 = 378, + MX35_PAD_RTCK = 379, + MX35_PAD_TCK = 380, + MX35_PAD_TMS = 381, + MX35_PAD_TDI = 382, + MX35_PAD_TDO = 383, + MX35_PAD_TRSTB = 384, + MX35_PAD_DE_B = 385, + MX35_PAD_SJC_MOD = 386, + MX35_PAD_RESERVE106 = 387, + MX35_PAD_RESERVE107 = 388, + MX35_PAD_RESERVE108 = 389, + MX35_PAD_RESERVE109 = 390, + MX35_PAD_RESERVE110 = 391, + MX35_PAD_RESERVE111 = 392, + MX35_PAD_RESERVE112 = 393, + MX35_PAD_RESERVE113 = 394, + MX35_PAD_RESERVE114 = 395, + MX35_PAD_RESERVE115 = 396, + MX35_PAD_RESERVE116 = 397, + MX35_PAD_RESERVE117 = 398, + MX35_PAD_RESERVE118 = 399, + MX35_PAD_RESERVE119 = 400, + MX35_PAD_RESERVE120 = 401, + MX35_PAD_RESERVE121 = 402, + MX35_PAD_RESERVE122 = 403, + MX35_PAD_RESERVE123 = 404, + MX35_PAD_RESERVE124 = 405, + MX35_PAD_RESERVE125 = 406, + MX35_PAD_RESERVE126 = 407, + MX35_PAD_RESERVE127 = 408, + MX35_PAD_RESERVE128 = 409, + MX35_PAD_RESERVE129 = 410, + MX35_PAD_RESERVE130 = 411, + MX35_PAD_RESERVE131 = 412, + MX35_PAD_RESERVE132 = 413, + MX35_PAD_RESERVE133 = 414, + MX35_PAD_RESERVE134 = 415, + MX35_PAD_RESERVE135 = 416, + MX35_PAD_RESERVE136 = 417, + MX35_PAD_RESERVE137 = 418, + MX35_PAD_RESERVE138 = 419, + MX35_PAD_RESERVE139 = 420, + MX35_PAD_RESERVE140 = 421, + MX35_PAD_RESERVE141 = 422, + MX35_PAD_RESERVE142 = 423, + MX35_PAD_RESERVE143 = 424, + MX35_PAD_RESERVE144 = 425, + MX35_PAD_RESERVE145 = 426, + MX35_PAD_RESERVE146 = 427, + MX35_PAD_RESERVE147 = 428, + MX35_PAD_RESERVE148 = 429, + MX35_PAD_RESERVE149 = 430, + MX35_PAD_RESERVE150 = 431, + MX35_PAD_RESERVE151 = 432, + MX35_PAD_RESERVE152 = 433, + MX35_PAD_RESERVE153 = 434, + MX35_PAD_RESERVE154 = 435, + MX35_PAD_RESERVE155 = 436, + MX35_PAD_RESERVE156 = 437, + MX35_PAD_RESERVE157 = 438, + MX35_PAD_RESERVE158 = 439, + MX35_PAD_RESERVE159 = 440, + MX35_PAD_RESERVE160 = 441, + MX35_PAD_RESERVE161 = 442, + MX35_PAD_RESERVE162 = 443, + MX35_PAD_RESERVE163 = 444, + MX35_PAD_RESERVE164 = 445, + MX35_PAD_RESERVE165 = 446, + MX35_PAD_RESERVE166 = 447, + MX35_PAD_RESERVE167 = 448, + MX35_PAD_RESERVE168 = 449, + MX35_PAD_RESERVE169 = 450, + MX35_PAD_RESERVE170 = 451, + MX35_PAD_RESERVE171 = 452, + MX35_PAD_RESERVE172 = 453, + MX35_PAD_RESERVE173 = 454, + MX35_PAD_RESERVE174 = 455, + MX35_PAD_RESERVE175 = 456, + MX35_PAD_RESERVE176 = 457, + MX35_PAD_RESERVE177 = 458, + MX35_PAD_RESERVE178 = 459, + MX35_PAD_RESERVE179 = 460, + MX35_PAD_RESERVE180 = 461, + MX35_PAD_RESERVE181 = 462, + MX35_PAD_RESERVE182 = 463, + MX35_PAD_RESERVE183 = 464, + MX35_PAD_RESERVE184 = 465, + MX35_PAD_RESERVE185 = 466, + MX35_PAD_RESERVE186 = 467, + MX35_PAD_RESERVE187 = 468, + MX35_PAD_RESERVE188 = 469, + MX35_PAD_RESERVE189 = 470, + MX35_PAD_RESERVE190 = 471, + MX35_PAD_RESERVE191 = 472, + MX35_PAD_RESERVE192 = 473, + MX35_PAD_RESERVE193 = 474, + MX35_PAD_RESERVE194 = 475, + MX35_PAD_RESERVE195 = 476, + MX35_PAD_RESERVE196 = 477, + MX35_PAD_RESERVE197 = 478, + MX35_PAD_RESERVE198 = 479, + MX35_PAD_RESERVE199 = 480, + MX35_PAD_RESERVE200 = 481, + MX35_PAD_RESERVE201 = 482, + MX35_PAD_EXT_ARMCLK = 483, + MX35_PAD_TEST_MODE = 484, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX35_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX35_PAD_CAPTURE), + IMX_PINCTRL_PIN(MX35_PAD_COMPARE), + IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST), + IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0), + IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1), + IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0), + IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0), + IMX_PINCTRL_PIN(MX35_PAD_CLKO), + IMX_PINCTRL_PIN(MX35_PAD_VSTBY), + IMX_PINCTRL_PIN(MX35_PAD_A0), + IMX_PINCTRL_PIN(MX35_PAD_A1), + IMX_PINCTRL_PIN(MX35_PAD_A2), + IMX_PINCTRL_PIN(MX35_PAD_A3), + IMX_PINCTRL_PIN(MX35_PAD_A4), + IMX_PINCTRL_PIN(MX35_PAD_A5), + IMX_PINCTRL_PIN(MX35_PAD_A6), + IMX_PINCTRL_PIN(MX35_PAD_A7), + IMX_PINCTRL_PIN(MX35_PAD_A8), + IMX_PINCTRL_PIN(MX35_PAD_A9), + IMX_PINCTRL_PIN(MX35_PAD_A10), + IMX_PINCTRL_PIN(MX35_PAD_MA10), + IMX_PINCTRL_PIN(MX35_PAD_A11), + IMX_PINCTRL_PIN(MX35_PAD_A12), + IMX_PINCTRL_PIN(MX35_PAD_A13), + IMX_PINCTRL_PIN(MX35_PAD_A14), + IMX_PINCTRL_PIN(MX35_PAD_A15), + IMX_PINCTRL_PIN(MX35_PAD_A16), + IMX_PINCTRL_PIN(MX35_PAD_A17), + IMX_PINCTRL_PIN(MX35_PAD_A18), + IMX_PINCTRL_PIN(MX35_PAD_A19), + IMX_PINCTRL_PIN(MX35_PAD_A20), + IMX_PINCTRL_PIN(MX35_PAD_A21), + IMX_PINCTRL_PIN(MX35_PAD_A22), + IMX_PINCTRL_PIN(MX35_PAD_A23), + IMX_PINCTRL_PIN(MX35_PAD_A24), + IMX_PINCTRL_PIN(MX35_PAD_A25), + IMX_PINCTRL_PIN(MX35_PAD_EB0), + IMX_PINCTRL_PIN(MX35_PAD_EB1), + IMX_PINCTRL_PIN(MX35_PAD_OE), + IMX_PINCTRL_PIN(MX35_PAD_CS0), + IMX_PINCTRL_PIN(MX35_PAD_CS1), + IMX_PINCTRL_PIN(MX35_PAD_CS2), + IMX_PINCTRL_PIN(MX35_PAD_CS3), + IMX_PINCTRL_PIN(MX35_PAD_CS4), + IMX_PINCTRL_PIN(MX35_PAD_CS5), + IMX_PINCTRL_PIN(MX35_PAD_NF_CE0), + IMX_PINCTRL_PIN(MX35_PAD_LBA), + IMX_PINCTRL_PIN(MX35_PAD_BCLK), + IMX_PINCTRL_PIN(MX35_PAD_RW), + IMX_PINCTRL_PIN(MX35_PAD_NFWE_B), + IMX_PINCTRL_PIN(MX35_PAD_NFRE_B), + IMX_PINCTRL_PIN(MX35_PAD_NFALE), + IMX_PINCTRL_PIN(MX35_PAD_NFCLE), + IMX_PINCTRL_PIN(MX35_PAD_NFWP_B), + IMX_PINCTRL_PIN(MX35_PAD_NFRB), + IMX_PINCTRL_PIN(MX35_PAD_CSI_D8), + IMX_PINCTRL_PIN(MX35_PAD_CSI_D9), + IMX_PINCTRL_PIN(MX35_PAD_CSI_D10), + IMX_PINCTRL_PIN(MX35_PAD_CSI_D11), + IMX_PINCTRL_PIN(MX35_PAD_CSI_D12), + IMX_PINCTRL_PIN(MX35_PAD_CSI_D13), + IMX_PINCTRL_PIN(MX35_PAD_CSI_D14), + IMX_PINCTRL_PIN(MX35_PAD_CSI_D15), + IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK), + IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT), + IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK), + IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT), + IMX_PINCTRL_PIN(MX35_PAD_STXD4), + IMX_PINCTRL_PIN(MX35_PAD_SRXD4), + IMX_PINCTRL_PIN(MX35_PAD_SCK4), + IMX_PINCTRL_PIN(MX35_PAD_STXFS4), + IMX_PINCTRL_PIN(MX35_PAD_STXD5), + IMX_PINCTRL_PIN(MX35_PAD_SRXD5), + IMX_PINCTRL_PIN(MX35_PAD_SCK5), + IMX_PINCTRL_PIN(MX35_PAD_STXFS5), + IMX_PINCTRL_PIN(MX35_PAD_SCKR), + IMX_PINCTRL_PIN(MX35_PAD_FSR), + IMX_PINCTRL_PIN(MX35_PAD_HCKR), + IMX_PINCTRL_PIN(MX35_PAD_SCKT), + IMX_PINCTRL_PIN(MX35_PAD_FST), + IMX_PINCTRL_PIN(MX35_PAD_HCKT), + IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0), + IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1), + IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2), + IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3), + IMX_PINCTRL_PIN(MX35_PAD_TX1), + IMX_PINCTRL_PIN(MX35_PAD_TX0), + IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI), + IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY), + IMX_PINCTRL_PIN(MX35_PAD_RXD1), + IMX_PINCTRL_PIN(MX35_PAD_TXD1), + IMX_PINCTRL_PIN(MX35_PAD_RTS1), + IMX_PINCTRL_PIN(MX35_PAD_CTS1), + IMX_PINCTRL_PIN(MX35_PAD_RXD2), + IMX_PINCTRL_PIN(MX35_PAD_TXD2), + IMX_PINCTRL_PIN(MX35_PAD_RTS2), + IMX_PINCTRL_PIN(MX35_PAD_CTS2), + IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR), + IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC), + IMX_PINCTRL_PIN(MX35_PAD_LD0), + IMX_PINCTRL_PIN(MX35_PAD_LD1), + IMX_PINCTRL_PIN(MX35_PAD_LD2), + IMX_PINCTRL_PIN(MX35_PAD_LD3), + IMX_PINCTRL_PIN(MX35_PAD_LD4), + IMX_PINCTRL_PIN(MX35_PAD_LD5), + IMX_PINCTRL_PIN(MX35_PAD_LD6), + IMX_PINCTRL_PIN(MX35_PAD_LD7), + IMX_PINCTRL_PIN(MX35_PAD_LD8), + IMX_PINCTRL_PIN(MX35_PAD_LD9), + IMX_PINCTRL_PIN(MX35_PAD_LD10), + IMX_PINCTRL_PIN(MX35_PAD_LD11), + IMX_PINCTRL_PIN(MX35_PAD_LD12), + IMX_PINCTRL_PIN(MX35_PAD_LD13), + IMX_PINCTRL_PIN(MX35_PAD_LD14), + IMX_PINCTRL_PIN(MX35_PAD_LD15), + IMX_PINCTRL_PIN(MX35_PAD_LD16), + IMX_PINCTRL_PIN(MX35_PAD_LD17), + IMX_PINCTRL_PIN(MX35_PAD_LD18), + IMX_PINCTRL_PIN(MX35_PAD_LD19), + IMX_PINCTRL_PIN(MX35_PAD_LD20), + IMX_PINCTRL_PIN(MX35_PAD_LD21), + IMX_PINCTRL_PIN(MX35_PAD_LD22), + IMX_PINCTRL_PIN(MX35_PAD_LD23), + IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC), + IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT), + IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY), + IMX_PINCTRL_PIN(MX35_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC), + IMX_PINCTRL_PIN(MX35_PAD_D3_REV), + IMX_PINCTRL_PIN(MX35_PAD_D3_CLS), + IMX_PINCTRL_PIN(MX35_PAD_D3_SPL), + IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0), + IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1), + IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2), + IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3), + IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0), + IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK), + IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B), + IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15), + IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ), + IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1), + IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2), + IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK), + IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT), + IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG), + IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK), + IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK), + IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV), + IMX_PINCTRL_PIN(MX35_PAD_FEC_COL), + IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0), + IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0), + IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN), + IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC), + IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO), + IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR), + IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR), + IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS), + IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1), + IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1), + IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2), + IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2), + IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3), + IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B), + IMX_PINCTRL_PIN(MX35_PAD_POR_B), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0), + IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1), + IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0), + IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1), + IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE19), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE20), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE21), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE22), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE23), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE24), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE25), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE26), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE27), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE28), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE29), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE30), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE31), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE32), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE33), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE34), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE35), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE36), + IMX_PINCTRL_PIN(MX35_PAD_SDBA1), + IMX_PINCTRL_PIN(MX35_PAD_SDBA0), + IMX_PINCTRL_PIN(MX35_PAD_SD0), + IMX_PINCTRL_PIN(MX35_PAD_SD1), + IMX_PINCTRL_PIN(MX35_PAD_SD2), + IMX_PINCTRL_PIN(MX35_PAD_SD3), + IMX_PINCTRL_PIN(MX35_PAD_SD4), + IMX_PINCTRL_PIN(MX35_PAD_SD5), + IMX_PINCTRL_PIN(MX35_PAD_SD6), + IMX_PINCTRL_PIN(MX35_PAD_SD7), + IMX_PINCTRL_PIN(MX35_PAD_SD8), + IMX_PINCTRL_PIN(MX35_PAD_SD9), + IMX_PINCTRL_PIN(MX35_PAD_SD10), + IMX_PINCTRL_PIN(MX35_PAD_SD11), + IMX_PINCTRL_PIN(MX35_PAD_SD12), + IMX_PINCTRL_PIN(MX35_PAD_SD13), + IMX_PINCTRL_PIN(MX35_PAD_SD14), + IMX_PINCTRL_PIN(MX35_PAD_SD15), + IMX_PINCTRL_PIN(MX35_PAD_SD16), + IMX_PINCTRL_PIN(MX35_PAD_SD17), + IMX_PINCTRL_PIN(MX35_PAD_SD18), + IMX_PINCTRL_PIN(MX35_PAD_SD19), + IMX_PINCTRL_PIN(MX35_PAD_SD20), + IMX_PINCTRL_PIN(MX35_PAD_SD21), + IMX_PINCTRL_PIN(MX35_PAD_SD22), + IMX_PINCTRL_PIN(MX35_PAD_SD23), + IMX_PINCTRL_PIN(MX35_PAD_SD24), + IMX_PINCTRL_PIN(MX35_PAD_SD25), + IMX_PINCTRL_PIN(MX35_PAD_SD26), + IMX_PINCTRL_PIN(MX35_PAD_SD27), + IMX_PINCTRL_PIN(MX35_PAD_SD28), + IMX_PINCTRL_PIN(MX35_PAD_SD29), + IMX_PINCTRL_PIN(MX35_PAD_SD30), + IMX_PINCTRL_PIN(MX35_PAD_SD31), + IMX_PINCTRL_PIN(MX35_PAD_DQM0), + IMX_PINCTRL_PIN(MX35_PAD_DQM1), + IMX_PINCTRL_PIN(MX35_PAD_DQM2), + IMX_PINCTRL_PIN(MX35_PAD_DQM3), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE37), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE38), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE39), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE40), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE41), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE42), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE43), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE44), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE45), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE46), + IMX_PINCTRL_PIN(MX35_PAD_ECB), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE47), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE48), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE49), + IMX_PINCTRL_PIN(MX35_PAD_RAS), + IMX_PINCTRL_PIN(MX35_PAD_CAS), + IMX_PINCTRL_PIN(MX35_PAD_SDWE), + IMX_PINCTRL_PIN(MX35_PAD_SDCKE0), + IMX_PINCTRL_PIN(MX35_PAD_SDCKE1), + IMX_PINCTRL_PIN(MX35_PAD_SDCLK), + IMX_PINCTRL_PIN(MX35_PAD_SDQS0), + IMX_PINCTRL_PIN(MX35_PAD_SDQS1), + IMX_PINCTRL_PIN(MX35_PAD_SDQS2), + IMX_PINCTRL_PIN(MX35_PAD_SDQS3), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE50), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE51), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE52), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE53), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE54), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE55), + IMX_PINCTRL_PIN(MX35_PAD_D15), + IMX_PINCTRL_PIN(MX35_PAD_D14), + IMX_PINCTRL_PIN(MX35_PAD_D13), + IMX_PINCTRL_PIN(MX35_PAD_D12), + IMX_PINCTRL_PIN(MX35_PAD_D11), + IMX_PINCTRL_PIN(MX35_PAD_D10), + IMX_PINCTRL_PIN(MX35_PAD_D9), + IMX_PINCTRL_PIN(MX35_PAD_D8), + IMX_PINCTRL_PIN(MX35_PAD_D7), + IMX_PINCTRL_PIN(MX35_PAD_D6), + IMX_PINCTRL_PIN(MX35_PAD_D5), + IMX_PINCTRL_PIN(MX35_PAD_D4), + IMX_PINCTRL_PIN(MX35_PAD_D3), + IMX_PINCTRL_PIN(MX35_PAD_D2), + IMX_PINCTRL_PIN(MX35_PAD_D1), + IMX_PINCTRL_PIN(MX35_PAD_D0), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE56), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE57), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE58), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE59), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE60), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE61), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE62), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE63), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE64), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE65), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE66), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE67), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE68), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE69), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE70), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE71), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE72), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE73), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE74), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE75), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE76), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE77), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE78), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE79), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE80), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE81), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE82), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE83), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE84), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE85), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE86), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE87), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE88), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE89), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE90), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE91), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE92), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE93), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE94), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE95), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE96), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE97), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE98), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE99), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE100), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE101), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE102), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE103), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE104), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE105), + IMX_PINCTRL_PIN(MX35_PAD_RTCK), + IMX_PINCTRL_PIN(MX35_PAD_TCK), + IMX_PINCTRL_PIN(MX35_PAD_TMS), + IMX_PINCTRL_PIN(MX35_PAD_TDI), + IMX_PINCTRL_PIN(MX35_PAD_TDO), + IMX_PINCTRL_PIN(MX35_PAD_TRSTB), + IMX_PINCTRL_PIN(MX35_PAD_DE_B), + IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE106), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE107), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE108), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE109), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE110), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE111), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE112), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE113), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE114), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE115), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE116), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE117), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE118), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE119), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE120), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE121), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE122), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE123), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE124), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE125), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE126), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE127), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE128), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE129), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE130), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE131), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE132), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE133), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE134), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE135), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE136), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE137), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE138), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE139), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE140), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE141), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE142), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE143), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE144), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE145), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE146), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE147), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE148), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE149), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE150), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE151), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE152), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE153), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE154), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE155), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE156), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE157), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE158), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE159), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE160), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE161), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE162), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE163), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE164), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE165), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE166), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE167), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE168), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE169), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE170), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE171), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE172), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE173), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE174), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE175), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE176), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE177), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE178), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE179), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE180), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE181), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE182), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE183), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE184), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE185), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE186), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE187), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE188), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE189), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE190), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE191), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE192), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE193), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE194), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE195), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE196), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE197), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE198), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE199), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE200), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE201), + IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK), + IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE), +}; + +static struct imx_pinctrl_soc_info imx35_pinctrl_info = { + .pins = imx35_pinctrl_pads, + .npins = ARRAY_SIZE(imx35_pinctrl_pads), +}; + +static const struct of_device_id imx35_pinctrl_of_match[] = { + { .compatible = "fsl,imx35-iomuxc", }, + { /* sentinel */ } +}; + +static int imx35_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx35_pinctrl_info); +} + +static struct platform_driver imx35_pinctrl_driver = { + .driver = { + .name = "imx35-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx35_pinctrl_of_match, + }, + .probe = imx35_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx35_pinctrl_init(void) +{ + return platform_driver_register(&imx35_pinctrl_driver); +} +arch_initcall(imx35_pinctrl_init); + +static void __exit imx35_pinctrl_exit(void) +{ + platform_driver_unregister(&imx35_pinctrl_driver); +} +module_exit(imx35_pinctrl_exit); +MODULE_AUTHOR("Dong Aisheng "); +MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c new file mode 100644 index 000000000000..e8bd604ab147 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx50.c @@ -0,0 +1,426 @@ +/* + * imx50 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2013 Greg Ungerer + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx50_pads { + MX50_PAD_RESERVE0 = 0, + MX50_PAD_RESERVE1 = 1, + MX50_PAD_RESERVE2 = 2, + MX50_PAD_RESERVE3 = 3, + MX50_PAD_RESERVE4 = 4, + MX50_PAD_RESERVE5 = 5, + MX50_PAD_RESERVE6 = 6, + MX50_PAD_RESERVE7 = 7, + MX50_PAD_KEY_COL0 = 8, + MX50_PAD_KEY_ROW0 = 9, + MX50_PAD_KEY_COL1 = 10, + MX50_PAD_KEY_ROW1 = 11, + MX50_PAD_KEY_COL2 = 12, + MX50_PAD_KEY_ROW2 = 13, + MX50_PAD_KEY_COL3 = 14, + MX50_PAD_KEY_ROW3 = 15, + MX50_PAD_I2C1_SCL = 16, + MX50_PAD_I2C1_SDA = 17, + MX50_PAD_I2C2_SCL = 18, + MX50_PAD_I2C2_SDA = 19, + MX50_PAD_I2C3_SCL = 20, + MX50_PAD_I2C3_SDA = 21, + MX50_PAD_PWM1 = 22, + MX50_PAD_PWM2 = 23, + MX50_PAD_0WIRE = 24, + MX50_PAD_EPITO = 25, + MX50_PAD_WDOG = 26, + MX50_PAD_SSI_TXFS = 27, + MX50_PAD_SSI_TXC = 28, + MX50_PAD_SSI_TXD = 29, + MX50_PAD_SSI_RXD = 30, + MX50_PAD_SSI_RXF = 31, + MX50_PAD_SSI_RXC = 32, + MX50_PAD_UART1_TXD = 33, + MX50_PAD_UART1_RXD = 34, + MX50_PAD_UART1_CTS = 35, + MX50_PAD_UART1_RTS = 36, + MX50_PAD_UART2_TXD = 37, + MX50_PAD_UART2_RXD = 38, + MX50_PAD_UART2_CTS = 39, + MX50_PAD_UART2_RTS = 40, + MX50_PAD_UART3_TXD = 41, + MX50_PAD_UART3_RXD = 42, + MX50_PAD_UART4_TXD = 43, + MX50_PAD_UART4_RXD = 44, + MX50_PAD_CSPI_CLK = 45, + MX50_PAD_CSPI_MOSI = 46, + MX50_PAD_CSPI_MISO = 47, + MX50_PAD_CSPI_SS0 = 48, + MX50_PAD_ECSPI1_CLK = 49, + MX50_PAD_ECSPI1_MOSI = 50, + MX50_PAD_ECSPI1_MISO = 51, + MX50_PAD_ECSPI1_SS0 = 52, + MX50_PAD_ECSPI2_CLK = 53, + MX50_PAD_ECSPI2_MOSI = 54, + MX50_PAD_ECSPI2_MISO = 55, + MX50_PAD_ECSPI2_SS0 = 56, + MX50_PAD_SD1_CLK = 57, + MX50_PAD_SD1_CMD = 58, + MX50_PAD_SD1_D0 = 59, + MX50_PAD_SD1_D1 = 60, + MX50_PAD_SD1_D2 = 61, + MX50_PAD_SD1_D3 = 62, + MX50_PAD_SD2_CLK = 63, + MX50_PAD_SD2_CMD = 64, + MX50_PAD_SD2_D0 = 65, + MX50_PAD_SD2_D1 = 66, + MX50_PAD_SD2_D2 = 67, + MX50_PAD_SD2_D3 = 68, + MX50_PAD_SD2_D4 = 69, + MX50_PAD_SD2_D5 = 70, + MX50_PAD_SD2_D6 = 71, + MX50_PAD_SD2_D7 = 72, + MX50_PAD_SD2_WP = 73, + MX50_PAD_SD2_CD = 74, + MX50_PAD_DISP_D0 = 75, + MX50_PAD_DISP_D1 = 76, + MX50_PAD_DISP_D2 = 77, + MX50_PAD_DISP_D3 = 78, + MX50_PAD_DISP_D4 = 79, + MX50_PAD_DISP_D5 = 80, + MX50_PAD_DISP_D6 = 81, + MX50_PAD_DISP_D7 = 82, + MX50_PAD_DISP_WR = 83, + MX50_PAD_DISP_RD = 84, + MX50_PAD_DISP_RS = 85, + MX50_PAD_DISP_CS = 86, + MX50_PAD_DISP_BUSY = 87, + MX50_PAD_DISP_RESET = 88, + MX50_PAD_SD3_CLK = 89, + MX50_PAD_SD3_CMD = 90, + MX50_PAD_SD3_D0 = 91, + MX50_PAD_SD3_D1 = 92, + MX50_PAD_SD3_D2 = 93, + MX50_PAD_SD3_D3 = 94, + MX50_PAD_SD3_D4 = 95, + MX50_PAD_SD3_D5 = 96, + MX50_PAD_SD3_D6 = 97, + MX50_PAD_SD3_D7 = 98, + MX50_PAD_SD3_WP = 99, + MX50_PAD_DISP_D8 = 100, + MX50_PAD_DISP_D9 = 101, + MX50_PAD_DISP_D10 = 102, + MX50_PAD_DISP_D11 = 103, + MX50_PAD_DISP_D12 = 104, + MX50_PAD_DISP_D13 = 105, + MX50_PAD_DISP_D14 = 106, + MX50_PAD_DISP_D15 = 107, + MX50_PAD_EPDC_D0 = 108, + MX50_PAD_EPDC_D1 = 109, + MX50_PAD_EPDC_D2 = 110, + MX50_PAD_EPDC_D3 = 111, + MX50_PAD_EPDC_D4 = 112, + MX50_PAD_EPDC_D5 = 113, + MX50_PAD_EPDC_D6 = 114, + MX50_PAD_EPDC_D7 = 115, + MX50_PAD_EPDC_D8 = 116, + MX50_PAD_EPDC_D9 = 117, + MX50_PAD_EPDC_D10 = 118, + MX50_PAD_EPDC_D11 = 119, + MX50_PAD_EPDC_D12 = 120, + MX50_PAD_EPDC_D13 = 121, + MX50_PAD_EPDC_D14 = 122, + MX50_PAD_EPDC_D15 = 123, + MX50_PAD_EPDC_GDCLK = 124, + MX50_PAD_EPDC_GDSP = 125, + MX50_PAD_EPDC_GDOE = 126, + MX50_PAD_EPDC_GDRL = 127, + MX50_PAD_EPDC_SDCLK = 128, + MX50_PAD_EPDC_SDOEZ = 129, + MX50_PAD_EPDC_SDOED = 130, + MX50_PAD_EPDC_SDOE = 131, + MX50_PAD_EPDC_SDLE = 132, + MX50_PAD_EPDC_SDCLKN = 133, + MX50_PAD_EPDC_SDSHR = 134, + MX50_PAD_EPDC_PWRCOM = 135, + MX50_PAD_EPDC_PWRSTAT = 136, + MX50_PAD_EPDC_PWRCTRL0 = 137, + MX50_PAD_EPDC_PWRCTRL1 = 138, + MX50_PAD_EPDC_PWRCTRL2 = 139, + MX50_PAD_EPDC_PWRCTRL3 = 140, + MX50_PAD_EPDC_VCOM0 = 141, + MX50_PAD_EPDC_VCOM1 = 142, + MX50_PAD_EPDC_BDR0 = 143, + MX50_PAD_EPDC_BDR1 = 144, + MX50_PAD_EPDC_SDCE0 = 145, + MX50_PAD_EPDC_SDCE1 = 146, + MX50_PAD_EPDC_SDCE2 = 147, + MX50_PAD_EPDC_SDCE3 = 148, + MX50_PAD_EPDC_SDCE4 = 149, + MX50_PAD_EPDC_SDCE5 = 150, + MX50_PAD_EIM_DA0 = 151, + MX50_PAD_EIM_DA1 = 152, + MX50_PAD_EIM_DA2 = 153, + MX50_PAD_EIM_DA3 = 154, + MX50_PAD_EIM_DA4 = 155, + MX50_PAD_EIM_DA5 = 156, + MX50_PAD_EIM_DA6 = 157, + MX50_PAD_EIM_DA7 = 158, + MX50_PAD_EIM_DA8 = 159, + MX50_PAD_EIM_DA9 = 160, + MX50_PAD_EIM_DA10 = 161, + MX50_PAD_EIM_DA11 = 162, + MX50_PAD_EIM_DA12 = 163, + MX50_PAD_EIM_DA13 = 164, + MX50_PAD_EIM_DA14 = 165, + MX50_PAD_EIM_DA15 = 166, + MX50_PAD_EIM_CS2 = 167, + MX50_PAD_EIM_CS1 = 168, + MX50_PAD_EIM_CS0 = 169, + MX50_PAD_EIM_EB0 = 170, + MX50_PAD_EIM_EB1 = 171, + MX50_PAD_EIM_WAIT = 172, + MX50_PAD_EIM_BCLK = 173, + MX50_PAD_EIM_RDY = 174, + MX50_PAD_EIM_OE = 175, + MX50_PAD_EIM_RW = 176, + MX50_PAD_EIM_LBA = 177, + MX50_PAD_EIM_CRE = 178, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX50_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL), + IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA), + IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL), + IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA), + IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL), + IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA), + IMX_PINCTRL_PIN(MX50_PAD_PWM1), + IMX_PINCTRL_PIN(MX50_PAD_PWM2), + IMX_PINCTRL_PIN(MX50_PAD_0WIRE), + IMX_PINCTRL_PIN(MX50_PAD_EPITO), + IMX_PINCTRL_PIN(MX50_PAD_WDOG), + IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS), + IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC), + IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD), + IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD), + IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF), + IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC), + IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD), + IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD), + IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD), + IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD), + IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK), + IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI), + IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO), + IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX50_PAD_SD1_D0), + IMX_PINCTRL_PIN(MX50_PAD_SD1_D1), + IMX_PINCTRL_PIN(MX50_PAD_SD1_D2), + IMX_PINCTRL_PIN(MX50_PAD_SD1_D3), + IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D0), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D1), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D2), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D3), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D4), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D5), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D6), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D7), + IMX_PINCTRL_PIN(MX50_PAD_SD2_WP), + IMX_PINCTRL_PIN(MX50_PAD_SD2_CD), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D0), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D1), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D2), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D3), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D4), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D5), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D6), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D7), + IMX_PINCTRL_PIN(MX50_PAD_DISP_WR), + IMX_PINCTRL_PIN(MX50_PAD_DISP_RD), + IMX_PINCTRL_PIN(MX50_PAD_DISP_RS), + IMX_PINCTRL_PIN(MX50_PAD_DISP_CS), + IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY), + IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET), + IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D0), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D1), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D2), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D3), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D4), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D5), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D6), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D7), + IMX_PINCTRL_PIN(MX50_PAD_SD3_WP), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D8), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D9), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D10), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D11), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D12), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D13), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D14), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D15), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15), + IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2), + IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1), + IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0), + IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0), + IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1), + IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT), + IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK), + IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY), + IMX_PINCTRL_PIN(MX50_PAD_EIM_OE), + IMX_PINCTRL_PIN(MX50_PAD_EIM_RW), + IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA), + IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE), +}; + +static struct imx_pinctrl_soc_info imx50_pinctrl_info = { + .pins = imx50_pinctrl_pads, + .npins = ARRAY_SIZE(imx50_pinctrl_pads), +}; + +static const struct of_device_id imx50_pinctrl_of_match[] = { + { .compatible = "fsl,imx50-iomuxc", }, + { /* sentinel */ } +}; + +static int imx50_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx50_pinctrl_info); +} + +static struct platform_driver imx50_pinctrl_driver = { + .driver = { + .name = "imx50-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx50_pinctrl_of_match), + }, + .probe = imx50_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx50_pinctrl_init(void) +{ + return platform_driver_register(&imx50_pinctrl_driver); +} +arch_initcall(imx50_pinctrl_init); + +static void __exit imx50_pinctrl_exit(void) +{ + platform_driver_unregister(&imx50_pinctrl_driver); +} +module_exit(imx50_pinctrl_exit); +MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c new file mode 100644 index 000000000000..b818051db7c9 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx51.c @@ -0,0 +1,804 @@ +/* + * imx51 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro, Inc. + * + * Author: Dong Aisheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx51_pads { + MX51_PAD_RESERVE0 = 0, + MX51_PAD_RESERVE1 = 1, + MX51_PAD_RESERVE2 = 2, + MX51_PAD_RESERVE3 = 3, + MX51_PAD_RESERVE4 = 4, + MX51_PAD_RESERVE5 = 5, + MX51_PAD_RESERVE6 = 6, + MX51_PAD_EIM_DA0 = 7, + MX51_PAD_EIM_DA1 = 8, + MX51_PAD_EIM_DA2 = 9, + MX51_PAD_EIM_DA3 = 10, + MX51_PAD_EIM_DA4 = 11, + MX51_PAD_EIM_DA5 = 12, + MX51_PAD_EIM_DA6 = 13, + MX51_PAD_EIM_DA7 = 14, + MX51_PAD_EIM_DA8 = 15, + MX51_PAD_EIM_DA9 = 16, + MX51_PAD_EIM_DA10 = 17, + MX51_PAD_EIM_DA11 = 18, + MX51_PAD_EIM_DA12 = 19, + MX51_PAD_EIM_DA13 = 20, + MX51_PAD_EIM_DA14 = 21, + MX51_PAD_EIM_DA15 = 22, + MX51_PAD_EIM_D16 = 23, + MX51_PAD_EIM_D17 = 24, + MX51_PAD_EIM_D18 = 25, + MX51_PAD_EIM_D19 = 26, + MX51_PAD_EIM_D20 = 27, + MX51_PAD_EIM_D21 = 28, + MX51_PAD_EIM_D22 = 29, + MX51_PAD_EIM_D23 = 30, + MX51_PAD_EIM_D24 = 31, + MX51_PAD_EIM_D25 = 32, + MX51_PAD_EIM_D26 = 33, + MX51_PAD_EIM_D27 = 34, + MX51_PAD_EIM_D28 = 35, + MX51_PAD_EIM_D29 = 36, + MX51_PAD_EIM_D30 = 37, + MX51_PAD_EIM_D31 = 38, + MX51_PAD_EIM_A16 = 39, + MX51_PAD_EIM_A17 = 40, + MX51_PAD_EIM_A18 = 41, + MX51_PAD_EIM_A19 = 42, + MX51_PAD_EIM_A20 = 43, + MX51_PAD_EIM_A21 = 44, + MX51_PAD_EIM_A22 = 45, + MX51_PAD_EIM_A23 = 46, + MX51_PAD_EIM_A24 = 47, + MX51_PAD_EIM_A25 = 48, + MX51_PAD_EIM_A26 = 49, + MX51_PAD_EIM_A27 = 50, + MX51_PAD_EIM_EB0 = 51, + MX51_PAD_EIM_EB1 = 52, + MX51_PAD_EIM_EB2 = 53, + MX51_PAD_EIM_EB3 = 54, + MX51_PAD_EIM_OE = 55, + MX51_PAD_EIM_CS0 = 56, + MX51_PAD_EIM_CS1 = 57, + MX51_PAD_EIM_CS2 = 58, + MX51_PAD_EIM_CS3 = 59, + MX51_PAD_EIM_CS4 = 60, + MX51_PAD_EIM_CS5 = 61, + MX51_PAD_EIM_DTACK = 62, + MX51_PAD_EIM_LBA = 63, + MX51_PAD_EIM_CRE = 64, + MX51_PAD_DRAM_CS1 = 65, + MX51_PAD_NANDF_WE_B = 66, + MX51_PAD_NANDF_RE_B = 67, + MX51_PAD_NANDF_ALE = 68, + MX51_PAD_NANDF_CLE = 69, + MX51_PAD_NANDF_WP_B = 70, + MX51_PAD_NANDF_RB0 = 71, + MX51_PAD_NANDF_RB1 = 72, + MX51_PAD_NANDF_RB2 = 73, + MX51_PAD_NANDF_RB3 = 74, + MX51_PAD_GPIO_NAND = 75, + MX51_PAD_NANDF_CS0 = 76, + MX51_PAD_NANDF_CS1 = 77, + MX51_PAD_NANDF_CS2 = 78, + MX51_PAD_NANDF_CS3 = 79, + MX51_PAD_NANDF_CS4 = 80, + MX51_PAD_NANDF_CS5 = 81, + MX51_PAD_NANDF_CS6 = 82, + MX51_PAD_NANDF_CS7 = 83, + MX51_PAD_NANDF_RDY_INT = 84, + MX51_PAD_NANDF_D15 = 85, + MX51_PAD_NANDF_D14 = 86, + MX51_PAD_NANDF_D13 = 87, + MX51_PAD_NANDF_D12 = 88, + MX51_PAD_NANDF_D11 = 89, + MX51_PAD_NANDF_D10 = 90, + MX51_PAD_NANDF_D9 = 91, + MX51_PAD_NANDF_D8 = 92, + MX51_PAD_NANDF_D7 = 93, + MX51_PAD_NANDF_D6 = 94, + MX51_PAD_NANDF_D5 = 95, + MX51_PAD_NANDF_D4 = 96, + MX51_PAD_NANDF_D3 = 97, + MX51_PAD_NANDF_D2 = 98, + MX51_PAD_NANDF_D1 = 99, + MX51_PAD_NANDF_D0 = 100, + MX51_PAD_CSI1_D8 = 101, + MX51_PAD_CSI1_D9 = 102, + MX51_PAD_CSI1_D10 = 103, + MX51_PAD_CSI1_D11 = 104, + MX51_PAD_CSI1_D12 = 105, + MX51_PAD_CSI1_D13 = 106, + MX51_PAD_CSI1_D14 = 107, + MX51_PAD_CSI1_D15 = 108, + MX51_PAD_CSI1_D16 = 109, + MX51_PAD_CSI1_D17 = 110, + MX51_PAD_CSI1_D18 = 111, + MX51_PAD_CSI1_D19 = 112, + MX51_PAD_CSI1_VSYNC = 113, + MX51_PAD_CSI1_HSYNC = 114, + MX51_PAD_CSI2_D12 = 115, + MX51_PAD_CSI2_D13 = 116, + MX51_PAD_CSI2_D14 = 117, + MX51_PAD_CSI2_D15 = 118, + MX51_PAD_CSI2_D16 = 119, + MX51_PAD_CSI2_D17 = 120, + MX51_PAD_CSI2_D18 = 121, + MX51_PAD_CSI2_D19 = 122, + MX51_PAD_CSI2_VSYNC = 123, + MX51_PAD_CSI2_HSYNC = 124, + MX51_PAD_CSI2_PIXCLK = 125, + MX51_PAD_I2C1_CLK = 126, + MX51_PAD_I2C1_DAT = 127, + MX51_PAD_AUD3_BB_TXD = 128, + MX51_PAD_AUD3_BB_RXD = 129, + MX51_PAD_AUD3_BB_CK = 130, + MX51_PAD_AUD3_BB_FS = 131, + MX51_PAD_CSPI1_MOSI = 132, + MX51_PAD_CSPI1_MISO = 133, + MX51_PAD_CSPI1_SS0 = 134, + MX51_PAD_CSPI1_SS1 = 135, + MX51_PAD_CSPI1_RDY = 136, + MX51_PAD_CSPI1_SCLK = 137, + MX51_PAD_UART1_RXD = 138, + MX51_PAD_UART1_TXD = 139, + MX51_PAD_UART1_RTS = 140, + MX51_PAD_UART1_CTS = 141, + MX51_PAD_UART2_RXD = 142, + MX51_PAD_UART2_TXD = 143, + MX51_PAD_UART3_RXD = 144, + MX51_PAD_UART3_TXD = 145, + MX51_PAD_OWIRE_LINE = 146, + MX51_PAD_KEY_ROW0 = 147, + MX51_PAD_KEY_ROW1 = 148, + MX51_PAD_KEY_ROW2 = 149, + MX51_PAD_KEY_ROW3 = 150, + MX51_PAD_KEY_COL0 = 151, + MX51_PAD_KEY_COL1 = 152, + MX51_PAD_KEY_COL2 = 153, + MX51_PAD_KEY_COL3 = 154, + MX51_PAD_KEY_COL4 = 155, + MX51_PAD_KEY_COL5 = 156, + MX51_PAD_RESERVE7 = 157, + MX51_PAD_USBH1_CLK = 158, + MX51_PAD_USBH1_DIR = 159, + MX51_PAD_USBH1_STP = 160, + MX51_PAD_USBH1_NXT = 161, + MX51_PAD_USBH1_DATA0 = 162, + MX51_PAD_USBH1_DATA1 = 163, + MX51_PAD_USBH1_DATA2 = 164, + MX51_PAD_USBH1_DATA3 = 165, + MX51_PAD_USBH1_DATA4 = 166, + MX51_PAD_USBH1_DATA5 = 167, + MX51_PAD_USBH1_DATA6 = 168, + MX51_PAD_USBH1_DATA7 = 169, + MX51_PAD_DI1_PIN11 = 170, + MX51_PAD_DI1_PIN12 = 171, + MX51_PAD_DI1_PIN13 = 172, + MX51_PAD_DI1_D0_CS = 173, + MX51_PAD_DI1_D1_CS = 174, + MX51_PAD_DISPB2_SER_DIN = 175, + MX51_PAD_DISPB2_SER_DIO = 176, + MX51_PAD_DISPB2_SER_CLK = 177, + MX51_PAD_DISPB2_SER_RS = 178, + MX51_PAD_DISP1_DAT0 = 179, + MX51_PAD_DISP1_DAT1 = 180, + MX51_PAD_DISP1_DAT2 = 181, + MX51_PAD_DISP1_DAT3 = 182, + MX51_PAD_DISP1_DAT4 = 183, + MX51_PAD_DISP1_DAT5 = 184, + MX51_PAD_DISP1_DAT6 = 185, + MX51_PAD_DISP1_DAT7 = 186, + MX51_PAD_DISP1_DAT8 = 187, + MX51_PAD_DISP1_DAT9 = 188, + MX51_PAD_DISP1_DAT10 = 189, + MX51_PAD_DISP1_DAT11 = 190, + MX51_PAD_DISP1_DAT12 = 191, + MX51_PAD_DISP1_DAT13 = 192, + MX51_PAD_DISP1_DAT14 = 193, + MX51_PAD_DISP1_DAT15 = 194, + MX51_PAD_DISP1_DAT16 = 195, + MX51_PAD_DISP1_DAT17 = 196, + MX51_PAD_DISP1_DAT18 = 197, + MX51_PAD_DISP1_DAT19 = 198, + MX51_PAD_DISP1_DAT20 = 199, + MX51_PAD_DISP1_DAT21 = 200, + MX51_PAD_DISP1_DAT22 = 201, + MX51_PAD_DISP1_DAT23 = 202, + MX51_PAD_DI1_PIN3 = 203, + MX51_PAD_DI1_PIN2 = 204, + MX51_PAD_RESERVE8 = 205, + MX51_PAD_DI_GP2 = 206, + MX51_PAD_DI_GP3 = 207, + MX51_PAD_DI2_PIN4 = 208, + MX51_PAD_DI2_PIN2 = 209, + MX51_PAD_DI2_PIN3 = 210, + MX51_PAD_DI2_DISP_CLK = 211, + MX51_PAD_DI_GP4 = 212, + MX51_PAD_DISP2_DAT0 = 213, + MX51_PAD_DISP2_DAT1 = 214, + MX51_PAD_DISP2_DAT2 = 215, + MX51_PAD_DISP2_DAT3 = 216, + MX51_PAD_DISP2_DAT4 = 217, + MX51_PAD_DISP2_DAT5 = 218, + MX51_PAD_DISP2_DAT6 = 219, + MX51_PAD_DISP2_DAT7 = 220, + MX51_PAD_DISP2_DAT8 = 221, + MX51_PAD_DISP2_DAT9 = 222, + MX51_PAD_DISP2_DAT10 = 223, + MX51_PAD_DISP2_DAT11 = 224, + MX51_PAD_DISP2_DAT12 = 225, + MX51_PAD_DISP2_DAT13 = 226, + MX51_PAD_DISP2_DAT14 = 227, + MX51_PAD_DISP2_DAT15 = 228, + MX51_PAD_SD1_CMD = 229, + MX51_PAD_SD1_CLK = 230, + MX51_PAD_SD1_DATA0 = 231, + MX51_PAD_SD1_DATA1 = 232, + MX51_PAD_SD1_DATA2 = 233, + MX51_PAD_SD1_DATA3 = 234, + MX51_PAD_GPIO1_0 = 235, + MX51_PAD_GPIO1_1 = 236, + MX51_PAD_SD2_CMD = 237, + MX51_PAD_SD2_CLK = 238, + MX51_PAD_SD2_DATA0 = 239, + MX51_PAD_SD2_DATA1 = 240, + MX51_PAD_SD2_DATA2 = 241, + MX51_PAD_SD2_DATA3 = 242, + MX51_PAD_GPIO1_2 = 243, + MX51_PAD_GPIO1_3 = 244, + MX51_PAD_PMIC_INT_REQ = 245, + MX51_PAD_GPIO1_4 = 246, + MX51_PAD_GPIO1_5 = 247, + MX51_PAD_GPIO1_6 = 248, + MX51_PAD_GPIO1_7 = 249, + MX51_PAD_GPIO1_8 = 250, + MX51_PAD_GPIO1_9 = 251, + MX51_PAD_RESERVE9 = 252, + MX51_PAD_RESERVE10 = 253, + MX51_PAD_RESERVE11 = 254, + MX51_PAD_RESERVE12 = 255, + MX51_PAD_RESERVE13 = 256, + MX51_PAD_RESERVE14 = 257, + MX51_PAD_RESERVE15 = 258, + MX51_PAD_RESERVE16 = 259, + MX51_PAD_RESERVE17 = 260, + MX51_PAD_RESERVE18 = 261, + MX51_PAD_RESERVE19 = 262, + MX51_PAD_RESERVE20 = 263, + MX51_PAD_RESERVE21 = 264, + MX51_PAD_RESERVE22 = 265, + MX51_PAD_RESERVE23 = 266, + MX51_PAD_RESERVE24 = 267, + MX51_PAD_RESERVE25 = 268, + MX51_PAD_RESERVE26 = 269, + MX51_PAD_RESERVE27 = 270, + MX51_PAD_RESERVE28 = 271, + MX51_PAD_RESERVE29 = 272, + MX51_PAD_RESERVE30 = 273, + MX51_PAD_RESERVE31 = 274, + MX51_PAD_RESERVE32 = 275, + MX51_PAD_RESERVE33 = 276, + MX51_PAD_RESERVE34 = 277, + MX51_PAD_RESERVE35 = 278, + MX51_PAD_RESERVE36 = 279, + MX51_PAD_RESERVE37 = 280, + MX51_PAD_RESERVE38 = 281, + MX51_PAD_RESERVE39 = 282, + MX51_PAD_RESERVE40 = 283, + MX51_PAD_RESERVE41 = 284, + MX51_PAD_RESERVE42 = 285, + MX51_PAD_RESERVE43 = 286, + MX51_PAD_RESERVE44 = 287, + MX51_PAD_RESERVE45 = 288, + MX51_PAD_RESERVE46 = 289, + MX51_PAD_RESERVE47 = 290, + MX51_PAD_RESERVE48 = 291, + MX51_PAD_RESERVE49 = 292, + MX51_PAD_RESERVE50 = 293, + MX51_PAD_RESERVE51 = 294, + MX51_PAD_RESERVE52 = 295, + MX51_PAD_RESERVE53 = 296, + MX51_PAD_RESERVE54 = 297, + MX51_PAD_RESERVE55 = 298, + MX51_PAD_RESERVE56 = 299, + MX51_PAD_RESERVE57 = 300, + MX51_PAD_RESERVE58 = 301, + MX51_PAD_RESERVE59 = 302, + MX51_PAD_RESERVE60 = 303, + MX51_PAD_RESERVE61 = 304, + MX51_PAD_RESERVE62 = 305, + MX51_PAD_RESERVE63 = 306, + MX51_PAD_RESERVE64 = 307, + MX51_PAD_RESERVE65 = 308, + MX51_PAD_RESERVE66 = 309, + MX51_PAD_RESERVE67 = 310, + MX51_PAD_RESERVE68 = 311, + MX51_PAD_RESERVE69 = 312, + MX51_PAD_RESERVE70 = 313, + MX51_PAD_RESERVE71 = 314, + MX51_PAD_RESERVE72 = 315, + MX51_PAD_RESERVE73 = 316, + MX51_PAD_RESERVE74 = 317, + MX51_PAD_RESERVE75 = 318, + MX51_PAD_RESERVE76 = 319, + MX51_PAD_RESERVE77 = 320, + MX51_PAD_RESERVE78 = 321, + MX51_PAD_RESERVE79 = 322, + MX51_PAD_RESERVE80 = 323, + MX51_PAD_RESERVE81 = 324, + MX51_PAD_RESERVE82 = 325, + MX51_PAD_RESERVE83 = 326, + MX51_PAD_RESERVE84 = 327, + MX51_PAD_RESERVE85 = 328, + MX51_PAD_RESERVE86 = 329, + MX51_PAD_RESERVE87 = 330, + MX51_PAD_RESERVE88 = 331, + MX51_PAD_RESERVE89 = 332, + MX51_PAD_RESERVE90 = 333, + MX51_PAD_RESERVE91 = 334, + MX51_PAD_RESERVE92 = 335, + MX51_PAD_RESERVE93 = 336, + MX51_PAD_RESERVE94 = 337, + MX51_PAD_RESERVE95 = 338, + MX51_PAD_RESERVE96 = 339, + MX51_PAD_RESERVE97 = 340, + MX51_PAD_RESERVE98 = 341, + MX51_PAD_RESERVE99 = 342, + MX51_PAD_RESERVE100 = 343, + MX51_PAD_RESERVE101 = 344, + MX51_PAD_RESERVE102 = 345, + MX51_PAD_RESERVE103 = 346, + MX51_PAD_RESERVE104 = 347, + MX51_PAD_RESERVE105 = 348, + MX51_PAD_RESERVE106 = 349, + MX51_PAD_RESERVE107 = 350, + MX51_PAD_RESERVE108 = 351, + MX51_PAD_RESERVE109 = 352, + MX51_PAD_RESERVE110 = 353, + MX51_PAD_RESERVE111 = 354, + MX51_PAD_RESERVE112 = 355, + MX51_PAD_RESERVE113 = 356, + MX51_PAD_RESERVE114 = 357, + MX51_PAD_RESERVE115 = 358, + MX51_PAD_RESERVE116 = 359, + MX51_PAD_RESERVE117 = 360, + MX51_PAD_RESERVE118 = 361, + MX51_PAD_RESERVE119 = 362, + MX51_PAD_RESERVE120 = 363, + MX51_PAD_RESERVE121 = 364, + MX51_PAD_CSI1_PIXCLK = 365, + MX51_PAD_CSI1_MCLK = 366, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX51_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D16), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D17), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D18), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D19), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D20), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D21), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D22), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D23), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D24), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D25), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D26), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D27), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D28), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D29), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D30), + IMX_PINCTRL_PIN(MX51_PAD_EIM_D31), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A16), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A17), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A18), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A19), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A20), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A21), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A22), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A23), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A24), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A25), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A26), + IMX_PINCTRL_PIN(MX51_PAD_EIM_A27), + IMX_PINCTRL_PIN(MX51_PAD_EIM_EB0), + IMX_PINCTRL_PIN(MX51_PAD_EIM_EB1), + IMX_PINCTRL_PIN(MX51_PAD_EIM_EB2), + IMX_PINCTRL_PIN(MX51_PAD_EIM_EB3), + IMX_PINCTRL_PIN(MX51_PAD_EIM_OE), + IMX_PINCTRL_PIN(MX51_PAD_EIM_CS0), + IMX_PINCTRL_PIN(MX51_PAD_EIM_CS1), + IMX_PINCTRL_PIN(MX51_PAD_EIM_CS2), + IMX_PINCTRL_PIN(MX51_PAD_EIM_CS3), + IMX_PINCTRL_PIN(MX51_PAD_EIM_CS4), + IMX_PINCTRL_PIN(MX51_PAD_EIM_CS5), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DTACK), + IMX_PINCTRL_PIN(MX51_PAD_EIM_LBA), + IMX_PINCTRL_PIN(MX51_PAD_EIM_CRE), + IMX_PINCTRL_PIN(MX51_PAD_DRAM_CS1), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_WE_B), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_RE_B), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_ALE), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CLE), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_WP_B), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB0), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB1), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB2), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB3), + IMX_PINCTRL_PIN(MX51_PAD_GPIO_NAND), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS0), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS1), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS2), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS3), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS4), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS5), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS6), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS7), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_RDY_INT), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D15), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D14), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D13), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D12), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D11), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D10), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D9), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D8), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D7), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D6), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D5), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D4), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D3), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D2), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D1), + IMX_PINCTRL_PIN(MX51_PAD_NANDF_D0), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D8), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D9), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D10), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D11), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D12), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D13), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D14), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D15), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D16), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D17), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D18), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_D15), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_D16), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_D17), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_D18), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_D19), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_VSYNC), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_HSYNC), + IMX_PINCTRL_PIN(MX51_PAD_CSI2_PIXCLK), + IMX_PINCTRL_PIN(MX51_PAD_I2C1_CLK), + IMX_PINCTRL_PIN(MX51_PAD_I2C1_DAT), + IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_TXD), + IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_RXD), + IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_CK), + IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_FS), + IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MOSI), + IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX51_PAD_CSPI1_RDY), + IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX51_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX51_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX51_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX51_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX51_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX51_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX51_PAD_UART3_RXD), + IMX_PINCTRL_PIN(MX51_PAD_UART3_TXD), + IMX_PINCTRL_PIN(MX51_PAD_OWIRE_LINE), + IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX51_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX51_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX51_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_NXT), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA0), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA1), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA2), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA3), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA4), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA5), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA6), + IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA7), + IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN11), + IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN12), + IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN13), + IMX_PINCTRL_PIN(MX51_PAD_DI1_D0_CS), + IMX_PINCTRL_PIN(MX51_PAD_DI1_D1_CS), + IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIN), + IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIO), + IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_CLK), + IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_RS), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT0), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT1), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT2), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT3), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT4), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT5), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT6), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT7), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT8), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT9), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT10), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT11), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT12), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT13), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT14), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT15), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT16), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT17), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT18), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT19), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT20), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT21), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT22), + IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23), + IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3), + IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX51_PAD_DI_GP2), + IMX_PINCTRL_PIN(MX51_PAD_DI_GP3), + IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4), + IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN2), + IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN3), + IMX_PINCTRL_PIN(MX51_PAD_DI2_DISP_CLK), + IMX_PINCTRL_PIN(MX51_PAD_DI_GP4), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT0), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT1), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT2), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT3), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT4), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT5), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT6), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT7), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT8), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT9), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT10), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT11), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT12), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT13), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT14), + IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT15), + IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1), + IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0), + IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA1), + IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA2), + IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA3), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_2), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_3), + IMX_PINCTRL_PIN(MX51_PAD_PMIC_INT_REQ), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_4), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_5), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_6), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8), + IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE19), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE20), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE21), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE22), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE23), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE24), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE25), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE26), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE27), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE28), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE29), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE30), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE31), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE32), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE33), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE34), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE35), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE36), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE37), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE38), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE39), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE40), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE41), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE42), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE43), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE44), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE45), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE46), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE47), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE48), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE49), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE50), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE51), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE52), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE53), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE54), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE55), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE56), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE57), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE58), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE59), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE60), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE61), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE62), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE63), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE64), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE65), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE66), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE67), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE68), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE69), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE70), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE71), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE72), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE73), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE74), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE75), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE76), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE77), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE78), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE79), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE80), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE81), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE82), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE83), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE84), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE85), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE86), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE87), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE88), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE89), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE90), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE91), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE92), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE93), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE94), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE95), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE96), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE97), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE98), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE99), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE100), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE101), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE102), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE103), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE104), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE105), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE106), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE107), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE108), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE109), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE110), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE111), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE112), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE113), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE114), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE115), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE116), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE117), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE118), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE119), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE120), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE121), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK), +}; + +static struct imx_pinctrl_soc_info imx51_pinctrl_info = { + .pins = imx51_pinctrl_pads, + .npins = ARRAY_SIZE(imx51_pinctrl_pads), +}; + +static const struct of_device_id imx51_pinctrl_of_match[] = { + { .compatible = "fsl,imx51-iomuxc", }, + { /* sentinel */ } +}; + +static int imx51_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx51_pinctrl_info); +} + +static struct platform_driver imx51_pinctrl_driver = { + .driver = { + .name = "imx51-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx51_pinctrl_of_match, + }, + .probe = imx51_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx51_pinctrl_init(void) +{ + return platform_driver_register(&imx51_pinctrl_driver); +} +arch_initcall(imx51_pinctrl_init); + +static void __exit imx51_pinctrl_exit(void) +{ + platform_driver_unregister(&imx51_pinctrl_driver); +} +module_exit(imx51_pinctrl_exit); +MODULE_AUTHOR("Dong Aisheng "); +MODULE_DESCRIPTION("Freescale IMX51 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c new file mode 100644 index 000000000000..1884d53cf750 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx53.c @@ -0,0 +1,490 @@ +/* + * imx53 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro, Inc. + * + * Author: Dong Aisheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx53_pads { + MX53_PAD_RESERVE0 = 0, + MX53_PAD_RESERVE1 = 1, + MX53_PAD_RESERVE2 = 2, + MX53_PAD_RESERVE3 = 3, + MX53_PAD_RESERVE4 = 4, + MX53_PAD_RESERVE5 = 5, + MX53_PAD_RESERVE6 = 6, + MX53_PAD_RESERVE7 = 7, + MX53_PAD_GPIO_19 = 8, + MX53_PAD_KEY_COL0 = 9, + MX53_PAD_KEY_ROW0 = 10, + MX53_PAD_KEY_COL1 = 11, + MX53_PAD_KEY_ROW1 = 12, + MX53_PAD_KEY_COL2 = 13, + MX53_PAD_KEY_ROW2 = 14, + MX53_PAD_KEY_COL3 = 15, + MX53_PAD_KEY_ROW3 = 16, + MX53_PAD_KEY_COL4 = 17, + MX53_PAD_KEY_ROW4 = 18, + MX53_PAD_DI0_DISP_CLK = 19, + MX53_PAD_DI0_PIN15 = 20, + MX53_PAD_DI0_PIN2 = 21, + MX53_PAD_DI0_PIN3 = 22, + MX53_PAD_DI0_PIN4 = 23, + MX53_PAD_DISP0_DAT0 = 24, + MX53_PAD_DISP0_DAT1 = 25, + MX53_PAD_DISP0_DAT2 = 26, + MX53_PAD_DISP0_DAT3 = 27, + MX53_PAD_DISP0_DAT4 = 28, + MX53_PAD_DISP0_DAT5 = 29, + MX53_PAD_DISP0_DAT6 = 30, + MX53_PAD_DISP0_DAT7 = 31, + MX53_PAD_DISP0_DAT8 = 32, + MX53_PAD_DISP0_DAT9 = 33, + MX53_PAD_DISP0_DAT10 = 34, + MX53_PAD_DISP0_DAT11 = 35, + MX53_PAD_DISP0_DAT12 = 36, + MX53_PAD_DISP0_DAT13 = 37, + MX53_PAD_DISP0_DAT14 = 38, + MX53_PAD_DISP0_DAT15 = 39, + MX53_PAD_DISP0_DAT16 = 40, + MX53_PAD_DISP0_DAT17 = 41, + MX53_PAD_DISP0_DAT18 = 42, + MX53_PAD_DISP0_DAT19 = 43, + MX53_PAD_DISP0_DAT20 = 44, + MX53_PAD_DISP0_DAT21 = 45, + MX53_PAD_DISP0_DAT22 = 46, + MX53_PAD_DISP0_DAT23 = 47, + MX53_PAD_CSI0_PIXCLK = 48, + MX53_PAD_CSI0_MCLK = 49, + MX53_PAD_CSI0_DATA_EN = 50, + MX53_PAD_CSI0_VSYNC = 51, + MX53_PAD_CSI0_DAT4 = 52, + MX53_PAD_CSI0_DAT5 = 53, + MX53_PAD_CSI0_DAT6 = 54, + MX53_PAD_CSI0_DAT7 = 55, + MX53_PAD_CSI0_DAT8 = 56, + MX53_PAD_CSI0_DAT9 = 57, + MX53_PAD_CSI0_DAT10 = 58, + MX53_PAD_CSI0_DAT11 = 59, + MX53_PAD_CSI0_DAT12 = 60, + MX53_PAD_CSI0_DAT13 = 61, + MX53_PAD_CSI0_DAT14 = 62, + MX53_PAD_CSI0_DAT15 = 63, + MX53_PAD_CSI0_DAT16 = 64, + MX53_PAD_CSI0_DAT17 = 65, + MX53_PAD_CSI0_DAT18 = 66, + MX53_PAD_CSI0_DAT19 = 67, + MX53_PAD_EIM_A25 = 68, + MX53_PAD_EIM_EB2 = 69, + MX53_PAD_EIM_D16 = 70, + MX53_PAD_EIM_D17 = 71, + MX53_PAD_EIM_D18 = 72, + MX53_PAD_EIM_D19 = 73, + MX53_PAD_EIM_D20 = 74, + MX53_PAD_EIM_D21 = 75, + MX53_PAD_EIM_D22 = 76, + MX53_PAD_EIM_D23 = 77, + MX53_PAD_EIM_EB3 = 78, + MX53_PAD_EIM_D24 = 79, + MX53_PAD_EIM_D25 = 80, + MX53_PAD_EIM_D26 = 81, + MX53_PAD_EIM_D27 = 82, + MX53_PAD_EIM_D28 = 83, + MX53_PAD_EIM_D29 = 84, + MX53_PAD_EIM_D30 = 85, + MX53_PAD_EIM_D31 = 86, + MX53_PAD_EIM_A24 = 87, + MX53_PAD_EIM_A23 = 88, + MX53_PAD_EIM_A22 = 89, + MX53_PAD_EIM_A21 = 90, + MX53_PAD_EIM_A20 = 91, + MX53_PAD_EIM_A19 = 92, + MX53_PAD_EIM_A18 = 93, + MX53_PAD_EIM_A17 = 94, + MX53_PAD_EIM_A16 = 95, + MX53_PAD_EIM_CS0 = 96, + MX53_PAD_EIM_CS1 = 97, + MX53_PAD_EIM_OE = 98, + MX53_PAD_EIM_RW = 99, + MX53_PAD_EIM_LBA = 100, + MX53_PAD_EIM_EB0 = 101, + MX53_PAD_EIM_EB1 = 102, + MX53_PAD_EIM_DA0 = 103, + MX53_PAD_EIM_DA1 = 104, + MX53_PAD_EIM_DA2 = 105, + MX53_PAD_EIM_DA3 = 106, + MX53_PAD_EIM_DA4 = 107, + MX53_PAD_EIM_DA5 = 108, + MX53_PAD_EIM_DA6 = 109, + MX53_PAD_EIM_DA7 = 110, + MX53_PAD_EIM_DA8 = 111, + MX53_PAD_EIM_DA9 = 112, + MX53_PAD_EIM_DA10 = 113, + MX53_PAD_EIM_DA11 = 114, + MX53_PAD_EIM_DA12 = 115, + MX53_PAD_EIM_DA13 = 116, + MX53_PAD_EIM_DA14 = 117, + MX53_PAD_EIM_DA15 = 118, + MX53_PAD_NANDF_WE_B = 119, + MX53_PAD_NANDF_RE_B = 120, + MX53_PAD_EIM_WAIT = 121, + MX53_PAD_RESERVE8 = 122, + MX53_PAD_LVDS1_TX3_P = 123, + MX53_PAD_LVDS1_TX2_P = 124, + MX53_PAD_LVDS1_CLK_P = 125, + MX53_PAD_LVDS1_TX1_P = 126, + MX53_PAD_LVDS1_TX0_P = 127, + MX53_PAD_LVDS0_TX3_P = 128, + MX53_PAD_LVDS0_CLK_P = 129, + MX53_PAD_LVDS0_TX2_P = 130, + MX53_PAD_LVDS0_TX1_P = 131, + MX53_PAD_LVDS0_TX0_P = 132, + MX53_PAD_GPIO_10 = 133, + MX53_PAD_GPIO_11 = 134, + MX53_PAD_GPIO_12 = 135, + MX53_PAD_GPIO_13 = 136, + MX53_PAD_GPIO_14 = 137, + MX53_PAD_NANDF_CLE = 138, + MX53_PAD_NANDF_ALE = 139, + MX53_PAD_NANDF_WP_B = 140, + MX53_PAD_NANDF_RB0 = 141, + MX53_PAD_NANDF_CS0 = 142, + MX53_PAD_NANDF_CS1 = 143, + MX53_PAD_NANDF_CS2 = 144, + MX53_PAD_NANDF_CS3 = 145, + MX53_PAD_FEC_MDIO = 146, + MX53_PAD_FEC_REF_CLK = 147, + MX53_PAD_FEC_RX_ER = 148, + MX53_PAD_FEC_CRS_DV = 149, + MX53_PAD_FEC_RXD1 = 150, + MX53_PAD_FEC_RXD0 = 151, + MX53_PAD_FEC_TX_EN = 152, + MX53_PAD_FEC_TXD1 = 153, + MX53_PAD_FEC_TXD0 = 154, + MX53_PAD_FEC_MDC = 155, + MX53_PAD_PATA_DIOW = 156, + MX53_PAD_PATA_DMACK = 157, + MX53_PAD_PATA_DMARQ = 158, + MX53_PAD_PATA_BUFFER_EN = 159, + MX53_PAD_PATA_INTRQ = 160, + MX53_PAD_PATA_DIOR = 161, + MX53_PAD_PATA_RESET_B = 162, + MX53_PAD_PATA_IORDY = 163, + MX53_PAD_PATA_DA_0 = 164, + MX53_PAD_PATA_DA_1 = 165, + MX53_PAD_PATA_DA_2 = 166, + MX53_PAD_PATA_CS_0 = 167, + MX53_PAD_PATA_CS_1 = 168, + MX53_PAD_PATA_DATA0 = 169, + MX53_PAD_PATA_DATA1 = 170, + MX53_PAD_PATA_DATA2 = 171, + MX53_PAD_PATA_DATA3 = 172, + MX53_PAD_PATA_DATA4 = 173, + MX53_PAD_PATA_DATA5 = 174, + MX53_PAD_PATA_DATA6 = 175, + MX53_PAD_PATA_DATA7 = 176, + MX53_PAD_PATA_DATA8 = 177, + MX53_PAD_PATA_DATA9 = 178, + MX53_PAD_PATA_DATA10 = 179, + MX53_PAD_PATA_DATA11 = 180, + MX53_PAD_PATA_DATA12 = 181, + MX53_PAD_PATA_DATA13 = 182, + MX53_PAD_PATA_DATA14 = 183, + MX53_PAD_PATA_DATA15 = 184, + MX53_PAD_SD1_DATA0 = 185, + MX53_PAD_SD1_DATA1 = 186, + MX53_PAD_SD1_CMD = 187, + MX53_PAD_SD1_DATA2 = 188, + MX53_PAD_SD1_CLK = 189, + MX53_PAD_SD1_DATA3 = 190, + MX53_PAD_SD2_CLK = 191, + MX53_PAD_SD2_CMD = 192, + MX53_PAD_SD2_DATA3 = 193, + MX53_PAD_SD2_DATA2 = 194, + MX53_PAD_SD2_DATA1 = 195, + MX53_PAD_SD2_DATA0 = 196, + MX53_PAD_GPIO_0 = 197, + MX53_PAD_GPIO_1 = 198, + MX53_PAD_GPIO_9 = 199, + MX53_PAD_GPIO_3 = 200, + MX53_PAD_GPIO_6 = 201, + MX53_PAD_GPIO_2 = 202, + MX53_PAD_GPIO_4 = 203, + MX53_PAD_GPIO_5 = 204, + MX53_PAD_GPIO_7 = 205, + MX53_PAD_GPIO_8 = 206, + MX53_PAD_GPIO_16 = 207, + MX53_PAD_GPIO_17 = 208, + MX53_PAD_GPIO_18 = 209, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX53_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_19), + IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX53_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX53_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX53_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX53_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX53_PAD_DI0_DISP_CLK), + IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN15), + IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN2), + IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN3), + IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN4), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT0), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT1), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT2), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT3), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT4), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT5), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT6), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT7), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT8), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT9), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT10), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT11), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT12), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT13), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT14), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT15), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT16), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT17), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT18), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT19), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT20), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT21), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT22), + IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT23), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_PIXCLK), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_MCLK), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DATA_EN), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_VSYNC), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT4), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT5), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT6), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT7), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT8), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT9), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT10), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT11), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT12), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT13), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT14), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT15), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT16), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT17), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT18), + IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT19), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A25), + IMX_PINCTRL_PIN(MX53_PAD_EIM_EB2), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D16), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D17), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D18), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D19), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D20), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D21), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D22), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D23), + IMX_PINCTRL_PIN(MX53_PAD_EIM_EB3), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D24), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D25), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D26), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D27), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D28), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D29), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D30), + IMX_PINCTRL_PIN(MX53_PAD_EIM_D31), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A24), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A23), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A22), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A21), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A20), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A19), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A18), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A17), + IMX_PINCTRL_PIN(MX53_PAD_EIM_A16), + IMX_PINCTRL_PIN(MX53_PAD_EIM_CS0), + IMX_PINCTRL_PIN(MX53_PAD_EIM_CS1), + IMX_PINCTRL_PIN(MX53_PAD_EIM_OE), + IMX_PINCTRL_PIN(MX53_PAD_EIM_RW), + IMX_PINCTRL_PIN(MX53_PAD_EIM_LBA), + IMX_PINCTRL_PIN(MX53_PAD_EIM_EB0), + IMX_PINCTRL_PIN(MX53_PAD_EIM_EB1), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA0), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA1), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA2), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA3), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA4), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA5), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA6), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA7), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA8), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA9), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA10), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA11), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA12), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA13), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA14), + IMX_PINCTRL_PIN(MX53_PAD_EIM_DA15), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B), + IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX1_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX0_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX3_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS0_CLK_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX2_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX1_P), + IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX0_P), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_10), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_11), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_12), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_13), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_14), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_CLE), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_ALE), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_WP_B), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_RB0), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS0), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS1), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS2), + IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS3), + IMX_PINCTRL_PIN(MX53_PAD_FEC_MDIO), + IMX_PINCTRL_PIN(MX53_PAD_FEC_REF_CLK), + IMX_PINCTRL_PIN(MX53_PAD_FEC_RX_ER), + IMX_PINCTRL_PIN(MX53_PAD_FEC_CRS_DV), + IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD1), + IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD0), + IMX_PINCTRL_PIN(MX53_PAD_FEC_TX_EN), + IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD1), + IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD0), + IMX_PINCTRL_PIN(MX53_PAD_FEC_MDC), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOW), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DMACK), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DMARQ), + IMX_PINCTRL_PIN(MX53_PAD_PATA_BUFFER_EN), + IMX_PINCTRL_PIN(MX53_PAD_PATA_INTRQ), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOR), + IMX_PINCTRL_PIN(MX53_PAD_PATA_RESET_B), + IMX_PINCTRL_PIN(MX53_PAD_PATA_IORDY), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_0), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_1), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_2), + IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_0), + IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_1), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA0), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA1), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA2), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA3), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA4), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA5), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA6), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA7), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA8), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA9), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA10), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA11), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA12), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA13), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA14), + IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA15), + IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX53_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX53_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX53_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX53_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA3), + IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA2), + IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA1), + IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA0), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_0), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_1), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_9), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_3), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_6), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_2), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_4), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_5), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_7), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_8), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_16), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_17), + IMX_PINCTRL_PIN(MX53_PAD_GPIO_18), +}; + +static struct imx_pinctrl_soc_info imx53_pinctrl_info = { + .pins = imx53_pinctrl_pads, + .npins = ARRAY_SIZE(imx53_pinctrl_pads), +}; + +static const struct of_device_id imx53_pinctrl_of_match[] = { + { .compatible = "fsl,imx53-iomuxc", }, + { /* sentinel */ } +}; + +static int imx53_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx53_pinctrl_info); +} + +static struct platform_driver imx53_pinctrl_driver = { + .driver = { + .name = "imx53-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx53_pinctrl_of_match, + }, + .probe = imx53_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx53_pinctrl_init(void) +{ + return platform_driver_register(&imx53_pinctrl_driver); +} +arch_initcall(imx53_pinctrl_init); + +static void __exit imx53_pinctrl_exit(void) +{ + platform_driver_unregister(&imx53_pinctrl_driver); +} +module_exit(imx53_pinctrl_exit); +MODULE_AUTHOR("Dong Aisheng "); +MODULE_DESCRIPTION("Freescale IMX53 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c new file mode 100644 index 000000000000..656c4b08cc2e --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c @@ -0,0 +1,497 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx6dl_pads { + MX6DL_PAD_RESERVE0 = 0, + MX6DL_PAD_RESERVE1 = 1, + MX6DL_PAD_RESERVE2 = 2, + MX6DL_PAD_RESERVE3 = 3, + MX6DL_PAD_RESERVE4 = 4, + MX6DL_PAD_RESERVE5 = 5, + MX6DL_PAD_RESERVE6 = 6, + MX6DL_PAD_RESERVE7 = 7, + MX6DL_PAD_RESERVE8 = 8, + MX6DL_PAD_RESERVE9 = 9, + MX6DL_PAD_RESERVE10 = 10, + MX6DL_PAD_RESERVE11 = 11, + MX6DL_PAD_RESERVE12 = 12, + MX6DL_PAD_RESERVE13 = 13, + MX6DL_PAD_RESERVE14 = 14, + MX6DL_PAD_RESERVE15 = 15, + MX6DL_PAD_RESERVE16 = 16, + MX6DL_PAD_RESERVE17 = 17, + MX6DL_PAD_RESERVE18 = 18, + MX6DL_PAD_CSI0_DAT10 = 19, + MX6DL_PAD_CSI0_DAT11 = 20, + MX6DL_PAD_CSI0_DAT12 = 21, + MX6DL_PAD_CSI0_DAT13 = 22, + MX6DL_PAD_CSI0_DAT14 = 23, + MX6DL_PAD_CSI0_DAT15 = 24, + MX6DL_PAD_CSI0_DAT16 = 25, + MX6DL_PAD_CSI0_DAT17 = 26, + MX6DL_PAD_CSI0_DAT18 = 27, + MX6DL_PAD_CSI0_DAT19 = 28, + MX6DL_PAD_CSI0_DAT4 = 29, + MX6DL_PAD_CSI0_DAT5 = 30, + MX6DL_PAD_CSI0_DAT6 = 31, + MX6DL_PAD_CSI0_DAT7 = 32, + MX6DL_PAD_CSI0_DAT8 = 33, + MX6DL_PAD_CSI0_DAT9 = 34, + MX6DL_PAD_CSI0_DATA_EN = 35, + MX6DL_PAD_CSI0_MCLK = 36, + MX6DL_PAD_CSI0_PIXCLK = 37, + MX6DL_PAD_CSI0_VSYNC = 38, + MX6DL_PAD_DI0_DISP_CLK = 39, + MX6DL_PAD_DI0_PIN15 = 40, + MX6DL_PAD_DI0_PIN2 = 41, + MX6DL_PAD_DI0_PIN3 = 42, + MX6DL_PAD_DI0_PIN4 = 43, + MX6DL_PAD_DISP0_DAT0 = 44, + MX6DL_PAD_DISP0_DAT1 = 45, + MX6DL_PAD_DISP0_DAT10 = 46, + MX6DL_PAD_DISP0_DAT11 = 47, + MX6DL_PAD_DISP0_DAT12 = 48, + MX6DL_PAD_DISP0_DAT13 = 49, + MX6DL_PAD_DISP0_DAT14 = 50, + MX6DL_PAD_DISP0_DAT15 = 51, + MX6DL_PAD_DISP0_DAT16 = 52, + MX6DL_PAD_DISP0_DAT17 = 53, + MX6DL_PAD_DISP0_DAT18 = 54, + MX6DL_PAD_DISP0_DAT19 = 55, + MX6DL_PAD_DISP0_DAT2 = 56, + MX6DL_PAD_DISP0_DAT20 = 57, + MX6DL_PAD_DISP0_DAT21 = 58, + MX6DL_PAD_DISP0_DAT22 = 59, + MX6DL_PAD_DISP0_DAT23 = 60, + MX6DL_PAD_DISP0_DAT3 = 61, + MX6DL_PAD_DISP0_DAT4 = 62, + MX6DL_PAD_DISP0_DAT5 = 63, + MX6DL_PAD_DISP0_DAT6 = 64, + MX6DL_PAD_DISP0_DAT7 = 65, + MX6DL_PAD_DISP0_DAT8 = 66, + MX6DL_PAD_DISP0_DAT9 = 67, + MX6DL_PAD_EIM_A16 = 68, + MX6DL_PAD_EIM_A17 = 69, + MX6DL_PAD_EIM_A18 = 70, + MX6DL_PAD_EIM_A19 = 71, + MX6DL_PAD_EIM_A20 = 72, + MX6DL_PAD_EIM_A21 = 73, + MX6DL_PAD_EIM_A22 = 74, + MX6DL_PAD_EIM_A23 = 75, + MX6DL_PAD_EIM_A24 = 76, + MX6DL_PAD_EIM_A25 = 77, + MX6DL_PAD_EIM_BCLK = 78, + MX6DL_PAD_EIM_CS0 = 79, + MX6DL_PAD_EIM_CS1 = 80, + MX6DL_PAD_EIM_D16 = 81, + MX6DL_PAD_EIM_D17 = 82, + MX6DL_PAD_EIM_D18 = 83, + MX6DL_PAD_EIM_D19 = 84, + MX6DL_PAD_EIM_D20 = 85, + MX6DL_PAD_EIM_D21 = 86, + MX6DL_PAD_EIM_D22 = 87, + MX6DL_PAD_EIM_D23 = 88, + MX6DL_PAD_EIM_D24 = 89, + MX6DL_PAD_EIM_D25 = 90, + MX6DL_PAD_EIM_D26 = 91, + MX6DL_PAD_EIM_D27 = 92, + MX6DL_PAD_EIM_D28 = 93, + MX6DL_PAD_EIM_D29 = 94, + MX6DL_PAD_EIM_D30 = 95, + MX6DL_PAD_EIM_D31 = 96, + MX6DL_PAD_EIM_DA0 = 97, + MX6DL_PAD_EIM_DA1 = 98, + MX6DL_PAD_EIM_DA10 = 99, + MX6DL_PAD_EIM_DA11 = 100, + MX6DL_PAD_EIM_DA12 = 101, + MX6DL_PAD_EIM_DA13 = 102, + MX6DL_PAD_EIM_DA14 = 103, + MX6DL_PAD_EIM_DA15 = 104, + MX6DL_PAD_EIM_DA2 = 105, + MX6DL_PAD_EIM_DA3 = 106, + MX6DL_PAD_EIM_DA4 = 107, + MX6DL_PAD_EIM_DA5 = 108, + MX6DL_PAD_EIM_DA6 = 109, + MX6DL_PAD_EIM_DA7 = 110, + MX6DL_PAD_EIM_DA8 = 111, + MX6DL_PAD_EIM_DA9 = 112, + MX6DL_PAD_EIM_EB0 = 113, + MX6DL_PAD_EIM_EB1 = 114, + MX6DL_PAD_EIM_EB2 = 115, + MX6DL_PAD_EIM_EB3 = 116, + MX6DL_PAD_EIM_LBA = 117, + MX6DL_PAD_EIM_OE = 118, + MX6DL_PAD_EIM_RW = 119, + MX6DL_PAD_EIM_WAIT = 120, + MX6DL_PAD_ENET_CRS_DV = 121, + MX6DL_PAD_ENET_MDC = 122, + MX6DL_PAD_ENET_MDIO = 123, + MX6DL_PAD_ENET_REF_CLK = 124, + MX6DL_PAD_ENET_RX_ER = 125, + MX6DL_PAD_ENET_RXD0 = 126, + MX6DL_PAD_ENET_RXD1 = 127, + MX6DL_PAD_ENET_TX_EN = 128, + MX6DL_PAD_ENET_TXD0 = 129, + MX6DL_PAD_ENET_TXD1 = 130, + MX6DL_PAD_GPIO_0 = 131, + MX6DL_PAD_GPIO_1 = 132, + MX6DL_PAD_GPIO_16 = 133, + MX6DL_PAD_GPIO_17 = 134, + MX6DL_PAD_GPIO_18 = 135, + MX6DL_PAD_GPIO_19 = 136, + MX6DL_PAD_GPIO_2 = 137, + MX6DL_PAD_GPIO_3 = 138, + MX6DL_PAD_GPIO_4 = 139, + MX6DL_PAD_GPIO_5 = 140, + MX6DL_PAD_GPIO_6 = 141, + MX6DL_PAD_GPIO_7 = 142, + MX6DL_PAD_GPIO_8 = 143, + MX6DL_PAD_GPIO_9 = 144, + MX6DL_PAD_KEY_COL0 = 145, + MX6DL_PAD_KEY_COL1 = 146, + MX6DL_PAD_KEY_COL2 = 147, + MX6DL_PAD_KEY_COL3 = 148, + MX6DL_PAD_KEY_COL4 = 149, + MX6DL_PAD_KEY_ROW0 = 150, + MX6DL_PAD_KEY_ROW1 = 151, + MX6DL_PAD_KEY_ROW2 = 152, + MX6DL_PAD_KEY_ROW3 = 153, + MX6DL_PAD_KEY_ROW4 = 154, + MX6DL_PAD_NANDF_ALE = 155, + MX6DL_PAD_NANDF_CLE = 156, + MX6DL_PAD_NANDF_CS0 = 157, + MX6DL_PAD_NANDF_CS1 = 158, + MX6DL_PAD_NANDF_CS2 = 159, + MX6DL_PAD_NANDF_CS3 = 160, + MX6DL_PAD_NANDF_D0 = 161, + MX6DL_PAD_NANDF_D1 = 162, + MX6DL_PAD_NANDF_D2 = 163, + MX6DL_PAD_NANDF_D3 = 164, + MX6DL_PAD_NANDF_D4 = 165, + MX6DL_PAD_NANDF_D5 = 166, + MX6DL_PAD_NANDF_D6 = 167, + MX6DL_PAD_NANDF_D7 = 168, + MX6DL_PAD_NANDF_RB0 = 169, + MX6DL_PAD_NANDF_WP_B = 170, + MX6DL_PAD_RGMII_RD0 = 171, + MX6DL_PAD_RGMII_RD1 = 172, + MX6DL_PAD_RGMII_RD2 = 173, + MX6DL_PAD_RGMII_RD3 = 174, + MX6DL_PAD_RGMII_RX_CTL = 175, + MX6DL_PAD_RGMII_RXC = 176, + MX6DL_PAD_RGMII_TD0 = 177, + MX6DL_PAD_RGMII_TD1 = 178, + MX6DL_PAD_RGMII_TD2 = 179, + MX6DL_PAD_RGMII_TD3 = 180, + MX6DL_PAD_RGMII_TX_CTL = 181, + MX6DL_PAD_RGMII_TXC = 182, + MX6DL_PAD_SD1_CLK = 183, + MX6DL_PAD_SD1_CMD = 184, + MX6DL_PAD_SD1_DAT0 = 185, + MX6DL_PAD_SD1_DAT1 = 186, + MX6DL_PAD_SD1_DAT2 = 187, + MX6DL_PAD_SD1_DAT3 = 188, + MX6DL_PAD_SD2_CLK = 189, + MX6DL_PAD_SD2_CMD = 190, + MX6DL_PAD_SD2_DAT0 = 191, + MX6DL_PAD_SD2_DAT1 = 192, + MX6DL_PAD_SD2_DAT2 = 193, + MX6DL_PAD_SD2_DAT3 = 194, + MX6DL_PAD_SD3_CLK = 195, + MX6DL_PAD_SD3_CMD = 196, + MX6DL_PAD_SD3_DAT0 = 197, + MX6DL_PAD_SD3_DAT1 = 198, + MX6DL_PAD_SD3_DAT2 = 199, + MX6DL_PAD_SD3_DAT3 = 200, + MX6DL_PAD_SD3_DAT4 = 201, + MX6DL_PAD_SD3_DAT5 = 202, + MX6DL_PAD_SD3_DAT6 = 203, + MX6DL_PAD_SD3_DAT7 = 204, + MX6DL_PAD_SD3_RST = 205, + MX6DL_PAD_SD4_CLK = 206, + MX6DL_PAD_SD4_CMD = 207, + MX6DL_PAD_SD4_DAT0 = 208, + MX6DL_PAD_SD4_DAT1 = 209, + MX6DL_PAD_SD4_DAT2 = 210, + MX6DL_PAD_SD4_DAT3 = 211, + MX6DL_PAD_SD4_DAT4 = 212, + MX6DL_PAD_SD4_DAT5 = 213, + MX6DL_PAD_SD4_DAT6 = 214, + MX6DL_PAD_SD4_DAT7 = 215, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT10), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT11), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT12), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT13), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT14), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT15), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT16), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT17), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT18), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT19), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT4), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT5), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT6), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT7), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT8), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT9), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DATA_EN), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_MCLK), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_PIXCLK), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_VSYNC), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_DISP_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN15), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN2), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN3), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN4), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT10), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT11), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT12), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT13), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT14), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT15), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT16), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT17), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT18), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT19), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT20), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT21), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT22), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT23), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT4), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT5), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT6), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT7), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT8), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT9), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A16), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A17), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A18), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A19), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A20), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A21), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A22), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A23), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A24), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A25), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_BCLK), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS0), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS1), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D16), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D17), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D18), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D19), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D20), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D21), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D22), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D23), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D24), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D25), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D26), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D27), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D28), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D29), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D30), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D31), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA0), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA1), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA10), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA11), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA12), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA13), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA14), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA15), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA2), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA3), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA4), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA5), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA6), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA7), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA8), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA9), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB0), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB1), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB2), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB3), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_LBA), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_OE), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_RW), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_WAIT), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_CRS_DV), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDC), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDIO), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_REF_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RX_ER), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD0), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD1), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TX_EN), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD0), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD1), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_0), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_1), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_16), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_17), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_18), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_19), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_2), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_3), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_4), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_5), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_6), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_7), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_8), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_9), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_ALE), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CLE), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS0), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS1), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS2), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS3), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D0), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D1), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D2), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D3), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D4), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D5), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D6), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D7), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_RB0), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_WP_B), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD0), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD1), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD2), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD3), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RX_CTL), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RXC), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD0), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD1), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD2), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD3), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TX_CTL), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TXC), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT4), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT5), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT6), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT7), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_RST), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CMD), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT4), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7), +}; + +static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = { + .pins = imx6dl_pinctrl_pads, + .npins = ARRAY_SIZE(imx6dl_pinctrl_pads), +}; + +static const struct of_device_id imx6dl_pinctrl_of_match[] = { + { .compatible = "fsl,imx6dl-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6dl_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6dl_pinctrl_info); +} + +static struct platform_driver imx6dl_pinctrl_driver = { + .driver = { + .name = "imx6dl-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx6dl_pinctrl_of_match, + }, + .probe = imx6dl_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6dl_pinctrl_init(void) +{ + return platform_driver_register(&imx6dl_pinctrl_driver); +} +arch_initcall(imx6dl_pinctrl_init); + +static void __exit imx6dl_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6dl_pinctrl_driver); +} +module_exit(imx6dl_pinctrl_exit); + +MODULE_AUTHOR("Shawn Guo "); +MODULE_DESCRIPTION("Freescale imx6dl pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c new file mode 100644 index 000000000000..59bb5b4ec0f6 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c @@ -0,0 +1,502 @@ +/* + * imx6q pinctrl driver based on imx pinmux core + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro, Inc. + * + * Author: Dong Aisheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx6q_pads { + MX6Q_PAD_RESERVE0 = 0, + MX6Q_PAD_RESERVE1 = 1, + MX6Q_PAD_RESERVE2 = 2, + MX6Q_PAD_RESERVE3 = 3, + MX6Q_PAD_RESERVE4 = 4, + MX6Q_PAD_RESERVE5 = 5, + MX6Q_PAD_RESERVE6 = 6, + MX6Q_PAD_RESERVE7 = 7, + MX6Q_PAD_RESERVE8 = 8, + MX6Q_PAD_RESERVE9 = 9, + MX6Q_PAD_RESERVE10 = 10, + MX6Q_PAD_RESERVE11 = 11, + MX6Q_PAD_RESERVE12 = 12, + MX6Q_PAD_RESERVE13 = 13, + MX6Q_PAD_RESERVE14 = 14, + MX6Q_PAD_RESERVE15 = 15, + MX6Q_PAD_RESERVE16 = 16, + MX6Q_PAD_RESERVE17 = 17, + MX6Q_PAD_RESERVE18 = 18, + MX6Q_PAD_SD2_DAT1 = 19, + MX6Q_PAD_SD2_DAT2 = 20, + MX6Q_PAD_SD2_DAT0 = 21, + MX6Q_PAD_RGMII_TXC = 22, + MX6Q_PAD_RGMII_TD0 = 23, + MX6Q_PAD_RGMII_TD1 = 24, + MX6Q_PAD_RGMII_TD2 = 25, + MX6Q_PAD_RGMII_TD3 = 26, + MX6Q_PAD_RGMII_RX_CTL = 27, + MX6Q_PAD_RGMII_RD0 = 28, + MX6Q_PAD_RGMII_TX_CTL = 29, + MX6Q_PAD_RGMII_RD1 = 30, + MX6Q_PAD_RGMII_RD2 = 31, + MX6Q_PAD_RGMII_RD3 = 32, + MX6Q_PAD_RGMII_RXC = 33, + MX6Q_PAD_EIM_A25 = 34, + MX6Q_PAD_EIM_EB2 = 35, + MX6Q_PAD_EIM_D16 = 36, + MX6Q_PAD_EIM_D17 = 37, + MX6Q_PAD_EIM_D18 = 38, + MX6Q_PAD_EIM_D19 = 39, + MX6Q_PAD_EIM_D20 = 40, + MX6Q_PAD_EIM_D21 = 41, + MX6Q_PAD_EIM_D22 = 42, + MX6Q_PAD_EIM_D23 = 43, + MX6Q_PAD_EIM_EB3 = 44, + MX6Q_PAD_EIM_D24 = 45, + MX6Q_PAD_EIM_D25 = 46, + MX6Q_PAD_EIM_D26 = 47, + MX6Q_PAD_EIM_D27 = 48, + MX6Q_PAD_EIM_D28 = 49, + MX6Q_PAD_EIM_D29 = 50, + MX6Q_PAD_EIM_D30 = 51, + MX6Q_PAD_EIM_D31 = 52, + MX6Q_PAD_EIM_A24 = 53, + MX6Q_PAD_EIM_A23 = 54, + MX6Q_PAD_EIM_A22 = 55, + MX6Q_PAD_EIM_A21 = 56, + MX6Q_PAD_EIM_A20 = 57, + MX6Q_PAD_EIM_A19 = 58, + MX6Q_PAD_EIM_A18 = 59, + MX6Q_PAD_EIM_A17 = 60, + MX6Q_PAD_EIM_A16 = 61, + MX6Q_PAD_EIM_CS0 = 62, + MX6Q_PAD_EIM_CS1 = 63, + MX6Q_PAD_EIM_OE = 64, + MX6Q_PAD_EIM_RW = 65, + MX6Q_PAD_EIM_LBA = 66, + MX6Q_PAD_EIM_EB0 = 67, + MX6Q_PAD_EIM_EB1 = 68, + MX6Q_PAD_EIM_DA0 = 69, + MX6Q_PAD_EIM_DA1 = 70, + MX6Q_PAD_EIM_DA2 = 71, + MX6Q_PAD_EIM_DA3 = 72, + MX6Q_PAD_EIM_DA4 = 73, + MX6Q_PAD_EIM_DA5 = 74, + MX6Q_PAD_EIM_DA6 = 75, + MX6Q_PAD_EIM_DA7 = 76, + MX6Q_PAD_EIM_DA8 = 77, + MX6Q_PAD_EIM_DA9 = 78, + MX6Q_PAD_EIM_DA10 = 79, + MX6Q_PAD_EIM_DA11 = 80, + MX6Q_PAD_EIM_DA12 = 81, + MX6Q_PAD_EIM_DA13 = 82, + MX6Q_PAD_EIM_DA14 = 83, + MX6Q_PAD_EIM_DA15 = 84, + MX6Q_PAD_EIM_WAIT = 85, + MX6Q_PAD_EIM_BCLK = 86, + MX6Q_PAD_DI0_DISP_CLK = 87, + MX6Q_PAD_DI0_PIN15 = 88, + MX6Q_PAD_DI0_PIN2 = 89, + MX6Q_PAD_DI0_PIN3 = 90, + MX6Q_PAD_DI0_PIN4 = 91, + MX6Q_PAD_DISP0_DAT0 = 92, + MX6Q_PAD_DISP0_DAT1 = 93, + MX6Q_PAD_DISP0_DAT2 = 94, + MX6Q_PAD_DISP0_DAT3 = 95, + MX6Q_PAD_DISP0_DAT4 = 96, + MX6Q_PAD_DISP0_DAT5 = 97, + MX6Q_PAD_DISP0_DAT6 = 98, + MX6Q_PAD_DISP0_DAT7 = 99, + MX6Q_PAD_DISP0_DAT8 = 100, + MX6Q_PAD_DISP0_DAT9 = 101, + MX6Q_PAD_DISP0_DAT10 = 102, + MX6Q_PAD_DISP0_DAT11 = 103, + MX6Q_PAD_DISP0_DAT12 = 104, + MX6Q_PAD_DISP0_DAT13 = 105, + MX6Q_PAD_DISP0_DAT14 = 106, + MX6Q_PAD_DISP0_DAT15 = 107, + MX6Q_PAD_DISP0_DAT16 = 108, + MX6Q_PAD_DISP0_DAT17 = 109, + MX6Q_PAD_DISP0_DAT18 = 110, + MX6Q_PAD_DISP0_DAT19 = 111, + MX6Q_PAD_DISP0_DAT20 = 112, + MX6Q_PAD_DISP0_DAT21 = 113, + MX6Q_PAD_DISP0_DAT22 = 114, + MX6Q_PAD_DISP0_DAT23 = 115, + MX6Q_PAD_ENET_MDIO = 116, + MX6Q_PAD_ENET_REF_CLK = 117, + MX6Q_PAD_ENET_RX_ER = 118, + MX6Q_PAD_ENET_CRS_DV = 119, + MX6Q_PAD_ENET_RXD1 = 120, + MX6Q_PAD_ENET_RXD0 = 121, + MX6Q_PAD_ENET_TX_EN = 122, + MX6Q_PAD_ENET_TXD1 = 123, + MX6Q_PAD_ENET_TXD0 = 124, + MX6Q_PAD_ENET_MDC = 125, + MX6Q_PAD_KEY_COL0 = 126, + MX6Q_PAD_KEY_ROW0 = 127, + MX6Q_PAD_KEY_COL1 = 128, + MX6Q_PAD_KEY_ROW1 = 129, + MX6Q_PAD_KEY_COL2 = 130, + MX6Q_PAD_KEY_ROW2 = 131, + MX6Q_PAD_KEY_COL3 = 132, + MX6Q_PAD_KEY_ROW3 = 133, + MX6Q_PAD_KEY_COL4 = 134, + MX6Q_PAD_KEY_ROW4 = 135, + MX6Q_PAD_GPIO_0 = 136, + MX6Q_PAD_GPIO_1 = 137, + MX6Q_PAD_GPIO_9 = 138, + MX6Q_PAD_GPIO_3 = 139, + MX6Q_PAD_GPIO_6 = 140, + MX6Q_PAD_GPIO_2 = 141, + MX6Q_PAD_GPIO_4 = 142, + MX6Q_PAD_GPIO_5 = 143, + MX6Q_PAD_GPIO_7 = 144, + MX6Q_PAD_GPIO_8 = 145, + MX6Q_PAD_GPIO_16 = 146, + MX6Q_PAD_GPIO_17 = 147, + MX6Q_PAD_GPIO_18 = 148, + MX6Q_PAD_GPIO_19 = 149, + MX6Q_PAD_CSI0_PIXCLK = 150, + MX6Q_PAD_CSI0_MCLK = 151, + MX6Q_PAD_CSI0_DATA_EN = 152, + MX6Q_PAD_CSI0_VSYNC = 153, + MX6Q_PAD_CSI0_DAT4 = 154, + MX6Q_PAD_CSI0_DAT5 = 155, + MX6Q_PAD_CSI0_DAT6 = 156, + MX6Q_PAD_CSI0_DAT7 = 157, + MX6Q_PAD_CSI0_DAT8 = 158, + MX6Q_PAD_CSI0_DAT9 = 159, + MX6Q_PAD_CSI0_DAT10 = 160, + MX6Q_PAD_CSI0_DAT11 = 161, + MX6Q_PAD_CSI0_DAT12 = 162, + MX6Q_PAD_CSI0_DAT13 = 163, + MX6Q_PAD_CSI0_DAT14 = 164, + MX6Q_PAD_CSI0_DAT15 = 165, + MX6Q_PAD_CSI0_DAT16 = 166, + MX6Q_PAD_CSI0_DAT17 = 167, + MX6Q_PAD_CSI0_DAT18 = 168, + MX6Q_PAD_CSI0_DAT19 = 169, + MX6Q_PAD_SD3_DAT7 = 170, + MX6Q_PAD_SD3_DAT6 = 171, + MX6Q_PAD_SD3_DAT5 = 172, + MX6Q_PAD_SD3_DAT4 = 173, + MX6Q_PAD_SD3_CMD = 174, + MX6Q_PAD_SD3_CLK = 175, + MX6Q_PAD_SD3_DAT0 = 176, + MX6Q_PAD_SD3_DAT1 = 177, + MX6Q_PAD_SD3_DAT2 = 178, + MX6Q_PAD_SD3_DAT3 = 179, + MX6Q_PAD_SD3_RST = 180, + MX6Q_PAD_NANDF_CLE = 181, + MX6Q_PAD_NANDF_ALE = 182, + MX6Q_PAD_NANDF_WP_B = 183, + MX6Q_PAD_NANDF_RB0 = 184, + MX6Q_PAD_NANDF_CS0 = 185, + MX6Q_PAD_NANDF_CS1 = 186, + MX6Q_PAD_NANDF_CS2 = 187, + MX6Q_PAD_NANDF_CS3 = 188, + MX6Q_PAD_SD4_CMD = 189, + MX6Q_PAD_SD4_CLK = 190, + MX6Q_PAD_NANDF_D0 = 191, + MX6Q_PAD_NANDF_D1 = 192, + MX6Q_PAD_NANDF_D2 = 193, + MX6Q_PAD_NANDF_D3 = 194, + MX6Q_PAD_NANDF_D4 = 195, + MX6Q_PAD_NANDF_D5 = 196, + MX6Q_PAD_NANDF_D6 = 197, + MX6Q_PAD_NANDF_D7 = 198, + MX6Q_PAD_SD4_DAT0 = 199, + MX6Q_PAD_SD4_DAT1 = 200, + MX6Q_PAD_SD4_DAT2 = 201, + MX6Q_PAD_SD4_DAT3 = 202, + MX6Q_PAD_SD4_DAT4 = 203, + MX6Q_PAD_SD4_DAT5 = 204, + MX6Q_PAD_SD4_DAT6 = 205, + MX6Q_PAD_SD4_DAT7 = 206, + MX6Q_PAD_SD1_DAT1 = 207, + MX6Q_PAD_SD1_DAT0 = 208, + MX6Q_PAD_SD1_DAT3 = 209, + MX6Q_PAD_SD1_CMD = 210, + MX6Q_PAD_SD1_DAT2 = 211, + MX6Q_PAD_SD1_CLK = 212, + MX6Q_PAD_SD2_CLK = 213, + MX6Q_PAD_SD2_CMD = 214, + MX6Q_PAD_SD2_DAT3 = 215, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1), + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2), + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3), + IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT), + IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK), + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK), + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15), + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2), + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3), + IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22), + IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0), + IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18), + IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18), + IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3), + IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6), + IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6), + IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7), + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1), + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0), + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3), + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2), + IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3), +}; + +static struct imx_pinctrl_soc_info imx6q_pinctrl_info = { + .pins = imx6q_pinctrl_pads, + .npins = ARRAY_SIZE(imx6q_pinctrl_pads), +}; + +static const struct of_device_id imx6q_pinctrl_of_match[] = { + { .compatible = "fsl,imx6q-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6q_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info); +} + +static struct platform_driver imx6q_pinctrl_driver = { + .driver = { + .name = "imx6q-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx6q_pinctrl_of_match, + }, + .probe = imx6q_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6q_pinctrl_init(void) +{ + return platform_driver_register(&imx6q_pinctrl_driver); +} +arch_initcall(imx6q_pinctrl_init); + +static void __exit imx6q_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6q_pinctrl_driver); +} +module_exit(imx6q_pinctrl_exit); +MODULE_AUTHOR("Dong Aisheng "); +MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c new file mode 100644 index 000000000000..e0924bd7b98c --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c @@ -0,0 +1,404 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx6sl_pads { + MX6SL_PAD_RESERVE0 = 0, + MX6SL_PAD_RESERVE1 = 1, + MX6SL_PAD_RESERVE2 = 2, + MX6SL_PAD_RESERVE3 = 3, + MX6SL_PAD_RESERVE4 = 4, + MX6SL_PAD_RESERVE5 = 5, + MX6SL_PAD_RESERVE6 = 6, + MX6SL_PAD_RESERVE7 = 7, + MX6SL_PAD_RESERVE8 = 8, + MX6SL_PAD_RESERVE9 = 9, + MX6SL_PAD_RESERVE10 = 10, + MX6SL_PAD_RESERVE11 = 11, + MX6SL_PAD_RESERVE12 = 12, + MX6SL_PAD_RESERVE13 = 13, + MX6SL_PAD_RESERVE14 = 14, + MX6SL_PAD_RESERVE15 = 15, + MX6SL_PAD_RESERVE16 = 16, + MX6SL_PAD_RESERVE17 = 17, + MX6SL_PAD_RESERVE18 = 18, + MX6SL_PAD_AUD_MCLK = 19, + MX6SL_PAD_AUD_RXC = 20, + MX6SL_PAD_AUD_RXD = 21, + MX6SL_PAD_AUD_RXFS = 22, + MX6SL_PAD_AUD_TXC = 23, + MX6SL_PAD_AUD_TXD = 24, + MX6SL_PAD_AUD_TXFS = 25, + MX6SL_PAD_ECSPI1_MISO = 26, + MX6SL_PAD_ECSPI1_MOSI = 27, + MX6SL_PAD_ECSPI1_SCLK = 28, + MX6SL_PAD_ECSPI1_SS0 = 29, + MX6SL_PAD_ECSPI2_MISO = 30, + MX6SL_PAD_ECSPI2_MOSI = 31, + MX6SL_PAD_ECSPI2_SCLK = 32, + MX6SL_PAD_ECSPI2_SS0 = 33, + MX6SL_PAD_EPDC_BDR0 = 34, + MX6SL_PAD_EPDC_BDR1 = 35, + MX6SL_PAD_EPDC_D0 = 36, + MX6SL_PAD_EPDC_D1 = 37, + MX6SL_PAD_EPDC_D10 = 38, + MX6SL_PAD_EPDC_D11 = 39, + MX6SL_PAD_EPDC_D12 = 40, + MX6SL_PAD_EPDC_D13 = 41, + MX6SL_PAD_EPDC_D14 = 42, + MX6SL_PAD_EPDC_D15 = 43, + MX6SL_PAD_EPDC_D2 = 44, + MX6SL_PAD_EPDC_D3 = 45, + MX6SL_PAD_EPDC_D4 = 46, + MX6SL_PAD_EPDC_D5 = 47, + MX6SL_PAD_EPDC_D6 = 48, + MX6SL_PAD_EPDC_D7 = 49, + MX6SL_PAD_EPDC_D8 = 50, + MX6SL_PAD_EPDC_D9 = 51, + MX6SL_PAD_EPDC_GDCLK = 52, + MX6SL_PAD_EPDC_GDOE = 53, + MX6SL_PAD_EPDC_GDRL = 54, + MX6SL_PAD_EPDC_GDSP = 55, + MX6SL_PAD_EPDC_PWRCOM = 56, + MX6SL_PAD_EPDC_PWRCTRL0 = 57, + MX6SL_PAD_EPDC_PWRCTRL1 = 58, + MX6SL_PAD_EPDC_PWRCTRL2 = 59, + MX6SL_PAD_EPDC_PWRCTRL3 = 60, + MX6SL_PAD_EPDC_PWRINT = 61, + MX6SL_PAD_EPDC_PWRSTAT = 62, + MX6SL_PAD_EPDC_PWRWAKEUP = 63, + MX6SL_PAD_EPDC_SDCE0 = 64, + MX6SL_PAD_EPDC_SDCE1 = 65, + MX6SL_PAD_EPDC_SDCE2 = 66, + MX6SL_PAD_EPDC_SDCE3 = 67, + MX6SL_PAD_EPDC_SDCLK = 68, + MX6SL_PAD_EPDC_SDLE = 69, + MX6SL_PAD_EPDC_SDOE = 70, + MX6SL_PAD_EPDC_SDSHR = 71, + MX6SL_PAD_EPDC_VCOM0 = 72, + MX6SL_PAD_EPDC_VCOM1 = 73, + MX6SL_PAD_FEC_CRS_DV = 74, + MX6SL_PAD_FEC_MDC = 75, + MX6SL_PAD_FEC_MDIO = 76, + MX6SL_PAD_FEC_REF_CLK = 77, + MX6SL_PAD_FEC_RX_ER = 78, + MX6SL_PAD_FEC_RXD0 = 79, + MX6SL_PAD_FEC_RXD1 = 80, + MX6SL_PAD_FEC_TX_CLK = 81, + MX6SL_PAD_FEC_TX_EN = 82, + MX6SL_PAD_FEC_TXD0 = 83, + MX6SL_PAD_FEC_TXD1 = 84, + MX6SL_PAD_HSIC_DAT = 85, + MX6SL_PAD_HSIC_STROBE = 86, + MX6SL_PAD_I2C1_SCL = 87, + MX6SL_PAD_I2C1_SDA = 88, + MX6SL_PAD_I2C2_SCL = 89, + MX6SL_PAD_I2C2_SDA = 90, + MX6SL_PAD_KEY_COL0 = 91, + MX6SL_PAD_KEY_COL1 = 92, + MX6SL_PAD_KEY_COL2 = 93, + MX6SL_PAD_KEY_COL3 = 94, + MX6SL_PAD_KEY_COL4 = 95, + MX6SL_PAD_KEY_COL5 = 96, + MX6SL_PAD_KEY_COL6 = 97, + MX6SL_PAD_KEY_COL7 = 98, + MX6SL_PAD_KEY_ROW0 = 99, + MX6SL_PAD_KEY_ROW1 = 100, + MX6SL_PAD_KEY_ROW2 = 101, + MX6SL_PAD_KEY_ROW3 = 102, + MX6SL_PAD_KEY_ROW4 = 103, + MX6SL_PAD_KEY_ROW5 = 104, + MX6SL_PAD_KEY_ROW6 = 105, + MX6SL_PAD_KEY_ROW7 = 106, + MX6SL_PAD_LCD_CLK = 107, + MX6SL_PAD_LCD_DAT0 = 108, + MX6SL_PAD_LCD_DAT1 = 109, + MX6SL_PAD_LCD_DAT10 = 110, + MX6SL_PAD_LCD_DAT11 = 111, + MX6SL_PAD_LCD_DAT12 = 112, + MX6SL_PAD_LCD_DAT13 = 113, + MX6SL_PAD_LCD_DAT14 = 114, + MX6SL_PAD_LCD_DAT15 = 115, + MX6SL_PAD_LCD_DAT16 = 116, + MX6SL_PAD_LCD_DAT17 = 117, + MX6SL_PAD_LCD_DAT18 = 118, + MX6SL_PAD_LCD_DAT19 = 119, + MX6SL_PAD_LCD_DAT2 = 120, + MX6SL_PAD_LCD_DAT20 = 121, + MX6SL_PAD_LCD_DAT21 = 122, + MX6SL_PAD_LCD_DAT22 = 123, + MX6SL_PAD_LCD_DAT23 = 124, + MX6SL_PAD_LCD_DAT3 = 125, + MX6SL_PAD_LCD_DAT4 = 126, + MX6SL_PAD_LCD_DAT5 = 127, + MX6SL_PAD_LCD_DAT6 = 128, + MX6SL_PAD_LCD_DAT7 = 129, + MX6SL_PAD_LCD_DAT8 = 130, + MX6SL_PAD_LCD_DAT9 = 131, + MX6SL_PAD_LCD_ENABLE = 132, + MX6SL_PAD_LCD_HSYNC = 133, + MX6SL_PAD_LCD_RESET = 134, + MX6SL_PAD_LCD_VSYNC = 135, + MX6SL_PAD_PWM1 = 136, + MX6SL_PAD_REF_CLK_24M = 137, + MX6SL_PAD_REF_CLK_32K = 138, + MX6SL_PAD_SD1_CLK = 139, + MX6SL_PAD_SD1_CMD = 140, + MX6SL_PAD_SD1_DAT0 = 141, + MX6SL_PAD_SD1_DAT1 = 142, + MX6SL_PAD_SD1_DAT2 = 143, + MX6SL_PAD_SD1_DAT3 = 144, + MX6SL_PAD_SD1_DAT4 = 145, + MX6SL_PAD_SD1_DAT5 = 146, + MX6SL_PAD_SD1_DAT6 = 147, + MX6SL_PAD_SD1_DAT7 = 148, + MX6SL_PAD_SD2_CLK = 149, + MX6SL_PAD_SD2_CMD = 150, + MX6SL_PAD_SD2_DAT0 = 151, + MX6SL_PAD_SD2_DAT1 = 152, + MX6SL_PAD_SD2_DAT2 = 153, + MX6SL_PAD_SD2_DAT3 = 154, + MX6SL_PAD_SD2_DAT4 = 155, + MX6SL_PAD_SD2_DAT5 = 156, + MX6SL_PAD_SD2_DAT6 = 157, + MX6SL_PAD_SD2_DAT7 = 158, + MX6SL_PAD_SD2_RST = 159, + MX6SL_PAD_SD3_CLK = 160, + MX6SL_PAD_SD3_CMD = 161, + MX6SL_PAD_SD3_DAT0 = 162, + MX6SL_PAD_SD3_DAT1 = 163, + MX6SL_PAD_SD3_DAT2 = 164, + MX6SL_PAD_SD3_DAT3 = 165, + MX6SL_PAD_UART1_RXD = 166, + MX6SL_PAD_UART1_TXD = 167, + MX6SL_PAD_WDOG_B = 168, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1), + IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT), + IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE), + IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL), + IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA), + IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL), + IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC), + IMX_PINCTRL_PIN(MX6SL_PAD_PWM1), + IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M), + IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3), + IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B), +}; + +static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = { + .pins = imx6sl_pinctrl_pads, + .npins = ARRAY_SIZE(imx6sl_pinctrl_pads), +}; + +static const struct of_device_id imx6sl_pinctrl_of_match[] = { + { .compatible = "fsl,imx6sl-iomuxc", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match); + +static int imx6sl_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info); +} + +static struct platform_driver imx6sl_pinctrl_driver = { + .driver = { + .name = "imx6sl-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx6sl_pinctrl_of_match, + }, + .probe = imx6sl_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6sl_pinctrl_init(void) +{ + return platform_driver_register(&imx6sl_pinctrl_driver); +} +arch_initcall(imx6sl_pinctrl_init); + +static void __exit imx6sl_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6sl_pinctrl_driver); +} +module_exit(imx6sl_pinctrl_exit); + +MODULE_AUTHOR("Shawn Guo "); +MODULE_DESCRIPTION("Freescale imx6sl pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c new file mode 100644 index 000000000000..840344c8580d --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c @@ -0,0 +1,407 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx6sx_pads { + MX6Sx_PAD_RESERVE0 = 0, + MX6Sx_PAD_RESERVE1 = 1, + MX6Sx_PAD_RESERVE2 = 2, + MX6Sx_PAD_RESERVE3 = 3, + MX6Sx_PAD_RESERVE4 = 4, + MX6SX_PAD_GPIO1_IO00 = 5, + MX6SX_PAD_GPIO1_IO01 = 6, + MX6SX_PAD_GPIO1_IO02 = 7, + MX6SX_PAD_GPIO1_IO03 = 8, + MX6SX_PAD_GPIO1_IO04 = 9, + MX6SX_PAD_GPIO1_IO05 = 10, + MX6SX_PAD_GPIO1_IO06 = 11, + MX6SX_PAD_GPIO1_IO07 = 12, + MX6SX_PAD_GPIO1_IO08 = 13, + MX6SX_PAD_GPIO1_IO09 = 14, + MX6SX_PAD_GPIO1_IO10 = 15, + MX6SX_PAD_GPIO1_IO11 = 16, + MX6SX_PAD_GPIO1_IO12 = 17, + MX6SX_PAD_GPIO1_IO13 = 18, + MX6SX_PAD_CSI_DATA00 = 19, + MX6SX_PAD_CSI_DATA01 = 20, + MX6SX_PAD_CSI_DATA02 = 21, + MX6SX_PAD_CSI_DATA03 = 22, + MX6SX_PAD_CSI_DATA04 = 23, + MX6SX_PAD_CSI_DATA05 = 24, + MX6SX_PAD_CSI_DATA06 = 25, + MX6SX_PAD_CSI_DATA07 = 26, + MX6SX_PAD_CSI_HSYNC = 27, + MX6SX_PAD_CSI_MCLK = 28, + MX6SX_PAD_CSI_PIXCLK = 29, + MX6SX_PAD_CSI_VSYNC = 30, + MX6SX_PAD_ENET1_COL = 31, + MX6SX_PAD_ENET1_CRS = 32, + MX6SX_PAD_ENET1_MDC = 33, + MX6SX_PAD_ENET1_MDIO = 34, + MX6SX_PAD_ENET1_RX_CLK = 35, + MX6SX_PAD_ENET1_TX_CLK = 36, + MX6SX_PAD_ENET2_COL = 37, + MX6SX_PAD_ENET2_CRS = 38, + MX6SX_PAD_ENET2_RX_CLK = 39, + MX6SX_PAD_ENET2_TX_CLK = 40, + MX6SX_PAD_KEY_COL0 = 41, + MX6SX_PAD_KEY_COL1 = 42, + MX6SX_PAD_KEY_COL2 = 43, + MX6SX_PAD_KEY_COL3 = 44, + MX6SX_PAD_KEY_COL4 = 45, + MX6SX_PAD_KEY_ROW0 = 46, + MX6SX_PAD_KEY_ROW1 = 47, + MX6SX_PAD_KEY_ROW2 = 48, + MX6SX_PAD_KEY_ROW3 = 49, + MX6SX_PAD_KEY_ROW4 = 50, + MX6SX_PAD_LCD1_CLK = 51, + MX6SX_PAD_LCD1_DATA00 = 52, + MX6SX_PAD_LCD1_DATA01 = 53, + MX6SX_PAD_LCD1_DATA02 = 54, + MX6SX_PAD_LCD1_DATA03 = 55, + MX6SX_PAD_LCD1_DATA04 = 56, + MX6SX_PAD_LCD1_DATA05 = 57, + MX6SX_PAD_LCD1_DATA06 = 58, + MX6SX_PAD_LCD1_DATA07 = 59, + MX6SX_PAD_LCD1_DATA08 = 60, + MX6SX_PAD_LCD1_DATA09 = 61, + MX6SX_PAD_LCD1_DATA10 = 62, + MX6SX_PAD_LCD1_DATA11 = 63, + MX6SX_PAD_LCD1_DATA12 = 64, + MX6SX_PAD_LCD1_DATA13 = 65, + MX6SX_PAD_LCD1_DATA14 = 66, + MX6SX_PAD_LCD1_DATA15 = 67, + MX6SX_PAD_LCD1_DATA16 = 68, + MX6SX_PAD_LCD1_DATA17 = 69, + MX6SX_PAD_LCD1_DATA18 = 70, + MX6SX_PAD_LCD1_DATA19 = 71, + MX6SX_PAD_LCD1_DATA20 = 72, + MX6SX_PAD_LCD1_DATA21 = 73, + MX6SX_PAD_LCD1_DATA22 = 74, + MX6SX_PAD_LCD1_DATA23 = 75, + MX6SX_PAD_LCD1_ENABLE = 76, + MX6SX_PAD_LCD1_HSYNC = 77, + MX6SX_PAD_LCD1_RESET = 78, + MX6SX_PAD_LCD1_VSYNC = 79, + MX6SX_PAD_NAND_ALE = 80, + MX6SX_PAD_NAND_CE0_B = 81, + MX6SX_PAD_NAND_CE1_B = 82, + MX6SX_PAD_NAND_CLE = 83, + MX6SX_PAD_NAND_DATA00 = 84 , + MX6SX_PAD_NAND_DATA01 = 85, + MX6SX_PAD_NAND_DATA02 = 86, + MX6SX_PAD_NAND_DATA03 = 87, + MX6SX_PAD_NAND_DATA04 = 88, + MX6SX_PAD_NAND_DATA05 = 89, + MX6SX_PAD_NAND_DATA06 = 90, + MX6SX_PAD_NAND_DATA07 = 91, + MX6SX_PAD_NAND_RE_B = 92, + MX6SX_PAD_NAND_READY_B = 93, + MX6SX_PAD_NAND_WE_B = 94, + MX6SX_PAD_NAND_WP_B = 95, + MX6SX_PAD_QSPI1A_DATA0 = 96, + MX6SX_PAD_QSPI1A_DATA1 = 97, + MX6SX_PAD_QSPI1A_DATA2 = 98, + MX6SX_PAD_QSPI1A_DATA3 = 99, + MX6SX_PAD_QSPI1A_DQS = 100, + MX6SX_PAD_QSPI1A_SCLK = 101, + MX6SX_PAD_QSPI1A_SS0_B = 102, + MX6SX_PAD_QSPI1A_SS1_B = 103, + MX6SX_PAD_QSPI1B_DATA0 = 104, + MX6SX_PAD_QSPI1B_DATA1 = 105, + MX6SX_PAD_QSPI1B_DATA2 = 106, + MX6SX_PAD_QSPI1B_DATA3 = 107, + MX6SX_PAD_QSPI1B_DQS = 108, + MX6SX_PAD_QSPI1B_SCLK = 109, + MX6SX_PAD_QSPI1B_SS0_B = 110, + MX6SX_PAD_QSPI1B_SS1_B = 111, + MX6SX_PAD_RGMII1_RD0 = 112, + MX6SX_PAD_RGMII1_RD1 = 113, + MX6SX_PAD_RGMII1_RD2 = 114, + MX6SX_PAD_RGMII1_RD3 = 115, + MX6SX_PAD_RGMII1_RX_CTL = 116, + MX6SX_PAD_RGMII1_RXC = 117, + MX6SX_PAD_RGMII1_TD0 = 118, + MX6SX_PAD_RGMII1_TD1 = 119, + MX6SX_PAD_RGMII1_TD2 = 120, + MX6SX_PAD_RGMII1_TD3 = 121, + MX6SX_PAD_RGMII1_TX_CTL = 122, + MX6SX_PAD_RGMII1_TXC = 123, + MX6SX_PAD_RGMII2_RD0 = 124, + MX6SX_PAD_RGMII2_RD1 = 125, + MX6SX_PAD_RGMII2_RD2 = 126, + MX6SX_PAD_RGMII2_RD3 = 127, + MX6SX_PAD_RGMII2_RX_CTL = 128, + MX6SX_PAD_RGMII2_RXC = 129, + MX6SX_PAD_RGMII2_TD0 = 130, + MX6SX_PAD_RGMII2_TD1 = 131, + MX6SX_PAD_RGMII2_TD2 = 132, + MX6SX_PAD_RGMII2_TD3 = 133, + MX6SX_PAD_RGMII2_TX_CTL = 134, + MX6SX_PAD_RGMII2_TXC = 135, + MX6SX_PAD_SD1_CLK = 136, + MX6SX_PAD_SD1_CMD = 137, + MX6SX_PAD_SD1_DATA0 = 138, + MX6SX_PAD_SD1_DATA1 = 139, + MX6SX_PAD_SD1_DATA2 = 140, + MX6SX_PAD_SD1_DATA3 = 141, + MX6SX_PAD_SD2_CLK = 142, + MX6SX_PAD_SD2_CMD = 143, + MX6SX_PAD_SD2_DATA0 = 144, + MX6SX_PAD_SD2_DATA1 = 145, + MX6SX_PAD_SD2_DATA2 = 146, + MX6SX_PAD_SD2_DATA3 = 147, + MX6SX_PAD_SD3_CLK = 148, + MX6SX_PAD_SD3_CMD = 149, + MX6SX_PAD_SD3_DATA0 = 150, + MX6SX_PAD_SD3_DATA1 = 151, + MX6SX_PAD_SD3_DATA2 = 152, + MX6SX_PAD_SD3_DATA3 = 153, + MX6SX_PAD_SD3_DATA4 = 154, + MX6SX_PAD_SD3_DATA5 = 155, + MX6SX_PAD_SD3_DATA6 = 156, + MX6SX_PAD_SD3_DATA7 = 157, + MX6SX_PAD_SD4_CLK = 158, + MX6SX_PAD_SD4_CMD = 159, + MX6SX_PAD_SD4_DATA0 = 160, + MX6SX_PAD_SD4_DATA1 = 161, + MX6SX_PAD_SD4_DATA2 = 162, + MX6SX_PAD_SD4_DATA3 = 163, + MX6SX_PAD_SD4_DATA4 = 164, + MX6SX_PAD_SD4_DATA5 = 165, + MX6SX_PAD_SD4_DATA6 = 166, + MX6SX_PAD_SD4_DATA7 = 167, + MX6SX_PAD_SD4_RESET_B = 168, + MX6SX_PAD_USB_H_DATA = 169, + MX6SX_PAD_USB_H_STROBE = 170, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B), + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA), + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE), +}; + +static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = { + .pins = imx6sx_pinctrl_pads, + .npins = ARRAY_SIZE(imx6sx_pinctrl_pads), +}; + +static const struct of_device_id imx6sx_pinctrl_of_match[] = { + { .compatible = "fsl,imx6sx-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6sx_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info); +} + +static struct platform_driver imx6sx_pinctrl_driver = { + .driver = { + .name = "imx6sx-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match), + }, + .probe = imx6sx_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6sx_pinctrl_init(void) +{ + return platform_driver_register(&imx6sx_pinctrl_driver); +} +arch_initcall(imx6sx_pinctrl_init); + +static void __exit imx6sx_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6sx_pinctrl_driver); +} +module_exit(imx6sx_pinctrl_exit); + +MODULE_AUTHOR("Anson Huang "); +MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c new file mode 100644 index 000000000000..f98c6bb0f769 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-mxs.c @@ -0,0 +1,541 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../core.h" +#include "pinctrl-mxs.h" + +#define SUFFIX_LEN 4 + +struct mxs_pinctrl_data { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *base; + struct mxs_pinctrl_soc_data *soc; +}; + +static int mxs_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + + return d->soc->ngroups; +} + +static const char *mxs_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + + return d->soc->groups[group].name; +} + +static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, + const unsigned **pins, unsigned *num_pins) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + + *pins = d->soc->groups[group].pins; + *num_pins = d->soc->groups[group].npins; + + return 0; +} + +static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct pinctrl_map *new_map; + char *group = NULL; + unsigned new_num = 1; + unsigned long config = 0; + unsigned long *pconfig; + int length = strlen(np->name) + SUFFIX_LEN; + bool purecfg = false; + u32 val, reg; + int ret, i = 0; + + /* Check for pin config node which has no 'reg' property */ + if (of_property_read_u32(np, "reg", ®)) + purecfg = true; + + ret = of_property_read_u32(np, "fsl,drive-strength", &val); + if (!ret) + config = val | MA_PRESENT; + ret = of_property_read_u32(np, "fsl,voltage", &val); + if (!ret) + config |= val << VOL_SHIFT | VOL_PRESENT; + ret = of_property_read_u32(np, "fsl,pull-up", &val); + if (!ret) + config |= val << PULL_SHIFT | PULL_PRESENT; + + /* Check for group node which has both mux and config settings */ + if (!purecfg && config) + new_num = 2; + + new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + if (!purecfg) { + new_map[i].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[i].data.mux.function = np->name; + + /* Compose group name */ + group = kzalloc(length, GFP_KERNEL); + if (!group) { + ret = -ENOMEM; + goto free; + } + snprintf(group, length, "%s.%d", np->name, reg); + new_map[i].data.mux.group = group; + i++; + } + + if (config) { + pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL); + if (!pconfig) { + ret = -ENOMEM; + goto free_group; + } + + new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; + new_map[i].data.configs.group_or_pin = purecfg ? np->name : + group; + new_map[i].data.configs.configs = pconfig; + new_map[i].data.configs.num_configs = 1; + } + + *map = new_map; + *num_maps = new_num; + + return 0; + +free_group: + if (!purecfg) + kfree(group); +free: + kfree(new_map); + return ret; +} + +static void mxs_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + u32 i; + + for (i = 0; i < num_maps; i++) { + if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) + kfree(map[i].data.mux.group); + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + } + + kfree(map); +} + +static const struct pinctrl_ops mxs_pinctrl_ops = { + .get_groups_count = mxs_get_groups_count, + .get_group_name = mxs_get_group_name, + .get_group_pins = mxs_get_group_pins, + .pin_dbg_show = mxs_pin_dbg_show, + .dt_node_to_map = mxs_dt_node_to_map, + .dt_free_map = mxs_dt_free_map, +}; + +static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + + return d->soc->nfunctions; +} + +static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + + return d->soc->functions[function].name; +} + +static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned group, + const char * const **groups, + unsigned * const num_groups) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + + *groups = d->soc->functions[group].groups; + *num_groups = d->soc->functions[group].ngroups; + + return 0; +} + +static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + struct mxs_group *g = &d->soc->groups[group]; + void __iomem *reg; + u8 bank, shift; + u16 pin; + u32 i; + + for (i = 0; i < g->npins; i++) { + bank = PINID_TO_BANK(g->pins[i]); + pin = PINID_TO_PIN(g->pins[i]); + reg = d->base + d->soc->regs->muxsel; + reg += bank * 0x20 + pin / 16 * 0x10; + shift = pin % 16 * 2; + + writel(0x3 << shift, reg + CLR); + writel(g->muxsel[i] << shift, reg + SET); + } + + return 0; +} + +static const struct pinmux_ops mxs_pinmux_ops = { + .get_functions_count = mxs_pinctrl_get_funcs_count, + .get_function_name = mxs_pinctrl_get_func_name, + .get_function_groups = mxs_pinctrl_get_func_groups, + .set_mux = mxs_pinctrl_set_mux, +}; + +static int mxs_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *config) +{ + return -ENOTSUPP; +} + +static int mxs_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *configs, + unsigned num_configs) +{ + return -ENOTSUPP; +} + +static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *config) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + + *config = d->soc->groups[group].config; + + return 0; +} + +static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *configs, + unsigned num_configs) +{ + struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); + struct mxs_group *g = &d->soc->groups[group]; + void __iomem *reg; + u8 ma, vol, pull, bank, shift; + u16 pin; + u32 i; + int n; + unsigned long config; + + for (n = 0; n < num_configs; n++) { + config = configs[n]; + + ma = CONFIG_TO_MA(config); + vol = CONFIG_TO_VOL(config); + pull = CONFIG_TO_PULL(config); + + for (i = 0; i < g->npins; i++) { + bank = PINID_TO_BANK(g->pins[i]); + pin = PINID_TO_PIN(g->pins[i]); + + /* drive */ + reg = d->base + d->soc->regs->drive; + reg += bank * 0x40 + pin / 8 * 0x10; + + /* mA */ + if (config & MA_PRESENT) { + shift = pin % 8 * 4; + writel(0x3 << shift, reg + CLR); + writel(ma << shift, reg + SET); + } + + /* vol */ + if (config & VOL_PRESENT) { + shift = pin % 8 * 4 + 2; + if (vol) + writel(1 << shift, reg + SET); + else + writel(1 << shift, reg + CLR); + } + + /* pull */ + if (config & PULL_PRESENT) { + reg = d->base + d->soc->regs->pull; + reg += bank * 0x10; + shift = pin; + if (pull) + writel(1 << shift, reg + SET); + else + writel(1 << shift, reg + CLR); + } + } + + /* cache the config value for mxs_pinconf_group_get() */ + g->config = config; + + } /* for each config */ + + return 0; +} + +static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin) +{ + /* Not support */ +} + +static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned group) +{ + unsigned long config; + + if (!mxs_pinconf_group_get(pctldev, group, &config)) + seq_printf(s, "0x%lx", config); +} + +static const struct pinconf_ops mxs_pinconf_ops = { + .pin_config_get = mxs_pinconf_get, + .pin_config_set = mxs_pinconf_set, + .pin_config_group_get = mxs_pinconf_group_get, + .pin_config_group_set = mxs_pinconf_group_set, + .pin_config_dbg_show = mxs_pinconf_dbg_show, + .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show, +}; + +static struct pinctrl_desc mxs_pinctrl_desc = { + .pctlops = &mxs_pinctrl_ops, + .pmxops = &mxs_pinmux_ops, + .confops = &mxs_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int mxs_pinctrl_parse_group(struct platform_device *pdev, + struct device_node *np, int idx, + const char **out_name) +{ + struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); + struct mxs_group *g = &d->soc->groups[idx]; + struct property *prop; + const char *propname = "fsl,pinmux-ids"; + char *group; + int length = strlen(np->name) + SUFFIX_LEN; + u32 val, i; + + group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL); + if (!group) + return -ENOMEM; + if (of_property_read_u32(np, "reg", &val)) + snprintf(group, length, "%s", np->name); + else + snprintf(group, length, "%s.%d", np->name, val); + g->name = group; + + prop = of_find_property(np, propname, &length); + if (!prop) + return -EINVAL; + g->npins = length / sizeof(u32); + + g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins), + GFP_KERNEL); + if (!g->pins) + return -ENOMEM; + + g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel), + GFP_KERNEL); + if (!g->muxsel) + return -ENOMEM; + + of_property_read_u32_array(np, propname, g->pins, g->npins); + for (i = 0; i < g->npins; i++) { + g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]); + g->pins[i] = MUXID_TO_PINID(g->pins[i]); + } + + if (out_name) + *out_name = g->name; + + return 0; +} + +static int mxs_pinctrl_probe_dt(struct platform_device *pdev, + struct mxs_pinctrl_data *d) +{ + struct mxs_pinctrl_soc_data *soc = d->soc; + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + struct mxs_function *f; + const char *gpio_compat = "fsl,mxs-gpio"; + const char *fn, *fnull = ""; + int i = 0, idxf = 0, idxg = 0; + int ret; + u32 val; + + child = of_get_next_child(np, NULL); + if (!child) { + dev_err(&pdev->dev, "no group is defined\n"); + return -ENOENT; + } + + /* Count total functions and groups */ + fn = fnull; + for_each_child_of_node(np, child) { + if (of_device_is_compatible(child, gpio_compat)) + continue; + soc->ngroups++; + /* Skip pure pinconf node */ + if (of_property_read_u32(child, "reg", &val)) + continue; + if (strcmp(fn, child->name)) { + fn = child->name; + soc->nfunctions++; + } + } + + soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions * + sizeof(*soc->functions), GFP_KERNEL); + if (!soc->functions) + return -ENOMEM; + + soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups * + sizeof(*soc->groups), GFP_KERNEL); + if (!soc->groups) + return -ENOMEM; + + /* Count groups for each function */ + fn = fnull; + f = &soc->functions[idxf]; + for_each_child_of_node(np, child) { + if (of_device_is_compatible(child, gpio_compat)) + continue; + if (of_property_read_u32(child, "reg", &val)) + continue; + if (strcmp(fn, child->name)) { + f = &soc->functions[idxf++]; + f->name = fn = child->name; + } + f->ngroups++; + }; + + /* Get groups for each function */ + idxf = 0; + fn = fnull; + for_each_child_of_node(np, child) { + if (of_device_is_compatible(child, gpio_compat)) + continue; + if (of_property_read_u32(child, "reg", &val)) { + ret = mxs_pinctrl_parse_group(pdev, child, + idxg++, NULL); + if (ret) + return ret; + continue; + } + + if (strcmp(fn, child->name)) { + f = &soc->functions[idxf++]; + f->groups = devm_kzalloc(&pdev->dev, f->ngroups * + sizeof(*f->groups), + GFP_KERNEL); + if (!f->groups) + return -ENOMEM; + fn = child->name; + i = 0; + } + ret = mxs_pinctrl_parse_group(pdev, child, idxg++, + &f->groups[i++]); + if (ret) + return ret; + } + + return 0; +} + +int mxs_pinctrl_probe(struct platform_device *pdev, + struct mxs_pinctrl_soc_data *soc) +{ + struct device_node *np = pdev->dev.of_node; + struct mxs_pinctrl_data *d; + int ret; + + d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL); + if (!d) + return -ENOMEM; + + d->dev = &pdev->dev; + d->soc = soc; + + d->base = of_iomap(np, 0); + if (!d->base) + return -EADDRNOTAVAIL; + + mxs_pinctrl_desc.pins = d->soc->pins; + mxs_pinctrl_desc.npins = d->soc->npins; + mxs_pinctrl_desc.name = dev_name(&pdev->dev); + + platform_set_drvdata(pdev, d); + + ret = mxs_pinctrl_probe_dt(pdev, d); + if (ret) { + dev_err(&pdev->dev, "dt probe failed: %d\n", ret); + goto err; + } + + d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d); + if (!d->pctl) { + dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n"); + ret = -EINVAL; + goto err; + } + + return 0; + +err: + iounmap(d->base); + return ret; +} +EXPORT_SYMBOL_GPL(mxs_pinctrl_probe); + +int mxs_pinctrl_remove(struct platform_device *pdev) +{ + struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); + + pinctrl_unregister(d->pctl); + iounmap(d->base); + + return 0; +} +EXPORT_SYMBOL_GPL(mxs_pinctrl_remove); diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.h b/drivers/pinctrl/freescale/pinctrl-mxs.h new file mode 100644 index 000000000000..fdd88d0bae22 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-mxs.h @@ -0,0 +1,91 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __PINCTRL_MXS_H +#define __PINCTRL_MXS_H + +#include +#include + +#define SET 0x4 +#define CLR 0x8 +#define TOG 0xc + +#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) +#define PINID(bank, pin) ((bank) * 32 + (pin)) + +/* + * pinmux-id bit field definitions + * + * bank: 15..12 (4) + * pin: 11..4 (8) + * muxsel: 3..0 (4) + */ +#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff) +#define MUXID_TO_MUXSEL(m) ((m) & 0xf) + +#define PINID_TO_BANK(p) ((p) >> 5) +#define PINID_TO_PIN(p) ((p) % 32) + +/* + * pin config bit field definitions + * + * pull-up: 6..5 (2) + * voltage: 4..3 (2) + * mA: 2..0 (3) + * + * MSB of each field is presence bit for the config. + */ +#define PULL_PRESENT (1 << 6) +#define PULL_SHIFT 5 +#define VOL_PRESENT (1 << 4) +#define VOL_SHIFT 3 +#define MA_PRESENT (1 << 2) +#define MA_SHIFT 0 +#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1) +#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1) +#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3) + +struct mxs_function { + const char *name; + const char **groups; + unsigned ngroups; +}; + +struct mxs_group { + const char *name; + unsigned int *pins; + unsigned npins; + u8 *muxsel; + u8 config; +}; + +struct mxs_regs { + u16 muxsel; + u16 drive; + u16 pull; +}; + +struct mxs_pinctrl_soc_data { + const struct mxs_regs *regs; + const struct pinctrl_pin_desc *pins; + unsigned npins; + struct mxs_function *functions; + unsigned nfunctions; + struct mxs_group *groups; + unsigned ngroups; +}; + +int mxs_pinctrl_probe(struct platform_device *pdev, + struct mxs_pinctrl_soc_data *soc); +int mxs_pinctrl_remove(struct platform_device *pdev); + +#endif /* __PINCTRL_MXS_H */ diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c new file mode 100644 index 000000000000..bddd913d28ba --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -0,0 +1,338 @@ +/* + * VF610 pinctrl driver based on imx pinmux and pinconf core + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum vf610_pads { + VF610_PAD_PTA6 = 0, + VF610_PAD_PTA8 = 1, + VF610_PAD_PTA9 = 2, + VF610_PAD_PTA10 = 3, + VF610_PAD_PTA11 = 4, + VF610_PAD_PTA12 = 5, + VF610_PAD_PTA16 = 6, + VF610_PAD_PTA17 = 7, + VF610_PAD_PTA18 = 8, + VF610_PAD_PTA19 = 9, + VF610_PAD_PTA20 = 10, + VF610_PAD_PTA21 = 11, + VF610_PAD_PTA22 = 12, + VF610_PAD_PTA23 = 13, + VF610_PAD_PTA24 = 14, + VF610_PAD_PTA25 = 15, + VF610_PAD_PTA26 = 16, + VF610_PAD_PTA27 = 17, + VF610_PAD_PTA28 = 18, + VF610_PAD_PTA29 = 19, + VF610_PAD_PTA30 = 20, + VF610_PAD_PTA31 = 21, + VF610_PAD_PTB0 = 22, + VF610_PAD_PTB1 = 23, + VF610_PAD_PTB2 = 24, + VF610_PAD_PTB3 = 25, + VF610_PAD_PTB4 = 26, + VF610_PAD_PTB5 = 27, + VF610_PAD_PTB6 = 28, + VF610_PAD_PTB7 = 29, + VF610_PAD_PTB8 = 30, + VF610_PAD_PTB9 = 31, + VF610_PAD_PTB10 = 32, + VF610_PAD_PTB11 = 33, + VF610_PAD_PTB12 = 34, + VF610_PAD_PTB13 = 35, + VF610_PAD_PTB14 = 36, + VF610_PAD_PTB15 = 37, + VF610_PAD_PTB16 = 38, + VF610_PAD_PTB17 = 39, + VF610_PAD_PTB18 = 40, + VF610_PAD_PTB19 = 41, + VF610_PAD_PTB20 = 42, + VF610_PAD_PTB21 = 43, + VF610_PAD_PTB22 = 44, + VF610_PAD_PTC0 = 45, + VF610_PAD_PTC1 = 46, + VF610_PAD_PTC2 = 47, + VF610_PAD_PTC3 = 48, + VF610_PAD_PTC4 = 49, + VF610_PAD_PTC5 = 50, + VF610_PAD_PTC6 = 51, + VF610_PAD_PTC7 = 52, + VF610_PAD_PTC8 = 53, + VF610_PAD_PTC9 = 54, + VF610_PAD_PTC10 = 55, + VF610_PAD_PTC11 = 56, + VF610_PAD_PTC12 = 57, + VF610_PAD_PTC13 = 58, + VF610_PAD_PTC14 = 59, + VF610_PAD_PTC15 = 60, + VF610_PAD_PTC16 = 61, + VF610_PAD_PTC17 = 62, + VF610_PAD_PTD31 = 63, + VF610_PAD_PTD30 = 64, + VF610_PAD_PTD29 = 65, + VF610_PAD_PTD28 = 66, + VF610_PAD_PTD27 = 67, + VF610_PAD_PTD26 = 68, + VF610_PAD_PTD25 = 69, + VF610_PAD_PTD24 = 70, + VF610_PAD_PTD23 = 71, + VF610_PAD_PTD22 = 72, + VF610_PAD_PTD21 = 73, + VF610_PAD_PTD20 = 74, + VF610_PAD_PTD19 = 75, + VF610_PAD_PTD18 = 76, + VF610_PAD_PTD17 = 77, + VF610_PAD_PTD16 = 78, + VF610_PAD_PTD0 = 79, + VF610_PAD_PTD1 = 80, + VF610_PAD_PTD2 = 81, + VF610_PAD_PTD3 = 82, + VF610_PAD_PTD4 = 83, + VF610_PAD_PTD5 = 84, + VF610_PAD_PTD6 = 85, + VF610_PAD_PTD7 = 86, + VF610_PAD_PTD8 = 87, + VF610_PAD_PTD9 = 88, + VF610_PAD_PTD10 = 89, + VF610_PAD_PTD11 = 90, + VF610_PAD_PTD12 = 91, + VF610_PAD_PTD13 = 92, + VF610_PAD_PTB23 = 93, + VF610_PAD_PTB24 = 94, + VF610_PAD_PTB25 = 95, + VF610_PAD_PTB26 = 96, + VF610_PAD_PTB27 = 97, + VF610_PAD_PTB28 = 98, + VF610_PAD_PTC26 = 99, + VF610_PAD_PTC27 = 100, + VF610_PAD_PTC28 = 101, + VF610_PAD_PTC29 = 102, + VF610_PAD_PTC30 = 103, + VF610_PAD_PTC31 = 104, + VF610_PAD_PTE0 = 105, + VF610_PAD_PTE1 = 106, + VF610_PAD_PTE2 = 107, + VF610_PAD_PTE3 = 108, + VF610_PAD_PTE4 = 109, + VF610_PAD_PTE5 = 110, + VF610_PAD_PTE6 = 111, + VF610_PAD_PTE7 = 112, + VF610_PAD_PTE8 = 113, + VF610_PAD_PTE9 = 114, + VF610_PAD_PTE10 = 115, + VF610_PAD_PTE11 = 116, + VF610_PAD_PTE12 = 117, + VF610_PAD_PTE13 = 118, + VF610_PAD_PTE14 = 119, + VF610_PAD_PTE15 = 120, + VF610_PAD_PTE16 = 121, + VF610_PAD_PTE17 = 122, + VF610_PAD_PTE18 = 123, + VF610_PAD_PTE19 = 124, + VF610_PAD_PTE20 = 125, + VF610_PAD_PTE21 = 126, + VF610_PAD_PTE22 = 127, + VF610_PAD_PTE23 = 128, + VF610_PAD_PTE24 = 129, + VF610_PAD_PTE25 = 130, + VF610_PAD_PTE26 = 131, + VF610_PAD_PTE27 = 132, + VF610_PAD_PTE28 = 133, + VF610_PAD_PTA7 = 134, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = { + IMX_PINCTRL_PIN(VF610_PAD_PTA6), + IMX_PINCTRL_PIN(VF610_PAD_PTA8), + IMX_PINCTRL_PIN(VF610_PAD_PTA9), + IMX_PINCTRL_PIN(VF610_PAD_PTA10), + IMX_PINCTRL_PIN(VF610_PAD_PTA11), + IMX_PINCTRL_PIN(VF610_PAD_PTA12), + IMX_PINCTRL_PIN(VF610_PAD_PTA16), + IMX_PINCTRL_PIN(VF610_PAD_PTA17), + IMX_PINCTRL_PIN(VF610_PAD_PTA18), + IMX_PINCTRL_PIN(VF610_PAD_PTA19), + IMX_PINCTRL_PIN(VF610_PAD_PTA20), + IMX_PINCTRL_PIN(VF610_PAD_PTA21), + IMX_PINCTRL_PIN(VF610_PAD_PTA22), + IMX_PINCTRL_PIN(VF610_PAD_PTA23), + IMX_PINCTRL_PIN(VF610_PAD_PTA24), + IMX_PINCTRL_PIN(VF610_PAD_PTA25), + IMX_PINCTRL_PIN(VF610_PAD_PTA26), + IMX_PINCTRL_PIN(VF610_PAD_PTA27), + IMX_PINCTRL_PIN(VF610_PAD_PTA28), + IMX_PINCTRL_PIN(VF610_PAD_PTA29), + IMX_PINCTRL_PIN(VF610_PAD_PTA30), + IMX_PINCTRL_PIN(VF610_PAD_PTA31), + IMX_PINCTRL_PIN(VF610_PAD_PTB0), + IMX_PINCTRL_PIN(VF610_PAD_PTB1), + IMX_PINCTRL_PIN(VF610_PAD_PTB2), + IMX_PINCTRL_PIN(VF610_PAD_PTB3), + IMX_PINCTRL_PIN(VF610_PAD_PTB4), + IMX_PINCTRL_PIN(VF610_PAD_PTB5), + IMX_PINCTRL_PIN(VF610_PAD_PTB6), + IMX_PINCTRL_PIN(VF610_PAD_PTB7), + IMX_PINCTRL_PIN(VF610_PAD_PTB8), + IMX_PINCTRL_PIN(VF610_PAD_PTB9), + IMX_PINCTRL_PIN(VF610_PAD_PTB10), + IMX_PINCTRL_PIN(VF610_PAD_PTB11), + IMX_PINCTRL_PIN(VF610_PAD_PTB12), + IMX_PINCTRL_PIN(VF610_PAD_PTB13), + IMX_PINCTRL_PIN(VF610_PAD_PTB14), + IMX_PINCTRL_PIN(VF610_PAD_PTB15), + IMX_PINCTRL_PIN(VF610_PAD_PTB16), + IMX_PINCTRL_PIN(VF610_PAD_PTB17), + IMX_PINCTRL_PIN(VF610_PAD_PTB18), + IMX_PINCTRL_PIN(VF610_PAD_PTB19), + IMX_PINCTRL_PIN(VF610_PAD_PTB20), + IMX_PINCTRL_PIN(VF610_PAD_PTB21), + IMX_PINCTRL_PIN(VF610_PAD_PTB22), + IMX_PINCTRL_PIN(VF610_PAD_PTC0), + IMX_PINCTRL_PIN(VF610_PAD_PTC1), + IMX_PINCTRL_PIN(VF610_PAD_PTC2), + IMX_PINCTRL_PIN(VF610_PAD_PTC3), + IMX_PINCTRL_PIN(VF610_PAD_PTC4), + IMX_PINCTRL_PIN(VF610_PAD_PTC5), + IMX_PINCTRL_PIN(VF610_PAD_PTC6), + IMX_PINCTRL_PIN(VF610_PAD_PTC7), + IMX_PINCTRL_PIN(VF610_PAD_PTC8), + IMX_PINCTRL_PIN(VF610_PAD_PTC9), + IMX_PINCTRL_PIN(VF610_PAD_PTC10), + IMX_PINCTRL_PIN(VF610_PAD_PTC11), + IMX_PINCTRL_PIN(VF610_PAD_PTC12), + IMX_PINCTRL_PIN(VF610_PAD_PTC13), + IMX_PINCTRL_PIN(VF610_PAD_PTC14), + IMX_PINCTRL_PIN(VF610_PAD_PTC15), + IMX_PINCTRL_PIN(VF610_PAD_PTC16), + IMX_PINCTRL_PIN(VF610_PAD_PTC17), + IMX_PINCTRL_PIN(VF610_PAD_PTD31), + IMX_PINCTRL_PIN(VF610_PAD_PTD30), + IMX_PINCTRL_PIN(VF610_PAD_PTD29), + IMX_PINCTRL_PIN(VF610_PAD_PTD28), + IMX_PINCTRL_PIN(VF610_PAD_PTD27), + IMX_PINCTRL_PIN(VF610_PAD_PTD26), + IMX_PINCTRL_PIN(VF610_PAD_PTD25), + IMX_PINCTRL_PIN(VF610_PAD_PTD24), + IMX_PINCTRL_PIN(VF610_PAD_PTD23), + IMX_PINCTRL_PIN(VF610_PAD_PTD22), + IMX_PINCTRL_PIN(VF610_PAD_PTD21), + IMX_PINCTRL_PIN(VF610_PAD_PTD20), + IMX_PINCTRL_PIN(VF610_PAD_PTD19), + IMX_PINCTRL_PIN(VF610_PAD_PTD18), + IMX_PINCTRL_PIN(VF610_PAD_PTD17), + IMX_PINCTRL_PIN(VF610_PAD_PTD16), + IMX_PINCTRL_PIN(VF610_PAD_PTD0), + IMX_PINCTRL_PIN(VF610_PAD_PTD1), + IMX_PINCTRL_PIN(VF610_PAD_PTD2), + IMX_PINCTRL_PIN(VF610_PAD_PTD3), + IMX_PINCTRL_PIN(VF610_PAD_PTD4), + IMX_PINCTRL_PIN(VF610_PAD_PTD5), + IMX_PINCTRL_PIN(VF610_PAD_PTD6), + IMX_PINCTRL_PIN(VF610_PAD_PTD7), + IMX_PINCTRL_PIN(VF610_PAD_PTD8), + IMX_PINCTRL_PIN(VF610_PAD_PTD9), + IMX_PINCTRL_PIN(VF610_PAD_PTD10), + IMX_PINCTRL_PIN(VF610_PAD_PTD11), + IMX_PINCTRL_PIN(VF610_PAD_PTD12), + IMX_PINCTRL_PIN(VF610_PAD_PTD13), + IMX_PINCTRL_PIN(VF610_PAD_PTB23), + IMX_PINCTRL_PIN(VF610_PAD_PTB24), + IMX_PINCTRL_PIN(VF610_PAD_PTB25), + IMX_PINCTRL_PIN(VF610_PAD_PTB26), + IMX_PINCTRL_PIN(VF610_PAD_PTB27), + IMX_PINCTRL_PIN(VF610_PAD_PTB28), + IMX_PINCTRL_PIN(VF610_PAD_PTC26), + IMX_PINCTRL_PIN(VF610_PAD_PTC27), + IMX_PINCTRL_PIN(VF610_PAD_PTC28), + IMX_PINCTRL_PIN(VF610_PAD_PTC29), + IMX_PINCTRL_PIN(VF610_PAD_PTC30), + IMX_PINCTRL_PIN(VF610_PAD_PTC31), + IMX_PINCTRL_PIN(VF610_PAD_PTE0), + IMX_PINCTRL_PIN(VF610_PAD_PTE1), + IMX_PINCTRL_PIN(VF610_PAD_PTE2), + IMX_PINCTRL_PIN(VF610_PAD_PTE3), + IMX_PINCTRL_PIN(VF610_PAD_PTE4), + IMX_PINCTRL_PIN(VF610_PAD_PTE5), + IMX_PINCTRL_PIN(VF610_PAD_PTE6), + IMX_PINCTRL_PIN(VF610_PAD_PTE7), + IMX_PINCTRL_PIN(VF610_PAD_PTE8), + IMX_PINCTRL_PIN(VF610_PAD_PTE9), + IMX_PINCTRL_PIN(VF610_PAD_PTE10), + IMX_PINCTRL_PIN(VF610_PAD_PTE11), + IMX_PINCTRL_PIN(VF610_PAD_PTE12), + IMX_PINCTRL_PIN(VF610_PAD_PTE13), + IMX_PINCTRL_PIN(VF610_PAD_PTE14), + IMX_PINCTRL_PIN(VF610_PAD_PTE15), + IMX_PINCTRL_PIN(VF610_PAD_PTE16), + IMX_PINCTRL_PIN(VF610_PAD_PTE17), + IMX_PINCTRL_PIN(VF610_PAD_PTE18), + IMX_PINCTRL_PIN(VF610_PAD_PTE19), + IMX_PINCTRL_PIN(VF610_PAD_PTE20), + IMX_PINCTRL_PIN(VF610_PAD_PTE21), + IMX_PINCTRL_PIN(VF610_PAD_PTE22), + IMX_PINCTRL_PIN(VF610_PAD_PTE23), + IMX_PINCTRL_PIN(VF610_PAD_PTE24), + IMX_PINCTRL_PIN(VF610_PAD_PTE25), + IMX_PINCTRL_PIN(VF610_PAD_PTE26), + IMX_PINCTRL_PIN(VF610_PAD_PTE27), + IMX_PINCTRL_PIN(VF610_PAD_PTE28), + IMX_PINCTRL_PIN(VF610_PAD_PTA7), +}; + +static struct imx_pinctrl_soc_info vf610_pinctrl_info = { + .pins = vf610_pinctrl_pads, + .npins = ARRAY_SIZE(vf610_pinctrl_pads), + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, +}; + +static struct of_device_id vf610_pinctrl_of_match[] = { + { .compatible = "fsl,vf610-iomuxc", }, + { /* sentinel */ } +}; + +static int vf610_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &vf610_pinctrl_info); +} + +static struct platform_driver vf610_pinctrl_driver = { + .driver = { + .name = "vf610-pinctrl", + .owner = THIS_MODULE, + .of_match_table = vf610_pinctrl_of_match, + }, + .probe = vf610_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init vf610_pinctrl_init(void) +{ + return platform_driver_register(&vf610_pinctrl_driver); +} +arch_initcall(vf610_pinctrl_init); + +static void __exit vf610_pinctrl_exit(void) +{ + platform_driver_unregister(&vf610_pinctrl_driver); +} +module_exit(vf610_pinctrl_exit); + +MODULE_DESCRIPTION("Freescale VF610 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c deleted file mode 100644 index 570e5acb4a6a..000000000000 --- a/drivers/pinctrl/pinctrl-imx.c +++ /dev/null @@ -1,630 +0,0 @@ -/* - * Core driver for the imx pin controller - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro Ltd. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" -#include "pinctrl-imx.h" - -/* The bits in CONFIG cell defined in binding doc*/ -#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ -#define IMX_PAD_SION 0x40000000 /* set SION */ - -/** - * @dev: a pointer back to containing device - * @base: the offset to the controller in virtual memory - */ -struct imx_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - const struct imx_pinctrl_soc_info *info; -}; - -static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( - const struct imx_pinctrl_soc_info *info, - const char *name) -{ - const struct imx_pin_group *grp = NULL; - int i; - - for (i = 0; i < info->ngroups; i++) { - if (!strcmp(info->groups[i].name, name)) { - grp = &info->groups[i]; - break; - } - } - - return grp; -} - -static int imx_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->ngroups; -} - -static const char *imx_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->groups[selector].name; -} - -static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *npins) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - if (selector >= info->ngroups) - return -EINVAL; - - *pins = info->groups[selector].pin_ids; - *npins = info->groups[selector].npins; - - return 0; -} - -static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, "%s", dev_name(pctldev->dev)); -} - -static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_group *grp; - struct pinctrl_map *new_map; - struct device_node *parent; - int map_num = 1; - int i, j; - - /* - * first find the group of this node and check if we need create - * config maps for pins - */ - grp = imx_pinctrl_find_group_by_name(info, np->name); - if (!grp) { - dev_err(info->dev, "unable to find group for node %s\n", - np->name); - return -EINVAL; - } - - for (i = 0; i < grp->npins; i++) { - if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) - map_num++; - } - - new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - *map = new_map; - *num_maps = map_num; - - /* create mux map */ - parent = of_get_parent(np); - if (!parent) { - kfree(new_map); - return -EINVAL; - } - new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[0].data.mux.function = parent->name; - new_map[0].data.mux.group = np->name; - of_node_put(parent); - - /* create config map */ - new_map++; - for (i = j = 0; i < grp->npins; i++) { - if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) { - new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[j].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i].pin); - new_map[j].data.configs.configs = &grp->pins[i].config; - new_map[j].data.configs.num_configs = 1; - j++; - } - } - - dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", - (*map)->data.mux.function, (*map)->data.mux.group, map_num); - - return 0; -} - -static void imx_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - kfree(map); -} - -static const struct pinctrl_ops imx_pctrl_ops = { - .get_groups_count = imx_get_groups_count, - .get_group_name = imx_get_group_name, - .get_group_pins = imx_get_group_pins, - .pin_dbg_show = imx_pin_dbg_show, - .dt_node_to_map = imx_dt_node_to_map, - .dt_free_map = imx_dt_free_map, - -}; - -static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - unsigned int npins, pin_id; - int i; - struct imx_pin_group *grp; - - /* - * Configure the mux mode for each pin in the group for a specific - * function. - */ - grp = &info->groups[group]; - npins = grp->npins; - - dev_dbg(ipctl->dev, "enable function %s group %s\n", - info->functions[selector].name, grp->name); - - for (i = 0; i < npins; i++) { - struct imx_pin *pin = &grp->pins[i]; - pin_id = pin->pin; - pin_reg = &info->pin_regs[pin_id]; - - if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) { - dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - if (info->flags & SHARE_MUX_CONF_REG) { - u32 reg; - reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~(0x7 << 20); - reg |= (pin->mux_mode << 20); - writel(reg, ipctl->base + pin_reg->mux_reg); - } else { - writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); - } - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, pin->mux_mode); - - /* - * If the select input value begins with 0xff, it's a quirky - * select input and the value should be interpreted as below. - * 31 23 15 7 0 - * | 0xff | shift | width | select | - * It's used to work around the problem that the select - * input for some pin is not implemented in the select - * input register but in some general purpose register. - * We encode the select input value, width and shift of - * the bit field into input_val cell of pin function ID - * in device tree, and then decode them here for setting - * up the select input bits in general purpose register. - */ - if (pin->input_val >> 24 == 0xff) { - u32 val = pin->input_val; - u8 select = val & 0xff; - u8 width = (val >> 8) & 0xff; - u8 shift = (val >> 16) & 0xff; - u32 mask = ((1 << width) - 1) << shift; - /* - * The input_reg[i] here is actually some IOMUXC general - * purpose register, not regular select input register. - */ - val = readl(ipctl->base + pin->input_reg); - val &= ~mask; - val |= select << shift; - writel(val, ipctl->base + pin->input_reg); - } else if (pin->input_reg) { - /* - * Regular select input register can never be at offset - * 0, and we only print register value for regular case. - */ - writel(pin->input_val, ipctl->base + pin->input_reg); - dev_dbg(ipctl->dev, - "==>select_input: offset 0x%x val 0x%x\n", - pin->input_reg, pin->input_val); - } - } - - return 0; -} - -static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->nfunctions; -} - -static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->functions[selector].name; -} - -static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - *groups = info->functions[selector].groups; - *num_groups = info->functions[selector].num_groups; - - return 0; -} - -static const struct pinmux_ops imx_pmx_ops = { - .get_functions_count = imx_pmx_get_funcs_count, - .get_function_name = imx_pmx_get_func_name, - .get_function_groups = imx_pmx_get_groups, - .set_mux = imx_pmx_set, -}; - -static int imx_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; - - if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { - dev_err(info->dev, "Pin(%s) does not support config function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - *config = readl(ipctl->base + pin_reg->conf_reg); - - if (info->flags & SHARE_MUX_CONF_REG) - *config &= 0xffff; - - return 0; -} - -static int imx_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *configs, - unsigned num_configs) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; - int i; - - if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { - dev_err(info->dev, "Pin(%s) does not support config function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - dev_dbg(ipctl->dev, "pinconf set pin %s\n", - info->pins[pin_id].name); - - for (i = 0; i < num_configs; i++) { - if (info->flags & SHARE_MUX_CONF_REG) { - u32 reg; - reg = readl(ipctl->base + pin_reg->conf_reg); - reg &= ~0xffff; - reg |= configs[i]; - writel(reg, ipctl->base + pin_reg->conf_reg); - } else { - writel(configs[i], ipctl->base + pin_reg->conf_reg); - } - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", - pin_reg->conf_reg, configs[i]); - } /* for each config */ - - return 0; -} - -static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin_id) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; - unsigned long config; - - if (!pin_reg || !pin_reg->conf_reg) { - seq_printf(s, "N/A"); - return; - } - - config = readl(ipctl->base + pin_reg->conf_reg); - seq_printf(s, "0x%lx", config); -} - -static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - struct imx_pin_group *grp; - unsigned long config; - const char *name; - int i, ret; - - if (group > info->ngroups) - return; - - seq_printf(s, "\n"); - grp = &info->groups[group]; - for (i = 0; i < grp->npins; i++) { - struct imx_pin *pin = &grp->pins[i]; - name = pin_get_name(pctldev, pin->pin); - ret = imx_pinconf_get(pctldev, pin->pin, &config); - if (ret) - return; - seq_printf(s, "%s: 0x%lx", name, config); - } -} - -static const struct pinconf_ops imx_pinconf_ops = { - .pin_config_get = imx_pinconf_get, - .pin_config_set = imx_pinconf_set, - .pin_config_dbg_show = imx_pinconf_dbg_show, - .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc imx_pinctrl_desc = { - .pctlops = &imx_pctrl_ops, - .pmxops = &imx_pmx_ops, - .confops = &imx_pinconf_ops, - .owner = THIS_MODULE, -}; - -/* - * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and - * 1 u32 CONFIG, so 24 types in total for each pin. - */ -#define FSL_PIN_SIZE 24 -#define SHARE_FSL_PIN_SIZE 20 - -static int imx_pinctrl_parse_groups(struct device_node *np, - struct imx_pin_group *grp, - struct imx_pinctrl_soc_info *info, - u32 index) -{ - int size, pin_size; - const __be32 *list; - int i; - u32 config; - - dev_dbg(info->dev, "group(%d): %s\n", index, np->name); - - if (info->flags & SHARE_MUX_CONF_REG) - pin_size = SHARE_FSL_PIN_SIZE; - else - pin_size = FSL_PIN_SIZE; - /* Initialise group */ - grp->name = np->name; - - /* - * the binding format is fsl,pins = , - * do sanity check and calculate pins number - */ - list = of_get_property(np, "fsl,pins", &size); - if (!list) { - dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); - return -EINVAL; - } - - /* we do not check return since it's safe node passed down */ - if (!size || size % pin_size) { - dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); - return -EINVAL; - } - - grp->npins = size / pin_size; - grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin), - GFP_KERNEL); - grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - if (!grp->pins || ! grp->pin_ids) - return -ENOMEM; - - for (i = 0; i < grp->npins; i++) { - u32 mux_reg = be32_to_cpu(*list++); - u32 conf_reg; - unsigned int pin_id; - struct imx_pin_reg *pin_reg; - struct imx_pin *pin = &grp->pins[i]; - - if (info->flags & SHARE_MUX_CONF_REG) - conf_reg = mux_reg; - else - conf_reg = be32_to_cpu(*list++); - - pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; - pin_reg = &info->pin_regs[pin_id]; - pin->pin = pin_id; - grp->pin_ids[i] = pin_id; - pin_reg->mux_reg = mux_reg; - pin_reg->conf_reg = conf_reg; - pin->input_reg = be32_to_cpu(*list++); - pin->mux_mode = be32_to_cpu(*list++); - pin->input_val = be32_to_cpu(*list++); - - /* SION bit is in mux register */ - config = be32_to_cpu(*list++); - if (config & IMX_PAD_SION) - pin->mux_mode |= IOMUXC_CONFIG_SION; - pin->config = config & ~IMX_PAD_SION; - - dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, - pin->mux_mode, pin->config); - } - - return 0; -} - -static int imx_pinctrl_parse_functions(struct device_node *np, - struct imx_pinctrl_soc_info *info, - u32 index) -{ - struct device_node *child; - struct imx_pmx_func *func; - struct imx_pin_group *grp; - static u32 grp_index; - u32 i = 0; - - dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); - - func = &info->functions[index]; - - /* Initialise function */ - func->name = np->name; - func->num_groups = of_get_child_count(np); - if (func->num_groups == 0) { - dev_err(info->dev, "no groups defined in %s\n", np->full_name); - return -EINVAL; - } - func->groups = devm_kzalloc(info->dev, - func->num_groups * sizeof(char *), GFP_KERNEL); - - for_each_child_of_node(np, child) { - func->groups[i] = child->name; - grp = &info->groups[grp_index++]; - imx_pinctrl_parse_groups(child, grp, info, i++); - } - - return 0; -} - -static int imx_pinctrl_probe_dt(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - u32 nfuncs = 0; - u32 i = 0; - - if (!np) - return -ENODEV; - - nfuncs = of_get_child_count(np); - if (nfuncs <= 0) { - dev_err(&pdev->dev, "no functions defined\n"); - return -EINVAL; - } - - info->nfunctions = nfuncs; - info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), - GFP_KERNEL); - if (!info->functions) - return -ENOMEM; - - info->ngroups = 0; - for_each_child_of_node(np, child) - info->ngroups += of_get_child_count(child); - info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), - GFP_KERNEL); - if (!info->groups) - return -ENOMEM; - - for_each_child_of_node(np, child) - imx_pinctrl_parse_functions(child, info, i++); - - return 0; -} - -int imx_pinctrl_probe(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info) -{ - struct imx_pinctrl *ipctl; - struct resource *res; - int ret; - - if (!info || !info->pins || !info->npins) { - dev_err(&pdev->dev, "wrong pinctrl info\n"); - return -EINVAL; - } - info->dev = &pdev->dev; - - /* Create state holders etc for this driver */ - ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); - if (!ipctl) - return -ENOMEM; - - info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) * - info->npins, GFP_KERNEL); - if (!info->pin_regs) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ipctl->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(ipctl->base)) - return PTR_ERR(ipctl->base); - - imx_pinctrl_desc.name = dev_name(&pdev->dev); - imx_pinctrl_desc.pins = info->pins; - imx_pinctrl_desc.npins = info->npins; - - ret = imx_pinctrl_probe_dt(pdev, info); - if (ret) { - dev_err(&pdev->dev, "fail to probe dt properties\n"); - return ret; - } - - ipctl->info = info; - ipctl->dev = info->dev; - platform_set_drvdata(pdev, ipctl); - ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); - if (!ipctl->pctl) { - dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - return -EINVAL; - } - - dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); - - return 0; -} - -int imx_pinctrl_remove(struct platform_device *pdev) -{ - struct imx_pinctrl *ipctl = platform_get_drvdata(pdev); - - pinctrl_unregister(ipctl->pctl); - - return 0; -} diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h deleted file mode 100644 index db408b057000..000000000000 --- a/drivers/pinctrl/pinctrl-imx.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * IMX pinmux core definitions - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro Ltd. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __DRIVERS_PINCTRL_IMX_H -#define __DRIVERS_PINCTRL_IMX_H - -struct platform_device; - -/** - * struct imx_pin_group - describes a single i.MX pin - * @pin: the pin_id of this pin - * @mux_mode: the mux mode for this pin. - * @input_reg: the select input register offset for this pin if any - * 0 if no select input setting needed. - * @input_val: the select input value for this pin. - * @configs: the config for this pin. - */ -struct imx_pin { - unsigned int pin; - unsigned int mux_mode; - u16 input_reg; - unsigned int input_val; - unsigned long config; -}; - -/** - * struct imx_pin_group - describes an IMX pin group - * @name: the name of this specific pin group - * @npins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array - * @pins: array of pins - */ -struct imx_pin_group { - const char *name; - unsigned npins; - unsigned int *pin_ids; - struct imx_pin *pins; -}; - -/** - * struct imx_pmx_func - describes IMX pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @num_groups: the number of groups - */ -struct imx_pmx_func { - const char *name; - const char **groups; - unsigned num_groups; -}; - -/** - * struct imx_pin_reg - describe a pin reg map - * @mux_reg: mux register offset - * @conf_reg: config register offset - */ -struct imx_pin_reg { - u16 mux_reg; - u16 conf_reg; -}; - -struct imx_pinctrl_soc_info { - struct device *dev; - const struct pinctrl_pin_desc *pins; - unsigned int npins; - struct imx_pin_reg *pin_regs; - struct imx_pin_group *groups; - unsigned int ngroups; - struct imx_pmx_func *functions; - unsigned int nfunctions; - unsigned int flags; -}; - -#define ZERO_OFFSET_VALID 0x1 -#define SHARE_MUX_CONF_REG 0x2 - -#define NO_MUX 0x0 -#define NO_PAD 0x0 - -#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) - -#define PAD_CTL_MASK(len) ((1 << len) - 1) -#define IMX_MUX_MASK 0x7 -#define IOMUXC_CONFIG_SION (0x1 << 4) - -int imx_pinctrl_probe(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info); -int imx_pinctrl_remove(struct platform_device *pdev); -#endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c deleted file mode 100644 index 176a3e62f1cf..000000000000 --- a/drivers/pinctrl/pinctrl-imx1-core.c +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Core driver for the imx pin controller in imx1/21/27 - * - * Copyright (C) 2013 Pengutronix - * Author: Markus Pargmann - * - * Based on pinctrl-imx.c: - * Author: Dong Aisheng - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" -#include "pinctrl-imx1.h" - -struct imx1_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - const struct imx1_pinctrl_soc_info *info; -}; - -/* - * MX1 register offsets - */ - -#define MX1_DDIR 0x00 -#define MX1_OCR 0x04 -#define MX1_ICONFA 0x0c -#define MX1_ICONFB 0x14 -#define MX1_GIUS 0x20 -#define MX1_GPR 0x38 -#define MX1_PUEN 0x40 - -#define MX1_PORT_STRIDE 0x100 - - -/* - * MUX_ID format defines - */ -#define MX1_MUX_FUNCTION(val) (BIT(0) & val) -#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1) -#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2) -#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4) -#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8) -#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10) - - -/* - * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX - * control register are seperated into function, output configuration, input - * configuration A, input configuration B, GPIO in use and data direction. - * - * Those controls that are represented by 1 bit have a direct mapping between - * bit position and pin id. If they are represented by 2 bit, the lower 16 pins - * are in the first register and the upper 16 pins in the second (next) - * register. pin_id is stored in bit (pin_id%16)*2 and the bit above. - */ - -/* - * Calculates the register offset from a pin_id - */ -static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id) -{ - unsigned int port = pin_id / 32; - return ipctl->base + port * MX1_PORT_STRIDE; -} - -/* - * Write to a register with 2 bits per pin. The function will automatically - * use the next register if the pin is managed in the second register. - */ -static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, - u32 value, u32 reg_offset) -{ - void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; - int offset = (pin_id % 16) * 2; /* offset, regardless of register used */ - int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */ - u32 old_val; - u32 new_val; - - /* Use the next register if the pin's port pin number is >=16 */ - if (pin_id % 32 >= 16) - reg += 0x04; - - dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", - reg, offset, value); - - /* Get current state of pins */ - old_val = readl(reg); - old_val &= mask; - - new_val = value & 0x3; /* Make sure value is really 2 bit */ - new_val <<= offset; - new_val |= old_val;/* Set new state for pin_id */ - - writel(new_val, reg); -} - -static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, - u32 value, u32 reg_offset) -{ - void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; - int offset = pin_id % 32; - int mask = ~BIT_MASK(offset); - u32 old_val; - u32 new_val; - - /* Get current state of pins */ - old_val = readl(reg); - old_val &= mask; - - new_val = value & 0x1; /* Make sure value is really 1 bit */ - new_val <<= offset; - new_val |= old_val;/* Set new state for pin_id */ - - writel(new_val, reg); -} - -static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, - u32 reg_offset) -{ - void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; - int offset = (pin_id % 16) * 2; - - /* Use the next register if the pin's port pin number is >=16 */ - if (pin_id % 32 >= 16) - reg += 0x04; - - return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset; -} - -static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, - u32 reg_offset) -{ - void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; - int offset = pin_id % 32; - - return !!(readl(reg) & BIT(offset)); -} - -static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name( - const struct imx1_pinctrl_soc_info *info, - const char *name) -{ - const struct imx1_pin_group *grp = NULL; - int i; - - for (i = 0; i < info->ngroups; i++) { - if (!strcmp(info->groups[i].name, name)) { - grp = &info->groups[i]; - break; - } - } - - return grp; -} - -static int imx1_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - - return info->ngroups; -} - -static const char *imx1_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - - return info->groups[selector].name; -} - -static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned int **pins, - unsigned *npins) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - - if (selector >= info->ngroups) - return -EINVAL; - - *pins = info->groups[selector].pin_ids; - *npins = info->groups[selector].npins; - - return 0; -} - -static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - - seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d", - imx1_read_bit(ipctl, offset, MX1_GIUS), - imx1_read_bit(ipctl, offset, MX1_GPR), - imx1_read_bit(ipctl, offset, MX1_DDIR), - imx1_read_2bit(ipctl, offset, MX1_OCR), - imx1_read_2bit(ipctl, offset, MX1_ICONFA), - imx1_read_2bit(ipctl, offset, MX1_ICONFB)); -} - -static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - const struct imx1_pin_group *grp; - struct pinctrl_map *new_map; - struct device_node *parent; - int map_num = 1; - int i, j; - - /* - * first find the group of this node and check if we need create - * config maps for pins - */ - grp = imx1_pinctrl_find_group_by_name(info, np->name); - if (!grp) { - dev_err(info->dev, "unable to find group for node %s\n", - np->name); - return -EINVAL; - } - - for (i = 0; i < grp->npins; i++) - map_num++; - - new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - *map = new_map; - *num_maps = map_num; - - /* create mux map */ - parent = of_get_parent(np); - if (!parent) { - kfree(new_map); - return -EINVAL; - } - new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[0].data.mux.function = parent->name; - new_map[0].data.mux.group = np->name; - of_node_put(parent); - - /* create config map */ - new_map++; - for (i = j = 0; i < grp->npins; i++) { - new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[j].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i].pin_id); - new_map[j].data.configs.configs = &grp->pins[i].config; - new_map[j].data.configs.num_configs = 1; - j++; - } - - dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", - (*map)->data.mux.function, (*map)->data.mux.group, map_num); - - return 0; -} - -static void imx1_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - kfree(map); -} - -static const struct pinctrl_ops imx1_pctrl_ops = { - .get_groups_count = imx1_get_groups_count, - .get_group_name = imx1_get_group_name, - .get_group_pins = imx1_get_group_pins, - .pin_dbg_show = imx1_pin_dbg_show, - .dt_node_to_map = imx1_dt_node_to_map, - .dt_free_map = imx1_dt_free_map, - -}; - -static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - const struct imx1_pin *pins; - unsigned int npins; - int i; - - /* - * Configure the mux mode for each pin in the group for a specific - * function. - */ - pins = info->groups[group].pins; - npins = info->groups[group].npins; - - WARN_ON(!pins || !npins); - - dev_dbg(ipctl->dev, "enable function %s group %s\n", - info->functions[selector].name, info->groups[group].name); - - for (i = 0; i < npins; i++) { - unsigned int mux = pins[i].mux_id; - unsigned int pin_id = pins[i].pin_id; - unsigned int afunction = MX1_MUX_FUNCTION(mux); - unsigned int gpio_in_use = MX1_MUX_GPIO(mux); - unsigned int direction = MX1_MUX_DIR(mux); - unsigned int gpio_oconf = MX1_MUX_OCONF(mux); - unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux); - unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux); - - dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n", - __func__, pin_id, afunction, gpio_in_use, - direction, gpio_oconf, gpio_iconfa, - gpio_iconfb); - - imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS); - imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR); - - if (gpio_in_use) { - imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR); - imx1_write_2bit(ipctl, pin_id, gpio_iconfa, - MX1_ICONFA); - imx1_write_2bit(ipctl, pin_id, gpio_iconfb, - MX1_ICONFB); - } else { - imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR); - } - } - - return 0; -} - -static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - - return info->nfunctions; -} - -static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - - return info->functions[selector].name; -} - -static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - - *groups = info->functions[selector].groups; - *num_groups = info->functions[selector].num_groups; - - return 0; -} - -static const struct pinmux_ops imx1_pmx_ops = { - .get_functions_count = imx1_pmx_get_funcs_count, - .get_function_name = imx1_pmx_get_func_name, - .get_function_groups = imx1_pmx_get_groups, - .set_mux = imx1_pmx_set, -}; - -static int imx1_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - - *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN); - - return 0; -} - -static int imx1_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *configs, - unsigned num_configs) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - int i; - - for (i = 0; i != num_configs; ++i) { - imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN); - - dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n", - info->pins[pin_id].name); - } - - return 0; -} - -static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin_id) -{ - unsigned long config; - - imx1_pinconf_get(pctldev, pin_id, &config); - seq_printf(s, "0x%lx", config); -} - -static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ - struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; - struct imx1_pin_group *grp; - unsigned long config; - const char *name; - int i, ret; - - if (group > info->ngroups) - return; - - seq_puts(s, "\n"); - grp = &info->groups[group]; - for (i = 0; i < grp->npins; i++) { - name = pin_get_name(pctldev, grp->pins[i].pin_id); - ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config); - if (ret) - return; - seq_printf(s, "%s: 0x%lx", name, config); - } -} - -static const struct pinconf_ops imx1_pinconf_ops = { - .pin_config_get = imx1_pinconf_get, - .pin_config_set = imx1_pinconf_set, - .pin_config_dbg_show = imx1_pinconf_dbg_show, - .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc imx1_pinctrl_desc = { - .pctlops = &imx1_pctrl_ops, - .pmxops = &imx1_pmx_ops, - .confops = &imx1_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int imx1_pinctrl_parse_groups(struct device_node *np, - struct imx1_pin_group *grp, - struct imx1_pinctrl_soc_info *info, - u32 index) -{ - int size; - const __be32 *list; - int i; - - dev_dbg(info->dev, "group(%d): %s\n", index, np->name); - - /* Initialise group */ - grp->name = np->name; - - /* - * the binding format is fsl,pins = - */ - list = of_get_property(np, "fsl,pins", &size); - /* we do not check return since it's safe node passed down */ - if (!size || size % 12) { - dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n", - np->name); - return -EINVAL; - } - - grp->npins = size / 12; - grp->pins = devm_kzalloc(info->dev, - grp->npins * sizeof(struct imx1_pin), GFP_KERNEL); - grp->pin_ids = devm_kzalloc(info->dev, - grp->npins * sizeof(unsigned int), GFP_KERNEL); - - if (!grp->pins || !grp->pin_ids) - return -ENOMEM; - - for (i = 0; i < grp->npins; i++) { - grp->pins[i].pin_id = be32_to_cpu(*list++); - grp->pins[i].mux_id = be32_to_cpu(*list++); - grp->pins[i].config = be32_to_cpu(*list++); - - grp->pin_ids[i] = grp->pins[i].pin_id; - } - - return 0; -} - -static int imx1_pinctrl_parse_functions(struct device_node *np, - struct imx1_pinctrl_soc_info *info, - u32 index) -{ - struct device_node *child; - struct imx1_pmx_func *func; - struct imx1_pin_group *grp; - int ret; - static u32 grp_index; - u32 i = 0; - - dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); - - func = &info->functions[index]; - - /* Initialise function */ - func->name = np->name; - func->num_groups = of_get_child_count(np); - if (func->num_groups == 0) - return -EINVAL; - - func->groups = devm_kzalloc(info->dev, - func->num_groups * sizeof(char *), GFP_KERNEL); - - if (!func->groups) - return -ENOMEM; - - for_each_child_of_node(np, child) { - func->groups[i] = child->name; - grp = &info->groups[grp_index++]; - ret = imx1_pinctrl_parse_groups(child, grp, info, i++); - if (ret == -ENOMEM) - return ret; - } - - return 0; -} - -static int imx1_pinctrl_parse_dt(struct platform_device *pdev, - struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - int ret; - u32 nfuncs = 0; - u32 ngroups = 0; - u32 ifunc = 0; - - if (!np) - return -ENODEV; - - for_each_child_of_node(np, child) { - ++nfuncs; - ngroups += of_get_child_count(child); - } - - if (!nfuncs) { - dev_err(&pdev->dev, "No pin functions defined\n"); - return -EINVAL; - } - - info->nfunctions = nfuncs; - info->functions = devm_kzalloc(&pdev->dev, - nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL); - - info->ngroups = ngroups; - info->groups = devm_kzalloc(&pdev->dev, - ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL); - - - if (!info->functions || !info->groups) - return -ENOMEM; - - for_each_child_of_node(np, child) { - ret = imx1_pinctrl_parse_functions(child, info, ifunc++); - if (ret == -ENOMEM) - return -ENOMEM; - } - - return 0; -} - -int imx1_pinctrl_core_probe(struct platform_device *pdev, - struct imx1_pinctrl_soc_info *info) -{ - struct imx1_pinctrl *ipctl; - struct resource *res; - struct pinctrl_desc *pctl_desc; - int ret; - - if (!info || !info->pins || !info->npins) { - dev_err(&pdev->dev, "wrong pinctrl info\n"); - return -EINVAL; - } - info->dev = &pdev->dev; - - /* Create state holders etc for this driver */ - ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); - if (!ipctl) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENOENT; - - ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start, - resource_size(res)); - if (!ipctl->base) - return -ENOMEM; - - pctl_desc = &imx1_pinctrl_desc; - pctl_desc->name = dev_name(&pdev->dev); - pctl_desc->pins = info->pins; - pctl_desc->npins = info->npins; - - ret = imx1_pinctrl_parse_dt(pdev, ipctl, info); - if (ret) { - dev_err(&pdev->dev, "fail to probe dt properties\n"); - return ret; - } - - ipctl->info = info; - ipctl->dev = info->dev; - platform_set_drvdata(pdev, ipctl); - ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl); - if (!ipctl->pctl) { - dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - return -EINVAL; - } - - ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); - if (ret) { - pinctrl_unregister(ipctl->pctl); - dev_err(&pdev->dev, "Failed to populate subdevices\n"); - return ret; - } - - dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); - - return 0; -} - -int imx1_pinctrl_core_remove(struct platform_device *pdev) -{ - struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev); - - pinctrl_unregister(ipctl->pctl); - - return 0; -} diff --git a/drivers/pinctrl/pinctrl-imx1.c b/drivers/pinctrl/pinctrl-imx1.c deleted file mode 100644 index 533a6e519648..000000000000 --- a/drivers/pinctrl/pinctrl-imx1.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * i.MX1 pinctrl driver based on imx pinmux core - * - * Copyright (C) 2014 Alexander Shiyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include - -#include "pinctrl-imx1.h" - -#define PAD_ID(port, pin) ((port) * 32 + (pin)) -#define PA 0 -#define PB 1 -#define PC 2 -#define PD 3 - -enum imx1_pads { - MX1_PAD_A24 = PAD_ID(PA, 0), - MX1_PAD_TIN = PAD_ID(PA, 1), - MX1_PAD_PWMO = PAD_ID(PA, 2), - MX1_PAD_CSI_MCLK = PAD_ID(PA, 3), - MX1_PAD_CSI_D0 = PAD_ID(PA, 4), - MX1_PAD_CSI_D1 = PAD_ID(PA, 5), - MX1_PAD_CSI_D2 = PAD_ID(PA, 6), - MX1_PAD_CSI_D3 = PAD_ID(PA, 7), - MX1_PAD_CSI_D4 = PAD_ID(PA, 8), - MX1_PAD_CSI_D5 = PAD_ID(PA, 9), - MX1_PAD_CSI_D6 = PAD_ID(PA, 10), - MX1_PAD_CSI_D7 = PAD_ID(PA, 11), - MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12), - MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13), - MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14), - MX1_PAD_I2C_SDA = PAD_ID(PA, 15), - MX1_PAD_I2C_SCL = PAD_ID(PA, 16), - MX1_PAD_DTACK = PAD_ID(PA, 17), - MX1_PAD_BCLK = PAD_ID(PA, 18), - MX1_PAD_LBA = PAD_ID(PA, 19), - MX1_PAD_ECB = PAD_ID(PA, 20), - MX1_PAD_A0 = PAD_ID(PA, 21), - MX1_PAD_CS4 = PAD_ID(PA, 22), - MX1_PAD_CS5 = PAD_ID(PA, 23), - MX1_PAD_A16 = PAD_ID(PA, 24), - MX1_PAD_A17 = PAD_ID(PA, 25), - MX1_PAD_A18 = PAD_ID(PA, 26), - MX1_PAD_A19 = PAD_ID(PA, 27), - MX1_PAD_A20 = PAD_ID(PA, 28), - MX1_PAD_A21 = PAD_ID(PA, 29), - MX1_PAD_A22 = PAD_ID(PA, 30), - MX1_PAD_A23 = PAD_ID(PA, 31), - MX1_PAD_SD_DAT0 = PAD_ID(PB, 8), - MX1_PAD_SD_DAT1 = PAD_ID(PB, 9), - MX1_PAD_SD_DAT2 = PAD_ID(PB, 10), - MX1_PAD_SD_DAT3 = PAD_ID(PB, 11), - MX1_PAD_SD_SCLK = PAD_ID(PB, 12), - MX1_PAD_SD_CMD = PAD_ID(PB, 13), - MX1_PAD_SIM_SVEN = PAD_ID(PB, 14), - MX1_PAD_SIM_PD = PAD_ID(PB, 15), - MX1_PAD_SIM_TX = PAD_ID(PB, 16), - MX1_PAD_SIM_RX = PAD_ID(PB, 17), - MX1_PAD_SIM_RST = PAD_ID(PB, 18), - MX1_PAD_SIM_CLK = PAD_ID(PB, 19), - MX1_PAD_USBD_AFE = PAD_ID(PB, 20), - MX1_PAD_USBD_OE = PAD_ID(PB, 21), - MX1_PAD_USBD_RCV = PAD_ID(PB, 22), - MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23), - MX1_PAD_USBD_VP = PAD_ID(PB, 24), - MX1_PAD_USBD_VM = PAD_ID(PB, 25), - MX1_PAD_USBD_VPO = PAD_ID(PB, 26), - MX1_PAD_USBD_VMO = PAD_ID(PB, 27), - MX1_PAD_UART2_CTS = PAD_ID(PB, 28), - MX1_PAD_UART2_RTS = PAD_ID(PB, 29), - MX1_PAD_UART2_TXD = PAD_ID(PB, 30), - MX1_PAD_UART2_RXD = PAD_ID(PB, 31), - MX1_PAD_SSI_RXFS = PAD_ID(PC, 3), - MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4), - MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5), - MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6), - MX1_PAD_SSI_TXFS = PAD_ID(PC, 7), - MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8), - MX1_PAD_UART1_CTS = PAD_ID(PC, 9), - MX1_PAD_UART1_RTS = PAD_ID(PC, 10), - MX1_PAD_UART1_TXD = PAD_ID(PC, 11), - MX1_PAD_UART1_RXD = PAD_ID(PC, 12), - MX1_PAD_SPI1_RDY = PAD_ID(PC, 13), - MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14), - MX1_PAD_SPI1_SS = PAD_ID(PC, 15), - MX1_PAD_SPI1_MISO = PAD_ID(PC, 16), - MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17), - MX1_PAD_BT13 = PAD_ID(PC, 19), - MX1_PAD_BT12 = PAD_ID(PC, 20), - MX1_PAD_BT11 = PAD_ID(PC, 21), - MX1_PAD_BT10 = PAD_ID(PC, 22), - MX1_PAD_BT9 = PAD_ID(PC, 23), - MX1_PAD_BT8 = PAD_ID(PC, 24), - MX1_PAD_BT7 = PAD_ID(PC, 25), - MX1_PAD_BT6 = PAD_ID(PC, 26), - MX1_PAD_BT5 = PAD_ID(PC, 27), - MX1_PAD_BT4 = PAD_ID(PC, 28), - MX1_PAD_BT3 = PAD_ID(PC, 29), - MX1_PAD_BT2 = PAD_ID(PC, 30), - MX1_PAD_BT1 = PAD_ID(PC, 31), - MX1_PAD_LSCLK = PAD_ID(PD, 6), - MX1_PAD_REV = PAD_ID(PD, 7), - MX1_PAD_CLS = PAD_ID(PD, 8), - MX1_PAD_PS = PAD_ID(PD, 9), - MX1_PAD_SPL_SPR = PAD_ID(PD, 10), - MX1_PAD_CONTRAST = PAD_ID(PD, 11), - MX1_PAD_ACD_OE = PAD_ID(PD, 12), - MX1_PAD_LP_HSYNC = PAD_ID(PD, 13), - MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14), - MX1_PAD_LD0 = PAD_ID(PD, 15), - MX1_PAD_LD1 = PAD_ID(PD, 16), - MX1_PAD_LD2 = PAD_ID(PD, 17), - MX1_PAD_LD3 = PAD_ID(PD, 18), - MX1_PAD_LD4 = PAD_ID(PD, 19), - MX1_PAD_LD5 = PAD_ID(PD, 20), - MX1_PAD_LD6 = PAD_ID(PD, 21), - MX1_PAD_LD7 = PAD_ID(PD, 22), - MX1_PAD_LD8 = PAD_ID(PD, 23), - MX1_PAD_LD9 = PAD_ID(PD, 24), - MX1_PAD_LD10 = PAD_ID(PD, 25), - MX1_PAD_LD11 = PAD_ID(PD, 26), - MX1_PAD_LD12 = PAD_ID(PD, 27), - MX1_PAD_LD13 = PAD_ID(PD, 28), - MX1_PAD_LD14 = PAD_ID(PD, 29), - MX1_PAD_LD15 = PAD_ID(PD, 30), - MX1_PAD_TMR2OUT = PAD_ID(PD, 31), -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX1_PAD_A24), - IMX_PINCTRL_PIN(MX1_PAD_TIN), - IMX_PINCTRL_PIN(MX1_PAD_PWMO), - IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK), - IMX_PINCTRL_PIN(MX1_PAD_CSI_D0), - IMX_PINCTRL_PIN(MX1_PAD_CSI_D1), - IMX_PINCTRL_PIN(MX1_PAD_CSI_D2), - IMX_PINCTRL_PIN(MX1_PAD_CSI_D3), - IMX_PINCTRL_PIN(MX1_PAD_CSI_D4), - IMX_PINCTRL_PIN(MX1_PAD_CSI_D5), - IMX_PINCTRL_PIN(MX1_PAD_CSI_D6), - IMX_PINCTRL_PIN(MX1_PAD_CSI_D7), - IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC), - IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC), - IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK), - IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA), - IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL), - IMX_PINCTRL_PIN(MX1_PAD_DTACK), - IMX_PINCTRL_PIN(MX1_PAD_BCLK), - IMX_PINCTRL_PIN(MX1_PAD_LBA), - IMX_PINCTRL_PIN(MX1_PAD_ECB), - IMX_PINCTRL_PIN(MX1_PAD_A0), - IMX_PINCTRL_PIN(MX1_PAD_CS4), - IMX_PINCTRL_PIN(MX1_PAD_CS5), - IMX_PINCTRL_PIN(MX1_PAD_A16), - IMX_PINCTRL_PIN(MX1_PAD_A17), - IMX_PINCTRL_PIN(MX1_PAD_A18), - IMX_PINCTRL_PIN(MX1_PAD_A19), - IMX_PINCTRL_PIN(MX1_PAD_A20), - IMX_PINCTRL_PIN(MX1_PAD_A21), - IMX_PINCTRL_PIN(MX1_PAD_A22), - IMX_PINCTRL_PIN(MX1_PAD_A23), - IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0), - IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1), - IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2), - IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3), - IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK), - IMX_PINCTRL_PIN(MX1_PAD_SD_CMD), - IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN), - IMX_PINCTRL_PIN(MX1_PAD_SIM_PD), - IMX_PINCTRL_PIN(MX1_PAD_SIM_TX), - IMX_PINCTRL_PIN(MX1_PAD_SIM_RX), - IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK), - IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE), - IMX_PINCTRL_PIN(MX1_PAD_USBD_OE), - IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV), - IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND), - IMX_PINCTRL_PIN(MX1_PAD_USBD_VP), - IMX_PINCTRL_PIN(MX1_PAD_USBD_VM), - IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO), - IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO), - IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS), - IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS), - IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD), - IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD), - IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS), - IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK), - IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT), - IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT), - IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS), - IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK), - IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS), - IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS), - IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD), - IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD), - IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY), - IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK), - IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS), - IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO), - IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI), - IMX_PINCTRL_PIN(MX1_PAD_BT13), - IMX_PINCTRL_PIN(MX1_PAD_BT12), - IMX_PINCTRL_PIN(MX1_PAD_BT11), - IMX_PINCTRL_PIN(MX1_PAD_BT10), - IMX_PINCTRL_PIN(MX1_PAD_BT9), - IMX_PINCTRL_PIN(MX1_PAD_BT8), - IMX_PINCTRL_PIN(MX1_PAD_BT7), - IMX_PINCTRL_PIN(MX1_PAD_BT6), - IMX_PINCTRL_PIN(MX1_PAD_BT5), - IMX_PINCTRL_PIN(MX1_PAD_BT4), - IMX_PINCTRL_PIN(MX1_PAD_BT3), - IMX_PINCTRL_PIN(MX1_PAD_BT2), - IMX_PINCTRL_PIN(MX1_PAD_BT1), - IMX_PINCTRL_PIN(MX1_PAD_LSCLK), - IMX_PINCTRL_PIN(MX1_PAD_REV), - IMX_PINCTRL_PIN(MX1_PAD_CLS), - IMX_PINCTRL_PIN(MX1_PAD_PS), - IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR), - IMX_PINCTRL_PIN(MX1_PAD_CONTRAST), - IMX_PINCTRL_PIN(MX1_PAD_ACD_OE), - IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC), - IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC), - IMX_PINCTRL_PIN(MX1_PAD_LD0), - IMX_PINCTRL_PIN(MX1_PAD_LD1), - IMX_PINCTRL_PIN(MX1_PAD_LD2), - IMX_PINCTRL_PIN(MX1_PAD_LD3), - IMX_PINCTRL_PIN(MX1_PAD_LD4), - IMX_PINCTRL_PIN(MX1_PAD_LD5), - IMX_PINCTRL_PIN(MX1_PAD_LD6), - IMX_PINCTRL_PIN(MX1_PAD_LD7), - IMX_PINCTRL_PIN(MX1_PAD_LD8), - IMX_PINCTRL_PIN(MX1_PAD_LD9), - IMX_PINCTRL_PIN(MX1_PAD_LD10), - IMX_PINCTRL_PIN(MX1_PAD_LD11), - IMX_PINCTRL_PIN(MX1_PAD_LD12), - IMX_PINCTRL_PIN(MX1_PAD_LD13), - IMX_PINCTRL_PIN(MX1_PAD_LD14), - IMX_PINCTRL_PIN(MX1_PAD_LD15), - IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT), -}; - -static struct imx1_pinctrl_soc_info imx1_pinctrl_info = { - .pins = imx1_pinctrl_pads, - .npins = ARRAY_SIZE(imx1_pinctrl_pads), -}; - -static int __init imx1_pinctrl_probe(struct platform_device *pdev) -{ - return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info); -} - -static const struct of_device_id imx1_pinctrl_of_match[] = { - { .compatible = "fsl,imx1-iomuxc", }, - { } -}; -MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match); - -static struct platform_driver imx1_pinctrl_driver = { - .driver = { - .name = "imx1-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx1_pinctrl_of_match, - }, - .remove = imx1_pinctrl_core_remove, -}; -module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe); - -MODULE_AUTHOR("Alexander Shiyan "); -MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-imx1.h b/drivers/pinctrl/pinctrl-imx1.h deleted file mode 100644 index 692a54c15cda..000000000000 --- a/drivers/pinctrl/pinctrl-imx1.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * IMX pinmux core definitions - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro Ltd. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __DRIVERS_PINCTRL_IMX1_H -#define __DRIVERS_PINCTRL_IMX1_H - -struct platform_device; - -/** - * struct imx1_pin - describes an IMX1/21/27 pin. - * @pin_id: ID of the described pin. - * @mux_id: ID of the mux setup. - * @config: Configuration of the pin (currently only pullup-enable). - */ -struct imx1_pin { - unsigned int pin_id; - unsigned int mux_id; - unsigned long config; -}; - -/** - * struct imx1_pin_group - describes an IMX pin group - * @name: the name of this specific pin group - * @pins: an array of imx1_pin structs used in this group - * @npins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - */ -struct imx1_pin_group { - const char *name; - unsigned int *pin_ids; - struct imx1_pin *pins; - unsigned npins; -}; - -/** - * struct imx1_pmx_func - describes IMX pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @num_groups: the number of groups - */ -struct imx1_pmx_func { - const char *name; - const char **groups; - unsigned num_groups; -}; - -struct imx1_pinctrl_soc_info { - struct device *dev; - const struct pinctrl_pin_desc *pins; - unsigned int npins; - struct imx1_pin_group *groups; - unsigned int ngroups; - struct imx1_pmx_func *functions; - unsigned int nfunctions; -}; - -#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) - -int imx1_pinctrl_core_probe(struct platform_device *pdev, - struct imx1_pinctrl_soc_info *info); -int imx1_pinctrl_core_remove(struct platform_device *pdev); -#endif /* __DRIVERS_PINCTRL_IMX1_H */ diff --git a/drivers/pinctrl/pinctrl-imx21.c b/drivers/pinctrl/pinctrl-imx21.c deleted file mode 100644 index 1b3b2311b033..000000000000 --- a/drivers/pinctrl/pinctrl-imx21.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * i.MX21 pinctrl driver based on imx pinmux core - * - * Copyright (C) 2014 Alexander Shiyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include - -#include "pinctrl-imx1.h" - -#define PAD_ID(port, pin) ((port) * 32 + (pin)) -#define PA 0 -#define PB 1 -#define PC 2 -#define PD 3 -#define PE 4 -#define PF 5 - -enum imx21_pads { - MX21_PAD_LSCLK = PAD_ID(PA, 5), - MX21_PAD_LD0 = PAD_ID(PA, 6), - MX21_PAD_LD1 = PAD_ID(PA, 7), - MX21_PAD_LD2 = PAD_ID(PA, 8), - MX21_PAD_LD3 = PAD_ID(PA, 9), - MX21_PAD_LD4 = PAD_ID(PA, 10), - MX21_PAD_LD5 = PAD_ID(PA, 11), - MX21_PAD_LD6 = PAD_ID(PA, 12), - MX21_PAD_LD7 = PAD_ID(PA, 13), - MX21_PAD_LD8 = PAD_ID(PA, 14), - MX21_PAD_LD9 = PAD_ID(PA, 15), - MX21_PAD_LD10 = PAD_ID(PA, 16), - MX21_PAD_LD11 = PAD_ID(PA, 17), - MX21_PAD_LD12 = PAD_ID(PA, 18), - MX21_PAD_LD13 = PAD_ID(PA, 19), - MX21_PAD_LD14 = PAD_ID(PA, 20), - MX21_PAD_LD15 = PAD_ID(PA, 21), - MX21_PAD_LD16 = PAD_ID(PA, 22), - MX21_PAD_LD17 = PAD_ID(PA, 23), - MX21_PAD_REV = PAD_ID(PA, 24), - MX21_PAD_CLS = PAD_ID(PA, 25), - MX21_PAD_PS = PAD_ID(PA, 26), - MX21_PAD_SPL_SPR = PAD_ID(PA, 27), - MX21_PAD_HSYNC = PAD_ID(PA, 28), - MX21_PAD_VSYNC = PAD_ID(PA, 29), - MX21_PAD_CONTRAST = PAD_ID(PA, 30), - MX21_PAD_OE_ACD = PAD_ID(PA, 31), - MX21_PAD_SD2_D0 = PAD_ID(PB, 4), - MX21_PAD_SD2_D1 = PAD_ID(PB, 5), - MX21_PAD_SD2_D2 = PAD_ID(PB, 6), - MX21_PAD_SD2_D3 = PAD_ID(PB, 7), - MX21_PAD_SD2_CMD = PAD_ID(PB, 8), - MX21_PAD_SD2_CLK = PAD_ID(PB, 9), - MX21_PAD_CSI_D0 = PAD_ID(PB, 10), - MX21_PAD_CSI_D1 = PAD_ID(PB, 11), - MX21_PAD_CSI_D2 = PAD_ID(PB, 12), - MX21_PAD_CSI_D3 = PAD_ID(PB, 13), - MX21_PAD_CSI_D4 = PAD_ID(PB, 14), - MX21_PAD_CSI_MCLK = PAD_ID(PB, 15), - MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16), - MX21_PAD_CSI_D5 = PAD_ID(PB, 17), - MX21_PAD_CSI_D6 = PAD_ID(PB, 18), - MX21_PAD_CSI_D7 = PAD_ID(PB, 19), - MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20), - MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21), - MX21_PAD_USB_BYP = PAD_ID(PB, 22), - MX21_PAD_USB_PWR = PAD_ID(PB, 23), - MX21_PAD_USB_OC = PAD_ID(PB, 24), - MX21_PAD_USBH_ON = PAD_ID(PB, 25), - MX21_PAD_USBH1_FS = PAD_ID(PB, 26), - MX21_PAD_USBH1_OE = PAD_ID(PB, 27), - MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28), - MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29), - MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30), - MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31), - MX21_PAD_USBG_SDA = PAD_ID(PC, 5), - MX21_PAD_USBG_SCL = PAD_ID(PC, 6), - MX21_PAD_USBG_ON = PAD_ID(PC, 7), - MX21_PAD_USBG_FS = PAD_ID(PC, 8), - MX21_PAD_USBG_OE = PAD_ID(PC, 9), - MX21_PAD_USBG_TXDM = PAD_ID(PC, 10), - MX21_PAD_USBG_TXDP = PAD_ID(PC, 11), - MX21_PAD_USBG_RXDM = PAD_ID(PC, 12), - MX21_PAD_USBG_RXDP = PAD_ID(PC, 13), - MX21_PAD_TOUT = PAD_ID(PC, 14), - MX21_PAD_TIN = PAD_ID(PC, 15), - MX21_PAD_SAP_FS = PAD_ID(PC, 16), - MX21_PAD_SAP_RXD = PAD_ID(PC, 17), - MX21_PAD_SAP_TXD = PAD_ID(PC, 18), - MX21_PAD_SAP_CLK = PAD_ID(PC, 19), - MX21_PAD_SSI1_FS = PAD_ID(PC, 20), - MX21_PAD_SSI1_RXD = PAD_ID(PC, 21), - MX21_PAD_SSI1_TXD = PAD_ID(PC, 22), - MX21_PAD_SSI1_CLK = PAD_ID(PC, 23), - MX21_PAD_SSI2_FS = PAD_ID(PC, 24), - MX21_PAD_SSI2_RXD = PAD_ID(PC, 25), - MX21_PAD_SSI2_TXD = PAD_ID(PC, 26), - MX21_PAD_SSI2_CLK = PAD_ID(PC, 27), - MX21_PAD_SSI3_FS = PAD_ID(PC, 28), - MX21_PAD_SSI3_RXD = PAD_ID(PC, 29), - MX21_PAD_SSI3_TXD = PAD_ID(PC, 30), - MX21_PAD_SSI3_CLK = PAD_ID(PC, 31), - MX21_PAD_I2C_DATA = PAD_ID(PD, 17), - MX21_PAD_I2C_CLK = PAD_ID(PD, 18), - MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19), - MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20), - MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21), - MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22), - MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23), - MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24), - MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25), - MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26), - MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27), - MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28), - MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29), - MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30), - MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31), - MX21_PAD_TEST_WB2 = PAD_ID(PE, 0), - MX21_PAD_TEST_WB1 = PAD_ID(PE, 1), - MX21_PAD_TEST_WB0 = PAD_ID(PE, 2), - MX21_PAD_UART2_CTS = PAD_ID(PE, 3), - MX21_PAD_UART2_RTS = PAD_ID(PE, 4), - MX21_PAD_PWMO = PAD_ID(PE, 5), - MX21_PAD_UART2_TXD = PAD_ID(PE, 6), - MX21_PAD_UART2_RXD = PAD_ID(PE, 7), - MX21_PAD_UART3_TXD = PAD_ID(PE, 8), - MX21_PAD_UART3_RXD = PAD_ID(PE, 9), - MX21_PAD_UART3_CTS = PAD_ID(PE, 10), - MX21_PAD_UART3_RTS = PAD_ID(PE, 11), - MX21_PAD_UART1_TXD = PAD_ID(PE, 12), - MX21_PAD_UART1_RXD = PAD_ID(PE, 13), - MX21_PAD_UART1_CTS = PAD_ID(PE, 14), - MX21_PAD_UART1_RTS = PAD_ID(PE, 15), - MX21_PAD_RTCK = PAD_ID(PE, 16), - MX21_PAD_RESET_OUT = PAD_ID(PE, 17), - MX21_PAD_SD1_D0 = PAD_ID(PE, 18), - MX21_PAD_SD1_D1 = PAD_ID(PE, 19), - MX21_PAD_SD1_D2 = PAD_ID(PE, 20), - MX21_PAD_SD1_D3 = PAD_ID(PE, 21), - MX21_PAD_SD1_CMD = PAD_ID(PE, 22), - MX21_PAD_SD1_CLK = PAD_ID(PE, 23), - MX21_PAD_NFRB = PAD_ID(PF, 0), - MX21_PAD_NFCE = PAD_ID(PF, 1), - MX21_PAD_NFWP = PAD_ID(PF, 2), - MX21_PAD_NFCLE = PAD_ID(PF, 3), - MX21_PAD_NFALE = PAD_ID(PF, 4), - MX21_PAD_NFRE = PAD_ID(PF, 5), - MX21_PAD_NFWE = PAD_ID(PF, 6), - MX21_PAD_NFIO0 = PAD_ID(PF, 7), - MX21_PAD_NFIO1 = PAD_ID(PF, 8), - MX21_PAD_NFIO2 = PAD_ID(PF, 9), - MX21_PAD_NFIO3 = PAD_ID(PF, 10), - MX21_PAD_NFIO4 = PAD_ID(PF, 11), - MX21_PAD_NFIO5 = PAD_ID(PF, 12), - MX21_PAD_NFIO6 = PAD_ID(PF, 13), - MX21_PAD_NFIO7 = PAD_ID(PF, 14), - MX21_PAD_CLKO = PAD_ID(PF, 15), - MX21_PAD_RESERVED = PAD_ID(PF, 16), - MX21_PAD_CS4 = PAD_ID(PF, 21), - MX21_PAD_CS5 = PAD_ID(PF, 22), -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX21_PAD_LSCLK), - IMX_PINCTRL_PIN(MX21_PAD_LD0), - IMX_PINCTRL_PIN(MX21_PAD_LD1), - IMX_PINCTRL_PIN(MX21_PAD_LD2), - IMX_PINCTRL_PIN(MX21_PAD_LD3), - IMX_PINCTRL_PIN(MX21_PAD_LD4), - IMX_PINCTRL_PIN(MX21_PAD_LD5), - IMX_PINCTRL_PIN(MX21_PAD_LD6), - IMX_PINCTRL_PIN(MX21_PAD_LD7), - IMX_PINCTRL_PIN(MX21_PAD_LD8), - IMX_PINCTRL_PIN(MX21_PAD_LD9), - IMX_PINCTRL_PIN(MX21_PAD_LD10), - IMX_PINCTRL_PIN(MX21_PAD_LD11), - IMX_PINCTRL_PIN(MX21_PAD_LD12), - IMX_PINCTRL_PIN(MX21_PAD_LD13), - IMX_PINCTRL_PIN(MX21_PAD_LD14), - IMX_PINCTRL_PIN(MX21_PAD_LD15), - IMX_PINCTRL_PIN(MX21_PAD_LD16), - IMX_PINCTRL_PIN(MX21_PAD_LD17), - IMX_PINCTRL_PIN(MX21_PAD_REV), - IMX_PINCTRL_PIN(MX21_PAD_CLS), - IMX_PINCTRL_PIN(MX21_PAD_PS), - IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR), - IMX_PINCTRL_PIN(MX21_PAD_HSYNC), - IMX_PINCTRL_PIN(MX21_PAD_VSYNC), - IMX_PINCTRL_PIN(MX21_PAD_CONTRAST), - IMX_PINCTRL_PIN(MX21_PAD_OE_ACD), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D0), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D1), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D2), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D3), - IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D0), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D1), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D2), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D3), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D4), - IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D5), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D6), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D7), - IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC), - IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC), - IMX_PINCTRL_PIN(MX21_PAD_USB_BYP), - IMX_PINCTRL_PIN(MX21_PAD_USB_PWR), - IMX_PINCTRL_PIN(MX21_PAD_USB_OC), - IMX_PINCTRL_PIN(MX21_PAD_USBH_ON), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA), - IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL), - IMX_PINCTRL_PIN(MX21_PAD_USBG_ON), - IMX_PINCTRL_PIN(MX21_PAD_USBG_FS), - IMX_PINCTRL_PIN(MX21_PAD_USBG_OE), - IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP), - IMX_PINCTRL_PIN(MX21_PAD_TOUT), - IMX_PINCTRL_PIN(MX21_PAD_TIN), - IMX_PINCTRL_PIN(MX21_PAD_SAP_FS), - IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK), - IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS), - IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK), - IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA), - IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO), - IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO), - IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI), - IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2), - IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1), - IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0), - IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS), - IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS), - IMX_PINCTRL_PIN(MX21_PAD_PWMO), - IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD), - IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD), - IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD), - IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD), - IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS), - IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS), - IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD), - IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD), - IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS), - IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS), - IMX_PINCTRL_PIN(MX21_PAD_RTCK), - IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT), - IMX_PINCTRL_PIN(MX21_PAD_SD1_D0), - IMX_PINCTRL_PIN(MX21_PAD_SD1_D1), - IMX_PINCTRL_PIN(MX21_PAD_SD1_D2), - IMX_PINCTRL_PIN(MX21_PAD_SD1_D3), - IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX21_PAD_NFRB), - IMX_PINCTRL_PIN(MX21_PAD_NFCE), - IMX_PINCTRL_PIN(MX21_PAD_NFWP), - IMX_PINCTRL_PIN(MX21_PAD_NFCLE), - IMX_PINCTRL_PIN(MX21_PAD_NFALE), - IMX_PINCTRL_PIN(MX21_PAD_NFRE), - IMX_PINCTRL_PIN(MX21_PAD_NFWE), - IMX_PINCTRL_PIN(MX21_PAD_NFIO0), - IMX_PINCTRL_PIN(MX21_PAD_NFIO1), - IMX_PINCTRL_PIN(MX21_PAD_NFIO2), - IMX_PINCTRL_PIN(MX21_PAD_NFIO3), - IMX_PINCTRL_PIN(MX21_PAD_NFIO4), - IMX_PINCTRL_PIN(MX21_PAD_NFIO5), - IMX_PINCTRL_PIN(MX21_PAD_NFIO6), - IMX_PINCTRL_PIN(MX21_PAD_NFIO7), - IMX_PINCTRL_PIN(MX21_PAD_CLKO), - IMX_PINCTRL_PIN(MX21_PAD_RESERVED), - IMX_PINCTRL_PIN(MX21_PAD_CS4), - IMX_PINCTRL_PIN(MX21_PAD_CS5), -}; - -static struct imx1_pinctrl_soc_info imx21_pinctrl_info = { - .pins = imx21_pinctrl_pads, - .npins = ARRAY_SIZE(imx21_pinctrl_pads), -}; - -static int __init imx21_pinctrl_probe(struct platform_device *pdev) -{ - return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info); -} - -static const struct of_device_id imx21_pinctrl_of_match[] = { - { .compatible = "fsl,imx21-iomuxc", }, - { } -}; -MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match); - -static struct platform_driver imx21_pinctrl_driver = { - .driver = { - .name = "imx21-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx21_pinctrl_of_match, - }, - .remove = imx1_pinctrl_core_remove, -}; -module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe); - -MODULE_AUTHOR("Alexander Shiyan "); -MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c deleted file mode 100644 index df79096becb0..000000000000 --- a/drivers/pinctrl/pinctrl-imx23.c +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include "pinctrl-mxs.h" - -enum imx23_pin_enum { - GPMI_D00 = PINID(0, 0), - GPMI_D01 = PINID(0, 1), - GPMI_D02 = PINID(0, 2), - GPMI_D03 = PINID(0, 3), - GPMI_D04 = PINID(0, 4), - GPMI_D05 = PINID(0, 5), - GPMI_D06 = PINID(0, 6), - GPMI_D07 = PINID(0, 7), - GPMI_D08 = PINID(0, 8), - GPMI_D09 = PINID(0, 9), - GPMI_D10 = PINID(0, 10), - GPMI_D11 = PINID(0, 11), - GPMI_D12 = PINID(0, 12), - GPMI_D13 = PINID(0, 13), - GPMI_D14 = PINID(0, 14), - GPMI_D15 = PINID(0, 15), - GPMI_CLE = PINID(0, 16), - GPMI_ALE = PINID(0, 17), - GPMI_CE2N = PINID(0, 18), - GPMI_RDY0 = PINID(0, 19), - GPMI_RDY1 = PINID(0, 20), - GPMI_RDY2 = PINID(0, 21), - GPMI_RDY3 = PINID(0, 22), - GPMI_WPN = PINID(0, 23), - GPMI_WRN = PINID(0, 24), - GPMI_RDN = PINID(0, 25), - AUART1_CTS = PINID(0, 26), - AUART1_RTS = PINID(0, 27), - AUART1_RX = PINID(0, 28), - AUART1_TX = PINID(0, 29), - I2C_SCL = PINID(0, 30), - I2C_SDA = PINID(0, 31), - LCD_D00 = PINID(1, 0), - LCD_D01 = PINID(1, 1), - LCD_D02 = PINID(1, 2), - LCD_D03 = PINID(1, 3), - LCD_D04 = PINID(1, 4), - LCD_D05 = PINID(1, 5), - LCD_D06 = PINID(1, 6), - LCD_D07 = PINID(1, 7), - LCD_D08 = PINID(1, 8), - LCD_D09 = PINID(1, 9), - LCD_D10 = PINID(1, 10), - LCD_D11 = PINID(1, 11), - LCD_D12 = PINID(1, 12), - LCD_D13 = PINID(1, 13), - LCD_D14 = PINID(1, 14), - LCD_D15 = PINID(1, 15), - LCD_D16 = PINID(1, 16), - LCD_D17 = PINID(1, 17), - LCD_RESET = PINID(1, 18), - LCD_RS = PINID(1, 19), - LCD_WR = PINID(1, 20), - LCD_CS = PINID(1, 21), - LCD_DOTCK = PINID(1, 22), - LCD_ENABLE = PINID(1, 23), - LCD_HSYNC = PINID(1, 24), - LCD_VSYNC = PINID(1, 25), - PWM0 = PINID(1, 26), - PWM1 = PINID(1, 27), - PWM2 = PINID(1, 28), - PWM3 = PINID(1, 29), - PWM4 = PINID(1, 30), - SSP1_CMD = PINID(2, 0), - SSP1_DETECT = PINID(2, 1), - SSP1_DATA0 = PINID(2, 2), - SSP1_DATA1 = PINID(2, 3), - SSP1_DATA2 = PINID(2, 4), - SSP1_DATA3 = PINID(2, 5), - SSP1_SCK = PINID(2, 6), - ROTARYA = PINID(2, 7), - ROTARYB = PINID(2, 8), - EMI_A00 = PINID(2, 9), - EMI_A01 = PINID(2, 10), - EMI_A02 = PINID(2, 11), - EMI_A03 = PINID(2, 12), - EMI_A04 = PINID(2, 13), - EMI_A05 = PINID(2, 14), - EMI_A06 = PINID(2, 15), - EMI_A07 = PINID(2, 16), - EMI_A08 = PINID(2, 17), - EMI_A09 = PINID(2, 18), - EMI_A10 = PINID(2, 19), - EMI_A11 = PINID(2, 20), - EMI_A12 = PINID(2, 21), - EMI_BA0 = PINID(2, 22), - EMI_BA1 = PINID(2, 23), - EMI_CASN = PINID(2, 24), - EMI_CE0N = PINID(2, 25), - EMI_CE1N = PINID(2, 26), - GPMI_CE1N = PINID(2, 27), - GPMI_CE0N = PINID(2, 28), - EMI_CKE = PINID(2, 29), - EMI_RASN = PINID(2, 30), - EMI_WEN = PINID(2, 31), - EMI_D00 = PINID(3, 0), - EMI_D01 = PINID(3, 1), - EMI_D02 = PINID(3, 2), - EMI_D03 = PINID(3, 3), - EMI_D04 = PINID(3, 4), - EMI_D05 = PINID(3, 5), - EMI_D06 = PINID(3, 6), - EMI_D07 = PINID(3, 7), - EMI_D08 = PINID(3, 8), - EMI_D09 = PINID(3, 9), - EMI_D10 = PINID(3, 10), - EMI_D11 = PINID(3, 11), - EMI_D12 = PINID(3, 12), - EMI_D13 = PINID(3, 13), - EMI_D14 = PINID(3, 14), - EMI_D15 = PINID(3, 15), - EMI_DQM0 = PINID(3, 16), - EMI_DQM1 = PINID(3, 17), - EMI_DQS0 = PINID(3, 18), - EMI_DQS1 = PINID(3, 19), - EMI_CLK = PINID(3, 20), - EMI_CLKN = PINID(3, 21), -}; - -static const struct pinctrl_pin_desc imx23_pins[] = { - MXS_PINCTRL_PIN(GPMI_D00), - MXS_PINCTRL_PIN(GPMI_D01), - MXS_PINCTRL_PIN(GPMI_D02), - MXS_PINCTRL_PIN(GPMI_D03), - MXS_PINCTRL_PIN(GPMI_D04), - MXS_PINCTRL_PIN(GPMI_D05), - MXS_PINCTRL_PIN(GPMI_D06), - MXS_PINCTRL_PIN(GPMI_D07), - MXS_PINCTRL_PIN(GPMI_D08), - MXS_PINCTRL_PIN(GPMI_D09), - MXS_PINCTRL_PIN(GPMI_D10), - MXS_PINCTRL_PIN(GPMI_D11), - MXS_PINCTRL_PIN(GPMI_D12), - MXS_PINCTRL_PIN(GPMI_D13), - MXS_PINCTRL_PIN(GPMI_D14), - MXS_PINCTRL_PIN(GPMI_D15), - MXS_PINCTRL_PIN(GPMI_CLE), - MXS_PINCTRL_PIN(GPMI_ALE), - MXS_PINCTRL_PIN(GPMI_CE2N), - MXS_PINCTRL_PIN(GPMI_RDY0), - MXS_PINCTRL_PIN(GPMI_RDY1), - MXS_PINCTRL_PIN(GPMI_RDY2), - MXS_PINCTRL_PIN(GPMI_RDY3), - MXS_PINCTRL_PIN(GPMI_WPN), - MXS_PINCTRL_PIN(GPMI_WRN), - MXS_PINCTRL_PIN(GPMI_RDN), - MXS_PINCTRL_PIN(AUART1_CTS), - MXS_PINCTRL_PIN(AUART1_RTS), - MXS_PINCTRL_PIN(AUART1_RX), - MXS_PINCTRL_PIN(AUART1_TX), - MXS_PINCTRL_PIN(I2C_SCL), - MXS_PINCTRL_PIN(I2C_SDA), - MXS_PINCTRL_PIN(LCD_D00), - MXS_PINCTRL_PIN(LCD_D01), - MXS_PINCTRL_PIN(LCD_D02), - MXS_PINCTRL_PIN(LCD_D03), - MXS_PINCTRL_PIN(LCD_D04), - MXS_PINCTRL_PIN(LCD_D05), - MXS_PINCTRL_PIN(LCD_D06), - MXS_PINCTRL_PIN(LCD_D07), - MXS_PINCTRL_PIN(LCD_D08), - MXS_PINCTRL_PIN(LCD_D09), - MXS_PINCTRL_PIN(LCD_D10), - MXS_PINCTRL_PIN(LCD_D11), - MXS_PINCTRL_PIN(LCD_D12), - MXS_PINCTRL_PIN(LCD_D13), - MXS_PINCTRL_PIN(LCD_D14), - MXS_PINCTRL_PIN(LCD_D15), - MXS_PINCTRL_PIN(LCD_D16), - MXS_PINCTRL_PIN(LCD_D17), - MXS_PINCTRL_PIN(LCD_RESET), - MXS_PINCTRL_PIN(LCD_RS), - MXS_PINCTRL_PIN(LCD_WR), - MXS_PINCTRL_PIN(LCD_CS), - MXS_PINCTRL_PIN(LCD_DOTCK), - MXS_PINCTRL_PIN(LCD_ENABLE), - MXS_PINCTRL_PIN(LCD_HSYNC), - MXS_PINCTRL_PIN(LCD_VSYNC), - MXS_PINCTRL_PIN(PWM0), - MXS_PINCTRL_PIN(PWM1), - MXS_PINCTRL_PIN(PWM2), - MXS_PINCTRL_PIN(PWM3), - MXS_PINCTRL_PIN(PWM4), - MXS_PINCTRL_PIN(SSP1_CMD), - MXS_PINCTRL_PIN(SSP1_DETECT), - MXS_PINCTRL_PIN(SSP1_DATA0), - MXS_PINCTRL_PIN(SSP1_DATA1), - MXS_PINCTRL_PIN(SSP1_DATA2), - MXS_PINCTRL_PIN(SSP1_DATA3), - MXS_PINCTRL_PIN(SSP1_SCK), - MXS_PINCTRL_PIN(ROTARYA), - MXS_PINCTRL_PIN(ROTARYB), - MXS_PINCTRL_PIN(EMI_A00), - MXS_PINCTRL_PIN(EMI_A01), - MXS_PINCTRL_PIN(EMI_A02), - MXS_PINCTRL_PIN(EMI_A03), - MXS_PINCTRL_PIN(EMI_A04), - MXS_PINCTRL_PIN(EMI_A05), - MXS_PINCTRL_PIN(EMI_A06), - MXS_PINCTRL_PIN(EMI_A07), - MXS_PINCTRL_PIN(EMI_A08), - MXS_PINCTRL_PIN(EMI_A09), - MXS_PINCTRL_PIN(EMI_A10), - MXS_PINCTRL_PIN(EMI_A11), - MXS_PINCTRL_PIN(EMI_A12), - MXS_PINCTRL_PIN(EMI_BA0), - MXS_PINCTRL_PIN(EMI_BA1), - MXS_PINCTRL_PIN(EMI_CASN), - MXS_PINCTRL_PIN(EMI_CE0N), - MXS_PINCTRL_PIN(EMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE0N), - MXS_PINCTRL_PIN(EMI_CKE), - MXS_PINCTRL_PIN(EMI_RASN), - MXS_PINCTRL_PIN(EMI_WEN), - MXS_PINCTRL_PIN(EMI_D00), - MXS_PINCTRL_PIN(EMI_D01), - MXS_PINCTRL_PIN(EMI_D02), - MXS_PINCTRL_PIN(EMI_D03), - MXS_PINCTRL_PIN(EMI_D04), - MXS_PINCTRL_PIN(EMI_D05), - MXS_PINCTRL_PIN(EMI_D06), - MXS_PINCTRL_PIN(EMI_D07), - MXS_PINCTRL_PIN(EMI_D08), - MXS_PINCTRL_PIN(EMI_D09), - MXS_PINCTRL_PIN(EMI_D10), - MXS_PINCTRL_PIN(EMI_D11), - MXS_PINCTRL_PIN(EMI_D12), - MXS_PINCTRL_PIN(EMI_D13), - MXS_PINCTRL_PIN(EMI_D14), - MXS_PINCTRL_PIN(EMI_D15), - MXS_PINCTRL_PIN(EMI_DQM0), - MXS_PINCTRL_PIN(EMI_DQM1), - MXS_PINCTRL_PIN(EMI_DQS0), - MXS_PINCTRL_PIN(EMI_DQS1), - MXS_PINCTRL_PIN(EMI_CLK), - MXS_PINCTRL_PIN(EMI_CLKN), -}; - -static struct mxs_regs imx23_regs = { - .muxsel = 0x100, - .drive = 0x200, - .pull = 0x400, -}; - -static struct mxs_pinctrl_soc_data imx23_pinctrl_data = { - .regs = &imx23_regs, - .pins = imx23_pins, - .npins = ARRAY_SIZE(imx23_pins), -}; - -static int imx23_pinctrl_probe(struct platform_device *pdev) -{ - return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data); -} - -static const struct of_device_id imx23_pinctrl_of_match[] = { - { .compatible = "fsl,imx23-pinctrl", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match); - -static struct platform_driver imx23_pinctrl_driver = { - .driver = { - .name = "imx23-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx23_pinctrl_of_match, - }, - .probe = imx23_pinctrl_probe, - .remove = mxs_pinctrl_remove, -}; - -static int __init imx23_pinctrl_init(void) -{ - return platform_driver_register(&imx23_pinctrl_driver); -} -postcore_initcall(imx23_pinctrl_init); - -static void __exit imx23_pinctrl_exit(void) -{ - platform_driver_unregister(&imx23_pinctrl_driver); -} -module_exit(imx23_pinctrl_exit); - -MODULE_AUTHOR("Shawn Guo "); -MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx25.c b/drivers/pinctrl/pinctrl-imx25.c deleted file mode 100644 index 550e6d77ac2b..000000000000 --- a/drivers/pinctrl/pinctrl-imx25.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * imx25 pinctrl driver. - * - * Copyright 2013 Eukréa Electromatique - * - * This driver was mostly copied from the imx51 pinctrl driver which has: - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro, Inc. - * - * Author: Denis Carikli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx25_pads { - MX25_PAD_RESERVE0 = 1, - MX25_PAD_RESERVE1 = 2, - MX25_PAD_A10 = 3, - MX25_PAD_A13 = 4, - MX25_PAD_A14 = 5, - MX25_PAD_A15 = 6, - MX25_PAD_A16 = 7, - MX25_PAD_A17 = 8, - MX25_PAD_A18 = 9, - MX25_PAD_A19 = 10, - MX25_PAD_A20 = 11, - MX25_PAD_A21 = 12, - MX25_PAD_A22 = 13, - MX25_PAD_A23 = 14, - MX25_PAD_A24 = 15, - MX25_PAD_A25 = 16, - MX25_PAD_EB0 = 17, - MX25_PAD_EB1 = 18, - MX25_PAD_OE = 19, - MX25_PAD_CS0 = 20, - MX25_PAD_CS1 = 21, - MX25_PAD_CS4 = 22, - MX25_PAD_CS5 = 23, - MX25_PAD_NF_CE0 = 24, - MX25_PAD_ECB = 25, - MX25_PAD_LBA = 26, - MX25_PAD_BCLK = 27, - MX25_PAD_RW = 28, - MX25_PAD_NFWE_B = 29, - MX25_PAD_NFRE_B = 30, - MX25_PAD_NFALE = 31, - MX25_PAD_NFCLE = 32, - MX25_PAD_NFWP_B = 33, - MX25_PAD_NFRB = 34, - MX25_PAD_D15 = 35, - MX25_PAD_D14 = 36, - MX25_PAD_D13 = 37, - MX25_PAD_D12 = 38, - MX25_PAD_D11 = 39, - MX25_PAD_D10 = 40, - MX25_PAD_D9 = 41, - MX25_PAD_D8 = 42, - MX25_PAD_D7 = 43, - MX25_PAD_D6 = 44, - MX25_PAD_D5 = 45, - MX25_PAD_D4 = 46, - MX25_PAD_D3 = 47, - MX25_PAD_D2 = 48, - MX25_PAD_D1 = 49, - MX25_PAD_D0 = 50, - MX25_PAD_LD0 = 51, - MX25_PAD_LD1 = 52, - MX25_PAD_LD2 = 53, - MX25_PAD_LD3 = 54, - MX25_PAD_LD4 = 55, - MX25_PAD_LD5 = 56, - MX25_PAD_LD6 = 57, - MX25_PAD_LD7 = 58, - MX25_PAD_LD8 = 59, - MX25_PAD_LD9 = 60, - MX25_PAD_LD10 = 61, - MX25_PAD_LD11 = 62, - MX25_PAD_LD12 = 63, - MX25_PAD_LD13 = 64, - MX25_PAD_LD14 = 65, - MX25_PAD_LD15 = 66, - MX25_PAD_HSYNC = 67, - MX25_PAD_VSYNC = 68, - MX25_PAD_LSCLK = 69, - MX25_PAD_OE_ACD = 70, - MX25_PAD_CONTRAST = 71, - MX25_PAD_PWM = 72, - MX25_PAD_CSI_D2 = 73, - MX25_PAD_CSI_D3 = 74, - MX25_PAD_CSI_D4 = 75, - MX25_PAD_CSI_D5 = 76, - MX25_PAD_CSI_D6 = 77, - MX25_PAD_CSI_D7 = 78, - MX25_PAD_CSI_D8 = 79, - MX25_PAD_CSI_D9 = 80, - MX25_PAD_CSI_MCLK = 81, - MX25_PAD_CSI_VSYNC = 82, - MX25_PAD_CSI_HSYNC = 83, - MX25_PAD_CSI_PIXCLK = 84, - MX25_PAD_I2C1_CLK = 85, - MX25_PAD_I2C1_DAT = 86, - MX25_PAD_CSPI1_MOSI = 87, - MX25_PAD_CSPI1_MISO = 88, - MX25_PAD_CSPI1_SS0 = 89, - MX25_PAD_CSPI1_SS1 = 90, - MX25_PAD_CSPI1_SCLK = 91, - MX25_PAD_CSPI1_RDY = 92, - MX25_PAD_UART1_RXD = 93, - MX25_PAD_UART1_TXD = 94, - MX25_PAD_UART1_RTS = 95, - MX25_PAD_UART1_CTS = 96, - MX25_PAD_UART2_RXD = 97, - MX25_PAD_UART2_TXD = 98, - MX25_PAD_UART2_RTS = 99, - MX25_PAD_UART2_CTS = 100, - MX25_PAD_SD1_CMD = 101, - MX25_PAD_SD1_CLK = 102, - MX25_PAD_SD1_DATA0 = 103, - MX25_PAD_SD1_DATA1 = 104, - MX25_PAD_SD1_DATA2 = 105, - MX25_PAD_SD1_DATA3 = 106, - MX25_PAD_KPP_ROW0 = 107, - MX25_PAD_KPP_ROW1 = 108, - MX25_PAD_KPP_ROW2 = 109, - MX25_PAD_KPP_ROW3 = 110, - MX25_PAD_KPP_COL0 = 111, - MX25_PAD_KPP_COL1 = 112, - MX25_PAD_KPP_COL2 = 113, - MX25_PAD_KPP_COL3 = 114, - MX25_PAD_FEC_MDC = 115, - MX25_PAD_FEC_MDIO = 116, - MX25_PAD_FEC_TDATA0 = 117, - MX25_PAD_FEC_TDATA1 = 118, - MX25_PAD_FEC_TX_EN = 119, - MX25_PAD_FEC_RDATA0 = 120, - MX25_PAD_FEC_RDATA1 = 121, - MX25_PAD_FEC_RX_DV = 122, - MX25_PAD_FEC_TX_CLK = 123, - MX25_PAD_RTCK = 124, - MX25_PAD_DE_B = 125, - MX25_PAD_GPIO_A = 126, - MX25_PAD_GPIO_B = 127, - MX25_PAD_GPIO_C = 128, - MX25_PAD_GPIO_D = 129, - MX25_PAD_GPIO_E = 130, - MX25_PAD_GPIO_F = 131, - MX25_PAD_EXT_ARMCLK = 132, - MX25_PAD_UPLL_BYPCLK = 133, - MX25_PAD_VSTBY_REQ = 134, - MX25_PAD_VSTBY_ACK = 135, - MX25_PAD_POWER_FAIL = 136, - MX25_PAD_CLKO = 137, - MX25_PAD_BOOT_MODE0 = 138, - MX25_PAD_BOOT_MODE1 = 139, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX25_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX25_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX25_PAD_A10), - IMX_PINCTRL_PIN(MX25_PAD_A13), - IMX_PINCTRL_PIN(MX25_PAD_A14), - IMX_PINCTRL_PIN(MX25_PAD_A15), - IMX_PINCTRL_PIN(MX25_PAD_A16), - IMX_PINCTRL_PIN(MX25_PAD_A17), - IMX_PINCTRL_PIN(MX25_PAD_A18), - IMX_PINCTRL_PIN(MX25_PAD_A19), - IMX_PINCTRL_PIN(MX25_PAD_A20), - IMX_PINCTRL_PIN(MX25_PAD_A21), - IMX_PINCTRL_PIN(MX25_PAD_A22), - IMX_PINCTRL_PIN(MX25_PAD_A23), - IMX_PINCTRL_PIN(MX25_PAD_A24), - IMX_PINCTRL_PIN(MX25_PAD_A25), - IMX_PINCTRL_PIN(MX25_PAD_EB0), - IMX_PINCTRL_PIN(MX25_PAD_EB1), - IMX_PINCTRL_PIN(MX25_PAD_OE), - IMX_PINCTRL_PIN(MX25_PAD_CS0), - IMX_PINCTRL_PIN(MX25_PAD_CS1), - IMX_PINCTRL_PIN(MX25_PAD_CS4), - IMX_PINCTRL_PIN(MX25_PAD_CS5), - IMX_PINCTRL_PIN(MX25_PAD_NF_CE0), - IMX_PINCTRL_PIN(MX25_PAD_ECB), - IMX_PINCTRL_PIN(MX25_PAD_LBA), - IMX_PINCTRL_PIN(MX25_PAD_BCLK), - IMX_PINCTRL_PIN(MX25_PAD_RW), - IMX_PINCTRL_PIN(MX25_PAD_NFWE_B), - IMX_PINCTRL_PIN(MX25_PAD_NFRE_B), - IMX_PINCTRL_PIN(MX25_PAD_NFALE), - IMX_PINCTRL_PIN(MX25_PAD_NFCLE), - IMX_PINCTRL_PIN(MX25_PAD_NFWP_B), - IMX_PINCTRL_PIN(MX25_PAD_NFRB), - IMX_PINCTRL_PIN(MX25_PAD_D15), - IMX_PINCTRL_PIN(MX25_PAD_D14), - IMX_PINCTRL_PIN(MX25_PAD_D13), - IMX_PINCTRL_PIN(MX25_PAD_D12), - IMX_PINCTRL_PIN(MX25_PAD_D11), - IMX_PINCTRL_PIN(MX25_PAD_D10), - IMX_PINCTRL_PIN(MX25_PAD_D9), - IMX_PINCTRL_PIN(MX25_PAD_D8), - IMX_PINCTRL_PIN(MX25_PAD_D7), - IMX_PINCTRL_PIN(MX25_PAD_D6), - IMX_PINCTRL_PIN(MX25_PAD_D5), - IMX_PINCTRL_PIN(MX25_PAD_D4), - IMX_PINCTRL_PIN(MX25_PAD_D3), - IMX_PINCTRL_PIN(MX25_PAD_D2), - IMX_PINCTRL_PIN(MX25_PAD_D1), - IMX_PINCTRL_PIN(MX25_PAD_D0), - IMX_PINCTRL_PIN(MX25_PAD_LD0), - IMX_PINCTRL_PIN(MX25_PAD_LD1), - IMX_PINCTRL_PIN(MX25_PAD_LD2), - IMX_PINCTRL_PIN(MX25_PAD_LD3), - IMX_PINCTRL_PIN(MX25_PAD_LD4), - IMX_PINCTRL_PIN(MX25_PAD_LD5), - IMX_PINCTRL_PIN(MX25_PAD_LD6), - IMX_PINCTRL_PIN(MX25_PAD_LD7), - IMX_PINCTRL_PIN(MX25_PAD_LD8), - IMX_PINCTRL_PIN(MX25_PAD_LD9), - IMX_PINCTRL_PIN(MX25_PAD_LD10), - IMX_PINCTRL_PIN(MX25_PAD_LD11), - IMX_PINCTRL_PIN(MX25_PAD_LD12), - IMX_PINCTRL_PIN(MX25_PAD_LD13), - IMX_PINCTRL_PIN(MX25_PAD_LD14), - IMX_PINCTRL_PIN(MX25_PAD_LD15), - IMX_PINCTRL_PIN(MX25_PAD_HSYNC), - IMX_PINCTRL_PIN(MX25_PAD_VSYNC), - IMX_PINCTRL_PIN(MX25_PAD_LSCLK), - IMX_PINCTRL_PIN(MX25_PAD_OE_ACD), - IMX_PINCTRL_PIN(MX25_PAD_CONTRAST), - IMX_PINCTRL_PIN(MX25_PAD_PWM), - IMX_PINCTRL_PIN(MX25_PAD_CSI_D2), - IMX_PINCTRL_PIN(MX25_PAD_CSI_D3), - IMX_PINCTRL_PIN(MX25_PAD_CSI_D4), - IMX_PINCTRL_PIN(MX25_PAD_CSI_D5), - IMX_PINCTRL_PIN(MX25_PAD_CSI_D6), - IMX_PINCTRL_PIN(MX25_PAD_CSI_D7), - IMX_PINCTRL_PIN(MX25_PAD_CSI_D8), - IMX_PINCTRL_PIN(MX25_PAD_CSI_D9), - IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK), - IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC), - IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC), - IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK), - IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK), - IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT), - IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI), - IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO), - IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0), - IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1), - IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK), - IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY), - IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD), - IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD), - IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS), - IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS), - IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD), - IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD), - IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS), - IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS), - IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0), - IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1), - IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2), - IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3), - IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0), - IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1), - IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2), - IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3), - IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0), - IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1), - IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2), - IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3), - IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC), - IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO), - IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0), - IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1), - IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN), - IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0), - IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1), - IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV), - IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK), - IMX_PINCTRL_PIN(MX25_PAD_RTCK), - IMX_PINCTRL_PIN(MX25_PAD_DE_B), - IMX_PINCTRL_PIN(MX25_PAD_GPIO_A), - IMX_PINCTRL_PIN(MX25_PAD_GPIO_B), - IMX_PINCTRL_PIN(MX25_PAD_GPIO_C), - IMX_PINCTRL_PIN(MX25_PAD_GPIO_D), - IMX_PINCTRL_PIN(MX25_PAD_GPIO_E), - IMX_PINCTRL_PIN(MX25_PAD_GPIO_F), - IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK), - IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK), - IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ), - IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK), - IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL), - IMX_PINCTRL_PIN(MX25_PAD_CLKO), - IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0), - IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1), -}; - -static struct imx_pinctrl_soc_info imx25_pinctrl_info = { - .pins = imx25_pinctrl_pads, - .npins = ARRAY_SIZE(imx25_pinctrl_pads), -}; - -static const struct of_device_id imx25_pinctrl_of_match[] = { - { .compatible = "fsl,imx25-iomuxc", }, - { /* sentinel */ } -}; - -static int imx25_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx25_pinctrl_info); -} - -static struct platform_driver imx25_pinctrl_driver = { - .driver = { - .name = "imx25-pinctrl", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx25_pinctrl_of_match), - }, - .probe = imx25_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx25_pinctrl_init(void) -{ - return platform_driver_register(&imx25_pinctrl_driver); -} -arch_initcall(imx25_pinctrl_init); - -static void __exit imx25_pinctrl_exit(void) -{ - platform_driver_unregister(&imx25_pinctrl_driver); -} -module_exit(imx25_pinctrl_exit); -MODULE_AUTHOR("Denis Carikli "); -MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c deleted file mode 100644 index 945eccadea74..000000000000 --- a/drivers/pinctrl/pinctrl-imx27.c +++ /dev/null @@ -1,425 +0,0 @@ -/* - * imx27 pinctrl driver based on imx pinmux core - * - * Copyright (C) 2013 Pengutronix - * - * Author: Markus Pargmann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx1.h" - -#define PAD_ID(port, pin) (port*32 + pin) -#define PA 0 -#define PB 1 -#define PC 2 -#define PD 3 -#define PE 4 -#define PF 5 - -enum imx27_pads { - MX27_PAD_USBH2_CLK = PAD_ID(PA, 0), - MX27_PAD_USBH2_DIR = PAD_ID(PA, 1), - MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2), - MX27_PAD_USBH2_NXT = PAD_ID(PA, 3), - MX27_PAD_USBH2_STP = PAD_ID(PA, 4), - MX27_PAD_LSCLK = PAD_ID(PA, 5), - MX27_PAD_LD0 = PAD_ID(PA, 6), - MX27_PAD_LD1 = PAD_ID(PA, 7), - MX27_PAD_LD2 = PAD_ID(PA, 8), - MX27_PAD_LD3 = PAD_ID(PA, 9), - MX27_PAD_LD4 = PAD_ID(PA, 10), - MX27_PAD_LD5 = PAD_ID(PA, 11), - MX27_PAD_LD6 = PAD_ID(PA, 12), - MX27_PAD_LD7 = PAD_ID(PA, 13), - MX27_PAD_LD8 = PAD_ID(PA, 14), - MX27_PAD_LD9 = PAD_ID(PA, 15), - MX27_PAD_LD10 = PAD_ID(PA, 16), - MX27_PAD_LD11 = PAD_ID(PA, 17), - MX27_PAD_LD12 = PAD_ID(PA, 18), - MX27_PAD_LD13 = PAD_ID(PA, 19), - MX27_PAD_LD14 = PAD_ID(PA, 20), - MX27_PAD_LD15 = PAD_ID(PA, 21), - MX27_PAD_LD16 = PAD_ID(PA, 22), - MX27_PAD_LD17 = PAD_ID(PA, 23), - MX27_PAD_REV = PAD_ID(PA, 24), - MX27_PAD_CLS = PAD_ID(PA, 25), - MX27_PAD_PS = PAD_ID(PA, 26), - MX27_PAD_SPL_SPR = PAD_ID(PA, 27), - MX27_PAD_HSYNC = PAD_ID(PA, 28), - MX27_PAD_VSYNC = PAD_ID(PA, 29), - MX27_PAD_CONTRAST = PAD_ID(PA, 30), - MX27_PAD_OE_ACD = PAD_ID(PA, 31), - - MX27_PAD_SD2_D0 = PAD_ID(PB, 4), - MX27_PAD_SD2_D1 = PAD_ID(PB, 5), - MX27_PAD_SD2_D2 = PAD_ID(PB, 6), - MX27_PAD_SD2_D3 = PAD_ID(PB, 7), - MX27_PAD_SD2_CMD = PAD_ID(PB, 8), - MX27_PAD_SD2_CLK = PAD_ID(PB, 9), - MX27_PAD_CSI_D0 = PAD_ID(PB, 10), - MX27_PAD_CSI_D1 = PAD_ID(PB, 11), - MX27_PAD_CSI_D2 = PAD_ID(PB, 12), - MX27_PAD_CSI_D3 = PAD_ID(PB, 13), - MX27_PAD_CSI_D4 = PAD_ID(PB, 14), - MX27_PAD_CSI_MCLK = PAD_ID(PB, 15), - MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16), - MX27_PAD_CSI_D5 = PAD_ID(PB, 17), - MX27_PAD_CSI_D6 = PAD_ID(PB, 18), - MX27_PAD_CSI_D7 = PAD_ID(PB, 19), - MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20), - MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21), - MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22), - MX27_PAD_USB_PWR = PAD_ID(PB, 23), - MX27_PAD_USB_OC_B = PAD_ID(PB, 24), - MX27_PAD_USBH1_RCV = PAD_ID(PB, 25), - MX27_PAD_USBH1_FS = PAD_ID(PB, 26), - MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27), - MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28), - MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29), - MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), - MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), - - MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), - MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), - MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), - MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8), - MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9), - MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10), - MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11), - MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12), - MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13), - MX27_PAD_TOUT = PAD_ID(PC, 14), - MX27_PAD_TIN = PAD_ID(PC, 15), - MX27_PAD_SSI4_FS = PAD_ID(PC, 16), - MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17), - MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18), - MX27_PAD_SSI4_CLK = PAD_ID(PC, 19), - MX27_PAD_SSI1_FS = PAD_ID(PC, 20), - MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21), - MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22), - MX27_PAD_SSI1_CLK = PAD_ID(PC, 23), - MX27_PAD_SSI2_FS = PAD_ID(PC, 24), - MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25), - MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26), - MX27_PAD_SSI2_CLK = PAD_ID(PC, 27), - MX27_PAD_SSI3_FS = PAD_ID(PC, 28), - MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29), - MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30), - MX27_PAD_SSI3_CLK = PAD_ID(PC, 31), - - MX27_PAD_SD3_CMD = PAD_ID(PD, 0), - MX27_PAD_SD3_CLK = PAD_ID(PD, 1), - MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2), - MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3), - MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4), - MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5), - MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6), - MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7), - MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8), - MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9), - MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10), - MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11), - MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12), - MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13), - MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14), - MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15), - MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16), - MX27_PAD_I2C_DATA = PAD_ID(PD, 17), - MX27_PAD_I2C_CLK = PAD_ID(PD, 18), - MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19), - MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20), - MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21), - MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22), - MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23), - MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24), - MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25), - MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26), - MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27), - MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28), - MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29), - MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30), - MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31), - - MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0), - MX27_PAD_USBOTG_STP = PAD_ID(PE, 1), - MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2), - MX27_PAD_UART2_CTS = PAD_ID(PE, 3), - MX27_PAD_UART2_RTS = PAD_ID(PE, 4), - MX27_PAD_PWMO = PAD_ID(PE, 5), - MX27_PAD_UART2_TXD = PAD_ID(PE, 6), - MX27_PAD_UART2_RXD = PAD_ID(PE, 7), - MX27_PAD_UART3_TXD = PAD_ID(PE, 8), - MX27_PAD_UART3_RXD = PAD_ID(PE, 9), - MX27_PAD_UART3_CTS = PAD_ID(PE, 10), - MX27_PAD_UART3_RTS = PAD_ID(PE, 11), - MX27_PAD_UART1_TXD = PAD_ID(PE, 12), - MX27_PAD_UART1_RXD = PAD_ID(PE, 13), - MX27_PAD_UART1_CTS = PAD_ID(PE, 14), - MX27_PAD_UART1_RTS = PAD_ID(PE, 15), - MX27_PAD_RTCK = PAD_ID(PE, 16), - MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17), - MX27_PAD_SD1_D0 = PAD_ID(PE, 18), - MX27_PAD_SD1_D1 = PAD_ID(PE, 19), - MX27_PAD_SD1_D2 = PAD_ID(PE, 20), - MX27_PAD_SD1_D3 = PAD_ID(PE, 21), - MX27_PAD_SD1_CMD = PAD_ID(PE, 22), - MX27_PAD_SD1_CLK = PAD_ID(PE, 23), - MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), - MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), - - MX27_PAD_NFRB = PAD_ID(PF, 0), - MX27_PAD_NFCLE = PAD_ID(PF, 1), - MX27_PAD_NFWP_B = PAD_ID(PF, 2), - MX27_PAD_NFCE_B = PAD_ID(PF, 3), - MX27_PAD_NFALE = PAD_ID(PF, 4), - MX27_PAD_NFRE_B = PAD_ID(PF, 5), - MX27_PAD_NFWE_B = PAD_ID(PF, 6), - MX27_PAD_PC_POE = PAD_ID(PF, 7), - MX27_PAD_PC_RW_B = PAD_ID(PF, 8), - MX27_PAD_IOIS16 = PAD_ID(PF, 9), - MX27_PAD_PC_RST = PAD_ID(PF, 10), - MX27_PAD_PC_BVD2 = PAD_ID(PF, 11), - MX27_PAD_PC_BVD1 = PAD_ID(PF, 12), - MX27_PAD_PC_VS2 = PAD_ID(PF, 13), - MX27_PAD_PC_VS1 = PAD_ID(PF, 14), - MX27_PAD_CLKO = PAD_ID(PF, 15), - MX27_PAD_PC_PWRON = PAD_ID(PF, 16), - MX27_PAD_PC_READY = PAD_ID(PF, 17), - MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18), - MX27_PAD_PC_CD2_B = PAD_ID(PF, 19), - MX27_PAD_PC_CD1_B = PAD_ID(PF, 20), - MX27_PAD_CS4_B = PAD_ID(PF, 21), - MX27_PAD_CS5_B = PAD_ID(PF, 22), - MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK), - IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR), - IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7), - IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT), - IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP), - IMX_PINCTRL_PIN(MX27_PAD_LSCLK), - IMX_PINCTRL_PIN(MX27_PAD_LD0), - IMX_PINCTRL_PIN(MX27_PAD_LD1), - IMX_PINCTRL_PIN(MX27_PAD_LD2), - IMX_PINCTRL_PIN(MX27_PAD_LD3), - IMX_PINCTRL_PIN(MX27_PAD_LD4), - IMX_PINCTRL_PIN(MX27_PAD_LD5), - IMX_PINCTRL_PIN(MX27_PAD_LD6), - IMX_PINCTRL_PIN(MX27_PAD_LD7), - IMX_PINCTRL_PIN(MX27_PAD_LD8), - IMX_PINCTRL_PIN(MX27_PAD_LD9), - IMX_PINCTRL_PIN(MX27_PAD_LD10), - IMX_PINCTRL_PIN(MX27_PAD_LD11), - IMX_PINCTRL_PIN(MX27_PAD_LD12), - IMX_PINCTRL_PIN(MX27_PAD_LD13), - IMX_PINCTRL_PIN(MX27_PAD_LD14), - IMX_PINCTRL_PIN(MX27_PAD_LD15), - IMX_PINCTRL_PIN(MX27_PAD_LD16), - IMX_PINCTRL_PIN(MX27_PAD_LD17), - IMX_PINCTRL_PIN(MX27_PAD_REV), - IMX_PINCTRL_PIN(MX27_PAD_CLS), - IMX_PINCTRL_PIN(MX27_PAD_PS), - IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR), - IMX_PINCTRL_PIN(MX27_PAD_HSYNC), - IMX_PINCTRL_PIN(MX27_PAD_VSYNC), - IMX_PINCTRL_PIN(MX27_PAD_CONTRAST), - IMX_PINCTRL_PIN(MX27_PAD_OE_ACD), - - IMX_PINCTRL_PIN(MX27_PAD_SD2_D0), - IMX_PINCTRL_PIN(MX27_PAD_SD2_D1), - IMX_PINCTRL_PIN(MX27_PAD_SD2_D2), - IMX_PINCTRL_PIN(MX27_PAD_SD2_D3), - IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX27_PAD_CSI_D0), - IMX_PINCTRL_PIN(MX27_PAD_CSI_D1), - IMX_PINCTRL_PIN(MX27_PAD_CSI_D2), - IMX_PINCTRL_PIN(MX27_PAD_CSI_D3), - IMX_PINCTRL_PIN(MX27_PAD_CSI_D4), - IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK), - IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK), - IMX_PINCTRL_PIN(MX27_PAD_CSI_D5), - IMX_PINCTRL_PIN(MX27_PAD_CSI_D6), - IMX_PINCTRL_PIN(MX27_PAD_CSI_D7), - IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC), - IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC), - IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP), - IMX_PINCTRL_PIN(MX27_PAD_USB_PWR), - IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B), - IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV), - IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS), - IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B), - IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM), - IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP), - IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM), - IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP), - - IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA), - IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3), - IMX_PINCTRL_PIN(MX27_PAD_TOUT), - IMX_PINCTRL_PIN(MX27_PAD_TIN), - IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS), - IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT), - IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT), - IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK), - IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS), - IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT), - IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT), - IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK), - IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS), - IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT), - IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT), - IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK), - IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS), - IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT), - IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT), - IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK), - - IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD), - IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14), - IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA), - IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK), - IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2), - IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1), - IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0), - IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK), - IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO), - IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI), - IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY), - IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2), - IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1), - IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0), - IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK), - IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO), - IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI), - - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR), - IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS), - IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS), - IMX_PINCTRL_PIN(MX27_PAD_PWMO), - IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD), - IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD), - IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD), - IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD), - IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS), - IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS), - IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD), - IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD), - IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS), - IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS), - IMX_PINCTRL_PIN(MX27_PAD_RTCK), - IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B), - IMX_PINCTRL_PIN(MX27_PAD_SD1_D0), - IMX_PINCTRL_PIN(MX27_PAD_SD1_D1), - IMX_PINCTRL_PIN(MX27_PAD_SD1_D2), - IMX_PINCTRL_PIN(MX27_PAD_SD1_D3), - IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK), - IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7), - - IMX_PINCTRL_PIN(MX27_PAD_NFRB), - IMX_PINCTRL_PIN(MX27_PAD_NFCLE), - IMX_PINCTRL_PIN(MX27_PAD_NFWP_B), - IMX_PINCTRL_PIN(MX27_PAD_NFCE_B), - IMX_PINCTRL_PIN(MX27_PAD_NFALE), - IMX_PINCTRL_PIN(MX27_PAD_NFRE_B), - IMX_PINCTRL_PIN(MX27_PAD_NFWE_B), - IMX_PINCTRL_PIN(MX27_PAD_PC_POE), - IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B), - IMX_PINCTRL_PIN(MX27_PAD_IOIS16), - IMX_PINCTRL_PIN(MX27_PAD_PC_RST), - IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2), - IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1), - IMX_PINCTRL_PIN(MX27_PAD_PC_VS2), - IMX_PINCTRL_PIN(MX27_PAD_PC_VS1), - IMX_PINCTRL_PIN(MX27_PAD_CLKO), - IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON), - IMX_PINCTRL_PIN(MX27_PAD_PC_READY), - IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B), - IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B), - IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B), - IMX_PINCTRL_PIN(MX27_PAD_CS4_B), - IMX_PINCTRL_PIN(MX27_PAD_CS5_B), - IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15), -}; - -static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { - .pins = imx27_pinctrl_pads, - .npins = ARRAY_SIZE(imx27_pinctrl_pads), -}; - -static const struct of_device_id imx27_pinctrl_of_match[] = { - { .compatible = "fsl,imx27-iomuxc", }, - { /* sentinel */ } -}; - -static int imx27_pinctrl_probe(struct platform_device *pdev) -{ - return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info); -} - -static struct platform_driver imx27_pinctrl_driver = { - .driver = { - .name = "imx27-pinctrl", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx27_pinctrl_of_match), - }, - .probe = imx27_pinctrl_probe, - .remove = imx1_pinctrl_core_remove, -}; - -static int __init imx27_pinctrl_init(void) -{ - return platform_driver_register(&imx27_pinctrl_driver); -} -arch_initcall(imx27_pinctrl_init); - -static void __exit imx27_pinctrl_exit(void) -{ - platform_driver_unregister(&imx27_pinctrl_driver); -} -module_exit(imx27_pinctrl_exit); -MODULE_AUTHOR("Markus Pargmann "); -MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c deleted file mode 100644 index 3bd45da21229..000000000000 --- a/drivers/pinctrl/pinctrl-imx28.c +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include "pinctrl-mxs.h" - -enum imx28_pin_enum { - GPMI_D00 = PINID(0, 0), - GPMI_D01 = PINID(0, 1), - GPMI_D02 = PINID(0, 2), - GPMI_D03 = PINID(0, 3), - GPMI_D04 = PINID(0, 4), - GPMI_D05 = PINID(0, 5), - GPMI_D06 = PINID(0, 6), - GPMI_D07 = PINID(0, 7), - GPMI_CE0N = PINID(0, 16), - GPMI_CE1N = PINID(0, 17), - GPMI_CE2N = PINID(0, 18), - GPMI_CE3N = PINID(0, 19), - GPMI_RDY0 = PINID(0, 20), - GPMI_RDY1 = PINID(0, 21), - GPMI_RDY2 = PINID(0, 22), - GPMI_RDY3 = PINID(0, 23), - GPMI_RDN = PINID(0, 24), - GPMI_WRN = PINID(0, 25), - GPMI_ALE = PINID(0, 26), - GPMI_CLE = PINID(0, 27), - GPMI_RESETN = PINID(0, 28), - LCD_D00 = PINID(1, 0), - LCD_D01 = PINID(1, 1), - LCD_D02 = PINID(1, 2), - LCD_D03 = PINID(1, 3), - LCD_D04 = PINID(1, 4), - LCD_D05 = PINID(1, 5), - LCD_D06 = PINID(1, 6), - LCD_D07 = PINID(1, 7), - LCD_D08 = PINID(1, 8), - LCD_D09 = PINID(1, 9), - LCD_D10 = PINID(1, 10), - LCD_D11 = PINID(1, 11), - LCD_D12 = PINID(1, 12), - LCD_D13 = PINID(1, 13), - LCD_D14 = PINID(1, 14), - LCD_D15 = PINID(1, 15), - LCD_D16 = PINID(1, 16), - LCD_D17 = PINID(1, 17), - LCD_D18 = PINID(1, 18), - LCD_D19 = PINID(1, 19), - LCD_D20 = PINID(1, 20), - LCD_D21 = PINID(1, 21), - LCD_D22 = PINID(1, 22), - LCD_D23 = PINID(1, 23), - LCD_RD_E = PINID(1, 24), - LCD_WR_RWN = PINID(1, 25), - LCD_RS = PINID(1, 26), - LCD_CS = PINID(1, 27), - LCD_VSYNC = PINID(1, 28), - LCD_HSYNC = PINID(1, 29), - LCD_DOTCLK = PINID(1, 30), - LCD_ENABLE = PINID(1, 31), - SSP0_DATA0 = PINID(2, 0), - SSP0_DATA1 = PINID(2, 1), - SSP0_DATA2 = PINID(2, 2), - SSP0_DATA3 = PINID(2, 3), - SSP0_DATA4 = PINID(2, 4), - SSP0_DATA5 = PINID(2, 5), - SSP0_DATA6 = PINID(2, 6), - SSP0_DATA7 = PINID(2, 7), - SSP0_CMD = PINID(2, 8), - SSP0_DETECT = PINID(2, 9), - SSP0_SCK = PINID(2, 10), - SSP1_SCK = PINID(2, 12), - SSP1_CMD = PINID(2, 13), - SSP1_DATA0 = PINID(2, 14), - SSP1_DATA3 = PINID(2, 15), - SSP2_SCK = PINID(2, 16), - SSP2_MOSI = PINID(2, 17), - SSP2_MISO = PINID(2, 18), - SSP2_SS0 = PINID(2, 19), - SSP2_SS1 = PINID(2, 20), - SSP2_SS2 = PINID(2, 21), - SSP3_SCK = PINID(2, 24), - SSP3_MOSI = PINID(2, 25), - SSP3_MISO = PINID(2, 26), - SSP3_SS0 = PINID(2, 27), - AUART0_RX = PINID(3, 0), - AUART0_TX = PINID(3, 1), - AUART0_CTS = PINID(3, 2), - AUART0_RTS = PINID(3, 3), - AUART1_RX = PINID(3, 4), - AUART1_TX = PINID(3, 5), - AUART1_CTS = PINID(3, 6), - AUART1_RTS = PINID(3, 7), - AUART2_RX = PINID(3, 8), - AUART2_TX = PINID(3, 9), - AUART2_CTS = PINID(3, 10), - AUART2_RTS = PINID(3, 11), - AUART3_RX = PINID(3, 12), - AUART3_TX = PINID(3, 13), - AUART3_CTS = PINID(3, 14), - AUART3_RTS = PINID(3, 15), - PWM0 = PINID(3, 16), - PWM1 = PINID(3, 17), - PWM2 = PINID(3, 18), - SAIF0_MCLK = PINID(3, 20), - SAIF0_LRCLK = PINID(3, 21), - SAIF0_BITCLK = PINID(3, 22), - SAIF0_SDATA0 = PINID(3, 23), - I2C0_SCL = PINID(3, 24), - I2C0_SDA = PINID(3, 25), - SAIF1_SDATA0 = PINID(3, 26), - SPDIF = PINID(3, 27), - PWM3 = PINID(3, 28), - PWM4 = PINID(3, 29), - LCD_RESET = PINID(3, 30), - ENET0_MDC = PINID(4, 0), - ENET0_MDIO = PINID(4, 1), - ENET0_RX_EN = PINID(4, 2), - ENET0_RXD0 = PINID(4, 3), - ENET0_RXD1 = PINID(4, 4), - ENET0_TX_CLK = PINID(4, 5), - ENET0_TX_EN = PINID(4, 6), - ENET0_TXD0 = PINID(4, 7), - ENET0_TXD1 = PINID(4, 8), - ENET0_RXD2 = PINID(4, 9), - ENET0_RXD3 = PINID(4, 10), - ENET0_TXD2 = PINID(4, 11), - ENET0_TXD3 = PINID(4, 12), - ENET0_RX_CLK = PINID(4, 13), - ENET0_COL = PINID(4, 14), - ENET0_CRS = PINID(4, 15), - ENET_CLK = PINID(4, 16), - JTAG_RTCK = PINID(4, 20), - EMI_D00 = PINID(5, 0), - EMI_D01 = PINID(5, 1), - EMI_D02 = PINID(5, 2), - EMI_D03 = PINID(5, 3), - EMI_D04 = PINID(5, 4), - EMI_D05 = PINID(5, 5), - EMI_D06 = PINID(5, 6), - EMI_D07 = PINID(5, 7), - EMI_D08 = PINID(5, 8), - EMI_D09 = PINID(5, 9), - EMI_D10 = PINID(5, 10), - EMI_D11 = PINID(5, 11), - EMI_D12 = PINID(5, 12), - EMI_D13 = PINID(5, 13), - EMI_D14 = PINID(5, 14), - EMI_D15 = PINID(5, 15), - EMI_ODT0 = PINID(5, 16), - EMI_DQM0 = PINID(5, 17), - EMI_ODT1 = PINID(5, 18), - EMI_DQM1 = PINID(5, 19), - EMI_DDR_OPEN_FB = PINID(5, 20), - EMI_CLK = PINID(5, 21), - EMI_DQS0 = PINID(5, 22), - EMI_DQS1 = PINID(5, 23), - EMI_DDR_OPEN = PINID(5, 26), - EMI_A00 = PINID(6, 0), - EMI_A01 = PINID(6, 1), - EMI_A02 = PINID(6, 2), - EMI_A03 = PINID(6, 3), - EMI_A04 = PINID(6, 4), - EMI_A05 = PINID(6, 5), - EMI_A06 = PINID(6, 6), - EMI_A07 = PINID(6, 7), - EMI_A08 = PINID(6, 8), - EMI_A09 = PINID(6, 9), - EMI_A10 = PINID(6, 10), - EMI_A11 = PINID(6, 11), - EMI_A12 = PINID(6, 12), - EMI_A13 = PINID(6, 13), - EMI_A14 = PINID(6, 14), - EMI_BA0 = PINID(6, 16), - EMI_BA1 = PINID(6, 17), - EMI_BA2 = PINID(6, 18), - EMI_CASN = PINID(6, 19), - EMI_RASN = PINID(6, 20), - EMI_WEN = PINID(6, 21), - EMI_CE0N = PINID(6, 22), - EMI_CE1N = PINID(6, 23), - EMI_CKE = PINID(6, 24), -}; - -static const struct pinctrl_pin_desc imx28_pins[] = { - MXS_PINCTRL_PIN(GPMI_D00), - MXS_PINCTRL_PIN(GPMI_D01), - MXS_PINCTRL_PIN(GPMI_D02), - MXS_PINCTRL_PIN(GPMI_D03), - MXS_PINCTRL_PIN(GPMI_D04), - MXS_PINCTRL_PIN(GPMI_D05), - MXS_PINCTRL_PIN(GPMI_D06), - MXS_PINCTRL_PIN(GPMI_D07), - MXS_PINCTRL_PIN(GPMI_CE0N), - MXS_PINCTRL_PIN(GPMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE2N), - MXS_PINCTRL_PIN(GPMI_CE3N), - MXS_PINCTRL_PIN(GPMI_RDY0), - MXS_PINCTRL_PIN(GPMI_RDY1), - MXS_PINCTRL_PIN(GPMI_RDY2), - MXS_PINCTRL_PIN(GPMI_RDY3), - MXS_PINCTRL_PIN(GPMI_RDN), - MXS_PINCTRL_PIN(GPMI_WRN), - MXS_PINCTRL_PIN(GPMI_ALE), - MXS_PINCTRL_PIN(GPMI_CLE), - MXS_PINCTRL_PIN(GPMI_RESETN), - MXS_PINCTRL_PIN(LCD_D00), - MXS_PINCTRL_PIN(LCD_D01), - MXS_PINCTRL_PIN(LCD_D02), - MXS_PINCTRL_PIN(LCD_D03), - MXS_PINCTRL_PIN(LCD_D04), - MXS_PINCTRL_PIN(LCD_D05), - MXS_PINCTRL_PIN(LCD_D06), - MXS_PINCTRL_PIN(LCD_D07), - MXS_PINCTRL_PIN(LCD_D08), - MXS_PINCTRL_PIN(LCD_D09), - MXS_PINCTRL_PIN(LCD_D10), - MXS_PINCTRL_PIN(LCD_D11), - MXS_PINCTRL_PIN(LCD_D12), - MXS_PINCTRL_PIN(LCD_D13), - MXS_PINCTRL_PIN(LCD_D14), - MXS_PINCTRL_PIN(LCD_D15), - MXS_PINCTRL_PIN(LCD_D16), - MXS_PINCTRL_PIN(LCD_D17), - MXS_PINCTRL_PIN(LCD_D18), - MXS_PINCTRL_PIN(LCD_D19), - MXS_PINCTRL_PIN(LCD_D20), - MXS_PINCTRL_PIN(LCD_D21), - MXS_PINCTRL_PIN(LCD_D22), - MXS_PINCTRL_PIN(LCD_D23), - MXS_PINCTRL_PIN(LCD_RD_E), - MXS_PINCTRL_PIN(LCD_WR_RWN), - MXS_PINCTRL_PIN(LCD_RS), - MXS_PINCTRL_PIN(LCD_CS), - MXS_PINCTRL_PIN(LCD_VSYNC), - MXS_PINCTRL_PIN(LCD_HSYNC), - MXS_PINCTRL_PIN(LCD_DOTCLK), - MXS_PINCTRL_PIN(LCD_ENABLE), - MXS_PINCTRL_PIN(SSP0_DATA0), - MXS_PINCTRL_PIN(SSP0_DATA1), - MXS_PINCTRL_PIN(SSP0_DATA2), - MXS_PINCTRL_PIN(SSP0_DATA3), - MXS_PINCTRL_PIN(SSP0_DATA4), - MXS_PINCTRL_PIN(SSP0_DATA5), - MXS_PINCTRL_PIN(SSP0_DATA6), - MXS_PINCTRL_PIN(SSP0_DATA7), - MXS_PINCTRL_PIN(SSP0_CMD), - MXS_PINCTRL_PIN(SSP0_DETECT), - MXS_PINCTRL_PIN(SSP0_SCK), - MXS_PINCTRL_PIN(SSP1_SCK), - MXS_PINCTRL_PIN(SSP1_CMD), - MXS_PINCTRL_PIN(SSP1_DATA0), - MXS_PINCTRL_PIN(SSP1_DATA3), - MXS_PINCTRL_PIN(SSP2_SCK), - MXS_PINCTRL_PIN(SSP2_MOSI), - MXS_PINCTRL_PIN(SSP2_MISO), - MXS_PINCTRL_PIN(SSP2_SS0), - MXS_PINCTRL_PIN(SSP2_SS1), - MXS_PINCTRL_PIN(SSP2_SS2), - MXS_PINCTRL_PIN(SSP3_SCK), - MXS_PINCTRL_PIN(SSP3_MOSI), - MXS_PINCTRL_PIN(SSP3_MISO), - MXS_PINCTRL_PIN(SSP3_SS0), - MXS_PINCTRL_PIN(AUART0_RX), - MXS_PINCTRL_PIN(AUART0_TX), - MXS_PINCTRL_PIN(AUART0_CTS), - MXS_PINCTRL_PIN(AUART0_RTS), - MXS_PINCTRL_PIN(AUART1_RX), - MXS_PINCTRL_PIN(AUART1_TX), - MXS_PINCTRL_PIN(AUART1_CTS), - MXS_PINCTRL_PIN(AUART1_RTS), - MXS_PINCTRL_PIN(AUART2_RX), - MXS_PINCTRL_PIN(AUART2_TX), - MXS_PINCTRL_PIN(AUART2_CTS), - MXS_PINCTRL_PIN(AUART2_RTS), - MXS_PINCTRL_PIN(AUART3_RX), - MXS_PINCTRL_PIN(AUART3_TX), - MXS_PINCTRL_PIN(AUART3_CTS), - MXS_PINCTRL_PIN(AUART3_RTS), - MXS_PINCTRL_PIN(PWM0), - MXS_PINCTRL_PIN(PWM1), - MXS_PINCTRL_PIN(PWM2), - MXS_PINCTRL_PIN(SAIF0_MCLK), - MXS_PINCTRL_PIN(SAIF0_LRCLK), - MXS_PINCTRL_PIN(SAIF0_BITCLK), - MXS_PINCTRL_PIN(SAIF0_SDATA0), - MXS_PINCTRL_PIN(I2C0_SCL), - MXS_PINCTRL_PIN(I2C0_SDA), - MXS_PINCTRL_PIN(SAIF1_SDATA0), - MXS_PINCTRL_PIN(SPDIF), - MXS_PINCTRL_PIN(PWM3), - MXS_PINCTRL_PIN(PWM4), - MXS_PINCTRL_PIN(LCD_RESET), - MXS_PINCTRL_PIN(ENET0_MDC), - MXS_PINCTRL_PIN(ENET0_MDIO), - MXS_PINCTRL_PIN(ENET0_RX_EN), - MXS_PINCTRL_PIN(ENET0_RXD0), - MXS_PINCTRL_PIN(ENET0_RXD1), - MXS_PINCTRL_PIN(ENET0_TX_CLK), - MXS_PINCTRL_PIN(ENET0_TX_EN), - MXS_PINCTRL_PIN(ENET0_TXD0), - MXS_PINCTRL_PIN(ENET0_TXD1), - MXS_PINCTRL_PIN(ENET0_RXD2), - MXS_PINCTRL_PIN(ENET0_RXD3), - MXS_PINCTRL_PIN(ENET0_TXD2), - MXS_PINCTRL_PIN(ENET0_TXD3), - MXS_PINCTRL_PIN(ENET0_RX_CLK), - MXS_PINCTRL_PIN(ENET0_COL), - MXS_PINCTRL_PIN(ENET0_CRS), - MXS_PINCTRL_PIN(ENET_CLK), - MXS_PINCTRL_PIN(JTAG_RTCK), - MXS_PINCTRL_PIN(EMI_D00), - MXS_PINCTRL_PIN(EMI_D01), - MXS_PINCTRL_PIN(EMI_D02), - MXS_PINCTRL_PIN(EMI_D03), - MXS_PINCTRL_PIN(EMI_D04), - MXS_PINCTRL_PIN(EMI_D05), - MXS_PINCTRL_PIN(EMI_D06), - MXS_PINCTRL_PIN(EMI_D07), - MXS_PINCTRL_PIN(EMI_D08), - MXS_PINCTRL_PIN(EMI_D09), - MXS_PINCTRL_PIN(EMI_D10), - MXS_PINCTRL_PIN(EMI_D11), - MXS_PINCTRL_PIN(EMI_D12), - MXS_PINCTRL_PIN(EMI_D13), - MXS_PINCTRL_PIN(EMI_D14), - MXS_PINCTRL_PIN(EMI_D15), - MXS_PINCTRL_PIN(EMI_ODT0), - MXS_PINCTRL_PIN(EMI_DQM0), - MXS_PINCTRL_PIN(EMI_ODT1), - MXS_PINCTRL_PIN(EMI_DQM1), - MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB), - MXS_PINCTRL_PIN(EMI_CLK), - MXS_PINCTRL_PIN(EMI_DQS0), - MXS_PINCTRL_PIN(EMI_DQS1), - MXS_PINCTRL_PIN(EMI_DDR_OPEN), - MXS_PINCTRL_PIN(EMI_A00), - MXS_PINCTRL_PIN(EMI_A01), - MXS_PINCTRL_PIN(EMI_A02), - MXS_PINCTRL_PIN(EMI_A03), - MXS_PINCTRL_PIN(EMI_A04), - MXS_PINCTRL_PIN(EMI_A05), - MXS_PINCTRL_PIN(EMI_A06), - MXS_PINCTRL_PIN(EMI_A07), - MXS_PINCTRL_PIN(EMI_A08), - MXS_PINCTRL_PIN(EMI_A09), - MXS_PINCTRL_PIN(EMI_A10), - MXS_PINCTRL_PIN(EMI_A11), - MXS_PINCTRL_PIN(EMI_A12), - MXS_PINCTRL_PIN(EMI_A13), - MXS_PINCTRL_PIN(EMI_A14), - MXS_PINCTRL_PIN(EMI_BA0), - MXS_PINCTRL_PIN(EMI_BA1), - MXS_PINCTRL_PIN(EMI_BA2), - MXS_PINCTRL_PIN(EMI_CASN), - MXS_PINCTRL_PIN(EMI_RASN), - MXS_PINCTRL_PIN(EMI_WEN), - MXS_PINCTRL_PIN(EMI_CE0N), - MXS_PINCTRL_PIN(EMI_CE1N), - MXS_PINCTRL_PIN(EMI_CKE), -}; - -static struct mxs_regs imx28_regs = { - .muxsel = 0x100, - .drive = 0x300, - .pull = 0x600, -}; - -static struct mxs_pinctrl_soc_data imx28_pinctrl_data = { - .regs = &imx28_regs, - .pins = imx28_pins, - .npins = ARRAY_SIZE(imx28_pins), -}; - -static int imx28_pinctrl_probe(struct platform_device *pdev) -{ - return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data); -} - -static const struct of_device_id imx28_pinctrl_of_match[] = { - { .compatible = "fsl,imx28-pinctrl", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match); - -static struct platform_driver imx28_pinctrl_driver = { - .driver = { - .name = "imx28-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx28_pinctrl_of_match, - }, - .probe = imx28_pinctrl_probe, - .remove = mxs_pinctrl_remove, -}; - -static int __init imx28_pinctrl_init(void) -{ - return platform_driver_register(&imx28_pinctrl_driver); -} -postcore_initcall(imx28_pinctrl_init); - -static void __exit imx28_pinctrl_exit(void) -{ - platform_driver_unregister(&imx28_pinctrl_driver); -} -module_exit(imx28_pinctrl_exit); - -MODULE_AUTHOR("Shawn Guo "); -MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c deleted file mode 100644 index 6bfbcd0112c1..000000000000 --- a/drivers/pinctrl/pinctrl-imx35.c +++ /dev/null @@ -1,1041 +0,0 @@ -/* - * imx35 pinctrl driver. - * - * This driver was mostly copied from the imx51 pinctrl driver which has: - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro, Inc. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx35_pads { - MX35_PAD_RESERVE0 = 0, - MX35_PAD_CAPTURE = 1, - MX35_PAD_COMPARE = 2, - MX35_PAD_WDOG_RST = 3, - MX35_PAD_GPIO1_0 = 4, - MX35_PAD_GPIO1_1 = 5, - MX35_PAD_GPIO2_0 = 6, - MX35_PAD_GPIO3_0 = 7, - MX35_PAD_CLKO = 8, - MX35_PAD_VSTBY = 9, - MX35_PAD_A0 = 10, - MX35_PAD_A1 = 11, - MX35_PAD_A2 = 12, - MX35_PAD_A3 = 13, - MX35_PAD_A4 = 14, - MX35_PAD_A5 = 15, - MX35_PAD_A6 = 16, - MX35_PAD_A7 = 17, - MX35_PAD_A8 = 18, - MX35_PAD_A9 = 19, - MX35_PAD_A10 = 20, - MX35_PAD_MA10 = 21, - MX35_PAD_A11 = 22, - MX35_PAD_A12 = 23, - MX35_PAD_A13 = 24, - MX35_PAD_A14 = 25, - MX35_PAD_A15 = 26, - MX35_PAD_A16 = 27, - MX35_PAD_A17 = 28, - MX35_PAD_A18 = 29, - MX35_PAD_A19 = 30, - MX35_PAD_A20 = 31, - MX35_PAD_A21 = 32, - MX35_PAD_A22 = 33, - MX35_PAD_A23 = 34, - MX35_PAD_A24 = 35, - MX35_PAD_A25 = 36, - MX35_PAD_EB0 = 37, - MX35_PAD_EB1 = 38, - MX35_PAD_OE = 39, - MX35_PAD_CS0 = 40, - MX35_PAD_CS1 = 41, - MX35_PAD_CS2 = 42, - MX35_PAD_CS3 = 43, - MX35_PAD_CS4 = 44, - MX35_PAD_CS5 = 45, - MX35_PAD_NF_CE0 = 46, - MX35_PAD_LBA = 47, - MX35_PAD_BCLK = 48, - MX35_PAD_RW = 49, - MX35_PAD_NFWE_B = 50, - MX35_PAD_NFRE_B = 51, - MX35_PAD_NFALE = 52, - MX35_PAD_NFCLE = 53, - MX35_PAD_NFWP_B = 54, - MX35_PAD_NFRB = 55, - MX35_PAD_CSI_D8 = 56, - MX35_PAD_CSI_D9 = 57, - MX35_PAD_CSI_D10 = 58, - MX35_PAD_CSI_D11 = 59, - MX35_PAD_CSI_D12 = 60, - MX35_PAD_CSI_D13 = 61, - MX35_PAD_CSI_D14 = 62, - MX35_PAD_CSI_D15 = 63, - MX35_PAD_CSI_MCLK = 64, - MX35_PAD_CSI_VSYNC = 65, - MX35_PAD_CSI_HSYNC = 66, - MX35_PAD_CSI_PIXCLK = 67, - MX35_PAD_I2C1_CLK = 68, - MX35_PAD_I2C1_DAT = 69, - MX35_PAD_I2C2_CLK = 70, - MX35_PAD_I2C2_DAT = 71, - MX35_PAD_STXD4 = 72, - MX35_PAD_SRXD4 = 73, - MX35_PAD_SCK4 = 74, - MX35_PAD_STXFS4 = 75, - MX35_PAD_STXD5 = 76, - MX35_PAD_SRXD5 = 77, - MX35_PAD_SCK5 = 78, - MX35_PAD_STXFS5 = 79, - MX35_PAD_SCKR = 80, - MX35_PAD_FSR = 81, - MX35_PAD_HCKR = 82, - MX35_PAD_SCKT = 83, - MX35_PAD_FST = 84, - MX35_PAD_HCKT = 85, - MX35_PAD_TX5_RX0 = 86, - MX35_PAD_TX4_RX1 = 87, - MX35_PAD_TX3_RX2 = 88, - MX35_PAD_TX2_RX3 = 89, - MX35_PAD_TX1 = 90, - MX35_PAD_TX0 = 91, - MX35_PAD_CSPI1_MOSI = 92, - MX35_PAD_CSPI1_MISO = 93, - MX35_PAD_CSPI1_SS0 = 94, - MX35_PAD_CSPI1_SS1 = 95, - MX35_PAD_CSPI1_SCLK = 96, - MX35_PAD_CSPI1_SPI_RDY = 97, - MX35_PAD_RXD1 = 98, - MX35_PAD_TXD1 = 99, - MX35_PAD_RTS1 = 100, - MX35_PAD_CTS1 = 101, - MX35_PAD_RXD2 = 102, - MX35_PAD_TXD2 = 103, - MX35_PAD_RTS2 = 104, - MX35_PAD_CTS2 = 105, - MX35_PAD_USBOTG_PWR = 106, - MX35_PAD_USBOTG_OC = 107, - MX35_PAD_LD0 = 108, - MX35_PAD_LD1 = 109, - MX35_PAD_LD2 = 110, - MX35_PAD_LD3 = 111, - MX35_PAD_LD4 = 112, - MX35_PAD_LD5 = 113, - MX35_PAD_LD6 = 114, - MX35_PAD_LD7 = 115, - MX35_PAD_LD8 = 116, - MX35_PAD_LD9 = 117, - MX35_PAD_LD10 = 118, - MX35_PAD_LD11 = 119, - MX35_PAD_LD12 = 120, - MX35_PAD_LD13 = 121, - MX35_PAD_LD14 = 122, - MX35_PAD_LD15 = 123, - MX35_PAD_LD16 = 124, - MX35_PAD_LD17 = 125, - MX35_PAD_LD18 = 126, - MX35_PAD_LD19 = 127, - MX35_PAD_LD20 = 128, - MX35_PAD_LD21 = 129, - MX35_PAD_LD22 = 130, - MX35_PAD_LD23 = 131, - MX35_PAD_D3_HSYNC = 132, - MX35_PAD_D3_FPSHIFT = 133, - MX35_PAD_D3_DRDY = 134, - MX35_PAD_CONTRAST = 135, - MX35_PAD_D3_VSYNC = 136, - MX35_PAD_D3_REV = 137, - MX35_PAD_D3_CLS = 138, - MX35_PAD_D3_SPL = 139, - MX35_PAD_SD1_CMD = 140, - MX35_PAD_SD1_CLK = 141, - MX35_PAD_SD1_DATA0 = 142, - MX35_PAD_SD1_DATA1 = 143, - MX35_PAD_SD1_DATA2 = 144, - MX35_PAD_SD1_DATA3 = 145, - MX35_PAD_SD2_CMD = 146, - MX35_PAD_SD2_CLK = 147, - MX35_PAD_SD2_DATA0 = 148, - MX35_PAD_SD2_DATA1 = 149, - MX35_PAD_SD2_DATA2 = 150, - MX35_PAD_SD2_DATA3 = 151, - MX35_PAD_ATA_CS0 = 152, - MX35_PAD_ATA_CS1 = 153, - MX35_PAD_ATA_DIOR = 154, - MX35_PAD_ATA_DIOW = 155, - MX35_PAD_ATA_DMACK = 156, - MX35_PAD_ATA_RESET_B = 157, - MX35_PAD_ATA_IORDY = 158, - MX35_PAD_ATA_DATA0 = 159, - MX35_PAD_ATA_DATA1 = 160, - MX35_PAD_ATA_DATA2 = 161, - MX35_PAD_ATA_DATA3 = 162, - MX35_PAD_ATA_DATA4 = 163, - MX35_PAD_ATA_DATA5 = 164, - MX35_PAD_ATA_DATA6 = 165, - MX35_PAD_ATA_DATA7 = 166, - MX35_PAD_ATA_DATA8 = 167, - MX35_PAD_ATA_DATA9 = 168, - MX35_PAD_ATA_DATA10 = 169, - MX35_PAD_ATA_DATA11 = 170, - MX35_PAD_ATA_DATA12 = 171, - MX35_PAD_ATA_DATA13 = 172, - MX35_PAD_ATA_DATA14 = 173, - MX35_PAD_ATA_DATA15 = 174, - MX35_PAD_ATA_INTRQ = 175, - MX35_PAD_ATA_BUFF_EN = 176, - MX35_PAD_ATA_DMARQ = 177, - MX35_PAD_ATA_DA0 = 178, - MX35_PAD_ATA_DA1 = 179, - MX35_PAD_ATA_DA2 = 180, - MX35_PAD_MLB_CLK = 181, - MX35_PAD_MLB_DAT = 182, - MX35_PAD_MLB_SIG = 183, - MX35_PAD_FEC_TX_CLK = 184, - MX35_PAD_FEC_RX_CLK = 185, - MX35_PAD_FEC_RX_DV = 186, - MX35_PAD_FEC_COL = 187, - MX35_PAD_FEC_RDATA0 = 188, - MX35_PAD_FEC_TDATA0 = 189, - MX35_PAD_FEC_TX_EN = 190, - MX35_PAD_FEC_MDC = 191, - MX35_PAD_FEC_MDIO = 192, - MX35_PAD_FEC_TX_ERR = 193, - MX35_PAD_FEC_RX_ERR = 194, - MX35_PAD_FEC_CRS = 195, - MX35_PAD_FEC_RDATA1 = 196, - MX35_PAD_FEC_TDATA1 = 197, - MX35_PAD_FEC_RDATA2 = 198, - MX35_PAD_FEC_TDATA2 = 199, - MX35_PAD_FEC_RDATA3 = 200, - MX35_PAD_FEC_TDATA3 = 201, - MX35_PAD_RESERVE1 = 202, - MX35_PAD_RESERVE2 = 203, - MX35_PAD_RESERVE3 = 204, - MX35_PAD_RESERVE4 = 205, - MX35_PAD_RESERVE5 = 206, - MX35_PAD_RESERVE6 = 207, - MX35_PAD_RESERVE7 = 208, - MX35_PAD_RESET_IN_B = 209, - MX35_PAD_POR_B = 210, - MX35_PAD_RESERVE8 = 211, - MX35_PAD_BOOT_MODE0 = 212, - MX35_PAD_BOOT_MODE1 = 213, - MX35_PAD_CLK_MODE0 = 214, - MX35_PAD_CLK_MODE1 = 215, - MX35_PAD_POWER_FAIL = 216, - MX35_PAD_RESERVE9 = 217, - MX35_PAD_RESERVE10 = 218, - MX35_PAD_RESERVE11 = 219, - MX35_PAD_RESERVE12 = 220, - MX35_PAD_RESERVE13 = 221, - MX35_PAD_RESERVE14 = 222, - MX35_PAD_RESERVE15 = 223, - MX35_PAD_RESERVE16 = 224, - MX35_PAD_RESERVE17 = 225, - MX35_PAD_RESERVE18 = 226, - MX35_PAD_RESERVE19 = 227, - MX35_PAD_RESERVE20 = 228, - MX35_PAD_RESERVE21 = 229, - MX35_PAD_RESERVE22 = 230, - MX35_PAD_RESERVE23 = 231, - MX35_PAD_RESERVE24 = 232, - MX35_PAD_RESERVE25 = 233, - MX35_PAD_RESERVE26 = 234, - MX35_PAD_RESERVE27 = 235, - MX35_PAD_RESERVE28 = 236, - MX35_PAD_RESERVE29 = 237, - MX35_PAD_RESERVE30 = 238, - MX35_PAD_RESERVE31 = 239, - MX35_PAD_RESERVE32 = 240, - MX35_PAD_RESERVE33 = 241, - MX35_PAD_RESERVE34 = 242, - MX35_PAD_RESERVE35 = 243, - MX35_PAD_RESERVE36 = 244, - MX35_PAD_SDBA1 = 245, - MX35_PAD_SDBA0 = 246, - MX35_PAD_SD0 = 247, - MX35_PAD_SD1 = 248, - MX35_PAD_SD2 = 249, - MX35_PAD_SD3 = 250, - MX35_PAD_SD4 = 251, - MX35_PAD_SD5 = 252, - MX35_PAD_SD6 = 253, - MX35_PAD_SD7 = 254, - MX35_PAD_SD8 = 255, - MX35_PAD_SD9 = 256, - MX35_PAD_SD10 = 257, - MX35_PAD_SD11 = 258, - MX35_PAD_SD12 = 259, - MX35_PAD_SD13 = 260, - MX35_PAD_SD14 = 261, - MX35_PAD_SD15 = 262, - MX35_PAD_SD16 = 263, - MX35_PAD_SD17 = 264, - MX35_PAD_SD18 = 265, - MX35_PAD_SD19 = 266, - MX35_PAD_SD20 = 267, - MX35_PAD_SD21 = 268, - MX35_PAD_SD22 = 269, - MX35_PAD_SD23 = 270, - MX35_PAD_SD24 = 271, - MX35_PAD_SD25 = 272, - MX35_PAD_SD26 = 273, - MX35_PAD_SD27 = 274, - MX35_PAD_SD28 = 275, - MX35_PAD_SD29 = 276, - MX35_PAD_SD30 = 277, - MX35_PAD_SD31 = 278, - MX35_PAD_DQM0 = 279, - MX35_PAD_DQM1 = 280, - MX35_PAD_DQM2 = 281, - MX35_PAD_DQM3 = 282, - MX35_PAD_RESERVE37 = 283, - MX35_PAD_RESERVE38 = 284, - MX35_PAD_RESERVE39 = 285, - MX35_PAD_RESERVE40 = 286, - MX35_PAD_RESERVE41 = 287, - MX35_PAD_RESERVE42 = 288, - MX35_PAD_RESERVE43 = 289, - MX35_PAD_RESERVE44 = 290, - MX35_PAD_RESERVE45 = 291, - MX35_PAD_RESERVE46 = 292, - MX35_PAD_ECB = 293, - MX35_PAD_RESERVE47 = 294, - MX35_PAD_RESERVE48 = 295, - MX35_PAD_RESERVE49 = 296, - MX35_PAD_RAS = 297, - MX35_PAD_CAS = 298, - MX35_PAD_SDWE = 299, - MX35_PAD_SDCKE0 = 300, - MX35_PAD_SDCKE1 = 301, - MX35_PAD_SDCLK = 302, - MX35_PAD_SDQS0 = 303, - MX35_PAD_SDQS1 = 304, - MX35_PAD_SDQS2 = 305, - MX35_PAD_SDQS3 = 306, - MX35_PAD_RESERVE50 = 307, - MX35_PAD_RESERVE51 = 308, - MX35_PAD_RESERVE52 = 309, - MX35_PAD_RESERVE53 = 310, - MX35_PAD_RESERVE54 = 311, - MX35_PAD_RESERVE55 = 312, - MX35_PAD_D15 = 313, - MX35_PAD_D14 = 314, - MX35_PAD_D13 = 315, - MX35_PAD_D12 = 316, - MX35_PAD_D11 = 317, - MX35_PAD_D10 = 318, - MX35_PAD_D9 = 319, - MX35_PAD_D8 = 320, - MX35_PAD_D7 = 321, - MX35_PAD_D6 = 322, - MX35_PAD_D5 = 323, - MX35_PAD_D4 = 324, - MX35_PAD_D3 = 325, - MX35_PAD_D2 = 326, - MX35_PAD_D1 = 327, - MX35_PAD_D0 = 328, - MX35_PAD_RESERVE56 = 329, - MX35_PAD_RESERVE57 = 330, - MX35_PAD_RESERVE58 = 331, - MX35_PAD_RESERVE59 = 332, - MX35_PAD_RESERVE60 = 333, - MX35_PAD_RESERVE61 = 334, - MX35_PAD_RESERVE62 = 335, - MX35_PAD_RESERVE63 = 336, - MX35_PAD_RESERVE64 = 337, - MX35_PAD_RESERVE65 = 338, - MX35_PAD_RESERVE66 = 339, - MX35_PAD_RESERVE67 = 340, - MX35_PAD_RESERVE68 = 341, - MX35_PAD_RESERVE69 = 342, - MX35_PAD_RESERVE70 = 343, - MX35_PAD_RESERVE71 = 344, - MX35_PAD_RESERVE72 = 345, - MX35_PAD_RESERVE73 = 346, - MX35_PAD_RESERVE74 = 347, - MX35_PAD_RESERVE75 = 348, - MX35_PAD_RESERVE76 = 349, - MX35_PAD_RESERVE77 = 350, - MX35_PAD_RESERVE78 = 351, - MX35_PAD_RESERVE79 = 352, - MX35_PAD_RESERVE80 = 353, - MX35_PAD_RESERVE81 = 354, - MX35_PAD_RESERVE82 = 355, - MX35_PAD_RESERVE83 = 356, - MX35_PAD_RESERVE84 = 357, - MX35_PAD_RESERVE85 = 358, - MX35_PAD_RESERVE86 = 359, - MX35_PAD_RESERVE87 = 360, - MX35_PAD_RESERVE88 = 361, - MX35_PAD_RESERVE89 = 362, - MX35_PAD_RESERVE90 = 363, - MX35_PAD_RESERVE91 = 364, - MX35_PAD_RESERVE92 = 365, - MX35_PAD_RESERVE93 = 366, - MX35_PAD_RESERVE94 = 367, - MX35_PAD_RESERVE95 = 368, - MX35_PAD_RESERVE96 = 369, - MX35_PAD_RESERVE97 = 370, - MX35_PAD_RESERVE98 = 371, - MX35_PAD_RESERVE99 = 372, - MX35_PAD_RESERVE100 = 373, - MX35_PAD_RESERVE101 = 374, - MX35_PAD_RESERVE102 = 375, - MX35_PAD_RESERVE103 = 376, - MX35_PAD_RESERVE104 = 377, - MX35_PAD_RESERVE105 = 378, - MX35_PAD_RTCK = 379, - MX35_PAD_TCK = 380, - MX35_PAD_TMS = 381, - MX35_PAD_TDI = 382, - MX35_PAD_TDO = 383, - MX35_PAD_TRSTB = 384, - MX35_PAD_DE_B = 385, - MX35_PAD_SJC_MOD = 386, - MX35_PAD_RESERVE106 = 387, - MX35_PAD_RESERVE107 = 388, - MX35_PAD_RESERVE108 = 389, - MX35_PAD_RESERVE109 = 390, - MX35_PAD_RESERVE110 = 391, - MX35_PAD_RESERVE111 = 392, - MX35_PAD_RESERVE112 = 393, - MX35_PAD_RESERVE113 = 394, - MX35_PAD_RESERVE114 = 395, - MX35_PAD_RESERVE115 = 396, - MX35_PAD_RESERVE116 = 397, - MX35_PAD_RESERVE117 = 398, - MX35_PAD_RESERVE118 = 399, - MX35_PAD_RESERVE119 = 400, - MX35_PAD_RESERVE120 = 401, - MX35_PAD_RESERVE121 = 402, - MX35_PAD_RESERVE122 = 403, - MX35_PAD_RESERVE123 = 404, - MX35_PAD_RESERVE124 = 405, - MX35_PAD_RESERVE125 = 406, - MX35_PAD_RESERVE126 = 407, - MX35_PAD_RESERVE127 = 408, - MX35_PAD_RESERVE128 = 409, - MX35_PAD_RESERVE129 = 410, - MX35_PAD_RESERVE130 = 411, - MX35_PAD_RESERVE131 = 412, - MX35_PAD_RESERVE132 = 413, - MX35_PAD_RESERVE133 = 414, - MX35_PAD_RESERVE134 = 415, - MX35_PAD_RESERVE135 = 416, - MX35_PAD_RESERVE136 = 417, - MX35_PAD_RESERVE137 = 418, - MX35_PAD_RESERVE138 = 419, - MX35_PAD_RESERVE139 = 420, - MX35_PAD_RESERVE140 = 421, - MX35_PAD_RESERVE141 = 422, - MX35_PAD_RESERVE142 = 423, - MX35_PAD_RESERVE143 = 424, - MX35_PAD_RESERVE144 = 425, - MX35_PAD_RESERVE145 = 426, - MX35_PAD_RESERVE146 = 427, - MX35_PAD_RESERVE147 = 428, - MX35_PAD_RESERVE148 = 429, - MX35_PAD_RESERVE149 = 430, - MX35_PAD_RESERVE150 = 431, - MX35_PAD_RESERVE151 = 432, - MX35_PAD_RESERVE152 = 433, - MX35_PAD_RESERVE153 = 434, - MX35_PAD_RESERVE154 = 435, - MX35_PAD_RESERVE155 = 436, - MX35_PAD_RESERVE156 = 437, - MX35_PAD_RESERVE157 = 438, - MX35_PAD_RESERVE158 = 439, - MX35_PAD_RESERVE159 = 440, - MX35_PAD_RESERVE160 = 441, - MX35_PAD_RESERVE161 = 442, - MX35_PAD_RESERVE162 = 443, - MX35_PAD_RESERVE163 = 444, - MX35_PAD_RESERVE164 = 445, - MX35_PAD_RESERVE165 = 446, - MX35_PAD_RESERVE166 = 447, - MX35_PAD_RESERVE167 = 448, - MX35_PAD_RESERVE168 = 449, - MX35_PAD_RESERVE169 = 450, - MX35_PAD_RESERVE170 = 451, - MX35_PAD_RESERVE171 = 452, - MX35_PAD_RESERVE172 = 453, - MX35_PAD_RESERVE173 = 454, - MX35_PAD_RESERVE174 = 455, - MX35_PAD_RESERVE175 = 456, - MX35_PAD_RESERVE176 = 457, - MX35_PAD_RESERVE177 = 458, - MX35_PAD_RESERVE178 = 459, - MX35_PAD_RESERVE179 = 460, - MX35_PAD_RESERVE180 = 461, - MX35_PAD_RESERVE181 = 462, - MX35_PAD_RESERVE182 = 463, - MX35_PAD_RESERVE183 = 464, - MX35_PAD_RESERVE184 = 465, - MX35_PAD_RESERVE185 = 466, - MX35_PAD_RESERVE186 = 467, - MX35_PAD_RESERVE187 = 468, - MX35_PAD_RESERVE188 = 469, - MX35_PAD_RESERVE189 = 470, - MX35_PAD_RESERVE190 = 471, - MX35_PAD_RESERVE191 = 472, - MX35_PAD_RESERVE192 = 473, - MX35_PAD_RESERVE193 = 474, - MX35_PAD_RESERVE194 = 475, - MX35_PAD_RESERVE195 = 476, - MX35_PAD_RESERVE196 = 477, - MX35_PAD_RESERVE197 = 478, - MX35_PAD_RESERVE198 = 479, - MX35_PAD_RESERVE199 = 480, - MX35_PAD_RESERVE200 = 481, - MX35_PAD_RESERVE201 = 482, - MX35_PAD_EXT_ARMCLK = 483, - MX35_PAD_TEST_MODE = 484, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX35_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX35_PAD_CAPTURE), - IMX_PINCTRL_PIN(MX35_PAD_COMPARE), - IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST), - IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0), - IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1), - IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0), - IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0), - IMX_PINCTRL_PIN(MX35_PAD_CLKO), - IMX_PINCTRL_PIN(MX35_PAD_VSTBY), - IMX_PINCTRL_PIN(MX35_PAD_A0), - IMX_PINCTRL_PIN(MX35_PAD_A1), - IMX_PINCTRL_PIN(MX35_PAD_A2), - IMX_PINCTRL_PIN(MX35_PAD_A3), - IMX_PINCTRL_PIN(MX35_PAD_A4), - IMX_PINCTRL_PIN(MX35_PAD_A5), - IMX_PINCTRL_PIN(MX35_PAD_A6), - IMX_PINCTRL_PIN(MX35_PAD_A7), - IMX_PINCTRL_PIN(MX35_PAD_A8), - IMX_PINCTRL_PIN(MX35_PAD_A9), - IMX_PINCTRL_PIN(MX35_PAD_A10), - IMX_PINCTRL_PIN(MX35_PAD_MA10), - IMX_PINCTRL_PIN(MX35_PAD_A11), - IMX_PINCTRL_PIN(MX35_PAD_A12), - IMX_PINCTRL_PIN(MX35_PAD_A13), - IMX_PINCTRL_PIN(MX35_PAD_A14), - IMX_PINCTRL_PIN(MX35_PAD_A15), - IMX_PINCTRL_PIN(MX35_PAD_A16), - IMX_PINCTRL_PIN(MX35_PAD_A17), - IMX_PINCTRL_PIN(MX35_PAD_A18), - IMX_PINCTRL_PIN(MX35_PAD_A19), - IMX_PINCTRL_PIN(MX35_PAD_A20), - IMX_PINCTRL_PIN(MX35_PAD_A21), - IMX_PINCTRL_PIN(MX35_PAD_A22), - IMX_PINCTRL_PIN(MX35_PAD_A23), - IMX_PINCTRL_PIN(MX35_PAD_A24), - IMX_PINCTRL_PIN(MX35_PAD_A25), - IMX_PINCTRL_PIN(MX35_PAD_EB0), - IMX_PINCTRL_PIN(MX35_PAD_EB1), - IMX_PINCTRL_PIN(MX35_PAD_OE), - IMX_PINCTRL_PIN(MX35_PAD_CS0), - IMX_PINCTRL_PIN(MX35_PAD_CS1), - IMX_PINCTRL_PIN(MX35_PAD_CS2), - IMX_PINCTRL_PIN(MX35_PAD_CS3), - IMX_PINCTRL_PIN(MX35_PAD_CS4), - IMX_PINCTRL_PIN(MX35_PAD_CS5), - IMX_PINCTRL_PIN(MX35_PAD_NF_CE0), - IMX_PINCTRL_PIN(MX35_PAD_LBA), - IMX_PINCTRL_PIN(MX35_PAD_BCLK), - IMX_PINCTRL_PIN(MX35_PAD_RW), - IMX_PINCTRL_PIN(MX35_PAD_NFWE_B), - IMX_PINCTRL_PIN(MX35_PAD_NFRE_B), - IMX_PINCTRL_PIN(MX35_PAD_NFALE), - IMX_PINCTRL_PIN(MX35_PAD_NFCLE), - IMX_PINCTRL_PIN(MX35_PAD_NFWP_B), - IMX_PINCTRL_PIN(MX35_PAD_NFRB), - IMX_PINCTRL_PIN(MX35_PAD_CSI_D8), - IMX_PINCTRL_PIN(MX35_PAD_CSI_D9), - IMX_PINCTRL_PIN(MX35_PAD_CSI_D10), - IMX_PINCTRL_PIN(MX35_PAD_CSI_D11), - IMX_PINCTRL_PIN(MX35_PAD_CSI_D12), - IMX_PINCTRL_PIN(MX35_PAD_CSI_D13), - IMX_PINCTRL_PIN(MX35_PAD_CSI_D14), - IMX_PINCTRL_PIN(MX35_PAD_CSI_D15), - IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK), - IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC), - IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC), - IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK), - IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK), - IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT), - IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK), - IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT), - IMX_PINCTRL_PIN(MX35_PAD_STXD4), - IMX_PINCTRL_PIN(MX35_PAD_SRXD4), - IMX_PINCTRL_PIN(MX35_PAD_SCK4), - IMX_PINCTRL_PIN(MX35_PAD_STXFS4), - IMX_PINCTRL_PIN(MX35_PAD_STXD5), - IMX_PINCTRL_PIN(MX35_PAD_SRXD5), - IMX_PINCTRL_PIN(MX35_PAD_SCK5), - IMX_PINCTRL_PIN(MX35_PAD_STXFS5), - IMX_PINCTRL_PIN(MX35_PAD_SCKR), - IMX_PINCTRL_PIN(MX35_PAD_FSR), - IMX_PINCTRL_PIN(MX35_PAD_HCKR), - IMX_PINCTRL_PIN(MX35_PAD_SCKT), - IMX_PINCTRL_PIN(MX35_PAD_FST), - IMX_PINCTRL_PIN(MX35_PAD_HCKT), - IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0), - IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1), - IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2), - IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3), - IMX_PINCTRL_PIN(MX35_PAD_TX1), - IMX_PINCTRL_PIN(MX35_PAD_TX0), - IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI), - IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO), - IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0), - IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1), - IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK), - IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY), - IMX_PINCTRL_PIN(MX35_PAD_RXD1), - IMX_PINCTRL_PIN(MX35_PAD_TXD1), - IMX_PINCTRL_PIN(MX35_PAD_RTS1), - IMX_PINCTRL_PIN(MX35_PAD_CTS1), - IMX_PINCTRL_PIN(MX35_PAD_RXD2), - IMX_PINCTRL_PIN(MX35_PAD_TXD2), - IMX_PINCTRL_PIN(MX35_PAD_RTS2), - IMX_PINCTRL_PIN(MX35_PAD_CTS2), - IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR), - IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC), - IMX_PINCTRL_PIN(MX35_PAD_LD0), - IMX_PINCTRL_PIN(MX35_PAD_LD1), - IMX_PINCTRL_PIN(MX35_PAD_LD2), - IMX_PINCTRL_PIN(MX35_PAD_LD3), - IMX_PINCTRL_PIN(MX35_PAD_LD4), - IMX_PINCTRL_PIN(MX35_PAD_LD5), - IMX_PINCTRL_PIN(MX35_PAD_LD6), - IMX_PINCTRL_PIN(MX35_PAD_LD7), - IMX_PINCTRL_PIN(MX35_PAD_LD8), - IMX_PINCTRL_PIN(MX35_PAD_LD9), - IMX_PINCTRL_PIN(MX35_PAD_LD10), - IMX_PINCTRL_PIN(MX35_PAD_LD11), - IMX_PINCTRL_PIN(MX35_PAD_LD12), - IMX_PINCTRL_PIN(MX35_PAD_LD13), - IMX_PINCTRL_PIN(MX35_PAD_LD14), - IMX_PINCTRL_PIN(MX35_PAD_LD15), - IMX_PINCTRL_PIN(MX35_PAD_LD16), - IMX_PINCTRL_PIN(MX35_PAD_LD17), - IMX_PINCTRL_PIN(MX35_PAD_LD18), - IMX_PINCTRL_PIN(MX35_PAD_LD19), - IMX_PINCTRL_PIN(MX35_PAD_LD20), - IMX_PINCTRL_PIN(MX35_PAD_LD21), - IMX_PINCTRL_PIN(MX35_PAD_LD22), - IMX_PINCTRL_PIN(MX35_PAD_LD23), - IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC), - IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT), - IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY), - IMX_PINCTRL_PIN(MX35_PAD_CONTRAST), - IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC), - IMX_PINCTRL_PIN(MX35_PAD_D3_REV), - IMX_PINCTRL_PIN(MX35_PAD_D3_CLS), - IMX_PINCTRL_PIN(MX35_PAD_D3_SPL), - IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0), - IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1), - IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2), - IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3), - IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0), - IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1), - IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2), - IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3), - IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0), - IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK), - IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B), - IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15), - IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ), - IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1), - IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2), - IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK), - IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT), - IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG), - IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK), - IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK), - IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV), - IMX_PINCTRL_PIN(MX35_PAD_FEC_COL), - IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0), - IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0), - IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN), - IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC), - IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO), - IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR), - IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR), - IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS), - IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1), - IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1), - IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2), - IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2), - IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3), - IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE2), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE3), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE4), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE5), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE6), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE7), - IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B), - IMX_PINCTRL_PIN(MX35_PAD_POR_B), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE8), - IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0), - IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1), - IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0), - IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1), - IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE9), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE10), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE11), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE12), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE13), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE14), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE15), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE16), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE17), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE18), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE19), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE20), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE21), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE22), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE23), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE24), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE25), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE26), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE27), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE28), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE29), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE30), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE31), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE32), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE33), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE34), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE35), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE36), - IMX_PINCTRL_PIN(MX35_PAD_SDBA1), - IMX_PINCTRL_PIN(MX35_PAD_SDBA0), - IMX_PINCTRL_PIN(MX35_PAD_SD0), - IMX_PINCTRL_PIN(MX35_PAD_SD1), - IMX_PINCTRL_PIN(MX35_PAD_SD2), - IMX_PINCTRL_PIN(MX35_PAD_SD3), - IMX_PINCTRL_PIN(MX35_PAD_SD4), - IMX_PINCTRL_PIN(MX35_PAD_SD5), - IMX_PINCTRL_PIN(MX35_PAD_SD6), - IMX_PINCTRL_PIN(MX35_PAD_SD7), - IMX_PINCTRL_PIN(MX35_PAD_SD8), - IMX_PINCTRL_PIN(MX35_PAD_SD9), - IMX_PINCTRL_PIN(MX35_PAD_SD10), - IMX_PINCTRL_PIN(MX35_PAD_SD11), - IMX_PINCTRL_PIN(MX35_PAD_SD12), - IMX_PINCTRL_PIN(MX35_PAD_SD13), - IMX_PINCTRL_PIN(MX35_PAD_SD14), - IMX_PINCTRL_PIN(MX35_PAD_SD15), - IMX_PINCTRL_PIN(MX35_PAD_SD16), - IMX_PINCTRL_PIN(MX35_PAD_SD17), - IMX_PINCTRL_PIN(MX35_PAD_SD18), - IMX_PINCTRL_PIN(MX35_PAD_SD19), - IMX_PINCTRL_PIN(MX35_PAD_SD20), - IMX_PINCTRL_PIN(MX35_PAD_SD21), - IMX_PINCTRL_PIN(MX35_PAD_SD22), - IMX_PINCTRL_PIN(MX35_PAD_SD23), - IMX_PINCTRL_PIN(MX35_PAD_SD24), - IMX_PINCTRL_PIN(MX35_PAD_SD25), - IMX_PINCTRL_PIN(MX35_PAD_SD26), - IMX_PINCTRL_PIN(MX35_PAD_SD27), - IMX_PINCTRL_PIN(MX35_PAD_SD28), - IMX_PINCTRL_PIN(MX35_PAD_SD29), - IMX_PINCTRL_PIN(MX35_PAD_SD30), - IMX_PINCTRL_PIN(MX35_PAD_SD31), - IMX_PINCTRL_PIN(MX35_PAD_DQM0), - IMX_PINCTRL_PIN(MX35_PAD_DQM1), - IMX_PINCTRL_PIN(MX35_PAD_DQM2), - IMX_PINCTRL_PIN(MX35_PAD_DQM3), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE37), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE38), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE39), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE40), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE41), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE42), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE43), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE44), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE45), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE46), - IMX_PINCTRL_PIN(MX35_PAD_ECB), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE47), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE48), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE49), - IMX_PINCTRL_PIN(MX35_PAD_RAS), - IMX_PINCTRL_PIN(MX35_PAD_CAS), - IMX_PINCTRL_PIN(MX35_PAD_SDWE), - IMX_PINCTRL_PIN(MX35_PAD_SDCKE0), - IMX_PINCTRL_PIN(MX35_PAD_SDCKE1), - IMX_PINCTRL_PIN(MX35_PAD_SDCLK), - IMX_PINCTRL_PIN(MX35_PAD_SDQS0), - IMX_PINCTRL_PIN(MX35_PAD_SDQS1), - IMX_PINCTRL_PIN(MX35_PAD_SDQS2), - IMX_PINCTRL_PIN(MX35_PAD_SDQS3), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE50), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE51), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE52), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE53), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE54), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE55), - IMX_PINCTRL_PIN(MX35_PAD_D15), - IMX_PINCTRL_PIN(MX35_PAD_D14), - IMX_PINCTRL_PIN(MX35_PAD_D13), - IMX_PINCTRL_PIN(MX35_PAD_D12), - IMX_PINCTRL_PIN(MX35_PAD_D11), - IMX_PINCTRL_PIN(MX35_PAD_D10), - IMX_PINCTRL_PIN(MX35_PAD_D9), - IMX_PINCTRL_PIN(MX35_PAD_D8), - IMX_PINCTRL_PIN(MX35_PAD_D7), - IMX_PINCTRL_PIN(MX35_PAD_D6), - IMX_PINCTRL_PIN(MX35_PAD_D5), - IMX_PINCTRL_PIN(MX35_PAD_D4), - IMX_PINCTRL_PIN(MX35_PAD_D3), - IMX_PINCTRL_PIN(MX35_PAD_D2), - IMX_PINCTRL_PIN(MX35_PAD_D1), - IMX_PINCTRL_PIN(MX35_PAD_D0), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE56), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE57), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE58), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE59), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE60), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE61), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE62), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE63), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE64), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE65), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE66), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE67), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE68), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE69), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE70), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE71), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE72), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE73), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE74), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE75), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE76), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE77), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE78), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE79), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE80), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE81), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE82), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE83), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE84), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE85), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE86), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE87), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE88), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE89), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE90), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE91), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE92), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE93), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE94), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE95), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE96), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE97), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE98), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE99), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE100), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE101), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE102), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE103), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE104), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE105), - IMX_PINCTRL_PIN(MX35_PAD_RTCK), - IMX_PINCTRL_PIN(MX35_PAD_TCK), - IMX_PINCTRL_PIN(MX35_PAD_TMS), - IMX_PINCTRL_PIN(MX35_PAD_TDI), - IMX_PINCTRL_PIN(MX35_PAD_TDO), - IMX_PINCTRL_PIN(MX35_PAD_TRSTB), - IMX_PINCTRL_PIN(MX35_PAD_DE_B), - IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE106), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE107), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE108), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE109), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE110), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE111), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE112), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE113), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE114), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE115), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE116), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE117), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE118), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE119), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE120), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE121), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE122), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE123), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE124), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE125), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE126), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE127), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE128), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE129), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE130), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE131), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE132), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE133), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE134), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE135), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE136), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE137), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE138), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE139), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE140), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE141), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE142), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE143), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE144), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE145), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE146), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE147), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE148), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE149), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE150), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE151), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE152), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE153), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE154), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE155), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE156), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE157), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE158), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE159), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE160), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE161), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE162), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE163), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE164), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE165), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE166), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE167), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE168), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE169), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE170), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE171), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE172), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE173), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE174), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE175), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE176), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE177), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE178), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE179), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE180), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE181), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE182), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE183), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE184), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE185), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE186), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE187), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE188), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE189), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE190), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE191), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE192), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE193), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE194), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE195), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE196), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE197), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE198), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE199), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE200), - IMX_PINCTRL_PIN(MX35_PAD_RESERVE201), - IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK), - IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE), -}; - -static struct imx_pinctrl_soc_info imx35_pinctrl_info = { - .pins = imx35_pinctrl_pads, - .npins = ARRAY_SIZE(imx35_pinctrl_pads), -}; - -static const struct of_device_id imx35_pinctrl_of_match[] = { - { .compatible = "fsl,imx35-iomuxc", }, - { /* sentinel */ } -}; - -static int imx35_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx35_pinctrl_info); -} - -static struct platform_driver imx35_pinctrl_driver = { - .driver = { - .name = "imx35-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx35_pinctrl_of_match, - }, - .probe = imx35_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx35_pinctrl_init(void) -{ - return platform_driver_register(&imx35_pinctrl_driver); -} -arch_initcall(imx35_pinctrl_init); - -static void __exit imx35_pinctrl_exit(void) -{ - platform_driver_unregister(&imx35_pinctrl_driver); -} -module_exit(imx35_pinctrl_exit); -MODULE_AUTHOR("Dong Aisheng "); -MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx50.c b/drivers/pinctrl/pinctrl-imx50.c deleted file mode 100644 index e8bd604ab147..000000000000 --- a/drivers/pinctrl/pinctrl-imx50.c +++ /dev/null @@ -1,426 +0,0 @@ -/* - * imx50 pinctrl driver based on imx pinmux core - * - * Copyright (C) 2013 Greg Ungerer - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx50_pads { - MX50_PAD_RESERVE0 = 0, - MX50_PAD_RESERVE1 = 1, - MX50_PAD_RESERVE2 = 2, - MX50_PAD_RESERVE3 = 3, - MX50_PAD_RESERVE4 = 4, - MX50_PAD_RESERVE5 = 5, - MX50_PAD_RESERVE6 = 6, - MX50_PAD_RESERVE7 = 7, - MX50_PAD_KEY_COL0 = 8, - MX50_PAD_KEY_ROW0 = 9, - MX50_PAD_KEY_COL1 = 10, - MX50_PAD_KEY_ROW1 = 11, - MX50_PAD_KEY_COL2 = 12, - MX50_PAD_KEY_ROW2 = 13, - MX50_PAD_KEY_COL3 = 14, - MX50_PAD_KEY_ROW3 = 15, - MX50_PAD_I2C1_SCL = 16, - MX50_PAD_I2C1_SDA = 17, - MX50_PAD_I2C2_SCL = 18, - MX50_PAD_I2C2_SDA = 19, - MX50_PAD_I2C3_SCL = 20, - MX50_PAD_I2C3_SDA = 21, - MX50_PAD_PWM1 = 22, - MX50_PAD_PWM2 = 23, - MX50_PAD_0WIRE = 24, - MX50_PAD_EPITO = 25, - MX50_PAD_WDOG = 26, - MX50_PAD_SSI_TXFS = 27, - MX50_PAD_SSI_TXC = 28, - MX50_PAD_SSI_TXD = 29, - MX50_PAD_SSI_RXD = 30, - MX50_PAD_SSI_RXF = 31, - MX50_PAD_SSI_RXC = 32, - MX50_PAD_UART1_TXD = 33, - MX50_PAD_UART1_RXD = 34, - MX50_PAD_UART1_CTS = 35, - MX50_PAD_UART1_RTS = 36, - MX50_PAD_UART2_TXD = 37, - MX50_PAD_UART2_RXD = 38, - MX50_PAD_UART2_CTS = 39, - MX50_PAD_UART2_RTS = 40, - MX50_PAD_UART3_TXD = 41, - MX50_PAD_UART3_RXD = 42, - MX50_PAD_UART4_TXD = 43, - MX50_PAD_UART4_RXD = 44, - MX50_PAD_CSPI_CLK = 45, - MX50_PAD_CSPI_MOSI = 46, - MX50_PAD_CSPI_MISO = 47, - MX50_PAD_CSPI_SS0 = 48, - MX50_PAD_ECSPI1_CLK = 49, - MX50_PAD_ECSPI1_MOSI = 50, - MX50_PAD_ECSPI1_MISO = 51, - MX50_PAD_ECSPI1_SS0 = 52, - MX50_PAD_ECSPI2_CLK = 53, - MX50_PAD_ECSPI2_MOSI = 54, - MX50_PAD_ECSPI2_MISO = 55, - MX50_PAD_ECSPI2_SS0 = 56, - MX50_PAD_SD1_CLK = 57, - MX50_PAD_SD1_CMD = 58, - MX50_PAD_SD1_D0 = 59, - MX50_PAD_SD1_D1 = 60, - MX50_PAD_SD1_D2 = 61, - MX50_PAD_SD1_D3 = 62, - MX50_PAD_SD2_CLK = 63, - MX50_PAD_SD2_CMD = 64, - MX50_PAD_SD2_D0 = 65, - MX50_PAD_SD2_D1 = 66, - MX50_PAD_SD2_D2 = 67, - MX50_PAD_SD2_D3 = 68, - MX50_PAD_SD2_D4 = 69, - MX50_PAD_SD2_D5 = 70, - MX50_PAD_SD2_D6 = 71, - MX50_PAD_SD2_D7 = 72, - MX50_PAD_SD2_WP = 73, - MX50_PAD_SD2_CD = 74, - MX50_PAD_DISP_D0 = 75, - MX50_PAD_DISP_D1 = 76, - MX50_PAD_DISP_D2 = 77, - MX50_PAD_DISP_D3 = 78, - MX50_PAD_DISP_D4 = 79, - MX50_PAD_DISP_D5 = 80, - MX50_PAD_DISP_D6 = 81, - MX50_PAD_DISP_D7 = 82, - MX50_PAD_DISP_WR = 83, - MX50_PAD_DISP_RD = 84, - MX50_PAD_DISP_RS = 85, - MX50_PAD_DISP_CS = 86, - MX50_PAD_DISP_BUSY = 87, - MX50_PAD_DISP_RESET = 88, - MX50_PAD_SD3_CLK = 89, - MX50_PAD_SD3_CMD = 90, - MX50_PAD_SD3_D0 = 91, - MX50_PAD_SD3_D1 = 92, - MX50_PAD_SD3_D2 = 93, - MX50_PAD_SD3_D3 = 94, - MX50_PAD_SD3_D4 = 95, - MX50_PAD_SD3_D5 = 96, - MX50_PAD_SD3_D6 = 97, - MX50_PAD_SD3_D7 = 98, - MX50_PAD_SD3_WP = 99, - MX50_PAD_DISP_D8 = 100, - MX50_PAD_DISP_D9 = 101, - MX50_PAD_DISP_D10 = 102, - MX50_PAD_DISP_D11 = 103, - MX50_PAD_DISP_D12 = 104, - MX50_PAD_DISP_D13 = 105, - MX50_PAD_DISP_D14 = 106, - MX50_PAD_DISP_D15 = 107, - MX50_PAD_EPDC_D0 = 108, - MX50_PAD_EPDC_D1 = 109, - MX50_PAD_EPDC_D2 = 110, - MX50_PAD_EPDC_D3 = 111, - MX50_PAD_EPDC_D4 = 112, - MX50_PAD_EPDC_D5 = 113, - MX50_PAD_EPDC_D6 = 114, - MX50_PAD_EPDC_D7 = 115, - MX50_PAD_EPDC_D8 = 116, - MX50_PAD_EPDC_D9 = 117, - MX50_PAD_EPDC_D10 = 118, - MX50_PAD_EPDC_D11 = 119, - MX50_PAD_EPDC_D12 = 120, - MX50_PAD_EPDC_D13 = 121, - MX50_PAD_EPDC_D14 = 122, - MX50_PAD_EPDC_D15 = 123, - MX50_PAD_EPDC_GDCLK = 124, - MX50_PAD_EPDC_GDSP = 125, - MX50_PAD_EPDC_GDOE = 126, - MX50_PAD_EPDC_GDRL = 127, - MX50_PAD_EPDC_SDCLK = 128, - MX50_PAD_EPDC_SDOEZ = 129, - MX50_PAD_EPDC_SDOED = 130, - MX50_PAD_EPDC_SDOE = 131, - MX50_PAD_EPDC_SDLE = 132, - MX50_PAD_EPDC_SDCLKN = 133, - MX50_PAD_EPDC_SDSHR = 134, - MX50_PAD_EPDC_PWRCOM = 135, - MX50_PAD_EPDC_PWRSTAT = 136, - MX50_PAD_EPDC_PWRCTRL0 = 137, - MX50_PAD_EPDC_PWRCTRL1 = 138, - MX50_PAD_EPDC_PWRCTRL2 = 139, - MX50_PAD_EPDC_PWRCTRL3 = 140, - MX50_PAD_EPDC_VCOM0 = 141, - MX50_PAD_EPDC_VCOM1 = 142, - MX50_PAD_EPDC_BDR0 = 143, - MX50_PAD_EPDC_BDR1 = 144, - MX50_PAD_EPDC_SDCE0 = 145, - MX50_PAD_EPDC_SDCE1 = 146, - MX50_PAD_EPDC_SDCE2 = 147, - MX50_PAD_EPDC_SDCE3 = 148, - MX50_PAD_EPDC_SDCE4 = 149, - MX50_PAD_EPDC_SDCE5 = 150, - MX50_PAD_EIM_DA0 = 151, - MX50_PAD_EIM_DA1 = 152, - MX50_PAD_EIM_DA2 = 153, - MX50_PAD_EIM_DA3 = 154, - MX50_PAD_EIM_DA4 = 155, - MX50_PAD_EIM_DA5 = 156, - MX50_PAD_EIM_DA6 = 157, - MX50_PAD_EIM_DA7 = 158, - MX50_PAD_EIM_DA8 = 159, - MX50_PAD_EIM_DA9 = 160, - MX50_PAD_EIM_DA10 = 161, - MX50_PAD_EIM_DA11 = 162, - MX50_PAD_EIM_DA12 = 163, - MX50_PAD_EIM_DA13 = 164, - MX50_PAD_EIM_DA14 = 165, - MX50_PAD_EIM_DA15 = 166, - MX50_PAD_EIM_CS2 = 167, - MX50_PAD_EIM_CS1 = 168, - MX50_PAD_EIM_CS0 = 169, - MX50_PAD_EIM_EB0 = 170, - MX50_PAD_EIM_EB1 = 171, - MX50_PAD_EIM_WAIT = 172, - MX50_PAD_EIM_BCLK = 173, - MX50_PAD_EIM_RDY = 174, - MX50_PAD_EIM_OE = 175, - MX50_PAD_EIM_RW = 176, - MX50_PAD_EIM_LBA = 177, - MX50_PAD_EIM_CRE = 178, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX50_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX50_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX50_PAD_RESERVE2), - IMX_PINCTRL_PIN(MX50_PAD_RESERVE3), - IMX_PINCTRL_PIN(MX50_PAD_RESERVE4), - IMX_PINCTRL_PIN(MX50_PAD_RESERVE5), - IMX_PINCTRL_PIN(MX50_PAD_RESERVE6), - IMX_PINCTRL_PIN(MX50_PAD_RESERVE7), - IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL), - IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA), - IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL), - IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA), - IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL), - IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA), - IMX_PINCTRL_PIN(MX50_PAD_PWM1), - IMX_PINCTRL_PIN(MX50_PAD_PWM2), - IMX_PINCTRL_PIN(MX50_PAD_0WIRE), - IMX_PINCTRL_PIN(MX50_PAD_EPITO), - IMX_PINCTRL_PIN(MX50_PAD_WDOG), - IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS), - IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC), - IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD), - IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD), - IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF), - IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC), - IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD), - IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD), - IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS), - IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS), - IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD), - IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD), - IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS), - IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS), - IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD), - IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD), - IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD), - IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD), - IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK), - IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI), - IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO), - IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0), - IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK), - IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI), - IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO), - IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0), - IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK), - IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI), - IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO), - IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0), - IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX50_PAD_SD1_D0), - IMX_PINCTRL_PIN(MX50_PAD_SD1_D1), - IMX_PINCTRL_PIN(MX50_PAD_SD1_D2), - IMX_PINCTRL_PIN(MX50_PAD_SD1_D3), - IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX50_PAD_SD2_D0), - IMX_PINCTRL_PIN(MX50_PAD_SD2_D1), - IMX_PINCTRL_PIN(MX50_PAD_SD2_D2), - IMX_PINCTRL_PIN(MX50_PAD_SD2_D3), - IMX_PINCTRL_PIN(MX50_PAD_SD2_D4), - IMX_PINCTRL_PIN(MX50_PAD_SD2_D5), - IMX_PINCTRL_PIN(MX50_PAD_SD2_D6), - IMX_PINCTRL_PIN(MX50_PAD_SD2_D7), - IMX_PINCTRL_PIN(MX50_PAD_SD2_WP), - IMX_PINCTRL_PIN(MX50_PAD_SD2_CD), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D0), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D1), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D2), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D3), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D4), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D5), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D6), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D7), - IMX_PINCTRL_PIN(MX50_PAD_DISP_WR), - IMX_PINCTRL_PIN(MX50_PAD_DISP_RD), - IMX_PINCTRL_PIN(MX50_PAD_DISP_RS), - IMX_PINCTRL_PIN(MX50_PAD_DISP_CS), - IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY), - IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET), - IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK), - IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD), - IMX_PINCTRL_PIN(MX50_PAD_SD3_D0), - IMX_PINCTRL_PIN(MX50_PAD_SD3_D1), - IMX_PINCTRL_PIN(MX50_PAD_SD3_D2), - IMX_PINCTRL_PIN(MX50_PAD_SD3_D3), - IMX_PINCTRL_PIN(MX50_PAD_SD3_D4), - IMX_PINCTRL_PIN(MX50_PAD_SD3_D5), - IMX_PINCTRL_PIN(MX50_PAD_SD3_D6), - IMX_PINCTRL_PIN(MX50_PAD_SD3_D7), - IMX_PINCTRL_PIN(MX50_PAD_SD3_WP), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D8), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D9), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D10), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D11), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D12), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D13), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D14), - IMX_PINCTRL_PIN(MX50_PAD_DISP_D15), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4), - IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14), - IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15), - IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2), - IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1), - IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0), - IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0), - IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1), - IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT), - IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK), - IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY), - IMX_PINCTRL_PIN(MX50_PAD_EIM_OE), - IMX_PINCTRL_PIN(MX50_PAD_EIM_RW), - IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA), - IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE), -}; - -static struct imx_pinctrl_soc_info imx50_pinctrl_info = { - .pins = imx50_pinctrl_pads, - .npins = ARRAY_SIZE(imx50_pinctrl_pads), -}; - -static const struct of_device_id imx50_pinctrl_of_match[] = { - { .compatible = "fsl,imx50-iomuxc", }, - { /* sentinel */ } -}; - -static int imx50_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx50_pinctrl_info); -} - -static struct platform_driver imx50_pinctrl_driver = { - .driver = { - .name = "imx50-pinctrl", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx50_pinctrl_of_match), - }, - .probe = imx50_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx50_pinctrl_init(void) -{ - return platform_driver_register(&imx50_pinctrl_driver); -} -arch_initcall(imx50_pinctrl_init); - -static void __exit imx50_pinctrl_exit(void) -{ - platform_driver_unregister(&imx50_pinctrl_driver); -} -module_exit(imx50_pinctrl_exit); -MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c deleted file mode 100644 index b818051db7c9..000000000000 --- a/drivers/pinctrl/pinctrl-imx51.c +++ /dev/null @@ -1,804 +0,0 @@ -/* - * imx51 pinctrl driver based on imx pinmux core - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro, Inc. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx51_pads { - MX51_PAD_RESERVE0 = 0, - MX51_PAD_RESERVE1 = 1, - MX51_PAD_RESERVE2 = 2, - MX51_PAD_RESERVE3 = 3, - MX51_PAD_RESERVE4 = 4, - MX51_PAD_RESERVE5 = 5, - MX51_PAD_RESERVE6 = 6, - MX51_PAD_EIM_DA0 = 7, - MX51_PAD_EIM_DA1 = 8, - MX51_PAD_EIM_DA2 = 9, - MX51_PAD_EIM_DA3 = 10, - MX51_PAD_EIM_DA4 = 11, - MX51_PAD_EIM_DA5 = 12, - MX51_PAD_EIM_DA6 = 13, - MX51_PAD_EIM_DA7 = 14, - MX51_PAD_EIM_DA8 = 15, - MX51_PAD_EIM_DA9 = 16, - MX51_PAD_EIM_DA10 = 17, - MX51_PAD_EIM_DA11 = 18, - MX51_PAD_EIM_DA12 = 19, - MX51_PAD_EIM_DA13 = 20, - MX51_PAD_EIM_DA14 = 21, - MX51_PAD_EIM_DA15 = 22, - MX51_PAD_EIM_D16 = 23, - MX51_PAD_EIM_D17 = 24, - MX51_PAD_EIM_D18 = 25, - MX51_PAD_EIM_D19 = 26, - MX51_PAD_EIM_D20 = 27, - MX51_PAD_EIM_D21 = 28, - MX51_PAD_EIM_D22 = 29, - MX51_PAD_EIM_D23 = 30, - MX51_PAD_EIM_D24 = 31, - MX51_PAD_EIM_D25 = 32, - MX51_PAD_EIM_D26 = 33, - MX51_PAD_EIM_D27 = 34, - MX51_PAD_EIM_D28 = 35, - MX51_PAD_EIM_D29 = 36, - MX51_PAD_EIM_D30 = 37, - MX51_PAD_EIM_D31 = 38, - MX51_PAD_EIM_A16 = 39, - MX51_PAD_EIM_A17 = 40, - MX51_PAD_EIM_A18 = 41, - MX51_PAD_EIM_A19 = 42, - MX51_PAD_EIM_A20 = 43, - MX51_PAD_EIM_A21 = 44, - MX51_PAD_EIM_A22 = 45, - MX51_PAD_EIM_A23 = 46, - MX51_PAD_EIM_A24 = 47, - MX51_PAD_EIM_A25 = 48, - MX51_PAD_EIM_A26 = 49, - MX51_PAD_EIM_A27 = 50, - MX51_PAD_EIM_EB0 = 51, - MX51_PAD_EIM_EB1 = 52, - MX51_PAD_EIM_EB2 = 53, - MX51_PAD_EIM_EB3 = 54, - MX51_PAD_EIM_OE = 55, - MX51_PAD_EIM_CS0 = 56, - MX51_PAD_EIM_CS1 = 57, - MX51_PAD_EIM_CS2 = 58, - MX51_PAD_EIM_CS3 = 59, - MX51_PAD_EIM_CS4 = 60, - MX51_PAD_EIM_CS5 = 61, - MX51_PAD_EIM_DTACK = 62, - MX51_PAD_EIM_LBA = 63, - MX51_PAD_EIM_CRE = 64, - MX51_PAD_DRAM_CS1 = 65, - MX51_PAD_NANDF_WE_B = 66, - MX51_PAD_NANDF_RE_B = 67, - MX51_PAD_NANDF_ALE = 68, - MX51_PAD_NANDF_CLE = 69, - MX51_PAD_NANDF_WP_B = 70, - MX51_PAD_NANDF_RB0 = 71, - MX51_PAD_NANDF_RB1 = 72, - MX51_PAD_NANDF_RB2 = 73, - MX51_PAD_NANDF_RB3 = 74, - MX51_PAD_GPIO_NAND = 75, - MX51_PAD_NANDF_CS0 = 76, - MX51_PAD_NANDF_CS1 = 77, - MX51_PAD_NANDF_CS2 = 78, - MX51_PAD_NANDF_CS3 = 79, - MX51_PAD_NANDF_CS4 = 80, - MX51_PAD_NANDF_CS5 = 81, - MX51_PAD_NANDF_CS6 = 82, - MX51_PAD_NANDF_CS7 = 83, - MX51_PAD_NANDF_RDY_INT = 84, - MX51_PAD_NANDF_D15 = 85, - MX51_PAD_NANDF_D14 = 86, - MX51_PAD_NANDF_D13 = 87, - MX51_PAD_NANDF_D12 = 88, - MX51_PAD_NANDF_D11 = 89, - MX51_PAD_NANDF_D10 = 90, - MX51_PAD_NANDF_D9 = 91, - MX51_PAD_NANDF_D8 = 92, - MX51_PAD_NANDF_D7 = 93, - MX51_PAD_NANDF_D6 = 94, - MX51_PAD_NANDF_D5 = 95, - MX51_PAD_NANDF_D4 = 96, - MX51_PAD_NANDF_D3 = 97, - MX51_PAD_NANDF_D2 = 98, - MX51_PAD_NANDF_D1 = 99, - MX51_PAD_NANDF_D0 = 100, - MX51_PAD_CSI1_D8 = 101, - MX51_PAD_CSI1_D9 = 102, - MX51_PAD_CSI1_D10 = 103, - MX51_PAD_CSI1_D11 = 104, - MX51_PAD_CSI1_D12 = 105, - MX51_PAD_CSI1_D13 = 106, - MX51_PAD_CSI1_D14 = 107, - MX51_PAD_CSI1_D15 = 108, - MX51_PAD_CSI1_D16 = 109, - MX51_PAD_CSI1_D17 = 110, - MX51_PAD_CSI1_D18 = 111, - MX51_PAD_CSI1_D19 = 112, - MX51_PAD_CSI1_VSYNC = 113, - MX51_PAD_CSI1_HSYNC = 114, - MX51_PAD_CSI2_D12 = 115, - MX51_PAD_CSI2_D13 = 116, - MX51_PAD_CSI2_D14 = 117, - MX51_PAD_CSI2_D15 = 118, - MX51_PAD_CSI2_D16 = 119, - MX51_PAD_CSI2_D17 = 120, - MX51_PAD_CSI2_D18 = 121, - MX51_PAD_CSI2_D19 = 122, - MX51_PAD_CSI2_VSYNC = 123, - MX51_PAD_CSI2_HSYNC = 124, - MX51_PAD_CSI2_PIXCLK = 125, - MX51_PAD_I2C1_CLK = 126, - MX51_PAD_I2C1_DAT = 127, - MX51_PAD_AUD3_BB_TXD = 128, - MX51_PAD_AUD3_BB_RXD = 129, - MX51_PAD_AUD3_BB_CK = 130, - MX51_PAD_AUD3_BB_FS = 131, - MX51_PAD_CSPI1_MOSI = 132, - MX51_PAD_CSPI1_MISO = 133, - MX51_PAD_CSPI1_SS0 = 134, - MX51_PAD_CSPI1_SS1 = 135, - MX51_PAD_CSPI1_RDY = 136, - MX51_PAD_CSPI1_SCLK = 137, - MX51_PAD_UART1_RXD = 138, - MX51_PAD_UART1_TXD = 139, - MX51_PAD_UART1_RTS = 140, - MX51_PAD_UART1_CTS = 141, - MX51_PAD_UART2_RXD = 142, - MX51_PAD_UART2_TXD = 143, - MX51_PAD_UART3_RXD = 144, - MX51_PAD_UART3_TXD = 145, - MX51_PAD_OWIRE_LINE = 146, - MX51_PAD_KEY_ROW0 = 147, - MX51_PAD_KEY_ROW1 = 148, - MX51_PAD_KEY_ROW2 = 149, - MX51_PAD_KEY_ROW3 = 150, - MX51_PAD_KEY_COL0 = 151, - MX51_PAD_KEY_COL1 = 152, - MX51_PAD_KEY_COL2 = 153, - MX51_PAD_KEY_COL3 = 154, - MX51_PAD_KEY_COL4 = 155, - MX51_PAD_KEY_COL5 = 156, - MX51_PAD_RESERVE7 = 157, - MX51_PAD_USBH1_CLK = 158, - MX51_PAD_USBH1_DIR = 159, - MX51_PAD_USBH1_STP = 160, - MX51_PAD_USBH1_NXT = 161, - MX51_PAD_USBH1_DATA0 = 162, - MX51_PAD_USBH1_DATA1 = 163, - MX51_PAD_USBH1_DATA2 = 164, - MX51_PAD_USBH1_DATA3 = 165, - MX51_PAD_USBH1_DATA4 = 166, - MX51_PAD_USBH1_DATA5 = 167, - MX51_PAD_USBH1_DATA6 = 168, - MX51_PAD_USBH1_DATA7 = 169, - MX51_PAD_DI1_PIN11 = 170, - MX51_PAD_DI1_PIN12 = 171, - MX51_PAD_DI1_PIN13 = 172, - MX51_PAD_DI1_D0_CS = 173, - MX51_PAD_DI1_D1_CS = 174, - MX51_PAD_DISPB2_SER_DIN = 175, - MX51_PAD_DISPB2_SER_DIO = 176, - MX51_PAD_DISPB2_SER_CLK = 177, - MX51_PAD_DISPB2_SER_RS = 178, - MX51_PAD_DISP1_DAT0 = 179, - MX51_PAD_DISP1_DAT1 = 180, - MX51_PAD_DISP1_DAT2 = 181, - MX51_PAD_DISP1_DAT3 = 182, - MX51_PAD_DISP1_DAT4 = 183, - MX51_PAD_DISP1_DAT5 = 184, - MX51_PAD_DISP1_DAT6 = 185, - MX51_PAD_DISP1_DAT7 = 186, - MX51_PAD_DISP1_DAT8 = 187, - MX51_PAD_DISP1_DAT9 = 188, - MX51_PAD_DISP1_DAT10 = 189, - MX51_PAD_DISP1_DAT11 = 190, - MX51_PAD_DISP1_DAT12 = 191, - MX51_PAD_DISP1_DAT13 = 192, - MX51_PAD_DISP1_DAT14 = 193, - MX51_PAD_DISP1_DAT15 = 194, - MX51_PAD_DISP1_DAT16 = 195, - MX51_PAD_DISP1_DAT17 = 196, - MX51_PAD_DISP1_DAT18 = 197, - MX51_PAD_DISP1_DAT19 = 198, - MX51_PAD_DISP1_DAT20 = 199, - MX51_PAD_DISP1_DAT21 = 200, - MX51_PAD_DISP1_DAT22 = 201, - MX51_PAD_DISP1_DAT23 = 202, - MX51_PAD_DI1_PIN3 = 203, - MX51_PAD_DI1_PIN2 = 204, - MX51_PAD_RESERVE8 = 205, - MX51_PAD_DI_GP2 = 206, - MX51_PAD_DI_GP3 = 207, - MX51_PAD_DI2_PIN4 = 208, - MX51_PAD_DI2_PIN2 = 209, - MX51_PAD_DI2_PIN3 = 210, - MX51_PAD_DI2_DISP_CLK = 211, - MX51_PAD_DI_GP4 = 212, - MX51_PAD_DISP2_DAT0 = 213, - MX51_PAD_DISP2_DAT1 = 214, - MX51_PAD_DISP2_DAT2 = 215, - MX51_PAD_DISP2_DAT3 = 216, - MX51_PAD_DISP2_DAT4 = 217, - MX51_PAD_DISP2_DAT5 = 218, - MX51_PAD_DISP2_DAT6 = 219, - MX51_PAD_DISP2_DAT7 = 220, - MX51_PAD_DISP2_DAT8 = 221, - MX51_PAD_DISP2_DAT9 = 222, - MX51_PAD_DISP2_DAT10 = 223, - MX51_PAD_DISP2_DAT11 = 224, - MX51_PAD_DISP2_DAT12 = 225, - MX51_PAD_DISP2_DAT13 = 226, - MX51_PAD_DISP2_DAT14 = 227, - MX51_PAD_DISP2_DAT15 = 228, - MX51_PAD_SD1_CMD = 229, - MX51_PAD_SD1_CLK = 230, - MX51_PAD_SD1_DATA0 = 231, - MX51_PAD_SD1_DATA1 = 232, - MX51_PAD_SD1_DATA2 = 233, - MX51_PAD_SD1_DATA3 = 234, - MX51_PAD_GPIO1_0 = 235, - MX51_PAD_GPIO1_1 = 236, - MX51_PAD_SD2_CMD = 237, - MX51_PAD_SD2_CLK = 238, - MX51_PAD_SD2_DATA0 = 239, - MX51_PAD_SD2_DATA1 = 240, - MX51_PAD_SD2_DATA2 = 241, - MX51_PAD_SD2_DATA3 = 242, - MX51_PAD_GPIO1_2 = 243, - MX51_PAD_GPIO1_3 = 244, - MX51_PAD_PMIC_INT_REQ = 245, - MX51_PAD_GPIO1_4 = 246, - MX51_PAD_GPIO1_5 = 247, - MX51_PAD_GPIO1_6 = 248, - MX51_PAD_GPIO1_7 = 249, - MX51_PAD_GPIO1_8 = 250, - MX51_PAD_GPIO1_9 = 251, - MX51_PAD_RESERVE9 = 252, - MX51_PAD_RESERVE10 = 253, - MX51_PAD_RESERVE11 = 254, - MX51_PAD_RESERVE12 = 255, - MX51_PAD_RESERVE13 = 256, - MX51_PAD_RESERVE14 = 257, - MX51_PAD_RESERVE15 = 258, - MX51_PAD_RESERVE16 = 259, - MX51_PAD_RESERVE17 = 260, - MX51_PAD_RESERVE18 = 261, - MX51_PAD_RESERVE19 = 262, - MX51_PAD_RESERVE20 = 263, - MX51_PAD_RESERVE21 = 264, - MX51_PAD_RESERVE22 = 265, - MX51_PAD_RESERVE23 = 266, - MX51_PAD_RESERVE24 = 267, - MX51_PAD_RESERVE25 = 268, - MX51_PAD_RESERVE26 = 269, - MX51_PAD_RESERVE27 = 270, - MX51_PAD_RESERVE28 = 271, - MX51_PAD_RESERVE29 = 272, - MX51_PAD_RESERVE30 = 273, - MX51_PAD_RESERVE31 = 274, - MX51_PAD_RESERVE32 = 275, - MX51_PAD_RESERVE33 = 276, - MX51_PAD_RESERVE34 = 277, - MX51_PAD_RESERVE35 = 278, - MX51_PAD_RESERVE36 = 279, - MX51_PAD_RESERVE37 = 280, - MX51_PAD_RESERVE38 = 281, - MX51_PAD_RESERVE39 = 282, - MX51_PAD_RESERVE40 = 283, - MX51_PAD_RESERVE41 = 284, - MX51_PAD_RESERVE42 = 285, - MX51_PAD_RESERVE43 = 286, - MX51_PAD_RESERVE44 = 287, - MX51_PAD_RESERVE45 = 288, - MX51_PAD_RESERVE46 = 289, - MX51_PAD_RESERVE47 = 290, - MX51_PAD_RESERVE48 = 291, - MX51_PAD_RESERVE49 = 292, - MX51_PAD_RESERVE50 = 293, - MX51_PAD_RESERVE51 = 294, - MX51_PAD_RESERVE52 = 295, - MX51_PAD_RESERVE53 = 296, - MX51_PAD_RESERVE54 = 297, - MX51_PAD_RESERVE55 = 298, - MX51_PAD_RESERVE56 = 299, - MX51_PAD_RESERVE57 = 300, - MX51_PAD_RESERVE58 = 301, - MX51_PAD_RESERVE59 = 302, - MX51_PAD_RESERVE60 = 303, - MX51_PAD_RESERVE61 = 304, - MX51_PAD_RESERVE62 = 305, - MX51_PAD_RESERVE63 = 306, - MX51_PAD_RESERVE64 = 307, - MX51_PAD_RESERVE65 = 308, - MX51_PAD_RESERVE66 = 309, - MX51_PAD_RESERVE67 = 310, - MX51_PAD_RESERVE68 = 311, - MX51_PAD_RESERVE69 = 312, - MX51_PAD_RESERVE70 = 313, - MX51_PAD_RESERVE71 = 314, - MX51_PAD_RESERVE72 = 315, - MX51_PAD_RESERVE73 = 316, - MX51_PAD_RESERVE74 = 317, - MX51_PAD_RESERVE75 = 318, - MX51_PAD_RESERVE76 = 319, - MX51_PAD_RESERVE77 = 320, - MX51_PAD_RESERVE78 = 321, - MX51_PAD_RESERVE79 = 322, - MX51_PAD_RESERVE80 = 323, - MX51_PAD_RESERVE81 = 324, - MX51_PAD_RESERVE82 = 325, - MX51_PAD_RESERVE83 = 326, - MX51_PAD_RESERVE84 = 327, - MX51_PAD_RESERVE85 = 328, - MX51_PAD_RESERVE86 = 329, - MX51_PAD_RESERVE87 = 330, - MX51_PAD_RESERVE88 = 331, - MX51_PAD_RESERVE89 = 332, - MX51_PAD_RESERVE90 = 333, - MX51_PAD_RESERVE91 = 334, - MX51_PAD_RESERVE92 = 335, - MX51_PAD_RESERVE93 = 336, - MX51_PAD_RESERVE94 = 337, - MX51_PAD_RESERVE95 = 338, - MX51_PAD_RESERVE96 = 339, - MX51_PAD_RESERVE97 = 340, - MX51_PAD_RESERVE98 = 341, - MX51_PAD_RESERVE99 = 342, - MX51_PAD_RESERVE100 = 343, - MX51_PAD_RESERVE101 = 344, - MX51_PAD_RESERVE102 = 345, - MX51_PAD_RESERVE103 = 346, - MX51_PAD_RESERVE104 = 347, - MX51_PAD_RESERVE105 = 348, - MX51_PAD_RESERVE106 = 349, - MX51_PAD_RESERVE107 = 350, - MX51_PAD_RESERVE108 = 351, - MX51_PAD_RESERVE109 = 352, - MX51_PAD_RESERVE110 = 353, - MX51_PAD_RESERVE111 = 354, - MX51_PAD_RESERVE112 = 355, - MX51_PAD_RESERVE113 = 356, - MX51_PAD_RESERVE114 = 357, - MX51_PAD_RESERVE115 = 358, - MX51_PAD_RESERVE116 = 359, - MX51_PAD_RESERVE117 = 360, - MX51_PAD_RESERVE118 = 361, - MX51_PAD_RESERVE119 = 362, - MX51_PAD_RESERVE120 = 363, - MX51_PAD_RESERVE121 = 364, - MX51_PAD_CSI1_PIXCLK = 365, - MX51_PAD_CSI1_MCLK = 366, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX51_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE2), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE3), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE4), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE5), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE6), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D16), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D17), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D18), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D19), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D20), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D21), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D22), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D23), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D24), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D25), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D26), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D27), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D28), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D29), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D30), - IMX_PINCTRL_PIN(MX51_PAD_EIM_D31), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A16), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A17), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A18), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A19), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A20), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A21), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A22), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A23), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A24), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A25), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A26), - IMX_PINCTRL_PIN(MX51_PAD_EIM_A27), - IMX_PINCTRL_PIN(MX51_PAD_EIM_EB0), - IMX_PINCTRL_PIN(MX51_PAD_EIM_EB1), - IMX_PINCTRL_PIN(MX51_PAD_EIM_EB2), - IMX_PINCTRL_PIN(MX51_PAD_EIM_EB3), - IMX_PINCTRL_PIN(MX51_PAD_EIM_OE), - IMX_PINCTRL_PIN(MX51_PAD_EIM_CS0), - IMX_PINCTRL_PIN(MX51_PAD_EIM_CS1), - IMX_PINCTRL_PIN(MX51_PAD_EIM_CS2), - IMX_PINCTRL_PIN(MX51_PAD_EIM_CS3), - IMX_PINCTRL_PIN(MX51_PAD_EIM_CS4), - IMX_PINCTRL_PIN(MX51_PAD_EIM_CS5), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DTACK), - IMX_PINCTRL_PIN(MX51_PAD_EIM_LBA), - IMX_PINCTRL_PIN(MX51_PAD_EIM_CRE), - IMX_PINCTRL_PIN(MX51_PAD_DRAM_CS1), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_WE_B), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_RE_B), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_ALE), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CLE), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_WP_B), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB0), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB1), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB2), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB3), - IMX_PINCTRL_PIN(MX51_PAD_GPIO_NAND), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS0), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS1), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS2), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS3), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS4), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS5), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS6), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS7), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_RDY_INT), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D15), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D14), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D13), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D12), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D11), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D10), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D9), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D8), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D7), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D6), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D5), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D4), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D3), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D2), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D1), - IMX_PINCTRL_PIN(MX51_PAD_NANDF_D0), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D8), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D9), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D10), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D11), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D12), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D13), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D14), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D15), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D16), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D17), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D18), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_D15), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_D16), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_D17), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_D18), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_D19), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_VSYNC), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_HSYNC), - IMX_PINCTRL_PIN(MX51_PAD_CSI2_PIXCLK), - IMX_PINCTRL_PIN(MX51_PAD_I2C1_CLK), - IMX_PINCTRL_PIN(MX51_PAD_I2C1_DAT), - IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_TXD), - IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_RXD), - IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_CK), - IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_FS), - IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MOSI), - IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MISO), - IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS0), - IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS1), - IMX_PINCTRL_PIN(MX51_PAD_CSPI1_RDY), - IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SCLK), - IMX_PINCTRL_PIN(MX51_PAD_UART1_RXD), - IMX_PINCTRL_PIN(MX51_PAD_UART1_TXD), - IMX_PINCTRL_PIN(MX51_PAD_UART1_RTS), - IMX_PINCTRL_PIN(MX51_PAD_UART1_CTS), - IMX_PINCTRL_PIN(MX51_PAD_UART2_RXD), - IMX_PINCTRL_PIN(MX51_PAD_UART2_TXD), - IMX_PINCTRL_PIN(MX51_PAD_UART3_RXD), - IMX_PINCTRL_PIN(MX51_PAD_UART3_TXD), - IMX_PINCTRL_PIN(MX51_PAD_OWIRE_LINE), - IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX51_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX51_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX51_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4), - IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE7), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_NXT), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA0), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA1), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA2), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA3), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA4), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA5), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA6), - IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA7), - IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN11), - IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN12), - IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN13), - IMX_PINCTRL_PIN(MX51_PAD_DI1_D0_CS), - IMX_PINCTRL_PIN(MX51_PAD_DI1_D1_CS), - IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIN), - IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIO), - IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_CLK), - IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_RS), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT0), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT1), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT2), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT3), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT4), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT5), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT6), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT7), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT8), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT9), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT10), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT11), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT12), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT13), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT14), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT15), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT16), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT17), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT18), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT19), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT20), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT21), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT22), - IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23), - IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3), - IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE8), - IMX_PINCTRL_PIN(MX51_PAD_DI_GP2), - IMX_PINCTRL_PIN(MX51_PAD_DI_GP3), - IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4), - IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN2), - IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN3), - IMX_PINCTRL_PIN(MX51_PAD_DI2_DISP_CLK), - IMX_PINCTRL_PIN(MX51_PAD_DI_GP4), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT0), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT1), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT2), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT3), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT4), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT5), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT6), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT7), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT8), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT9), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT10), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT11), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT12), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT13), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT14), - IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT15), - IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0), - IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1), - IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2), - IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1), - IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0), - IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA1), - IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA2), - IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA3), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_2), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_3), - IMX_PINCTRL_PIN(MX51_PAD_PMIC_INT_REQ), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_4), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_5), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_6), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8), - IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE9), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE10), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE11), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE12), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE13), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE14), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE15), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE16), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE17), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE18), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE19), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE20), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE21), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE22), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE23), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE24), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE25), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE26), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE27), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE28), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE29), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE30), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE31), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE32), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE33), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE34), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE35), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE36), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE37), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE38), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE39), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE40), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE41), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE42), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE43), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE44), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE45), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE46), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE47), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE48), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE49), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE50), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE51), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE52), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE53), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE54), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE55), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE56), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE57), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE58), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE59), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE60), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE61), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE62), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE63), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE64), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE65), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE66), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE67), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE68), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE69), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE70), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE71), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE72), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE73), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE74), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE75), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE76), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE77), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE78), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE79), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE80), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE81), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE82), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE83), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE84), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE85), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE86), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE87), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE88), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE89), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE90), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE91), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE92), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE93), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE94), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE95), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE96), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE97), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE98), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE99), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE100), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE101), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE102), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE103), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE104), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE105), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE106), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE107), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE108), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE109), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE110), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE111), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE112), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE113), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE114), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE115), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE116), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE117), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE118), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE119), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE120), - IMX_PINCTRL_PIN(MX51_PAD_RESERVE121), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK), -}; - -static struct imx_pinctrl_soc_info imx51_pinctrl_info = { - .pins = imx51_pinctrl_pads, - .npins = ARRAY_SIZE(imx51_pinctrl_pads), -}; - -static const struct of_device_id imx51_pinctrl_of_match[] = { - { .compatible = "fsl,imx51-iomuxc", }, - { /* sentinel */ } -}; - -static int imx51_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx51_pinctrl_info); -} - -static struct platform_driver imx51_pinctrl_driver = { - .driver = { - .name = "imx51-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx51_pinctrl_of_match, - }, - .probe = imx51_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx51_pinctrl_init(void) -{ - return platform_driver_register(&imx51_pinctrl_driver); -} -arch_initcall(imx51_pinctrl_init); - -static void __exit imx51_pinctrl_exit(void) -{ - platform_driver_unregister(&imx51_pinctrl_driver); -} -module_exit(imx51_pinctrl_exit); -MODULE_AUTHOR("Dong Aisheng "); -MODULE_DESCRIPTION("Freescale IMX51 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c deleted file mode 100644 index 1884d53cf750..000000000000 --- a/drivers/pinctrl/pinctrl-imx53.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * imx53 pinctrl driver based on imx pinmux core - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro, Inc. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx53_pads { - MX53_PAD_RESERVE0 = 0, - MX53_PAD_RESERVE1 = 1, - MX53_PAD_RESERVE2 = 2, - MX53_PAD_RESERVE3 = 3, - MX53_PAD_RESERVE4 = 4, - MX53_PAD_RESERVE5 = 5, - MX53_PAD_RESERVE6 = 6, - MX53_PAD_RESERVE7 = 7, - MX53_PAD_GPIO_19 = 8, - MX53_PAD_KEY_COL0 = 9, - MX53_PAD_KEY_ROW0 = 10, - MX53_PAD_KEY_COL1 = 11, - MX53_PAD_KEY_ROW1 = 12, - MX53_PAD_KEY_COL2 = 13, - MX53_PAD_KEY_ROW2 = 14, - MX53_PAD_KEY_COL3 = 15, - MX53_PAD_KEY_ROW3 = 16, - MX53_PAD_KEY_COL4 = 17, - MX53_PAD_KEY_ROW4 = 18, - MX53_PAD_DI0_DISP_CLK = 19, - MX53_PAD_DI0_PIN15 = 20, - MX53_PAD_DI0_PIN2 = 21, - MX53_PAD_DI0_PIN3 = 22, - MX53_PAD_DI0_PIN4 = 23, - MX53_PAD_DISP0_DAT0 = 24, - MX53_PAD_DISP0_DAT1 = 25, - MX53_PAD_DISP0_DAT2 = 26, - MX53_PAD_DISP0_DAT3 = 27, - MX53_PAD_DISP0_DAT4 = 28, - MX53_PAD_DISP0_DAT5 = 29, - MX53_PAD_DISP0_DAT6 = 30, - MX53_PAD_DISP0_DAT7 = 31, - MX53_PAD_DISP0_DAT8 = 32, - MX53_PAD_DISP0_DAT9 = 33, - MX53_PAD_DISP0_DAT10 = 34, - MX53_PAD_DISP0_DAT11 = 35, - MX53_PAD_DISP0_DAT12 = 36, - MX53_PAD_DISP0_DAT13 = 37, - MX53_PAD_DISP0_DAT14 = 38, - MX53_PAD_DISP0_DAT15 = 39, - MX53_PAD_DISP0_DAT16 = 40, - MX53_PAD_DISP0_DAT17 = 41, - MX53_PAD_DISP0_DAT18 = 42, - MX53_PAD_DISP0_DAT19 = 43, - MX53_PAD_DISP0_DAT20 = 44, - MX53_PAD_DISP0_DAT21 = 45, - MX53_PAD_DISP0_DAT22 = 46, - MX53_PAD_DISP0_DAT23 = 47, - MX53_PAD_CSI0_PIXCLK = 48, - MX53_PAD_CSI0_MCLK = 49, - MX53_PAD_CSI0_DATA_EN = 50, - MX53_PAD_CSI0_VSYNC = 51, - MX53_PAD_CSI0_DAT4 = 52, - MX53_PAD_CSI0_DAT5 = 53, - MX53_PAD_CSI0_DAT6 = 54, - MX53_PAD_CSI0_DAT7 = 55, - MX53_PAD_CSI0_DAT8 = 56, - MX53_PAD_CSI0_DAT9 = 57, - MX53_PAD_CSI0_DAT10 = 58, - MX53_PAD_CSI0_DAT11 = 59, - MX53_PAD_CSI0_DAT12 = 60, - MX53_PAD_CSI0_DAT13 = 61, - MX53_PAD_CSI0_DAT14 = 62, - MX53_PAD_CSI0_DAT15 = 63, - MX53_PAD_CSI0_DAT16 = 64, - MX53_PAD_CSI0_DAT17 = 65, - MX53_PAD_CSI0_DAT18 = 66, - MX53_PAD_CSI0_DAT19 = 67, - MX53_PAD_EIM_A25 = 68, - MX53_PAD_EIM_EB2 = 69, - MX53_PAD_EIM_D16 = 70, - MX53_PAD_EIM_D17 = 71, - MX53_PAD_EIM_D18 = 72, - MX53_PAD_EIM_D19 = 73, - MX53_PAD_EIM_D20 = 74, - MX53_PAD_EIM_D21 = 75, - MX53_PAD_EIM_D22 = 76, - MX53_PAD_EIM_D23 = 77, - MX53_PAD_EIM_EB3 = 78, - MX53_PAD_EIM_D24 = 79, - MX53_PAD_EIM_D25 = 80, - MX53_PAD_EIM_D26 = 81, - MX53_PAD_EIM_D27 = 82, - MX53_PAD_EIM_D28 = 83, - MX53_PAD_EIM_D29 = 84, - MX53_PAD_EIM_D30 = 85, - MX53_PAD_EIM_D31 = 86, - MX53_PAD_EIM_A24 = 87, - MX53_PAD_EIM_A23 = 88, - MX53_PAD_EIM_A22 = 89, - MX53_PAD_EIM_A21 = 90, - MX53_PAD_EIM_A20 = 91, - MX53_PAD_EIM_A19 = 92, - MX53_PAD_EIM_A18 = 93, - MX53_PAD_EIM_A17 = 94, - MX53_PAD_EIM_A16 = 95, - MX53_PAD_EIM_CS0 = 96, - MX53_PAD_EIM_CS1 = 97, - MX53_PAD_EIM_OE = 98, - MX53_PAD_EIM_RW = 99, - MX53_PAD_EIM_LBA = 100, - MX53_PAD_EIM_EB0 = 101, - MX53_PAD_EIM_EB1 = 102, - MX53_PAD_EIM_DA0 = 103, - MX53_PAD_EIM_DA1 = 104, - MX53_PAD_EIM_DA2 = 105, - MX53_PAD_EIM_DA3 = 106, - MX53_PAD_EIM_DA4 = 107, - MX53_PAD_EIM_DA5 = 108, - MX53_PAD_EIM_DA6 = 109, - MX53_PAD_EIM_DA7 = 110, - MX53_PAD_EIM_DA8 = 111, - MX53_PAD_EIM_DA9 = 112, - MX53_PAD_EIM_DA10 = 113, - MX53_PAD_EIM_DA11 = 114, - MX53_PAD_EIM_DA12 = 115, - MX53_PAD_EIM_DA13 = 116, - MX53_PAD_EIM_DA14 = 117, - MX53_PAD_EIM_DA15 = 118, - MX53_PAD_NANDF_WE_B = 119, - MX53_PAD_NANDF_RE_B = 120, - MX53_PAD_EIM_WAIT = 121, - MX53_PAD_RESERVE8 = 122, - MX53_PAD_LVDS1_TX3_P = 123, - MX53_PAD_LVDS1_TX2_P = 124, - MX53_PAD_LVDS1_CLK_P = 125, - MX53_PAD_LVDS1_TX1_P = 126, - MX53_PAD_LVDS1_TX0_P = 127, - MX53_PAD_LVDS0_TX3_P = 128, - MX53_PAD_LVDS0_CLK_P = 129, - MX53_PAD_LVDS0_TX2_P = 130, - MX53_PAD_LVDS0_TX1_P = 131, - MX53_PAD_LVDS0_TX0_P = 132, - MX53_PAD_GPIO_10 = 133, - MX53_PAD_GPIO_11 = 134, - MX53_PAD_GPIO_12 = 135, - MX53_PAD_GPIO_13 = 136, - MX53_PAD_GPIO_14 = 137, - MX53_PAD_NANDF_CLE = 138, - MX53_PAD_NANDF_ALE = 139, - MX53_PAD_NANDF_WP_B = 140, - MX53_PAD_NANDF_RB0 = 141, - MX53_PAD_NANDF_CS0 = 142, - MX53_PAD_NANDF_CS1 = 143, - MX53_PAD_NANDF_CS2 = 144, - MX53_PAD_NANDF_CS3 = 145, - MX53_PAD_FEC_MDIO = 146, - MX53_PAD_FEC_REF_CLK = 147, - MX53_PAD_FEC_RX_ER = 148, - MX53_PAD_FEC_CRS_DV = 149, - MX53_PAD_FEC_RXD1 = 150, - MX53_PAD_FEC_RXD0 = 151, - MX53_PAD_FEC_TX_EN = 152, - MX53_PAD_FEC_TXD1 = 153, - MX53_PAD_FEC_TXD0 = 154, - MX53_PAD_FEC_MDC = 155, - MX53_PAD_PATA_DIOW = 156, - MX53_PAD_PATA_DMACK = 157, - MX53_PAD_PATA_DMARQ = 158, - MX53_PAD_PATA_BUFFER_EN = 159, - MX53_PAD_PATA_INTRQ = 160, - MX53_PAD_PATA_DIOR = 161, - MX53_PAD_PATA_RESET_B = 162, - MX53_PAD_PATA_IORDY = 163, - MX53_PAD_PATA_DA_0 = 164, - MX53_PAD_PATA_DA_1 = 165, - MX53_PAD_PATA_DA_2 = 166, - MX53_PAD_PATA_CS_0 = 167, - MX53_PAD_PATA_CS_1 = 168, - MX53_PAD_PATA_DATA0 = 169, - MX53_PAD_PATA_DATA1 = 170, - MX53_PAD_PATA_DATA2 = 171, - MX53_PAD_PATA_DATA3 = 172, - MX53_PAD_PATA_DATA4 = 173, - MX53_PAD_PATA_DATA5 = 174, - MX53_PAD_PATA_DATA6 = 175, - MX53_PAD_PATA_DATA7 = 176, - MX53_PAD_PATA_DATA8 = 177, - MX53_PAD_PATA_DATA9 = 178, - MX53_PAD_PATA_DATA10 = 179, - MX53_PAD_PATA_DATA11 = 180, - MX53_PAD_PATA_DATA12 = 181, - MX53_PAD_PATA_DATA13 = 182, - MX53_PAD_PATA_DATA14 = 183, - MX53_PAD_PATA_DATA15 = 184, - MX53_PAD_SD1_DATA0 = 185, - MX53_PAD_SD1_DATA1 = 186, - MX53_PAD_SD1_CMD = 187, - MX53_PAD_SD1_DATA2 = 188, - MX53_PAD_SD1_CLK = 189, - MX53_PAD_SD1_DATA3 = 190, - MX53_PAD_SD2_CLK = 191, - MX53_PAD_SD2_CMD = 192, - MX53_PAD_SD2_DATA3 = 193, - MX53_PAD_SD2_DATA2 = 194, - MX53_PAD_SD2_DATA1 = 195, - MX53_PAD_SD2_DATA0 = 196, - MX53_PAD_GPIO_0 = 197, - MX53_PAD_GPIO_1 = 198, - MX53_PAD_GPIO_9 = 199, - MX53_PAD_GPIO_3 = 200, - MX53_PAD_GPIO_6 = 201, - MX53_PAD_GPIO_2 = 202, - MX53_PAD_GPIO_4 = 203, - MX53_PAD_GPIO_5 = 204, - MX53_PAD_GPIO_7 = 205, - MX53_PAD_GPIO_8 = 206, - MX53_PAD_GPIO_16 = 207, - MX53_PAD_GPIO_17 = 208, - MX53_PAD_GPIO_18 = 209, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX53_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX53_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX53_PAD_RESERVE2), - IMX_PINCTRL_PIN(MX53_PAD_RESERVE3), - IMX_PINCTRL_PIN(MX53_PAD_RESERVE4), - IMX_PINCTRL_PIN(MX53_PAD_RESERVE5), - IMX_PINCTRL_PIN(MX53_PAD_RESERVE6), - IMX_PINCTRL_PIN(MX53_PAD_RESERVE7), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_19), - IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX53_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX53_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX53_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX53_PAD_KEY_COL4), - IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW4), - IMX_PINCTRL_PIN(MX53_PAD_DI0_DISP_CLK), - IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN15), - IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN2), - IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN3), - IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN4), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT0), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT1), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT2), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT3), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT4), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT5), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT6), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT7), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT8), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT9), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT10), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT11), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT12), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT13), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT14), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT15), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT16), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT17), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT18), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT19), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT20), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT21), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT22), - IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT23), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_PIXCLK), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_MCLK), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DATA_EN), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_VSYNC), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT4), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT5), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT6), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT7), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT8), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT9), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT10), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT11), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT12), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT13), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT14), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT15), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT16), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT17), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT18), - IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT19), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A25), - IMX_PINCTRL_PIN(MX53_PAD_EIM_EB2), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D16), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D17), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D18), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D19), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D20), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D21), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D22), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D23), - IMX_PINCTRL_PIN(MX53_PAD_EIM_EB3), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D24), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D25), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D26), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D27), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D28), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D29), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D30), - IMX_PINCTRL_PIN(MX53_PAD_EIM_D31), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A24), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A23), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A22), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A21), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A20), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A19), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A18), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A17), - IMX_PINCTRL_PIN(MX53_PAD_EIM_A16), - IMX_PINCTRL_PIN(MX53_PAD_EIM_CS0), - IMX_PINCTRL_PIN(MX53_PAD_EIM_CS1), - IMX_PINCTRL_PIN(MX53_PAD_EIM_OE), - IMX_PINCTRL_PIN(MX53_PAD_EIM_RW), - IMX_PINCTRL_PIN(MX53_PAD_EIM_LBA), - IMX_PINCTRL_PIN(MX53_PAD_EIM_EB0), - IMX_PINCTRL_PIN(MX53_PAD_EIM_EB1), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA0), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA1), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA2), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA3), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA4), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA5), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA6), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA7), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA8), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA9), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA10), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA11), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA12), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA13), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA14), - IMX_PINCTRL_PIN(MX53_PAD_EIM_DA15), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B), - IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT), - IMX_PINCTRL_PIN(MX53_PAD_RESERVE8), - IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX1_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX0_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX3_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS0_CLK_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX2_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX1_P), - IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX0_P), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_10), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_11), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_12), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_13), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_14), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_CLE), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_ALE), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_WP_B), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_RB0), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS0), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS1), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS2), - IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS3), - IMX_PINCTRL_PIN(MX53_PAD_FEC_MDIO), - IMX_PINCTRL_PIN(MX53_PAD_FEC_REF_CLK), - IMX_PINCTRL_PIN(MX53_PAD_FEC_RX_ER), - IMX_PINCTRL_PIN(MX53_PAD_FEC_CRS_DV), - IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD1), - IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD0), - IMX_PINCTRL_PIN(MX53_PAD_FEC_TX_EN), - IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD1), - IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD0), - IMX_PINCTRL_PIN(MX53_PAD_FEC_MDC), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOW), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DMACK), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DMARQ), - IMX_PINCTRL_PIN(MX53_PAD_PATA_BUFFER_EN), - IMX_PINCTRL_PIN(MX53_PAD_PATA_INTRQ), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOR), - IMX_PINCTRL_PIN(MX53_PAD_PATA_RESET_B), - IMX_PINCTRL_PIN(MX53_PAD_PATA_IORDY), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_0), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_1), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_2), - IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_0), - IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_1), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA0), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA1), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA2), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA3), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA4), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA5), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA6), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA7), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA8), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA9), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA10), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA11), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA12), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA13), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA14), - IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA15), - IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA0), - IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA1), - IMX_PINCTRL_PIN(MX53_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA2), - IMX_PINCTRL_PIN(MX53_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA3), - IMX_PINCTRL_PIN(MX53_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX53_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA3), - IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA2), - IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA1), - IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA0), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_0), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_1), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_9), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_3), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_6), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_2), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_4), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_5), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_7), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_8), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_16), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_17), - IMX_PINCTRL_PIN(MX53_PAD_GPIO_18), -}; - -static struct imx_pinctrl_soc_info imx53_pinctrl_info = { - .pins = imx53_pinctrl_pads, - .npins = ARRAY_SIZE(imx53_pinctrl_pads), -}; - -static const struct of_device_id imx53_pinctrl_of_match[] = { - { .compatible = "fsl,imx53-iomuxc", }, - { /* sentinel */ } -}; - -static int imx53_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx53_pinctrl_info); -} - -static struct platform_driver imx53_pinctrl_driver = { - .driver = { - .name = "imx53-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx53_pinctrl_of_match, - }, - .probe = imx53_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx53_pinctrl_init(void) -{ - return platform_driver_register(&imx53_pinctrl_driver); -} -arch_initcall(imx53_pinctrl_init); - -static void __exit imx53_pinctrl_exit(void) -{ - platform_driver_unregister(&imx53_pinctrl_driver); -} -module_exit(imx53_pinctrl_exit); -MODULE_AUTHOR("Dong Aisheng "); -MODULE_DESCRIPTION("Freescale IMX53 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/pinctrl-imx6dl.c deleted file mode 100644 index 656c4b08cc2e..000000000000 --- a/drivers/pinctrl/pinctrl-imx6dl.c +++ /dev/null @@ -1,497 +0,0 @@ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx6dl_pads { - MX6DL_PAD_RESERVE0 = 0, - MX6DL_PAD_RESERVE1 = 1, - MX6DL_PAD_RESERVE2 = 2, - MX6DL_PAD_RESERVE3 = 3, - MX6DL_PAD_RESERVE4 = 4, - MX6DL_PAD_RESERVE5 = 5, - MX6DL_PAD_RESERVE6 = 6, - MX6DL_PAD_RESERVE7 = 7, - MX6DL_PAD_RESERVE8 = 8, - MX6DL_PAD_RESERVE9 = 9, - MX6DL_PAD_RESERVE10 = 10, - MX6DL_PAD_RESERVE11 = 11, - MX6DL_PAD_RESERVE12 = 12, - MX6DL_PAD_RESERVE13 = 13, - MX6DL_PAD_RESERVE14 = 14, - MX6DL_PAD_RESERVE15 = 15, - MX6DL_PAD_RESERVE16 = 16, - MX6DL_PAD_RESERVE17 = 17, - MX6DL_PAD_RESERVE18 = 18, - MX6DL_PAD_CSI0_DAT10 = 19, - MX6DL_PAD_CSI0_DAT11 = 20, - MX6DL_PAD_CSI0_DAT12 = 21, - MX6DL_PAD_CSI0_DAT13 = 22, - MX6DL_PAD_CSI0_DAT14 = 23, - MX6DL_PAD_CSI0_DAT15 = 24, - MX6DL_PAD_CSI0_DAT16 = 25, - MX6DL_PAD_CSI0_DAT17 = 26, - MX6DL_PAD_CSI0_DAT18 = 27, - MX6DL_PAD_CSI0_DAT19 = 28, - MX6DL_PAD_CSI0_DAT4 = 29, - MX6DL_PAD_CSI0_DAT5 = 30, - MX6DL_PAD_CSI0_DAT6 = 31, - MX6DL_PAD_CSI0_DAT7 = 32, - MX6DL_PAD_CSI0_DAT8 = 33, - MX6DL_PAD_CSI0_DAT9 = 34, - MX6DL_PAD_CSI0_DATA_EN = 35, - MX6DL_PAD_CSI0_MCLK = 36, - MX6DL_PAD_CSI0_PIXCLK = 37, - MX6DL_PAD_CSI0_VSYNC = 38, - MX6DL_PAD_DI0_DISP_CLK = 39, - MX6DL_PAD_DI0_PIN15 = 40, - MX6DL_PAD_DI0_PIN2 = 41, - MX6DL_PAD_DI0_PIN3 = 42, - MX6DL_PAD_DI0_PIN4 = 43, - MX6DL_PAD_DISP0_DAT0 = 44, - MX6DL_PAD_DISP0_DAT1 = 45, - MX6DL_PAD_DISP0_DAT10 = 46, - MX6DL_PAD_DISP0_DAT11 = 47, - MX6DL_PAD_DISP0_DAT12 = 48, - MX6DL_PAD_DISP0_DAT13 = 49, - MX6DL_PAD_DISP0_DAT14 = 50, - MX6DL_PAD_DISP0_DAT15 = 51, - MX6DL_PAD_DISP0_DAT16 = 52, - MX6DL_PAD_DISP0_DAT17 = 53, - MX6DL_PAD_DISP0_DAT18 = 54, - MX6DL_PAD_DISP0_DAT19 = 55, - MX6DL_PAD_DISP0_DAT2 = 56, - MX6DL_PAD_DISP0_DAT20 = 57, - MX6DL_PAD_DISP0_DAT21 = 58, - MX6DL_PAD_DISP0_DAT22 = 59, - MX6DL_PAD_DISP0_DAT23 = 60, - MX6DL_PAD_DISP0_DAT3 = 61, - MX6DL_PAD_DISP0_DAT4 = 62, - MX6DL_PAD_DISP0_DAT5 = 63, - MX6DL_PAD_DISP0_DAT6 = 64, - MX6DL_PAD_DISP0_DAT7 = 65, - MX6DL_PAD_DISP0_DAT8 = 66, - MX6DL_PAD_DISP0_DAT9 = 67, - MX6DL_PAD_EIM_A16 = 68, - MX6DL_PAD_EIM_A17 = 69, - MX6DL_PAD_EIM_A18 = 70, - MX6DL_PAD_EIM_A19 = 71, - MX6DL_PAD_EIM_A20 = 72, - MX6DL_PAD_EIM_A21 = 73, - MX6DL_PAD_EIM_A22 = 74, - MX6DL_PAD_EIM_A23 = 75, - MX6DL_PAD_EIM_A24 = 76, - MX6DL_PAD_EIM_A25 = 77, - MX6DL_PAD_EIM_BCLK = 78, - MX6DL_PAD_EIM_CS0 = 79, - MX6DL_PAD_EIM_CS1 = 80, - MX6DL_PAD_EIM_D16 = 81, - MX6DL_PAD_EIM_D17 = 82, - MX6DL_PAD_EIM_D18 = 83, - MX6DL_PAD_EIM_D19 = 84, - MX6DL_PAD_EIM_D20 = 85, - MX6DL_PAD_EIM_D21 = 86, - MX6DL_PAD_EIM_D22 = 87, - MX6DL_PAD_EIM_D23 = 88, - MX6DL_PAD_EIM_D24 = 89, - MX6DL_PAD_EIM_D25 = 90, - MX6DL_PAD_EIM_D26 = 91, - MX6DL_PAD_EIM_D27 = 92, - MX6DL_PAD_EIM_D28 = 93, - MX6DL_PAD_EIM_D29 = 94, - MX6DL_PAD_EIM_D30 = 95, - MX6DL_PAD_EIM_D31 = 96, - MX6DL_PAD_EIM_DA0 = 97, - MX6DL_PAD_EIM_DA1 = 98, - MX6DL_PAD_EIM_DA10 = 99, - MX6DL_PAD_EIM_DA11 = 100, - MX6DL_PAD_EIM_DA12 = 101, - MX6DL_PAD_EIM_DA13 = 102, - MX6DL_PAD_EIM_DA14 = 103, - MX6DL_PAD_EIM_DA15 = 104, - MX6DL_PAD_EIM_DA2 = 105, - MX6DL_PAD_EIM_DA3 = 106, - MX6DL_PAD_EIM_DA4 = 107, - MX6DL_PAD_EIM_DA5 = 108, - MX6DL_PAD_EIM_DA6 = 109, - MX6DL_PAD_EIM_DA7 = 110, - MX6DL_PAD_EIM_DA8 = 111, - MX6DL_PAD_EIM_DA9 = 112, - MX6DL_PAD_EIM_EB0 = 113, - MX6DL_PAD_EIM_EB1 = 114, - MX6DL_PAD_EIM_EB2 = 115, - MX6DL_PAD_EIM_EB3 = 116, - MX6DL_PAD_EIM_LBA = 117, - MX6DL_PAD_EIM_OE = 118, - MX6DL_PAD_EIM_RW = 119, - MX6DL_PAD_EIM_WAIT = 120, - MX6DL_PAD_ENET_CRS_DV = 121, - MX6DL_PAD_ENET_MDC = 122, - MX6DL_PAD_ENET_MDIO = 123, - MX6DL_PAD_ENET_REF_CLK = 124, - MX6DL_PAD_ENET_RX_ER = 125, - MX6DL_PAD_ENET_RXD0 = 126, - MX6DL_PAD_ENET_RXD1 = 127, - MX6DL_PAD_ENET_TX_EN = 128, - MX6DL_PAD_ENET_TXD0 = 129, - MX6DL_PAD_ENET_TXD1 = 130, - MX6DL_PAD_GPIO_0 = 131, - MX6DL_PAD_GPIO_1 = 132, - MX6DL_PAD_GPIO_16 = 133, - MX6DL_PAD_GPIO_17 = 134, - MX6DL_PAD_GPIO_18 = 135, - MX6DL_PAD_GPIO_19 = 136, - MX6DL_PAD_GPIO_2 = 137, - MX6DL_PAD_GPIO_3 = 138, - MX6DL_PAD_GPIO_4 = 139, - MX6DL_PAD_GPIO_5 = 140, - MX6DL_PAD_GPIO_6 = 141, - MX6DL_PAD_GPIO_7 = 142, - MX6DL_PAD_GPIO_8 = 143, - MX6DL_PAD_GPIO_9 = 144, - MX6DL_PAD_KEY_COL0 = 145, - MX6DL_PAD_KEY_COL1 = 146, - MX6DL_PAD_KEY_COL2 = 147, - MX6DL_PAD_KEY_COL3 = 148, - MX6DL_PAD_KEY_COL4 = 149, - MX6DL_PAD_KEY_ROW0 = 150, - MX6DL_PAD_KEY_ROW1 = 151, - MX6DL_PAD_KEY_ROW2 = 152, - MX6DL_PAD_KEY_ROW3 = 153, - MX6DL_PAD_KEY_ROW4 = 154, - MX6DL_PAD_NANDF_ALE = 155, - MX6DL_PAD_NANDF_CLE = 156, - MX6DL_PAD_NANDF_CS0 = 157, - MX6DL_PAD_NANDF_CS1 = 158, - MX6DL_PAD_NANDF_CS2 = 159, - MX6DL_PAD_NANDF_CS3 = 160, - MX6DL_PAD_NANDF_D0 = 161, - MX6DL_PAD_NANDF_D1 = 162, - MX6DL_PAD_NANDF_D2 = 163, - MX6DL_PAD_NANDF_D3 = 164, - MX6DL_PAD_NANDF_D4 = 165, - MX6DL_PAD_NANDF_D5 = 166, - MX6DL_PAD_NANDF_D6 = 167, - MX6DL_PAD_NANDF_D7 = 168, - MX6DL_PAD_NANDF_RB0 = 169, - MX6DL_PAD_NANDF_WP_B = 170, - MX6DL_PAD_RGMII_RD0 = 171, - MX6DL_PAD_RGMII_RD1 = 172, - MX6DL_PAD_RGMII_RD2 = 173, - MX6DL_PAD_RGMII_RD3 = 174, - MX6DL_PAD_RGMII_RX_CTL = 175, - MX6DL_PAD_RGMII_RXC = 176, - MX6DL_PAD_RGMII_TD0 = 177, - MX6DL_PAD_RGMII_TD1 = 178, - MX6DL_PAD_RGMII_TD2 = 179, - MX6DL_PAD_RGMII_TD3 = 180, - MX6DL_PAD_RGMII_TX_CTL = 181, - MX6DL_PAD_RGMII_TXC = 182, - MX6DL_PAD_SD1_CLK = 183, - MX6DL_PAD_SD1_CMD = 184, - MX6DL_PAD_SD1_DAT0 = 185, - MX6DL_PAD_SD1_DAT1 = 186, - MX6DL_PAD_SD1_DAT2 = 187, - MX6DL_PAD_SD1_DAT3 = 188, - MX6DL_PAD_SD2_CLK = 189, - MX6DL_PAD_SD2_CMD = 190, - MX6DL_PAD_SD2_DAT0 = 191, - MX6DL_PAD_SD2_DAT1 = 192, - MX6DL_PAD_SD2_DAT2 = 193, - MX6DL_PAD_SD2_DAT3 = 194, - MX6DL_PAD_SD3_CLK = 195, - MX6DL_PAD_SD3_CMD = 196, - MX6DL_PAD_SD3_DAT0 = 197, - MX6DL_PAD_SD3_DAT1 = 198, - MX6DL_PAD_SD3_DAT2 = 199, - MX6DL_PAD_SD3_DAT3 = 200, - MX6DL_PAD_SD3_DAT4 = 201, - MX6DL_PAD_SD3_DAT5 = 202, - MX6DL_PAD_SD3_DAT6 = 203, - MX6DL_PAD_SD3_DAT7 = 204, - MX6DL_PAD_SD3_RST = 205, - MX6DL_PAD_SD4_CLK = 206, - MX6DL_PAD_SD4_CMD = 207, - MX6DL_PAD_SD4_DAT0 = 208, - MX6DL_PAD_SD4_DAT1 = 209, - MX6DL_PAD_SD4_DAT2 = 210, - MX6DL_PAD_SD4_DAT3 = 211, - MX6DL_PAD_SD4_DAT4 = 212, - MX6DL_PAD_SD4_DAT5 = 213, - MX6DL_PAD_SD4_DAT6 = 214, - MX6DL_PAD_SD4_DAT7 = 215, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE16), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE17), - IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE18), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT10), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT11), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT12), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT13), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT14), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT15), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT16), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT17), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT18), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT19), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT4), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT5), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT6), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT7), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT8), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT9), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DATA_EN), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_MCLK), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_PIXCLK), - IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_VSYNC), - IMX_PINCTRL_PIN(MX6DL_PAD_DI0_DISP_CLK), - IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN15), - IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN2), - IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN3), - IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN4), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT0), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT1), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT10), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT11), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT12), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT13), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT14), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT15), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT16), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT17), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT18), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT19), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT2), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT20), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT21), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT22), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT23), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT3), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT4), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT5), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT6), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT7), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT8), - IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT9), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A16), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A17), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A18), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A19), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A20), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A21), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A22), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A23), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A24), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A25), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_BCLK), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS0), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS1), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D16), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D17), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D18), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D19), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D20), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D21), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D22), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D23), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D24), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D25), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D26), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D27), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D28), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D29), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D30), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D31), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA0), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA1), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA10), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA11), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA12), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA13), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA14), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA15), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA2), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA3), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA4), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA5), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA6), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA7), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA8), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA9), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB0), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB1), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB2), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB3), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_LBA), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_OE), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_RW), - IMX_PINCTRL_PIN(MX6DL_PAD_EIM_WAIT), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_CRS_DV), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDC), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDIO), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_REF_CLK), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RX_ER), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD0), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD1), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TX_EN), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD0), - IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD1), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_0), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_1), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_16), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_17), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_18), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_19), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_2), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_3), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_4), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_5), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_6), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_7), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_8), - IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_9), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL4), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW4), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_ALE), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CLE), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS0), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS1), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS2), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS3), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D0), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D1), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D2), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D3), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D4), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D5), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D6), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D7), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_RB0), - IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_WP_B), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD0), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD1), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD2), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD3), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RX_CTL), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RXC), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD0), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD1), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD2), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD3), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TX_CTL), - IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TXC), - IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT0), - IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT1), - IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT2), - IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT3), - IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT0), - IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT1), - IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT2), - IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT3), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CLK), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CMD), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT0), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT1), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT2), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT3), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT4), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT5), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT6), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT7), - IMX_PINCTRL_PIN(MX6DL_PAD_SD3_RST), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CLK), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CMD), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT0), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT1), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT2), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT3), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT4), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6), - IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7), -}; - -static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = { - .pins = imx6dl_pinctrl_pads, - .npins = ARRAY_SIZE(imx6dl_pinctrl_pads), -}; - -static const struct of_device_id imx6dl_pinctrl_of_match[] = { - { .compatible = "fsl,imx6dl-iomuxc", }, - { /* sentinel */ } -}; - -static int imx6dl_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx6dl_pinctrl_info); -} - -static struct platform_driver imx6dl_pinctrl_driver = { - .driver = { - .name = "imx6dl-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx6dl_pinctrl_of_match, - }, - .probe = imx6dl_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx6dl_pinctrl_init(void) -{ - return platform_driver_register(&imx6dl_pinctrl_driver); -} -arch_initcall(imx6dl_pinctrl_init); - -static void __exit imx6dl_pinctrl_exit(void) -{ - platform_driver_unregister(&imx6dl_pinctrl_driver); -} -module_exit(imx6dl_pinctrl_exit); - -MODULE_AUTHOR("Shawn Guo "); -MODULE_DESCRIPTION("Freescale imx6dl pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c deleted file mode 100644 index 59bb5b4ec0f6..000000000000 --- a/drivers/pinctrl/pinctrl-imx6q.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * imx6q pinctrl driver based on imx pinmux core - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro, Inc. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx6q_pads { - MX6Q_PAD_RESERVE0 = 0, - MX6Q_PAD_RESERVE1 = 1, - MX6Q_PAD_RESERVE2 = 2, - MX6Q_PAD_RESERVE3 = 3, - MX6Q_PAD_RESERVE4 = 4, - MX6Q_PAD_RESERVE5 = 5, - MX6Q_PAD_RESERVE6 = 6, - MX6Q_PAD_RESERVE7 = 7, - MX6Q_PAD_RESERVE8 = 8, - MX6Q_PAD_RESERVE9 = 9, - MX6Q_PAD_RESERVE10 = 10, - MX6Q_PAD_RESERVE11 = 11, - MX6Q_PAD_RESERVE12 = 12, - MX6Q_PAD_RESERVE13 = 13, - MX6Q_PAD_RESERVE14 = 14, - MX6Q_PAD_RESERVE15 = 15, - MX6Q_PAD_RESERVE16 = 16, - MX6Q_PAD_RESERVE17 = 17, - MX6Q_PAD_RESERVE18 = 18, - MX6Q_PAD_SD2_DAT1 = 19, - MX6Q_PAD_SD2_DAT2 = 20, - MX6Q_PAD_SD2_DAT0 = 21, - MX6Q_PAD_RGMII_TXC = 22, - MX6Q_PAD_RGMII_TD0 = 23, - MX6Q_PAD_RGMII_TD1 = 24, - MX6Q_PAD_RGMII_TD2 = 25, - MX6Q_PAD_RGMII_TD3 = 26, - MX6Q_PAD_RGMII_RX_CTL = 27, - MX6Q_PAD_RGMII_RD0 = 28, - MX6Q_PAD_RGMII_TX_CTL = 29, - MX6Q_PAD_RGMII_RD1 = 30, - MX6Q_PAD_RGMII_RD2 = 31, - MX6Q_PAD_RGMII_RD3 = 32, - MX6Q_PAD_RGMII_RXC = 33, - MX6Q_PAD_EIM_A25 = 34, - MX6Q_PAD_EIM_EB2 = 35, - MX6Q_PAD_EIM_D16 = 36, - MX6Q_PAD_EIM_D17 = 37, - MX6Q_PAD_EIM_D18 = 38, - MX6Q_PAD_EIM_D19 = 39, - MX6Q_PAD_EIM_D20 = 40, - MX6Q_PAD_EIM_D21 = 41, - MX6Q_PAD_EIM_D22 = 42, - MX6Q_PAD_EIM_D23 = 43, - MX6Q_PAD_EIM_EB3 = 44, - MX6Q_PAD_EIM_D24 = 45, - MX6Q_PAD_EIM_D25 = 46, - MX6Q_PAD_EIM_D26 = 47, - MX6Q_PAD_EIM_D27 = 48, - MX6Q_PAD_EIM_D28 = 49, - MX6Q_PAD_EIM_D29 = 50, - MX6Q_PAD_EIM_D30 = 51, - MX6Q_PAD_EIM_D31 = 52, - MX6Q_PAD_EIM_A24 = 53, - MX6Q_PAD_EIM_A23 = 54, - MX6Q_PAD_EIM_A22 = 55, - MX6Q_PAD_EIM_A21 = 56, - MX6Q_PAD_EIM_A20 = 57, - MX6Q_PAD_EIM_A19 = 58, - MX6Q_PAD_EIM_A18 = 59, - MX6Q_PAD_EIM_A17 = 60, - MX6Q_PAD_EIM_A16 = 61, - MX6Q_PAD_EIM_CS0 = 62, - MX6Q_PAD_EIM_CS1 = 63, - MX6Q_PAD_EIM_OE = 64, - MX6Q_PAD_EIM_RW = 65, - MX6Q_PAD_EIM_LBA = 66, - MX6Q_PAD_EIM_EB0 = 67, - MX6Q_PAD_EIM_EB1 = 68, - MX6Q_PAD_EIM_DA0 = 69, - MX6Q_PAD_EIM_DA1 = 70, - MX6Q_PAD_EIM_DA2 = 71, - MX6Q_PAD_EIM_DA3 = 72, - MX6Q_PAD_EIM_DA4 = 73, - MX6Q_PAD_EIM_DA5 = 74, - MX6Q_PAD_EIM_DA6 = 75, - MX6Q_PAD_EIM_DA7 = 76, - MX6Q_PAD_EIM_DA8 = 77, - MX6Q_PAD_EIM_DA9 = 78, - MX6Q_PAD_EIM_DA10 = 79, - MX6Q_PAD_EIM_DA11 = 80, - MX6Q_PAD_EIM_DA12 = 81, - MX6Q_PAD_EIM_DA13 = 82, - MX6Q_PAD_EIM_DA14 = 83, - MX6Q_PAD_EIM_DA15 = 84, - MX6Q_PAD_EIM_WAIT = 85, - MX6Q_PAD_EIM_BCLK = 86, - MX6Q_PAD_DI0_DISP_CLK = 87, - MX6Q_PAD_DI0_PIN15 = 88, - MX6Q_PAD_DI0_PIN2 = 89, - MX6Q_PAD_DI0_PIN3 = 90, - MX6Q_PAD_DI0_PIN4 = 91, - MX6Q_PAD_DISP0_DAT0 = 92, - MX6Q_PAD_DISP0_DAT1 = 93, - MX6Q_PAD_DISP0_DAT2 = 94, - MX6Q_PAD_DISP0_DAT3 = 95, - MX6Q_PAD_DISP0_DAT4 = 96, - MX6Q_PAD_DISP0_DAT5 = 97, - MX6Q_PAD_DISP0_DAT6 = 98, - MX6Q_PAD_DISP0_DAT7 = 99, - MX6Q_PAD_DISP0_DAT8 = 100, - MX6Q_PAD_DISP0_DAT9 = 101, - MX6Q_PAD_DISP0_DAT10 = 102, - MX6Q_PAD_DISP0_DAT11 = 103, - MX6Q_PAD_DISP0_DAT12 = 104, - MX6Q_PAD_DISP0_DAT13 = 105, - MX6Q_PAD_DISP0_DAT14 = 106, - MX6Q_PAD_DISP0_DAT15 = 107, - MX6Q_PAD_DISP0_DAT16 = 108, - MX6Q_PAD_DISP0_DAT17 = 109, - MX6Q_PAD_DISP0_DAT18 = 110, - MX6Q_PAD_DISP0_DAT19 = 111, - MX6Q_PAD_DISP0_DAT20 = 112, - MX6Q_PAD_DISP0_DAT21 = 113, - MX6Q_PAD_DISP0_DAT22 = 114, - MX6Q_PAD_DISP0_DAT23 = 115, - MX6Q_PAD_ENET_MDIO = 116, - MX6Q_PAD_ENET_REF_CLK = 117, - MX6Q_PAD_ENET_RX_ER = 118, - MX6Q_PAD_ENET_CRS_DV = 119, - MX6Q_PAD_ENET_RXD1 = 120, - MX6Q_PAD_ENET_RXD0 = 121, - MX6Q_PAD_ENET_TX_EN = 122, - MX6Q_PAD_ENET_TXD1 = 123, - MX6Q_PAD_ENET_TXD0 = 124, - MX6Q_PAD_ENET_MDC = 125, - MX6Q_PAD_KEY_COL0 = 126, - MX6Q_PAD_KEY_ROW0 = 127, - MX6Q_PAD_KEY_COL1 = 128, - MX6Q_PAD_KEY_ROW1 = 129, - MX6Q_PAD_KEY_COL2 = 130, - MX6Q_PAD_KEY_ROW2 = 131, - MX6Q_PAD_KEY_COL3 = 132, - MX6Q_PAD_KEY_ROW3 = 133, - MX6Q_PAD_KEY_COL4 = 134, - MX6Q_PAD_KEY_ROW4 = 135, - MX6Q_PAD_GPIO_0 = 136, - MX6Q_PAD_GPIO_1 = 137, - MX6Q_PAD_GPIO_9 = 138, - MX6Q_PAD_GPIO_3 = 139, - MX6Q_PAD_GPIO_6 = 140, - MX6Q_PAD_GPIO_2 = 141, - MX6Q_PAD_GPIO_4 = 142, - MX6Q_PAD_GPIO_5 = 143, - MX6Q_PAD_GPIO_7 = 144, - MX6Q_PAD_GPIO_8 = 145, - MX6Q_PAD_GPIO_16 = 146, - MX6Q_PAD_GPIO_17 = 147, - MX6Q_PAD_GPIO_18 = 148, - MX6Q_PAD_GPIO_19 = 149, - MX6Q_PAD_CSI0_PIXCLK = 150, - MX6Q_PAD_CSI0_MCLK = 151, - MX6Q_PAD_CSI0_DATA_EN = 152, - MX6Q_PAD_CSI0_VSYNC = 153, - MX6Q_PAD_CSI0_DAT4 = 154, - MX6Q_PAD_CSI0_DAT5 = 155, - MX6Q_PAD_CSI0_DAT6 = 156, - MX6Q_PAD_CSI0_DAT7 = 157, - MX6Q_PAD_CSI0_DAT8 = 158, - MX6Q_PAD_CSI0_DAT9 = 159, - MX6Q_PAD_CSI0_DAT10 = 160, - MX6Q_PAD_CSI0_DAT11 = 161, - MX6Q_PAD_CSI0_DAT12 = 162, - MX6Q_PAD_CSI0_DAT13 = 163, - MX6Q_PAD_CSI0_DAT14 = 164, - MX6Q_PAD_CSI0_DAT15 = 165, - MX6Q_PAD_CSI0_DAT16 = 166, - MX6Q_PAD_CSI0_DAT17 = 167, - MX6Q_PAD_CSI0_DAT18 = 168, - MX6Q_PAD_CSI0_DAT19 = 169, - MX6Q_PAD_SD3_DAT7 = 170, - MX6Q_PAD_SD3_DAT6 = 171, - MX6Q_PAD_SD3_DAT5 = 172, - MX6Q_PAD_SD3_DAT4 = 173, - MX6Q_PAD_SD3_CMD = 174, - MX6Q_PAD_SD3_CLK = 175, - MX6Q_PAD_SD3_DAT0 = 176, - MX6Q_PAD_SD3_DAT1 = 177, - MX6Q_PAD_SD3_DAT2 = 178, - MX6Q_PAD_SD3_DAT3 = 179, - MX6Q_PAD_SD3_RST = 180, - MX6Q_PAD_NANDF_CLE = 181, - MX6Q_PAD_NANDF_ALE = 182, - MX6Q_PAD_NANDF_WP_B = 183, - MX6Q_PAD_NANDF_RB0 = 184, - MX6Q_PAD_NANDF_CS0 = 185, - MX6Q_PAD_NANDF_CS1 = 186, - MX6Q_PAD_NANDF_CS2 = 187, - MX6Q_PAD_NANDF_CS3 = 188, - MX6Q_PAD_SD4_CMD = 189, - MX6Q_PAD_SD4_CLK = 190, - MX6Q_PAD_NANDF_D0 = 191, - MX6Q_PAD_NANDF_D1 = 192, - MX6Q_PAD_NANDF_D2 = 193, - MX6Q_PAD_NANDF_D3 = 194, - MX6Q_PAD_NANDF_D4 = 195, - MX6Q_PAD_NANDF_D5 = 196, - MX6Q_PAD_NANDF_D6 = 197, - MX6Q_PAD_NANDF_D7 = 198, - MX6Q_PAD_SD4_DAT0 = 199, - MX6Q_PAD_SD4_DAT1 = 200, - MX6Q_PAD_SD4_DAT2 = 201, - MX6Q_PAD_SD4_DAT3 = 202, - MX6Q_PAD_SD4_DAT4 = 203, - MX6Q_PAD_SD4_DAT5 = 204, - MX6Q_PAD_SD4_DAT6 = 205, - MX6Q_PAD_SD4_DAT7 = 206, - MX6Q_PAD_SD1_DAT1 = 207, - MX6Q_PAD_SD1_DAT0 = 208, - MX6Q_PAD_SD1_DAT3 = 209, - MX6Q_PAD_SD1_CMD = 210, - MX6Q_PAD_SD1_DAT2 = 211, - MX6Q_PAD_SD1_CLK = 212, - MX6Q_PAD_SD2_CLK = 213, - MX6Q_PAD_SD2_CMD = 214, - MX6Q_PAD_SD2_DAT3 = 215, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17), - IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3), -}; - -static struct imx_pinctrl_soc_info imx6q_pinctrl_info = { - .pins = imx6q_pinctrl_pads, - .npins = ARRAY_SIZE(imx6q_pinctrl_pads), -}; - -static const struct of_device_id imx6q_pinctrl_of_match[] = { - { .compatible = "fsl,imx6q-iomuxc", }, - { /* sentinel */ } -}; - -static int imx6q_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info); -} - -static struct platform_driver imx6q_pinctrl_driver = { - .driver = { - .name = "imx6q-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx6q_pinctrl_of_match, - }, - .probe = imx6q_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx6q_pinctrl_init(void) -{ - return platform_driver_register(&imx6q_pinctrl_driver); -} -arch_initcall(imx6q_pinctrl_init); - -static void __exit imx6q_pinctrl_exit(void) -{ - platform_driver_unregister(&imx6q_pinctrl_driver); -} -module_exit(imx6q_pinctrl_exit); -MODULE_AUTHOR("Dong Aisheng "); -MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/pinctrl-imx6sl.c deleted file mode 100644 index e0924bd7b98c..000000000000 --- a/drivers/pinctrl/pinctrl-imx6sl.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx6sl_pads { - MX6SL_PAD_RESERVE0 = 0, - MX6SL_PAD_RESERVE1 = 1, - MX6SL_PAD_RESERVE2 = 2, - MX6SL_PAD_RESERVE3 = 3, - MX6SL_PAD_RESERVE4 = 4, - MX6SL_PAD_RESERVE5 = 5, - MX6SL_PAD_RESERVE6 = 6, - MX6SL_PAD_RESERVE7 = 7, - MX6SL_PAD_RESERVE8 = 8, - MX6SL_PAD_RESERVE9 = 9, - MX6SL_PAD_RESERVE10 = 10, - MX6SL_PAD_RESERVE11 = 11, - MX6SL_PAD_RESERVE12 = 12, - MX6SL_PAD_RESERVE13 = 13, - MX6SL_PAD_RESERVE14 = 14, - MX6SL_PAD_RESERVE15 = 15, - MX6SL_PAD_RESERVE16 = 16, - MX6SL_PAD_RESERVE17 = 17, - MX6SL_PAD_RESERVE18 = 18, - MX6SL_PAD_AUD_MCLK = 19, - MX6SL_PAD_AUD_RXC = 20, - MX6SL_PAD_AUD_RXD = 21, - MX6SL_PAD_AUD_RXFS = 22, - MX6SL_PAD_AUD_TXC = 23, - MX6SL_PAD_AUD_TXD = 24, - MX6SL_PAD_AUD_TXFS = 25, - MX6SL_PAD_ECSPI1_MISO = 26, - MX6SL_PAD_ECSPI1_MOSI = 27, - MX6SL_PAD_ECSPI1_SCLK = 28, - MX6SL_PAD_ECSPI1_SS0 = 29, - MX6SL_PAD_ECSPI2_MISO = 30, - MX6SL_PAD_ECSPI2_MOSI = 31, - MX6SL_PAD_ECSPI2_SCLK = 32, - MX6SL_PAD_ECSPI2_SS0 = 33, - MX6SL_PAD_EPDC_BDR0 = 34, - MX6SL_PAD_EPDC_BDR1 = 35, - MX6SL_PAD_EPDC_D0 = 36, - MX6SL_PAD_EPDC_D1 = 37, - MX6SL_PAD_EPDC_D10 = 38, - MX6SL_PAD_EPDC_D11 = 39, - MX6SL_PAD_EPDC_D12 = 40, - MX6SL_PAD_EPDC_D13 = 41, - MX6SL_PAD_EPDC_D14 = 42, - MX6SL_PAD_EPDC_D15 = 43, - MX6SL_PAD_EPDC_D2 = 44, - MX6SL_PAD_EPDC_D3 = 45, - MX6SL_PAD_EPDC_D4 = 46, - MX6SL_PAD_EPDC_D5 = 47, - MX6SL_PAD_EPDC_D6 = 48, - MX6SL_PAD_EPDC_D7 = 49, - MX6SL_PAD_EPDC_D8 = 50, - MX6SL_PAD_EPDC_D9 = 51, - MX6SL_PAD_EPDC_GDCLK = 52, - MX6SL_PAD_EPDC_GDOE = 53, - MX6SL_PAD_EPDC_GDRL = 54, - MX6SL_PAD_EPDC_GDSP = 55, - MX6SL_PAD_EPDC_PWRCOM = 56, - MX6SL_PAD_EPDC_PWRCTRL0 = 57, - MX6SL_PAD_EPDC_PWRCTRL1 = 58, - MX6SL_PAD_EPDC_PWRCTRL2 = 59, - MX6SL_PAD_EPDC_PWRCTRL3 = 60, - MX6SL_PAD_EPDC_PWRINT = 61, - MX6SL_PAD_EPDC_PWRSTAT = 62, - MX6SL_PAD_EPDC_PWRWAKEUP = 63, - MX6SL_PAD_EPDC_SDCE0 = 64, - MX6SL_PAD_EPDC_SDCE1 = 65, - MX6SL_PAD_EPDC_SDCE2 = 66, - MX6SL_PAD_EPDC_SDCE3 = 67, - MX6SL_PAD_EPDC_SDCLK = 68, - MX6SL_PAD_EPDC_SDLE = 69, - MX6SL_PAD_EPDC_SDOE = 70, - MX6SL_PAD_EPDC_SDSHR = 71, - MX6SL_PAD_EPDC_VCOM0 = 72, - MX6SL_PAD_EPDC_VCOM1 = 73, - MX6SL_PAD_FEC_CRS_DV = 74, - MX6SL_PAD_FEC_MDC = 75, - MX6SL_PAD_FEC_MDIO = 76, - MX6SL_PAD_FEC_REF_CLK = 77, - MX6SL_PAD_FEC_RX_ER = 78, - MX6SL_PAD_FEC_RXD0 = 79, - MX6SL_PAD_FEC_RXD1 = 80, - MX6SL_PAD_FEC_TX_CLK = 81, - MX6SL_PAD_FEC_TX_EN = 82, - MX6SL_PAD_FEC_TXD0 = 83, - MX6SL_PAD_FEC_TXD1 = 84, - MX6SL_PAD_HSIC_DAT = 85, - MX6SL_PAD_HSIC_STROBE = 86, - MX6SL_PAD_I2C1_SCL = 87, - MX6SL_PAD_I2C1_SDA = 88, - MX6SL_PAD_I2C2_SCL = 89, - MX6SL_PAD_I2C2_SDA = 90, - MX6SL_PAD_KEY_COL0 = 91, - MX6SL_PAD_KEY_COL1 = 92, - MX6SL_PAD_KEY_COL2 = 93, - MX6SL_PAD_KEY_COL3 = 94, - MX6SL_PAD_KEY_COL4 = 95, - MX6SL_PAD_KEY_COL5 = 96, - MX6SL_PAD_KEY_COL6 = 97, - MX6SL_PAD_KEY_COL7 = 98, - MX6SL_PAD_KEY_ROW0 = 99, - MX6SL_PAD_KEY_ROW1 = 100, - MX6SL_PAD_KEY_ROW2 = 101, - MX6SL_PAD_KEY_ROW3 = 102, - MX6SL_PAD_KEY_ROW4 = 103, - MX6SL_PAD_KEY_ROW5 = 104, - MX6SL_PAD_KEY_ROW6 = 105, - MX6SL_PAD_KEY_ROW7 = 106, - MX6SL_PAD_LCD_CLK = 107, - MX6SL_PAD_LCD_DAT0 = 108, - MX6SL_PAD_LCD_DAT1 = 109, - MX6SL_PAD_LCD_DAT10 = 110, - MX6SL_PAD_LCD_DAT11 = 111, - MX6SL_PAD_LCD_DAT12 = 112, - MX6SL_PAD_LCD_DAT13 = 113, - MX6SL_PAD_LCD_DAT14 = 114, - MX6SL_PAD_LCD_DAT15 = 115, - MX6SL_PAD_LCD_DAT16 = 116, - MX6SL_PAD_LCD_DAT17 = 117, - MX6SL_PAD_LCD_DAT18 = 118, - MX6SL_PAD_LCD_DAT19 = 119, - MX6SL_PAD_LCD_DAT2 = 120, - MX6SL_PAD_LCD_DAT20 = 121, - MX6SL_PAD_LCD_DAT21 = 122, - MX6SL_PAD_LCD_DAT22 = 123, - MX6SL_PAD_LCD_DAT23 = 124, - MX6SL_PAD_LCD_DAT3 = 125, - MX6SL_PAD_LCD_DAT4 = 126, - MX6SL_PAD_LCD_DAT5 = 127, - MX6SL_PAD_LCD_DAT6 = 128, - MX6SL_PAD_LCD_DAT7 = 129, - MX6SL_PAD_LCD_DAT8 = 130, - MX6SL_PAD_LCD_DAT9 = 131, - MX6SL_PAD_LCD_ENABLE = 132, - MX6SL_PAD_LCD_HSYNC = 133, - MX6SL_PAD_LCD_RESET = 134, - MX6SL_PAD_LCD_VSYNC = 135, - MX6SL_PAD_PWM1 = 136, - MX6SL_PAD_REF_CLK_24M = 137, - MX6SL_PAD_REF_CLK_32K = 138, - MX6SL_PAD_SD1_CLK = 139, - MX6SL_PAD_SD1_CMD = 140, - MX6SL_PAD_SD1_DAT0 = 141, - MX6SL_PAD_SD1_DAT1 = 142, - MX6SL_PAD_SD1_DAT2 = 143, - MX6SL_PAD_SD1_DAT3 = 144, - MX6SL_PAD_SD1_DAT4 = 145, - MX6SL_PAD_SD1_DAT5 = 146, - MX6SL_PAD_SD1_DAT6 = 147, - MX6SL_PAD_SD1_DAT7 = 148, - MX6SL_PAD_SD2_CLK = 149, - MX6SL_PAD_SD2_CMD = 150, - MX6SL_PAD_SD2_DAT0 = 151, - MX6SL_PAD_SD2_DAT1 = 152, - MX6SL_PAD_SD2_DAT2 = 153, - MX6SL_PAD_SD2_DAT3 = 154, - MX6SL_PAD_SD2_DAT4 = 155, - MX6SL_PAD_SD2_DAT5 = 156, - MX6SL_PAD_SD2_DAT6 = 157, - MX6SL_PAD_SD2_DAT7 = 158, - MX6SL_PAD_SD2_RST = 159, - MX6SL_PAD_SD3_CLK = 160, - MX6SL_PAD_SD3_CMD = 161, - MX6SL_PAD_SD3_DAT0 = 162, - MX6SL_PAD_SD3_DAT1 = 163, - MX6SL_PAD_SD3_DAT2 = 164, - MX6SL_PAD_SD3_DAT3 = 165, - MX6SL_PAD_UART1_RXD = 166, - MX6SL_PAD_UART1_TXD = 167, - MX6SL_PAD_WDOG_B = 168, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17), - IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18), - IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK), - IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC), - IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD), - IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS), - IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC), - IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD), - IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS), - IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO), - IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI), - IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK), - IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0), - IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO), - IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI), - IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK), - IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0), - IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0), - IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1), - IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT), - IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE), - IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL), - IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA), - IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL), - IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6), - IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET), - IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC), - IMX_PINCTRL_PIN(MX6SL_PAD_PWM1), - IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M), - IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6), - IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7), - IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST), - IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK), - IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD), - IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0), - IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1), - IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2), - IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3), - IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD), - IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD), - IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B), -}; - -static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = { - .pins = imx6sl_pinctrl_pads, - .npins = ARRAY_SIZE(imx6sl_pinctrl_pads), -}; - -static const struct of_device_id imx6sl_pinctrl_of_match[] = { - { .compatible = "fsl,imx6sl-iomuxc", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match); - -static int imx6sl_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info); -} - -static struct platform_driver imx6sl_pinctrl_driver = { - .driver = { - .name = "imx6sl-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx6sl_pinctrl_of_match, - }, - .probe = imx6sl_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx6sl_pinctrl_init(void) -{ - return platform_driver_register(&imx6sl_pinctrl_driver); -} -arch_initcall(imx6sl_pinctrl_init); - -static void __exit imx6sl_pinctrl_exit(void) -{ - platform_driver_unregister(&imx6sl_pinctrl_driver); -} -module_exit(imx6sl_pinctrl_exit); - -MODULE_AUTHOR("Shawn Guo "); -MODULE_DESCRIPTION("Freescale imx6sl pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/pinctrl-imx6sx.c deleted file mode 100644 index 840344c8580d..000000000000 --- a/drivers/pinctrl/pinctrl-imx6sx.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx6sx_pads { - MX6Sx_PAD_RESERVE0 = 0, - MX6Sx_PAD_RESERVE1 = 1, - MX6Sx_PAD_RESERVE2 = 2, - MX6Sx_PAD_RESERVE3 = 3, - MX6Sx_PAD_RESERVE4 = 4, - MX6SX_PAD_GPIO1_IO00 = 5, - MX6SX_PAD_GPIO1_IO01 = 6, - MX6SX_PAD_GPIO1_IO02 = 7, - MX6SX_PAD_GPIO1_IO03 = 8, - MX6SX_PAD_GPIO1_IO04 = 9, - MX6SX_PAD_GPIO1_IO05 = 10, - MX6SX_PAD_GPIO1_IO06 = 11, - MX6SX_PAD_GPIO1_IO07 = 12, - MX6SX_PAD_GPIO1_IO08 = 13, - MX6SX_PAD_GPIO1_IO09 = 14, - MX6SX_PAD_GPIO1_IO10 = 15, - MX6SX_PAD_GPIO1_IO11 = 16, - MX6SX_PAD_GPIO1_IO12 = 17, - MX6SX_PAD_GPIO1_IO13 = 18, - MX6SX_PAD_CSI_DATA00 = 19, - MX6SX_PAD_CSI_DATA01 = 20, - MX6SX_PAD_CSI_DATA02 = 21, - MX6SX_PAD_CSI_DATA03 = 22, - MX6SX_PAD_CSI_DATA04 = 23, - MX6SX_PAD_CSI_DATA05 = 24, - MX6SX_PAD_CSI_DATA06 = 25, - MX6SX_PAD_CSI_DATA07 = 26, - MX6SX_PAD_CSI_HSYNC = 27, - MX6SX_PAD_CSI_MCLK = 28, - MX6SX_PAD_CSI_PIXCLK = 29, - MX6SX_PAD_CSI_VSYNC = 30, - MX6SX_PAD_ENET1_COL = 31, - MX6SX_PAD_ENET1_CRS = 32, - MX6SX_PAD_ENET1_MDC = 33, - MX6SX_PAD_ENET1_MDIO = 34, - MX6SX_PAD_ENET1_RX_CLK = 35, - MX6SX_PAD_ENET1_TX_CLK = 36, - MX6SX_PAD_ENET2_COL = 37, - MX6SX_PAD_ENET2_CRS = 38, - MX6SX_PAD_ENET2_RX_CLK = 39, - MX6SX_PAD_ENET2_TX_CLK = 40, - MX6SX_PAD_KEY_COL0 = 41, - MX6SX_PAD_KEY_COL1 = 42, - MX6SX_PAD_KEY_COL2 = 43, - MX6SX_PAD_KEY_COL3 = 44, - MX6SX_PAD_KEY_COL4 = 45, - MX6SX_PAD_KEY_ROW0 = 46, - MX6SX_PAD_KEY_ROW1 = 47, - MX6SX_PAD_KEY_ROW2 = 48, - MX6SX_PAD_KEY_ROW3 = 49, - MX6SX_PAD_KEY_ROW4 = 50, - MX6SX_PAD_LCD1_CLK = 51, - MX6SX_PAD_LCD1_DATA00 = 52, - MX6SX_PAD_LCD1_DATA01 = 53, - MX6SX_PAD_LCD1_DATA02 = 54, - MX6SX_PAD_LCD1_DATA03 = 55, - MX6SX_PAD_LCD1_DATA04 = 56, - MX6SX_PAD_LCD1_DATA05 = 57, - MX6SX_PAD_LCD1_DATA06 = 58, - MX6SX_PAD_LCD1_DATA07 = 59, - MX6SX_PAD_LCD1_DATA08 = 60, - MX6SX_PAD_LCD1_DATA09 = 61, - MX6SX_PAD_LCD1_DATA10 = 62, - MX6SX_PAD_LCD1_DATA11 = 63, - MX6SX_PAD_LCD1_DATA12 = 64, - MX6SX_PAD_LCD1_DATA13 = 65, - MX6SX_PAD_LCD1_DATA14 = 66, - MX6SX_PAD_LCD1_DATA15 = 67, - MX6SX_PAD_LCD1_DATA16 = 68, - MX6SX_PAD_LCD1_DATA17 = 69, - MX6SX_PAD_LCD1_DATA18 = 70, - MX6SX_PAD_LCD1_DATA19 = 71, - MX6SX_PAD_LCD1_DATA20 = 72, - MX6SX_PAD_LCD1_DATA21 = 73, - MX6SX_PAD_LCD1_DATA22 = 74, - MX6SX_PAD_LCD1_DATA23 = 75, - MX6SX_PAD_LCD1_ENABLE = 76, - MX6SX_PAD_LCD1_HSYNC = 77, - MX6SX_PAD_LCD1_RESET = 78, - MX6SX_PAD_LCD1_VSYNC = 79, - MX6SX_PAD_NAND_ALE = 80, - MX6SX_PAD_NAND_CE0_B = 81, - MX6SX_PAD_NAND_CE1_B = 82, - MX6SX_PAD_NAND_CLE = 83, - MX6SX_PAD_NAND_DATA00 = 84 , - MX6SX_PAD_NAND_DATA01 = 85, - MX6SX_PAD_NAND_DATA02 = 86, - MX6SX_PAD_NAND_DATA03 = 87, - MX6SX_PAD_NAND_DATA04 = 88, - MX6SX_PAD_NAND_DATA05 = 89, - MX6SX_PAD_NAND_DATA06 = 90, - MX6SX_PAD_NAND_DATA07 = 91, - MX6SX_PAD_NAND_RE_B = 92, - MX6SX_PAD_NAND_READY_B = 93, - MX6SX_PAD_NAND_WE_B = 94, - MX6SX_PAD_NAND_WP_B = 95, - MX6SX_PAD_QSPI1A_DATA0 = 96, - MX6SX_PAD_QSPI1A_DATA1 = 97, - MX6SX_PAD_QSPI1A_DATA2 = 98, - MX6SX_PAD_QSPI1A_DATA3 = 99, - MX6SX_PAD_QSPI1A_DQS = 100, - MX6SX_PAD_QSPI1A_SCLK = 101, - MX6SX_PAD_QSPI1A_SS0_B = 102, - MX6SX_PAD_QSPI1A_SS1_B = 103, - MX6SX_PAD_QSPI1B_DATA0 = 104, - MX6SX_PAD_QSPI1B_DATA1 = 105, - MX6SX_PAD_QSPI1B_DATA2 = 106, - MX6SX_PAD_QSPI1B_DATA3 = 107, - MX6SX_PAD_QSPI1B_DQS = 108, - MX6SX_PAD_QSPI1B_SCLK = 109, - MX6SX_PAD_QSPI1B_SS0_B = 110, - MX6SX_PAD_QSPI1B_SS1_B = 111, - MX6SX_PAD_RGMII1_RD0 = 112, - MX6SX_PAD_RGMII1_RD1 = 113, - MX6SX_PAD_RGMII1_RD2 = 114, - MX6SX_PAD_RGMII1_RD3 = 115, - MX6SX_PAD_RGMII1_RX_CTL = 116, - MX6SX_PAD_RGMII1_RXC = 117, - MX6SX_PAD_RGMII1_TD0 = 118, - MX6SX_PAD_RGMII1_TD1 = 119, - MX6SX_PAD_RGMII1_TD2 = 120, - MX6SX_PAD_RGMII1_TD3 = 121, - MX6SX_PAD_RGMII1_TX_CTL = 122, - MX6SX_PAD_RGMII1_TXC = 123, - MX6SX_PAD_RGMII2_RD0 = 124, - MX6SX_PAD_RGMII2_RD1 = 125, - MX6SX_PAD_RGMII2_RD2 = 126, - MX6SX_PAD_RGMII2_RD3 = 127, - MX6SX_PAD_RGMII2_RX_CTL = 128, - MX6SX_PAD_RGMII2_RXC = 129, - MX6SX_PAD_RGMII2_TD0 = 130, - MX6SX_PAD_RGMII2_TD1 = 131, - MX6SX_PAD_RGMII2_TD2 = 132, - MX6SX_PAD_RGMII2_TD3 = 133, - MX6SX_PAD_RGMII2_TX_CTL = 134, - MX6SX_PAD_RGMII2_TXC = 135, - MX6SX_PAD_SD1_CLK = 136, - MX6SX_PAD_SD1_CMD = 137, - MX6SX_PAD_SD1_DATA0 = 138, - MX6SX_PAD_SD1_DATA1 = 139, - MX6SX_PAD_SD1_DATA2 = 140, - MX6SX_PAD_SD1_DATA3 = 141, - MX6SX_PAD_SD2_CLK = 142, - MX6SX_PAD_SD2_CMD = 143, - MX6SX_PAD_SD2_DATA0 = 144, - MX6SX_PAD_SD2_DATA1 = 145, - MX6SX_PAD_SD2_DATA2 = 146, - MX6SX_PAD_SD2_DATA3 = 147, - MX6SX_PAD_SD3_CLK = 148, - MX6SX_PAD_SD3_CMD = 149, - MX6SX_PAD_SD3_DATA0 = 150, - MX6SX_PAD_SD3_DATA1 = 151, - MX6SX_PAD_SD3_DATA2 = 152, - MX6SX_PAD_SD3_DATA3 = 153, - MX6SX_PAD_SD3_DATA4 = 154, - MX6SX_PAD_SD3_DATA5 = 155, - MX6SX_PAD_SD3_DATA6 = 156, - MX6SX_PAD_SD3_DATA7 = 157, - MX6SX_PAD_SD4_CLK = 158, - MX6SX_PAD_SD4_CMD = 159, - MX6SX_PAD_SD4_DATA0 = 160, - MX6SX_PAD_SD4_DATA1 = 161, - MX6SX_PAD_SD4_DATA2 = 162, - MX6SX_PAD_SD4_DATA3 = 163, - MX6SX_PAD_SD4_DATA4 = 164, - MX6SX_PAD_SD4_DATA5 = 165, - MX6SX_PAD_SD4_DATA6 = 166, - MX6SX_PAD_SD4_DATA7 = 167, - MX6SX_PAD_SD4_RESET_B = 168, - MX6SX_PAD_USB_H_DATA = 169, - MX6SX_PAD_USB_H_STROBE = 170, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1), - IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2), - IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3), - IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12), - IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK), - IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET), - IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B), - IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B), - IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL), - IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC), - IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0), - IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1), - IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2), - IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3), - IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0), - IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1), - IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2), - IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6), - IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7), - IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B), - IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA), - IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE), -}; - -static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = { - .pins = imx6sx_pinctrl_pads, - .npins = ARRAY_SIZE(imx6sx_pinctrl_pads), -}; - -static const struct of_device_id imx6sx_pinctrl_of_match[] = { - { .compatible = "fsl,imx6sx-iomuxc", }, - { /* sentinel */ } -}; - -static int imx6sx_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info); -} - -static struct platform_driver imx6sx_pinctrl_driver = { - .driver = { - .name = "imx6sx-pinctrl", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match), - }, - .probe = imx6sx_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init imx6sx_pinctrl_init(void) -{ - return platform_driver_register(&imx6sx_pinctrl_driver); -} -arch_initcall(imx6sx_pinctrl_init); - -static void __exit imx6sx_pinctrl_exit(void) -{ - platform_driver_unregister(&imx6sx_pinctrl_driver); -} -module_exit(imx6sx_pinctrl_exit); - -MODULE_AUTHOR("Anson Huang "); -MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c deleted file mode 100644 index 67035091f8fd..000000000000 --- a/drivers/pinctrl/pinctrl-mxs.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "core.h" -#include "pinctrl-mxs.h" - -#define SUFFIX_LEN 4 - -struct mxs_pinctrl_data { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - struct mxs_pinctrl_soc_data *soc; -}; - -static int mxs_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->ngroups; -} - -static const char *mxs_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->groups[group].name; -} - -static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, - const unsigned **pins, unsigned *num_pins) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *pins = d->soc->groups[group].pins; - *num_pins = d->soc->groups[group].npins; - - return 0; -} - -static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, " %s", dev_name(pctldev->dev)); -} - -static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct pinctrl_map *new_map; - char *group = NULL; - unsigned new_num = 1; - unsigned long config = 0; - unsigned long *pconfig; - int length = strlen(np->name) + SUFFIX_LEN; - bool purecfg = false; - u32 val, reg; - int ret, i = 0; - - /* Check for pin config node which has no 'reg' property */ - if (of_property_read_u32(np, "reg", ®)) - purecfg = true; - - ret = of_property_read_u32(np, "fsl,drive-strength", &val); - if (!ret) - config = val | MA_PRESENT; - ret = of_property_read_u32(np, "fsl,voltage", &val); - if (!ret) - config |= val << VOL_SHIFT | VOL_PRESENT; - ret = of_property_read_u32(np, "fsl,pull-up", &val); - if (!ret) - config |= val << PULL_SHIFT | PULL_PRESENT; - - /* Check for group node which has both mux and config settings */ - if (!purecfg && config) - new_num = 2; - - new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - if (!purecfg) { - new_map[i].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[i].data.mux.function = np->name; - - /* Compose group name */ - group = kzalloc(length, GFP_KERNEL); - if (!group) { - ret = -ENOMEM; - goto free; - } - snprintf(group, length, "%s.%d", np->name, reg); - new_map[i].data.mux.group = group; - i++; - } - - if (config) { - pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL); - if (!pconfig) { - ret = -ENOMEM; - goto free_group; - } - - new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; - new_map[i].data.configs.group_or_pin = purecfg ? np->name : - group; - new_map[i].data.configs.configs = pconfig; - new_map[i].data.configs.num_configs = 1; - } - - *map = new_map; - *num_maps = new_num; - - return 0; - -free_group: - if (!purecfg) - kfree(group); -free: - kfree(new_map); - return ret; -} - -static void mxs_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - u32 i; - - for (i = 0; i < num_maps; i++) { - if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) - kfree(map[i].data.mux.group); - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - } - - kfree(map); -} - -static const struct pinctrl_ops mxs_pinctrl_ops = { - .get_groups_count = mxs_get_groups_count, - .get_group_name = mxs_get_group_name, - .get_group_pins = mxs_get_group_pins, - .pin_dbg_show = mxs_pin_dbg_show, - .dt_node_to_map = mxs_dt_node_to_map, - .dt_free_map = mxs_dt_free_map, -}; - -static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->nfunctions; -} - -static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->functions[function].name; -} - -static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned group, - const char * const **groups, - unsigned * const num_groups) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *groups = d->soc->functions[group].groups; - *num_groups = d->soc->functions[group].ngroups; - - return 0; -} - -static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - struct mxs_group *g = &d->soc->groups[group]; - void __iomem *reg; - u8 bank, shift; - u16 pin; - u32 i; - - for (i = 0; i < g->npins; i++) { - bank = PINID_TO_BANK(g->pins[i]); - pin = PINID_TO_PIN(g->pins[i]); - reg = d->base + d->soc->regs->muxsel; - reg += bank * 0x20 + pin / 16 * 0x10; - shift = pin % 16 * 2; - - writel(0x3 << shift, reg + CLR); - writel(g->muxsel[i] << shift, reg + SET); - } - - return 0; -} - -static const struct pinmux_ops mxs_pinmux_ops = { - .get_functions_count = mxs_pinctrl_get_funcs_count, - .get_function_name = mxs_pinctrl_get_func_name, - .get_function_groups = mxs_pinctrl_get_func_groups, - .set_mux = mxs_pinctrl_set_mux, -}; - -static int mxs_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long *config) -{ - return -ENOTSUPP; -} - -static int mxs_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long *configs, - unsigned num_configs) -{ - return -ENOTSUPP; -} - -static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned group, unsigned long *config) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *config = d->soc->groups[group].config; - - return 0; -} - -static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long *configs, - unsigned num_configs) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - struct mxs_group *g = &d->soc->groups[group]; - void __iomem *reg; - u8 ma, vol, pull, bank, shift; - u16 pin; - u32 i; - int n; - unsigned long config; - - for (n = 0; n < num_configs; n++) { - config = configs[n]; - - ma = CONFIG_TO_MA(config); - vol = CONFIG_TO_VOL(config); - pull = CONFIG_TO_PULL(config); - - for (i = 0; i < g->npins; i++) { - bank = PINID_TO_BANK(g->pins[i]); - pin = PINID_TO_PIN(g->pins[i]); - - /* drive */ - reg = d->base + d->soc->regs->drive; - reg += bank * 0x40 + pin / 8 * 0x10; - - /* mA */ - if (config & MA_PRESENT) { - shift = pin % 8 * 4; - writel(0x3 << shift, reg + CLR); - writel(ma << shift, reg + SET); - } - - /* vol */ - if (config & VOL_PRESENT) { - shift = pin % 8 * 4 + 2; - if (vol) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); - } - - /* pull */ - if (config & PULL_PRESENT) { - reg = d->base + d->soc->regs->pull; - reg += bank * 0x10; - shift = pin; - if (pull) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); - } - } - - /* cache the config value for mxs_pinconf_group_get() */ - g->config = config; - - } /* for each config */ - - return 0; -} - -static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin) -{ - /* Not support */ -} - -static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ - unsigned long config; - - if (!mxs_pinconf_group_get(pctldev, group, &config)) - seq_printf(s, "0x%lx", config); -} - -static const struct pinconf_ops mxs_pinconf_ops = { - .pin_config_get = mxs_pinconf_get, - .pin_config_set = mxs_pinconf_set, - .pin_config_group_get = mxs_pinconf_group_get, - .pin_config_group_set = mxs_pinconf_group_set, - .pin_config_dbg_show = mxs_pinconf_dbg_show, - .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc mxs_pinctrl_desc = { - .pctlops = &mxs_pinctrl_ops, - .pmxops = &mxs_pinmux_ops, - .confops = &mxs_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int mxs_pinctrl_parse_group(struct platform_device *pdev, - struct device_node *np, int idx, - const char **out_name) -{ - struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); - struct mxs_group *g = &d->soc->groups[idx]; - struct property *prop; - const char *propname = "fsl,pinmux-ids"; - char *group; - int length = strlen(np->name) + SUFFIX_LEN; - u32 val, i; - - group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL); - if (!group) - return -ENOMEM; - if (of_property_read_u32(np, "reg", &val)) - snprintf(group, length, "%s", np->name); - else - snprintf(group, length, "%s.%d", np->name, val); - g->name = group; - - prop = of_find_property(np, propname, &length); - if (!prop) - return -EINVAL; - g->npins = length / sizeof(u32); - - g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins), - GFP_KERNEL); - if (!g->pins) - return -ENOMEM; - - g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel), - GFP_KERNEL); - if (!g->muxsel) - return -ENOMEM; - - of_property_read_u32_array(np, propname, g->pins, g->npins); - for (i = 0; i < g->npins; i++) { - g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]); - g->pins[i] = MUXID_TO_PINID(g->pins[i]); - } - - if (out_name) - *out_name = g->name; - - return 0; -} - -static int mxs_pinctrl_probe_dt(struct platform_device *pdev, - struct mxs_pinctrl_data *d) -{ - struct mxs_pinctrl_soc_data *soc = d->soc; - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - struct mxs_function *f; - const char *gpio_compat = "fsl,mxs-gpio"; - const char *fn, *fnull = ""; - int i = 0, idxf = 0, idxg = 0; - int ret; - u32 val; - - child = of_get_next_child(np, NULL); - if (!child) { - dev_err(&pdev->dev, "no group is defined\n"); - return -ENOENT; - } - - /* Count total functions and groups */ - fn = fnull; - for_each_child_of_node(np, child) { - if (of_device_is_compatible(child, gpio_compat)) - continue; - soc->ngroups++; - /* Skip pure pinconf node */ - if (of_property_read_u32(child, "reg", &val)) - continue; - if (strcmp(fn, child->name)) { - fn = child->name; - soc->nfunctions++; - } - } - - soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions * - sizeof(*soc->functions), GFP_KERNEL); - if (!soc->functions) - return -ENOMEM; - - soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups * - sizeof(*soc->groups), GFP_KERNEL); - if (!soc->groups) - return -ENOMEM; - - /* Count groups for each function */ - fn = fnull; - f = &soc->functions[idxf]; - for_each_child_of_node(np, child) { - if (of_device_is_compatible(child, gpio_compat)) - continue; - if (of_property_read_u32(child, "reg", &val)) - continue; - if (strcmp(fn, child->name)) { - f = &soc->functions[idxf++]; - f->name = fn = child->name; - } - f->ngroups++; - }; - - /* Get groups for each function */ - idxf = 0; - fn = fnull; - for_each_child_of_node(np, child) { - if (of_device_is_compatible(child, gpio_compat)) - continue; - if (of_property_read_u32(child, "reg", &val)) { - ret = mxs_pinctrl_parse_group(pdev, child, - idxg++, NULL); - if (ret) - return ret; - continue; - } - - if (strcmp(fn, child->name)) { - f = &soc->functions[idxf++]; - f->groups = devm_kzalloc(&pdev->dev, f->ngroups * - sizeof(*f->groups), - GFP_KERNEL); - if (!f->groups) - return -ENOMEM; - fn = child->name; - i = 0; - } - ret = mxs_pinctrl_parse_group(pdev, child, idxg++, - &f->groups[i++]); - if (ret) - return ret; - } - - return 0; -} - -int mxs_pinctrl_probe(struct platform_device *pdev, - struct mxs_pinctrl_soc_data *soc) -{ - struct device_node *np = pdev->dev.of_node; - struct mxs_pinctrl_data *d; - int ret; - - d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL); - if (!d) - return -ENOMEM; - - d->dev = &pdev->dev; - d->soc = soc; - - d->base = of_iomap(np, 0); - if (!d->base) - return -EADDRNOTAVAIL; - - mxs_pinctrl_desc.pins = d->soc->pins; - mxs_pinctrl_desc.npins = d->soc->npins; - mxs_pinctrl_desc.name = dev_name(&pdev->dev); - - platform_set_drvdata(pdev, d); - - ret = mxs_pinctrl_probe_dt(pdev, d); - if (ret) { - dev_err(&pdev->dev, "dt probe failed: %d\n", ret); - goto err; - } - - d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d); - if (!d->pctl) { - dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n"); - ret = -EINVAL; - goto err; - } - - return 0; - -err: - iounmap(d->base); - return ret; -} -EXPORT_SYMBOL_GPL(mxs_pinctrl_probe); - -int mxs_pinctrl_remove(struct platform_device *pdev) -{ - struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); - - pinctrl_unregister(d->pctl); - iounmap(d->base); - - return 0; -} -EXPORT_SYMBOL_GPL(mxs_pinctrl_remove); diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/pinctrl-mxs.h deleted file mode 100644 index fdd88d0bae22..000000000000 --- a/drivers/pinctrl/pinctrl-mxs.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __PINCTRL_MXS_H -#define __PINCTRL_MXS_H - -#include -#include - -#define SET 0x4 -#define CLR 0x8 -#define TOG 0xc - -#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) -#define PINID(bank, pin) ((bank) * 32 + (pin)) - -/* - * pinmux-id bit field definitions - * - * bank: 15..12 (4) - * pin: 11..4 (8) - * muxsel: 3..0 (4) - */ -#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff) -#define MUXID_TO_MUXSEL(m) ((m) & 0xf) - -#define PINID_TO_BANK(p) ((p) >> 5) -#define PINID_TO_PIN(p) ((p) % 32) - -/* - * pin config bit field definitions - * - * pull-up: 6..5 (2) - * voltage: 4..3 (2) - * mA: 2..0 (3) - * - * MSB of each field is presence bit for the config. - */ -#define PULL_PRESENT (1 << 6) -#define PULL_SHIFT 5 -#define VOL_PRESENT (1 << 4) -#define VOL_SHIFT 3 -#define MA_PRESENT (1 << 2) -#define MA_SHIFT 0 -#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1) -#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1) -#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3) - -struct mxs_function { - const char *name; - const char **groups; - unsigned ngroups; -}; - -struct mxs_group { - const char *name; - unsigned int *pins; - unsigned npins; - u8 *muxsel; - u8 config; -}; - -struct mxs_regs { - u16 muxsel; - u16 drive; - u16 pull; -}; - -struct mxs_pinctrl_soc_data { - const struct mxs_regs *regs; - const struct pinctrl_pin_desc *pins; - unsigned npins; - struct mxs_function *functions; - unsigned nfunctions; - struct mxs_group *groups; - unsigned ngroups; -}; - -int mxs_pinctrl_probe(struct platform_device *pdev, - struct mxs_pinctrl_soc_data *soc); -int mxs_pinctrl_remove(struct platform_device *pdev); - -#endif /* __PINCTRL_MXS_H */ diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c deleted file mode 100644 index bddd913d28ba..000000000000 --- a/drivers/pinctrl/pinctrl-vf610.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * VF610 pinctrl driver based on imx pinmux and pinconf core - * - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum vf610_pads { - VF610_PAD_PTA6 = 0, - VF610_PAD_PTA8 = 1, - VF610_PAD_PTA9 = 2, - VF610_PAD_PTA10 = 3, - VF610_PAD_PTA11 = 4, - VF610_PAD_PTA12 = 5, - VF610_PAD_PTA16 = 6, - VF610_PAD_PTA17 = 7, - VF610_PAD_PTA18 = 8, - VF610_PAD_PTA19 = 9, - VF610_PAD_PTA20 = 10, - VF610_PAD_PTA21 = 11, - VF610_PAD_PTA22 = 12, - VF610_PAD_PTA23 = 13, - VF610_PAD_PTA24 = 14, - VF610_PAD_PTA25 = 15, - VF610_PAD_PTA26 = 16, - VF610_PAD_PTA27 = 17, - VF610_PAD_PTA28 = 18, - VF610_PAD_PTA29 = 19, - VF610_PAD_PTA30 = 20, - VF610_PAD_PTA31 = 21, - VF610_PAD_PTB0 = 22, - VF610_PAD_PTB1 = 23, - VF610_PAD_PTB2 = 24, - VF610_PAD_PTB3 = 25, - VF610_PAD_PTB4 = 26, - VF610_PAD_PTB5 = 27, - VF610_PAD_PTB6 = 28, - VF610_PAD_PTB7 = 29, - VF610_PAD_PTB8 = 30, - VF610_PAD_PTB9 = 31, - VF610_PAD_PTB10 = 32, - VF610_PAD_PTB11 = 33, - VF610_PAD_PTB12 = 34, - VF610_PAD_PTB13 = 35, - VF610_PAD_PTB14 = 36, - VF610_PAD_PTB15 = 37, - VF610_PAD_PTB16 = 38, - VF610_PAD_PTB17 = 39, - VF610_PAD_PTB18 = 40, - VF610_PAD_PTB19 = 41, - VF610_PAD_PTB20 = 42, - VF610_PAD_PTB21 = 43, - VF610_PAD_PTB22 = 44, - VF610_PAD_PTC0 = 45, - VF610_PAD_PTC1 = 46, - VF610_PAD_PTC2 = 47, - VF610_PAD_PTC3 = 48, - VF610_PAD_PTC4 = 49, - VF610_PAD_PTC5 = 50, - VF610_PAD_PTC6 = 51, - VF610_PAD_PTC7 = 52, - VF610_PAD_PTC8 = 53, - VF610_PAD_PTC9 = 54, - VF610_PAD_PTC10 = 55, - VF610_PAD_PTC11 = 56, - VF610_PAD_PTC12 = 57, - VF610_PAD_PTC13 = 58, - VF610_PAD_PTC14 = 59, - VF610_PAD_PTC15 = 60, - VF610_PAD_PTC16 = 61, - VF610_PAD_PTC17 = 62, - VF610_PAD_PTD31 = 63, - VF610_PAD_PTD30 = 64, - VF610_PAD_PTD29 = 65, - VF610_PAD_PTD28 = 66, - VF610_PAD_PTD27 = 67, - VF610_PAD_PTD26 = 68, - VF610_PAD_PTD25 = 69, - VF610_PAD_PTD24 = 70, - VF610_PAD_PTD23 = 71, - VF610_PAD_PTD22 = 72, - VF610_PAD_PTD21 = 73, - VF610_PAD_PTD20 = 74, - VF610_PAD_PTD19 = 75, - VF610_PAD_PTD18 = 76, - VF610_PAD_PTD17 = 77, - VF610_PAD_PTD16 = 78, - VF610_PAD_PTD0 = 79, - VF610_PAD_PTD1 = 80, - VF610_PAD_PTD2 = 81, - VF610_PAD_PTD3 = 82, - VF610_PAD_PTD4 = 83, - VF610_PAD_PTD5 = 84, - VF610_PAD_PTD6 = 85, - VF610_PAD_PTD7 = 86, - VF610_PAD_PTD8 = 87, - VF610_PAD_PTD9 = 88, - VF610_PAD_PTD10 = 89, - VF610_PAD_PTD11 = 90, - VF610_PAD_PTD12 = 91, - VF610_PAD_PTD13 = 92, - VF610_PAD_PTB23 = 93, - VF610_PAD_PTB24 = 94, - VF610_PAD_PTB25 = 95, - VF610_PAD_PTB26 = 96, - VF610_PAD_PTB27 = 97, - VF610_PAD_PTB28 = 98, - VF610_PAD_PTC26 = 99, - VF610_PAD_PTC27 = 100, - VF610_PAD_PTC28 = 101, - VF610_PAD_PTC29 = 102, - VF610_PAD_PTC30 = 103, - VF610_PAD_PTC31 = 104, - VF610_PAD_PTE0 = 105, - VF610_PAD_PTE1 = 106, - VF610_PAD_PTE2 = 107, - VF610_PAD_PTE3 = 108, - VF610_PAD_PTE4 = 109, - VF610_PAD_PTE5 = 110, - VF610_PAD_PTE6 = 111, - VF610_PAD_PTE7 = 112, - VF610_PAD_PTE8 = 113, - VF610_PAD_PTE9 = 114, - VF610_PAD_PTE10 = 115, - VF610_PAD_PTE11 = 116, - VF610_PAD_PTE12 = 117, - VF610_PAD_PTE13 = 118, - VF610_PAD_PTE14 = 119, - VF610_PAD_PTE15 = 120, - VF610_PAD_PTE16 = 121, - VF610_PAD_PTE17 = 122, - VF610_PAD_PTE18 = 123, - VF610_PAD_PTE19 = 124, - VF610_PAD_PTE20 = 125, - VF610_PAD_PTE21 = 126, - VF610_PAD_PTE22 = 127, - VF610_PAD_PTE23 = 128, - VF610_PAD_PTE24 = 129, - VF610_PAD_PTE25 = 130, - VF610_PAD_PTE26 = 131, - VF610_PAD_PTE27 = 132, - VF610_PAD_PTE28 = 133, - VF610_PAD_PTA7 = 134, -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = { - IMX_PINCTRL_PIN(VF610_PAD_PTA6), - IMX_PINCTRL_PIN(VF610_PAD_PTA8), - IMX_PINCTRL_PIN(VF610_PAD_PTA9), - IMX_PINCTRL_PIN(VF610_PAD_PTA10), - IMX_PINCTRL_PIN(VF610_PAD_PTA11), - IMX_PINCTRL_PIN(VF610_PAD_PTA12), - IMX_PINCTRL_PIN(VF610_PAD_PTA16), - IMX_PINCTRL_PIN(VF610_PAD_PTA17), - IMX_PINCTRL_PIN(VF610_PAD_PTA18), - IMX_PINCTRL_PIN(VF610_PAD_PTA19), - IMX_PINCTRL_PIN(VF610_PAD_PTA20), - IMX_PINCTRL_PIN(VF610_PAD_PTA21), - IMX_PINCTRL_PIN(VF610_PAD_PTA22), - IMX_PINCTRL_PIN(VF610_PAD_PTA23), - IMX_PINCTRL_PIN(VF610_PAD_PTA24), - IMX_PINCTRL_PIN(VF610_PAD_PTA25), - IMX_PINCTRL_PIN(VF610_PAD_PTA26), - IMX_PINCTRL_PIN(VF610_PAD_PTA27), - IMX_PINCTRL_PIN(VF610_PAD_PTA28), - IMX_PINCTRL_PIN(VF610_PAD_PTA29), - IMX_PINCTRL_PIN(VF610_PAD_PTA30), - IMX_PINCTRL_PIN(VF610_PAD_PTA31), - IMX_PINCTRL_PIN(VF610_PAD_PTB0), - IMX_PINCTRL_PIN(VF610_PAD_PTB1), - IMX_PINCTRL_PIN(VF610_PAD_PTB2), - IMX_PINCTRL_PIN(VF610_PAD_PTB3), - IMX_PINCTRL_PIN(VF610_PAD_PTB4), - IMX_PINCTRL_PIN(VF610_PAD_PTB5), - IMX_PINCTRL_PIN(VF610_PAD_PTB6), - IMX_PINCTRL_PIN(VF610_PAD_PTB7), - IMX_PINCTRL_PIN(VF610_PAD_PTB8), - IMX_PINCTRL_PIN(VF610_PAD_PTB9), - IMX_PINCTRL_PIN(VF610_PAD_PTB10), - IMX_PINCTRL_PIN(VF610_PAD_PTB11), - IMX_PINCTRL_PIN(VF610_PAD_PTB12), - IMX_PINCTRL_PIN(VF610_PAD_PTB13), - IMX_PINCTRL_PIN(VF610_PAD_PTB14), - IMX_PINCTRL_PIN(VF610_PAD_PTB15), - IMX_PINCTRL_PIN(VF610_PAD_PTB16), - IMX_PINCTRL_PIN(VF610_PAD_PTB17), - IMX_PINCTRL_PIN(VF610_PAD_PTB18), - IMX_PINCTRL_PIN(VF610_PAD_PTB19), - IMX_PINCTRL_PIN(VF610_PAD_PTB20), - IMX_PINCTRL_PIN(VF610_PAD_PTB21), - IMX_PINCTRL_PIN(VF610_PAD_PTB22), - IMX_PINCTRL_PIN(VF610_PAD_PTC0), - IMX_PINCTRL_PIN(VF610_PAD_PTC1), - IMX_PINCTRL_PIN(VF610_PAD_PTC2), - IMX_PINCTRL_PIN(VF610_PAD_PTC3), - IMX_PINCTRL_PIN(VF610_PAD_PTC4), - IMX_PINCTRL_PIN(VF610_PAD_PTC5), - IMX_PINCTRL_PIN(VF610_PAD_PTC6), - IMX_PINCTRL_PIN(VF610_PAD_PTC7), - IMX_PINCTRL_PIN(VF610_PAD_PTC8), - IMX_PINCTRL_PIN(VF610_PAD_PTC9), - IMX_PINCTRL_PIN(VF610_PAD_PTC10), - IMX_PINCTRL_PIN(VF610_PAD_PTC11), - IMX_PINCTRL_PIN(VF610_PAD_PTC12), - IMX_PINCTRL_PIN(VF610_PAD_PTC13), - IMX_PINCTRL_PIN(VF610_PAD_PTC14), - IMX_PINCTRL_PIN(VF610_PAD_PTC15), - IMX_PINCTRL_PIN(VF610_PAD_PTC16), - IMX_PINCTRL_PIN(VF610_PAD_PTC17), - IMX_PINCTRL_PIN(VF610_PAD_PTD31), - IMX_PINCTRL_PIN(VF610_PAD_PTD30), - IMX_PINCTRL_PIN(VF610_PAD_PTD29), - IMX_PINCTRL_PIN(VF610_PAD_PTD28), - IMX_PINCTRL_PIN(VF610_PAD_PTD27), - IMX_PINCTRL_PIN(VF610_PAD_PTD26), - IMX_PINCTRL_PIN(VF610_PAD_PTD25), - IMX_PINCTRL_PIN(VF610_PAD_PTD24), - IMX_PINCTRL_PIN(VF610_PAD_PTD23), - IMX_PINCTRL_PIN(VF610_PAD_PTD22), - IMX_PINCTRL_PIN(VF610_PAD_PTD21), - IMX_PINCTRL_PIN(VF610_PAD_PTD20), - IMX_PINCTRL_PIN(VF610_PAD_PTD19), - IMX_PINCTRL_PIN(VF610_PAD_PTD18), - IMX_PINCTRL_PIN(VF610_PAD_PTD17), - IMX_PINCTRL_PIN(VF610_PAD_PTD16), - IMX_PINCTRL_PIN(VF610_PAD_PTD0), - IMX_PINCTRL_PIN(VF610_PAD_PTD1), - IMX_PINCTRL_PIN(VF610_PAD_PTD2), - IMX_PINCTRL_PIN(VF610_PAD_PTD3), - IMX_PINCTRL_PIN(VF610_PAD_PTD4), - IMX_PINCTRL_PIN(VF610_PAD_PTD5), - IMX_PINCTRL_PIN(VF610_PAD_PTD6), - IMX_PINCTRL_PIN(VF610_PAD_PTD7), - IMX_PINCTRL_PIN(VF610_PAD_PTD8), - IMX_PINCTRL_PIN(VF610_PAD_PTD9), - IMX_PINCTRL_PIN(VF610_PAD_PTD10), - IMX_PINCTRL_PIN(VF610_PAD_PTD11), - IMX_PINCTRL_PIN(VF610_PAD_PTD12), - IMX_PINCTRL_PIN(VF610_PAD_PTD13), - IMX_PINCTRL_PIN(VF610_PAD_PTB23), - IMX_PINCTRL_PIN(VF610_PAD_PTB24), - IMX_PINCTRL_PIN(VF610_PAD_PTB25), - IMX_PINCTRL_PIN(VF610_PAD_PTB26), - IMX_PINCTRL_PIN(VF610_PAD_PTB27), - IMX_PINCTRL_PIN(VF610_PAD_PTB28), - IMX_PINCTRL_PIN(VF610_PAD_PTC26), - IMX_PINCTRL_PIN(VF610_PAD_PTC27), - IMX_PINCTRL_PIN(VF610_PAD_PTC28), - IMX_PINCTRL_PIN(VF610_PAD_PTC29), - IMX_PINCTRL_PIN(VF610_PAD_PTC30), - IMX_PINCTRL_PIN(VF610_PAD_PTC31), - IMX_PINCTRL_PIN(VF610_PAD_PTE0), - IMX_PINCTRL_PIN(VF610_PAD_PTE1), - IMX_PINCTRL_PIN(VF610_PAD_PTE2), - IMX_PINCTRL_PIN(VF610_PAD_PTE3), - IMX_PINCTRL_PIN(VF610_PAD_PTE4), - IMX_PINCTRL_PIN(VF610_PAD_PTE5), - IMX_PINCTRL_PIN(VF610_PAD_PTE6), - IMX_PINCTRL_PIN(VF610_PAD_PTE7), - IMX_PINCTRL_PIN(VF610_PAD_PTE8), - IMX_PINCTRL_PIN(VF610_PAD_PTE9), - IMX_PINCTRL_PIN(VF610_PAD_PTE10), - IMX_PINCTRL_PIN(VF610_PAD_PTE11), - IMX_PINCTRL_PIN(VF610_PAD_PTE12), - IMX_PINCTRL_PIN(VF610_PAD_PTE13), - IMX_PINCTRL_PIN(VF610_PAD_PTE14), - IMX_PINCTRL_PIN(VF610_PAD_PTE15), - IMX_PINCTRL_PIN(VF610_PAD_PTE16), - IMX_PINCTRL_PIN(VF610_PAD_PTE17), - IMX_PINCTRL_PIN(VF610_PAD_PTE18), - IMX_PINCTRL_PIN(VF610_PAD_PTE19), - IMX_PINCTRL_PIN(VF610_PAD_PTE20), - IMX_PINCTRL_PIN(VF610_PAD_PTE21), - IMX_PINCTRL_PIN(VF610_PAD_PTE22), - IMX_PINCTRL_PIN(VF610_PAD_PTE23), - IMX_PINCTRL_PIN(VF610_PAD_PTE24), - IMX_PINCTRL_PIN(VF610_PAD_PTE25), - IMX_PINCTRL_PIN(VF610_PAD_PTE26), - IMX_PINCTRL_PIN(VF610_PAD_PTE27), - IMX_PINCTRL_PIN(VF610_PAD_PTE28), - IMX_PINCTRL_PIN(VF610_PAD_PTA7), -}; - -static struct imx_pinctrl_soc_info vf610_pinctrl_info = { - .pins = vf610_pinctrl_pads, - .npins = ARRAY_SIZE(vf610_pinctrl_pads), - .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, -}; - -static struct of_device_id vf610_pinctrl_of_match[] = { - { .compatible = "fsl,vf610-iomuxc", }, - { /* sentinel */ } -}; - -static int vf610_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &vf610_pinctrl_info); -} - -static struct platform_driver vf610_pinctrl_driver = { - .driver = { - .name = "vf610-pinctrl", - .owner = THIS_MODULE, - .of_match_table = vf610_pinctrl_of_match, - }, - .probe = vf610_pinctrl_probe, - .remove = imx_pinctrl_remove, -}; - -static int __init vf610_pinctrl_init(void) -{ - return platform_driver_register(&vf610_pinctrl_driver); -} -arch_initcall(vf610_pinctrl_init); - -static void __exit vf610_pinctrl_exit(void) -{ - platform_driver_unregister(&vf610_pinctrl_driver); -} -module_exit(vf610_pinctrl_exit); - -MODULE_DESCRIPTION("Freescale VF610 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 51128e8ac839495e0f2c8287cfe65f9277494a98 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 3 Sep 2014 13:46:26 +0200 Subject: pinctrl: sh-pfc: rename confusing pinmux ops variable The vtable named *pinmux_ops in the affected files are not really about pin multiplexing, but a struct related to some PFC-specific operations, inclusing pin config (bias setting). Rename the variable so as to avoid confusions. Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-sh7372.c | 4 ++-- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index ce9fb7aa8ba3..280a56f97786 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2717,14 +2717,14 @@ static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, iowrite8(value, addr); } -static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = { .get_bias = r8a73a4_pinmux_get_bias, .set_bias = r8a73a4_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .name = "r8a73a4_pfc", - .ops = &r8a73a4_pinmux_ops, + .ops = &r8a73a4_pfc_ops, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index e4c1ef477053..b486e9d20cc2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -3752,14 +3752,14 @@ static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, iowrite8(value, addr); } -static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7740_pfc_ops = { .get_bias = r8a7740_pinmux_get_bias, .set_bias = r8a7740_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7740_pinmux_info = { .name = "r8a7740_pfc", - .ops = &r8a7740_pinmux_ops, + .ops = &r8a7740_pfc_ops, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index d9158b3b2919..8211f66a2f68 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -2614,14 +2614,14 @@ static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, iowrite8(value, addr); } -static const struct sh_pfc_soc_operations sh7372_pinmux_ops = { +static const struct sh_pfc_soc_operations sh7372_pfc_ops = { .get_bias = sh7372_pinmux_get_bias, .set_bias = sh7372_pinmux_set_bias, }; const struct sh_pfc_soc_info sh7372_pinmux_info = { .name = "sh7372_pfc", - .ops = &sh7372_pinmux_ops, + .ops = &sh7372_pfc_ops, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 0bd8f4401b42..2dd8fd524a80 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3856,7 +3856,7 @@ static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) return 0; } -static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { +static const struct sh_pfc_soc_operations sh73a0_pfc_ops = { .init = sh73a0_pinmux_soc_init, .get_bias = sh73a0_pinmux_get_bias, .set_bias = sh73a0_pinmux_set_bias, @@ -3864,7 +3864,7 @@ static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { const struct sh_pfc_soc_info sh73a0_pinmux_info = { .name = "sh73a0_pfc", - .ops = &sh73a0_pinmux_ops, + .ops = &sh73a0_pfc_ops, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, -- cgit v1.2.3 From c4f6f9c0f38a30148f05bf477ffe3213b8dc2e0c Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 3 Sep 2014 19:28:13 +0300 Subject: pinctrl: qcom: Add APQ8084 pinctrl support This patchset adds pinctrl support for the Qualcomm APQ8084 platform. This set of patches adds pinctrl support for the Qualcomm APQ8084 platform. The first patch adds the pin definitions. The second patch contains the devicetree binding documentation. The third patch adds the DT node. The last patch makes the INTR_TARGET_PROC_APPS value configurable and defines it for each existing SoC. Tested on IFC6540 board. Changes since v3: - Fixed the sdc valid pin values in the binding documentation - sdc2 instead of sdc3. (suggested by Bjorn Andersson) Changes since v2: - Fixed some incorrect bits and offsets. (suggested by Bjorn Andersson) - Updated binding documentation to follow the format of msm8960. (suggested by Bjorn Andersson) - Added fourth patch, which removes the hardcoded INTR_TARGET_PROC_APPS value and makes it configurable. Also we keep the current value for existing SoCs. (suggested by Bjorn Andersson) Changes since v1: - Updated the total number of pins (suggested by Bjorn Andersson) - Added the missing pin info (provided by Andy Gross) - Updated groups and functions to be consistent with other pinctrls. (suggested by Andy Gross) - Removed unused functions, qdss and test pins. (suggested by Andy Gross) - Updated the documentation with the possible functions. Reviewed-by: Andy Gross Acked-by: Bjorn Andersson Signed-off-by: Georgi Djakov Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-apq8084.c | 1243 ++++++++++++++++++++++++++++++++ 3 files changed, 1252 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-apq8084.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index d160a710d704..81275af9638b 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -15,6 +15,14 @@ config PINCTRL_APQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8064 platform. +config PINCTRL_APQ8084 + tristate "Qualcomm APQ8084 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm APQ8084 platform. + config PINCTRL_IPQ8064 tristate "Qualcomm IPQ8064 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 2a02602d715c..ba8519fcd8d3 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -1,6 +1,7 @@ # Qualcomm pin control drivers obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o +obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c new file mode 100644 index 000000000000..5362959c448f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -0,0 +1,1243 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc apq8084_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + + PINCTRL_PIN(147, "SDC1_CLK"), + PINCTRL_PIN(148, "SDC1_CMD"), + PINCTRL_PIN(149, "SDC1_DATA"), + PINCTRL_PIN(150, "SDC2_CLK"), + PINCTRL_PIN(151, "SDC2_CMD"), + PINCTRL_PIN(152, "SDC2_DATA"), +}; + +#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } + +DECLARE_APQ_GPIO_PINS(0); +DECLARE_APQ_GPIO_PINS(1); +DECLARE_APQ_GPIO_PINS(2); +DECLARE_APQ_GPIO_PINS(3); +DECLARE_APQ_GPIO_PINS(4); +DECLARE_APQ_GPIO_PINS(5); +DECLARE_APQ_GPIO_PINS(6); +DECLARE_APQ_GPIO_PINS(7); +DECLARE_APQ_GPIO_PINS(8); +DECLARE_APQ_GPIO_PINS(9); +DECLARE_APQ_GPIO_PINS(10); +DECLARE_APQ_GPIO_PINS(11); +DECLARE_APQ_GPIO_PINS(12); +DECLARE_APQ_GPIO_PINS(13); +DECLARE_APQ_GPIO_PINS(14); +DECLARE_APQ_GPIO_PINS(15); +DECLARE_APQ_GPIO_PINS(16); +DECLARE_APQ_GPIO_PINS(17); +DECLARE_APQ_GPIO_PINS(18); +DECLARE_APQ_GPIO_PINS(19); +DECLARE_APQ_GPIO_PINS(20); +DECLARE_APQ_GPIO_PINS(21); +DECLARE_APQ_GPIO_PINS(22); +DECLARE_APQ_GPIO_PINS(23); +DECLARE_APQ_GPIO_PINS(24); +DECLARE_APQ_GPIO_PINS(25); +DECLARE_APQ_GPIO_PINS(26); +DECLARE_APQ_GPIO_PINS(27); +DECLARE_APQ_GPIO_PINS(28); +DECLARE_APQ_GPIO_PINS(29); +DECLARE_APQ_GPIO_PINS(30); +DECLARE_APQ_GPIO_PINS(31); +DECLARE_APQ_GPIO_PINS(32); +DECLARE_APQ_GPIO_PINS(33); +DECLARE_APQ_GPIO_PINS(34); +DECLARE_APQ_GPIO_PINS(35); +DECLARE_APQ_GPIO_PINS(36); +DECLARE_APQ_GPIO_PINS(37); +DECLARE_APQ_GPIO_PINS(38); +DECLARE_APQ_GPIO_PINS(39); +DECLARE_APQ_GPIO_PINS(40); +DECLARE_APQ_GPIO_PINS(41); +DECLARE_APQ_GPIO_PINS(42); +DECLARE_APQ_GPIO_PINS(43); +DECLARE_APQ_GPIO_PINS(44); +DECLARE_APQ_GPIO_PINS(45); +DECLARE_APQ_GPIO_PINS(46); +DECLARE_APQ_GPIO_PINS(47); +DECLARE_APQ_GPIO_PINS(48); +DECLARE_APQ_GPIO_PINS(49); +DECLARE_APQ_GPIO_PINS(50); +DECLARE_APQ_GPIO_PINS(51); +DECLARE_APQ_GPIO_PINS(52); +DECLARE_APQ_GPIO_PINS(53); +DECLARE_APQ_GPIO_PINS(54); +DECLARE_APQ_GPIO_PINS(55); +DECLARE_APQ_GPIO_PINS(56); +DECLARE_APQ_GPIO_PINS(57); +DECLARE_APQ_GPIO_PINS(58); +DECLARE_APQ_GPIO_PINS(59); +DECLARE_APQ_GPIO_PINS(60); +DECLARE_APQ_GPIO_PINS(61); +DECLARE_APQ_GPIO_PINS(62); +DECLARE_APQ_GPIO_PINS(63); +DECLARE_APQ_GPIO_PINS(64); +DECLARE_APQ_GPIO_PINS(65); +DECLARE_APQ_GPIO_PINS(66); +DECLARE_APQ_GPIO_PINS(67); +DECLARE_APQ_GPIO_PINS(68); +DECLARE_APQ_GPIO_PINS(69); +DECLARE_APQ_GPIO_PINS(70); +DECLARE_APQ_GPIO_PINS(71); +DECLARE_APQ_GPIO_PINS(72); +DECLARE_APQ_GPIO_PINS(73); +DECLARE_APQ_GPIO_PINS(74); +DECLARE_APQ_GPIO_PINS(75); +DECLARE_APQ_GPIO_PINS(76); +DECLARE_APQ_GPIO_PINS(77); +DECLARE_APQ_GPIO_PINS(78); +DECLARE_APQ_GPIO_PINS(79); +DECLARE_APQ_GPIO_PINS(80); +DECLARE_APQ_GPIO_PINS(81); +DECLARE_APQ_GPIO_PINS(82); +DECLARE_APQ_GPIO_PINS(83); +DECLARE_APQ_GPIO_PINS(84); +DECLARE_APQ_GPIO_PINS(85); +DECLARE_APQ_GPIO_PINS(86); +DECLARE_APQ_GPIO_PINS(87); +DECLARE_APQ_GPIO_PINS(88); +DECLARE_APQ_GPIO_PINS(89); +DECLARE_APQ_GPIO_PINS(90); +DECLARE_APQ_GPIO_PINS(91); +DECLARE_APQ_GPIO_PINS(92); +DECLARE_APQ_GPIO_PINS(93); +DECLARE_APQ_GPIO_PINS(94); +DECLARE_APQ_GPIO_PINS(95); +DECLARE_APQ_GPIO_PINS(96); +DECLARE_APQ_GPIO_PINS(97); +DECLARE_APQ_GPIO_PINS(98); +DECLARE_APQ_GPIO_PINS(99); +DECLARE_APQ_GPIO_PINS(100); +DECLARE_APQ_GPIO_PINS(101); +DECLARE_APQ_GPIO_PINS(102); +DECLARE_APQ_GPIO_PINS(103); +DECLARE_APQ_GPIO_PINS(104); +DECLARE_APQ_GPIO_PINS(105); +DECLARE_APQ_GPIO_PINS(106); +DECLARE_APQ_GPIO_PINS(107); +DECLARE_APQ_GPIO_PINS(108); +DECLARE_APQ_GPIO_PINS(109); +DECLARE_APQ_GPIO_PINS(110); +DECLARE_APQ_GPIO_PINS(111); +DECLARE_APQ_GPIO_PINS(112); +DECLARE_APQ_GPIO_PINS(113); +DECLARE_APQ_GPIO_PINS(114); +DECLARE_APQ_GPIO_PINS(115); +DECLARE_APQ_GPIO_PINS(116); +DECLARE_APQ_GPIO_PINS(117); +DECLARE_APQ_GPIO_PINS(118); +DECLARE_APQ_GPIO_PINS(119); +DECLARE_APQ_GPIO_PINS(120); +DECLARE_APQ_GPIO_PINS(121); +DECLARE_APQ_GPIO_PINS(122); +DECLARE_APQ_GPIO_PINS(123); +DECLARE_APQ_GPIO_PINS(124); +DECLARE_APQ_GPIO_PINS(125); +DECLARE_APQ_GPIO_PINS(126); +DECLARE_APQ_GPIO_PINS(127); +DECLARE_APQ_GPIO_PINS(128); +DECLARE_APQ_GPIO_PINS(129); +DECLARE_APQ_GPIO_PINS(130); +DECLARE_APQ_GPIO_PINS(131); +DECLARE_APQ_GPIO_PINS(132); +DECLARE_APQ_GPIO_PINS(133); +DECLARE_APQ_GPIO_PINS(134); +DECLARE_APQ_GPIO_PINS(135); +DECLARE_APQ_GPIO_PINS(136); +DECLARE_APQ_GPIO_PINS(137); +DECLARE_APQ_GPIO_PINS(138); +DECLARE_APQ_GPIO_PINS(139); +DECLARE_APQ_GPIO_PINS(140); +DECLARE_APQ_GPIO_PINS(141); +DECLARE_APQ_GPIO_PINS(142); +DECLARE_APQ_GPIO_PINS(143); +DECLARE_APQ_GPIO_PINS(144); +DECLARE_APQ_GPIO_PINS(145); +DECLARE_APQ_GPIO_PINS(146); + +static const unsigned int sdc1_clk_pins[] = { 147 }; +static const unsigned int sdc1_cmd_pins[] = { 148 }; +static const unsigned int sdc1_data_pins[] = { 149 }; +static const unsigned int sdc2_clk_pins[] = { 150 }; +static const unsigned int sdc2_cmd_pins[] = { 151 }; +static const unsigned int sdc2_data_pins[] = { 152 }; + +#define FUNCTION(fname) \ + [APQ_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + APQ_MUX_gpio, \ + APQ_MUX_##f1, \ + APQ_MUX_##f2, \ + APQ_MUX_##f3, \ + APQ_MUX_##f4, \ + APQ_MUX_##f5, \ + APQ_MUX_##f6, \ + APQ_MUX_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 0, \ + .intr_target_bit = 5, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum apq8084_functions { + APQ_MUX_adsp_ext, + APQ_MUX_audio_ref, + APQ_MUX_blsp_i2c1, + APQ_MUX_blsp_i2c2, + APQ_MUX_blsp_i2c3, + APQ_MUX_blsp_i2c4, + APQ_MUX_blsp_i2c5, + APQ_MUX_blsp_i2c6, + APQ_MUX_blsp_i2c7, + APQ_MUX_blsp_i2c8, + APQ_MUX_blsp_i2c9, + APQ_MUX_blsp_i2c10, + APQ_MUX_blsp_i2c11, + APQ_MUX_blsp_i2c12, + APQ_MUX_blsp_spi1, + APQ_MUX_blsp_spi1_cs1, + APQ_MUX_blsp_spi1_cs2, + APQ_MUX_blsp_spi1_cs3, + APQ_MUX_blsp_spi2, + APQ_MUX_blsp_spi3, + APQ_MUX_blsp_spi3_cs1, + APQ_MUX_blsp_spi3_cs2, + APQ_MUX_blsp_spi3_cs3, + APQ_MUX_blsp_spi4, + APQ_MUX_blsp_spi5, + APQ_MUX_blsp_spi6, + APQ_MUX_blsp_spi7, + APQ_MUX_blsp_spi8, + APQ_MUX_blsp_spi9, + APQ_MUX_blsp_spi10, + APQ_MUX_blsp_spi10_cs1, + APQ_MUX_blsp_spi10_cs2, + APQ_MUX_blsp_spi10_cs3, + APQ_MUX_blsp_spi11, + APQ_MUX_blsp_spi12, + APQ_MUX_blsp_uart1, + APQ_MUX_blsp_uart2, + APQ_MUX_blsp_uart3, + APQ_MUX_blsp_uart4, + APQ_MUX_blsp_uart5, + APQ_MUX_blsp_uart6, + APQ_MUX_blsp_uart7, + APQ_MUX_blsp_uart8, + APQ_MUX_blsp_uart9, + APQ_MUX_blsp_uart10, + APQ_MUX_blsp_uart11, + APQ_MUX_blsp_uart12, + APQ_MUX_blsp_uim1, + APQ_MUX_blsp_uim2, + APQ_MUX_blsp_uim3, + APQ_MUX_blsp_uim4, + APQ_MUX_blsp_uim5, + APQ_MUX_blsp_uim6, + APQ_MUX_blsp_uim7, + APQ_MUX_blsp_uim8, + APQ_MUX_blsp_uim9, + APQ_MUX_blsp_uim10, + APQ_MUX_blsp_uim11, + APQ_MUX_blsp_uim12, + APQ_MUX_cam_mclk0, + APQ_MUX_cam_mclk1, + APQ_MUX_cam_mclk2, + APQ_MUX_cam_mclk3, + APQ_MUX_cci_async, + APQ_MUX_cci_async_in0, + APQ_MUX_cci_i2c0, + APQ_MUX_cci_i2c1, + APQ_MUX_cci_timer0, + APQ_MUX_cci_timer1, + APQ_MUX_cci_timer2, + APQ_MUX_cci_timer3, + APQ_MUX_cci_timer4, + APQ_MUX_edp_hpd, + APQ_MUX_gcc_gp1, + APQ_MUX_gcc_gp2, + APQ_MUX_gcc_gp3, + APQ_MUX_gcc_obt, + APQ_MUX_gcc_vtt, + APQ_MUX_gp_mn, + APQ_MUX_gp_pdm0, + APQ_MUX_gp_pdm1, + APQ_MUX_gp_pdm2, + APQ_MUX_gp0_clk, + APQ_MUX_gp1_clk, + APQ_MUX_gpio, + APQ_MUX_hdmi_cec, + APQ_MUX_hdmi_ddc, + APQ_MUX_hdmi_dtest, + APQ_MUX_hdmi_hpd, + APQ_MUX_hdmi_rcv, + APQ_MUX_hsic, + APQ_MUX_ldo_en, + APQ_MUX_ldo_update, + APQ_MUX_mdp_vsync, + APQ_MUX_pci_e0, + APQ_MUX_pci_e0_n, + APQ_MUX_pci_e0_rst, + APQ_MUX_pci_e1, + APQ_MUX_pci_e1_rst, + APQ_MUX_pci_e1_rst_n, + APQ_MUX_pci_e1_clkreq_n, + APQ_MUX_pri_mi2s, + APQ_MUX_qua_mi2s, + APQ_MUX_sata_act, + APQ_MUX_sata_devsleep, + APQ_MUX_sata_devsleep_n, + APQ_MUX_sd_write, + APQ_MUX_sdc_emmc_mode, + APQ_MUX_sdc3, + APQ_MUX_sdc4, + APQ_MUX_sec_mi2s, + APQ_MUX_slimbus, + APQ_MUX_spdif_tx, + APQ_MUX_spkr_i2s, + APQ_MUX_spkr_i2s_ws, + APQ_MUX_spss_geni, + APQ_MUX_ter_mi2s, + APQ_MUX_tsif1, + APQ_MUX_tsif2, + APQ_MUX_uim, + APQ_MUX_uim_batt_alarm, + APQ_MUX_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146" +}; + +static const char * const adsp_ext_groups[] = { + "gpio34" +}; +static const char * const audio_ref_groups[] = { + "gpio100" +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3" +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7" +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11" +}; +static const char * const blsp_i2c4_groups[] = { + "gpio29", "gpio30" +}; +static const char * const blsp_i2c5_groups[] = { + "gpio41", "gpio42" +}; +static const char * const blsp_i2c6_groups[] = { + "gpio45", "gpio46" +}; +static const char * const blsp_i2c7_groups[] = { + "gpio132", "gpio133" +}; +static const char * const blsp_i2c8_groups[] = { + "gpio53", "gpio54" +}; +static const char * const blsp_i2c9_groups[] = { + "gpio57", "gpio58" +}; +static const char * const blsp_i2c10_groups[] = { + "gpio61", "gpio62" +}; +static const char * const blsp_i2c11_groups[] = { + "gpio65", "gpio66" +}; +static const char * const blsp_i2c12_groups[] = { + "gpio49", "gpio50" +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_spi4_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_spi5_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42" +}; +static const char * const blsp_spi6_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char * const blsp_spi7_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133" +}; +static const char * const blsp_spi8_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54" +}; +static const char * const blsp_spi9_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58" +}; +static const char * const blsp_spi10_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62" +}; +static const char * const blsp_spi11_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; +static const char * const blsp_spi12_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50" +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uart3_groups[] = { + "gpio8" +}; +static const char * const blsp_uart4_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_uart5_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42" +}; +static const char * const blsp_uart6_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char * const blsp_uart7_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133" +}; +static const char * const blsp_uart8_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54" +}; +static const char * const blsp_uart9_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58" +}; +static const char * const blsp_uart10_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62" +}; +static const char * const blsp_uart11_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; +static const char * const blsp_uart12_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50" +}; +static const char * const blsp_uim1_groups[] = { + "gpio0", "gpio1" +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5" +}; +static const char * const blsp_uim3_groups[] = { + "gpio8", "gpio9" +}; +static const char * const blsp_uim4_groups[] = { + "gpio27", "gpio28" +}; +static const char * const blsp_uim5_groups[] = { + "gpio39", "gpio40" +}; +static const char * const blsp_uim6_groups[] = { + "gpio43", "gpio44" +}; +static const char * const blsp_uim7_groups[] = { + "gpio130", "gpio131" +}; +static const char * const blsp_uim8_groups[] = { + "gpio51", "gpio52" +}; +static const char * const blsp_uim9_groups[] = { + "gpio55", "gpio56" +}; +static const char * const blsp_uim10_groups[] = { + "gpio59", "gpio60" +}; +static const char * const blsp_uim11_groups[] = { + "gpio63", "gpio64" +}; +static const char * const blsp_uim12_groups[] = { + "gpio47", "gpio48" +}; +static const char * const blsp_spi1_cs1_groups[] = { + "gpio116" +}; +static const char * const blsp_spi1_cs2_groups[] = { + "gpio117" +}; +static const char * const blsp_spi1_cs3_groups[] = { + "gpio118" +}; +static const char * const blsp_spi3_cs1_groups[] = { + "gpio67" +}; +static const char * const blsp_spi3_cs2_groups[] = { + "gpio71" +}; +static const char * const blsp_spi3_cs3_groups[] = { + "gpio72" +}; +static const char * const blsp_spi10_cs1_groups[] = { + "gpio106" +}; +static const char * const blsp_spi10_cs2_groups[] = { + "gpio111" +}; +static const char * const blsp_spi10_cs3_groups[] = { + "gpio128" +}; +static const char * const cam_mclk0_groups[] = { + "gpio15" +}; +static const char * const cam_mclk1_groups[] = { + "gpio16" +}; +static const char * const cam_mclk2_groups[] = { + "gpio17" +}; +static const char * const cam_mclk3_groups[] = { + "gpio18" +}; +static const char * const cci_async_groups[] = { + "gpio26", "gpio119" +}; +static const char * const cci_async_in0_groups[] = { + "gpio120" +}; +static const char * const cci_i2c0_groups[] = { + "gpio19", "gpio20" +}; +static const char * const cci_i2c1_groups[] = { + "gpio21", "gpio22" +}; +static const char * const cci_timer0_groups[] = { + "gpio23" +}; +static const char * const cci_timer1_groups[] = { + "gpio24" +}; +static const char * const cci_timer2_groups[] = { + "gpio25" +}; +static const char * const cci_timer3_groups[] = { + "gpio26" +}; +static const char * const cci_timer4_groups[] = { + "gpio119" +}; +static const char * const edp_hpd_groups[] = { + "gpio103" +}; +static const char * const gcc_gp1_groups[] = { + "gpio37" +}; +static const char * const gcc_gp2_groups[] = { + "gpio38" +}; +static const char * const gcc_gp3_groups[] = { + "gpio86" +}; +static const char * const gcc_obt_groups[] = { + "gpio127" +}; +static const char * const gcc_vtt_groups[] = { + "gpio126" +}; +static const char * const gp_mn_groups[] = { + "gpio29" +}; +static const char * const gp_pdm0_groups[] = { + "gpio48", "gpio83" +}; +static const char * const gp_pdm1_groups[] = { + "gpio84", "gpio101" +}; +static const char * const gp_pdm2_groups[] = { + "gpio85", "gpio110" +}; +static const char * const gp0_clk_groups[] = { + "gpio25" +}; +static const char * const gp1_clk_groups[] = { + "gpio26" +}; +static const char * const hdmi_cec_groups[] = { + "gpio31" +}; +static const char * const hdmi_ddc_groups[] = { + "gpio32", "gpio33" +}; +static const char * const hdmi_dtest_groups[] = { + "gpio123" +}; +static const char * const hdmi_hpd_groups[] = { + "gpio34" +}; +static const char * const hdmi_rcv_groups[] = { + "gpio125" +}; +static const char * const hsic_groups[] = { + "gpio134", "gpio135" +}; +static const char * const ldo_en_groups[] = { + "gpio124" +}; +static const char * const ldo_update_groups[] = { + "gpio125" +}; +static const char * const mdp_vsync_groups[] = { + "gpio12", "gpio13", "gpio14" +}; +static const char * const pci_e0_groups[] = { + "gpio68", "gpio70" +}; +static const char * const pci_e0_n_groups[] = { + "gpio68", "gpio70" +}; +static const char * const pci_e0_rst_groups[] = { + "gpio70" +}; +static const char * const pci_e1_groups[] = { + "gpio140" +}; +static const char * const pci_e1_rst_groups[] = { + "gpio140" +}; +static const char * const pci_e1_rst_n_groups[] = { + "gpio140" +}; +static const char * const pci_e1_clkreq_n_groups[] = { + "gpio141" +}; +static const char * const pri_mi2s_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", "gpio80" +}; +static const char * const qua_mi2s_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97" +}; +static const char * const sata_act_groups[] = { + "gpio129" +}; +static const char * const sata_devsleep_groups[] = { + "gpio119" +}; +static const char * const sata_devsleep_n_groups[] = { + "gpio119" +}; +static const char * const sd_write_groups[] = { + "gpio75" +}; +static const char * const sdc_emmc_mode_groups[] = { + "gpio146" +}; +static const char * const sdc3_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72" +}; +static const char * const sdc4_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85", "gpio86", + "gpio91", "gpio95", "gpio96", "gpio97", "gpio101" +}; +static const char * const sec_mi2s_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", "gpio85" +}; +static const char * const slimbus_groups[] = { + "gpio98", "gpio99" +}; +static const char * const spdif_tx_groups[] = { + "gpio124", "gpio136", "gpio142" +}; +static const char * const spkr_i2s_groups[] = { + "gpio98", "gpio99", "gpio100" +}; +static const char * const spkr_i2s_ws_groups[] = { + "gpio104" +}; +static const char * const spss_geni_groups[] = { + "gpio8", "gpio9" +}; +static const char * const ter_mi2s_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90" +}; +static const char * const tsif1_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85", "gpio86" +}; +static const char * const tsif2_groups[] = { + "gpio91", "gpio95", "gpio96", "gpio97", "gpio101" +}; +static const char * const uim_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133" +}; +static const char * const uim_batt_alarm_groups[] = { + "gpio102" +}; +static const struct msm_function apq8084_functions[] = { + FUNCTION(adsp_ext), + FUNCTION(audio_ref), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_i2c7), + FUNCTION(blsp_i2c8), + FUNCTION(blsp_i2c9), + FUNCTION(blsp_i2c10), + FUNCTION(blsp_i2c11), + FUNCTION(blsp_i2c12), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi1_cs1), + FUNCTION(blsp_spi1_cs2), + FUNCTION(blsp_spi1_cs3), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi3_cs1), + FUNCTION(blsp_spi3_cs2), + FUNCTION(blsp_spi3_cs3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_spi7), + FUNCTION(blsp_spi8), + FUNCTION(blsp_spi9), + FUNCTION(blsp_spi10), + FUNCTION(blsp_spi10_cs1), + FUNCTION(blsp_spi10_cs2), + FUNCTION(blsp_spi10_cs3), + FUNCTION(blsp_spi11), + FUNCTION(blsp_spi12), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(blsp_uart5), + FUNCTION(blsp_uart6), + FUNCTION(blsp_uart7), + FUNCTION(blsp_uart8), + FUNCTION(blsp_uart9), + FUNCTION(blsp_uart10), + FUNCTION(blsp_uart11), + FUNCTION(blsp_uart12), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim4), + FUNCTION(blsp_uim5), + FUNCTION(blsp_uim6), + FUNCTION(blsp_uim7), + FUNCTION(blsp_uim8), + FUNCTION(blsp_uim9), + FUNCTION(blsp_uim10), + FUNCTION(blsp_uim11), + FUNCTION(blsp_uim12), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cam_mclk2), + FUNCTION(cam_mclk3), + FUNCTION(cci_async), + FUNCTION(cci_async_in0), + FUNCTION(cci_i2c0), + FUNCTION(cci_i2c1), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(edp_hpd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gcc_obt), + FUNCTION(gcc_vtt), + FUNCTION(gp_mn), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gp0_clk), + FUNCTION(gp1_clk), + FUNCTION(gpio), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc), + FUNCTION(hdmi_dtest), + FUNCTION(hdmi_hpd), + FUNCTION(hdmi_rcv), + FUNCTION(hsic), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(mdp_vsync), + FUNCTION(pci_e0), + FUNCTION(pci_e0_n), + FUNCTION(pci_e0_rst), + FUNCTION(pci_e1), + FUNCTION(pci_e1_rst), + FUNCTION(pci_e1_rst_n), + FUNCTION(pci_e1_clkreq_n), + FUNCTION(pri_mi2s), + FUNCTION(qua_mi2s), + FUNCTION(sata_act), + FUNCTION(sata_devsleep), + FUNCTION(sata_devsleep_n), + FUNCTION(sd_write), + FUNCTION(sdc_emmc_mode), + FUNCTION(sdc3), + FUNCTION(sdc4), + FUNCTION(sec_mi2s), + FUNCTION(slimbus), + FUNCTION(spdif_tx), + FUNCTION(spkr_i2s), + FUNCTION(spkr_i2s_ws), + FUNCTION(spss_geni), + FUNCTION(ter_mi2s), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(uim), + FUNCTION(uim_batt_alarm), +}; + +static const struct msm_pingroup apq8084_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, spss_geni, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uim3, blsp_uart3, spss_geni, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), + PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), + PINGROUP(19, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(20, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(21, cci_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(22, cci_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(23, cci_timer0, NA, NA, NA, NA, NA, NA), + PINGROUP(24, cci_timer1, NA, NA, NA, NA, NA, NA), + PINGROUP(25, cci_timer2, gp0_clk, NA, NA, NA, NA, NA), + PINGROUP(26, cci_timer3, cci_async, gp1_clk, NA, NA, NA, NA), + PINGROUP(27, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA), + PINGROUP(28, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA), + PINGROUP(29, blsp_spi4, blsp_uart4, blsp_i2c4, gp_mn, NA, NA, NA), + PINGROUP(30, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hpd, NA, adsp_ext, NA, NA, NA, NA), + PINGROUP(35, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, gcc_gp1, NA, NA, NA, NA, NA, NA), + PINGROUP(38, gcc_gp2, NA, NA, NA, NA, NA, NA), + PINGROUP(39, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(40, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(41, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(42, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(43, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA), + PINGROUP(44, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA), + PINGROUP(45, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(46, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(47, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), + PINGROUP(48, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm0, NA, NA, NA), + PINGROUP(49, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(50, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(51, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(52, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(53, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA), + PINGROUP(54, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA), + PINGROUP(55, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA), + PINGROUP(56, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA), + PINGROUP(57, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA), + PINGROUP(58, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA), + PINGROUP(59, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA), + PINGROUP(60, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA), + PINGROUP(61, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(62, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(63, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA), + PINGROUP(64, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA), + PINGROUP(65, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(66, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(67, sdc3, blsp_spi3_cs1, NA, NA, NA, NA, NA), + PINGROUP(68, sdc3, pci_e0, NA, NA, NA, NA, NA), + PINGROUP(69, sdc3, NA, NA, NA, NA, NA, NA), + PINGROUP(70, sdc3, pci_e0_n, pci_e0, NA, NA, NA, NA), + PINGROUP(71, sdc3, blsp_spi3_cs2, NA, NA, NA, NA, NA), + PINGROUP(72, sdc3, blsp_spi3_cs3, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, sd_write, NA, NA, NA, NA, NA, NA), + PINGROUP(76, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(77, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(78, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(79, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(80, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(82, sec_mi2s, sdc4, tsif1, NA, NA, NA, NA), + PINGROUP(83, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm0), + PINGROUP(84, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm1), + PINGROUP(85, sec_mi2s, sdc4, tsif1, NA, gp_pdm2, NA, NA), + PINGROUP(86, ter_mi2s, sdc4, tsif1, NA, NA, NA, gcc_gp3), + PINGROUP(87, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(88, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(89, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(90, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(91, qua_mi2s, sdc4, tsif2, NA, NA, NA, NA), + PINGROUP(92, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(93, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(94, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(95, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp1), + PINGROUP(96, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp2), + PINGROUP(97, qua_mi2s, sdc4, tsif2, NA, gcc_gp3, NA, NA), + PINGROUP(98, slimbus, spkr_i2s, NA, NA, NA, NA, NA), + PINGROUP(99, slimbus, spkr_i2s, NA, NA, NA, NA, NA), + PINGROUP(100, audio_ref, spkr_i2s, NA, NA, NA, NA, NA), + PINGROUP(101, sdc4, tsif2, gp_pdm1, NA, NA, NA, NA), + PINGROUP(102, uim_batt_alarm, NA, NA, NA, NA, NA, NA), + PINGROUP(103, edp_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(104, spkr_i2s, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, blsp_spi10_cs1, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, gp_pdm2, NA, NA, NA, NA, NA, NA), + PINGROUP(111, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, blsp_spi1_cs1, NA, NA, NA, NA, NA, NA), + PINGROUP(117, blsp_spi1_cs2, NA, NA, NA, NA, NA, NA), + PINGROUP(118, blsp_spi1_cs3, NA, NA, NA, NA, NA, NA), + PINGROUP(119, cci_timer4, cci_async, sata_devsleep, sata_devsleep_n, NA, NA, NA), + PINGROUP(120, cci_async, NA, NA, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, hdmi_dtest, NA, NA, NA, NA, NA, NA), + PINGROUP(124, spdif_tx, ldo_en, NA, NA, NA, NA, NA), + PINGROUP(125, ldo_update, hdmi_rcv, NA, NA, NA, NA, NA), + PINGROUP(126, gcc_vtt, NA, NA, NA, NA, NA, NA), + PINGROUP(127, gcc_obt, NA, NA, NA, NA, NA, NA), + PINGROUP(128, blsp_spi10_cs3, NA, NA, NA, NA, NA, NA), + PINGROUP(129, sata_act, NA, NA, NA, NA, NA, NA), + PINGROUP(130, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(131, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(132, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(133, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(134, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(135, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(136, spdif_tx, NA, NA, NA, NA, NA, NA), + PINGROUP(137, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, pci_e1_rst_n, pci_e1_rst, NA, NA, NA, NA, NA), + PINGROUP(141, pci_e1_clkreq_n, NA, NA, NA, NA, NA, NA), + PINGROUP(142, spdif_tx, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, sdc_emmc_mode, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 147 + +static const struct msm_pinctrl_soc_data apq8084_pinctrl = { + .pins = apq8084_pins, + .npins = ARRAY_SIZE(apq8084_pins), + .functions = apq8084_functions, + .nfunctions = ARRAY_SIZE(apq8084_functions), + .groups = apq8084_groups, + .ngroups = ARRAY_SIZE(apq8084_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int apq8084_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &apq8084_pinctrl); +} + +static const struct of_device_id apq8084_pinctrl_of_match[] = { + { .compatible = "qcom,apq8084-pinctrl", }, + { }, +}; + +static struct platform_driver apq8084_pinctrl_driver = { + .driver = { + .name = "apq8084-pinctrl", + .owner = THIS_MODULE, + .of_match_table = apq8084_pinctrl_of_match, + }, + .probe = apq8084_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init apq8084_pinctrl_init(void) +{ + return platform_driver_register(&apq8084_pinctrl_driver); +} +arch_initcall(apq8084_pinctrl_init); + +static void __exit apq8084_pinctrl_exit(void) +{ + platform_driver_unregister(&apq8084_pinctrl_driver); +} +module_exit(apq8084_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match); -- cgit v1.2.3 From f712c554a7fca8f6308afbce844eacbf5e48787b Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 3 Sep 2014 19:28:16 +0300 Subject: pinctrl: qcom: Make the target processor value configurable Currently the value used to specify that interrupts from the gpio should be routed to the application processor is hardcoded for all Qualcomm SoCs. But the new APQ8084 SoC uses a different value. To resolve this, we make this value configurable for each SoC. For all existing SoCs we continue to use the current value, and only for APQ8084 we use the new value. Suggested-by: Bjorn Andersson Acked-by: Bjorn Andersson Signed-off-by: Georgi Djakov Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-apq8064.c | 2 ++ drivers/pinctrl/qcom/pinctrl-apq8084.c | 2 ++ drivers/pinctrl/qcom/pinctrl-ipq8064.c | 2 ++ drivers/pinctrl/qcom/pinctrl-msm.c | 4 +--- drivers/pinctrl/qcom/pinctrl-msm.h | 3 +++ drivers/pinctrl/qcom/pinctrl-msm8960.c | 2 ++ drivers/pinctrl/qcom/pinctrl-msm8x74.c | 2 ++ 7 files changed, 14 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index ef1263c7bdde..c832d7d6b912 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -258,6 +258,7 @@ static const unsigned int sdc3_data_pins[] = { 95 }; .intr_status_bit = 0, \ .intr_ack_high = 1, \ .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ .intr_raw_status_bit = 3, \ .intr_polarity_bit = 1, \ .intr_detection_bit = 2, \ @@ -283,6 +284,7 @@ static const unsigned int sdc3_data_pins[] = { 95 }; .intr_enable_bit = -1, \ .intr_status_bit = -1, \ .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ .intr_raw_status_bit = -1, \ .intr_polarity_bit = -1, \ .intr_detection_bit = -1, \ diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c index 5362959c448f..138cbf6134a5 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -371,6 +371,7 @@ static const unsigned int sdc2_data_pins[] = { 152 }; .intr_status_bit = 0, \ .intr_ack_high = 0, \ .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ .intr_raw_status_bit = 4, \ .intr_polarity_bit = 1, \ .intr_detection_bit = 2, \ @@ -396,6 +397,7 @@ static const unsigned int sdc2_data_pins[] = { 152 }; .intr_enable_bit = -1, \ .intr_status_bit = -1, \ .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ .intr_raw_status_bit = -1, \ .intr_polarity_bit = -1, \ .intr_detection_bit = -1, \ diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c index 767cf1120b20..81f49a9b4dbe 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -211,6 +211,7 @@ static const unsigned int sdc3_data_pins[] = { 71 }; .intr_status_bit = 0, \ .intr_ack_high = 1, \ .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ .intr_raw_status_bit = 3, \ .intr_polarity_bit = 1, \ .intr_detection_bit = 2, \ @@ -236,6 +237,7 @@ static const unsigned int sdc3_data_pins[] = { 71 }; .intr_enable_bit = -1, \ .intr_status_bit = -1, \ .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ .intr_raw_status_bit = -1, \ .intr_polarity_bit = -1, \ .intr_detection_bit = -1, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 01eab47a746f..d5ed1272b928 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -653,8 +653,6 @@ static void msm_gpio_irq_ack(struct irq_data *d) spin_unlock_irqrestore(&pctrl->lock, flags); } -#define INTR_TARGET_PROC_APPS 4 - static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -678,7 +676,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) /* Route interrupts to application cpu */ val = readl(pctrl->regs + g->intr_target_reg); val &= ~(7 << g->intr_target_bit); - val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; + val |= g->intr_target_kpss_val << g->intr_target_bit; writel(val, pctrl->regs + g->intr_target_reg); /* Update configuration for gpio. diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 7b2a227a590a..b952c4b4a8e9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -53,6 +53,8 @@ struct msm_function { * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt * status. * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. + * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from + * this gpio should get routed to the KPSS processor. * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. @@ -88,6 +90,7 @@ struct msm_pingroup { unsigned intr_ack_high:1; unsigned intr_target_bit:5; + unsigned intr_target_kpss_val:5; unsigned intr_raw_status_bit:5; unsigned intr_polarity_bit:5; unsigned intr_detection_bit:5; diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c index 35047036a053..2ab21ce5575a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -384,6 +384,7 @@ static const unsigned int sdc3_data_pins[] = { 157 }; .intr_status_bit = 0, \ .intr_ack_high = 1, \ .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ .intr_raw_status_bit = 3, \ .intr_polarity_bit = 1, \ .intr_detection_bit = 2, \ @@ -409,6 +410,7 @@ static const unsigned int sdc3_data_pins[] = { 157 }; .intr_enable_bit = -1, \ .intr_status_bit = -1, \ .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ .intr_raw_status_bit = -1, \ .intr_polarity_bit = -1, \ .intr_detection_bit = -1, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index 8c9720154d1e..3c858384d041 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -366,6 +366,7 @@ static const unsigned int sdc2_data_pins[] = { 151 }; .intr_enable_bit = 0, \ .intr_status_bit = 0, \ .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ .intr_raw_status_bit = 4, \ .intr_polarity_bit = 1, \ .intr_detection_bit = 2, \ @@ -391,6 +392,7 @@ static const unsigned int sdc2_data_pins[] = { 151 }; .intr_enable_bit = -1, \ .intr_status_bit = -1, \ .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ .intr_raw_status_bit = -1, \ .intr_polarity_bit = -1, \ .intr_detection_bit = -1, \ -- cgit v1.2.3 From 0a5d667048ab3b22dff3c60561a79310981ee897 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Sat, 30 Aug 2014 16:43:00 +0530 Subject: pinctrl: sirf: Remove gpiochip on failure cases This patch releases gpiochip related resources by calling gpiochip_remove when gpiochip_irqchip_add fails. CC: Linus Walleij CC: Barry Song CC: Rongjun Ying CC: Yuping Luo Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-sirf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 6f252fd7cb0c..b713bd59ffbb 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -853,7 +853,7 @@ static int sirfsoc_gpio_probe(struct device_node *np) if (err) { dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n"); - goto out; + goto out_banks; } for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { -- cgit v1.2.3 From c4edb116803933346d7ac5640a3f91c91158f9db Mon Sep 17 00:00:00 2001 From: Rongjun Ying Date: Tue, 2 Sep 2014 17:46:47 +0800 Subject: pinctrl: prima2: add I2S 2ch, 6ch, nodin, mclk groups we have done that for atlas6 in commit ed36c1a, 086b8904 etc. here we do same things for prima2. Signed-off-by: Rongjun Ying Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-prima2.c | 88 ++++++++++++++++++++++++++++++++--- 1 file changed, 82 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c index fda2547f205e..357678ee28e3 100644 --- a/drivers/pinctrl/sirf/pinctrl-prima2.c +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -386,12 +386,44 @@ static const struct sirfsoc_padmux cko1_padmux = { static const unsigned cko1_pins[] = { 42 }; +static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = { + { + .group = 1, + .mask = BIT(10), + }, +}; + +static const struct sirfsoc_padmux i2s_mclk_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask), + .muxmask = i2s_mclk_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(3), + .funcval = BIT(3), +}; + +static const unsigned i2s_mclk_pins[] = { 42 }; + +static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = { + { + .group = 1, + .mask = BIT(19), + }, +}; + +static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask), + .muxmask = i2s_ext_clk_input_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(2), + .funcval = BIT(2), +}; + +static const unsigned i2s_ext_clk_input_pins[] = { 51 }; + static const struct sirfsoc_muxmask i2s_muxmask[] = { { .group = 1, - .mask = - BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19) - | BIT(23) | BIT(28), + .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), }, }; @@ -399,11 +431,42 @@ static const struct sirfsoc_padmux i2s_padmux = { .muxmask_counts = ARRAY_SIZE(i2s_muxmask), .muxmask = i2s_muxmask, .ctrlreg = SIRFSOC_RSC_PIN_MUX, - .funcmask = BIT(3) | BIT(9), - .funcval = BIT(3), }; -static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 }; +static const unsigned i2s_pins[] = { 43, 44, 45, 46 }; + +static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { + { + .group = 1, + .mask = BIT(11) | BIT(12) | BIT(14), + }, +}; + +static const struct sirfsoc_padmux i2s_no_din_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), + .muxmask = i2s_no_din_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, +}; + +static const unsigned i2s_no_din_pins[] = { 43, 44, 46 }; + +static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { + { + .group = 1, + .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14) + | BIT(23) | BIT(28), + }, +}; + +static const struct sirfsoc_padmux i2s_6chn_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), + .muxmask = i2s_6chn_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(9), + .funcval = BIT(1) | BIT(9), +}; + +static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 }; static const struct sirfsoc_muxmask ac97_muxmask[] = { { @@ -926,7 +989,11 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), + SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins), + SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins), SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), + SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), + SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), SIRFSOC_PIN_GROUP("nandgrp", nand_pins), SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), @@ -980,7 +1047,11 @@ static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; static const char * const pulse_countgrp[] = { "pulse_countgrp" }; +static const char * const i2smclkgrp[] = { "i2smclkgrp" }; +static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" }; static const char * const i2sgrp[] = { "i2sgrp" }; +static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; +static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; static const char * const ac97grp[] = { "ac97grp" }; static const char * const nandgrp[] = { "nandgrp" }; static const char * const spi0grp[] = { "spi0grp" }; @@ -1037,7 +1108,12 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), + SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux), + SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp, + i2s_ext_clk_input_padmux), SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), + SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), + SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), -- cgit v1.2.3 From 4334ac2db2be9e278c95fd15260c1f49f698ffc5 Mon Sep 17 00:00:00 2001 From: Marek Roszko Date: Sat, 23 Aug 2014 23:12:04 -0400 Subject: pinctrl: at91: add drive strength configuration The SAMA5 and SAM9x5 series both have drive strength options for the PIOs. This patch adds the ability to set one of three hardware options for drive strengths of low, medium or high for the each pin. The actual current output of the chip based on the setting is defined in the datasheets and varies per pins separate from banks and with supply voltage. This patch adds three new dt-bindings that allow setting the strength when configuring pins. By default, no change will be made to the drive strength of a pin from its reset value. Due to the difference between the register addresses of the SAMA5 and SAM9x5 series, a new sama5d3-pinctrl id was added. Signed-off-by: Marek Roszko Acked-by: Nicolas Ferre Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 162 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 161 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 4839c36a3a1c..03b748ea3810 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -58,10 +58,27 @@ static int gpio_banks; #define DEGLITCH (1 << 2) #define PULL_DOWN (1 << 3) #define DIS_SCHMIT (1 << 4) +#define DRIVE_STRENGTH_SHIFT 5 +#define DRIVE_STRENGTH_MASK 0x3 +#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) #define DEBOUNCE (1 << 16) #define DEBOUNCE_VAL_SHIFT 17 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) +/** + * These defines will translated the dt binding settings to our internal + * settings. They are not necessarily the same value as the register setting. + * The actual drive strength current of low, medium and high must be looked up + * from the corresponding device datasheet. This value is different for pins + * that are even in the same banks. It is also dependent on VCC. + * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive + * strength when there is no dt config for it. + */ +#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT) +#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT) +#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT) +#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT) + /** * struct at91_pmx_func - describes AT91 pinmux functions * @name: the name of this specific function @@ -148,6 +165,9 @@ struct at91_pinctrl_mux_ops { void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); + unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); + void (*set_drivestrength)(void __iomem *pio, unsigned pin, + u32 strength); /* irq */ int (*irq_type)(struct irq_data *d, unsigned type); }; @@ -315,6 +335,30 @@ static unsigned pin_to_mask(unsigned int pin) return 1 << pin; } +static unsigned two_bit_pin_value_shift_amount(unsigned int pin) +{ + /* return the shift value for a pin for "two bit" per pin registers, + * i.e. drive strength */ + return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) + ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); +} + +static unsigned sama5d3_get_drive_register(unsigned int pin) +{ + /* drive strength is split between two registers + * with two bits per pin */ + return (pin >= MAX_NB_GPIO_PER_BANK/2) + ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; +} + +static unsigned at91sam9x5_get_drive_register(unsigned int pin) +{ + /* drive strength is split between two registers + * with two bits per pin */ + return (pin >= MAX_NB_GPIO_PER_BANK/2) + ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; +} + static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) { writel_relaxed(mask, pio + PIO_IDR); @@ -468,6 +512,79 @@ static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; } +static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) +{ + unsigned tmp = __raw_readl(reg); + + tmp = tmp >> two_bit_pin_value_shift_amount(pin); + + return tmp & DRIVE_STRENGTH_MASK; +} + +static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, + unsigned pin) +{ + unsigned tmp = read_drive_strength(pio + + sama5d3_get_drive_register(pin), pin); + + /* SAMA5 strength is 1:1 with our defines, + * except 0 is equivalent to low per datasheet */ + if (!tmp) + tmp = DRIVE_STRENGTH_LOW; + + return tmp; +} + +static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, + unsigned pin) +{ + unsigned tmp = read_drive_strength(pio + + at91sam9x5_get_drive_register(pin), pin); + + /* strength is inverse in SAM9x5s hardware with the pinctrl defines + * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ + tmp = DRIVE_STRENGTH_HI - tmp; + + return tmp; +} + +static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) +{ + unsigned tmp = __raw_readl(reg); + unsigned shift = two_bit_pin_value_shift_amount(pin); + + tmp &= ~(DRIVE_STRENGTH_MASK << shift); + tmp |= strength << shift; + + __raw_writel(tmp, reg); +} + +static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, + u32 setting) +{ + /* do nothing if setting is zero */ + if (!setting) + return; + + /* strength is 1 to 1 with setting for SAMA5 */ + set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); +} + +static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, + u32 setting) +{ + /* do nothing if setting is zero */ + if (!setting) + return; + + /* strength is inverse on SAM9x5s with our defines + * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ + setting = DRIVE_STRENGTH_HI - setting; + + set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, + setting); +} + static struct at91_pinctrl_mux_ops at91rm9200_ops = { .get_periph = at91_mux_get_periph, .mux_A_periph = at91_mux_set_A_periph, @@ -491,6 +608,27 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = { .set_pulldown = at91_mux_pio3_set_pulldown, .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, + .get_drivestrength = at91_mux_sam9x5_get_drivestrength, + .set_drivestrength = at91_mux_sam9x5_set_drivestrength, + .irq_type = alt_gpio_irq_type, +}; + +static struct at91_pinctrl_mux_ops sama5d3_ops = { + .get_periph = at91_mux_pio3_get_periph, + .mux_A_periph = at91_mux_pio3_set_A_periph, + .mux_B_periph = at91_mux_pio3_set_B_periph, + .mux_C_periph = at91_mux_pio3_set_C_periph, + .mux_D_periph = at91_mux_pio3_set_D_periph, + .get_deglitch = at91_mux_pio3_get_deglitch, + .set_deglitch = at91_mux_pio3_set_deglitch, + .get_debounce = at91_mux_pio3_get_debounce, + .set_debounce = at91_mux_pio3_set_debounce, + .get_pulldown = at91_mux_pio3_get_pulldown, + .set_pulldown = at91_mux_pio3_set_pulldown, + .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, + .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, + .get_drivestrength = at91_mux_sama5d3_get_drivestrength, + .set_drivestrength = at91_mux_sama5d3_set_drivestrength, .irq_type = alt_gpio_irq_type, }; @@ -716,6 +854,9 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev, *config |= PULL_DOWN; if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) *config |= DIS_SCHMIT; + if (info->ops->get_drivestrength) + *config |= (info->ops->get_drivestrength(pio, pin) + << DRIVE_STRENGTH_SHIFT); return 0; } @@ -729,6 +870,7 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev, void __iomem *pio; int i; unsigned long config; + unsigned pin; for (i = 0; i < num_configs; i++) { config = configs[i]; @@ -737,7 +879,8 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config); pio = pin_to_controller(info, pin_to_bank(pin_id)); - mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); + pin = pin_id % MAX_NB_GPIO_PER_BANK; + mask = pin_to_mask(pin); if (config & PULL_UP && config & PULL_DOWN) return -EINVAL; @@ -753,6 +896,10 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev, info->ops->set_pulldown(pio, mask, config & PULL_DOWN); if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) info->ops->disable_schmitt_trig(pio, mask); + if (info->ops->set_drivestrength) + info->ops->set_drivestrength(pio, pin, + (config & DRIVE_STRENGTH) + >> DRIVE_STRENGTH_SHIFT); } /* for each config */ @@ -768,6 +915,15 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev, } \ } while (0) +#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \ + if ((config & mask) == flag) { \ + if (num_conf) \ + seq_puts(s, "|"); \ + seq_puts(s, #flag); \ + num_conf++; \ + } \ +} while (0) + static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { @@ -781,6 +937,9 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, DBG_SHOW_FLAG(PULL_DOWN); DBG_SHOW_FLAG(DIS_SCHMIT); DBG_SHOW_FLAG(DEGLITCH); + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW); + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED); + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI); DBG_SHOW_FLAG(DEBOUNCE); if (config & DEBOUNCE) { val = config >> DEBOUNCE_VAL_SHIFT; @@ -945,6 +1104,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np, } static struct of_device_id at91_pinctrl_of_match[] = { + { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, { /* sentinel */ } -- cgit v1.2.3 From 9e3a979f03b37b8502da6cfce8581e28375cf96f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 5 Sep 2014 09:53:23 +0200 Subject: pinctrl: single: fix freudian slip commit 03e9f0cac5da6af85758276cb4624caf5911f2b9 "pinctrl: clean up after enable refactoring" renamed the vtable callback .enable to .set_mux. The renaming was done manually, and one of the alterations contained a freudian slip. I confess, I am human. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 9032422ad18f..fb94b772ad62 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -519,7 +519,7 @@ static const struct pinmux_ops pcs_pinmux_ops = { .get_functions_count = pcs_get_functions_count, .get_function_name = pcs_get_function_name, .get_function_groups = pcs_get_function_groups, - .set_mux = pcs_sex_mux, + .set_mux = pcs_set_mux, .gpio_request_enable = pcs_request_gpio, }; -- cgit v1.2.3 From 1f81bdc7a08e7aee271a4969f451207fd7946894 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Sat, 30 Aug 2014 23:05:13 +0530 Subject: pinctrl: adi2: Remove duplicate gpiochip_remove_pin_ranges This patch removes call to gpiochip_remove_pin_ranges() from platform_driver remove function as it will anway be called by gpiochip_remove(). CC: Sonic Zhang CC: Linus Walleij Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-adi2.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index e02943b0285d..8434439c5017 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -1041,7 +1041,6 @@ static int adi_gpio_remove(struct platform_device *pdev) u8 offset; list_del(&port->node); - gpiochip_remove_pin_ranges(&port->chip); gpiochip_remove(&port->chip); if (port->pint) { for (offset = 0; offset < port->width; offset++) -- cgit v1.2.3 From 02b837ffe033ed3b50787e0f3e4103ea5a34636b Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Sun, 31 Aug 2014 16:51:52 +0530 Subject: pinctrl: at91: Switch to using managed clk_get This patch switches to using managed version of clk_get and hence removes clk_put from failure path. CC: Jean-Christophe Plagniol-Villard CC: Linus Walleij Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 03b748ea3810..22b82ad4461c 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1735,14 +1735,14 @@ static int at91_gpio_probe(struct platform_device *pdev) at91_chip->pioc_virq = irq; at91_chip->pioc_idx = alias_idx; - at91_chip->clock = clk_get(&pdev->dev, NULL); + at91_chip->clock = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(at91_chip->clock)) { dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); goto err; } if (clk_prepare(at91_chip->clock)) - goto clk_prep_err; + goto err; /* enable PIO controller's clock */ if (clk_enable(at91_chip->clock)) { @@ -1805,8 +1805,6 @@ static int at91_gpio_probe(struct platform_device *pdev) clk_err: clk_unprepare(at91_chip->clock); -clk_prep_err: - clk_put(at91_chip->clock); err: dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); -- cgit v1.2.3 From 41939e699c507a3441625862d125eb348f5319e0 Mon Sep 17 00:00:00 2001 From: Mathias Nyman Date: Mon, 11 Aug 2014 16:51:55 +0300 Subject: pinctrl: baytrail: resolve unbalanced IRQ wake disable warning Add the IRQCHIP_SKIP_SET_WAKE flag to baytrail gpio irq_chip to resolve unbalaced IRQ wake disable warnings. Suggested-by: Borun Fu Signed-off-by: Mathias Nyman Reviewed-by: Mika Westerberg Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-baytrail.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c index 9ca59a018743..e12e5b07f6d7 100644 --- a/drivers/pinctrl/pinctrl-baytrail.c +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -461,6 +461,7 @@ static struct irq_chip byt_irqchip = { .irq_mask = byt_irq_mask, .irq_unmask = byt_irq_unmask, .irq_set_type = byt_irq_type, + .flags = IRQCHIP_SKIP_SET_WAKE, }; static void byt_gpio_irq_init_hw(struct byt_gpio *vg) -- cgit v1.2.3 From 3ccc11f6b82c34646c8a4233278251d9e9e99390 Mon Sep 17 00:00:00 2001 From: Sean Paul Date: Tue, 9 Sep 2014 15:58:45 -0400 Subject: pinctrl: tegra: Add MIPI pad control This patch adds MIPI CSI/DSIB pad control mux register from the APB misc block to tegra pinctrl. Without writing to this register, the dsib pads are muxed as csi, and cannot be used. The register is not yet documented in the TRM, here is the description: 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0 [31:02] RESERVED [01:01] DSIB_MODE [CSI=0,DSIB=1] [00:00] RESERVED Signed-off-by: Sean Paul Acked-by: Stephen Warren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-tegra124.c | 67 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c index cb3e596cade1..2f9b75c14967 100644 --- a/drivers/pinctrl/pinctrl-tegra124.c +++ b/drivers/pinctrl/pinctrl-tegra124.c @@ -224,6 +224,16 @@ #define TEGRA_PIN_OWR _PIN(5) #define TEGRA_PIN_CLK_32K_IN _PIN(6) #define TEGRA_PIN_JTAG_RTCK _PIN(7) +#define TEGRA_PIN_DSI_B_CLK_P _PIN(8) +#define TEGRA_PIN_DSI_B_CLK_N _PIN(9) +#define TEGRA_PIN_DSI_B_D0_P _PIN(10) +#define TEGRA_PIN_DSI_B_D0_N _PIN(11) +#define TEGRA_PIN_DSI_B_D1_P _PIN(12) +#define TEGRA_PIN_DSI_B_D1_N _PIN(13) +#define TEGRA_PIN_DSI_B_D2_P _PIN(14) +#define TEGRA_PIN_DSI_B_D2_N _PIN(15) +#define TEGRA_PIN_DSI_B_D3_P _PIN(16) +#define TEGRA_PIN_DSI_B_D3_N _PIN(17) static const struct pinctrl_pin_desc tegra124_pins[] = { PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), @@ -417,6 +427,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = { PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"), PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"), }; static const unsigned clk_32k_out_pa0_pins[] = { @@ -1495,6 +1515,19 @@ static const unsigned drive_ao4_pins[] = { TEGRA_PIN_JTAG_RTCK, }; +static const unsigned mipi_pad_ctrl_dsi_b_pins[] = { + TEGRA_PIN_DSI_B_CLK_P, + TEGRA_PIN_DSI_B_CLK_N, + TEGRA_PIN_DSI_B_D0_P, + TEGRA_PIN_DSI_B_D0_N, + TEGRA_PIN_DSI_B_D1_P, + TEGRA_PIN_DSI_B_D1_N, + TEGRA_PIN_DSI_B_D2_P, + TEGRA_PIN_DSI_B_D2_N, + TEGRA_PIN_DSI_B_D3_P, + TEGRA_PIN_DSI_B_D3_N, +}; + enum tegra_mux { TEGRA_MUX_BLINK, TEGRA_MUX_CCLA, @@ -1580,6 +1613,8 @@ enum tegra_mux { TEGRA_MUX_VI_ALT3, TEGRA_MUX_VIMCLK2, TEGRA_MUX_VIMCLK2_ALT, + TEGRA_MUX_CSI, + TEGRA_MUX_DSI_B, }; #define FUNCTION(fname) \ @@ -1672,10 +1707,13 @@ static struct tegra_function tegra124_functions[] = { FUNCTION(vi_alt3), FUNCTION(vimclk2), FUNCTION(vimclk2_alt), + FUNCTION(csi), + FUNCTION(dsi_b), }; #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ #define PINGROUP_REG_A 0x3000 /* bank 1 */ +#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */ #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) @@ -1744,6 +1782,32 @@ static struct tegra_function tegra124_functions[] = { .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ } +#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A) + +#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \ + { \ + .name = "mipi_pad_ctrl_" #pg_name, \ + .pins = mipi_pad_ctrl_##pg_name##_pins, \ + .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_RSVD3, \ + TEGRA_MUX_RSVD4, \ + }, \ + .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \ + .mux_bank = 2, \ + .mux_bit = b, \ + .pupd_reg = -1, \ + .tri_reg = -1, \ + .einput_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = -1, \ + .drv_reg = -1, \ + } + static const struct tegra_pingroup tegra124_groups[] = { /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */ PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N), @@ -1979,6 +2043,9 @@ static const struct tegra_pingroup tegra124_groups[] = { DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), + + /* pg_name, r b f0, f1 */ + MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B) }; static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { -- cgit v1.2.3 From 3dac1918a4912cea9375e76cb3916b751cef22db Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sat, 6 Sep 2014 18:25:04 +0200 Subject: pinctrl: imx: detect uninitialized pins The pinctrl driver initialized the register offsets for the pins with 0. On Vybrid an offset of 0 is a valid offset for the pinctrl mux register. So far, this was solved using the ZERO_OFFSET_VALID flag which allowed offsets of 0. However, this does not allow to verify whether a pins struct imx_pmx_func was initialized or not. Use signed offset values for register offsets and initialize those with -1 in order to detect uninitialized offset values reliable. Signed-off-by: Stefan Agner Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 9 +++++---- drivers/pinctrl/freescale/pinctrl-imx.h | 7 +++---- drivers/pinctrl/freescale/pinctrl-vf610.c | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index e89268c09e4c..f2446769247f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -204,7 +204,7 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, pin_id = pin->pin; pin_reg = &info->pin_regs[pin_id]; - if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) { + if (pin_reg->mux_reg == -1) { dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", info->pins[pin_id].name); return -EINVAL; @@ -308,7 +308,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, const struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; - if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { + if (pin_reg->conf_reg == -1) { dev_err(info->dev, "Pin(%s) does not support config function\n", info->pins[pin_id].name); return -EINVAL; @@ -331,7 +331,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; int i; - if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { + if (pin_reg->conf_reg == -1) { dev_err(info->dev, "Pin(%s) does not support config function\n", info->pins[pin_id].name); return -EINVAL; @@ -586,10 +586,11 @@ int imx_pinctrl_probe(struct platform_device *pdev, if (!ipctl) return -ENOMEM; - info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) * + info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * info->npins, GFP_KERNEL); if (!info->pin_regs) return -ENOMEM; + memset(info->pin_regs, 0xff, sizeof(*info->pin_regs) * info->npins); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ipctl->base = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index db408b057000..49e55d39f7c8 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -67,8 +67,8 @@ struct imx_pmx_func { * @conf_reg: config register offset */ struct imx_pin_reg { - u16 mux_reg; - u16 conf_reg; + s16 mux_reg; + s16 conf_reg; }; struct imx_pinctrl_soc_info { @@ -83,8 +83,7 @@ struct imx_pinctrl_soc_info { unsigned int flags; }; -#define ZERO_OFFSET_VALID 0x1 -#define SHARE_MUX_CONF_REG 0x2 +#define SHARE_MUX_CONF_REG 0x1 #define NO_MUX 0x0 #define NO_PAD 0x0 diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index bddd913d28ba..b788e1578954 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -299,7 +299,7 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = { static struct imx_pinctrl_soc_info vf610_pinctrl_info = { .pins = vf610_pinctrl_pads, .npins = ARRAY_SIZE(vf610_pinctrl_pads), - .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, + .flags = SHARE_MUX_CONF_REG, }; static struct of_device_id vf610_pinctrl_of_match[] = { -- cgit v1.2.3 From 849a8c25c80a2cde824072813bf4aabbc79b8789 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Tue, 9 Sep 2014 13:35:52 +0530 Subject: pinctrl: lantiq: Release gpiochip resources in fail case This patch releases gpiochip resources with of_gpiochip_remove and gpiochip_remove in failure cases. CC: John Crispin CC: Linus Walleij Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-xway.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index e66f4cae7633..37040ab42890 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -801,6 +801,7 @@ static int pinmux_xway_probe(struct platform_device *pdev) of_gpiochip_add(&xway_chip); ret = gpiochip_add(&xway_chip); if (ret) { + of_gpiochip_remove(&xway_chip); dev_err(&pdev->dev, "Failed to register gpio chip\n"); return ret; } @@ -822,6 +823,7 @@ static int pinmux_xway_probe(struct platform_device *pdev) /* register with the generic lantiq layer */ ret = ltq_pinctrl_register(pdev, &xway_info); if (ret) { + gpiochip_remove(&xway_chip); dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); return ret; } -- cgit v1.2.3 From 70e4197420a154a2a684b6e7b496dda70b20d9ec Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Tue, 9 Sep 2014 15:50:36 +0530 Subject: pinctrl: at91: Fix failure path in at91_gpio_probe path This fixes the whole error handling in probe function by capturing and returning error values on kernel function like clk_prepare, clk_enable, gpiochip_add etc. CC: Jean-Christophe Plagniol-Villard CC: Linus Walleij Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 22b82ad4461c..71a8e8c4f19c 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1738,16 +1738,19 @@ static int at91_gpio_probe(struct platform_device *pdev) at91_chip->clock = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(at91_chip->clock)) { dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); + ret = PTR_ERR(at91_chip->clock); goto err; } - if (clk_prepare(at91_chip->clock)) - goto err; + ret = clk_prepare(at91_chip->clock); + if (ret) + goto clk_prepare_err; /* enable PIO controller's clock */ - if (clk_enable(at91_chip->clock)) { + ret = clk_enable(at91_chip->clock); + if (ret) { dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); - goto clk_err; + goto clk_enable_err; } at91_chip->chip = at91_gpio_template; @@ -1772,7 +1775,7 @@ static int at91_gpio_probe(struct platform_device *pdev) if (!names) { ret = -ENOMEM; - goto clk_err; + goto clk_enable_err; } for (i = 0; i < chip->ngpio; i++) @@ -1790,7 +1793,7 @@ static int at91_gpio_probe(struct platform_device *pdev) ret = gpiochip_add(chip); if (ret) - goto clk_err; + goto gpiochip_add_err; gpio_chips[alias_idx] = at91_chip; gpio_banks = max(gpio_banks, alias_idx + 1); @@ -1803,8 +1806,11 @@ static int at91_gpio_probe(struct platform_device *pdev) return 0; -clk_err: +gpiochip_add_err: + clk_disable(at91_chip->clock); +clk_enable_err: clk_unprepare(at91_chip->clock); +clk_prepare_err: err: dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); -- cgit v1.2.3 From 834e1678649db1e064ee397cca161a65bacfa801 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Tue, 9 Sep 2014 15:50:37 +0530 Subject: pinctrl: at91: Fix error handling while doing gpiochio_irqchip_add This patch removes a call to panic function when gpiochio_irqchip_add fails and just returns the error to the calling function. Same return value is used to handle the error case and adds a lable to release resources on error. The error message has been improved to indicate failure to add irqchip to gpiochip. This also changes first argument to function at91_gpio_of_irq_setup from struct device_node to struct platform_device. Because The device_node argument was anyway not being used. Passed pdev so that on failure dev_err can use &pdev->dev and log can be associated with proper device. CC: Jean-Christophe Plagniol-Villard CC: Linus Walleij Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 71a8e8c4f19c..51d094cc3f10 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1605,7 +1605,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) /* now it may re-trigger */ } -static int at91_gpio_of_irq_setup(struct device_node *node, +static int at91_gpio_of_irq_setup(struct platform_device *pdev, struct at91_gpio_chip *at91_gpio) { struct at91_gpio_chip *prev = NULL; @@ -1630,9 +1630,11 @@ static int at91_gpio_of_irq_setup(struct device_node *node, 0, handle_edge_irq, IRQ_TYPE_EDGE_BOTH); - if (ret) - panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", + if (ret) { + dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n", at91_gpio->pioc_idx); + return ret; + } /* Setup chained handler */ if (at91_gpio->pioc_idx) @@ -1800,12 +1802,16 @@ static int at91_gpio_probe(struct platform_device *pdev) at91_gpio_probe_fixup(); - at91_gpio_of_irq_setup(np, at91_chip); + ret = at91_gpio_of_irq_setup(pdev, at91_chip); + if (ret) + goto irq_setup_err; dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); return 0; +irq_setup_err: + gpiochip_remove(chip); gpiochip_add_err: clk_disable(at91_chip->clock); clk_enable_err: -- cgit v1.2.3 From 7471725f618b95d2a61a4bf789dbdc5c7805ffa9 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Tue, 9 Sep 2014 13:21:40 +0530 Subject: pinctrl: st: remove gpiochip in failure cases This patch releases gpiochip related resources by calling gpiochip_remove when gpiochip_irqchip_add fails. Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Bjorn Andersson Acked-by: Srinivas Kandagatla Signed-off-by: Pramod Gurav Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 6c4c41bed1e3..4b1792aad3d8 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1517,6 +1517,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, 0, handle_simple_irq, IRQ_TYPE_LEVEL_LOW); if (err) { + gpiochip_remove(&bank->gpio_chip); dev_info(dev, "could not add irqchip\n"); return err; } -- cgit v1.2.3 From 3d78427397daea47b5a38642f46f75ef993de571 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 11 Sep 2014 16:40:15 +0200 Subject: pinctrl: at91: disable PD or PU before enabling PU or PD Disable Pull-Down or Pull-Up property before enabling Pull-Up or Pull-Down, because the pin's Pull-Up and Pull-Down property is mutually exclusive. Signed-off-by: Wenyou Yang Acked-by: Nicolas Ferre Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 51d094cc3f10..09de74964276 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -371,6 +371,9 @@ static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) { + if (on) + writel_relaxed(mask, pio + PIO_PPDDR); + writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); } @@ -499,6 +502,9 @@ static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) { + if (is_on) + __raw_writel(mask, pio + PIO_PUDR); + __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); } -- cgit v1.2.3 From 6064b1474ef3cfa523916008b5176026bbc990d3 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 10 Sep 2014 11:15:51 +0200 Subject: pinctrl: berlin: fix the dt_free_map function The berlin_pinctrl_dt_free_map function tries to free memory allocated and handled by the of subsystem. This is wrong and already handled by pinctrl_dt_free_maps() which calls of_node_put(). This patch fixes the Berlin pinctrl way of freeing its maps, avoiding a kernel BUG(), by using the common pinctrl_utils_dt_free_map function instead. Signed-off-by: Antoine Tenart Acked-by: Sebastian Hesselbarth Signed-off-by: Linus Walleij --- drivers/pinctrl/berlin/berlin.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index 61f1bf0e60ba..7f0b0f93242b 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -99,30 +99,11 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev, return 0; } -static void berlin_pinctrl_dt_free_map(struct pinctrl_dev *pctrl_dev, - struct pinctrl_map *map, - unsigned nmaps) -{ - int i; - - for (i = 0; i < nmaps; i++) { - if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) { - kfree(map[i].data.mux.group); - - /* a function can be applied to multiple groups */ - if (i == 0) - kfree(map[i].data.mux.function); - } - } - - kfree(map); -} - static const struct pinctrl_ops berlin_pinctrl_ops = { .get_groups_count = &berlin_pinctrl_get_group_count, .get_group_name = &berlin_pinctrl_get_group_name, .dt_node_to_map = &berlin_pinctrl_dt_node_to_map, - .dt_free_map = &berlin_pinctrl_dt_free_map, + .dt_free_map = &pinctrl_utils_dt_free_map, }; static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev) -- cgit v1.2.3 From 0a332c96c29c84cd9205c29dfa1add4667456059 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 11 Sep 2014 00:55:55 +0300 Subject: pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation The SoC data structure allocated at init time only holds a regulator pointer that is only used in the init function. Replace it with a local variable and get rid of the SoC data structure allocation altogether. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/core.c | 10 +--------- drivers/pinctrl/sh-pfc/core.h | 1 - drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 19 ++++--------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 1 - 4 files changed, 5 insertions(+), 26 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index b9b464d0578c..6572c233f73d 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -542,7 +542,7 @@ static int sh_pfc_probe(struct platform_device *pdev) */ ret = sh_pfc_register_pinctrl(pfc); if (unlikely(ret != 0)) - goto error; + return ret; #ifdef CONFIG_GPIO_SH_PFC /* @@ -564,11 +564,6 @@ static int sh_pfc_probe(struct platform_device *pdev) dev_info(pfc->dev, "%s support registered\n", info->name); return 0; - -error: - if (info->ops && info->ops->exit) - info->ops->exit(pfc); - return ret; } static int sh_pfc_remove(struct platform_device *pdev) @@ -580,9 +575,6 @@ static int sh_pfc_remove(struct platform_device *pdev) #endif sh_pfc_unregister_pinctrl(pfc); - if (pfc->info->ops && pfc->info->ops->exit) - pfc->info->ops->exit(pfc); - return 0; } diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index b7b0e6ccf305..3daaa5241c47 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -33,7 +33,6 @@ struct sh_pfc_pin_range { struct sh_pfc { struct device *dev; const struct sh_pfc_soc_info *info; - void *soc_data; spinlock_t lock; unsigned int num_windows; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 2dd8fd524a80..d2efbfb776ac 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3824,35 +3824,24 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, * SoC information */ -struct sh73a0_pinmux_data { - struct regulator_dev *vccq_mc0; -}; - static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) { - struct sh73a0_pinmux_data *data; struct regulator_config cfg = { }; + struct regulator_dev *vccq; int ret; - data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL); - if (data == NULL) - return -ENOMEM; - cfg.dev = pfc->dev; cfg.init_data = &sh73a0_vccq_mc0_init_data; cfg.driver_data = pfc; - data->vccq_mc0 = devm_regulator_register(pfc->dev, - &sh73a0_vccq_mc0_desc, &cfg); - if (IS_ERR(data->vccq_mc0)) { - ret = PTR_ERR(data->vccq_mc0); + vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg); + if (IS_ERR(vccq)) { + ret = PTR_ERR(vccq); dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", ret); return ret; } - pfc->soc_data = data; - return 0; } diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index d482c40b012a..5b7283182c1e 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -116,7 +116,6 @@ struct sh_pfc; struct sh_pfc_soc_operations { int (*init)(struct sh_pfc *pfc); - void (*exit)(struct sh_pfc *pfc); unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); -- cgit v1.2.3 From 2fcea6cecbc965b4e02a39537d9d939f5251bbbd Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 16 Sep 2014 15:05:41 -0700 Subject: pinctrl: remove remaining users of gpiochip_remove() retval Some drivers accidentally still use the return value from gpiochip_remove(). Get rid of them so we can simplify this function and get rid of the return value. Cc: Abdoulaye Berthe Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 14 ++------------ drivers/pinctrl/nomadik/pinctrl-nomadik.c | 2 +- drivers/pinctrl/qcom/pinctrl-msm.c | 9 +-------- drivers/pinctrl/samsung/pinctrl-exynos5440.c | 6 +----- drivers/pinctrl/samsung/pinctrl-samsung.c | 15 ++++----------- drivers/pinctrl/sirf/pinctrl-sirf.c | 3 +-- 6 files changed, 10 insertions(+), 39 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index a53a689a2bfa..7df34b70e8b6 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -1298,10 +1298,7 @@ static int abx500_gpio_probe(struct platform_device *pdev) return 0; out_rem_chip: - err = gpiochip_remove(&pct->chip); - if (err) - dev_info(&pdev->dev, "failed to remove gpiochip\n"); - + gpiochip_remove(&pct->chip); return ret; } @@ -1312,15 +1309,8 @@ out_rem_chip: static int abx500_gpio_remove(struct platform_device *pdev) { struct abx500_pinctrl *pct = platform_get_drvdata(pdev); - int ret; - - ret = gpiochip_remove(&pct->chip); - if (ret < 0) { - dev_err(pct->dev, "unable to remove gpiochip: %d\n", - ret); - return ret; - } + gpiochip_remove(&pct->chip); return 0; } diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index e7cab07eef47..4332b38c52ab 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1261,7 +1261,7 @@ static int nmk_gpio_probe(struct platform_device *dev) IRQ_TYPE_EDGE_FALLING); if (ret) { dev_err(&dev->dev, "could not add irqchip\n"); - ret = gpiochip_remove(&nmk_chip->chip); + gpiochip_remove(&nmk_chip->chip); return -ENODEV; } /* Then register the chain on the parent IRQ */ diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 2738108caff2..041677113a48 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -903,16 +903,9 @@ EXPORT_SYMBOL(msm_pinctrl_probe); int msm_pinctrl_remove(struct platform_device *pdev) { struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); - int ret; - - ret = gpiochip_remove(&pctrl->chip); - if (ret) { - dev_err(&pdev->dev, "Failed to remove gpiochip\n"); - return ret; - } + gpiochip_remove(&pctrl->chip); pinctrl_unregister(pctrl->pctrl); - return 0; } EXPORT_SYMBOL(msm_pinctrl_remove); diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c index 603da2f9dd95..8ef370244aee 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -873,11 +873,7 @@ static int exynos5440_gpiolib_register(struct platform_device *pdev, static int exynos5440_gpiolib_unregister(struct platform_device *pdev, struct exynos5440_pinctrl_priv_data *priv) { - int ret = gpiochip_remove(priv->gc); - if (ret) { - dev_err(&pdev->dev, "gpio chip remove failed\n"); - return ret; - } + gpiochip_remove(priv->gc); return 0; } diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index b07406da333c..83faddf456e0 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -945,9 +945,7 @@ static int samsung_gpiolib_register(struct platform_device *pdev, fail: for (--i, --bank; i >= 0; --i, --bank) - if (gpiochip_remove(&bank->gpio_chip)) - dev_err(&pdev->dev, "gpio chip %s remove failed\n", - bank->gpio_chip.label); + gpiochip_remove(&bank->gpio_chip); return ret; } @@ -957,16 +955,11 @@ static int samsung_gpiolib_unregister(struct platform_device *pdev, { struct samsung_pin_ctrl *ctrl = drvdata->ctrl; struct samsung_pin_bank *bank = ctrl->pin_banks; - int ret = 0; int i; - for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) - ret = gpiochip_remove(&bank->gpio_chip); - - if (ret) - dev_err(&pdev->dev, "gpio chip remove failed\n"); - - return ret; + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) + gpiochip_remove(&bank->gpio_chip); + return 0; } static const struct of_device_id samsung_pinctrl_dt_match[]; diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 4c1d7c68666d..25eefdbb76b6 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -877,8 +877,7 @@ static int sirfsoc_gpio_probe(struct device_node *np) out_no_range: out_banks: - if (gpiochip_remove(&sgpio->chip.gc)) - dev_err(&pdev->dev, "could not remove gpio chip\n"); + gpiochip_remove(&sgpio->chip.gc); out: iounmap(regs); return err; -- cgit v1.2.3 From e4742d5769e7f502f1b928b759ddecabf03375d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 24 Sep 2014 10:15:24 +0200 Subject: pinctrl: bcm281xx: make Kconfig dependency more strict MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver is only useful on BCM281xx, so let the driver depend on ARCH_BCM_MOBILE but allow compile coverage testing. The main benefit is that the driver isn't available to be selected for machines that don't have the matching hardware. Signed-off-by: Uwe Kleine-König Reviewed-by: Sherman Yin Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index bfd2c2e9f6cd..a95d5ca6d830 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -86,7 +86,7 @@ config PINCTRL_BCM2835 config PINCTRL_BCM281XX bool "Broadcom BCM281xx pinctrl driver" - depends on OF + depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST) select PINMUX select PINCONF select GENERIC_PINCONF -- cgit v1.2.3 From cf1fc187628913070c3e418ce0e205732435aa2f Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Tue, 23 Sep 2014 15:59:53 -0500 Subject: pinctrl: qcom: use restart_notifier mechanism for ps_hold By converting to the restart_notifier mechanism for restart, we allow for other mechanisms, like the watchdog, to be used for restart in the case where PS_HOLD has failed to reset the chip. Since this mechanism may be one of several mechanisms registered, change the post-ps_hold write timeout to be a more reasonable 1 second instead of 10 seconds. Choose priority 128, as according to documentation, this mechanism "is sufficient to restart the entire system". Tested-by: Pramod Gurav Signed-off-by: Josh Cartwright Acked-by: Bjorn Andersson Reviewed-by: Guenter Roeck Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index d5ed1272b928..d30dddd21323 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -27,8 +27,7 @@ #include #include #include - -#include +#include #include "../core.h" #include "../pinconf.h" @@ -43,6 +42,7 @@ * @dev: device handle. * @pctrl: pinctrl handle. * @chip: gpiochip handle. + * @restart_nb: restart notifier block. * @irq: parent irq for the TLMM irq_chip. * @lock: Spinlock to protect register resources as well * as msm_pinctrl data structures. @@ -56,6 +56,7 @@ struct msm_pinctrl { struct device *dev; struct pinctrl_dev *pctrl; struct gpio_chip chip; + struct notifier_block restart_nb; int irq; spinlock_t lock; @@ -852,13 +853,14 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) return 0; } -#ifdef CONFIG_ARM -static void __iomem *msm_ps_hold; - -static void msm_reset(enum reboot_mode reboot_mode, const char *cmd) +static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, + void *data) { - writel(0, msm_ps_hold); - mdelay(10000); + struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); + + writel(0, pctrl->regs + PS_HOLD_OFFSET); + mdelay(1000); + return NOTIFY_DONE; } static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) @@ -868,13 +870,14 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) for (; i <= pctrl->soc->nfunctions; i++) if (!strcmp(func[i].name, "ps_hold")) { - msm_ps_hold = pctrl->regs + PS_HOLD_OFFSET; - arm_pm_restart = msm_reset; + pctrl->restart_nb.notifier_call = msm_ps_hold_restart; + pctrl->restart_nb.priority = 128; + if (register_restart_handler(&pctrl->restart_nb)) + dev_err(pctrl->dev, + "failed to setup restart handler.\n"); + break; } } -#else -static void msm_pinctrl_setup_pm_reset(const struct msm_pinctrl *pctrl) {} -#endif int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) @@ -943,6 +946,8 @@ int msm_pinctrl_remove(struct platform_device *pdev) pinctrl_unregister(pctrl->pctrl); + unregister_restart_handler(&pctrl->restart_nb); + return 0; } EXPORT_SYMBOL(msm_pinctrl_remove); -- cgit v1.2.3 From ba388294a5e07335a998d64f0b4a05857425a440 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 29 Sep 2014 15:17:04 +0200 Subject: pinctrl: nomadik: use util function to reserve maps Stop brewing our own pin map reservation function and use the generic code. Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index c093d75a022a..9fe31daf9230 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -32,6 +32,7 @@ #include #include "pinctrl-nomadik.h" #include "../core.h" +#include "../pinctrl-utils.h" /* * The GPIO module in the Nomadik family of Systems-on-Chip is an @@ -1349,28 +1350,6 @@ static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, unsigned reserve) -{ - unsigned old_num = *reserved_maps; - unsigned new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps, const char *group, const char *function) @@ -1561,7 +1540,7 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, reserve *= ret; - ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve); + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, reserve); if (ret < 0) goto exit; -- cgit v1.2.3 From 6e9b1c351dd66ab3d5ecbec44aa1e0b4f576e913 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 29 Sep 2014 15:22:20 +0200 Subject: pinctrl: nomadik: use utils map free function Stop brewing our own map free function and rely on the pinctrl utils helpers. Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 9fe31daf9230..6c9667a44b7b 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1339,17 +1339,6 @@ static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); } -static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) - kfree(map[i].data.configs.configs); - kfree(map); -} - static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps, const char *group, const char *function) @@ -1581,7 +1570,7 @@ static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, &reserved_maps, num_maps); if (ret < 0) { - nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); return ret; } } @@ -1595,7 +1584,7 @@ static const struct pinctrl_ops nmk_pinctrl_ops = { .get_group_pins = nmk_get_group_pins, .pin_dbg_show = nmk_pin_dbg_show, .dt_node_to_map = nmk_pinctrl_dt_node_to_map, - .dt_free_map = nmk_pinctrl_dt_free_map, + .dt_free_map = pinctrl_utils_dt_free_map, }; static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) -- cgit v1.2.3 From c2f6d059abfc29822af732e4da70813a5b6fd9cd Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 29 Sep 2014 16:54:14 +0200 Subject: pinctrl: nomadik: refactor DT parser to take two paths We refactor the DT parser to look for either a config or a function and then look for further nodes and reserve maps, not the two things mixed up like prior to this patch. Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 62 ++++++++++++++++--------------- 1 file changed, 33 insertions(+), 29 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 6c9667a44b7b..09efb8c1a2eb 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1505,51 +1505,55 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, const char *function = NULL; unsigned long configs = 0; bool has_config = 0; - unsigned reserve = 0; struct property *prop; const char *group, *gpio_name; struct device_node *np_config; ret = of_property_read_string(np, "ste,function", &function); - if (ret >= 0) - reserve = 1; - - has_config = nmk_pinctrl_dt_get_config(np, &configs); - - np_config = of_parse_phandle(np, "ste,config", 0); - if (np_config) - has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); - - ret = of_property_count_strings(np, "ste,pins"); - if (ret < 0) - goto exit; - - if (has_config) - reserve++; - - reserve *= ret; - - ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "ste,pins", prop, group) { - if (function) { + if (ret >= 0) { + ret = of_property_count_strings(np, "ste,pins"); + if (ret < 0) + goto exit; + + ret = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, + num_maps, ret); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "ste,pins", prop, group) { ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, group, function); if (ret < 0) goto exit; } - if (has_config) { + } + + has_config = nmk_pinctrl_dt_get_config(np, &configs); + np_config = of_parse_phandle(np, "ste,config", 0); + if (np_config) + has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); + if (has_config) { + ret = of_property_count_strings(np, "ste,pins"); + if (ret < 0) + goto exit; + ret = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, + num_maps, ret); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "ste,pins", prop, group) { gpio_name = nmk_find_pin_name(pctldev, group); - ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, - gpio_name, &configs, 1); + ret = nmk_dt_add_map_configs(map, reserved_maps, + num_maps, + gpio_name, &configs, 1); if (ret < 0) goto exit; } - } + exit: return ret; } -- cgit v1.2.3 From b07f92a220fa4df01e7feb1791245882249ba200 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 30 Sep 2014 11:11:50 +0200 Subject: pinctrl: abx500: use helpers for map allocation/free This switches the abx500 driver to use the pin control helper utils for allocating and free:ing maps. Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 43 ++++---------------------------- 1 file changed, 5 insertions(+), 38 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index b0289824cf73..be95f5e68c01 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -34,6 +34,7 @@ #include "pinctrl-abx500.h" #include "../core.h" #include "../pinconf.h" +#include "../pinctrl-utils.h" /* * The AB9540 and AB8540 GPIO support are extended versions @@ -827,41 +828,6 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, chip->base + offset - 1); } -static void abx500_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) - kfree(map[i].data.configs.configs); - kfree(map); -} - -static int abx500_dt_reserve_map(struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps, - unsigned reserve) -{ - unsigned old_num = *reserved_maps; - unsigned new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - static int abx500_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps, const char *group, @@ -958,7 +924,8 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, reserve *= ret; - ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve); + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, + num_maps, reserve); if (ret < 0) goto exit; @@ -999,7 +966,7 @@ static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, ret = abx500_dt_subnode_to_map(pctldev, np, map, &reserved_maps, num_maps); if (ret < 0) { - abx500_dt_free_map(pctldev, *map, *num_maps); + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); return ret; } } @@ -1013,7 +980,7 @@ static const struct pinctrl_ops abx500_pinctrl_ops = { .get_group_pins = abx500_get_group_pins, .pin_dbg_show = abx500_pin_dbg_show, .dt_node_to_map = abx500_dt_node_to_map, - .dt_free_map = abx500_dt_free_map, + .dt_free_map = pinctrl_utils_dt_free_map, }; static int abx500_pin_config_get(struct pinctrl_dev *pctldev, -- cgit v1.2.3 From 259145feff723cd65fcf53156bdd7a11816b1e31 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 30 Sep 2014 11:22:07 +0200 Subject: pinctrl: abx500: refactor DT parser to take two paths We refactor the DT parser to look for either a config or a function and then look for further nodes and reserve maps, not the two things mixed up like prior to this patch. Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 54 +++++++++++++++++--------------- 1 file changed, 28 insertions(+), 26 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index be95f5e68c01..af0d417fe3fb 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -893,19 +893,32 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, unsigned long *configs; unsigned int nconfigs = 0; bool has_config = 0; - unsigned reserve = 0; struct property *prop; const char *group, *gpio_name; struct device_node *np_config; ret = of_property_read_string(np, "ste,function", &function); - if (ret >= 0) - reserve = 1; + if (ret >= 0) { + ret = of_property_count_strings(np, "ste,pins"); + if (ret < 0) + goto exit; + + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, + num_maps, ret); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "ste,pins", prop, group) { + ret = abx500_dt_add_map_mux(map, reserved_maps, + num_maps, group, function); + if (ret < 0) + goto exit; + } + } ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); if (nconfigs) has_config = 1; - np_config = of_parse_phandle(np, "ste,config", 0); if (np_config) { ret = pinconf_generic_parse_dt_config(np_config, &configs, @@ -914,29 +927,18 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, goto exit; has_config |= nconfigs; } + if (has_config) { + ret = of_property_count_strings(np, "ste,pins"); + if (ret < 0) + goto exit; - ret = of_property_count_strings(np, "ste,pins"); - if (ret < 0) - goto exit; - - if (has_config) - reserve++; - - reserve *= ret; - - ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, - num_maps, reserve); - if (ret < 0) - goto exit; + ret = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, + num_maps, ret); + if (ret < 0) + goto exit; - of_property_for_each_string(np, "ste,pins", prop, group) { - if (function) { - ret = abx500_dt_add_map_mux(map, reserved_maps, - num_maps, group, function); - if (ret < 0) - goto exit; - } - if (has_config) { + of_property_for_each_string(np, "ste,pins", prop, group) { gpio_name = abx500_find_pin_name(pctldev, group); ret = abx500_dt_add_map_configs(map, reserved_maps, @@ -944,8 +946,8 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (ret < 0) goto exit; } - } + exit: return ret; } -- cgit v1.2.3 From 8f1774a2a97135db35c5f42531a148135158705a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 30 Sep 2014 15:05:21 +0200 Subject: pinctrl: nomadik: improve GPIO debug prints The debugfs file would only define if the line was "pulled" and not which direction (pull up or pull down). Improve this by taking two print paths depending on whether the pin is set as input or output and use the data register directly to figure out whether the pin is set for pull up or pull down. Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 36 +++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 11 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 09efb8c1a2eb..3c29d9187146 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -986,6 +986,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, container_of(chip, struct nmk_gpio_chip, chip); int mode; bool is_out; + bool data_out; bool pull; u32 bit = 1 << offset; const char *modes[] = { @@ -998,28 +999,41 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, [NMK_GPIO_ALT_C+3] = "altC3", [NMK_GPIO_ALT_C+4] = "altC4", }; + const char *pulls[] = { + "none ", + "pull down", + "pull up ", + }; clk_enable(nmk_chip->clk); is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); + data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit); mode = nmk_gpio_get_mode(gpio); if ((mode == NMK_GPIO_ALT_C) && pctldev) mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); - seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", - gpio, label ?: "(none)", - is_out ? "out" : "in ", - chip->get - ? (chip->get(chip, offset) ? "hi" : "lo") - : "? ", - (mode < 0) ? "unknown" : modes[mode], - pull ? "pull" : "none"); - - if (!is_out) { + if (is_out) { + seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", + gpio, + label ?: "(none)", + data_out ? "hi" : "lo", + (mode < 0) ? "unknown" : modes[mode]); + } else { int irq = gpio_to_irq(gpio); struct irq_desc *desc = irq_to_desc(irq); + int pullidx = 0; - /* This races with request_irq(), set_irq_type(), + if (pull) + pullidx = data_out ? 1 : 2; + + seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", + gpio, + label ?: "(none)", + pulls[pullidx], + (mode < 0) ? "unknown" : modes[mode]); + /* + * This races with request_irq(), set_irq_type(), * and set_irq_wake() ... but those are "rare". */ if (irq > 0 && desc && desc->action) { -- cgit v1.2.3 From 3a4b094d5d09b8e0d007b2ca3de4f42df3af46e6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 2 Oct 2014 09:30:43 +0200 Subject: pinctrl: abx500: get rid of unused variable commit 2fcea6cecbc965b4e02a39537d9d939f5251bbbd "pinctrl: remove remaining users of gpiochip_remove() retval" removed the use of the return value from gpiochip_remove() but missed to delete the dangling "err" variable: drivers/pinctrl/nomadik/pinctrl-abx500.c: In function 'abx500_gpio_probe': drivers/pinctrl/nomadik/pinctrl-abx500.c:1208:11: warning: unused variable 'err' [-Wunused-variable] Fix this by getting rid of the dangling variable. Reported-by: Arnd Bergmann Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 7df34b70e8b6..080bcf8568c9 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -1206,7 +1206,7 @@ static int abx500_gpio_probe(struct platform_device *pdev) const struct of_device_id *match; struct abx500_pinctrl *pct; unsigned int id = -1; - int ret, err; + int ret; int i; if (!np) { -- cgit v1.2.3 From 3a71c05e66e597a1349fdbd5f0bb119d8d9cb850 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 26 Sep 2014 16:14:51 +0200 Subject: pinctrl: baytrail: Clear DIRECT_IRQ bit Direct irq en bit should be cleared for pads using io mode. If not, the io based irq will never be detected. However, this bit can sometimes be misconfigured (BIOS issue). Force clearing of this bit in io mode and trigger a WARN. Signed-off-by: Loic Poulain Acked-by: Mika Westerberg Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-baytrail.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c index e12e5b07f6d7..b83ec87c71fe 100644 --- a/drivers/pinctrl/pinctrl-baytrail.c +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -227,10 +227,14 @@ static int byt_irq_type(struct irq_data *d, unsigned type) spin_lock_irqsave(&vg->lock, flags); value = readl(reg); + WARN(value & BYT_DIRECT_IRQ_EN, + "Bad pad config for io mode, force direct_irq_en bit clearing"); + /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits * are used to indicate high and low level triggering */ - value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | + BYT_TRIG_LVL); switch (type) { case IRQ_TYPE_LEVEL_HIGH: -- cgit v1.2.3 From d90c33818967c5e5371961604ad98b4dea4fa3f4 Mon Sep 17 00:00:00 2001 From: David Cohen Date: Tue, 14 Oct 2014 10:54:37 -0700 Subject: pinctrl: baytrail: show output gpio state correctly on Intel Baytrail Even if a gpio pin is set to output, we still need to set INPUT_EN functionality (by clearing INPUT_EN bit) to be able to read the pin's level. E.g. without this change, we'll always read low level state from sysfs. Cc: # v3.14+ Cc: Mathias Nyman Signed-off-by: David Cohen Reviewed-by: Felipe Balbi Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-baytrail.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c index b83ec87c71fe..9dc38140194b 100644 --- a/drivers/pinctrl/pinctrl-baytrail.c +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -322,7 +322,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip, "Potential Error: Setting GPIO with direct_irq_en to output"); reg_val = readl(reg) | BYT_DIR_MASK; - reg_val &= ~BYT_OUTPUT_EN; + reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN); if (value) writel(reg_val | BYT_LEVEL, reg); -- cgit v1.2.3