From 8e93675e5b235291d9dec91af78e01dd4f73629a Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:22:57 +0100 Subject: [ARM] 4767/2: ixp4xx: Add bitops.h include to io.h Add include of to io.h to solve compilations errors in files such as drivers/w1/w1_io.c caused by the ixp4xx version of io.h using the BIT() macro without including first. Signed-off-by: Rod Whitby Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/io.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index 9c5d2357aff3..de181ce958db 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h @@ -13,6 +13,8 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H +#include + #include #define IO_SPACE_LIMIT 0xffff0000 -- cgit v1.2.3 From 14645ebabd96d29f3050ea78a6417b6653bc48cf Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:29:38 +0100 Subject: [ARM] 4768/2: ixp4xx: Button and LED updates for the nas100d board * Convert GPIO and IRQ handling to use the api. * Perform the reset only after the power button has been held down for at least two seconds. Do the reset on the release of the power button, so that NAS devices which have been set to auto-power-on (by solder bridging the power button) do not continuously power cycle. * Remove all superflous constants from nas100d.h * Add LED constants to nas100d.h while we're there. * Update the board LED setup code to use those constants. Signed-off-by: Rod Whitby Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/nas100d.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/nas100d.h b/include/asm-arm/arch-ixp4xx/nas100d.h index 131e0a1d0df3..98d937897bce 100644 --- a/include/asm-arm/arch-ixp4xx/nas100d.h +++ b/include/asm-arm/arch-ixp4xx/nas100d.h @@ -38,15 +38,15 @@ /* Buttons */ -#define NAS100D_PB_GPIO 14 -#define NAS100D_RB_GPIO 4 +#define NAS100D_PB_GPIO 14 /* power button */ +#define NAS100D_RB_GPIO 4 /* reset button */ + +/* Power control */ + #define NAS100D_PO_GPIO 12 /* power off */ -#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14 -#define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4 +/* LEDs */ -/* -#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO) -#define NAS100D_PO_BM (1L << NAS100D_PO_GPIO) -#define NAS100D_RB_BM (1L << NAS100D_RB_GPIO) -*/ +#define NAS100D_LED_WLAN_GPIO 0 +#define NAS100D_LED_DISK_GPIO 3 +#define NAS100D_LED_PWR_GPIO 15 -- cgit v1.2.3 From 2bea80187f6218ed8b5c1e1280220b1c53d8dd05 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:30:54 +0100 Subject: [ARM] 4769/2: ixp4xx: Button updates for the dsmg600 board * Remove the superfluous declaration of ctrl_alt_del(). * Convert GPIO and IRQ handling to use the api. * Perform the reset on the release of the power button, so that NAS devices which have been set to auto-power-on (by solder bridging the power button) do not continuously power cycle. * Remove all superflous constants from dsmg600.h Signed-off-by: Rod Whitby Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/dsmg600.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/dsmg600.h b/include/asm-arm/arch-ixp4xx/dsmg600.h index a19605ad240d..b7673e171abe 100644 --- a/include/asm-arm/arch-ixp4xx/dsmg600.h +++ b/include/asm-arm/arch-ixp4xx/dsmg600.h @@ -40,18 +40,13 @@ /* Buttons */ #define DSMG600_PB_GPIO 15 /* power button */ -#define DSMG600_PB_BM (1L << DSMG600_PB_GPIO) - #define DSMG600_RB_GPIO 3 /* reset button */ -#define DSMG600_RB_IRQ IRQ_IXP4XX_GPIO3 +/* Power control */ #define DSMG600_PO_GPIO 2 /* power off */ /* LEDs */ #define DSMG600_LED_PWR_GPIO 0 -#define DSMG600_LED_PWR_BM (1L << DSMG600_LED_PWR_GPIO) - #define DSMG600_LED_WLAN_GPIO 14 -#define DSMG600_LED_WLAN_BM (1L << DSMG600_LED_WLAN_GPIO) -- cgit v1.2.3 From c18f65816ef80b67eb4511ed8359c2dfcd69680d Mon Sep 17 00:00:00 2001 From: Krzysztof Halasa Date: Tue, 18 Dec 2007 03:53:27 +0100 Subject: [ARM] 4712/2: Adds functions to read and write IXP4xx "feature" bits Adds functions to read and write IXP4xx "feature" (aka "fuse") bits, containing information about available/enabled CPU features. The uncompress.h included by boot/compressed/misc.c resides in a different space than rest of the kernel and thus can't use asm/hardware.h (including asm/arch/cpu.h - which, in turn, may use EXPORTed symbol "processor_id"). Posted to linux-arm-kernel on 2 Dec 2007 and revised. Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/cpu.h | 15 +++++++++++++ include/asm-arm/arch-ixp4xx/hardware.h | 6 +++--- include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 36 +++++++++++++++++++++++++++---- include/asm-arm/arch-ixp4xx/uncompress.h | 2 +- 4 files changed, 51 insertions(+), 8 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h index d2523b326c6c..2fa3d6b8dbb8 100644 --- a/include/asm-arm/arch-ixp4xx/cpu.h +++ b/include/asm-arm/arch-ixp4xx/cpu.h @@ -28,4 +28,19 @@ extern unsigned int processor_id; #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ IXP465_PROCESSOR_ID_VALUE) +static inline u32 ixp4xx_read_feature_bits(void) +{ + unsigned int val = ~*IXP4XX_EXP_CFG2; + val &= ~IXP4XX_FEATURE_RESERVED; + if (!cpu_is_ixp46x()) + val &= ~IXP4XX_FEATURE_IXP46X_ONLY; + + return val; +} + +static inline void ixp4xx_write_feature_bits(u32 value) +{ + *IXP4XX_EXP_CFG2 = ~value; +} + #endif /* _ASM_ARCH_CPU_H */ diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h index 297ceda08b61..73e8dc36f6a4 100644 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ b/include/asm-arm/arch-ixp4xx/hardware.h @@ -27,13 +27,13 @@ #define pcibios_assign_all_busses() 1 +/* Register locations and bits */ +#include "ixp4xx-regs.h" + #ifndef __ASSEMBLER__ #include #endif -/* Register locations and bits */ -#include "ixp4xx-regs.h" - /* Platform helper functions and definitions */ #include "platform.h" diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h index 5d949d763a91..c704fe8cf42f 100644 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h @@ -15,10 +15,6 @@ * */ -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - #ifndef _ASM_ARM_IXP4XX_H_ #define _ASM_ARM_IXP4XX_H_ @@ -607,4 +603,36 @@ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ +/* "fuse" bits of IXP_EXP_CFG2 */ +#define IXP4XX_FEATURE_RCOMP (1 << 0) +#define IXP4XX_FEATURE_USB_DEVICE (1 << 1) +#define IXP4XX_FEATURE_HASH (1 << 2) +#define IXP4XX_FEATURE_AES (1 << 3) +#define IXP4XX_FEATURE_DES (1 << 4) +#define IXP4XX_FEATURE_HDLC (1 << 5) +#define IXP4XX_FEATURE_AAL (1 << 6) +#define IXP4XX_FEATURE_HSS (1 << 7) +#define IXP4XX_FEATURE_UTOPIA (1 << 8) +#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) +#define IXP4XX_FEATURE_NPEC_ETH (1 << 10) +#define IXP4XX_FEATURE_RESET_NPEA (1 << 11) +#define IXP4XX_FEATURE_RESET_NPEB (1 << 12) +#define IXP4XX_FEATURE_RESET_NPEC (1 << 13) +#define IXP4XX_FEATURE_PCI (1 << 14) +#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) +#define IXP4XX_FEATURE_USB_HOST (1 << 18) +#define IXP4XX_FEATURE_NPEA_ETH (1 << 19) +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) +#define IXP4XX_FEATURE_RSA (1 << 21) +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) +#define IXP4XX_FEATURE_RESERVED (0xFF << 24) + +#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ + IXP4XX_FEATURE_USB_HOST | \ + IXP4XX_FEATURE_NPEA_ETH | \ + IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ + IXP4XX_FEATURE_RSA | \ + IXP4XX_FEATURE_XSCALE_MAX_FREQ) + #endif diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h index f7a35b78823f..34ef48fe327e 100644 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ b/include/asm-arm/arch-ixp4xx/uncompress.h @@ -13,7 +13,7 @@ #ifndef _ARCH_UNCOMPRESS_H_ #define _ARCH_UNCOMPRESS_H_ -#include +#include "ixp4xx-regs.h" #include #include -- cgit v1.2.3 From 82a96f5790ac93a406be72ed8f308dd29ad7e6af Mon Sep 17 00:00:00 2001 From: Krzysztof Halasa Date: Tue, 1 Jan 2008 21:55:23 +0100 Subject: [ARM] 4713/3: Adds drivers for IXP4xx QMgr and NPE features This patch adds drivers for IXP4xx hardware Queue Manager and for Network Processor Engines. Requires patch #4712 (reading/writing CPU feature (aka fuse) bits). Posted to linux-arm-kernel on 2 Dec 2007 and revised. Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/npe.h | 39 ++++++++++++ include/asm-arm/arch-ixp4xx/qmgr.h | 126 +++++++++++++++++++++++++++++++++++++ 2 files changed, 165 insertions(+) create mode 100644 include/asm-arm/arch-ixp4xx/npe.h create mode 100644 include/asm-arm/arch-ixp4xx/qmgr.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h new file mode 100644 index 000000000000..37d0511689dc --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/npe.h @@ -0,0 +1,39 @@ +#ifndef __IXP4XX_NPE_H +#define __IXP4XX_NPE_H + +#include + +extern const char *npe_names[]; + +struct npe_regs { + u32 exec_addr, exec_data, exec_status_cmd, exec_count; + u32 action_points[4]; + u32 watchpoint_fifo, watch_count; + u32 profile_count; + u32 messaging_status, messaging_control; + u32 mailbox_status, /*messaging_*/ in_out_fifo; +}; + +struct npe { + struct resource *mem_res; + struct npe_regs __iomem *regs; + u32 regs_phys; + int id; + int valid; +}; + + +static inline const char *npe_name(struct npe *npe) +{ + return npe_names[npe->id]; +} + +int npe_running(struct npe *npe); +int npe_send_message(struct npe *npe, const void *msg, const char *what); +int npe_recv_message(struct npe *npe, void *msg, const char *what); +int npe_send_recv_message(struct npe *npe, void *msg, const char *what); +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); +struct npe *npe_request(int id); +void npe_release(struct npe *npe); + +#endif /* __IXP4XX_NPE_H */ diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h new file mode 100644 index 000000000000..1e52b95cede5 --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/qmgr.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + */ + +#ifndef IXP4XX_QMGR_H +#define IXP4XX_QMGR_H + +#include +#include + +#define HALF_QUEUES 32 +#define QUEUES 64 /* only 32 lower queues currently supported */ +#define MAX_QUEUE_LENGTH 4 /* in dwords */ + +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */ +#define QUEUE_STAT1_NEARLY_EMPTY 2 +#define QUEUE_STAT1_NEARLY_FULL 4 +#define QUEUE_STAT1_FULL 8 +#define QUEUE_STAT2_UNDERFLOW 1 +#define QUEUE_STAT2_OVERFLOW 2 + +#define QUEUE_WATERMARK_0_ENTRIES 0 +#define QUEUE_WATERMARK_1_ENTRY 1 +#define QUEUE_WATERMARK_2_ENTRIES 2 +#define QUEUE_WATERMARK_4_ENTRIES 3 +#define QUEUE_WATERMARK_8_ENTRIES 4 +#define QUEUE_WATERMARK_16_ENTRIES 5 +#define QUEUE_WATERMARK_32_ENTRIES 6 +#define QUEUE_WATERMARK_64_ENTRIES 7 + +/* queue interrupt request conditions */ +#define QUEUE_IRQ_SRC_EMPTY 0 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2 +#define QUEUE_IRQ_SRC_FULL 3 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6 +#define QUEUE_IRQ_SRC_NOT_FULL 7 + +struct qmgr_regs { + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */ + u32 stat1[4]; /* 0x400 - 0x40F */ + u32 stat2[2]; /* 0x410 - 0x417 */ + u32 statne_h; /* 0x418 - queue nearly empty */ + u32 statf_h; /* 0x41C - queue full */ + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */ + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */ + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */ + u32 reserved[1776]; + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */ +}; + +void qmgr_set_irq(unsigned int queue, int src, + void (*handler)(void *pdev), void *pdev); +void qmgr_enable_irq(unsigned int queue); +void qmgr_disable_irq(unsigned int queue); + +/* request_ and release_queue() must be called from non-IRQ context */ +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, + unsigned int nearly_empty_watermark, + unsigned int nearly_full_watermark); +void qmgr_release_queue(unsigned int queue); + + +static inline void qmgr_put_entry(unsigned int queue, u32 val) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + __raw_writel(val, &qmgr_regs->acc[queue][0]); +} + +static inline u32 qmgr_get_entry(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return __raw_readl(&qmgr_regs->acc[queue][0]); +} + +static inline int qmgr_get_stat1(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) + >> ((queue & 7) << 2)) & 0xF; +} + +static inline int qmgr_get_stat2(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) + >> ((queue & 0xF) << 1)) & 0x3; +} + +static inline int qmgr_stat_empty(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY); +} + +static inline int qmgr_stat_nearly_empty(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY); +} + +static inline int qmgr_stat_nearly_full(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL); +} + +static inline int qmgr_stat_full(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL); +} + +static inline int qmgr_stat_underflow(unsigned int queue) +{ + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW); +} + +static inline int qmgr_stat_overflow(unsigned int queue) +{ + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW); +} + +#endif -- cgit v1.2.3 From 80bbdd27e4016ad39d33160ea7f39ac05bfe1d7c Mon Sep 17 00:00:00 2001 From: Krzysztof Halasa Date: Tue, 29 Jan 2008 01:03:00 +0100 Subject: [ARM] 4714/2: Headers for IXP4xx built-in Ethernet and WAN drivers Adds platform structs and #defines required by drivers for IXP4xx built-in Ethernet and WAN (sync serial) ports. The actual drivers will reside in drivers/net/arm and drivers/net/wan and will be submitted separately. Signed-off-by: Krzysztof Halasa Signed-off-by: Rod Whitby Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/platform.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h index 2ce28e3fd325..a1f2b5404db1 100644 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ b/include/asm-arm/arch-ixp4xx/platform.h @@ -91,6 +91,27 @@ struct ixp4xx_pata_data { struct sys_timer; +#define IXP4XX_ETH_NPEA 0x00 +#define IXP4XX_ETH_NPEB 0x10 +#define IXP4XX_ETH_NPEC 0x20 + +/* Information about built-in Ethernet MAC interfaces */ +struct eth_plat_info { + u8 phy; /* MII PHY ID, 0 - 31 */ + u8 rxq; /* configurable, currently 0 - 31 only */ + u8 txreadyq; + u8 hwaddr[6]; +}; + +/* Information about built-in HSS (synchronous serial) interfaces */ +struct hss_plat_info { + int (*set_clock)(int port, unsigned int clock_type); + int (*open)(int port, void *pdev, + void (*set_carrier_cb)(void *pdev, int carrier)); + void (*close)(int port, void *pdev); + u8 txreadyq; +}; + /* * Frequency of clock used for primary clocksource */ -- cgit v1.2.3 From 0929ac3ea4c0bece16b0c5c5365181fa45fbf582 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Sun, 3 Feb 2008 12:05:42 +0100 Subject: [ARM] 4807/2: ixp4xx: Merge nslu2-power.c into nslu2-setup.c There is no reason to have power control in a separate file from the board setup code. Merge it back into the board setup file, removing superfluous header includes and removing superfluous constants from the machine header file. -- Signed-off-by: Rod Whitby Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/nslu2.h | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h index 850fdc5b45da..714bbc65126a 100644 --- a/include/asm-arm/arch-ixp4xx/nslu2.h +++ b/include/asm-arm/arch-ixp4xx/nslu2.h @@ -39,34 +39,17 @@ /* Buttons */ -#define NSLU2_PB_GPIO 5 +#define NSLU2_PB_GPIO 5 /* power button */ #define NSLU2_PO_GPIO 8 /* power off */ -#define NSLU2_RB_GPIO 12 - -#define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5 -#define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12 - -#define NSLU2_PB_BM (1L << NSLU2_PB_GPIO) -#define NSLU2_PO_BM (1L << NSLU2_PO_GPIO) -#define NSLU2_RB_BM (1L << NSLU2_RB_GPIO) +#define NSLU2_RB_GPIO 12 /* reset button */ /* Buzzer */ #define NSLU2_GPIO_BUZZ 4 -#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ) /* LEDs */ #define NSLU2_LED_RED_GPIO 0 #define NSLU2_LED_GRN_GPIO 1 - -#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED_GPIO) -#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN_GPIO) - #define NSLU2_LED_DISK1_GPIO 3 #define NSLU2_LED_DISK2_GPIO 2 - -#define NSLU2_LED_DISK1_BM (1L << NSLU2_LED_DISK1_GPIO) -#define NSLU2_LED_DISK2_BM (1L << NSLU2_LED_DISK2_GPIO) - - -- cgit v1.2.3 From fa3218d8594869b38b1a170ea36d176ac455b897 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 29 Jan 2008 15:43:13 +0100 Subject: [ARM] 4660/3: at91: allow selecting UART for early kernel messages Currently early kernel messages, i.e., those from uncompression, go to the debugging UART. And if it is enabled in the platform configuration, but not initialized by the bootloader, the machine hangs, waiting for UART status change. Besides, having those messages on another UART - typically the console UART - may be preferrable. This patch allows selecting the UART in kernel configuration. Signed-off-by: Guennadi Liakhovetski Acked-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91rm9200.h | 5 +++++ include/asm-arm/arch-at91/at91sam9260.h | 7 +++++++ include/asm-arm/arch-at91/at91sam9261.h | 4 ++++ include/asm-arm/arch-at91/at91sam9263.h | 4 ++++ include/asm-arm/arch-at91/at91sam9rl.h | 5 +++++ include/asm-arm/arch-at91/uncompress.h | 32 ++++++++++++++++++++++++-------- 6 files changed, 49 insertions(+), 8 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h index 802891a9cd81..e8fc0b1c33f4 100644 --- a/include/asm-arm/arch-at91/at91rm9200.h +++ b/include/asm-arm/arch-at91/at91rm9200.h @@ -93,6 +93,11 @@ #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ +#define AT91_USART0 AT91RM9200_BASE_US0 +#define AT91_USART1 AT91RM9200_BASE_US1 +#define AT91_USART2 AT91RM9200_BASE_US2 +#define AT91_USART3 AT91RM9200_BASE_US3 + #define AT91_MATRIX 0 /* not supported */ /* diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index 0427f8698c07..c8934fe34dc5 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -99,6 +99,13 @@ #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_USART0 AT91SAM9260_BASE_US0 +#define AT91_USART1 AT91SAM9260_BASE_US1 +#define AT91_USART2 AT91SAM9260_BASE_US2 +#define AT91_USART3 AT91SAM9260_BASE_US3 +#define AT91_USART4 AT91SAM9260_BASE_US4 +#define AT91_USART5 AT91SAM9260_BASE_US5 + /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index 9eb459570330..c7c4778dac49 100644 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -84,6 +84,10 @@ #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_USART0 AT91SAM9261_BASE_US0 +#define AT91_USART1 AT91SAM9261_BASE_US1 +#define AT91_USART2 AT91SAM9261_BASE_US2 + /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index 115c47ac7ebb..018a647311da 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -101,6 +101,10 @@ #define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91_USART0 AT91SAM9263_BASE_US0 +#define AT91_USART1 AT91SAM9263_BASE_US1 +#define AT91_USART2 AT91SAM9263_BASE_US2 + #define AT91_SMC AT91_SMC0 /* diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 8a9708a370c6..16d2832f6c0a 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -94,6 +94,11 @@ #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) +#define AT91_USART0 AT91SAM9RL_BASE_US0 +#define AT91_USART1 AT91SAM9RL_BASE_US1 +#define AT91_USART2 AT91SAM9RL_BASE_US2 +#define AT91_USART3 AT91SAM9RL_BASE_US3 + /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index 272a7e0dc6cf..f5636a8f6132 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -22,7 +22,23 @@ #define __ASM_ARCH_UNCOMPRESS_H #include -#include +#include + +#if defined(CONFIG_AT91_EARLY_DBGU) +#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS) +#elif defined(CONFIG_AT91_EARLY_USART0) +#define UART_OFFSET AT91_USART0 +#elif defined(CONFIG_AT91_EARLY_USART1) +#define UART_OFFSET AT91_USART1 +#elif defined(CONFIG_AT91_EARLY_USART2) +#define UART_OFFSET AT91_USART2 +#elif defined(CONFIG_AT91_EARLY_USART3) +#define UART_OFFSET AT91_USART3 +#elif defined(CONFIG_AT91_EARLY_USART4) +#define UART_OFFSET AT91_USART4 +#elif defined(CONFIG_AT91_EARLY_USART5) +#define UART_OFFSET AT91_USART5 +#endif /* * The following code assumes the serial port has already been @@ -33,22 +49,22 @@ */ static void putc(int c) { -#ifdef AT91_DBGU - void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ +#ifdef UART_OFFSET + void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) + while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY)) barrier(); - __raw_writel(c, sys + AT91_DBGU_THR); + __raw_writel(c, sys + ATMEL_US_THR); #endif } static inline void flush(void) { -#ifdef AT91_DBGU - void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ +#ifdef UART_OFFSET + void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ /* wait for transmission to complete */ - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) + while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) barrier(); #endif } -- cgit v1.2.3 From a78de2f704a0954df011348c6022e0d49e773a44 Mon Sep 17 00:00:00 2001 From: Marc Pignat Date: Wed, 30 Jan 2008 13:41:32 +0100 Subject: [ARM] 4802/1: Fix typo and remove vague comment Fix typo and remove vague comment Signed-off-by: Marc Pignat Acked-by: Andrew Victor Acked-by: Nicolas Ferre Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91_mci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h index c2e11cc374ba..1551fc24eb43 100644 --- a/include/asm-arm/arch-at91/at91_mci.h +++ b/include/asm-arm/arch-at91/at91_mci.h @@ -89,7 +89,7 @@ #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ #define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ -#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ +#define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */ #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ -- cgit v1.2.3 From c4d1fb627ff307256d792280efcb09e1235affea Mon Sep 17 00:00:00 2001 From: eric miao Date: Mon, 28 Jan 2008 23:00:02 +0000 Subject: [ARM] pxa: add preliminary suspend/resume code for pxa3xx 1. clear RDH bit after resuming back from D3, otherwise, the multi function pins will retain the low power state 2. save/restore essential system registers Signed-off-by: eric miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/pxa3xx-regs.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h index 66d54119757c..8e1b3ead827f 100644 --- a/include/asm-arm/arch-pxa/pxa3xx-regs.h +++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h @@ -12,6 +12,19 @@ #ifndef __ASM_ARCH_PXA3XX_REGS_H #define __ASM_ARCH_PXA3XX_REGS_H +/* + * Service Power Management Unit (MPMU) + */ +#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ +#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ +#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ +#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ +#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ +#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ +#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ +#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ +#define PCMD(x) __REG(0x40F50110 + ((x) << 2)) /* * Slave Power Managment Unit -- cgit v1.2.3 From 4cd9d6f774c7e0578bbc4409d4490d8f2097d40a Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Wed, 2 Jan 2008 00:56:46 +0100 Subject: [ARM] 4736/1: Export atags to userspace and allow kexec to use customised atags Currently, the atags used by kexec are fixed to the ones originally used to boot the kernel. This is less than ideal as changing the commandline, initrd and other options would be a useful feature. This patch exports the atags used for the current kernel to userspace through an "atags" file in procfs. The presence of the file is controlled by its own Kconfig option and cleans up several ifdef blocks into a separate file. The tags for the new kernel are assumed to be at a fixed location before the kernel image itself. The location of the tags used to boot the original kernel is unimportant and no longer saved. Based on a patch from Uli Luckas Signed-off-by: Richard Purdie Acked-by: Uli Luckas Signed-off-by: Russell King --- include/asm-arm/kexec.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h index 46dcc4d0b9bd..1ee17b6951d0 100644 --- a/include/asm-arm/kexec.h +++ b/include/asm-arm/kexec.h @@ -16,6 +16,9 @@ #define KEXEC_BOOT_PARAMS_SIZE 1536 +#define KEXEC_ARM_ATAGS_OFFSET 0x1000 +#define KEXEC_ARM_ZIMAGE_OFFSET 0x8000 + #ifndef __ASSEMBLY__ struct kimage; -- cgit v1.2.3 From 3e459990961db7f3f2dcf21e2b38a7216dfd10dd Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:28:56 +0100 Subject: [ARM] 4813/1: Add SMP helper functions for clockevents support This patch adds the smp_call_function_single and smp_timer_broadcast functions and modifies ipi_timer to call the platform-specific function local_timer_interrupt. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/smp.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h index f67acce387e7..1f7c51a1886d 100644 --- a/include/asm-arm/smp.h +++ b/include/asm-arm/smp.h @@ -60,6 +60,11 @@ extern void smp_cross_call(cpumask_t callmap); */ extern void smp_send_timer(void); +/* + * Broadcast a clock event to other CPUs. + */ +extern void smp_timer_broadcast(cpumask_t mask); + /* * Boot a secondary CPU, and assign it the specified idle task. * This also gives us the initial stack to use for this CPU. @@ -96,6 +101,11 @@ extern void platform_cpu_die(unsigned int cpu); extern int platform_cpu_kill(unsigned int cpu); extern void platform_cpu_enable(unsigned int cpu); +/* + * Local timer interrupt handling function (can be IPI'ed). + */ +extern void local_timer_interrupt(void); + #ifdef CONFIG_LOCAL_TIMERS /* * Setup a local timer interrupt for a CPU. -- cgit v1.2.3 From a8655e83fc44ec2b92cbea9f3ff3cc0da05a991c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:30:57 +0100 Subject: [ARM] 4814/1: RealView: Add broadcasting clockevents support for ARM11MPCore This patch adds dummy local timers for each CPU so that the board clock device is used to broadcast events to the other CPUs. The patch also adds the declaration for the dummy_timer_setup function (the equivalent of local_timer_setup when CONFIG_LOCAL_TIMERS is not set). Due to the way clockevents work, the dummy timer on the first CPU has to be registered before the board timer. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/smp.h | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h index 1f7c51a1886d..af99636db400 100644 --- a/include/asm-arm/smp.h +++ b/include/asm-arm/smp.h @@ -107,10 +107,6 @@ extern void platform_cpu_enable(unsigned int cpu); extern void local_timer_interrupt(void); #ifdef CONFIG_LOCAL_TIMERS -/* - * Setup a local timer interrupt for a CPU. - */ -extern void local_timer_setup(unsigned int cpu); /* * Stop a local timer interrupt. @@ -124,16 +120,17 @@ extern int local_timer_ack(void); #else -static inline void local_timer_setup(unsigned int cpu) -{ -} - static inline void local_timer_stop(unsigned int cpu) { } #endif +/* + * Setup a local timer interrupt for a CPU. + */ +extern void local_timer_setup(unsigned int cpu); + /* * show local interrupt info */ -- cgit v1.2.3 From 93c2904d5081468128e66792a85439df314de773 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:32:57 +0100 Subject: [ARM] 4815/1: RealView: Add clockevents suport for the local timers This patch registers the local timers on ARM11MPCore as clock event devices. The clock device can be set up as periodic or oneshot. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/hardware/arm_twd.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/hardware/arm_twd.h b/include/asm-arm/hardware/arm_twd.h index 131d5b40e072..e521b70713c8 100644 --- a/include/asm-arm/hardware/arm_twd.h +++ b/include/asm-arm/hardware/arm_twd.h @@ -1,7 +1,7 @@ #ifndef __ASM_HARDWARE_TWD_H #define __ASM_HARDWARE_TWD_H -#define TWD_TIMER_LOAD 0x00 +#define TWD_TIMER_LOAD 0x00 #define TWD_TIMER_COUNTER 0x04 #define TWD_TIMER_CONTROL 0x08 #define TWD_TIMER_INTSTAT 0x0C @@ -13,4 +13,9 @@ #define TWD_WDOG_RESETSTAT 0x30 #define TWD_WDOG_DISABLE 0x34 +#define TWD_TIMER_CONTROL_ENABLE (1 << 0) +#define TWD_TIMER_CONTROL_ONESHOT (0 << 1) +#define TWD_TIMER_CONTROL_PERIODIC (1 << 1) +#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) + #endif -- cgit v1.2.3 From 356cb470b84bda67738ba320a75629acae70e5fa Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:34:58 +0100 Subject: [ARM] 4816/1: RealView: Move the platform-specific definitions into board-eb.h This patch moves the platform specific definitions from platform.h into the board-eb.h file. It drops the INT_* definitions as they are no longer used in irqs.h (moved to board-eb.h). It renames REALVIEW_* macros to REALVIEW_EB_* or REALVIEW_EB11MP_* to distinguish between standard EB and EB + the ARM11MPCore tile. The platform.h file contains common definitions to the RealView platforms and it is only directly included in board-*.h files. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/arch-realview/board-eb.h | 152 +++++++++++++++++++++++++ include/asm-arm/arch-realview/entry-macro.S | 5 + include/asm-arm/arch-realview/hardware.h | 1 - include/asm-arm/arch-realview/irqs.h | 105 ++--------------- include/asm-arm/arch-realview/platform.h | 170 ++-------------------------- include/asm-arm/arch-realview/scu.h | 4 +- include/asm-arm/arch-realview/uncompress.h | 2 + 7 files changed, 181 insertions(+), 258 deletions(-) create mode 100644 include/asm-arm/arch-realview/board-eb.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h new file mode 100644 index 000000000000..943efc5de4eb --- /dev/null +++ b/include/asm-arm/arch-realview/board-eb.h @@ -0,0 +1,152 @@ +/* + * include/asm-arm/arch-realview/board-eb.h + * + * Copyright (C) 2007 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_BOARD_EB_H +#define __ASM_ARCH_BOARD_EB_H + +#include + +/* + * RealView EB + ARM11MPCore peripheral addresses + */ +#ifdef CONFIG_REALVIEW_MPCORE_REVB +#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ +#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ +#define REALVIEW_EB11MP_TWD_BASE 0x10100700 +#define REALVIEW_EB11MP_TWD_SIZE 0x00000100 +#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ +#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ +#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ +#else +#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */ +#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ +#define REALVIEW_EB11MP_TWD_BASE 0x1F000700 +#define REALVIEW_EB11MP_TWD_SIZE 0x00000100 +#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ +#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ +#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ +#endif + +#define IRQ_EB_GIC_START 32 + +/* + * RealView EB interrupt sources + */ +#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */ +#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */ +#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */ +#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */ +#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */ +#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */ +#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */ +#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */ +#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */ +#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */ +#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */ +#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */ +#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */ +#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */ +#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */ +#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */ + +/* + * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile) + */ +#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0) +#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1) +#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2) +#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3) +#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4) +#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5) +#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6) +#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7) +#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8) +#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9) +#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */ +#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */ +#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */ +#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */ +#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14) +#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15) + +#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17) +#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18) +#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19) +#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20) +#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21) +#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22) +#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23) +#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24) +#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25) +#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26) +#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27) +#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28) + +#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29) +#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30) +#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31) + +#define IRQ_EB11MP_UART2 -1 +#define IRQ_EB11MP_UART3 -1 +#define IRQ_EB11MP_CLCD -1 +#define IRQ_EB11MP_DMA -1 +#define IRQ_EB11MP_WDOG -1 +#define IRQ_EB11MP_GPIO0 -1 +#define IRQ_EB11MP_GPIO1 -1 +#define IRQ_EB11MP_GPIO2 -1 +#define IRQ_EB11MP_SCI -1 +#define IRQ_EB11MP_SSP -1 + +#define NR_GIC_EB11MP 2 + +/* + * Only define NR_IRQS if less than NR_IRQS_EB + */ +#define NR_IRQS_EB (IRQ_EB_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_EB) \ + && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB)) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_EB +#endif + +#if defined(CONFIG_REALVIEW_MPCORE) \ + && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_EB11MP +#endif + +#endif /* __ASM_ARCH_BOARD_EB_H */ diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 3b4e2076603a..629944deed50 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -9,12 +9,17 @@ */ #include #include +#include .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp +#ifdef CONFIG_REALVIEW_MPCORE + ldr \base, =IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE) +#else ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) +#endif .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h index aa78fe087ab2..bad8d7ce9bfe 100644 --- a/include/asm-arm/arch-realview/hardware.h +++ b/include/asm-arm/arch-realview/hardware.h @@ -23,7 +23,6 @@ #define __ASM_ARCH_HARDWARE_H #include -#include /* macro to get at IO space when running virtually */ #define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h index 5a5db56f86b8..ad0c911002fc 100644 --- a/include/asm-arm/arch-realview/irqs.h +++ b/include/asm-arm/arch-realview/irqs.h @@ -19,103 +19,18 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H -#define IRQ_LOCALTIMER 29 -#define IRQ_LOCALWDOG 30 +#include -/* - * IRQ interrupts definitions are the same the INT definitions - * held within platform.h - */ -#define IRQ_GIC_START 32 -#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT) -#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT) -#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx) -#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx) -#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1) -#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3) -#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0) -#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1) -#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2) -#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3) -#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT) -#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT) -#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0) -#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1) -#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2) -#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3) -#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT) -#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT) -#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT) -#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT) -#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT) -#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT) -#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B) -#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B) -#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0) -#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1) -#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3) -#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD) -#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH) -#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD) -#define IRQ_DoC (IRQ_GIC_START + INT_DoC) -#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A) -#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A) -#define IRQ_AACI (IRQ_GIC_START + INT_AACI) -#define IRQ_ETH (IRQ_GIC_START + INT_ETH) -#define IRQ_USB (IRQ_GIC_START + INT_USB) -#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0) -#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1) -#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2) -#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3) -#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0) -#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1) -#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2) -#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3) -#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4) -#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5) -#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6) -#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7) +#define IRQ_LOCALTIMER 29 +#define IRQ_LOCALWDOG 30 -#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1) -#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2) +#define IRQ_GIC_START 32 -#define IRQMASK_WDOGINT INTMASK_WDOGINT -#define IRQMASK_SOFTINT INTMASK_SOFTINT -#define IRQMASK_COMMRx INTMASK_COMMRx -#define IRQMASK_COMMTx INTMASK_COMMTx -#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 -#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 -#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 -#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 -#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 -#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 -#define IRQMASK_RTCINT INTMASK_RTCINT -#define IRQMASK_SSPINT INTMASK_SSPINT -#define IRQMASK_UARTINT0 INTMASK_UARTINT0 -#define IRQMASK_UARTINT1 INTMASK_UARTINT1 -#define IRQMASK_UARTINT2 INTMASK_UARTINT2 -#define IRQMASK_SCIINT INTMASK_SCIINT -#define IRQMASK_CLCDINT INTMASK_CLCDINT -#define IRQMASK_DMAINT INTMASK_DMAINT -#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT -#define IRQMASK_MBXINT INTMASK_MBXINT -#define IRQMASK_GNDINT INTMASK_GNDINT -#define IRQMASK_MMCI0B INTMASK_MMCI0B -#define IRQMASK_MMCI1B INTMASK_MMCI1B -#define IRQMASK_KMI0 INTMASK_KMI0 -#define IRQMASK_KMI1 INTMASK_KMI1 -#define IRQMASK_SCI3 INTMASK_SCI3 -#define IRQMASK_UART3 INTMASK_UART3 -#define IRQMASK_CLCD INTMASK_CLCD -#define IRQMASK_TOUCH INTMASK_TOUCH -#define IRQMASK_KEYPAD INTMASK_KEYPAD -#define IRQMASK_DoC INTMASK_DoC -#define IRQMASK_MMCI0A INTMASK_MMCI0A -#define IRQMASK_MMCI1A INTMASK_MMCI1A -#define IRQMASK_AACI INTMASK_AACI -#define IRQMASK_ETH INTMASK_ETH -#define IRQMASK_USB INTMASK_USB +#ifndef NR_IRQS +#error "NR_IRQS not defined by the board-specific files" +#endif -#define NR_IRQS (IRQ_GIC_START + 96) +#endif diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h index 6e0eab95a3a2..4fd351b5e4a2 100644 --- a/include/asm-arm/arch-realview/platform.h +++ b/include/asm-arm/arch-realview/platform.h @@ -18,8 +18,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __address_h -#define __address_h 1 +#ifndef __ASM_ARCH_PLATFORM_H +#define __ASM_ARCH_PLATFORM_H /* * Memory definitions @@ -81,11 +81,12 @@ #define REALVIEW_SYS_24MHz_OFFSET 0x5C #define REALVIEW_SYS_MISC_OFFSET 0x60 #define REALVIEW_SYS_IOSEL_OFFSET 0x70 -#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 -#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 -#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 -#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C -#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 +#define REALVIEW_SYS_PROCID_OFFSET 0x84 +#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0 +#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4 +#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8 +#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC +#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0 #define REALVIEW_SYS_BASE 0x10000000 #define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) @@ -114,6 +115,7 @@ #define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) #define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) #define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) +#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET) #define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) #define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) #define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) @@ -203,30 +205,8 @@ /* Reserved 0x1001A000 - 0x1001FFFF */ #define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ -#ifndef CONFIG_REALVIEW_MPCORE #define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ #define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ -#else -#ifdef CONFIG_REALVIEW_MPCORE_REVB -#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */ -#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ -#define REALVIEW_TWD_BASE 0x10100700 -#define REALVIEW_TWD_SIZE 0x00000100 -#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ -#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */ -#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ -#else -#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */ -#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ -#define REALVIEW_TWD_BASE 0x1F000700 -#define REALVIEW_TWD_SIZE 0x00000100 -#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ -#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */ -#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ -#endif -#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ -#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ -#endif #define REALVIEW_SMC_BASE 0x10080000 /* SMC */ /* Reserved 0x10090000 - 0x100EFFFF */ @@ -283,134 +263,6 @@ #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ -/* ------------------------------------------------------------------------ - * Interrupts - bit assignment (primary) - * ------------------------------------------------------------------------ - */ -#ifndef CONFIG_REALVIEW_MPCORE -#define INT_WDOGINT 0 /* Watchdog timer */ -#define INT_SOFTINT 1 /* Software interrupt */ -#define INT_COMMRx 2 /* Debug Comm Rx interrupt */ -#define INT_COMMTx 3 /* Debug Comm Tx interrupt */ -#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ -#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ -#define INT_GPIOINT0 6 /* GPIO 0 */ -#define INT_GPIOINT1 7 /* GPIO 1 */ -#define INT_GPIOINT2 8 /* GPIO 2 */ -/* 9 reserved */ -#define INT_RTCINT 10 /* Real Time Clock */ -#define INT_SSPINT 11 /* Synchronous Serial Port */ -#define INT_UARTINT0 12 /* UART 0 on development chip */ -#define INT_UARTINT1 13 /* UART 1 on development chip */ -#define INT_UARTINT2 14 /* UART 2 on development chip */ -#define INT_UARTINT3 15 /* UART 3 on development chip */ -#define INT_SCIINT 16 /* Smart Card Interface */ -#define INT_MMCI0A 17 /* Multimedia Card 0A */ -#define INT_MMCI0B 18 /* Multimedia Card 0B */ -#define INT_AACI 19 /* Audio Codec */ -#define INT_KMI0 20 /* Keyboard/Mouse port 0 */ -#define INT_KMI1 21 /* Keyboard/Mouse port 1 */ -#define INT_CHARLCD 22 /* Character LCD */ -#define INT_CLCDINT 23 /* CLCD controller */ -#define INT_DMAINT 24 /* DMA controller */ -#define INT_PWRFAILINT 25 /* Power failure */ -#define INT_PISMO 26 -#define INT_DoC 27 /* Disk on Chip memory controller */ -#define INT_ETH 28 /* Ethernet controller */ -#define INT_USB 29 /* USB controller */ -#define INT_TSPENINT 30 /* Touchscreen pen */ -#define INT_TSKPADINT 31 /* Touchscreen keypad */ - -#else - -#define MAX_GIC_NR 2 - -#define INT_AACI 0 -#define INT_TIMERINT0_1 1 -#define INT_TIMERINT2_3 2 -#define INT_USB 3 -#define INT_UARTINT0 4 -#define INT_UARTINT1 5 -#define INT_RTCINT 6 -#define INT_KMI0 7 -#define INT_KMI1 8 -#define INT_ETH 9 -#define INT_EB_IRQ1 10 /* main GIC */ -#define INT_EB_IRQ2 11 /* tile GIC */ -#define INT_EB_FIQ1 12 /* main GIC */ -#define INT_EB_FIQ2 13 /* tile GIC */ -#define INT_MMCI0A 14 -#define INT_MMCI0B 15 - -#define INT_PMU_CPU0 17 -#define INT_PMU_CPU1 18 -#define INT_PMU_CPU2 19 -#define INT_PMU_CPU3 20 -#define INT_PMU_SCU0 21 -#define INT_PMU_SCU1 22 -#define INT_PMU_SCU2 23 -#define INT_PMU_SCU3 24 -#define INT_PMU_SCU4 25 -#define INT_PMU_SCU5 26 -#define INT_PMU_SCU6 27 -#define INT_PMU_SCU7 28 - -#define INT_L220_EVENT 29 -#define INT_L220_SLAVE 30 -#define INT_L220_DECODE 31 - -#define INT_UARTINT2 -1 -#define INT_UARTINT3 -1 -#define INT_CLCDINT -1 -#define INT_DMAINT -1 -#define INT_WDOGINT -1 -#define INT_GPIOINT0 -1 -#define INT_GPIOINT1 -1 -#define INT_GPIOINT2 -1 -#define INT_SCIINT -1 -#define INT_SSPINT -1 -#endif - -/* - * Interrupt bit positions - * - */ -#define INTMASK_WDOGINT (1 << INT_WDOGINT) -#define INTMASK_SOFTINT (1 << INT_SOFTINT) -#define INTMASK_COMMRx (1 << INT_COMMRx) -#define INTMASK_COMMTx (1 << INT_COMMTx) -#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) -#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) -#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) -#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) -#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) -#define INTMASK_RTCINT (1 << INT_RTCINT) -#define INTMASK_SSPINT (1 << INT_SSPINT) -#define INTMASK_UARTINT0 (1 << INT_UARTINT0) -#define INTMASK_UARTINT1 (1 << INT_UARTINT1) -#define INTMASK_UARTINT2 (1 << INT_UARTINT2) -#define INTMASK_UARTINT3 (1 << INT_UARTINT3) -#define INTMASK_SCIINT (1 << INT_SCIINT) -#define INTMASK_MMCI0A (1 << INT_MMCI0A) -#define INTMASK_MMCI0B (1 << INT_MMCI0B) -#define INTMASK_AACI (1 << INT_AACI) -#define INTMASK_KMI0 (1 << INT_KMI0) -#define INTMASK_KMI1 (1 << INT_KMI1) -#define INTMASK_CHARLCD (1 << INT_CHARLCD) -#define INTMASK_CLCDINT (1 << INT_CLCDINT) -#define INTMASK_DMAINT (1 << INT_DMAINT) -#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) -#define INTMASK_PISMO (1 << INT_PISMO) -#define INTMASK_DoC (1 << INT_DoC) -#define INTMASK_ETH (1 << INT_ETH) -#define INTMASK_USB (1 << INT_USB) -#define INTMASK_TSPENINT (1 << INT_TSPENINT) -#define INTMASK_TSKPADINT (1 << INT_TSKPADINT) - -#define MAXIRQNUM 31 -#define MAXFIQNUM 31 -#define MAXSWINUM 31 - /* * Application Flash * @@ -463,6 +315,4 @@ #define REALVIEW_CSR_BASE 0x10000000 #define REALVIEW_CSR_SIZE 0x10000000 -#endif - -/* END */ +#endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h index cc293640178e..08b3db883c36 100644 --- a/include/asm-arm/arch-realview/scu.h +++ b/include/asm-arm/arch-realview/scu.h @@ -1,8 +1,8 @@ #ifndef __ASMARM_ARCH_SCU_H #define __ASMARM_ARCH_SCU_H -#include +#include -#define SCU_BASE REALVIEW_MPCORE_SCU_BASE +#define SCU_BASE REALVIEW_EB11MP_SCU_BASE #endif diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h index f05631d76743..3d5c2db07a26 100644 --- a/include/asm-arm/arch-realview/uncompress.h +++ b/include/asm-arm/arch-realview/uncompress.h @@ -19,6 +19,8 @@ */ #include +#include + #define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) #define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) #define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) -- cgit v1.2.3 From 7dd19e755dbe481ae42590dbd921dfd47e94779c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:39:00 +0100 Subject: [ARM] 4818/1: RealView: Add core-tile detection This patch adds the core-tile detection and only enables devices if the corresponding tile is present. It currently detects the ARM11MPCore via the core_tile_eb11mp() macro. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/arch-realview/board-eb.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h index 943efc5de4eb..9e76b236b529 100644 --- a/include/asm-arm/arch-realview/board-eb.h +++ b/include/asm-arm/arch-realview/board-eb.h @@ -149,4 +149,23 @@ #define MAX_GIC_NR NR_GIC_EB11MP #endif +/* + * Core tile identification (REALVIEW_SYS_PROCID) + */ +#define REALVIEW_EB_PROC_MASK 0xFF000000 +#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000 +#define REALVIEW_EB_PROC_ARM9 0x02000000 +#define REALVIEW_EB_PROC_ARM11 0x04000000 +#define REALVIEW_EB_PROC_ARM11MP 0x06000000 + +#define check_eb_proc(proc_type) \ + ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \ + == proc_type) + +#ifdef CONFIG_REALVIEW_MPCORE +#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP) +#else +#define core_tile_eb11mp() 0 +#endif + #endif /* __ASM_ARCH_BOARD_EB_H */ -- cgit v1.2.3 From c4057f5260650f165054bc56e16acc4aa0510d4f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:41:01 +0100 Subject: [ARM] 4819/1: RealView: Fix entry-macro.S to work with multiple platforms This patch modifies the get_irqnr_preamble macro to work with multiple platforms at run-time by reading the address of the GIC controller from the gic_cpu_base_addr variable. This variable is defined in core.c and intialised in realview_eb.c (gic_init_irq). Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/arch-realview/entry-macro.S | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 629944deed50..cd26306d8e57 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -9,17 +9,13 @@ */ #include #include -#include .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp -#ifdef CONFIG_REALVIEW_MPCORE - ldr \base, =IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE) -#else - ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) -#endif + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] .endm .macro arch_ret_to_user, tmp1, tmp2 -- cgit v1.2.3 From 41579f49da23e2d26b6e5efa5c3311998e911e5c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:47:04 +0100 Subject: [ARM] 4822/1: RealView: Change the REALVIEW_MPCORE configuration option This patch changes the REALVIEW_MPCORE configuration option to REALVIEW_EB_ARM11MP since this is only specific to RealView/EB. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/arch-realview/board-eb.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h index 9e76b236b529..3e437b7f425a 100644 --- a/include/asm-arm/arch-realview/board-eb.h +++ b/include/asm-arm/arch-realview/board-eb.h @@ -26,7 +26,7 @@ /* * RealView EB + ARM11MPCore peripheral addresses */ -#ifdef CONFIG_REALVIEW_MPCORE_REVB +#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB #define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ #define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ #define REALVIEW_EB11MP_TWD_BASE 0x10100700 @@ -143,7 +143,7 @@ #define NR_IRQS NR_IRQS_EB #endif -#if defined(CONFIG_REALVIEW_MPCORE) \ +#if defined(CONFIG_REALVIEW_EB_ARM11MP) \ && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) #undef MAX_GIC_NR #define MAX_GIC_NR NR_GIC_EB11MP @@ -162,7 +162,7 @@ ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \ == proc_type) -#ifdef CONFIG_REALVIEW_MPCORE +#ifdef CONFIG_REALVIEW_EB_ARM11MP #define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP) #else #define core_tile_eb11mp() 0 -- cgit v1.2.3