From cbf4f7325a638ced1d815580dfed44ea3b76163c Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Wed, 19 Jun 2019 20:36:32 +0200 Subject: i3c: add mixed limited bus mode The i3c bus spec defines a bus configuration where i2c devices don't have a 50ns filter but support SCL running at SDR max rate (12.5MHz). This patch introduces the limited bus mode so that users can use a higher speed in presence of i2c devices index 1. Signed-off-by: Vitor Soares Cc: Boris Brezillon Cc: Signed-off-by: Boris Brezillon --- include/linux/i3c/master.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux/i3c') diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index eca8337bdaa5..1f08fa8d69d2 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -250,12 +250,17 @@ struct i3c_device { * the bus. The only impact in this mode is that the * high SCL pulse has to stay below 50ns to trick I2C * devices when transmitting I3C frames + * @I3C_BUS_MODE_MIXED_LIMITED: I2C devices without 50ns spike filter are + * present on the bus. However they allow + * compliance up to the maximum SDR SCL clock + * frequency. * @I3C_BUS_MODE_MIXED_SLOW: I2C devices without 50ns spike filter are present * on the bus */ enum i3c_bus_mode { I3C_BUS_MODE_PURE, I3C_BUS_MODE_MIXED_FAST, + I3C_BUS_MODE_MIXED_LIMITED, I3C_BUS_MODE_MIXED_SLOW, }; -- cgit v1.2.3