blob: 96de41d32b3eb741cbbcb5267f34f1ad052d76c9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
|
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 Detail Enhancement Unit Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
description: |
The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
can sharpen the display content in both luma and chroma channels.
properties:
compatible:
const: allwinner,sun9i-a80-deu
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: The DEU interface clock
- description: The DEU module clock
- description: The DEU DRAM clock
clock-names:
items:
- const: ahb
- const: mod
- const: ram
resets:
maxItems: 1
ports:
type: object
description: |
A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
port@0:
type: object
description: |
Input endpoints of the controller.
port@1:
type: object
description: |
Output endpoints of the controller.
required:
- "#address-cells"
- "#size-cells"
- port@0
- port@1
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun9i-a80-de.h>
#include <dt-bindings/reset/sun9i-a80-de.h>
deu0: deu@3300000 {
compatible = "allwinner,sun9i-a80-deu";
reg = <0x03300000 0x40000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&de_clocks CLK_BUS_DEU0>,
<&de_clocks CLK_IEP_DEU0>,
<&de_clocks CLK_DRAM_DEU0>;
clock-names = "ahb",
"mod",
"ram";
resets = <&de_clocks RST_DEU0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
deu0_in: port@0 {
reg = <0>;
deu0_in_fe0: endpoint {
remote-endpoint = <&fe0_out_deu0>;
};
};
deu0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
deu0_out_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_in_deu0>;
};
deu0_out_be1: endpoint@1 {
reg = <1>;
remote-endpoint = <&be1_in_deu0>;
};
};
};
};
...
|
