summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
blob: fd93b941f07ae6e5a165e9239cba4f961eadc0a7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SuperSpeed DWC3 USB SoC controller

maintainers:
  - Manu Gautam <mgautam@codeaurora.org>

properties:
  compatible:
    items:
      - enum:
          - qcom,msm8996-dwc3
          - qcom,msm8998-dwc3
          - qcom,sc7180-dwc3
          - qcom,sdm845-dwc3
          - qcom,sdx55-dwc3
      - const: qcom,dwc3

  reg:
    description: Offset and length of register set for QSCRATCH wrapper
    maxItems: 1

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  power-domains:
    description: specifies a phandle to PM domain provider node
    maxItems: 1

  clocks:
    description:
      A list of phandle and clock-specifier pairs for the clocks
      listed in clock-names.
    items:
      - description: System Config NOC clock.
      - description: Master/Core clock, has to be >= 125 MHz
          for SS operation and >= 60MHz for HS operation.
      - description: System bus AXI clock.
      - description: Mock utmi clock needed for ITP/SOF generation
          in host mode. Its frequency should be 19.2MHz.
      - description: Sleep clock, used for wakeup when
          USB3 core goes into low power mode (U3).

  clock-names:
    items:
      - const: cfg_noc
      - const: core
      - const: iface
      - const: mock_utmi
      - const: sleep

  assigned-clocks:
    items:
      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
      - description: Phandle and clock specifoer of MASTER_CLK.

  assigned-clock-rates:
    items:
      - description: Must be 19.2MHz (19200000).
      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
  resets:
    maxItems: 1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: usb-ddr
      - const: apps-usb

  interrupts:
    items:
      - description: The interrupt that is asserted
          when a wakeup event is received on USB2 bus.
      - description: The interrupt that is asserted
          when a wakeup event is received on USB3 bus.
      - description: Wakeup event on DM line.
      - description: Wakeup event on DP line.

  interrupt-names:
    items:
      - const: hs_phy_irq
      - const: ss_phy_irq
      - const: dm_hs_phy_irq
      - const: dp_hs_phy_irq

  qcom,select-utmi-as-pipe-clk:
    description:
      If present, disable USB3 pipe_clk requirement.
      Used when dwc3 operates without SSPHY and only
      HS/FS/LS modes are supported.
    type: boolean

# Required child node:

patternProperties:
  "^dwc3@[0-9a-f]+$":
    type: object
    description:
      A child node must exist to represent the core DWC3 IP block
      The content of the node is defined in dwc3.txt.

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - power-domains
  - clocks
  - clock-names
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        usb@a6f8800 {
            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
            reg = <0 0x0a6f8800 0 0x400>;

            #address-cells = <2>;
            #size-cells = <2>;
            ranges;
            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
            clock-names = "cfg_noc", "core", "iface", "mock_utmi",
                      "sleep";

            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
            assigned-clock-rates = <19200000>, <150000000>;

            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "hs_phy_irq", "ss_phy_irq",
                          "dm_hs_phy_irq", "dp_hs_phy_irq";

            power-domains = <&gcc USB30_PRIM_GDSC>;

            resets = <&gcc GCC_USB30_PRIM_BCR>;

            dwc3@a600000 {
                compatible = "snps,dwc3";
                reg = <0 0x0a600000 0 0xcd00>;
                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
                iommus = <&apps_smmu 0x740 0>;
                snps,dis_u2_susphy_quirk;
                snps,dis_enblslpm_quirk;
                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
                phy-names = "usb2-phy", "usb3-phy";
            };
        };
    };