blob: f9345e02ca49e069b846563dc474432b77377b45 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
#include "socfpga.dtsi"
/ {
model = "Altera SOCFPGA VT";
compatible = "altr,socfpga-vt", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,57600";
};
memory {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1 GB */
};
soc {
clkmgr@ffd04000 {
clocks {
osc1 {
clock-frequency = <10000000>;
};
};
};
dwmmc0@ff704000 {
num-slots = <1>;
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
};
ethernet@ff700000 {
phy-mode = "gmii";
status = "okay";
};
timer0@ffc08000 {
clock-frequency = <7000000>;
};
timer1@ffc09000 {
clock-frequency = <7000000>;
};
timer2@ffd00000 {
clock-frequency = <7000000>;
};
timer3@ffd01000 {
clock-frequency = <7000000>;
};
serial0@ffc02000 {
clock-frequency = <7372800>;
};
serial1@ffc03000 {
clock-frequency = <7372800>;
};
sysmgr@ffd08000 {
cpu1-start-addr = <0xffd08010>;
};
};
};
&gmac0 {
status = "okay";
phy-mode = "gmii";
};
|
