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/dts-v1/;
/memreserve/ 0x00000000 0x00001000; // reserved
/memreserve/ 0x00001000 0x000ef000; // ROM data
/memreserve/ 0x000f0000 0x004cc000; // reserved
#include <dt-bindings/interrupt-controller/mips-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mti,sead-3";
interrupt-parent = <&gic>;
chosen {
stdout-path = "uart1:115200";
};
aliases {
uart0 = &uart0;
uart1 = &uart1;
};
cpus {
cpu@0 {
compatible = "mti,mips14KEc", "mti,mips14Kc";
};
};
memory {
device_type = "memory";
reg = <0x0 0x08000000>;
};
cpu_intc: interrupt-controller {
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
gic: interrupt-controller@1b1c0000 {
compatible = "mti,gic";
reg = <0x1b1c0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
/*
* Declare the interrupt-parent even though the mti,gic
* binding doesn't require it, such that the kernel can
* figure out that cpu_intc is the root interrupt
* controller & should be probed first.
*/
interrupt-parent = <&cpu_intc>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
};
};
/* UART connected to FTDI & miniUSB socket */
uart0: uart@1f000900 {
compatible = "ns16550a";
reg = <0x1f000900 0x20>;
reg-io-width = <4>;
reg-shift = <2>;
clock-frequency = <14745600>;
interrupts = <3>; /* GIC 3 or CPU 4 */
no-loopback-test;
};
/* UART connected to RS232 socket */
uart1: uart@1f000800 {
compatible = "ns16550a";
reg = <0x1f000800 0x20>;
reg-io-width = <4>;
reg-shift = <2>;
clock-frequency = <14745600>;
interrupts = <2>; /* GIC 2 or CPU 4 */
no-loopback-test;
};
eth@1f010000 {
compatible = "smsc,lan9115";
reg = <0x1f010000 0x10000>;
reg-io-width = <4>;
interrupts = <0>; /* GIC 0 or CPU 6 */
phy-mode = "mii";
smsc,irq-push-pull;
smsc,save-mac-address;
};
};
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