summaryrefslogtreecommitdiffstats
path: root/arch/mips/nxp/pnx8550/stb810/board_setup.c
blob: 1282c27cfcb7fe1e2255f675fb32e8aa518657f1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
/*
 *  STB810 specific board startup routines.
 *
 *  Based on the arch/mips/nxp/pnx8550/jbs/board_setup.c
 *
 *  Author: MontaVista Software, Inc.
 *          source@mvista.com
 *
 *  Copyright 2005 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 */

#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/console.h>
#include <linux/mc146818rtc.h>
#include <linux/delay.h>

#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
#include <asm/pgtable.h>

#include <glb.h>

void __init board_setup(void)
{
	unsigned long config0, configpr;

	config0 = read_c0_config();

	/* clear all three cache coherency fields */
	config0 &= ~(0x7 | (7<<25) | (7<<28));
	config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
			(CONF_CM_DEFAULT<<28));
	write_c0_config(config0);

	configpr = read_c0_config7();
	configpr |= (1<<19); /* enable tlb */
	write_c0_config7(configpr);
}