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| author | Tianling Shen <cnsztl@immortalwrt.org> | 2024-05-09 16:03:08 +0800 |
|---|---|---|
| committer | Nick Hainke <vincent@systemli.org> | 2024-05-09 10:43:37 +0200 |
| commit | 0341a06f1f22cf1d4de81bc5501364342a388e0f (patch) | |
| tree | e19a538fe17a35624a59f30997b41f5e823071fd | |
| parent | 592b6aabca48246e452b702496796fee258a8466 (diff) | |
| download | openwrt-0341a06f1f22cf1d4de81bc5501364342a388e0f.tar.gz openwrt-0341a06f1f22cf1d4de81bc5501364342a388e0f.tar.bz2 openwrt-0341a06f1f22cf1d4de81bc5501364342a388e0f.zip | |
rockchip: switch to kernel 6.6
Switch to Linux kernel version 6.6 and drop configs, files and patches
for Linux 6.1.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
44 files changed, 1 insertions, 6494 deletions
diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index 75423f70ef..26af6855ac 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -7,8 +7,7 @@ BOARDNAME:=Rockchip FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs SUBTARGETS:=armv8 -KERNEL_PATCHVER:=6.1 -KERNEL_TESTING_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.6 define Target/Description Build firmware image for Rockchip SoC devices. diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1 deleted file mode 100644 index 6337245ff8..0000000000 --- a/target/linux/rockchip/armv8/config-6.1 +++ /dev/null @@ -1,709 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=33 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARC_EMAC_CORE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CNP=y -CONFIG_ARM64_EPAN=y -CONFIG_ARM64_ERRATUM_2051678=y -CONFIG_ARM64_ERRATUM_2054223=y -CONFIG_ARM64_ERRATUM_2067961=y -CONFIG_ARM64_ERRATUM_2077057=y -CONFIG_ARM64_ERRATUM_2658417=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_858921=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_PTR_AUTH_KERNEL=y -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_SME=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=48 -# CONFIG_ARM64_VA_BITS_39 is not set -CONFIG_ARM64_VA_BITS_48=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MHU=y -CONFIG_ARM_MHU_V2=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_SCMI_HAVE_SHMEM=y -CONFIG_ARM_SCMI_HAVE_TRANSPORT=y -CONFIG_ARM_SCMI_POWER_CONTROL=y -CONFIG_ARM_SCMI_POWER_DOMAIN=y -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y -CONFIG_ARM_SCMI_TRANSPORT_SMC=y -CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_V3=y -# CONFIG_ARM_SMMU_V3_SVA is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_BSG_COMMON=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CHARGER_GPIO=y -# CONFIG_CHARGER_RK817 is not set -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -CONFIG_CLK_RK3568=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SYSFS is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_COMMON_CLK_SCMI=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC64=y -CONFIG_CRC64_ROCKSOFT=y -CONFIG_CRC_T10DIF=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC64_ROCKSOFT=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DEV_ROCKCHIP is not set -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_POLYVAL=y -CONFIG_CRYPTO_POLYVAL_ARM64_CE=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SM3=y -CONFIG_CRYPTO_SM3_NEON=y -CONFIG_CRYPTO_SM4=y -CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y -CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DEVMEM=y -# CONFIG_DEVPORT is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DT_IDLE_GENPD=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DWMAC_DWC_QOS_ETH=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_ROCKCHIP=y -CONFIG_DW_WATCHDOG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_EMAC_ROCKCHIP=y -CONFIG_ENERGY_MODEL=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FANOTIFY=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FORTIFY_SOURCE is not set -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_ROCKCHIP=y -CONFIG_GPIO_SYSCON=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_PCIE is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_ROCKCHIP=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_RK3X=y -CONFIG_IIO=y -# CONFIG_IIO_SCMI is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INDIRECT_PIO=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_MATRIXKMAP=y -CONFIG_INPUT_RK805_PWRKEY=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set -CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_IO_PGTABLE=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_DART is not set -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IO_STRICT_DEVMEM is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KEXEC_CORE=y -CONFIG_KEXEC_FILE=y -CONFIG_KSM=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOG_BUF_SHIFT=19 -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_GPIO=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_KHADAS_MCU is not set -CONFIG_MFD_RK808=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_DW=y -# CONFIG_MMC_DW_BLUEFIELD is not set -# CONFIG_MMC_DW_EXYNOS is not set -# CONFIG_MMC_DW_HI3798CV200 is not set -# CONFIG_MMC_DW_K3 is not set -# CONFIG_MMC_DW_PCI is not set -CONFIG_MMC_DW_PLTFM=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MOTORCOMM_PHY=y -CONFIG_MQ_IOSCHED_DEADLINE=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -CONFIG_NET_DSA_MT7530_MMIO=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=256 -CONFIG_NVMEM=y -CONFIG_NVMEM_ROCKCHIP_EFUSE=y -# CONFIG_NVMEM_ROCKCHIP_OTP is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_PME=y -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_DW_HOST=y -CONFIG_PCIE_ROCKCHIP_HOST=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_STUB=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PCS_XPCS=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_ROCKCHIP_DP=y -# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set -CONFIG_PHY_ROCKCHIP_EMMC=y -# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y -CONFIG_PHY_ROCKCHIP_PCIE=y -CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_ROCKCHIP_USB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_RK805=y -CONFIG_PINCTRL_ROCKCHIP=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PL330_DMA=y -CONFIG_PLATFORM_MHU=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_BUILD=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_VMCORE=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SYSFS=y -# CONFIG_QFMT_V2 is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -CONFIG_RAID_ATTRS=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_RCU_TRACE=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_ARM_SCMI=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_RK808=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SCMI=y -CONFIG_RFS_ACCEL=y -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_ROCKCHIP_MBOX=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -# CONFIG_ROCKCHIP_SARADC is not set -CONFIG_ROCKCHIP_THERMAL=y -CONFIG_ROCKCHIP_TIMER=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RSEQ=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_HYM8563=y -CONFIG_RTC_DRV_RK808=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_NVMEM=y -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SAS_LIBSAS=y -# CONFIG_SECURITY_DMESG_RESTRICT is not set -CONFIG_SENSORS_ARM_SCMI=y -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_AMBAKMI=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_ROCKCHIP_SFC=y -CONFIG_SPI_SPIDEV=y -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SRAM=y -CONFIG_SRCU=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_PER_TASK=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_STACKTRACE=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_STRICT_DEVMEM=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_SWAP is not set -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_SYSCALL=y -# CONFIG_TEXTSEARCH is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_CLOCK=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TRANS_TABLE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TYPEC=y -# CONFIG_TYPEC_ANX7411 is not set -CONFIG_TYPEC_FUSB302=y -# CONFIG_TYPEC_HD3SS3220 is not set -# CONFIG_TYPEC_MUX_FSA4480 is not set -# CONFIG_TYPEC_MUX_PI3USB30532 is not set -# CONFIG_TYPEC_RT1719 is not set -# CONFIG_TYPEC_STUSB160X is not set -# CONFIG_TYPEC_TCPCI is not set -CONFIG_TYPEC_TCPM=y -# CONFIG_TYPEC_TPS6598X is not set -# CONFIG_TYPEC_WUSB3801 is not set -# CONFIG_UACCE is not set -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UEVENT_HELPER is not set -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_HOST=y -CONFIG_USB_DWC3_OF_SIMPLE=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_HID=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -# CONFIG_VIRTIO_MENU is not set -CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XARRAY_MULTI=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch b/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch deleted file mode 100644 index 2bb542be36..0000000000 --- a/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch +++ /dev/null @@ -1,60 +0,0 @@ -From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001 -From: Shawn Lin <shawn.lin@rock-chips.com> -Date: Thu, 2 Feb 2023 08:35:16 +0800 -Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for - rockchip platform - -For Rockchip platform, DLL bypass bit and start bit need to be set if -DLL is not locked. And adjust pre-change delay to 0x3 for better signal -test result. - -Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> -Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com -Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> ---- - drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - ---- a/drivers/mmc/host/sdhci-of-dwcmshc.c -+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c -@@ -48,6 +48,7 @@ - #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 - #define DWCMSHC_EMMC_DLL_START_POINT 16 - #define DWCMSHC_EMMC_DLL_INC 8 -+#define DWCMSHC_EMMC_DLL_BYPASS BIT(24) - #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) - #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 - #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA -@@ -60,6 +61,7 @@ - #define DLL_RXCLK_NO_INVERTER 1 - #define DLL_RXCLK_INVERTER 0 - #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 -+#define DLL_RXCLK_ORI_GATE BIT(31) - #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) - #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) - #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) -@@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str - sdhci_writel(host, extra, reg); - - if (clock <= 52000000) { -- /* Disable DLL and reset both of sample and drive clock */ -- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); -- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK); -+ /* -+ * Disable DLL and reset both of sample and drive clock. -+ * The bypass bit and start bit need to be set if DLL is not locked. -+ */ -+ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); -+ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); - sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); - /* -@@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str - } - - extra = 0x1 << 16 | /* tune clock stop en */ -- 0x2 << 17 | /* pre-change delay */ -+ 0x3 << 17 | /* pre-change delay */ - 0x3 << 19; /* post-change delay */ - sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); - diff --git a/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch b/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch deleted file mode 100644 index 9d9c1b5c1c..0000000000 --- a/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001 -From: Vasily Khoruzhick <anarsoul@gmail.com> -Date: Thu, 9 Mar 2023 17:03:49 -0800 -Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on - Rockchip - -Currently .get_max_clock returns the current clock rate for cclk_emmc -on rk35xx, thus max clock gets set to whatever bootloader set it to. - -In case of u-boot, it is intentionally reset to 50 MHz if it boots -from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and -HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit -clears appropriate caps if host->mmc->f_max is < 52MHz - -cclk_emmc is not a fixed clock on rk35xx, so using -sdhci_pltfm_clk_get_max_clock is not appropriate here. - -Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc. - -Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> -Acked-by: Adrian Hunter <adrian.hunter@intel.com> -Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com -Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> ---- - drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/drivers/mmc/host/sdhci-of-dwcmshc.c -+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c -@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc - return pltfm_host->clock; - } - -+static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) -+{ -+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); -+ -+ return clk_round_rate(pltfm_host->clk, ULONG_MAX); -+} -+ - static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, - struct mmc_request *mrq) - { -@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm - .set_clock = dwcmshc_rk3568_set_clock, - .set_bus_width = sdhci_set_bus_width, - .set_uhs_signaling = dwcmshc_set_uhs_signaling, -- .get_max_clock = sdhci_pltfm_clk_get_max_clock, -+ .get_max_clock = rk35xx_get_max_clock, - .reset = rk35xx_sdhci_reset, - .adma_write_desc = dwcmshc_adma_write_desc, - }; diff --git a/target/linux/rockchip/patches-6.1/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch b/target/linux/rockchip/patches-6.1/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch deleted file mode 100644 index 049c8ad1af..0000000000 --- a/target/linux/rockchip/patches-6.1/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Sat, 25 Mar 2023 15:40:20 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C - -The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC -chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++ - 2 files changed, 41 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9 - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com> -+ */ -+ -+/dts-v1/; -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R2C"; -+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8521s>; -+ tx_delay = <0x22>; -+ rx_delay = <0x12>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8521s: ethernet-phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch b/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch deleted file mode 100644 index 4e48218b89..0000000000 --- a/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch +++ /dev/null @@ -1,407 +0,0 @@ -From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001 -From: Chukun Pan <amadeus@jmu.edu.cn> -Date: Sat, 3 Dec 2022 15:41:49 +0800 -Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus - -Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. - -This device is similar to the NanoPi R2S, and has a 16MB -SPI NOR (mx25l12805d). The reset button is changed to -directly reset the power supply, another detail is that -both network ports have independent MAC addresses. - -Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> -Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++ - 2 files changed, 374 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1 - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -0,0 +1,373 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Based on rk3328-nanopi-r2s.dts, which is: -+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net> -+ */ -+ -+/dts-v1/; -+ -+#include <dt-bindings/gpio/gpio.h> -+#include <dt-bindings/leds/common.h> -+#include "rk3328.dtsi" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus"; -+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; -+ -+ aliases { -+ ethernet1 = &rtl8153; -+ mmc0 = &sdmmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ gmac_clk: gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ pinctrl-names = "default"; -+ -+ led-0 { -+ function = LED_FUNCTION_LAN; -+ color = <LED_COLOR_ID_GREEN>; -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = <LED_COLOR_ID_RED>; -+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led-2 { -+ function = LED_FUNCTION_WAN; -+ color = <LED_COLOR_ID_GREEN>; -+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&sdmmc0m1_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vcc_sd"; -+ regulator-boot-on; -+ vin-supply = <&vcc_io>; -+ }; -+ -+ vcc_sys: vcc-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vdd_5v_lan: vdd-5v-lan-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&lan_vdd_pin>; -+ pinctrl-names = "default"; -+ regulator-name = "vdd_5v_lan"; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc_sys>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&display_subsystem { -+ status = "disabled"; -+}; -+ -+&gmac2io { -+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -+ clock_in_out = "input"; -+ phy-handle = <&rtl8211e>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_io>; -+ pinctrl-0 = <&rgmiim1_pins>; -+ pinctrl-names = "default"; -+ snps,aal; -+ rx_delay = <0x18>; -+ tx_delay = <0x24>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211e: ethernet-phy@1 { -+ reg = <1>; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ rk805: pmic@18 { -+ compatible = "rockchip,rk805"; -+ reg = <0x18>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk805-clkout2"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-0 = <&pmic_int_l>; -+ pinctrl-names = "default"; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_io>; -+ vcc6-supply = <&vcc_sys>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1450000>; -+ regulator-ramp-delay = <12500>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_io: DCDC_REG4 { -+ regulator-name = "vcc_io"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_18: LDO_REG1 { -+ regulator-name = "vcc_18"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc18_emmc: LDO_REG2 { -+ regulator-name = "vcc18_emmc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_10: LDO_REG3 { -+ regulator-name = "vdd_10"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&io_domains { -+ pmuio-supply = <&vcc_io>; -+ vccio1-supply = <&vcc_io>; -+ vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_io>; -+ vccio4-supply = <&vcc_io>; -+ vccio5-supply = <&vcc_io>; -+ vccio6-supply = <&vcc_io>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gmac2io { -+ eth_phy_reset_pin: eth-phy-reset-pin { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ lan { -+ lan_vdd_pin: lan-vdd-pin { -+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; -+ pinctrl-names = "default"; -+ vmmc-supply = <&vcc_sd>; -+ status = "okay"; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ }; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&u2phy { -+ status = "okay"; -+}; -+ -+&u2phy_host { -+ status = "okay"; -+}; -+ -+&u2phy_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb20_otg { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdrd3 { -+ dr_mode = "host"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* Second port is for USB 3.0 */ -+ rtl8153: device@2 { -+ compatible = "usbbda,8153"; -+ reg = <2>; -+ }; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch deleted file mode 100644 index 78d3d51a17..0000000000 --- a/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Sat, 25 Mar 2023 15:40:22 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS - -The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with -the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise -identical to OrangePi R1 Plus. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++ - 2 files changed, 41 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -@@ -0,0 +1,40 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2016 Xunlong Software. Co., Ltd. -+ * (http://www.orangepi.org) -+ * -+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com> -+ */ -+ -+/dts-v1/; -+#include "rk3328-orangepi-r1-plus.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus LTS"; -+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8531c>; -+ tx_delay = <0x19>; -+ rx_delay = <0x05>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8531c: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <15000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch b/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch deleted file mode 100644 index 3d502a65b6..0000000000 --- a/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch +++ /dev/null @@ -1,754 +0,0 @@ -From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001 -From: Vasily Khoruzhick <anarsoul@gmail.com> -Date: Tue, 7 Mar 2023 22:32:40 -0800 -Subject: [PATCH] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S - -FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device. - -Board Specifications -- Rockchip RK3568 -- 2 or 4GB LPDDR4X -- 8GB or 16GB eMMC, SD card slot -- GbE LAN (Native) -- 2x 2.5G LAN (PCIe) -- M.2 Connector -- HDMI 2.0, MIPI DSI/CSI -- 2xUSB 3.0 Host -- USB Type C PD, 5V/9V/12V -- GPIO: 12-pin 0.5mm FPC connector - -Based on Tianling Shen's <cnsztl@gmail.com> work. - -Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> -Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 713 ++++++++++++++++++ - 2 files changed, 714 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -74,4 +74,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -@@ -0,0 +1,713 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyelec.com) -+ * -+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> -+ */ -+ -+/dts-v1/; -+#include <dt-bindings/gpio/gpio.h> -+#include <dt-bindings/input/input.h> -+#include <dt-bindings/leds/common.h> -+#include <dt-bindings/pinctrl/rockchip.h> -+#include <dt-bindings/soc/rockchip,vop2.h> -+#include "rk3568.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R5S"; -+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; -+ -+ aliases { -+ ethernet0 = &gmac0; -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; -+ -+ led-lan1 { -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <1>; -+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-lan2 { -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <2>; -+ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ power_led: led-power { -+ color = <LED_COLOR_ID_RED>; -+ function = LED_FUNCTION_POWER; -+ linux,default-trigger = "heartbeat"; -+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-wan { -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_WAN; -+ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ vdd_usbc: vdd-usbc-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_usbc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vdd_usbc>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vdd_usbc>; -+ }; -+ -+ vcc3v3_pcie: vcc3v3-pcie-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <200000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_usb: vcc5v0-usb-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vdd_usbc>; -+ }; -+ -+ vcc5v0_usb_host: vcc5v0-usb-host-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_host_en>; -+ regulator-name = "vcc5v0_usb_host"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en>; -+ regulator-name = "vcc5v0_usb_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ pcie30_avdd0v9: pcie30-avdd0v9-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ pcie30_avdd1v8: pcie30-avdd1v8-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+}; -+ -+&combphy0 { -+ status = "okay"; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&combphy2 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gmac0 { -+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; -+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; -+ assigned-clock-rates = <0>, <125000000>; -+ clock_in_out = "output"; -+ phy-handle = <&rgmii_phy0>; -+ phy-mode = "rgmii-id"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac0_miim -+ &gmac0_tx_bus2 -+ &gmac0_rx_bus2 -+ &gmac0_rgmii_clk -+ &gmac0_rgmii_bus>; -+ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ /* Reset time is 15ms, 50ms for rtl8211f */ -+ snps,reset-delays-us = <0 15000 50000>; -+ tx_delay = <0x3c>; -+ rx_delay = <0x2f>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ rockchip,system-power-controller; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <950000>; -+ regulator-max-microvolt = <950000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ -+ }; -+}; -+ -+&i2c5 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <0>; -+ clock-output-names = "rtcic_32kout"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ wakeup-source; -+ }; -+}; -+ -+&i2s0_8ch { -+ status = "okay"; -+}; -+ -+&i2s1_8ch { -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ -+&mdio0 { -+ rgmii_phy0: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ pinctrl-0 = <ð_phy0_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pcie2x1 { -+ num-lanes = <1>; -+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ data-lanes = <1 2>; -+ status = "okay"; -+}; -+ -+&pcie3x1 { -+ num-lanes = <1>; -+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie>; -+ status = "okay"; -+}; -+ -+&pcie3x2 { -+ num-lanes = <1>; -+ num-ib-windows = <8>; -+ num-ob-windows = <8>; -+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gmac0 { -+ eth_phy0_reset_pin: eth-phy0-reset-pin { -+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ gpio-leds { -+ lan1_led_pin: lan1-led-pin { -+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ lan2_led_pin: lan2-led-pin { -+ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ power_led_pin: power-led-pin { -+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int: pmic-int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb_host_en: vcc5v0-usb-host-en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_1v8>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ max-frequency = <150000000>; -+ no-sdio; -+ no-mmc; -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ extcon = <&usb2phy0>; -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ status = "okay"; -+}; -+ -+&usb2phy1 { -+ status = "okay"; -+}; -+ -+&usb2phy1_host { -+ phy-supply = <&vcc5v0_usb_otg>; -+ status = "okay"; -+}; -+ -+&usb2phy1_otg { -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = <ROCKCHIP_VOP2_EP_HDMI0>; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch b/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch deleted file mode 100644 index cf9fe06ad0..0000000000 --- a/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch +++ /dev/null @@ -1,1226 +0,0 @@ -From c8ec73b05a95d9f0969ae0f28dd8799a54fcdfc7 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Sat, 18 Mar 2023 16:37:41 +0800 -Subject: [PATCH] arm64: dts: rockchip: create common dtsi for NanoPi R5 series - -Create common dtsi for the FriendlyElec NanoPi R5 series. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20230318083745.6181-2-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 575 +---------------- - .../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 596 ++++++++++++++++++ - 2 files changed, 597 insertions(+), 574 deletions(-) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -@@ -7,12 +7,7 @@ - */ - - /dts-v1/; --#include <dt-bindings/gpio/gpio.h> --#include <dt-bindings/input/input.h> --#include <dt-bindings/leds/common.h> --#include <dt-bindings/pinctrl/rockchip.h> --#include <dt-bindings/soc/rockchip,vop2.h> --#include "rk3568.dtsi" -+#include "rk3568-nanopi-r5s.dtsi" - - / { - model = "FriendlyElec NanoPi R5S"; -@@ -20,23 +15,6 @@ - - aliases { - ethernet0 = &gmac0; -- mmc0 = &sdmmc0; -- mmc1 = &sdhci; -- }; -- -- chosen: chosen { -- stdout-path = "serial2:1500000n8"; -- }; -- -- hdmi-con { -- compatible = "hdmi-connector"; -- type = "a"; -- -- port { -- hdmi_con_in: endpoint { -- remote-endpoint = <&hdmi_out_con>; -- }; -- }; - }; - - gpio-leds { -@@ -71,130 +49,6 @@ - gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - }; - }; -- -- vdd_usbc: vdd-usbc-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vdd_usbc"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- }; -- -- vcc3v3_sys: vcc3v3-sys-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc3v3_sys"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vdd_usbc>; -- }; -- -- vcc5v0_sys: vcc5v0-sys-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_sys"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vdd_usbc>; -- }; -- -- vcc3v3_pcie: vcc3v3-pcie-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc3v3_pcie"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- enable-active-high; -- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -- startup-delay-us = <200000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc5v0_usb: vcc5v0-usb-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_usb"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vdd_usbc>; -- }; -- -- vcc5v0_usb_host: vcc5v0-usb-host-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&vcc5v0_usb_host_en>; -- regulator-name = "vcc5v0_usb_host"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc5v0_usb>; -- }; -- -- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&vcc5v0_usb_otg_en>; -- regulator-name = "vcc5v0_usb_otg"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc5v0_usb>; -- }; -- -- pcie30_avdd0v9: pcie30-avdd0v9-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "pcie30_avdd0v9"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <900000>; -- vin-supply = <&vcc3v3_sys>; -- }; -- -- pcie30_avdd1v8: pcie30-avdd1v8-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "pcie30_avdd1v8"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- vin-supply = <&vcc3v3_sys>; -- }; --}; -- --&combphy0 { -- status = "okay"; --}; -- --&combphy1 { -- status = "okay"; --}; -- --&combphy2 { -- status = "okay"; --}; -- --&cpu0 { -- cpu-supply = <&vdd_cpu>; --}; -- --&cpu1 { -- cpu-supply = <&vdd_cpu>; --}; -- --&cpu2 { -- cpu-supply = <&vdd_cpu>; --}; -- --&cpu3 { -- cpu-supply = <&vdd_cpu>; - }; - - &gmac0 { -@@ -219,292 +73,6 @@ - status = "okay"; - }; - --&gpu { -- mali-supply = <&vdd_gpu>; -- status = "okay"; --}; -- --&hdmi { -- avdd-0v9-supply = <&vdda0v9_image>; -- avdd-1v8-supply = <&vcca1v8_image>; -- status = "okay"; --}; -- --&hdmi_in { -- hdmi_in_vp0: endpoint { -- remote-endpoint = <&vp0_out_hdmi>; -- }; --}; -- --&hdmi_out { -- hdmi_out_con: endpoint { -- remote-endpoint = <&hdmi_con_in>; -- }; --}; -- --&hdmi_sound { -- status = "okay"; --}; -- --&i2c0 { -- status = "okay"; -- -- vdd_cpu: regulator@1c { -- compatible = "tcs,tcs4525"; -- reg = <0x1c>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <800000>; -- regulator-max-microvolt = <1150000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc5v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- rk809: pmic@20 { -- compatible = "rockchip,rk809"; -- reg = <0x20>; -- interrupt-parent = <&gpio0>; -- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; -- #clock-cells = <1>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_int>; -- rockchip,system-power-controller; -- vcc1-supply = <&vcc3v3_sys>; -- vcc2-supply = <&vcc3v3_sys>; -- vcc3-supply = <&vcc3v3_sys>; -- vcc4-supply = <&vcc3v3_sys>; -- vcc5-supply = <&vcc3v3_sys>; -- vcc6-supply = <&vcc3v3_sys>; -- vcc7-supply = <&vcc3v3_sys>; -- vcc8-supply = <&vcc3v3_sys>; -- vcc9-supply = <&vcc3v3_sys>; -- wakeup-source; -- -- regulators { -- vdd_logic: DCDC_REG1 { -- regulator-name = "vdd_logic"; -- regulator-always-on; -- regulator-boot-on; -- regulator-init-microvolt = <900000>; -- regulator-initial-mode = <0x2>; -- regulator-min-microvolt = <500000>; -- regulator-max-microvolt = <1350000>; -- regulator-ramp-delay = <6001>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_gpu: DCDC_REG2 { -- regulator-name = "vdd_gpu"; -- regulator-always-on; -- regulator-init-microvolt = <900000>; -- regulator-initial-mode = <0x2>; -- regulator-min-microvolt = <500000>; -- regulator-max-microvolt = <1350000>; -- regulator-ramp-delay = <6001>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_ddr: DCDC_REG3 { -- regulator-name = "vcc_ddr"; -- regulator-always-on; -- regulator-boot-on; -- regulator-initial-mode = <0x2>; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- }; -- }; -- -- vdd_npu: DCDC_REG4 { -- regulator-name = "vdd_npu"; -- regulator-init-microvolt = <900000>; -- regulator-initial-mode = <0x2>; -- regulator-min-microvolt = <500000>; -- regulator-max-microvolt = <1350000>; -- regulator-ramp-delay = <6001>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8: DCDC_REG5 { -- regulator-name = "vcc_1v8"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdda0v9_image: LDO_REG1 { -- regulator-name = "vdda0v9_image"; -- regulator-min-microvolt = <950000>; -- regulator-max-microvolt = <950000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdda_0v9: LDO_REG2 { -- regulator-name = "vdda_0v9"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <900000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdda0v9_pmu: LDO_REG3 { -- regulator-name = "vdda0v9_pmu"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <900000>; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <900000>; -- }; -- }; -- -- vccio_acodec: LDO_REG4 { -- regulator-name = "vccio_acodec"; -- regulator-always-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vccio_sd: LDO_REG5 { -- regulator-name = "vccio_sd"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <3300000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc3v3_pmu: LDO_REG6 { -- regulator-name = "vcc3v3_pmu"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <3300000>; -- }; -- }; -- -- vcca_1v8: LDO_REG7 { -- regulator-name = "vcca_1v8"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcca1v8_pmu: LDO_REG8 { -- regulator-name = "vcca1v8_pmu"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- vcca1v8_image: LDO_REG9 { -- regulator-name = "vcca1v8_image"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_3v3: SWITCH_REG1 { -- regulator-name = "vcc_3v3"; -- regulator-always-on; -- regulator-boot-on; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc3v3_sd: SWITCH_REG2 { -- regulator-name = "vcc3v3_sd"; -- regulator-always-on; -- regulator-boot-on; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- }; -- -- }; --}; -- --&i2c5 { -- status = "okay"; -- -- hym8563: rtc@51 { -- compatible = "haoyu,hym8563"; -- reg = <0x51>; -- interrupt-parent = <&gpio0>; -- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; -- #clock-cells = <0>; -- clock-output-names = "rtcic_32kout"; -- pinctrl-names = "default"; -- pinctrl-0 = <&hym8563_int>; -- wakeup-source; -- }; --}; -- --&i2s0_8ch { -- status = "okay"; --}; -- --&i2s1_8ch { -- rockchip,trcm-sync-tx-only; -- status = "okay"; --}; -- - &mdio0 { - rgmii_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; -@@ -568,146 +136,5 @@ - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -- -- hym8563 { -- hym8563_int: hym8563-int { -- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -- }; -- }; -- -- pmic { -- pmic_int: pmic-int { -- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -- }; -- }; -- -- usb { -- vcc5v0_usb_host_en: vcc5v0-usb-host-en { -- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { -- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; --}; -- --&pmu_io_domains { -- pmuio1-supply = <&vcc3v3_pmu>; -- pmuio2-supply = <&vcc3v3_pmu>; -- vccio1-supply = <&vccio_acodec>; -- vccio3-supply = <&vccio_sd>; -- vccio4-supply = <&vcc_1v8>; -- vccio5-supply = <&vcc_3v3>; -- vccio6-supply = <&vcc_1v8>; -- vccio7-supply = <&vcc_3v3>; -- status = "okay"; --}; -- --&saradc { -- vref-supply = <&vcca_1v8>; -- status = "okay"; --}; -- --&sdhci { -- bus-width = <8>; -- max-frequency = <200000000>; -- non-removable; -- pinctrl-names = "default"; -- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; -- status = "okay"; --}; -- --&sdmmc0 { -- max-frequency = <150000000>; -- no-sdio; -- no-mmc; -- bus-width = <4>; -- cap-mmc-highspeed; -- cap-sd-highspeed; -- disable-wp; -- vmmc-supply = <&vcc3v3_sd>; -- vqmmc-supply = <&vccio_sd>; -- pinctrl-names = "default"; -- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -- status = "okay"; --}; -- --&tsadc { -- rockchip,hw-tshut-mode = <1>; -- rockchip,hw-tshut-polarity = <0>; -- status = "okay"; --}; -- --&uart2 { -- status = "okay"; --}; -- --&usb_host0_ehci { -- status = "okay"; --}; -- --&usb_host0_ohci { -- status = "okay"; --}; -- --&usb_host0_xhci { -- extcon = <&usb2phy0>; -- dr_mode = "host"; -- status = "okay"; --}; -- --&usb_host1_ehci { -- status = "okay"; --}; -- --&usb_host1_ohci { -- status = "okay"; - }; - --&usb_host1_xhci { -- status = "okay"; --}; -- --&usb2phy0 { -- status = "okay"; --}; -- --&usb2phy0_host { -- phy-supply = <&vcc5v0_usb_host>; -- status = "okay"; --}; -- --&usb2phy0_otg { -- status = "okay"; --}; -- --&usb2phy1 { -- status = "okay"; --}; -- --&usb2phy1_host { -- phy-supply = <&vcc5v0_usb_otg>; -- status = "okay"; --}; -- --&usb2phy1_otg { -- status = "okay"; --}; -- --&vop { -- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -- status = "okay"; --}; -- --&vop_mmu { -- status = "okay"; --}; -- --&vp0 { -- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -- reg = <ROCKCHIP_VOP2_EP_HDMI0>; -- remote-endpoint = <&hdmi_in_vp0>; -- }; --}; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -@@ -0,0 +1,596 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyelec.com) -+ * -+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> -+ */ -+ -+/dts-v1/; -+#include <dt-bindings/gpio/gpio.h> -+#include <dt-bindings/input/input.h> -+#include <dt-bindings/leds/common.h> -+#include <dt-bindings/pinctrl/rockchip.h> -+#include <dt-bindings/soc/rockchip,vop2.h> -+#include "rk3568.dtsi" -+ -+/ { -+ aliases { -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ vdd_usbc: vdd-usbc-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_usbc"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vdd_usbc>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vdd_usbc>; -+ }; -+ -+ vcc3v3_pcie: vcc3v3-pcie-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <200000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_usb: vcc5v0-usb-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vdd_usbc>; -+ }; -+ -+ vcc5v0_usb_host: vcc5v0-usb-host-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_host_en>; -+ regulator-name = "vcc5v0_usb_host"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en>; -+ regulator-name = "vcc5v0_usb_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ pcie30_avdd0v9: pcie30-avdd0v9-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ pcie30_avdd1v8: pcie30-avdd1v8-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+}; -+ -+&combphy0 { -+ status = "okay"; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&combphy2 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ rockchip,system-power-controller; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <950000>; -+ regulator-max-microvolt = <950000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ -+ }; -+}; -+ -+&i2c5 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <0>; -+ clock-output-names = "rtcic_32kout"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ wakeup-source; -+ }; -+}; -+ -+&i2s0_8ch { -+ status = "okay"; -+}; -+ -+&i2s1_8ch { -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ data-lanes = <1 2>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int: pmic-int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb_host_en: vcc5v0-usb-host-en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_1v8>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ max-frequency = <150000000>; -+ no-sdio; -+ no-mmc; -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ extcon = <&usb2phy0>; -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ status = "okay"; -+}; -+ -+&usb2phy1 { -+ status = "okay"; -+}; -+ -+&usb2phy1_host { -+ phy-supply = <&vcc5v0_usb_otg>; -+ status = "okay"; -+}; -+ -+&usb2phy1_otg { -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = <ROCKCHIP_VOP2_EP_HDMI0>; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch b/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch deleted file mode 100644 index 47f76d54e7..0000000000 --- a/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Sat, 18 Mar 2023 16:37:44 +0800 -Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S - -- Changed phy-mode to rgmii. - -- Fixed pull type in pinctrl for gmac0. - -- Removed duplicate properties in mdio node. - These properties are defined in the gmac0 node already. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -@@ -57,7 +57,7 @@ - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy0>; -- phy-mode = "rgmii-id"; -+ phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 -@@ -79,9 +79,6 @@ - reg = <1>; - pinctrl-0 = <ð_phy0_reset_pin>; - pinctrl-names = "default"; -- reset-assert-us = <10000>; -- reset-deassert-us = <50000>; -- reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; - }; - }; - -@@ -115,7 +112,7 @@ - &pinctrl { - gmac0 { - eth_phy0_reset_pin: eth-phy0-reset-pin { -- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; -+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - diff --git a/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch b/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch deleted file mode 100644 index 48021b226a..0000000000 --- a/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Sat, 18 Mar 2023 16:37:45 +0800 -Subject: [PATCH] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5 - series - -This is for the audio output which does not exist on the boards. -Also disable regulator-always-on for vccio_acodec since it's only -used by the audio output. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -@@ -330,7 +330,6 @@ - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; -- regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - -@@ -441,11 +440,6 @@ - status = "okay"; - }; - --&i2s1_8ch { -- rockchip,trcm-sync-tx-only; -- status = "okay"; --}; -- - &pcie30phy { - data-lanes = <1 2>; - status = "okay"; diff --git a/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch b/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch deleted file mode 100644 index 0465d80cba..0000000000 --- a/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Sat, 18 Mar 2023 16:37:43 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C - -FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. - -Specification: -- Rockchip RK3568 -- 1/4GB LPDDR4X RAM -- 8/32GB eMMC -- SD card slot -- M.2 Connector -- 2x USB 3.0 Port -- 2x 2500 Base-T (PCIe, r8125) -- HDMI 2.0 -- MIPI DSI/CSI -- USB Type C 5V - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++ - 2 files changed, 113 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -74,5 +74,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -@@ -0,0 +1,112 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyelec.com) -+ * -+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> -+ */ -+ -+/dts-v1/; -+#include "rk3568-nanopi-r5s.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R5C"; -+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&reset_button_pin>; -+ -+ button-reset { -+ debounce-interval = <50>; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; -+ label = "reset"; -+ linux,code = <KEY_RESTART>; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; -+ -+ led-lan { -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_LAN; -+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ power_led: led-power { -+ color = <LED_COLOR_ID_RED>; -+ function = LED_FUNCTION_POWER; -+ linux,default-trigger = "heartbeat"; -+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-wan { -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_WAN; -+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-wlan { -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_WLAN; -+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; -+ -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie20_reset_pin>; -+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&pcie3x1 { -+ num-lanes = <1>; -+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie>; -+ status = "okay"; -+}; -+ -+&pcie3x2 { -+ num-lanes = <1>; -+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ power_led_pin: power-led-pin { -+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wlan_led_pin: wlan-led-pin { -+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie20_reset_pin: pcie20-reset-pin { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch b/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch deleted file mode 100644 index 0e59f0275b..0000000000 --- a/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 5325593377f07de31f7e473a9677a28a04c891f3 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Thu, 11 May 2023 00:18:50 +0800 -Subject: [PATCH] arm64: dts: rockchip: fix button reset pin for nanopi r5c - -The reset pin was wrongly assigned due to a copy/paste error, -fix it to match actual gpio pin. - -While at it, remove a blank line from nanopi r5s dts. - -Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C") -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 - - 2 files changed, 1 insertion(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -@@ -106,7 +106,7 @@ - - rockchip-key { - reset_button_pin: reset-button-pin { -- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - }; ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -@@ -134,4 +134,3 @@ - }; - }; - }; -- diff --git a/target/linux/rockchip/patches-6.1/015-v6.8-arm64-dts-rockchip-configure-eth-pad-driver-strength-for-.patch b/target/linux/rockchip/patches-6.1/015-v6.8-arm64-dts-rockchip-configure-eth-pad-driver-strength-for-.patch deleted file mode 100644 index 01efaa3a9d..0000000000 --- a/target/linux/rockchip/patches-6.1/015-v6.8-arm64-dts-rockchip-configure-eth-pad-driver-strength-for-.patch +++ /dev/null @@ -1,33 +0,0 @@ -From fc5a80a432607d05e85bba37971712405f75c546 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Sat, 16 Dec 2023 12:07:23 +0800 -Subject: [PATCH] arm64: dts: rockchip: configure eth pad driver strength - for orangepi r1 plus lts - -The default strength is not enough to provide stable connection -under 3.3v LDO voltage. - -Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS") -Cc: stable@vger.kernel.org # 6.6+ -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts -@@ -26,9 +26,11 @@ - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - -+ motorcomm,auto-sleep-disabled; - motorcomm,clk-out-frequency-hz = <125000000>; - motorcomm,keep-pll-enabled; -- motorcomm,auto-sleep-disabled; -+ motorcomm,rx-clk-drv-microamp = <5020>; -+ motorcomm,rx-data-drv-microamp = <5020>; - - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; diff --git a/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch b/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch deleted file mode 100644 index b4a68d1558..0000000000 --- a/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch +++ /dev/null @@ -1,233 +0,0 @@ -From 096ebfb74b19f2d4bdcbc33ae02e857ff4b3e0a0 Mon Sep 17 00:00:00 2001 -From: Jagan Teki <jagan@amarulasolutions.com> -Date: Thu, 12 Jan 2023 16:29:02 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Radxa Compute Module 3 IO board - -Radxa Compute Module 3(CM3) IO board is an application board from Radxa -and is compatible with Raspberry Pi CM4 IO form factor. - -Specification: -- 1x HDMI, -- 2x MIPI DSI -- 2x MIPI CSI2 -- 1x eDP -- 1x PCIe card -- 2x SATA -- 2x USB 2.0 Host -- 1x USB 3.0 -- 1x USB 2.0 OTG -- Phone jack -- microSD slot -- 40-pin GPIO expansion header -- 12V DC - -Radxa CM3 needs to mount on top of this IO board in order to create -complete Radxa CM3 IO board platform. - -Add support for Radxa CM3 IO Board. - -Co-developed-by: FUKAUMI Naoki <naoki@radxa.com> -Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> -Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> -Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> -Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> -Link: https://lore.kernel.org/r/20230112105902.192852-3-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 179 ++++++++++++++++++ - 2 files changed, 180 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -0,0 +1,179 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2022 Radxa Limited -+ * Copyright (c) 2022 Amarula Solutions(India) -+ */ -+ -+/dts-v1/; -+#include <dt-bindings/soc/rockchip,vop2.h> -+#include "rk3566.dtsi" -+#include "rk3566-radxa-cm3.dtsi" -+ -+/ { -+ model = "Radxa Compute Module 3(CM3) IO Board"; -+ compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566"; -+ -+ aliases { -+ mmc1 = &sdmmc0; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-1 { -+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>; -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_ACTIVITY; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pi_nled_activity>; -+ }; -+ }; -+ -+ vcc5v0_usb30: vcc5v0-usb30-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb30"; -+ enable-active-high; -+ gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb30_en_h>; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcca1v8_image: vcca1v8-image-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca1v8_image"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_1v8_p>; -+ }; -+ -+ vdda0v9_image: vdda0v9-image-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca0v9_image"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vdda_0v9>; -+ }; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&pinctrl { -+ leds { -+ pi_nled_activity: pi-nled-activity { -+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdcard { -+ sdmmc_pwren: sdmmc-pwren { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb30_en_h: vcc5v0-host-en-h { -+ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ vqmmc-supply = <&vccio_sd>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb30>; -+ status = "okay"; -+}; -+ -+&usb2phy1_host { -+ status = "okay"; -+}; -+ -+&usb2phy1_otg { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = <ROCKCHIP_VOP2_EP_HDMI0>; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch b/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch deleted file mode 100644 index d0a0aa1b69..0000000000 --- a/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch +++ /dev/null @@ -1,63 +0,0 @@ -From d211665c5a833873ee37e501af58adbf028e6b5f Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Sat, 13 May 2023 21:53:07 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus - -The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board -eMMC flash (8G) included. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> -Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 33 ++++++++++++++++++++++ - 2 files changed, 34 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts -@@ -0,0 +1,33 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> -+ */ -+ -+/dts-v1/; -+#include "rk3328-nanopi-r2c.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R2C Plus"; -+ compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; -+ -+ aliases { -+ mmc1 = &emmc; -+ }; -+}; -+ -+&emmc { -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ max-frequency = <150000000>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -+ vmmc-supply = <&vcc_io_33>; -+ vqmmc-supply = <&vcc18_emmc>; -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch b/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch deleted file mode 100644 index 305b5702d5..0000000000 --- a/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch +++ /dev/null @@ -1,131 +0,0 @@ -From cc52bfc04726a574fc4440bbbe0c710890e7040a Mon Sep 17 00:00:00 2001 -From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> -Date: Wed, 25 Jan 2023 21:40:22 +0530 -Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO - -Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board. - -Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> -Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++ - 1 file changed, 93 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -21,6 +21,13 @@ - stdout-path = "serial2:1500000n8"; - }; - -+ gmac1_clkin: external-gmac1-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac1_clkin"; -+ #clock-cells = <0>; -+ }; -+ - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; -@@ -83,6 +90,29 @@ - status = "okay"; - }; - -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; -+ assigned-clock-rates = <0>, <125000000>; -+ clock_in_out = "input"; -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m0_miim -+ &gmac1m0_tx_bus2 -+ &gmac1m0_rx_bus2 -+ &gmac1m0_rgmii_clk -+ &gmac1m0_rgmii_bus -+ &gmac1m0_clkinout>; -+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ /* Reset time is 20ms, 100ms for rtl8211f */ -+ snps,reset-delays-us = <0 20000 100000>; -+ tx_delay = <0x46>; -+ rx_delay = <0x2e>; -+ status = "okay"; -+}; -+ - &hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; -@@ -105,7 +135,70 @@ - status = "okay"; - }; - -+&mdio1 { -+ rgmii_phy1: ethernet-phy@0 { -+ compatible="ethernet-phy-ieee802.3-c22"; -+ reg= <0x0>; -+ }; -+}; -+ - &pinctrl { -+ gmac1 { -+ gmac1m0_miim: gmac1m0-miim { -+ rockchip,pins = -+ /* gmac1_mdcm0 */ -+ <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_mdiom0 */ -+ <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>; -+ }; -+ -+ gmac1m0_rx_bus2: gmac1m0-rx-bus2 { -+ rockchip,pins = -+ /* gmac1_rxd0m0 */ -+ <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_rxd1m0 */ -+ <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_rxdvcrsm0 */ -+ <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>; -+ }; -+ -+ gmac1m0_tx_bus2: gmac1m0-tx-bus2 { -+ rockchip,pins = -+ /* gmac1_txd0m0 */ -+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_txd1m0 */ -+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_txenm0 */ -+ <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>; -+ }; -+ -+ gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { -+ rockchip,pins = -+ /* gmac1_rxclkm0 */ -+ <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_txclkm0 */ -+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>; -+ }; -+ -+ gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { -+ rockchip,pins = -+ /* gmac1_rxd2m0 */ -+ <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_rxd3m0 */ -+ <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_txd2m0 */ -+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>, -+ /* gmac1_txd3m0 */ -+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>; -+ }; -+ -+ gmac1m0_clkinout: gmac1m0-clkinout { -+ rockchip,pins = -+ /* gmac1_mclkinoutm0 */ -+ <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>; -+ }; -+ }; -+ - leds { - pi_nled_activity: pi-nled-activity { - rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch b/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch deleted file mode 100644 index e53f7fa7e0..0000000000 --- a/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch +++ /dev/null @@ -1,386 +0,0 @@ -From 7469ab529bcad50490f6ff651c3e4f03bfa88fe0 Mon Sep 17 00:00:00 2001 -From: Jagan Teki <jagan@amarulasolutions.com> -Date: Thu, 12 Jan 2023 16:29:01 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Radxa Compute Module 3(CM3) is one of the modules from a series -System On Module based on the Radxa ROCK 3 series and is compatible -with Raspberry Pi CM4 pinout and form factor. - -Specification: -- Rockchip RK3566 -- up to 8GB LPDDR4 -- up to 128GB high performance eMMC -- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless, - BT 5.0, BLE with onboard and external antenna. -- Gigabit Ethernet PHY - -Radxa CM3 needs to mount on top of this IO board in order to create -complete Radxa CM3 IO board platform. - -Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is -possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board. - -Add support for Radxa CM3. - -Co-developed-by: FUKAUMI Naoki <naoki@radxa.com> -Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> -Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> -Link: https://lore.kernel.org/r/20230112105902.192852-2-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 345 ++++++++++++++++++ - 1 file changed, 345 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -@@ -0,0 +1,345 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2022 Radxa Limited -+ * Copyright (c) 2022 Amarula Solutions(India) -+ */ -+ -+#include <dt-bindings/gpio/gpio.h> -+#include <dt-bindings/leds/common.h> -+ -+/ { -+ compatible = "radxa,radxa-cm3", "rockchip,rk3566"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-0 { -+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_STATUS; -+ linux,default-trigger = "timer"; -+ default-state = "on"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&user_led2>; -+ }; -+ }; -+ -+ vcc_sys: vcc-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc_1v8: vcc-1v8-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_1v8_p>; -+ }; -+ -+ vcc_3v3: vcc-3v3-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vcca_1v8: vcca-1v8-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_1v8_p>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu_npu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1390000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk817: pmic@20 { -+ compatible = "rockchip,rk817"; -+ reg = <0x20>; -+ #clock-cells = <1>; -+ clock-output-names = "rk817-clkout1", "rk817-clkout2"; -+ interrupt-parent = <&gpio0>; -+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_sys>; -+ vcc6-supply = <&vcc_sys>; -+ vcc7-supply = <&vcc_sys>; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vdd_gpu_npu: DCDC_REG2 { -+ regulator-name = "vdd_gpu_npu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sys: DCDC_REG4 { -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG1 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_1v8_p: LDO_REG7 { -+ regulator-name = "vcc_1v8_p"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG8 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc2v8_dvp: LDO_REG9 { -+ regulator-name = "vcc2v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ leds { -+ user_led2: user-led2 { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc_3v3>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_3v3>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ mmc-hs200-1_8v; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch deleted file mode 100644 index 9855b9e1a6..0000000000 --- a/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch +++ /dev/null @@ -1,134 +0,0 @@ -From af5a803bf212e077e5fb7a1d4cf6be02f74a74ca Mon Sep 17 00:00:00 2001 -From: Jagan Teki <jagan@amarulasolutions.com> -Date: Wed, 25 Jan 2023 21:40:23 +0530 -Subject: [PATCH] arm64: dts: rockchip: rk3566: Enable WiFi, BT support for - Radxa CM3 - -Radxa Compute Module 3 has an onboard AW_CM256SM WiFi/BT module. - -Add nodes for enabling it. - -Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> -Link: https://lore.kernel.org/r/20230125161023.12115-2-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 80 +++++++++++++++++++ - 1 file changed, 80 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -@@ -66,6 +66,15 @@ - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8_p>; - }; -+ -+ sdio_pwrseq: pwrseq-sdio { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk817 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on_h>; -+ reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; -+ }; - }; - - &cpu0 { -@@ -287,6 +296,20 @@ - }; - - &pinctrl { -+ bluetooth { -+ bt_host_wake_h: bt-host-wake-h { -+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_reg_on_h: bt-reg-on-h { -+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_host_h: bt-wake-host-h { -+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -@@ -298,6 +321,16 @@ - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -+ -+ wifi { -+ wifi_reg_on_h: wifi-reg-on-h { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_host_wake_h: wifi-host-wake-h { -+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - - &pmu_io_domains { -@@ -318,6 +351,34 @@ - status = "okay"; - }; - -+&sdmmc1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ bus-width = <4>; -+ disable-wp; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+ -+ wifi@1 { -+ compatible = "brcm,bcm43455-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "host-wake"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_host_wake_h>; -+ }; -+}; -+ - &sdhci { - bus-width = <8>; - max-frequency = <200000000>; -@@ -330,6 +391,25 @@ - status = "okay"; - }; - -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rk817 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>; -+ vbat-supply = <&vcc_3v3>; -+ vddio-supply = <&vcc_1v8>; -+ }; -+}; -+ - &usb2phy0 { - status = "okay"; - }; diff --git a/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch deleted file mode 100644 index bfd6dbe0db..0000000000 --- a/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 477ed3ade6a46e445b4e2348b710c51df4f6f4b1 Mon Sep 17 00:00:00 2001 -From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> -Date: Thu, 23 Feb 2023 19:29:29 +0530 -Subject: [PATCH] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa CM3 - -Enable USB OTG support for Radxa Compute Module 3 IO Board - -Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> -Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> -Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -254,6 +254,14 @@ - status = "okay"; - }; - -+&usb2phy0_otg { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ status = "okay"; -+}; -+ - &vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; diff --git a/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch deleted file mode 100644 index e7e3ea0100..0000000000 --- a/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 8f19828844f20b22182719cf53be64f8c955aee8 Mon Sep 17 00:00:00 2001 -From: Jagan Teki <jagan@amarulasolutions.com> -Date: Mon, 23 Jan 2023 12:46:50 +0530 -Subject: [PATCH] arm64: dts: rockchip: Fix compatible for Radxa CM3 - -The compatible string "radxa,radxa-cm3" referring the product name -as "Radxa Radxa CM3" but the actual product name is "Radxa CM3". - -Fix the compatible strings. - -Fixes: 24a28d3eb07d ("dt-bindings: arm: rockchip: Add Radxa Compute Module 3") -Fixes: 7469ab529bca ("arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3") -Fixes: 096ebfb74b19 ("arm64: dts: rockchip: Add Radxa Compute Module 3 IO board") -Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> -Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> -Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> -Link: https://lore.kernel.org/r/20230123071654.73139-1-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -11,7 +11,7 @@ - - / { - model = "Radxa Compute Module 3(CM3) IO Board"; -- compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566"; -+ compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; - - aliases { - mmc1 = &sdmmc0; ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -@@ -8,7 +8,7 @@ - #include <dt-bindings/leds/common.h> - - / { -- compatible = "radxa,radxa-cm3", "rockchip,rk3566"; -+ compatible = "radxa,cm3", "rockchip,rk3566"; - - aliases { - mmc0 = &sdhci; diff --git a/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch b/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch deleted file mode 100644 index 8342c14ea4..0000000000 --- a/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch +++ /dev/null @@ -1,28 +0,0 @@ -From f99a75f11f46a24dabb33e90893eebf61dca0566 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> -Date: Sun, 2 Jul 2023 20:52:42 +0200 -Subject: [PATCH] arm64: dts: rockchip: minor whitespace cleanup around '=' - -The DTS code coding style expects exactly one space before and after '=' -sign. - -Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> -Link: https://lore.kernel.org/r/20230702185242.44421-1-krzysztof.kozlowski@linaro.org -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -137,8 +137,8 @@ - - &mdio1 { - rgmii_phy1: ethernet-phy@0 { -- compatible="ethernet-phy-ieee802.3-c22"; -- reg= <0x0>; -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0x0>; - }; - }; - diff --git a/target/linux/rockchip/patches-6.1/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch b/target/linux/rockchip/patches-6.1/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch deleted file mode 100644 index fb5015cf6e..0000000000 --- a/target/linux/rockchip/patches-6.1/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001 -From: Dragan Simic <dsimic@manjaro.org> -Date: Tue, 12 Dec 2023 09:01:39 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for - RK3566 boards - -Add ethernet0 alias to the board dts files for a few supported RK3566 boards -that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM -dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to -the dependent board dts files, which actually enable the GMAC. - -Signed-off-by: Dragan Simic <dsimic@manjaro.org> -Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 + - 1 files changed, 1 insertions(+), 0 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -14,6 +14,7 @@ - compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; - - aliases { -+ ethernet0 = &gmac1; - mmc1 = &sdmmc0; - }; - diff --git a/target/linux/rockchip/patches-6.1/024-v6.3-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch b/target/linux/rockchip/patches-6.1/024-v6.3-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch deleted file mode 100644 index 354c546d7e..0000000000 --- a/target/linux/rockchip/patches-6.1/024-v6.3-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch +++ /dev/null @@ -1,689 +0,0 @@ -From 2bf2f4d9f673013a58109626b87329310537a611 Mon Sep 17 00:00:00 2001 -From: Chukun Pan <amadeus@jmu.edu.cn> -Date: Fri, 9 Dec 2022 18:25:24 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add Radxa CM3I E25 - -Radxa E25 is a network application carrier board for the Radxa CM3 -Industrial (CM3I) SoM, which is based on the Rockchip RK3568 SoC. - -It has the following features: - -- MicroSD card socket, on board eMMC flash -- 2x 2.5GbE Realtek RTL8125B Ethernet transceiver -- 1x USB Type-C port (Power and Serial console) -- 1x USB 3.0 OTG port -- mini PCIe socket (USB or PCIe) -- ngff PCIe socket (USB or SATA) -- 1x User LED and 16x RGB LEDs -- 26-pin expansion header - -Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> -Link: https://lore.kernel.org/r/20221209102524.129367-3-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 416 ++++++++++++++++++ - .../boot/dts/rockchip/rk3568-radxa-e25.dts | 229 ++++++++++ - 3 files changed, 646 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi - create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -78,4 +78,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bp - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi -@@ -0,0 +1,416 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include <dt-bindings/gpio/gpio.h> -+#include <dt-bindings/leds/common.h> -+#include <dt-bindings/pinctrl/rockchip.h> -+#include "rk3568.dtsi" -+ -+/ { -+ model = "Radxa CM3 Industrial Board"; -+ compatible = "radxa,cm3i", "rockchip,rk3568"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ -+ led_user: led-0 { -+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ function = LED_FUNCTION_HEARTBEAT; -+ color = <LED_COLOR_ID_GREEN>; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_user_en>; -+ }; -+ }; -+ -+ pcie30_avdd0v9: pcie30-avdd0v9-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ pcie30_avdd1v8: pcie30-avdd1v8-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v_input>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v_input>; -+ }; -+ -+ /* labeled +5v_input in schematic */ -+ vcc5v_input: vcc5v-input-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v_input"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&combphy0 { -+ status = "okay"; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&combphy2 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&display_subsystem { -+ status = "disabled"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v_input>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ leds { -+ led_user_en: led_user_en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_1v8>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy1 { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ extcon = <&usb2phy0>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -0,0 +1,229 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3568-radxa-cm3i.dtsi" -+ -+/ { -+ model = "Radxa E25"; -+ compatible = "radxa,e25", "rockchip,rk3568"; -+ -+ aliases { -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+ -+ pwm-leds { -+ compatible = "pwm-leds-multicolor"; -+ -+ multi-led { -+ color = <LED_COLOR_ID_RGB>; -+ max-brightness = <255>; -+ -+ led-red { -+ color = <LED_COLOR_ID_RED>; -+ pwms = <&pwm1 0 1000000 0>; -+ }; -+ -+ led-green { -+ color = <LED_COLOR_ID_GREEN>; -+ pwms = <&pwm2 0 1000000 0>; -+ }; -+ -+ led-blue { -+ color = <LED_COLOR_ID_BLUE>; -+ pwms = <&pwm12 0 1000000 0>; -+ }; -+ }; -+ }; -+ -+ vbus_typec: vbus-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vbus_typec_en>; -+ regulator-name = "vbus_typec"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_minipcie: vcc3v3-minipcie-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&minipcie_enable_h>; -+ regulator-name = "vcc3v3_minipcie"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_ngff: vcc3v3-ngff-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ngffpcie_enable_h>; -+ regulator-name = "vcc3v3_ngff"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ /* actually fed by vcc5v0_sys, dependent -+ * on pi6c clock generator -+ */ -+ vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie30x1_enable_h>; -+ regulator-name = "vcc3v3_pcie30x1"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_pi6c_05>; -+ }; -+ -+ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_enable_h>; -+ regulator-name = "vcc3v3_pcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie20_reset_h>; -+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pi6c_05>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ data-lanes = <1 2>; -+ status = "okay"; -+}; -+ -+&pcie3x1 { -+ num-lanes = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie30x1m0_pins>; -+ reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30x1>; -+ status = "okay"; -+}; -+ -+&pcie3x2 { -+ num-lanes = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie30x2_reset_h>; -+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pi6c_05>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ pcie { -+ pcie20_reset_h: pcie20-reset-h { -+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie30x1_enable_h: pcie30x1-enable-h { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie30x2_reset_h: pcie30x2-reset-h { -+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_enable_h: pcie-enable-h { -+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ minipcie_enable_h: minipcie-enable-h { -+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ ngffpcie_enable_h: ngffpcie-enable-h { -+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vbus_typec_en: vbus_typec_en { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&pwm12 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm12m1_pins>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ /* Also used in pcie30x1_clkreqnm0 */ -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ phy-supply = <&vbus_typec>; -+ status = "okay"; -+}; -+ -+&usb2phy1_host { -+ phy-supply = <&vcc3v3_minipcie>; -+ status = "okay"; -+}; -+ -+&usb2phy1_otg { -+ phy-supply = <&vcc3v3_ngff>; -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-6.1/025-v6.3-arm64-dts-rockchip-Update-eMMC-SD.patch b/target/linux/rockchip/patches-6.1/025-v6.3-arm64-dts-rockchip-Update-eMMC-SD.patch deleted file mode 100644 index e556e2eb42..0000000000 --- a/target/linux/rockchip/patches-6.1/025-v6.3-arm64-dts-rockchip-Update-eMMC-SD.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c80992abd2877590059e9cb254213c16824e2106 Mon Sep 17 00:00:00 2001 -From: Jagan Teki <jagan@amarulasolutions.com> -Date: Wed, 18 Jan 2023 13:34:53 +0530 -Subject: [PATCH] arm64: dts: rockchip: Update eMMC, SD aliases for Radxa SoM - boards - -Radxa has produced Compute Modules like RK3399pro VMARC and CM3i with -onboarding eMMC flash, so the eMMC is the primary MMC device. - -On the other hand, Rockchip boot orders start from eMMC from an MMC -device perspective. - -Mark, the eMMC has mmc0 to satisfy the above two conditions. - -Reported-by: FUKAUMI Naoki <naoki@radxa.com> -Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> -Link: https://lore.kernel.org/r/20230118080454.11643-1-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 4 ++-- - arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 3 +-- - 2 files changed, 3 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -@@ -13,8 +13,8 @@ - compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; - - aliases { -- mmc0 = &sdmmc; -- mmc1 = &sdhci; -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; - }; - - vcc3v3_pcie: vcc-pcie-regulator { ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -8,8 +8,7 @@ - compatible = "radxa,e25", "rockchip,rk3568"; - - aliases { -- mmc0 = &sdmmc0; -- mmc1 = &sdhci; -+ mmc1 = &sdmmc0; - }; - - pwm-leds { diff --git a/target/linux/rockchip/patches-6.1/026-v6.3-arm64-dts-rockchip-Add-missing-CM3i.patch b/target/linux/rockchip/patches-6.1/026-v6.3-arm64-dts-rockchip-Add-missing-CM3i.patch deleted file mode 100644 index c1f1a09219..0000000000 --- a/target/linux/rockchip/patches-6.1/026-v6.3-arm64-dts-rockchip-Add-missing-CM3i.patch +++ /dev/null @@ -1,35 +0,0 @@ -From c4d2b02d63ee38b381fbc886c02eecfec4f981cc Mon Sep 17 00:00:00 2001 -From: Jagan Teki <jagan@amarulasolutions.com> -Date: Mon, 23 Jan 2023 12:46:51 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add missing CM3i fallback compatible - for Radxa E25 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -In order to function the Radxa E25 Carrier board, it is mandatory to -mount the Radxa CM3i module. - -Add Radxa CM3i compatible as fallback compatible to string to satisfy -the Module and Carrier board topology. - -Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25") -Cc: Chukun Pan <amadeus@jmu.edu.cn> -Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> -Link: https://lore.kernel.org/r/20230123071654.73139-2-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -5,7 +5,7 @@ - - / { - model = "Radxa E25"; -- compatible = "radxa,e25", "rockchip,rk3568"; -+ compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; - - aliases { - mmc1 = &sdmmc0; diff --git a/target/linux/rockchip/patches-6.1/027-v6.3-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-E25.patch b/target/linux/rockchip/patches-6.1/027-v6.3-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-E25.patch deleted file mode 100644 index 84e87bae05..0000000000 --- a/target/linux/rockchip/patches-6.1/027-v6.3-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-E25.patch +++ /dev/null @@ -1,28 +0,0 @@ -From ef9134d9bbce071c9e4ebdcbb6f8fb1a5dd0a67e Mon Sep 17 00:00:00 2001 -From: Jagan Teki <jagan@amarulasolutions.com> -Date: Mon, 23 Jan 2023 12:46:53 +0530 -Subject: [PATCH] arm64: dts: rockchip: Correct the model name for Radxa E25 - -Radxa E25 is a Carrier board, so update the model name for Radxa E25 -as suggested by the Radxa website. - -Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25") -Cc: Chukun Pan <amadeus@jmu.edu.cn> -Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> -Link: https://lore.kernel.org/r/20230123071654.73139-4-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -4,7 +4,7 @@ - #include "rk3568-radxa-cm3i.dtsi" - - / { -- model = "Radxa E25"; -+ model = "Radxa E25 Carrier Board"; - compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; - - aliases { diff --git a/target/linux/rockchip/patches-6.1/028-v6.6-arm64-dts-rockchip-Fix-PCIe-regulators-on-Radxa-E25.patch b/target/linux/rockchip/patches-6.1/028-v6.6-arm64-dts-rockchip-Fix-PCIe-regulators-on-Radxa-E25.patch deleted file mode 100644 index da02c4c001..0000000000 --- a/target/linux/rockchip/patches-6.1/028-v6.6-arm64-dts-rockchip-Fix-PCIe-regulators-on-Radxa-E25.patch +++ /dev/null @@ -1,79 +0,0 @@ -From a87852e37f782257ebc57cc44a0d3fbf806471f6 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Mon, 24 Jul 2023 14:52:16 +0000 -Subject: [PATCH] arm64: dts: rockchip: Fix PCIe regulators on Radxa E25 - -Despite its name, the regulator vcc3v3_pcie30x1 has nothing to do with -pcie30x1. Instead, it supply power to VBAT1-5 on the M.2 KEY B port as -seen on page 8 of the schematic [1]. - -pcie30x1 is used for the mini PCIe slot, and as seen on page 9 the -vcc3v3_minipcie regulator is instead related to pcie30x1. - -The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives. - -Use correct regulator vcc3v3_minipcie for pcie30x1. - -[1] https://dl.radxa.com/cm3p/e25/radxa-e25-v1.4-sch.pdf - -Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25") -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> -Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - .../arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -47,6 +47,9 @@ - vin-supply = <&vcc5v0_sys>; - }; - -+ /* actually fed by vcc5v0_sys, dependent -+ * on pi6c clock generator -+ */ - vcc3v3_minipcie: vcc3v3-minipcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -54,9 +57,9 @@ - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_enable_h>; - regulator-name = "vcc3v3_minipcie"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc5v0_sys>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_pi6c_05>; - }; - - vcc3v3_ngff: vcc3v3-ngff-regulator { -@@ -71,9 +74,6 @@ - vin-supply = <&vcc5v0_sys>; - }; - -- /* actually fed by vcc5v0_sys, dependent -- * on pi6c clock generator -- */ - vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -83,7 +83,7 @@ - regulator-name = "vcc3v3_pcie30x1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc3v3_pi6c_05>; -+ vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { -@@ -117,7 +117,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x1m0_pins>; - reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie30x1>; -+ vpcie3v3-supply = <&vcc3v3_minipcie>; - status = "okay"; - }; - diff --git a/target/linux/rockchip/patches-6.1/029-v6.6-arm64-dts-rockchip-Enable-SATA-on-Radxa-E25.patch b/target/linux/rockchip/patches-6.1/029-v6.6-arm64-dts-rockchip-Enable-SATA-on-Radxa-E25.patch deleted file mode 100644 index c0abdeb267..0000000000 --- a/target/linux/rockchip/patches-6.1/029-v6.6-arm64-dts-rockchip-Enable-SATA-on-Radxa-E25.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 2bdfe84fbd57a4ed9fd65a67210442559ce078f0 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Mon, 24 Jul 2023 14:52:16 +0000 -Subject: [PATCH] arm64: dts: rockchip: Enable SATA on Radxa E25 - -The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives. - -Enable sata1 node to fix use of SATA drives on the M.2 slot. - -Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25") -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> -Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -99,6 +99,10 @@ - }; - }; - -+&combphy1 { -+ phy-supply = <&vcc3v3_pcie30x1>; -+}; -+ - &pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie20_reset_h>; -@@ -178,6 +182,10 @@ - status = "okay"; - }; - -+&sata1 { -+ status = "okay"; -+}; -+ - &sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; diff --git a/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch deleted file mode 100644 index 9be609f661..0000000000 --- a/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001 -From: Tim Lunn <tim@feathertop.org> -Date: Wed, 14 Feb 2024 15:07:30 +1100 -Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board - -Adjust compatible string to match the board vendor of Sinovoip - -Signed-off-by: Tim Lunn <tim@feathertop.org> -Reviewed-by: Dragan Simic <dsimic@manjaro.org> -Acked-by: Conor Dooley <conor.dooley@microchip.com> -Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -13,7 +13,7 @@ - - / { - model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; -- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; -+ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; diff --git a/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch b/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch deleted file mode 100644 index 6a5622b813..0000000000 --- a/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch +++ /dev/null @@ -1,40 +0,0 @@ -From a2ac2a1b02590a22a236c43c455f421cdede45f5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com> -Date: Thu, 14 Mar 2024 15:24:35 +0300 -Subject: [PATCH] arm64: dts: rockchip: set PHY address of MT7531 switch to - 0x1f -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7531 switch listens on PHY address 0x1f on an MDIO bus. I've got two -findings that support this. There's no bootstrapping option to change the -PHY address of the switch. The Linux driver hardcodes 0x1f as the PHY -address of the switch. So the reg property on the device tree is currently -ignored by the Linux driver. - -Therefore, describe the correct PHY address on Banana Pi BPI-R2 Pro that -has this switch. - -Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> -Fixes: c1804463e5c6 ("arm64: dts: rockchip: Add mt7531 dsa node to BPI-R2-Pro board") -Link: https://lore.kernel.org/r/20240314-for-rockchip-mt7531-phy-address-v1-1-743b5873358f@arinc9.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -521,9 +521,9 @@ - #address-cells = <1>; - #size-cells = <0>; - -- switch@0 { -+ switch@1f { - compatible = "mediatek,mt7531"; -- reg = <0>; -+ reg = <0x1f>; - - ports { - #address-cells = <1>; diff --git a/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch b/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch deleted file mode 100644 index dca18f5c58..0000000000 --- a/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 433d54818f64a2fe0562f8c04c7a81f562368515 Mon Sep 17 00:00:00 2001 -From: Jose Ignacio Tornos Martinez <jtornosm@redhat.com> -Date: Tue, 5 Mar 2024 15:32:18 +0100 -Subject: [PATCH] arm64: dts: rockchip: regulator for sd needs to be always on - for BPI-R2Pro - -With default dts configuration for BPI-R2Pro, the regulator for sd card is -powered off when reboot is commanded, and the only solution to detect the -sd card again, and therefore, allow rebooting from there, is to do a -hardware reset. - -Configure the regulator for sd to be always on for BPI-R2Pro in order to -avoid this issue. - -Fixes: f901aaadaa2a ("arm64: dts: rockchip: Add Bananapi R2 Pro") -Signed-off-by: Jose Ignacio Tornos Martinez <jtornosm@redhat.com> -Link: https://lore.kernel.org/r/20240305143222.189413-1-jtornosm@redhat.com -Signed-off-by: Heiko Stuebner <heiko@sntech.de> ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -412,6 +412,8 @@ - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; -+ regulator-always-on; -+ regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - diff --git a/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch deleted file mode 100644 index 683e5347f7..0000000000 --- a/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 -From: David Bauer <mail@david-bauer.net> -Date: Fri, 10 Jul 2020 21:38:20 +0200 -Subject: [PATCH] rockchip: use system LED for OpenWrt - -Use the SYS LED on the casing for showing system status. - -This patch is kept separate from the NanoPi R2S support patch, as i plan -on submitting the device support upstream. - -Signed-off-by: David Bauer <mail@david-bauer.net> ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -6,6 +6,7 @@ - /dts-v1/; - - #include <dt-bindings/input/input.h> -+#include <dt-bindings/leds/common.h> - #include <dt-bindings/gpio/gpio.h> - #include "rk3328.dtsi" - -@@ -16,6 +17,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; - }; - - chosen { -@@ -48,19 +54,22 @@ - pinctrl-names = "default"; - - lan_led: led-0 { -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_LAN; - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:lan"; - }; - - sys_led: led-1 { -+ color = <LED_COLOR_ID_RED>; -+ function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:red:sys"; - default-state = "on"; - }; - - wan_led: led-2 { -+ color = <LED_COLOR_ID_GREEN>; -+ function = LED_FUNCTION_WAN; - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:wan"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -13,6 +13,11 @@ - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen { diff --git a/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch deleted file mode 100644 index eeef0df014..0000000000 --- a/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 -From: David Bauer <mail@david-bauer.net> -Date: Sun, 26 Jul 2020 13:32:59 +0200 -Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S - -This adds the OF node for the USB3 ethernet adapter on the FriendlyARM -NanoPi R2S. Add the correct value for the RTL8153 LED configuration -register to match the blink behavior of the other port on the device. - -Signed-off-by: David Bauer <mail@david-bauer.net> ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ - 1 file changed, 1 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -406,6 +406,7 @@ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; - }; - }; - diff --git a/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch deleted file mode 100644 index b3c941821a..0000000000 --- a/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch +++ /dev/null @@ -1,36 +0,0 @@ -From: David Bauer <mail@david-bauer.net> -Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S - -The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting -while U-Boot requires the card to be in 3.3V mode. - -Remove UHS support from the SD controller so the card remains in 3.3V -mode. This reduces transfer speeds but ensures a reboot whether from -userspace or following a kernel panic is always working. - -Signed-off-by: David Bauer <mail@david-bauer.net> - ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -335,7 +335,6 @@ - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; -- sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -112,6 +112,11 @@ - status = "disabled"; - }; - -+&sdmmc { -+ /delete-property/ sd-uhs-sdr104; -+ cap-sd-highspeed; -+}; -+ - &u2phy0_host { - phy-supply = <&vdd_5v>; - }; diff --git a/target/linux/rockchip/patches-6.1/106-r4s-openwrt-leds.patch b/target/linux/rockchip/patches-6.1/106-r4s-openwrt-leds.patch deleted file mode 100644 index d7579d61e9..0000000000 --- a/target/linux/rockchip/patches-6.1/106-r4s-openwrt-leds.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -19,6 +19,13 @@ - model = "FriendlyElec NanoPi R4S"; - compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ - /delete-node/ display-subsystem; - - gpio-leds { diff --git a/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch deleted file mode 100644 index 3aff37d096..0000000000 --- a/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch +++ /dev/null @@ -1,40 +0,0 @@ -From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Fri, 19 May 2023 12:10:52 +0800 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1 - Plus - -Add OpenWrt's LED aliases for showing system status. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> ---- - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -17,6 +17,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -41,11 +46,10 @@ - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - }; - -- led-1 { -+ status_led: led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - - led-2 { diff --git a/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch deleted file mode 100644 index af8f8b16ba..0000000000 --- a/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Fri, 19 May 2023 12:38:04 +0800 -Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1 - Plus - -Add the correct value for the RTL8153 LED configuration register to -match the blink behavior of the other port on the device. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> ---- - arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -365,6 +365,7 @@ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; - }; - }; - diff --git a/target/linux/rockchip/patches-6.1/109-nanopc-t4-add-led-aliases.patch b/target/linux/rockchip/patches-6.1/109-nanopc-t4-add-led-aliases.patch deleted file mode 100644 index 1a80dadd48..0000000000 --- a/target/linux/rockchip/patches-6.1/109-nanopc-t4-add-led-aliases.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -@@ -15,6 +15,13 @@ - model = "FriendlyElec NanoPC-T4"; - compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; -+ }; -+ - vcc12v0_sys: vcc12v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; diff --git a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch deleted file mode 100644 index c22fdd52b8..0000000000 --- a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Tianling Shen <cnsztl@gmail.com> -Date: Tue Jun 20 16:45:27 2023 +0800 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5 - series - -Add OpenWrt's LED aliases for showing system status. - -Signed-off-by: Tianling Shen <cnsztl@gmail.com> ---- - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -@@ -40,7 +40,6 @@ - power_led: led-power { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_POWER; -- linux,default-trigger = "heartbeat"; - gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -@@ -39,7 +39,6 @@ - power_led: led-power { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_POWER; -- linux,default-trigger = "heartbeat"; - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -@@ -18,6 +18,11 @@ - aliases { - mmc0 = &sdmmc0; - mmc1 = &sdhci; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen: chosen { diff --git a/target/linux/rockchip/patches-6.1/111-radxa-cm3-io-add-led-aliases.patch b/target/linux/rockchip/patches-6.1/111-radxa-cm3-io-add-led-aliases.patch deleted file mode 100644 index c8183a2b8a..0000000000 --- a/target/linux/rockchip/patches-6.1/111-radxa-cm3-io-add-led-aliases.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marius Durbaca <mariusd84@gmail.com> -Date: Tue Feb 20 15:05:27 2024 +0200 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa -CM3 IO board - -Add OpenWrt's LED aliases for showing system status. - -Suggested-by: Tianling Shen <cnsztl@immortalwrt.org> -Signed-off-by: Marius Durbaca <mariusd84@gmail.com> ---- - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -16,6 +16,10 @@ - aliases { - ethernet0 = &gmac1; - mmc1 = &sdmmc0; -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen: chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -@@ -17,7 +17,7 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ status_led: led-0 { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; diff --git a/target/linux/rockchip/patches-6.1/112-radxa-e25-add-led-aliases.patch b/target/linux/rockchip/patches-6.1/112-radxa-e25-add-led-aliases.patch deleted file mode 100644 index 75038c7f39..0000000000 --- a/target/linux/rockchip/patches-6.1/112-radxa-e25-add-led-aliases.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marius Durbaca <mariusd84@gmail.com> -Date: Tue Feb 27 16:25:27 2024 +0200 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa -E25 - -Add OpenWrt's LED aliases for showing system status. - -Signed-off-by: Marius Durbaca <mariusd84@gmail.com> ---- - ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -9,6 +9,10 @@ - - aliases { - mmc1 = &sdmmc0; -+ led-boot = &led_user; -+ led-failsafe = &led_user; -+ led-running = &led_user; -+ led-upgrade = &led_user; - }; - - pwm-leds { diff --git a/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch b/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch deleted file mode 100644 index 6a2d35889b..0000000000 --- a/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch +++ /dev/null @@ -1,339 +0,0 @@ -From patchwork Sat Nov 12 14:10:58 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Aurelien Jarno <aurelien@aurel32.net> -X-Patchwork-Id: 13041222 -Return-Path: - <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org> -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -From: Aurelien Jarno <aurelien@aurel32.net> -To: Olivia Mackall <olivia@selenic.com>, - Herbert Xu <herbert@gondor.apana.org.au>, - Rob Herring <robh+dt@kernel.org>, - Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, - Heiko Stuebner <heiko@sntech.de>, - Philipp Zabel <p.zabel@pengutronix.de>, - Lin Jinhan <troy.lin@rock-chips.com> -Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR - CORE), - devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE - BINDINGS), - linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC - support), - linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), - linux-kernel@vger.kernel.org (open list), - Aurelien Jarno <aurelien@aurel32.net> -Subject: [PATCH v1 2/3] hwrng: add Rockchip SoC hwrng driver -Date: Sat, 12 Nov 2022 15:10:58 +0100 -Message-Id: <20221112141059.3802506-3-aurelien@aurel32.net> -In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> -References: <20221112141059.3802506-1-aurelien@aurel32.net> -MIME-Version: 1.0 -List-Id: <linux-arm-kernel.lists.infradead.org> - -Rockchip SoCs used to have a random number generator as part of their -crypto device, and support for it has to be added to the corresponding -driver. However newer Rockchip SoCs like the RK356x have an independent -True Random Number Generator device. This patch adds a driver for it, -greatly inspired from the downstream driver. - -The TRNG device does not seem to have a signal conditionner and the FIPS -140-2 test returns a lot of failures. They can be reduced by increasing -RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value -has been adjusted to get ~90% of successes and the quality value has -been set accordingly. - -Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> ---- - drivers/char/hw_random/Kconfig | 14 ++ - drivers/char/hw_random/Makefile | 1 + - drivers/char/hw_random/rockchip-rng.c | 251 ++++++++++++++++++++++++++ - 3 files changed, 266 insertions(+) - create mode 100644 drivers/char/hw_random/rockchip-rng.c - ---- a/drivers/char/hw_random/Kconfig -+++ b/drivers/char/hw_random/Kconfig -@@ -549,6 +549,20 @@ config HW_RANDOM_CN10K - To compile this driver as a module, choose M here. - The module will be called cn10k_rng. If unsure, say Y. - -+config HW_RANDOM_ROCKCHIP -+ tristate "Rockchip True Random Number Generator" -+ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST) -+ depends on HAS_IOMEM -+ default HW_RANDOM -+ help -+ This driver provides kernel-side support for the True Random Number -+ Generator hardware found on some Rockchip SoC like RK3566 or RK3568. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called rockchip-rng. -+ -+ If unsure, say Y. -+ - endif # HW_RANDOM - - config UML_RANDOM ---- a/drivers/char/hw_random/Makefile -+++ b/drivers/char/hw_random/Makefile -@@ -47,3 +47,4 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe - obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o - obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o - obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o -+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o ---- /dev/null -+++ b/drivers/char/hw_random/rockchip-rng.c -@@ -0,0 +1,251 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs -+ * -+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2022, Aurelien Jarno -+ * Authors: -+ * Lin Jinhan <troy.lin@rock-chips.com> -+ * Aurelien Jarno <aurelien@aurel32.net> -+ */ -+#include <linux/clk.h> -+#include <linux/hw_random.h> -+#include <linux/io.h> -+#include <linux/iopoll.h> -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/of_platform.h> -+#include <linux/pm_runtime.h> -+#include <linux/reset.h> -+#include <linux/slab.h> -+ -+#define RK_RNG_AUTOSUSPEND_DELAY 100 -+#define RK_RNG_MAX_BYTE 32 -+#define RK_RNG_POLL_PERIOD_US 100 -+#define RK_RNG_POLL_TIMEOUT_US 10000 -+ -+/* -+ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is -+ * a tradeoff between speed and quality and has been adjusted to get a quality -+ * of ~900 (~90% of FIPS 140-2 successes). -+ */ -+#define RK_RNG_SAMPLE_CNT 1000 -+ -+/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */ -+#define TRNG_RST_CTL 0x0004 -+#define TRNG_RNG_CTL 0x0400 -+#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4) -+#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4) -+#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4) -+#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4) -+#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2) -+#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2) -+#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2) -+#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2) -+#define TRNG_RNG_CTL_ENABLE BIT(1) -+#define TRNG_RNG_CTL_START BIT(0) -+#define TRNG_RNG_SAMPLE_CNT 0x0404 -+#define TRNG_RNG_DOUT_0 0x0410 -+#define TRNG_RNG_DOUT_1 0x0414 -+#define TRNG_RNG_DOUT_2 0x0418 -+#define TRNG_RNG_DOUT_3 0x041c -+#define TRNG_RNG_DOUT_4 0x0420 -+#define TRNG_RNG_DOUT_5 0x0424 -+#define TRNG_RNG_DOUT_6 0x0428 -+#define TRNG_RNG_DOUT_7 0x042c -+ -+struct rk_rng { -+ struct hwrng rng; -+ void __iomem *base; -+ struct reset_control *rst; -+ int clk_num; -+ struct clk_bulk_data *clk_bulks; -+}; -+ -+/* The mask determine the bits that are updated */ -+static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask) -+{ -+ writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL); -+} -+ -+static int rk_rng_init(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg; -+ int ret; -+ -+ /* start clocks */ -+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); -+ if (ret < 0) { -+ dev_err((struct device *) rk_rng->rng.priv, -+ "Failed to enable clks %d\n", ret); -+ return ret; -+ } -+ -+ /* set the sample period */ -+ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); -+ -+ /* set osc ring speed and enable it */ -+ reg = TRNG_RNG_CTL_LEN_256_BIT | -+ TRNG_RNG_CTL_OSC_RING_SPEED_0 | -+ TRNG_RNG_CTL_ENABLE; -+ rk_rng_write_ctl(rk_rng, reg, 0xffff); -+ -+ return 0; -+} -+ -+static void rk_rng_cleanup(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg; -+ -+ /* stop TRNG */ -+ reg = 0; -+ rk_rng_write_ctl(rk_rng, reg, 0xffff); -+ -+ /* stop clocks */ -+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); -+} -+ -+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg; -+ int ret = 0; -+ int i; -+ -+ pm_runtime_get_sync((struct device *) rk_rng->rng.priv); -+ -+ /* Start collecting random data */ -+ reg = TRNG_RNG_CTL_START; -+ rk_rng_write_ctl(rk_rng, reg, reg); -+ -+ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg, -+ !(reg & TRNG_RNG_CTL_START), -+ RK_RNG_POLL_PERIOD_US, -+ RK_RNG_POLL_TIMEOUT_US); -+ if (ret < 0) -+ goto out; -+ -+ /* Read random data stored in big endian in the registers */ -+ ret = min_t(size_t, max, RK_RNG_MAX_BYTE); -+ for (i = 0; i < ret; i += 4) { -+ reg = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i); -+ *(u32 *)(buf + i) = be32_to_cpu(reg); -+ } -+ -+out: -+ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); -+ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); -+ -+ return ret; -+} -+ -+static int rk_rng_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct rk_rng *rk_rng; -+ int ret; -+ -+ rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL); -+ if (!rk_rng) -+ return -ENOMEM; -+ -+ rk_rng->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(rk_rng->base)) -+ return PTR_ERR(rk_rng->base); -+ -+ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks); -+ if (rk_rng->clk_num < 0) -+ return dev_err_probe(dev, rk_rng->clk_num, -+ "Failed to get clks property\n"); -+ -+ rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false); -+ if (IS_ERR(rk_rng->rst)) -+ return dev_err_probe(dev, PTR_ERR(rk_rng->rst), -+ "Failed to get reset property\n"); -+ -+ reset_control_assert(rk_rng->rst); -+ udelay(2); -+ reset_control_deassert(rk_rng->rst); -+ -+ platform_set_drvdata(pdev, rk_rng); -+ -+ rk_rng->rng.name = dev_driver_string(dev); -+#ifndef CONFIG_PM -+ rk_rng->rng.init = rk_rng_init; -+ rk_rng->rng.cleanup = rk_rng_cleanup; -+#endif -+ rk_rng->rng.read = rk_rng_read; -+ rk_rng->rng.priv = (unsigned long) dev; -+ rk_rng->rng.quality = 900; -+ -+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); -+ pm_runtime_use_autosuspend(dev); -+ pm_runtime_enable(dev); -+ -+ ret = devm_hwrng_register(dev, &rk_rng->rng); -+ if (ret) -+ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); -+ -+ dev_info(&pdev->dev, "Registered Rockchip hwrng\n"); -+ -+ return 0; -+} -+ -+static int rk_rng_remove(struct platform_device *pdev) -+{ -+ pm_runtime_disable(&pdev->dev); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int rk_rng_runtime_suspend(struct device *dev) -+{ -+ struct rk_rng *rk_rng = dev_get_drvdata(dev); -+ -+ rk_rng_cleanup(&rk_rng->rng); -+ -+ return 0; -+} -+ -+static int rk_rng_runtime_resume(struct device *dev) -+{ -+ struct rk_rng *rk_rng = dev_get_drvdata(dev); -+ -+ return rk_rng_init(&rk_rng->rng); -+} -+#endif -+ -+static const struct dev_pm_ops rk_rng_pm_ops = { -+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, -+ rk_rng_runtime_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+}; -+ -+static const struct of_device_id rk_rng_dt_match[] = { -+ { -+ .compatible = "rockchip,rk3568-rng", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, rk_rng_dt_match); -+ -+static struct platform_driver rk_rng_driver = { -+ .driver = { -+ .name = "rockchip-rng", -+ .pm = &rk_rng_pm_ops, -+ .of_match_table = rk_rng_dt_match, -+ }, -+ .probe = rk_rng_probe, -+ .remove = rk_rng_remove, -+}; -+ -+module_platform_driver(rk_rng_driver); -+ -+MODULE_DESCRIPTION("Rockchip True Random Number Generator driver"); -+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>, Aurelien Jarno <aurelien@aurel32.net>"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch b/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch deleted file mode 100644 index bb34ba76e0..0000000000 --- a/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch +++ /dev/null @@ -1,56 +0,0 @@ -From patchwork Sat Nov 12 14:10:59 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Aurelien Jarno <aurelien@aurel32.net> -X-Patchwork-Id: 13041221 -From: Aurelien Jarno <aurelien@aurel32.net> -To: Olivia Mackall <olivia@selenic.com>, - Herbert Xu <herbert@gondor.apana.org.au>, - Rob Herring <robh+dt@kernel.org>, - Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, - Heiko Stuebner <heiko@sntech.de>, - Philipp Zabel <p.zabel@pengutronix.de>, - Lin Jinhan <troy.lin@rock-chips.com> -Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR - CORE), - devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE - BINDINGS), - linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC - support), - linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), - linux-kernel@vger.kernel.org (open list), - Aurelien Jarno <aurelien@aurel32.net> -Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x -Date: Sat, 12 Nov 2022 15:10:59 +0100 -Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net> -In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> -References: <20221112141059.3802506-1-aurelien@aurel32.net> -MIME-Version: 1.0 -List-Id: <linux-arm-kernel.lists.infradead.org> - -Enable the just added Rockchip RNG driver for RK356x SoCs. - -Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -1773,6 +1773,15 @@ - }; - }; - -+ rng: rng@fe388000 { -+ compatible = "rockchip,rk3568-rng"; -+ reg = <0x0 0xfe388000 0x0 0x4000>; -+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; -+ clock-names = "trng_clk", "trng_hclk"; -+ resets = <&cru SRST_TRNG_NS>; -+ reset-names = "reset"; -+ }; -+ - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; |