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| author | INAGAKI Hiroshi <musashino.open@gmail.com> | 2024-03-04 19:08:07 +0900 |
|---|---|---|
| committer | Christian Lamparter <chunkeey@gmail.com> | 2024-03-08 17:35:01 +0100 |
| commit | 35ae18fc061eda057ce531e516f9623ff8d94210 (patch) | |
| tree | 2df1c28a1a772907cb209f773b370cd931b50788 /target/linux/ath79 | |
| parent | e0ee4195fc7b1a119cfb02bf292a9410af3b9fe4 (diff) | |
| download | openwrt-35ae18fc061eda057ce531e516f9623ff8d94210.tar.gz openwrt-35ae18fc061eda057ce531e516f9623ff8d94210.tar.bz2 openwrt-35ae18fc061eda057ce531e516f9623ff8d94210.zip | |
ath79: add HighSpeed UART (uart1) support for QCA955x
Add HighSpeed UART support to QCA955x series SoCs as a secondary UART
(uart1). This UART is compatible with qca,ar9330-uart.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Diffstat (limited to 'target/linux/ath79')
| -rw-r--r-- | target/linux/ath79/dts/qca955x.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/qca955x.dtsi b/target/linux/ath79/dts/qca955x.dtsi index 13fbd03ccb..c12a266cda 100644 --- a/target/linux/ath79/dts/qca955x.dtsi +++ b/target/linux/ath79/dts/qca955x.dtsi @@ -178,6 +178,18 @@ #reset-cells = <1>; }; + + uart1: uart@18500000 { + compatible = "qca,ar9330-uart"; + reg = <0x18500000 0x14>; + + interrupts = <6>; + + clocks = <&pll ATH79_CLK_REF>; + clock-names = "uart"; + + status = "disabled"; + }; }; gmac: gmac@18070000 { |